diff options
| author | Shaohua Li <shaohua.li@intel.com> | 2007-08-17 13:43:50 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-08-17 13:43:50 -0700 |
| commit | b09e789c438c406bd9bcaac6f1c940a75007e59f (patch) | |
| tree | 2e753d921e182653acf7badb1c6ebc0761047d7f /arch/ia64 | |
| parent | e8c59c0cf9c91dccfb6367c306d753500d5a0150 (diff) | |
[IA64] forbid ptrace changes psr.ri to 3
The "ri" field in the processor status register only has defined
values of 0, 1, 2. Do not let ptrace set this to 3. As with
other reserved fields in registers we silently discard the value.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
| -rw-r--r-- | arch/ia64/kernel/ptrace.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c index 00f803246948..122444a97897 100644 --- a/arch/ia64/kernel/ptrace.c +++ b/arch/ia64/kernel/ptrace.c @@ -951,10 +951,14 @@ access_uarea (struct task_struct *child, unsigned long addr, return 0; case PT_CR_IPSR: - if (write_access) - pt->cr_ipsr = ((*data & IPSR_MASK) + if (write_access) { + unsigned long tmp = *data; + /* psr.ri==3 is a reserved value: SDM 2:25 */ + if ((tmp & IA64_PSR_RI) == IA64_PSR_RI) + tmp &= ~IA64_PSR_RI; + pt->cr_ipsr = ((tmp & IPSR_MASK) | (pt->cr_ipsr & ~IPSR_MASK)); - else + } else *data = (pt->cr_ipsr & IPSR_MASK); return 0; |