Support 512mb RAM configuration for Momenco Ocelot. Patch from

David Woodhouse (dwmw2@infradead.org).

12 files changed, 468 insertions, 38 deletions

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 02dfccd33..d87b276b1 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -198,7 +198,9 @@ endif
 # Momentum Ocelot board
 #
 ifdef CONFIG_MOMENCO_OCELOT
-LIBS          += arch/mips/gt64120/common/gt64120.o arch/mips/gt64120/momenco_ocelot/momenco_ocelot.o
+# The Ocelot setup.o must be linked early - it does the ioremap() for the
+# mips_io_port_base.
+CORE_FILES    += arch/mips/gt64120/common/gt64120.o arch/mips/gt64120/momenco_ocelot/momenco_ocelot.o
 SUBDIRS       += arch/mips/gt64120/common arch/mips/gt64120/momenco_ocelot
 LOADADDR      += 0x80100000
 endif
diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c
index e74b86bd6..dc50b1b3c 100644
--- a/arch/mips/gt64120/common/pci.c
+++ b/arch/mips/gt64120/common/pci.c
@@ -1113,15 +1113,15 @@ void __init pcibios_init(void)
 	pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
 
 	/*  This scans the PCI bus and sets up initial values.  */
-	// scan_and_initialize_pci();
+	scan_and_initialize_pci();
 
 	/*
 	 *  Reset PCI I/O and PCI MEM values to ones supported by EVM.
 	 */
-	ioport_resource.start = 0x10000000;
-	ioport_resource.end   = 0x11ffffff;	/*  32 MB */
-	iomem_resource.start  = 0x12000000;
-	iomem_resource.end    = 0x13ffffff;	/* 32 MB */
+	ioport_resource.start = GT_PCI_IO_BASE;
+	ioport_resource.end   = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
+	iomem_resource.start  = GT_PCI_MEM_BASE;
+	iomem_resource.end    = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
 
 	pci_scan_bus(0, &galileo_pci_ops, NULL);
 }
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
new file mode 100644
index 000000000..e840ed42f
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
@@ -0,0 +1,34 @@
+/*
+ * $Id$
+ *
+ * Ocelot Board Register Definitions
+ *
+ * (C) 2001 Red Hat, Inc.
+ *
+ * GPL'd
+ *
+ */
+
+#ifndef __MOMENCO_OCELOT_PLD_H__
+#define __MOMENCO_OCELOT_PLD_H__
+
+#define OCELOT_CS0_ADDR (0xe0020000)
+
+#define OCELOT_REG_BOARDREV (0)
+#define OCELOT_REG_PLD1_ID (1)
+#define OCELOT_REG_PLD2_ID (2)
+#define OCELOT_REG_RESET_STATUS (3)
+#define OCELOT_REG_BOARD_STATUS (4)
+#define OCELOT_REG_CPCI_ID (5)
+#define OCELOT_REG_I2C_CTRL (8)
+#define OCELOT_REG_EEPROM_MODE (9)
+#define OCELOT_REG_INTMASK (10)
+#define OCELOT_REG_INTSTATUS (11)
+#define OCELOT_REG_INTSET (12)
+#define OCELOT_REG_INTCLR (13)
+
+#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
+#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
+
+
+#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c
index 6dfadf1fe..73a4a1133 100644
--- a/arch/mips/gt64120/momenco_ocelot/prom.c
+++ b/arch/mips/gt64120/momenco_ocelot/prom.c
@@ -36,8 +36,9 @@ void __init prom_init(int argc, const char **arg)
 	mips_machgroup = MACH_GROUP_MOMENCO;
 	mips_machtype = MACH_MOMENCO_OCELOT;
 
-	/* 128MB - we should detect this through ocelot board status register */
-	add_memory_region(0, 128 << 20, BOOT_MEM_RAM);
+	/* All the boards have at least 64MiB. If there's more, we
+	   detect and register it later */
+	add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 0ffc8c317..f08f32074 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -6,6 +6,8 @@
  *
  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
  * Copyright (C) 2000 RidgeRun, Inc.
+ * Copyright (C) 2001 Red Hat, Inc.
+ *
  * Author: RidgeRun, Inc.
  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  *
@@ -43,6 +45,8 @@
 #include <linux/interrupt.h>
 #include <linux/pci.h>
 #include <linux/timex.h>
+#include <linux/vmalloc.h>
+#include <asm/time.h>
 #include <asm/bootinfo.h>
 #include <asm/page.h>
 #include <asm/bootinfo.h>
@@ -57,10 +61,13 @@
 #include <linux/bootmem.h>
 #include <linux/blk.h>
 #include <asm/gt64120/gt64120.h>
+#include "ocelot_pld.h"
 
 extern struct rtc_ops no_rtc_ops;
 struct rtc_ops *rtc_ops;
 
+unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
+
 /* These functions are used for rebooting or halting the machine*/
 extern void momenco_ocelot_restart(char *command);
 extern void momenco_ocelot_halt(void);
@@ -68,20 +75,22 @@ extern void momenco_ocelot_power_off(void);
 
 char arcs_cmdline[COMMAND_LINE_SIZE]= { ""/*console=ttyS0,9600"*/ };
 
-void (*board_time_init) (struct irqaction * irq);
-
 extern void gt64120_time_init(void);
 extern void momenco_ocelot_irq_setup(void);
 
-void momenco_ocelot_setup(void)
-{
-	unsigned int i, j;
+static char reset_reason;
+
+#define ENTRYLO(x) ((pte_val(mk_pte_phys((x), PAGE_KERNEL_UNCACHED)) >> 6)|1)
+
+static void __init setup_l3cache(unsigned long size);
 
+void __init momenco_ocelot_setup(void)
+{
+	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
+	unsigned int tmpword;
 	irq_setup = momenco_ocelot_irq_setup;
 	board_time_init = gt64120_time_init;
 
-	mips_io_port_base = KSEG1;
-
 	_machine_restart = momenco_ocelot_restart;
 	_machine_halt = momenco_ocelot_halt;
 	_machine_power_off = momenco_ocelot_power_off;
@@ -92,4 +101,184 @@ void momenco_ocelot_setup(void)
 	 * initrd_below_start_ok = 1;
 	 */
 	rtc_ops = &no_rtc_ops;
+
+
+	/* A wired TLB entry for the GT64120A and the serial port. The
+	   GT64120A is going to be hit on every IRQ anyway - there's
+	   absolutely no point in letting it be a random TLB entry, as
+	   it'll just cause needless churning of the TLB. And we use
+	   the other half for the serial port, which is just a PITA
+	   otherwise :)
+
+		Device			Physical	Virtual
+		GT64120 Internal Regs	0x24000000	0xe0000000
+		UARTs (CS2)		0x2d000000	0xe0001000
+	*/
+	add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
+
+	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
+	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
+	   appears to be one of the variants of ST M48T35 - see 
+	   http://www.st.com/stonline/bin/sftab.exe?table=172&filter0=M48T35
+
+		Ocelot PLD (CS0)	0x2c000000	0xe0020000
+		NVRAM			0x2c800000	0xe0030000
+	*/
+		
+	add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
+
+
+	/* Relocate the CS3/BootCS region */
+  	GT_WRITE( GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
+
+	/* Relocate CS[012] */
+ 	GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
+
+	/* Relocate the GT64120A itself... */
+	GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
+	mb();
+	gt64120_base = 0xe0000000;
+
+	/* ...and the PCI0 view of it. */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
+	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
+	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
+	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
+
+	/* Relocate PCI0 I/O and Mem0 */
+	GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
+	GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
+
+	/* Relocate PCI0 Mem1 */
+	GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
+
+	/* Relocate all the PCI1 stuff, not that we use it */
+	GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
+	GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
+	GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
+
+	/* Relocate the CPU's view of the RAM... */
+	GT_WRITE(GT_SCS10LD_OFS, 0);
+	GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
+	GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
+	GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
+
+	GT_WRITE(GT_SCS1LD_OFS, 0xff);
+	GT_WRITE(GT_SCS1HD_OFS, 0x00);
+	GT_WRITE(GT_SCS0LD_OFS, 0);
+	GT_WRITE(GT_SCS0HD_OFS, 0xff);
+	GT_WRITE(GT_SCS3LD_OFS, 0xff);
+	GT_WRITE(GT_SCS3HD_OFS, 0x00);
+	GT_WRITE(GT_SCS2LD_OFS, 0);
+	GT_WRITE(GT_SCS2HD_OFS, 0xff);
+
+	/* ...and the PCI0 view of it. */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
+	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
+	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
+	GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
+	GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
+
+	tmpword = OCELOT_PLD_READ(BOARDREV);
+	if (tmpword < 26)
+		printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
+	else
+		printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
+
+	tmpword = OCELOT_PLD_READ(PLD1_ID);
+	printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
+	tmpword = OCELOT_PLD_READ(PLD2_ID);
+	printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
+	tmpword = OCELOT_PLD_READ(RESET_STATUS);
+	printk("Reset reason: 0x%x\n", tmpword);
+	reset_reason = tmpword;
+	OCELOT_PLD_WRITE(0xff, RESET_STATUS);
+
+	tmpword = OCELOT_PLD_READ(BOARD_STATUS);
+	printk("Board Status register: 0x%02x\n", tmpword);
+	printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
+	printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
+	printk("  - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
+	printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
+	printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
+
+	if (tmpword&12)
+		l3func((1<<(((tmpword&12) >> 2)+20)));
+
+	switch(tmpword &3) {
+	case 3:
+		/* 512MiB */
+		add_memory_region(256<<20, 256<<20, BOOT_MEM_RAM);
+	case 2:
+		/* 256MiB */
+		/* FIXME: Is it actually here, or at 0x10000000? */
+		add_memory_region(128<<20, 128<<20, BOOT_MEM_RAM);
+	case 1:
+		/* 128MiB */
+		add_memory_region(64<<20, 64<<20, BOOT_MEM_RAM);
+	case 0:
+		/* 64MiB */
+		;
+	}
+
+	/* Fix up the DiskOnChip mapping */
+	GT_WRITE(0x468, 0xfef73);
 }
+
+extern int rm7k_tcache_enabled;
+/*
+ * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
+ */
+#define Page_Invalidate_T 0x16
+static void __init setup_l3cache(unsigned long size)
+{
+	int register i;
+	unsigned long tmp;
+	
+	printk("Enabling L3 cache...");
+
+	/* Enable the L3 cache in the GT64120A's CPU Configuration register */
+	GT_READ(0, &tmp);
+	GT_WRITE(0, tmp | (1<<14));
+
+	/* Enable the L3 cache in the CPU */
+	set_cp0_config(1<<12 /* CONF_TE */);
+
+	/* Clear the cache */
+	set_taglo(0);
+	set_taghi(0);
+
+	for (i=0; i < size; i+= 4096) {
+		__asm__ __volatile__ (
+			".set noreorder\n\t"
+			".set mips3\n\t"
+			"cache %1, (%0)\n\t"
+			".set mips0\n\t"
+			".set reorder"
+			:
+			: "r" (KSEG0ADDR(i)),
+			  "i" (Page_Invalidate_T));
+	}
+
+	/* Let the RM7000 MM code know that the tertiary cache is enabled */
+	rm7k_tcache_enabled = 1;
+
+	printk("Done\n");
+}
+
+
+/* This needs to be one of the first initcalls, because no I/O port access
+   can work before this */
+
+static int io_base_ioremap(void)
+{
+	void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
+	if (!io_remap_range) {
+		panic("Could not ioremap I/O port range\n");
+	}
+	mips_io_port_base = io_remap_range - GT_PCI_IO_BASE;
+	return 0;
+}
+module_init(io_base_ioremap);
+
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ecb0fcde1..dfed66171 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -771,7 +771,27 @@ void cache_parity_error(void)
 	printk("Cache error exception:\n");
 	printk("cp0_errorepc == %08x\n", reg_val);
 	reg_val = read_32bit_cp0_register(CP0_CACHEERR);
-	printk("c0_cacheerr == %08x\n", reg_val);
+	printk("cp0_cacheerr == %08x\n", reg_val);
+
+	printk("Decoded CP0_CACHEERR: %s cache fault in %s reference.\n",
+	       reg_val&(1<<30)?"secondary":"primary",
+	       reg_val&(1<<31)?"data":"insn");
+	printk("Error bits: %s%s%s%s%s%s%s\n",
+	       reg_val&(1<<29)?"ED ":"",
+	       reg_val&(1<<28)?"ET ":"",
+	       reg_val&(1<<26)?"EE ":"",
+	       reg_val&(1<<25)?"EB ":"",
+	       reg_val&(1<<24)?"EI ":"",
+	       reg_val&(1<<23)?"E1 ":"",
+	       reg_val&(1<<22)?"E0 ":"");
+	printk("IDX: 0x%08x\n", reg_val&((1<<22)-1));
+
+	if (reg_val&(1<<22))
+		printk("DErrAddr0: 0x%08x\n", read_32bit_cp0_set1_register(CP0_S1_DERRADDR0));
+
+	if (reg_val&(1<<23))
+		printk("DErrAddr1: 0x%08x\n", read_32bit_cp0_set1_register(CP0_S1_DERRADDR1));
+
 
 	panic("Can't handle the cache error - panic!");
 }
diff --git a/arch/mips/mm/rm7k.c b/arch/mips/mm/rm7k.c
index 9659ac477..f18c0ef08 100644
--- a/arch/mips/mm/rm7k.c
+++ b/arch/mips/mm/rm7k.c
@@ -37,13 +37,34 @@ static int icache_size, dcache_size; /* Size in bytes */
 #define ic_lsize	32		/* Fixed to 32 byte on RM7000  */
 #define dc_lsize	32		/* Fixed to 32 byte on RM7000  */
 #define sc_lsize	32		/* Fixed to 32 byte on RM7000  */
+#define tc_pagesize	(32*128)
 
 /* Secondary cache parameters. */
-#define scache_size	(256*1024)	/* Fixed to 256kb on RM7000 */
+#define scache_size	(256*1024)	/* Fixed to 256KiB on RM7000 */
 
 #include <asm/cacheops.h>
 #include <asm/r4kcache.h>
 
+int rm7k_tcache_enabled = 0;
+
+/*
+ * Not added to asm/r4kcache.h because it seems to be RM7000-specific.
+ */
+#define Page_Invalidate_T 0x16
+
+static inline void invalidate_tcache_page(unsigned long addr)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"cache %1, (%0)\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		:
+		: "r" (addr),
+		  "i" (Page_Invalidate_T));
+}
+
 /*
  * Zero an entire page.  Note that while the RM7000 has a second level cache
  * it doesn't have a Create_Dirty_Excl_SD operation.
@@ -202,37 +223,53 @@ rm7k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 {
 	unsigned long end, a;
 
-	if (size >= scache_size) {
-		blast_dcache32();
-		return;
-	}
-
 	a = addr & ~(sc_lsize - 1);
 	end = (addr + size) & ~(sc_lsize - 1);
 	while (1) {
+		flush_dcache_line(a);	/* Hit_Writeback_Inv_D */
+		flush_icache_line(a);	/* Hit_Invalidate_I */
 		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
 		if (a == end) break;
 		a += sc_lsize;
 	}
-}
 
+	if (!rm7k_tcache_enabled) 
+		return;
+
+	a = addr & ~(tc_pagesize - 1);
+	end = (addr + size) & ~(tc_pagesize - 1);
+	while(1) {
+		invalidate_tcache_page(a);	/* Page_Invalidate_T */
+		if (a == end) break;
+		a += tc_pagesize;
+	}
+}
+	       
 static void
 rm7k_dma_cache_inv(unsigned long addr, unsigned long size)
 {
 	unsigned long end, a;
 
-	if (size >= scache_size) {
-		blast_dcache32();
-		return;
-	}
-
 	a = addr & ~(sc_lsize - 1);
 	end = (addr + size) & ~(sc_lsize - 1);
 	while (1) {
-		flush_scache_line(a); /* Hit_Writeback_Inv_SD */
+		invalidate_dcache_line(a);	/* Hit_Invalidate_D */
+		flush_icache_line(a);		/* Hit_Invalidate_I */
+		invalidate_scache_line(a);	/* Hit_Invalidate_SD */
 		if (a == end) break;
 		a += sc_lsize;
 	}
+
+	if (!rm7k_tcache_enabled) 
+		return;
+
+	a = addr & ~(tc_pagesize - 1);
+	end = (addr + size) & ~(tc_pagesize - 1);
+	while(1) {
+		invalidate_tcache_page(a);	/* Page_Invalidate_T */
+		if (a == end) break;
+		a += tc_pagesize;
+	}
 }
 
 static void
@@ -505,28 +542,144 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
         __restore_flags(flags);
 }
 
+/* Used for loading TLB entries before trap_init() has started, when we
+   don't actually want to add a wired entry which remains throughout the
+   lifetime of the system */
+
+static int temp_tlb_entry __initdata;
+
+__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask)
+{
+	int ret = 0;
+        unsigned long flags;
+        unsigned long wired;
+        unsigned long old_pagemask;
+        unsigned long old_ctx;
+
+        __save_and_cli(flags);
+        /* Save old context and create impossible VPN2 value */
+        old_ctx = (get_entryhi() & 0xff);
+        old_pagemask = get_pagemask();
+        wired = get_wired();
+        if (--temp_tlb_entry < wired) {
+		printk(KERN_WARNING "No TLB space left for add_temporary_entry\n");
+		ret = -ENOSPC;
+		goto out;
+	}
+
+        set_index (temp_tlb_entry);
+        BARRIER;    
+        set_pagemask (pagemask);
+        set_entryhi(entryhi);
+        set_entrylo0(entrylo0);
+        set_entrylo1(entrylo1);
+        BARRIER;    
+        tlb_write_indexed();
+        BARRIER;    
+    
+        set_entryhi(old_ctx);
+        BARRIER;    
+        set_pagemask (old_pagemask);
+ out:
+        __restore_flags(flags);
+	return ret;
+}
+
+
+
 /* Detect and size the caches. */
 static inline void probe_icache(unsigned long config)
 {
 	icache_size = 1 << (12 + ((config >> 9) & 7));
 
-	printk("Primary instruction cache %dkb.\n", icache_size >> 10);
+	printk("Primary instruction cache %dKiB.\n", icache_size >> 10);
 }
 
 static inline void probe_dcache(unsigned long config)
 {
 	dcache_size = 1 << (12 + ((config >> 6) & 7));
 
-	printk("Primary data cache %dkb.\n", dcache_size >> 10);
+	printk("Primary data cache %dKiB.\n", dcache_size >> 10);
+}
+
+
+/* 
+ * This function is executed in the uncached segment KSEG1.
+ * It must not touch the stack, because the stack pointer still points
+ * into KSEG0. 
+ *
+ * Three options:
+ *	- Write it in assembly and guarantee that we don't use the stack.
+ *	- Disable caching for KSEG0 before calling it.
+ *	- Pray that GCC doesn't randomly start using the stack.
+ *
+ * This being Linux, we obviously take the least sane of those options -
+ * following DaveM's lead in r4xx0.c
+ *
+ * It seems we get our kicks from relying on unguaranteed behaviour in GCC
+ *
+ */
+
+static void setup_scache(void)
+{
+	int register i;
+	
+	set_cp0_config(1<<3 /* CONF_SE */);
+
+	set_taglo(0);
+	set_taghi(0);
+	
+	for (i=0; i<scache_size; i+=sc_lsize) {
+		__asm__ __volatile__ (
+		      ".set noreorder\n\t"
+		      ".set mips3\n\t"
+		      "cache %1, (%0)\n\t"
+		      ".set mips0\n\t"
+		      ".set reorder"
+		      :
+		      : "r" (KSEG0ADDR(i)),
+		        "i" (Index_Store_Tag_SD));
+	}
+
 }
 
 static inline void probe_scache(unsigned long config)
 {
+	int (*func)(void)=KSEG1ADDR(&setup_scache);
+
 	if ((config >> 31) & 1)
 		return;
 
-	printk("Secondary cache %dkb, linesize %d bytes.\n",
+	printk("Secondary cache %dKiB, linesize %d bytes.\n",
 	       (scache_size >> 10), sc_lsize);
+
+	if ((config >> 3) & 1)
+		return;
+
+	printk("Enabling secondary cache...");
+	func();
+	printk("Done\n");
+}
+ 
+static inline void probe_tcache(unsigned long config)
+{
+	if ((config >> 17) & 1)
+		return;
+
+	/* We can't enable the L3 cache yet. There may be board-specific
+	 * magic necessary to turn it on, and blindly asking the CPU to
+	 * start using it would may give cache errors.
+	 *
+	 * Also, board-specific knowledge may allow us to use the 
+	 * CACHE Flash_Invalidate_T instruction if the tag RAM supports
+	 * it, and may specify the size of the L3 cache so we don't have
+	 * to probe it. 
+	 */
+	printk("Tertiary cache present, %s enabled\n", config&(1<<12)?"already":"not (yet)");
+
+	if ((config >> 12) & 1)
+		rm7k_tcache_enabled = 1;
 }
 
 void __init ld_mmu_rm7k(void)
@@ -540,6 +693,7 @@ void __init ld_mmu_rm7k(void)
 	probe_icache(config);
 	probe_dcache(config);
 	probe_scache(config);
+	probe_tcache(config);
 
 	printk("TLB has %d entries.\n", ntlb_entries());
 
@@ -562,7 +716,7 @@ void __init ld_mmu_rm7k(void)
 
 	__flush_cache_all_d32i32();
 	write_32bit_cp0_register(CP0_WIRED, 0);
-
+	temp_tlb_entry = ntlb_entries() - 1;
 	write_32bit_cp0_register(CP0_PAGEMASK, PM_4K);
 	flush_tlb_all();
 }
diff --git a/drivers/mtd/docprobe.c b/drivers/mtd/docprobe.c
index 9f5ba083b..b19df8fd3 100644
--- a/drivers/mtd/docprobe.c
+++ b/drivers/mtd/docprobe.c
@@ -86,6 +86,8 @@ static unsigned long __initdata doc_locations[] = {
 #endif /*  CONFIG_MTD_DOCPROBE_HIGH */
 #elif defined(__ppc__)
 	0xe4000000,
+#elif defined(CONFIG_MOMENCO_OCELOT)
+	0x2f000000,
 #else 
 #warning Unknown architecture for DiskOnChip. No default probe locations defined
 #endif
diff --git a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h
index 9984048f2..b87658a66 100644
--- a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h
+++ b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h
@@ -19,14 +19,16 @@
 #include <asm/byteorder.h>		/* for cpu_to_le32() */
 
 /*
- * PCI address allocatoin 
+ * PCI address allocation 
  */
-#define GT_PCI_MEM_BASE    GT_DEF_PCI0_MEM0_BASE
+#define GT_PCI_MEM_BASE    (0x22000000)
 #define GT_PCI_MEM_SIZE    GT_DEF_PCI0_MEM0_SIZE
-#define GT_PCI_IO_BASE     GT_DEF_PCI0_IO_BASE
+#define GT_PCI_IO_BASE     (0x20000000)
 #define GT_PCI_IO_SIZE     GT_DEF_PCI0_IO_SIZE
 
-#define GT64120_BASE       (KSEG1ADDR(GT_DEF_BASE))
+extern unsigned long gt64120_base;
+
+#define GT64120_BASE       (gt64120_base)
 
 /*
  * Because of an error/peculiarity in the Galileo chip, we need to swap the
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 76da1b3aa..f45669442 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -72,6 +72,12 @@
 #define CP0_IWATCH $18
 #define CP0_DWATCH $19
 
+/* 
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+
 /*
  * Coprocessor 1 (FPU) register names
  */
@@ -165,6 +171,16 @@
         : "=r" (__res));                                        \
         __res;})
 
+#define read_32bit_cp0_set1_register(source)                    \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "cfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
 /*
  * For now use this only with interrupts disabled!
  */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 6b4ebcbc3..605d48080 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -59,6 +59,16 @@ extern void (*_flush_icache_page)(struct vm_area_struct *vma,
 extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 			       unsigned long entryhi, unsigned long pagemask);
 
+/*
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
+ *	starting at the top and working down. This is for populating the
+ *	TLB before trap_init() puts the TLB miss handler in place. It 
+ *	should be used only for entries matching the actual page tables,
+ *	to prevent inconsistencies.
+ */
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+			       unsigned long entryhi, unsigned long pagemask);
+
 
 /* Basically we have the same two-level (which is the logical three level
  * Linux page table layout folded) page tables as the i386.  Some day
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 6d5634aa3..6c33daa38 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -234,7 +234,7 @@
 #define OCELOT_BASE_BAUD ( 20000000 / 16 )
 
 #define OCELOT_SERIAL1_IRQ	4
-#define OCELOT_SERIAL1_BASE	0xbd000020
+#define OCELOT_SERIAL1_BASE	0xe0001020
 
 #define _OCELOT_SERIAL_INIT(int, base)					\
 	{ baud_base: OCELOT_BASE_BAUD, irq: int, flags: STD_COM_FLAGS,	\