Rest of the merge.

31 files changed, 10753 insertions, 0 deletions

diff --git a/Documentation/usb/rio.txt b/Documentation/usb/rio.txt
new file mode 100644
index 000000000..0aa79ab00
--- /dev/null
+++ b/Documentation/usb/rio.txt
@@ -0,0 +1,138 @@
+Copyright (C) 1999, 2000 Bruce Tenison
+Portions Copyright (C) 1999, 2000 David Nelson
+Thanks to David Nelson for guidance and the usage of the scanner.txt
+and scanner.c files to model our driver and this informative file.
+
+Mar. 2, 2000
+
+CHANGES
+
+- Initial Revision
+
+
+OVERVIEW
+
+This README will address issues regarding how to configure the kernel
+to access a RIO 500 mp3 player.  
+Before I explain how to use this to access the Rio500 please be warned:
+
+W A R N I N G:
+--------------
+
+Please note that this software is still under development.  The authors
+are in no way responsible for any damage that may occur, no matter how
+inconsequential.
+
+It seems that the Rio has a problem when sending .mp3 with low batteries.
+I suggest when the batteries are low and want to transfer stuff that you
+replace it with a fresh one. In my case, what happened is I lost two 16kb
+blocks (they are no longer usable to store information to it). But I don't
+know if thats normal or not. It could simply be a problem with the flash 
+memory.
+
+In an extreme case, I left my Rio playing overnight and the batteries wore 
+down to nothing and appear to have corrupted the flash memory. My RIO 
+needed to be replaced as a result.  Diamond tech support is aware of the 
+problem.  Do NOT allow your batteries to wear down to nothing before 
+changing them.  It appears RIO 500 firmware does not handle low battery 
+power well at all. 
+
+On systems with OHCI controllers, the kernel OHCI code appears to have 
+power on problems with some chipsets.  If you are having problems 
+connecting to your RIO 500, try turning it on first and then plugging it 
+into the USB cable.  
+
+Contact information:
+--------------------
+
+   The main page for the project is hosted at sourceforge.net in the following
+   address: http://rio500.sourceforge.net You can also go to the sourceforge
+   project page at: http://sourceforge.net/project/?group_id=1944 There is 
+   also a mailing list: rio500-users@lists.sourceforge.net
+
+Authors:
+-------
+
+Most of the code was written by Cesar Miquel <miquel@df.uba.ar>. Keith 
+Clayton <kclayton@jps.net> is incharge of the PPC port and making sure
+things work there. Bruce Tenison <btenison@dibbs.net> is adding support
+for .fon files and also does testing. The program will mostly sure be
+re-written and Pete Ikusz along with the rest will re-design it. I would
+also like to thank Tri Nguyen <tmn_3022000@hotmail.com> who provided use 
+with some important information regarding the communication with the Rio.
+
+ADDITIONAL INFORMATION and Userspace tools
+
+http://rio500.sourceforge.net/
+
+
+REQUIREMENTS
+
+A host with a USB port.  Ideally, either a UHCI (Intel) or OHCI
+(Compaq and others) hardware port should work.
+
+A Linux development kernel (2.3.x) with USB support enabled or a
+backported version to linux-2.2.x.  See http://www.linux-usb.org for
+more information on accomplishing this.
+
+A Linux kernel with RIO 500 support enabled.
+
+'lspci' which is only needed to determine the type of USB hardware
+available in your machine.
+
+CONFIGURATION
+
+Using `lspci -v`, determine the type of USB hardware available.
+
+  If you see something like:
+
+    USB Controller: ......
+    Flags: .....
+    I/O ports at ....
+
+  Then you have a UHCI based controller.
+
+  If you see something like:
+
+     USB Controller: .....
+     Flags: ....
+     Memory at .....
+
+  Then you have a OHCI based controller.
+
+Using `make menuconfig` or your preferred method for configuring the
+kernel, select 'Support for USB', 'OHCI/UHCI' depending on your
+hardware (determined from the steps above), 'USB Diamond Rio500 support', and
+'Preliminary USB device filesystem'.  Compile and install the modules
+(you may need to execute `depmod -a` to update the module
+dependencies).
+
+Add a device for the USB rio500:
+  `mknod /dev/usb/rio500 c 180 64`
+
+Set appropriate permissions for /dev/usb/rio500 (don't forget about
+group and world permissions).  Both read and write permissions are
+required for proper operation.
+
+Load the appropriate modules (if compiled as modules):
+
+  OHCI:
+    modprobe usbcore
+    modprobe usb-ohci
+    modprobe rio500
+
+  UHCI:
+    modprobe usbcore
+    modprobe usb-uhci  (or uhci)
+    modprobe rio500
+
+That's it.  The Rio500 Utils at: http://rio500.sourceforge.net should
+be able to access the rio500.
+
+BUGS
+
+If you encounter any problems feel free to drop me an email.
+
+Bruce Tenison
+btenison@dibbs.net
+
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
new file mode 100644
index 000000000..62ba2362f
--- /dev/null
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -0,0 +1,248 @@
+/*
+ * Alpha specific irq code.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+
+#include <asm/machvec.h>
+#include <asm/dma.h>
+
+#include "proto.h"
+#include "irq_impl.h"
+
+/* Only uniprocessor needs this IRQ/BH locking depth, on SMP it lives
+   in the per-cpu structure for cache reasons.  */
+#ifndef CONFIG_SMP
+int __local_irq_count;
+int __local_bh_count;
+unsigned long __irq_attempt[NR_IRQS];
+#endif
+
+/* Hack minimum IPL during interupt processing for broken hardware.  */
+#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
+int __min_ipl;
+#endif
+
+/*
+ * Performance counter hook.  A module can override this to
+ * do something useful.
+ */
+static void
+dummy_perf(unsigned long vector, struct pt_regs *regs)
+{
+	irq_err_count++;
+	printk(KERN_CRIT "Performance counter interrupt!\n");
+}
+
+void (*perf_irq)(unsigned long, struct pt_regs *) = dummy_perf;
+
+/*
+ * The main interrupt entry point.
+ */
+
+asmlinkage void 
+do_entInt(unsigned long type, unsigned long vector, unsigned long la_ptr,
+	  unsigned long a3, unsigned long a4, unsigned long a5,
+	  struct pt_regs regs)
+{
+	switch (type) {
+	case 0:
+#ifdef CONFIG_SMP
+		handle_ipi(&regs);
+		return;
+#else
+		irq_err_count++;
+		printk(KERN_CRIT "Interprocessor interrupt? "
+		       "You must be kidding!\n");
+#endif
+		break;
+	case 1:
+#ifdef CONFIG_SMP
+		cpu_data[smp_processor_id()].smp_local_irq_count++;
+		smp_percpu_timer_interrupt(&regs);
+		if (smp_processor_id() == boot_cpuid)
+#endif
+			handle_irq(RTC_IRQ, &regs);
+		return;
+	case 2:
+		irq_err_count++;
+		alpha_mv.machine_check(vector, la_ptr, &regs);
+		return;
+	case 3:
+		alpha_mv.device_interrupt(vector, &regs);
+		return;
+	case 4:
+		perf_irq(vector, &regs);
+		return;
+	default:
+		printk(KERN_CRIT "Hardware intr %ld %lx? Huh?\n",
+		       type, vector);
+	}
+	printk("PC = %016lx PS=%04lx\n", regs.pc, regs.ps);
+}
+
+void __init
+common_init_isa_dma(void)
+{
+	outb(0, DMA1_RESET_REG);
+	outb(0, DMA2_RESET_REG);
+	outb(0, DMA1_CLR_MASK_REG);
+	outb(0, DMA2_CLR_MASK_REG);
+}
+
+void __init
+init_IRQ(void)
+{
+	alpha_mv.init_irq();
+	wrent(entInt, 0);
+}
+
+/*
+ * machine error checks
+ */
+#define MCHK_K_TPERR           0x0080
+#define MCHK_K_TCPERR          0x0082
+#define MCHK_K_HERR            0x0084
+#define MCHK_K_ECC_C           0x0086
+#define MCHK_K_ECC_NC          0x0088
+#define MCHK_K_OS_BUGCHECK     0x008A
+#define MCHK_K_PAL_BUGCHECK    0x0090
+
+#ifndef CONFIG_SMP
+struct mcheck_info __mcheck_info;
+#endif
+
+void
+process_mcheck_info(unsigned long vector, unsigned long la_ptr,
+		    struct pt_regs *regs, const char *machine,
+		    int expected)
+{
+	struct el_common *mchk_header;
+	const char *reason;
+
+	/*
+	 * See if the machine check is due to a badaddr() and if so,
+	 * ignore it.
+	 */
+
+#if DEBUG_MCHECK > 0
+	 printk(KERN_CRIT "%s machine check %s\n", machine,
+	        expected ? "expected." : "NOT expected!!!");
+#endif
+
+	if (expected) {
+		int cpu = smp_processor_id();
+		mcheck_expected(cpu) = 0;
+		mcheck_taken(cpu) = 1;
+		return;
+	}
+
+	mchk_header = (struct el_common *)la_ptr;
+
+	printk(KERN_CRIT "%s machine check: vector=0x%lx pc=0x%lx code=0x%lx\n",
+	       machine, vector, regs->pc, mchk_header->code);
+
+	switch ((unsigned int) mchk_header->code) {
+	/* Machine check reasons.  Defined according to PALcode sources.  */
+	case 0x80: reason = "tag parity error"; break;
+	case 0x82: reason = "tag control parity error"; break;
+	case 0x84: reason = "generic hard error"; break;
+	case 0x86: reason = "correctable ECC error"; break;
+	case 0x88: reason = "uncorrectable ECC error"; break;
+	case 0x8A: reason = "OS-specific PAL bugcheck"; break;
+	case 0x90: reason = "callsys in kernel mode"; break;
+	case 0x96: reason = "i-cache read retryable error"; break;
+	case 0x98: reason = "processor detected hard error"; break;
+	
+	/* System specific (these are for Alcor, at least): */
+	case 0x202: reason = "system detected hard error"; break;
+	case 0x203: reason = "system detected uncorrectable ECC error"; break;
+	case 0x204: reason = "SIO SERR occurred on PCI bus"; break;
+	case 0x205: reason = "parity error detected by CIA"; break;
+	case 0x206: reason = "SIO IOCHK occurred on ISA bus"; break;
+	case 0x207: reason = "non-existent memory error"; break;
+	case 0x208: reason = "MCHK_K_DCSR"; break;
+	case 0x209: reason = "PCI SERR detected"; break;
+	case 0x20b: reason = "PCI data parity error detected"; break;
+	case 0x20d: reason = "PCI address parity error detected"; break;
+	case 0x20f: reason = "PCI master abort error"; break;
+	case 0x211: reason = "PCI target abort error"; break;
+	case 0x213: reason = "scatter/gather PTE invalid error"; break;
+	case 0x215: reason = "flash ROM write error"; break;
+	case 0x217: reason = "IOA timeout detected"; break;
+	case 0x219: reason = "IOCHK#, EISA add-in board parity or other catastrophic error"; break;
+	case 0x21b: reason = "EISA fail-safe timer timeout"; break;
+	case 0x21d: reason = "EISA bus time-out"; break;
+	case 0x21f: reason = "EISA software generated NMI"; break;
+	case 0x221: reason = "unexpected ev5 IRQ[3] interrupt"; break;
+	default: reason = "unknown"; break;
+	}
+
+	printk(KERN_CRIT "machine check type: %s%s\n",
+	       reason, mchk_header->retry ? " (retryable)" : "");
+
+	dik_show_regs(regs, NULL);
+
+#if DEBUG_MCHECK > 1
+	{
+		/* Dump the logout area to give all info.  */
+		unsigned long *ptr = (unsigned long *)la_ptr;
+		long i;
+		for (i = 0; i < mchk_header->size / sizeof(long); i += 2) {
+			printk(KERN_CRIT "   +%8lx %016lx %016lx\n",
+			       i*sizeof(long), ptr[i], ptr[i+1]);
+		}
+	}
+#endif
+}
+
+/*
+ * The special RTC interrupt type.  The interrupt itself was
+ * processed by PALcode, and comes in via entInt vector 1.
+ */
+
+static void rtc_enable_disable(unsigned int irq) { }
+static unsigned int rtc_startup(unsigned int irq) { return 0; }
+
+struct irqaction timer_irqaction = {
+	handler:	timer_interrupt,
+	flags:		SA_INTERRUPT,
+	name:		"timer",
+};
+
+static struct hw_interrupt_type rtc_irq_type = {
+	typename:	"RTC",
+	startup:	rtc_startup,
+	shutdown:	rtc_enable_disable,
+	enable:		rtc_enable_disable,
+	disable:	rtc_enable_disable,
+	ack:		rtc_enable_disable,
+	end:		rtc_enable_disable,
+};
+
+void __init
+init_rtc_irq(void)
+{
+	irq_desc[RTC_IRQ].status = IRQ_DISABLED;
+	irq_desc[RTC_IRQ].handler = &rtc_irq_type;
+	setup_irq(RTC_IRQ, &timer_irqaction);
+}
+
+/* Dummy irqactions.  */
+struct irqaction isa_cascade_irqaction = {
+	handler:	no_action,
+	name:		"isa-cascade"
+};
+
+struct irqaction timer_cascade_irqaction = {
+	handler:	no_action,
+	name:		"timer-cascade"
+};
+
+struct irqaction halt_switch_irqaction = {
+	handler:	no_action,
+	name:		"halt-switch"
+};
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
new file mode 100644
index 000000000..a47178050
--- /dev/null
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -0,0 +1,187 @@
+/*
+ *      linux/arch/alpha/kernel/irq_i8259.c
+ *
+ * This is the 'legacy' 8259A Programmable Interrupt Controller,
+ * present in the majority of PC/AT boxes.
+ *
+ * Started hacking from linux-2.3.30pre6/arch/i386/kernel/i8259.c.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/cache.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+
+#include "proto.h"
+#include "irq_impl.h"
+
+
+/* Note mask bit is true for DISABLED irqs.  */
+static unsigned int cached_irq_mask = 0xffff;
+spinlock_t i8259_irq_lock = SPIN_LOCK_UNLOCKED;
+
+static inline void
+i8259_update_irq_hw(unsigned int irq, unsigned long mask)
+{
+	int port = 0x21;
+	if (irq & 8) mask >>= 8;
+	if (irq & 8) port = 0xA1;
+	outb(mask, port);
+}
+
+inline void
+i8259a_enable_irq(unsigned int irq)
+{
+	spin_lock(&i8259_irq_lock);
+	i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+	spin_unlock(&i8259_irq_lock);
+}
+
+static inline void
+__i8259a_disable_irq(unsigned int irq)
+{
+	i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
+}
+
+void
+i8259a_disable_irq(unsigned int irq)
+{
+	spin_lock(&i8259_irq_lock);
+	__i8259a_disable_irq(irq);
+	spin_unlock(&i8259_irq_lock);
+}
+
+void
+i8259a_mask_and_ack_irq(unsigned int irq)
+{
+	spin_lock(&i8259_irq_lock);
+	__i8259a_disable_irq(irq);
+
+	/* Ack the interrupt making it the lowest priority.  */
+	if (irq >= 8) {
+		outb(0xE0 | (irq - 8), 0xa0);   /* ack the slave */
+		irq = 2;
+	}
+	outb(0xE0 | irq, 0x20);			/* ack the master */
+	spin_unlock(&i8259_irq_lock);
+}
+
+unsigned int
+i8259a_startup_irq(unsigned int irq)
+{
+	i8259a_enable_irq(irq);
+	return 0; /* never anything pending */
+}
+
+void
+i8259a_end_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		i8259a_enable_irq(irq);
+}
+
+struct hw_interrupt_type i8259a_irq_type = {
+	typename:	"XT-PIC",
+	startup:	i8259a_startup_irq,
+	shutdown:	i8259a_disable_irq,
+	enable:		i8259a_enable_irq,
+	disable:	i8259a_disable_irq,
+	ack:		i8259a_mask_and_ack_irq,
+	end:		i8259a_end_irq,
+};
+
+void __init
+init_i8259a_irqs(void)
+{
+	static struct irqaction cascade = {
+		handler:	no_action,
+		name:		"cascade",
+	};
+
+	long i;
+
+	outb(0xff, 0x21);	/* mask all of 8259A-1 */
+	outb(0xff, 0xA1);	/* mask all of 8259A-2 */
+
+	for (i = 0; i < 16; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].handler = &i8259a_irq_type;
+	}
+
+	setup_irq(2, &cascade);
+}
+
+
+#if defined(CONFIG_ALPHA_GENERIC)
+# define IACK_SC	alpha_mv.iack_sc
+#elif defined(CONFIG_ALPHA_APECS)
+# define IACK_SC	APECS_IACK_SC
+#elif defined(CONFIG_ALPHA_LCA)
+# define IACK_SC	LCA_IACK_SC
+#elif defined(CONFIG_ALPHA_CIA)
+# define IACK_SC	CIA_IACK_SC
+#elif defined(CONFIG_ALPHA_PYXIS)
+# define IACK_SC	PYXIS_IACK_SC
+#elif defined(CONFIG_ALPHA_TSUNAMI)
+# define IACK_SC	TSUNAMI_IACK_SC
+#elif defined(CONFIG_ALPHA_POLARIS)
+# define IACK_SC	POLARIS_IACK_SC
+#elif defined(CONFIG_ALPHA_IRONGATE)
+# define IACK_SC        IRONGATE_IACK_SC
+#endif
+
+#if defined(IACK_SC)
+void
+isa_device_interrupt(unsigned long vector, struct pt_regs *regs)
+{
+	/*
+	 * Generate a PCI interrupt acknowledge cycle.  The PIC will
+	 * respond with the interrupt vector of the highest priority
+	 * interrupt that is pending.  The PALcode sets up the
+	 * interrupts vectors such that irq level L generates vector L.
+	 */
+	int j = *(vuip) IACK_SC;
+	j &= 0xff;
+	if (j == 7) {
+		if (!(inb(0x20) & 0x80)) {
+			/* It's only a passive release... */
+			return;
+		}
+	}
+	handle_irq(j, regs);
+}
+#endif
+
+#if defined(CONFIG_ALPHA_GENERIC) || !defined(IACK_SC)
+void
+isa_no_iack_sc_device_interrupt(unsigned long vector, struct pt_regs *regs)
+{
+	unsigned long pic;
+
+	/*
+	 * It seems to me that the probability of two or more *device*
+	 * interrupts occurring at almost exactly the same time is
+	 * pretty low.  So why pay the price of checking for
+	 * additional interrupts here if the common case can be
+	 * handled so much easier?
+	 */
+	/* 
+	 *  The first read of gives you *all* interrupting lines.
+	 *  Therefore, read the mask register and and out those lines
+	 *  not enabled.  Note that some documentation has 21 and a1 
+	 *  write only.  This is not true.
+	 */
+	pic = inb(0x20) | (inb(0xA0) << 8);	/* read isr */
+	pic &= 0xFFFB;				/* mask out cascade & hibits */
+
+	while (pic) {
+		int j = ffz(~pic);
+		pic &= pic - 1;
+		handle_irq(j, regs);
+	}
+}
+#endif
diff --git a/arch/alpha/kernel/irq_smp.c b/arch/alpha/kernel/irq_smp.c
new file mode 100644
index 000000000..90a3c30b2
--- /dev/null
+++ b/arch/alpha/kernel/irq_smp.c
@@ -0,0 +1,250 @@
+/*
+ *	linux/arch/alpha/kernel/irq_smp.c
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/random.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+
+
+/* Who has global_irq_lock. */
+int global_irq_holder = NO_PROC_ID;
+
+/* This protects IRQ's. */
+spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED;
+
+/* Global IRQ locking depth. */
+static void *previous_irqholder = NULL;
+
+#define MAXCOUNT 100000000
+
+
+static void
+show(char * str, void *where)
+{
+#if 0
+	int i;
+        unsigned long *stack;
+#endif
+        int cpu = smp_processor_id();
+
+        printk("\n%s, CPU %d: %p\n", str, cpu, where);
+        printk("irq:  %d [%d %d]\n",
+	       irqs_running(),
+               cpu_data[0].irq_count,
+	       cpu_data[1].irq_count);
+
+        printk("bh:   %d [%d %d]\n",
+	       spin_is_locked(&global_bh_lock) ? 1 : 0,
+	       cpu_data[0].bh_count,
+	       cpu_data[1].bh_count);
+#if 0
+        stack = (unsigned long *) &str;
+        for (i = 40; i ; i--) {
+		unsigned long x = *++stack;
+                if (x > (unsigned long) &init_task_union &&
+		    x < (unsigned long) &vsprintf) {
+			printk("<[%08lx]> ", x);
+                }
+        }
+#endif
+}
+
+static inline void
+wait_on_irq(int cpu, void *where)
+{
+	int count = MAXCOUNT;
+
+	for (;;) {
+
+		/*
+		 * Wait until all interrupts are gone. Wait
+		 * for bottom half handlers unless we're
+		 * already executing in one..
+		 */
+		if (!irqs_running()) {
+			if (local_bh_count(cpu)
+			    || !spin_is_locked(&global_bh_lock))
+				break;
+		}
+
+		/* Duh, we have to loop. Release the lock to avoid deadlocks */
+		spin_unlock(&global_irq_lock);
+
+		for (;;) {
+			if (!--count) {
+				show("wait_on_irq", where);
+				count = MAXCOUNT;
+			}
+			__sti();
+			udelay(1); /* make sure to run pending irqs */
+			__cli();
+
+			if (irqs_running())
+				continue;
+			if (spin_is_locked(&global_irq_lock))
+				continue;
+			if (!local_bh_count(cpu)
+			    && spin_is_locked(&global_bh_lock))
+				continue;
+			if (spin_trylock(&global_irq_lock))
+				break;
+		}
+	}
+}
+
+static inline void
+get_irqlock(int cpu, void* where)
+{
+	if (!spin_trylock(&global_irq_lock)) {
+		/* Do we already hold the lock?  */
+		if (cpu == global_irq_holder)
+			return;
+		/* Uhhuh.. Somebody else got it.  Wait.  */
+		spin_lock(&global_irq_lock);
+	}
+
+	/*
+	 * Ok, we got the lock bit.
+	 * But that's actually just the easy part.. Now
+	 * we need to make sure that nobody else is running
+	 * in an interrupt context. 
+	 */
+	wait_on_irq(cpu, where);
+
+	/*
+	 * Finally.
+	 */
+#if DEBUG_SPINLOCK
+	global_irq_lock.task = current;
+	global_irq_lock.previous = where;
+#endif
+	global_irq_holder = cpu;
+	previous_irqholder = where;
+}
+
+void
+__global_cli(void)
+{
+	int cpu = smp_processor_id();
+	void *where = __builtin_return_address(0);
+
+	/*
+	 * Maximize ipl.  If ipl was previously 0 and if this thread
+	 * is not in an irq, then take global_irq_lock.
+	 */
+	if (swpipl(IPL_MAX) == IPL_MIN && !local_irq_count(cpu))
+		get_irqlock(cpu, where);
+}
+
+void
+__global_sti(void)
+{
+        int cpu = smp_processor_id();
+
+        if (!local_irq_count(cpu))
+		release_irqlock(cpu);
+	__sti();
+}
+
+/*
+ * SMP flags value to restore to:
+ * 0 - global cli
+ * 1 - global sti
+ * 2 - local cli
+ * 3 - local sti
+ */
+unsigned long
+__global_save_flags(void)
+{
+        int retval;
+        int local_enabled;
+        unsigned long flags;
+	int cpu = smp_processor_id();
+
+        __save_flags(flags);
+        local_enabled = (!(flags & 7));
+        /* default to local */
+        retval = 2 + local_enabled;
+
+        /* Check for global flags if we're not in an interrupt.  */
+        if (!local_irq_count(cpu)) {
+                if (local_enabled)
+                        retval = 1;
+                if (global_irq_holder == cpu)
+                        retval = 0;
+	}
+	return retval;
+}
+
+void
+__global_restore_flags(unsigned long flags)
+{
+        switch (flags) {
+        case 0:
+                __global_cli();
+                break;
+        case 1:
+                __global_sti();
+                break;
+        case 2:
+                __cli();
+                break;
+        case 3:
+                __sti();
+                break;
+        default:
+                printk(KERN_ERR "global_restore_flags: %08lx (%p)\n",
+                        flags, __builtin_return_address(0));
+        }
+}
+
+/*
+ * From its use, I infer that synchronize_irq() stalls a thread until
+ * the effects of a command to an external device are known to have
+ * taken hold.  Typically, the command is to stop sending interrupts.
+ * The strategy here is wait until there is at most one processor
+ * (this one) in an irq.  The memory barrier serializes the write to
+ * the device and the subsequent accesses of global_irq_count.
+ * --jmartin
+ */
+#define DEBUG_SYNCHRONIZE_IRQ 0
+
+void
+synchronize_irq(void)
+{
+#if 0
+	/* Joe's version.  */
+	int cpu = smp_processor_id();
+	int local_count;
+	int global_count;
+	int countdown = 1<<24;
+	void *where = __builtin_return_address(0);
+
+	mb();
+	do {
+		local_count = local_irq_count(cpu);
+		global_count = atomic_read(&global_irq_count);
+		if (DEBUG_SYNCHRONIZE_IRQ && (--countdown == 0)) {
+			printk("%d:%d/%d\n", cpu, local_count, global_count);
+			show("synchronize_irq", where);
+			break;
+		}
+	} while (global_count != local_count);
+#else
+	/* Jay's version.  */
+	if (irqs_running()) {
+		cli();
+		sti();
+	}
+#endif
+}
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c
new file mode 100644
index 000000000..8b14a59fe
--- /dev/null
+++ b/arch/alpha/kernel/irq_srm.c
@@ -0,0 +1,82 @@
+/*
+ * Handle interrupts from the SRM, assuming no additional weirdness.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+
+#include <asm/machvec.h>
+#include <asm/dma.h>
+
+#include "proto.h"
+#include "irq_impl.h"
+
+
+/*
+ * Is the palcode SMP safe? In other words: can we call cserve_ena/dis
+ * at the same time in multiple CPUs? To be safe I added a spinlock
+ * but it can be removed trivially if the palcode is robust against smp.
+ */
+spinlock_t srm_irq_lock = SPIN_LOCK_UNLOCKED;
+
+static inline void
+srm_enable_irq(unsigned int irq)
+{
+	spin_lock(&srm_irq_lock);
+	cserve_ena(irq - 16);
+	spin_unlock(&srm_irq_lock);
+}
+
+static void
+srm_disable_irq(unsigned int irq)
+{
+	spin_lock(&srm_irq_lock);
+	cserve_dis(irq - 16);
+	spin_unlock(&srm_irq_lock);
+}
+
+static unsigned int
+srm_startup_irq(unsigned int irq)
+{
+	srm_enable_irq(irq);
+	return 0;
+}
+
+static void
+srm_end_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		srm_enable_irq(irq);
+}
+
+/* Handle interrupts from the SRM, assuming no additional weirdness.  */
+static struct hw_interrupt_type srm_irq_type = {
+	typename:	"SRM",
+	startup:	srm_startup_irq,
+	shutdown:	srm_disable_irq,
+	enable:		srm_enable_irq,
+	disable:	srm_disable_irq,
+	ack:		srm_disable_irq,
+	end:		srm_end_irq,
+};
+
+void __init
+init_srm_irqs(long max, unsigned long ignore_mask)
+{
+	long i;
+
+	for (i = 16; i < max; ++i) {
+		if (i < 64 && ((ignore_mask >> i) & 1))
+			continue;
+		irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
+		irq_desc[i].handler = &srm_irq_type;
+	}
+}
+
+void 
+srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
+{
+	int irq = (vector - 0x800) >> 4;
+	handle_irq(irq, regs);
+}
diff --git a/arch/arm/mm/mm-clps7500.c b/arch/arm/mm/mm-clps7500.c
new file mode 100644
index 000000000..b9199de80
--- /dev/null
+++ b/arch/arm/mm/mm-clps7500.c
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mm/mm-cl7500.c
+ *
+ * Extra MM routines for CL7500 architecture
+ *
+ * Copyright (C) 1998 Russell King
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/page.h>
+#include <asm/proc/domain.h>
+#include <asm/setup.h>
+
+#include "map.h"
+
+#define SIZE(x) (sizeof(x) / sizeof(x[0]))
+
+struct map_desc io_desc[] __initdata = {
+	{ IO_BASE,	IO_START,	IO_SIZE	 , DOMAIN_IO, 0, 1 },	/* IO space	*/
+	{ ISA_BASE,	ISA_START,	ISA_SIZE , DOMAIN_IO, 0, 1 },	/* ISA space	*/
+	{ FLASH_BASE,	FLASH_START,	FLASH_SIZE, DOMAIN_IO, 0, 1 },	/* Flash	*/
+	{ LED_BASE,	LED_START,	LED_SIZE , DOMAIN_IO, 0, 1 }	/* LED		*/
+};
+
+unsigned int __initdata io_desc_size = SIZE(io_desc);
diff --git a/drivers/block/ide-cs.c b/drivers/block/ide-cs.c
new file mode 100644
index 000000000..73d285cb1
--- /dev/null
+++ b/drivers/block/ide-cs.c
@@ -0,0 +1,481 @@
+/*======================================================================
+
+    A driver for PCMCIA IDE/ATA disk cards
+
+    ide_cs.c 1.26 1999/11/16 02:10:49
+
+    The contents of this file are subject to the Mozilla Public
+    License Version 1.1 (the "License"); you may not use this file
+    except in compliance with the License. You may obtain a copy of
+    the License at http://www.mozilla.org/MPL/
+
+    Software distributed under the License is distributed on an "AS
+    IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+    implied. See the License for the specific language governing
+    rights and limitations under the License.
+
+    The initial developer of the original code is David A. Hinds
+    <dhinds@pcmcia.sourceforge.org>.  Portions created by David A. Hinds
+    are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+
+    Alternatively, the contents of this file may be used under the
+    terms of the GNU Public License version 2 (the "GPL"), in which
+    case the provisions of the GPL are applicable instead of the
+    above.  If you wish to allow the use of your version of this file
+    only under the terms of the GPL and not to allow others to use
+    your version of this file under the MPL, indicate your decision
+    by deleting the provisions above and replace them with the notice
+    and other provisions required by the GPL.  If you do not delete
+    the provisions above, a recipient may use your version of this
+    file under either the MPL or the GPL.
+    
+======================================================================*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/malloc.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/ioport.h>
+#include <linux/hdreg.h>
+#include <linux/major.h>
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+#include <pcmcia/version.h>
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/cistpl.h>
+#include <pcmcia/ds.h>
+#include <pcmcia/cisreg.h>
+
+#ifdef PCMCIA_DEBUG
+static int pc_debug = PCMCIA_DEBUG;
+MODULE_PARM(pc_debug, "i");
+#define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
+static char *version =
+"ide_cs.c 1.26 1999/11/16 02:10:49 (David Hinds)";
+#else
+#define DEBUG(n, args...)
+#endif
+
+/*====================================================================*/
+
+/* Parameters that can be set with 'insmod' */
+
+/* Bit map of interrupts to choose from */
+static u_int irq_mask = 0xdeb8;
+static int irq_list[4] = { -1 };
+
+MODULE_PARM(irq_mask, "i");
+MODULE_PARM(irq_list, "1-4i");
+
+/*====================================================================*/
+
+static const char ide_major[] = {
+    IDE0_MAJOR, IDE1_MAJOR, IDE2_MAJOR, IDE3_MAJOR,
+#ifdef IDE4_MAJOR
+    IDE4_MAJOR, IDE5_MAJOR
+#endif
+};
+
+typedef struct ide_info_t {
+    dev_link_t	link;
+    int		ndev;
+    dev_node_t	node;
+    int		hd;
+} ide_info_t;
+
+static void ide_config(dev_link_t *link);
+static void ide_release(u_long arg);
+static int ide_event(event_t event, int priority,
+		     event_callback_args_t *args);
+
+static dev_info_t dev_info = "ide_cs";
+
+static dev_link_t *ide_attach(void);
+static void ide_detach(dev_link_t *);
+
+static dev_link_t *dev_list = NULL;
+
+/*====================================================================*/
+
+static void cs_error(client_handle_t handle, int func, int ret)
+{
+    error_info_t err = { func, ret };
+    CardServices(ReportError, handle, &err);
+}
+
+/*======================================================================
+
+    ide_attach() creates an "instance" of the driver, allocating
+    local data structures for one device.  The device is registered
+    with Card Services.
+
+======================================================================*/
+
+static dev_link_t *ide_attach(void)
+{
+    ide_info_t *info;
+    dev_link_t *link;
+    client_reg_t client_reg;
+    int i, ret;
+    
+    DEBUG(0, "ide_attach()\n");
+
+    /* Create new ide device */
+    info = kmalloc(sizeof(*info), GFP_KERNEL);
+    if (!info) return NULL;
+    memset(info, 0, sizeof(*info));
+    link = &info->link; link->priv = info;
+
+    link->release.function = &ide_release;
+    link->release.data = (u_long)link;
+    link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
+    link->io.Attributes2 = IO_DATA_PATH_WIDTH_8;
+    link->io.IOAddrLines = 3;
+    link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
+    link->irq.IRQInfo1 = IRQ_INFO2_VALID|IRQ_LEVEL_ID;
+    if (irq_list[0] == -1)
+	link->irq.IRQInfo2 = irq_mask;
+    else
+	for (i = 0; i < 4; i++)
+	    link->irq.IRQInfo2 |= 1 << irq_list[i];
+    link->conf.Attributes = CONF_ENABLE_IRQ;
+    link->conf.Vcc = 50;
+    link->conf.IntType = INT_MEMORY_AND_IO;
+    
+    /* Register with Card Services */
+    link->next = dev_list;
+    dev_list = link;
+    client_reg.dev_info = &dev_info;
+    client_reg.Attributes = INFO_IO_CLIENT | INFO_CARD_SHARE;
+    client_reg.EventMask =
+	CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
+	CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
+	CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
+    client_reg.event_handler = &ide_event;
+    client_reg.Version = 0x0210;
+    client_reg.event_callback_args.client_data = link;
+    ret = CardServices(RegisterClient, &link->handle, &client_reg);
+    if (ret != CS_SUCCESS) {
+	cs_error(link->handle, RegisterClient, ret);
+	ide_detach(link);
+	return NULL;
+    }
+    
+    return link;
+} /* ide_attach */
+
+/*======================================================================
+
+    This deletes a driver "instance".  The device is de-registered
+    with Card Services.  If it has been released, all local data
+    structures are freed.  Otherwise, the structures will be freed
+    when the device is released.
+
+======================================================================*/
+
+static void ide_detach(dev_link_t *link)
+{
+    dev_link_t **linkp;
+    long flags;
+    int ret;
+
+    DEBUG(0, "ide_detach(0x%p)\n", link);
+    
+    /* Locate device structure */
+    for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
+	if (*linkp == link) break;
+    if (*linkp == NULL)
+	return;
+
+    save_flags(flags);
+    cli();
+    if (link->state & DEV_RELEASE_PENDING) {
+	del_timer(&link->release);
+	link->state &= ~DEV_RELEASE_PENDING;
+    }
+    restore_flags(flags);
+    
+    if (link->state & DEV_CONFIG)
+	ide_release((u_long)link);
+    
+    if (link->handle) {
+	ret = CardServices(DeregisterClient, link->handle);
+	if (ret != CS_SUCCESS)
+	    cs_error(link->handle, DeregisterClient, ret);
+    }
+    
+    /* Unlink, free device structure */
+    *linkp = link->next;
+    kfree(link->priv);
+    
+} /* ide_detach */
+
+/*======================================================================
+
+    ide_config() is scheduled to run after a CARD_INSERTION event
+    is received, to configure the PCMCIA socket, and to make the
+    ide device available to the system.
+
+======================================================================*/
+
+#define CS_CHECK(fn, args...) \
+while ((last_ret=CardServices(last_fn=(fn), args))!=0) goto cs_failed
+
+#define CFG_CHECK(fn, args...) \
+if (CardServices(fn, args) != 0) goto next_entry
+
+void ide_config(dev_link_t *link)
+{
+    client_handle_t handle = link->handle;
+    ide_info_t *info = link->priv;
+    tuple_t tuple;
+    u_short buf[128];
+    cisparse_t parse;
+    config_info_t conf;
+    cistpl_cftable_entry_t *cfg = &parse.cftable_entry;
+    cistpl_cftable_entry_t dflt = { 0 };
+    int i, pass, last_ret, last_fn, hd, io_base, ctl_base;
+
+    DEBUG(0, "ide_config(0x%p)\n", link);
+    
+    tuple.TupleData = (cisdata_t *)buf;
+    tuple.TupleOffset = 0; tuple.TupleDataMax = 255;
+    tuple.Attributes = 0;
+    tuple.DesiredTuple = CISTPL_CONFIG;
+    CS_CHECK(GetFirstTuple, handle, &tuple);
+    CS_CHECK(GetTupleData, handle, &tuple);
+    CS_CHECK(ParseTuple, handle, &tuple, &parse);
+    link->conf.ConfigBase = parse.config.base;
+    link->conf.Present = parse.config.rmask[0];
+    
+    /* Configure card */
+    link->state |= DEV_CONFIG;
+
+    /* Not sure if this is right... look up the current Vcc */
+    CS_CHECK(GetConfigurationInfo, handle, &conf);
+    link->conf.Vcc = conf.Vcc;
+    
+    pass = io_base = ctl_base = 0;
+    tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
+    tuple.Attributes = 0;
+    CS_CHECK(GetFirstTuple, handle, &tuple);
+    while (1) {
+	CFG_CHECK(GetTupleData, handle, &tuple);
+	CFG_CHECK(ParseTuple, handle, &tuple, &parse);
+
+	/* Check for matching Vcc, unless we're desperate */
+	if (!pass) {
+	    if (cfg->vcc.present & (1<<CISTPL_POWER_VNOM)) {
+		if (conf.Vcc != cfg->vcc.param[CISTPL_POWER_VNOM]/10000)
+		    goto next_entry;
+	    } else if (dflt.vcc.present & (1<<CISTPL_POWER_VNOM)) {
+		if (conf.Vcc != dflt.vcc.param[CISTPL_POWER_VNOM]/10000)
+		    goto next_entry;
+	    }
+	}
+	
+	if (cfg->vpp1.present & (1<<CISTPL_POWER_VNOM))
+	    link->conf.Vpp1 = link->conf.Vpp2 =
+		cfg->vpp1.param[CISTPL_POWER_VNOM]/10000;
+	else if (dflt.vpp1.present & (1<<CISTPL_POWER_VNOM))
+	    link->conf.Vpp1 = link->conf.Vpp2 =
+		dflt.vpp1.param[CISTPL_POWER_VNOM]/10000;
+	
+	if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
+	    cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt.io;
+	    link->conf.ConfigIndex = cfg->index;
+	    link->io.BasePort1 = io->win[0].base;
+	    link->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
+	    if (!(io->flags & CISTPL_IO_16BIT))
+		link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
+	    if (io->nwin == 2) {
+		link->io.NumPorts1 = 8;
+		link->io.BasePort2 = io->win[1].base;
+		link->io.NumPorts2 = 1;
+		CFG_CHECK(RequestIO, link->handle, &link->io);
+		io_base = link->io.BasePort1;
+		ctl_base = link->io.BasePort2;
+	    } else if ((io->nwin == 1) && (io->win[0].len >= 16)) {
+		link->io.NumPorts1 = io->win[0].len;
+		link->io.NumPorts2 = 0;
+		CFG_CHECK(RequestIO, link->handle, &link->io);
+		io_base = link->io.BasePort1;
+		ctl_base = link->io.BasePort1+0x0e;
+	    } else goto next_entry;
+	    /* If we've got this far, we're done */
+	    break;
+	}
+	
+    next_entry:
+	if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg;
+	if (pass) {
+	    CS_CHECK(GetNextTuple, handle, &tuple);
+	} else if (CardServices(GetNextTuple, handle, &tuple) != 0) {
+	    CS_CHECK(GetFirstTuple, handle, &tuple);
+	    memset(&dflt, 0, sizeof(dflt));
+	    pass++;
+	}
+    }
+    
+    CS_CHECK(RequestIRQ, handle, &link->irq);
+    CS_CHECK(RequestConfiguration, handle, &link->conf);
+
+    /* deal with brain dead IDE resource management */
+    release_region(link->io.BasePort1, link->io.NumPorts1);
+    if (link->io.NumPorts2)
+	release_region(link->io.BasePort2, link->io.NumPorts2);
+
+    /* retry registration in case device is still spinning up */
+    for (i = 0; i < 10; i++) {
+	hd = ide_register(io_base, ctl_base, link->irq.AssignedIRQ);
+	if (hd >= 0) break;
+	if (link->io.NumPorts1 == 0x20) {
+	    hd = ide_register(io_base+0x10, ctl_base+0x10,
+			      link->irq.AssignedIRQ);
+	    if (hd >= 0) {
+		io_base += 0x10; ctl_base += 0x10;
+		break;
+	    }
+	}
+	__set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(HZ/10);
+    }
+    
+    if (hd < 0) {
+	printk(KERN_NOTICE "ide_cs: ide_register() at 0x%3x & 0x%3x"
+	       ", irq %u failed\n", io_base, ctl_base,
+	       link->irq.AssignedIRQ);
+	goto failed;
+    }
+
+    MOD_INC_USE_COUNT;
+    info->ndev = 1;
+    sprintf(info->node.dev_name, "hd%c", 'a'+(hd*2));
+    info->node.major = ide_major[hd];
+    info->node.minor = 0;
+    info->hd = hd;
+    link->dev = &info->node;
+    printk(KERN_INFO "ide_cs: %s: Vcc = %d.%d, Vpp = %d.%d\n",
+	   info->node.dev_name, link->conf.Vcc/10, link->conf.Vcc%10,
+	   link->conf.Vpp1/10, link->conf.Vpp1%10);
+
+    link->state &= ~DEV_CONFIG_PENDING;
+    return;
+    
+cs_failed:
+    cs_error(link->handle, last_fn, last_ret);
+failed:
+    ide_release((u_long)link);
+
+} /* ide_config */
+
+/*======================================================================
+
+    After a card is removed, ide_release() will unregister the net
+    device, and release the PCMCIA configuration.  If the device is
+    still open, this will be postponed until it is closed.
+    
+======================================================================*/
+
+void ide_release(u_long arg)
+{
+    dev_link_t *link = (dev_link_t *)arg;
+    ide_info_t *info = link->priv;
+    
+    DEBUG(0, "ide_release(0x%p)\n", link);
+
+    if (info->ndev) {
+	ide_unregister(info->hd);
+	MOD_DEC_USE_COUNT;
+    }
+    info->ndev = 0;
+    link->dev = NULL;
+    
+    CardServices(ReleaseConfiguration, link->handle);
+    CardServices(ReleaseIO, link->handle, &link->io);
+    CardServices(ReleaseIRQ, link->handle, &link->irq);
+    
+    link->state &= ~DEV_CONFIG;
+
+} /* ide_release */
+
+/*======================================================================
+
+    The card status event handler.  Mostly, this schedules other
+    stuff to run after an event is received.  A CARD_REMOVAL event
+    also sets some flags to discourage the ide drivers from
+    talking to the ports.
+    
+======================================================================*/
+
+int ide_event(event_t event, int priority,
+	      event_callback_args_t *args)
+{
+    dev_link_t *link = args->client_data;
+
+    DEBUG(1, "ide_event(0x%06x)\n", event);
+    
+    switch (event) {
+    case CS_EVENT_CARD_REMOVAL:
+	link->state &= ~DEV_PRESENT;
+	if (link->state & DEV_CONFIG) {
+	    link->release.expires = jiffies + HZ/20;
+	    link->state |= DEV_RELEASE_PENDING;
+	    add_timer(&link->release);
+	}
+	break;
+    case CS_EVENT_CARD_INSERTION:
+	link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
+	ide_config(link);
+	break;
+    case CS_EVENT_PM_SUSPEND:
+	link->state |= DEV_SUSPEND;
+	/* Fall through... */
+    case CS_EVENT_RESET_PHYSICAL:
+	if (link->state & DEV_CONFIG)
+	    CardServices(ReleaseConfiguration, link->handle);
+	break;
+    case CS_EVENT_PM_RESUME:
+	link->state &= ~DEV_SUSPEND;
+	/* Fall through... */
+    case CS_EVENT_CARD_RESET:
+	if (DEV_OK(link))
+	    CardServices(RequestConfiguration, link->handle, &link->conf);
+	break;
+    }
+    return 0;
+} /* ide_event */
+
+/*====================================================================*/
+
+static int __init init_ide_cs(void)
+{
+    servinfo_t serv;
+    DEBUG(0, "%s\n", version);
+    CardServices(GetCardServicesInfo, &serv);
+    if (serv.Revision != CS_RELEASE_CODE) {
+	printk(KERN_NOTICE "ide_cs: Card Services release "
+	       "does not match!\n");
+	return -1;
+    }
+    register_pccard_driver(&dev_info, &ide_attach, &ide_detach);
+    return 0;
+}
+
+static void __exit exit_ide_cs(void)
+{
+    DEBUG(0, "ide_cs: unloading\n");
+    unregister_pccard_driver(&dev_info);
+    while (dev_list != NULL)
+	ide_detach(dev_list);
+}
+
+module_init(init_ide_cs);
+module_exit(exit_ide_cs);
diff --git a/drivers/char/digi1.h b/drivers/char/digi1.h
new file mode 100644
index 000000000..184378d23
--- /dev/null
+++ b/drivers/char/digi1.h
@@ -0,0 +1,100 @@
+/*          Definitions for DigiBoard ditty(1) command.                 */
+
+#if !defined(TIOCMODG)
+#define	TIOCMODG	('d'<<8) | 250		/* get modem ctrl state	*/
+#define	TIOCMODS	('d'<<8) | 251		/* set modem ctrl state	*/
+#endif
+
+#if !defined(TIOCMSET)
+#define	TIOCMSET	('d'<<8) | 252		/* set modem ctrl state	*/
+#define	TIOCMGET	('d'<<8) | 253		/* set modem ctrl state	*/
+#endif
+
+#if !defined(TIOCMBIC)
+#define	TIOCMBIC	('d'<<8) | 254		/* set modem ctrl state */
+#define	TIOCMBIS	('d'<<8) | 255		/* set modem ctrl state */
+#endif
+
+#if !defined(TIOCSDTR)
+#define	TIOCSDTR	('e'<<8) | 0		/* set DTR		*/
+#define	TIOCCDTR	('e'<<8) | 1		/* clear DTR		*/
+#endif
+
+/************************************************************************
+ * Ioctl command arguments for DIGI parameters.
+ ************************************************************************/
+#define DIGI_GETA	('e'<<8) | 94		/* Read params		*/
+
+#define DIGI_SETA	('e'<<8) | 95		/* Set params		*/
+#define DIGI_SETAW	('e'<<8) | 96		/* Drain & set params	*/
+#define DIGI_SETAF	('e'<<8) | 97		/* Drain, flush & set params */
+
+#define	DIGI_GETFLOW	('e'<<8) | 99		/* Get startc/stopc flow */
+						/* control characters 	 */
+#define	DIGI_SETFLOW	('e'<<8) | 100		/* Set startc/stopc flow */
+						/* control characters	 */
+#define	DIGI_GETAFLOW	('e'<<8) | 101		/* Get Aux. startc/stopc */
+						/* flow control chars 	 */
+#define	DIGI_SETAFLOW	('e'<<8) | 102		/* Set Aux. startc/stopc */
+						/* flow control chars	 */
+
+#define	DIGI_GETINFO	('e'<<8) | 103		/* Fill in digi_info */
+#define	DIGI_POLLER	('e'<<8) | 104		/* Turn on/off poller */
+#define	DIGI_INIT	('e'<<8) | 105		/* Allow things to run. */
+
+struct	digiflow_struct 
+{
+	unsigned char	startc;				/* flow cntl start char	*/
+	unsigned char	stopc;				/* flow cntl stop char	*/
+};
+
+typedef struct digiflow_struct digiflow_t;
+
+
+/************************************************************************
+ * Values for digi_flags 
+ ************************************************************************/
+#define DIGI_IXON	0x0001		/* Handle IXON in the FEP	*/
+#define DIGI_FAST	0x0002		/* Fast baud rates		*/
+#define RTSPACE		0x0004		/* RTS input flow control	*/
+#define CTSPACE		0x0008		/* CTS output flow control	*/
+#define DSRPACE		0x0010		/* DSR output flow control	*/
+#define DCDPACE		0x0020		/* DCD output flow control	*/
+#define DTRPACE		0x0040		/* DTR input flow control	*/
+#define DIGI_FORCEDCD	0x0100		/* Force carrier		*/
+#define	DIGI_ALTPIN	0x0200		/* Alternate RJ-45 pin config	*/
+#define	DIGI_AIXON	0x0400		/* Aux flow control in fep	*/
+
+
+/************************************************************************
+ * Values for digiDload
+ ************************************************************************/
+#define NORMAL  0
+#define PCI_CTL 1
+
+#define SIZE8  0
+#define SIZE16 1
+#define SIZE32 2
+
+/************************************************************************
+ * Structure used with ioctl commands for DIGI parameters.
+ ************************************************************************/
+struct digi_struct 
+{
+	unsigned short	digi_flags;		/* Flags (see above)	*/
+};
+
+typedef struct digi_struct digi_t;
+
+struct digi_info 
+{
+	unsigned long board;        /* Which board is this ? */
+	unsigned char status;       /* Alive or dead */
+	unsigned char type;         /* see epca.h */
+	unsigned char subtype;      /* For future XEM, XR, etc ... */
+	unsigned short numports;    /* Number of ports configured */
+	unsigned char *port;        /* I/O Address */
+	unsigned char *membase;     /* DPR Address */
+	unsigned char *version;     /* For future ... */
+	unsigned short windowData;  /* For future ... */
+} ;
diff --git a/drivers/char/digiFep1.h b/drivers/char/digiFep1.h
new file mode 100644
index 000000000..c47d7fcb8
--- /dev/null
+++ b/drivers/char/digiFep1.h
@@ -0,0 +1,136 @@
+
+#define CSTART       0x400L
+#define CMAX         0x800L
+#define ISTART       0x800L
+#define IMAX         0xC00L
+#define CIN          0xD10L
+#define GLOBAL       0xD10L
+#define EIN          0xD18L
+#define FEPSTAT      0xD20L
+#define CHANSTRUCT   0x1000L
+#define RXTXBUF      0x4000L
+
+
+struct global_data 
+{
+	volatile ushort cin;
+	volatile ushort cout;
+	volatile ushort cstart;
+	volatile ushort cmax;
+	volatile ushort ein;
+	volatile ushort eout;
+	volatile ushort istart;
+	volatile ushort imax;
+};
+
+
+struct board_chan 
+{
+	int filler1; 
+	int filler2;
+	volatile ushort tseg;
+	volatile ushort tin;
+	volatile ushort tout;
+	volatile ushort tmax;
+	
+	volatile ushort rseg;
+	volatile ushort rin;
+	volatile ushort rout;
+	volatile ushort rmax;
+	
+	volatile ushort tlow;
+	volatile ushort rlow;
+	volatile ushort rhigh;
+	volatile ushort incr;
+	
+	volatile ushort etime;
+	volatile ushort edelay;
+	volatile unchar *dev;
+	
+	volatile ushort iflag;
+	volatile ushort oflag;
+	volatile ushort cflag;
+	volatile ushort gmask;
+	
+	volatile ushort col;
+	volatile ushort delay;
+	volatile ushort imask;
+	volatile ushort tflush;
+
+	int filler3;
+	int filler4;
+	int filler5;
+	int filler6;
+	
+	volatile unchar num;
+	volatile unchar ract;
+	volatile unchar bstat;
+	volatile unchar tbusy;
+	volatile unchar iempty;
+	volatile unchar ilow;
+	volatile unchar idata;
+	volatile unchar eflag;
+	
+	volatile unchar tflag;
+	volatile unchar rflag;
+	volatile unchar xmask;
+	volatile unchar xval;
+	volatile unchar mstat;
+	volatile unchar mchange;
+	volatile unchar mint;
+	volatile unchar lstat;
+
+	volatile unchar mtran;
+	volatile unchar orun;
+	volatile unchar startca;
+	volatile unchar stopca;
+	volatile unchar startc;
+	volatile unchar stopc;
+	volatile unchar vnext;
+	volatile unchar hflow;
+
+	volatile unchar fillc;
+	volatile unchar ochar;
+	volatile unchar omask;
+
+	unchar filler7;
+	unchar filler8[28];
+}; 
+
+
+#define SRXLWATER      0xE0
+#define SRXHWATER      0xE1
+#define STOUT          0xE2
+#define PAUSETX        0xE3
+#define RESUMETX       0xE4
+#define SAUXONOFFC     0xE6
+#define SENDBREAK      0xE8
+#define SETMODEM       0xE9
+#define SETIFLAGS      0xEA
+#define SONOFFC        0xEB
+#define STXLWATER      0xEC
+#define PAUSERX        0xEE
+#define RESUMERX       0xEF
+#define SETBUFFER      0xF2
+#define SETCOOKED      0xF3
+#define SETHFLOW       0xF4
+#define SETCTRLFLAGS   0xF5
+#define SETVNEXT       0xF6
+
+
+
+#define BREAK_IND        0x01
+#define LOWTX_IND        0x02
+#define EMPTYTX_IND      0x04
+#define DATA_IND         0x08
+#define MODEMCHG_IND     0x20
+
+#define FEP_HUPCL  0002000
+#if 0
+#define RTS   0x02
+#define CD    0x08
+#define DSR   0x10
+#define CTS   0x20
+#define RI    0x40
+#define DTR   0x80
+#endif
diff --git a/drivers/char/digiPCI.h b/drivers/char/digiPCI.h
new file mode 100644
index 000000000..6ca7819e5
--- /dev/null
+++ b/drivers/char/digiPCI.h
@@ -0,0 +1,42 @@
+/*************************************************************************
+ * Defines and structure definitions for PCI BIOS Interface 
+ *************************************************************************/
+#define	PCIMAX  32		/* maximum number of PCI boards */
+
+
+#define	PCI_VENDOR_DIGI		0x114F
+#define	PCI_DEVICE_EPC		0x0002
+#define	PCI_DEVICE_RIGHTSWITCH 0x0003  /* For testing */
+#define	PCI_DEVICE_XEM		0x0004
+#define	PCI_DEVICE_XR		0x0005
+#define	PCI_DEVICE_CX		0x0006
+#define	PCI_DEVICE_XRJ		0x0009   /* Jupiter boards with */
+#define	PCI_DEVICE_EPCJ		0x000a   /* PLX 9060 chip for PCI  */
+
+
+/*
+ * On the PCI boards, there is no IO space allocated 
+ * The I/O registers will be in the first 3 bytes of the   
+ * upper 2MB of the 4MB memory space.  The board memory 
+ * will be mapped into the low 2MB of the 4MB memory space 
+ */
+
+/* Potential location of PCI Bios from E0000 to FFFFF*/
+#define PCI_BIOS_SIZE		0x00020000	
+
+/* Size of Memory and I/O for PCI (4MB) */
+#define PCI_RAM_SIZE		0x00400000	
+
+/* Size of Memory (2MB) */
+#define PCI_MEM_SIZE		0x00200000	
+
+/* Offset of I/0 in Memory (2MB) */
+#define PCI_IO_OFFSET 		0x00200000	
+
+#define MEMOUTB(basemem, pnum, setmemval)  *(caddr_t)((basemem) + ( PCI_IO_OFFSET | pnum << 4 | pnum )) = (setmemval)
+#define MEMINB(basemem, pnum)  *(caddr_t)((basemem) + (PCI_IO_OFFSET | pnum << 4 | pnum ))   /* for PCI I/O */
+
+
+
+
+
diff --git a/drivers/char/epca.h b/drivers/char/epca.h
new file mode 100644
index 000000000..18cedf37c
--- /dev/null
+++ b/drivers/char/epca.h
@@ -0,0 +1,170 @@
+#define XEMPORTS    0xC02
+#define XEPORTS     0xC22
+
+#define MAX_ALLOC   0x100
+
+#define MAXBOARDS   12
+#define FEPCODESEG  0x0200L
+#define FEPCODE     0x2000L
+#define BIOSCODE    0xf800L
+
+#define MISCGLOBAL  0x0C00L
+#define NPORT       0x0C22L
+#define MBOX        0x0C40L
+#define PORTBASE    0x0C90L
+
+/* Begin code defines used for epca_setup */
+
+#define INVALID_BOARD_TYPE   0x1
+#define INVALID_NUM_PORTS    0x2
+#define INVALID_MEM_BASE     0x4
+#define INVALID_PORT_BASE    0x8
+#define INVALID_BOARD_STATUS 0x10
+#define INVALID_ALTPIN       0x20
+
+/* End code defines used for epca_setup */
+
+
+#define FEPCLR      0x00
+#define FEPMEM      0x02
+#define FEPRST      0x04
+#define FEPINT      0x08
+#define	FEPMASK     0x0e
+#define	FEPWIN      0x80
+
+#define PCXE    0
+#define PCXEVE  1
+#define PCXEM   2   
+#define EISAXEM 3
+#define PC64XE  4
+#define PCXI    5
+#define PCIXEM  7
+#define PCICX   8
+#define PCIXR   9
+#define PCIXRJ  10
+#define EPCA_NUM_TYPES 6
+
+
+static char *board_desc[] = 
+{
+	"PC/Xe",
+	"PC/Xeve",
+	"PC/Xem",
+	"EISA/Xem",
+	"PC/64Xe",
+	"PC/Xi",
+	"unknown",
+	"PCI/Xem",
+	"PCI/CX",
+	"PCI/Xr",
+	"PCI/Xrj",
+};
+
+#define STARTC      021
+#define STOPC       023
+#define IAIXON      0x2000
+
+
+#define TXSTOPPED  0x1
+#define LOWWAIT    0x2
+#define EMPTYWAIT  0x4
+#define RXSTOPPED  0x8
+#define TXBUSY     0x10
+
+#define DISABLED   0
+#define ENABLED    1
+#define OFF        0
+#define ON         1
+
+#define FEPTIMEOUT 200000  
+#define SERIAL_TYPE_NORMAL  1
+#define SERIAL_TYPE_CALLOUT 2
+#define SERIAL_TYPE_INFO    3
+#define EPCA_EVENT_HANGUP   1
+#define EPCA_MAGIC          0x5c6df104L
+
+struct channel 
+{
+	long   magic;
+	unchar boardnum;
+	unchar channelnum;
+	unchar omodem;         /* FEP output modem status     */
+	unchar imodem;         /* FEP input modem status      */
+	unchar modemfake;      /* Modem values to be forced   */
+	unchar modem;          /* Force values                */
+	unchar hflow;
+	unchar dsr;
+	unchar dcd;
+	unchar m_rts ; 		/* The bits used in whatever FEP */
+	unchar m_dcd ;		/* is indiginous to this board to */
+	unchar m_dsr ;		/* represent each of the physical */
+	unchar m_cts ;		/* handshake lines */
+	unchar m_ri ;
+	unchar m_dtr ;
+	unchar stopc;
+	unchar startc;
+	unchar stopca;
+	unchar startca;
+	unchar fepstopc;
+	unchar fepstartc;
+	unchar fepstopca;
+	unchar fepstartca;
+	unchar txwin;
+	unchar rxwin;
+	ushort fepiflag;
+	ushort fepcflag;
+	ushort fepoflag;
+	ushort txbufhead;
+	ushort txbufsize;
+	ushort rxbufhead;
+	ushort rxbufsize;
+	int    close_delay;
+	int    count;
+	int    blocked_open;
+	int    event;
+	int    asyncflags;
+	uint   dev;
+	long   session;
+	long   pgrp;
+	ulong  statusflags;
+	ulong  c_iflag;
+	ulong  c_cflag;
+	ulong  c_lflag;
+	ulong  c_oflag;
+	unchar *txptr;
+	unchar *rxptr;
+	unchar *tmp_buf;
+	struct board_info           *board;
+	volatile struct board_chan  *brdchan;
+	struct digi_struct          digiext;
+	struct tty_struct           *tty;
+	struct termios              normal_termios;
+	struct termios              callout_termios;
+	wait_queue_head_t           open_wait;
+	wait_queue_head_t           close_wait;
+	struct tq_struct            tqueue;
+	volatile struct global_data *mailbox;
+};
+
+struct board_info	
+{
+	unchar status;
+	unchar type;
+	unchar altpin;
+	ushort numports;
+	unchar *port;
+	unchar *membase;
+	unchar *re_map_port;
+	unchar *re_map_membase;
+	ulong  memory_seg;
+	void ( * memwinon )	(struct board_info *, unsigned int) ;
+	void ( * memwinoff ) 	(struct board_info *, unsigned int) ;
+	void ( * globalwinon )	(struct channel *) ;
+	void ( * txwinon ) 	(struct channel *) ;
+	void ( * rxwinon )	(struct channel *) ;
+	void ( * memoff )	(struct channel *) ;
+	void ( * assertgwinon )	(struct channel *) ;
+	void ( * assertmemoff )	(struct channel *) ;
+	unchar poller_inhibited ;
+};
+
diff --git a/drivers/char/epcaconfig.h b/drivers/char/epcaconfig.h
new file mode 100644
index 000000000..55dec0670
--- /dev/null
+++ b/drivers/char/epcaconfig.h
@@ -0,0 +1,7 @@
+#define NUMCARDS 0
+#define NBDEVS 0
+
+struct board_info static_boards[NUMCARDS]={
+};
+
+/* DO NOT HAND EDIT THIS FILE! */
diff --git a/drivers/char/tuner-3036.c b/drivers/char/tuner-3036.c
new file mode 100644
index 000000000..807ae339b
--- /dev/null
+++ b/drivers/char/tuner-3036.c
@@ -0,0 +1,227 @@
+/*
+ * Driver for Philips SAB3036 "CITAC" tuner control chip.
+ *
+ * Author: Phil Blundell <philb@gnu.org>
+ *
+ * The SAB3036 is just about different enough from the chips that
+ * tuner.c copes with to make it not worth the effort to crowbar
+ * the support into that file.  So instead we have a separate driver. 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/malloc.h>
+#include <linux/version.h>
+#include <linux/init.h>
+
+#include <linux/i2c.h>
+#include <linux/videodev.h>
+
+#include "tuner.h"
+
+static int debug;	/* insmod parameter */
+static int this_adap;
+
+static struct i2c_client client_template;
+
+/* Addresses to scan */
+static unsigned short normal_i2c[] = {I2C_CLIENT_END};
+static unsigned short normal_i2c_range[] = {0x60, 0x61, I2C_CLIENT_END};
+static unsigned short probe[2]        = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short probe_range[2]  = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short ignore[2]       = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short ignore_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
+static unsigned short force[2]        = { I2C_CLIENT_END, I2C_CLIENT_END };
+
+static struct i2c_client_address_data addr_data = {
+	normal_i2c, normal_i2c_range, 
+	probe, probe_range, 
+	ignore, ignore_range, 
+	force
+};
+
+/* ---------------------------------------------------------------------- */
+
+static unsigned char
+tuner_getstatus (struct i2c_client *c)
+{
+	unsigned char byte;
+	if (i2c_master_recv(c, &byte, 1) != 1)
+		printk(KERN_ERR "tuner-3036: I/O error.\n");
+	return byte;
+}
+
+#define TUNER_FL        0x80
+
+static int 
+tuner_islocked (struct i2c_client *c)
+{
+        return (tuner_getstatus(c) & TUNER_FL);
+}
+
+/* ---------------------------------------------------------------------- */
+
+static void 
+set_tv_freq(struct i2c_client *c, int freq)
+{
+	u16 div = ((freq * 20) / 16);
+	unsigned long give_up = jiffies + HZ;
+	unsigned char buffer[2];
+
+	if (debug)
+		printk(KERN_DEBUG "tuner: setting frequency %dMHz, divisor %x\n", freq / 16, div);
+	
+	/* Select high tuning current */
+	buffer[0] = 0x29;
+	buffer[1] = 0x3e;
+
+	if (i2c_master_send(c, buffer, 2) != 2)
+		printk("tuner: i2c i/o error 1\n");
+	
+	buffer[0] = 0x80 | ((div>>8) & 0x7f);
+	buffer[1] = div & 0xff;
+
+	if (i2c_master_send(c, buffer, 2) != 2)
+		printk("tuner: i2c i/o error 2\n");
+	
+	while (!tuner_islocked(c) && time_before(jiffies, give_up))
+		schedule();
+	       
+	if (!tuner_islocked(c))
+		printk(KERN_WARNING "tuner: failed to achieve PLL lock\n");
+	
+	/* Select low tuning current and engage AFC */
+	buffer[0] = 0x29;
+	buffer[1] = 0xb2;
+
+	if (i2c_master_send(c, buffer, 2) != 2)
+		printk("tuner: i2c i/o error 3\n");
+
+	if (debug)
+		printk(KERN_DEBUG "tuner: status %02x\n", tuner_getstatus(c));
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int 
+tuner_attach(struct i2c_adapter *adap, int addr,
+	     unsigned short flags, int kind)
+{
+	static unsigned char buffer[] = { 0x29, 0x32, 0x2a, 0, 0x2b, 0 };
+
+	struct i2c_client *client;
+
+	if (this_adap > 0)
+		return -1;
+	this_adap++;
+	
+        client_template.adapter = adap;
+        client_template.addr = addr;
+
+	client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
+        if (client == NULL)
+                return -ENOMEM;
+        memcpy(client, &client_template, sizeof(struct i2c_client));
+
+	printk("tuner: SAB3036 found, status %02x\n", tuner_getstatus(client));
+
+        i2c_attach_client(client);
+	MOD_INC_USE_COUNT;
+
+	if (i2c_master_send(client, buffer, 2) != 2)
+		printk("tuner: i2c i/o error 1\n");
+	if (i2c_master_send(client, buffer+2, 2) != 2)
+		printk("tuner: i2c i/o error 2\n");
+	if (i2c_master_send(client, buffer+4, 2) != 2)
+		printk("tuner: i2c i/o error 3\n");
+	return 0;
+}
+
+static int 
+tuner_detach(struct i2c_client *c)
+{
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+static int 
+tuner_command(struct i2c_client *client, unsigned int cmd, void *arg)
+{
+	int *iarg = (int*)arg;
+
+	switch (cmd) 
+	{
+		case TUNER_SET_TVFREQ:
+			set_tv_freq(client, *iarg);
+			break;
+	    
+		default:
+			return -EINVAL;
+	}
+	return 0;
+}
+
+static int 
+tuner_probe(struct i2c_adapter *adap)
+{
+	this_adap = 0;
+	if (adap->id == (I2C_ALGO_BIT | I2C_HW_B_LP))
+		return i2c_probe(adap, &addr_data, tuner_attach);
+	return 0;
+}
+
+/* ----------------------------------------------------------------------- */
+
+static struct i2c_driver 
+i2c_driver_tuner = 
+{
+	"sab3036",		/* name       */
+	I2C_DRIVERID_SAB3036,	/* ID         */
+        I2C_DF_NOTIFY,
+	tuner_probe,
+	tuner_detach,
+	tuner_command
+};
+
+static struct i2c_client client_template =
+{
+        "SAB3036",		/* name       */
+        -1,
+        0,
+        0,
+        NULL,
+        &i2c_driver_tuner
+};
+
+EXPORT_NO_SYMBOLS;
+
+int __init
+tuner3036_init(void)
+{
+	i2c_add_driver(&i2c_driver_tuner);
+	return 0;
+}
+
+void __exit
+tuner3036_exit(void)
+{
+	i2c_del_driver(&i2c_driver_tuner);
+}
+
+MODULE_DESCRIPTION("SAB3036 tuner driver");
+MODULE_AUTHOR("Philip Blundell <philb@gnu.org>");
+MODULE_PARM(debug,"i");
+MODULE_PARM_DESC(debug,"Enable debugging output");
+
+module_init(tuner3036_init);
+module_exit(tuner3036_exit);
diff --git a/drivers/net/bonding.c b/drivers/net/bonding.c
new file mode 100644
index 000000000..f1a4526d4
--- /dev/null
+++ b/drivers/net/bonding.c
@@ -0,0 +1,350 @@
+/*
+ * originally based on the dummy device.
+ *
+ * Copyright 1999, Thomas Davis, tadavis@lbl.gov.  
+ * Licensed under the GPL. Based on dummy.c, and eql.c devices.
+ *
+ * bond.c: a bonding/etherchannel/sun trunking net driver
+ *
+ * This is useful to talk to a Cisco 5500, running Etherchannel, aka:
+ *	Linux Channel Bonding
+ *	Sun Trunking (Solaris)
+ *
+ * How it works:
+ *    ifconfig bond0 ipaddress netmask up
+ *      will setup a network device, with an ip address.  No mac address 
+ *	will be assigned at this time.  The hw mac address will come from 
+ *	the first slave bonded to the channel.  All slaves will then use 
+ *	this hw mac address.
+ *
+ *    ifconfig bond0 down
+ *         will release all slaves, marking them as down.
+ *
+ *    ifenslave bond0 eth0
+ *	will attache eth0 to bond0 as a slave.  eth0 hw mac address will either
+ *	a: be used as initial mac address
+ *	b: if a hw mac address already is there, eth0's hw mac address 
+ *	   will then  be set from bond0.
+ *
+ * v0.1 - first working version.
+ * v0.2 - changed stats to be calculated by summing slaves stats.
+ * 
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <linux/ioport.h>
+#include <linux/in.h>
+#include <linux/malloc.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <linux/if_bonding.h>
+
+typedef struct slave
+{
+	struct slave *next;
+	struct slave *prev;
+	struct net_device *dev;
+} slave_t;
+
+typedef struct bonding
+{
+	slave_t *next;
+	slave_t *prev;
+	struct net_device *master;
+
+	slave_t *current_slave;
+	struct net_device_stats stats;
+} bonding_t;
+
+
+static int bond_xmit(struct sk_buff *skb, struct net_device *dev);
+static struct net_device_stats *bond_get_stats(struct net_device *dev);
+
+static struct net_device *this_bond;
+
+static int bond_open(struct net_device *dev)
+{
+	MOD_INC_USE_COUNT;
+	return 0;
+}
+
+static int bond_close(struct net_device *master)
+{
+	bonding_t *bond = master->priv;
+	slave_t *slave;
+
+	while ((slave = bond->next) != (slave_t*)bond) {
+
+		spin_lock_bh(&master->xmit_lock);
+		slave->next->prev = slave->prev;
+		slave->prev->next = slave->next;
+		bond->current_slave = (slave_t*)bond;
+		spin_unlock_bh(&master->xmit_lock);
+
+		netdev_set_master(slave->dev, NULL);
+
+		kfree(slave);
+	}
+
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+/* Fake multicast ability.
+
+   NB. It is possible and necessary to make it true one, otherwise
+   the device is not functional.
+ */
+static void bond_set_multicast_list(struct net_device *dev)
+{
+}
+
+static int bond_enslave(struct net_device *master, struct net_device *dev)
+{
+	int err;
+	bonding_t *bond = master->priv;
+	slave_t *slave;
+
+	if (dev->type != master->type)
+		return -ENODEV;
+
+	if ((slave = kmalloc(sizeof(slave_t), GFP_KERNEL)) == NULL)
+		return -ENOMEM;
+
+	memset(slave, 0, sizeof(slave_t));
+
+	err = netdev_set_master(dev, master);
+	if (err) {
+		kfree(slave);
+		return err;
+	}
+
+	slave->dev = dev;
+
+	spin_lock_bh(&master->xmit_lock);
+
+	dev_hold(dev);
+
+	slave->prev = bond->prev;
+	slave->next = (slave_t*)bond;
+	slave->prev->next = slave;
+	slave->next->prev = slave;
+
+	spin_unlock_bh(&master->xmit_lock);
+
+	MOD_INC_USE_COUNT;
+	return 0;
+}
+
+static int bond_release(struct net_device *master, struct net_device *dev)
+{
+	bonding_t *bond = master->priv;
+	slave_t *slave;
+
+	if (dev->master != master)
+		return -EINVAL;
+
+	netdev_set_master(dev, NULL);
+
+	for (slave = bond->next; slave != (slave_t*)bond; slave = slave->next) {
+		if (slave->dev == dev) {
+			spin_lock_bh(&master->xmit_lock);
+			if (bond->current_slave == slave)
+				bond->current_slave = slave->next;
+			slave->next->prev = slave->prev;
+			slave->prev->next = slave->next;
+			spin_unlock_bh(&master->xmit_lock);
+
+			kfree(slave);
+			dev_put(dev);
+			MOD_DEC_USE_COUNT;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/* It is pretty silly, SIOCSIFHWADDR exists to make this. */
+
+static int bond_sethwaddr(struct net_device *master, struct net_device *slave)
+{
+	memcpy(master->dev_addr, slave->dev_addr, slave->addr_len);
+	return 0;
+}
+
+static int bond_ioctl(struct net_device *master, struct ifreq *ifr, int cmd)
+{
+	struct net_device *slave = __dev_get_by_name(ifr->ifr_slave);
+
+	if (slave == NULL)
+		return -ENODEV;
+
+	switch (cmd) {
+	case BOND_ENSLAVE:
+		return bond_enslave(master, slave);
+	case BOND_RELEASE:
+		return bond_release(master, slave);
+	case BOND_SETHWADDR:
+		return bond_sethwaddr(master, slave);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int bond_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	struct net_device *slave = ptr;
+
+	if (this_bond == NULL ||
+	    this_bond == slave ||
+	    this_bond != slave->master)
+		return NOTIFY_DONE;
+
+	switch (event) {
+	case NETDEV_UNREGISTER:
+		bond_release(this_bond, slave);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+struct notifier_block bond_netdev_notifier={
+	bond_event,
+	NULL,
+	0
+};
+
+int __init bond_init(struct net_device *dev)
+{
+	bonding_t *bond;
+
+	bond = kmalloc(sizeof(struct bonding), GFP_KERNEL);
+	if (bond == NULL)
+		return -ENOMEM;
+
+	memset(bond, 0, sizeof(struct bonding));
+	bond->next = (slave_t*)bond;
+	bond->prev = (slave_t*)bond;
+	bond->master = dev;
+	bond->current_slave = (slave_t*)bond;
+	dev->priv = bond;
+
+	/* Initialize the device structure. */
+	dev->hard_start_xmit = bond_xmit;
+	dev->get_stats	= bond_get_stats;
+	dev->open = bond_open;
+	dev->stop = bond_close;
+	dev->set_multicast_list = bond_set_multicast_list;
+	dev->do_ioctl = bond_ioctl;
+
+	/* Fill in the fields of the device structure with ethernet-generic 
+	   values. */
+	ether_setup(dev);
+	dev->tx_queue_len = 0;
+	dev->flags |= IFF_MASTER;
+
+	this_bond = dev;
+
+	register_netdevice_notifier(&bond_netdev_notifier);
+
+	return 0;
+}
+
+static int bond_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	bonding_t *bond = dev->priv;
+	slave_t *slave, *start_at;
+	int pkt_len = skb->len;
+
+	slave = start_at = bond->current_slave;
+
+	do {
+		if (slave == (slave_t*)bond)
+			continue;
+
+		if (netif_running(slave->dev) && netif_carrier_ok(dev)) {
+			bond->current_slave = slave->next;
+			skb->dev = slave->dev;
+
+			if (dev_queue_xmit(skb)) {
+				bond->stats.tx_dropped++;
+			} else {
+				bond->stats.tx_packets++;
+				bond->stats.tx_bytes += pkt_len;
+			}
+			return 0;
+		}
+	} while ((slave = slave->next) != start_at);
+
+	bond->stats.tx_dropped++;
+	kfree_skb(skb);
+	return 0;
+}
+
+static struct net_device_stats *bond_get_stats(struct net_device *dev)
+{
+	bonding_t *bond = dev->priv;
+
+	return &bond->stats;
+}
+
+#ifdef MODULE
+
+static char bond_name[16];
+
+static struct net_device dev_bond = {
+		bond_name, 	/* Needs to be writeable */
+		0, 0, 0, 0,
+	 	0x0, 0,
+	 	0, 0, 0, NULL, bond_init };
+
+int init_module(void)
+{
+	/* Find a name for this unit */
+	int err=dev_alloc_name(&dev_bond,"bond%d");
+
+	if (err<0)
+		return err;
+
+	if (register_netdev(&dev_bond) != 0)
+		return -EIO;
+
+	return 0;
+}
+
+void cleanup_module(void)
+{
+	unregister_netdevice_notifier(&bond_netdev_notifier);
+
+	unregister_netdev(&dev_bond);
+
+	kfree(dev_bond.priv);
+}
+#endif /* MODULE */
+
+/*
+ * Local variables:
+ *  c-indent-level: 8
+ *  c-basic-offset: 8
+ *  tab-width: 8
+ * End:
+ */
diff --git a/drivers/usb/pegasus.c b/drivers/usb/pegasus.c
new file mode 100644
index 000000000..1e752dc75
--- /dev/null
+++ b/drivers/usb/pegasus.c
@@ -0,0 +1,579 @@
+/*
+**
+**	Pegasus: USB 10/100Mbps/HomePNA (1Mbps) Controller
+**
+**	Copyleft (L) 1999 Petko Manolov - Petkan (petkan@spct.net)
+** 	
+**	Distribute under GPL version 2 or later.
+*/
+
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/malloc.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+
+#include "usb.h"
+
+#if LINUX_VERSION_CODE<0x2032d || !defined(__KERNEL__) || !defined(__OPTIMIZE__)
+#error You can not compile this driver on this kernel with this C options!
+#endif
+
+
+#define	ADMTEK_VENDOR_ID	0x07a6
+#define	ADMTEK_HPNA_PEGASUS	0x0986
+
+#define	HPNA_MTU		1500
+#define MAX_MTU			1536
+
+#define	TX_TIMEOUT		(HZ*5)
+#define	SOMETHING		(jiffies + TX_TIMEOUT)
+
+
+static const char version[] = "pegasus.c: v0.2.27 2000/02/29 Written by Petko Manolov (petkan@spct.net)\n";
+
+
+typedef struct usb_hpna
+{
+	struct usb_device	*usb_dev;
+	struct net_device	*net_dev;
+	int			present;
+	int			active;
+	void			*irq_handler;
+	struct list_head	list;
+	struct net_device_stats	stats;
+	spinlock_t		hpna_lock;
+	struct timer_list	timer;
+
+	unsigned int		rx_pipe;
+	unsigned char *		rx_buff;
+	urb_t 			rx_urb;
+
+	unsigned int		tx_pipe;
+	unsigned char *		tx_buff;
+	urb_t 			tx_urb;
+	struct sk_buff *	tx_skbuff;
+
+	__u8			intr_ival;
+	unsigned int		intr_pipe;
+	unsigned char 		intr_buff[8];
+	urb_t 			intr_urb;
+} usb_hpna_t;
+
+
+usb_hpna_t	usb_dev_hpna;
+static int	loopback = 0;
+int		multicast_filter_limit = 32;
+static LIST_HEAD(hpna_list);
+
+
+MODULE_AUTHOR("Petko Manolov <petkan@spct.net>");
+MODULE_DESCRIPTION("ADMtek \"Pegasus\" USB Ethernet driver");
+MODULE_PARM(loopback, "i");
+
+
+
+/*** vendor specific commands ***/
+static __inline__ int	hpna_get_registers( struct usb_device *dev, __u16 indx, __u16 size, void *data )
+{
+	return	usb_control_msg(dev, usb_rcvctrlpipe(dev,0), 0xf0, 0xc0, 0,
+				indx, data, size, HZ);
+}
+
+
+static __inline__ int	hpna_set_register( struct usb_device *dev, __u16 indx, __u8 value )
+{
+	__u8	data = value;
+	return	usb_control_msg(dev, usb_sndctrlpipe(dev,0), 0xf1, 0x40,
+				data, indx, &data, 1, HZ);
+}
+
+
+static __inline__ int	hpna_set_registers( struct usb_device *dev, __u16 indx, __u16 size, void *data )
+{
+	return	usb_control_msg(dev, usb_sndctrlpipe(dev,0), 0xf1, 0x40, 0,
+				indx, data, size, HZ);
+}
+
+
+static int read_phy_word( struct usb_device *dev, __u8 index, __u16 *regdata )
+{
+	int	i;
+	__u8	data[4];
+
+	data[0] = 1;
+	data[1] = 0;
+	data[2] = 0;
+	data[3] = 0x40 + index;
+	hpna_set_registers( dev, 0x25, 4, data );
+	for ( i=0; i<100; i++ ) {
+		hpna_get_registers( dev, 0x25, 4, data );
+		if ( data[3] & 0x80 ) {
+			*regdata = *(__u16 *)(data+1);
+			return	0;
+		}
+		udelay(100);
+	}
+	warn("read_phy_word() failed");
+	return	1;
+}
+
+
+static int write_phy_word( struct usb_device *dev, __u8 index, __u16 regdata )
+{
+	int	i;
+	__u8	data[4];
+
+	data[0] = 1;
+	data[1] = regdata;
+	data[2] = regdata >> 8;
+	data[3] = 0x20 + index;
+	hpna_set_registers( dev, 0x25, 4, data );
+	for ( i=0; i<100; i++ ) {
+		hpna_get_registers( dev, 0x28, 1, data );
+		if ( data[0] & 0x80 ) {
+			return	0;
+		}
+		udelay(100);
+	}
+	warn("write_phy_word() failed");
+	return	1;
+}
+
+
+int read_srom_word( struct usb_device *dev, __u8 index, __u16 *retdata)
+{
+	int	i;
+	__u8	data[4];
+
+	data[0] = index;
+	data[1] = data[2] = 0;
+	data[3] = 0x02;
+	hpna_set_registers(dev, 0x20, 4, data);
+	for ( i=0; i<100; i++ ) {
+		hpna_get_registers(dev, 0x23, 1, data);
+		if ( data[0] & 4 ) {
+			hpna_get_registers(dev, 0x21, 2, data);
+			*retdata = *(__u16 *)data;
+			return	0;		
+		}
+	}
+	warn("read_srom_word() failed");
+	return	1;
+}
+/*** end ***/
+
+
+
+
+int get_node_id( struct usb_device *dev, __u8 *id )
+{
+	int	i;
+
+	for ( i=0; i<3; i++ ) {
+		if ( read_srom_word(dev, i, (__u16 *)&id[i*2] ) )
+			return	1;
+	}
+	return	0;
+}
+
+
+static int reset_mac( struct usb_device *dev )
+{
+	__u8	data = 0x8;
+	int	i;
+	
+	hpna_set_register( dev, 1, 0x08 );
+	for ( i=0; i<100; i++ ) {
+		hpna_get_registers( dev, 1, 1, &data);
+		if ( !(data & 0x08) ) {
+			if ( loopback & 1 )
+				return	0;
+			else if ( loopback & 2 ) {
+				write_phy_word( dev, 0, 0x4000 );
+				/*return	0;*/
+			}
+			hpna_set_register( dev, 0x7e, 0x24 );
+			hpna_set_register( dev, 0x7e, 0x27 );
+			return	0;
+		}
+	}
+	return 1;
+}
+
+
+int start_net( struct net_device *dev, struct usb_device *usb_dev )
+{
+	__u16	partmedia, temp;
+	__u8	node_id[6];
+	__u8	data[4];
+	
+	if ( get_node_id(usb_dev, node_id) )
+		return	1;
+	hpna_set_registers(usb_dev, 0x10, 6, node_id);
+	memcpy(dev->dev_addr, node_id, 6);
+	if ( read_phy_word(usb_dev, 1, &temp) )
+		return	2;
+	if ( !(temp & 4) ) {
+		if ( loopback )
+			goto ok;
+		err("link NOT established - %x", temp);
+		return	3;
+	}
+ok:
+	if ( read_phy_word(usb_dev, 5, &partmedia) )
+		return	4;
+	temp = partmedia;
+	partmedia &= 0x1f;
+	if ( partmedia != 1 ) {
+		err("party FAIL %x", temp);
+		return	5;
+	}
+	partmedia = temp;
+	if ( partmedia & 0x100 )
+		data[1] = 0x30;
+	else {
+		if ( partmedia & 0x80 )
+			data[1] = 0x10;
+		else 
+			data[1] = 0;
+	}
+	
+	data[0] = 0xc9;
+	data[2] = (loopback & 1) ? 0x08 : 0x00; 
+	
+	hpna_set_registers(usb_dev, 0, 3, data);
+	
+	return	0;
+}
+
+
+static void hpna_read_irq( purb_t urb )
+{
+	struct net_device *net_dev = urb->context;
+	usb_hpna_t *hpna = net_dev->priv;
+	int	count = urb->actual_length, res;
+	int	rx_status = *(int *)(hpna->rx_buff + count - 4);
+
+
+	if ( urb->status ) {
+		info( "%s: RX status %d\n", net_dev->name, urb->status );
+		goto goon;
+	}
+
+	if ( !count )
+		goto goon;
+/*	if ( rx_status & 0x00010000 )
+		goto goon;
+*/	
+	if ( rx_status & 0x000e0000 ) {
+		dbg("%s: error receiving packet %x",
+			net_dev->name, rx_status & 0xe0000);
+		hpna->stats.rx_errors++;
+		if(rx_status & 0x060000) hpna->stats.rx_length_errors++;
+		if(rx_status & 0x080000) hpna->stats.rx_crc_errors++;
+		if(rx_status & 0x100000) hpna->stats.rx_frame_errors++;
+	} else {
+		struct sk_buff	*skb;
+		__u16 		pkt_len = (rx_status & 0xfff) - 8;
+
+
+		if((skb = dev_alloc_skb(pkt_len+2)) != NULL ) {
+			skb->dev = net_dev;
+			skb_reserve(skb, 2);
+			eth_copy_and_sum(skb, hpna->rx_buff, pkt_len, 0);
+			skb_put(skb, pkt_len);
+		} else
+			goto	goon;
+		skb->protocol = eth_type_trans(skb, net_dev);
+		netif_rx(skb);
+		hpna->stats.rx_packets++;
+		hpna->stats.rx_bytes += pkt_len;
+	}
+goon:
+	if ( (res = usb_submit_urb( &hpna->rx_urb )) )
+		warn("failed rx_urb %d", res);
+}
+
+
+static void hpna_irq( urb_t *urb)
+{
+	if( urb->status ) {
+		__u8	*d = urb->transfer_buffer;
+		printk("txst0 %x, txst1 %x, rxst %x, rxlst0 %x, rxlst1 %x, wakest %x",
+			d[0], d[1], d[2], d[3], d[4], d[5] );
+	}
+}
+
+
+static void hpna_write_irq( purb_t urb )
+{
+	struct net_device *net_dev = urb->context;
+	usb_hpna_t *hpna = net_dev->priv;
+
+
+	spin_lock( &hpna->hpna_lock );
+	
+	if ( urb->status ) 
+		info("%s: TX status %d\n", net_dev->name, urb->status);
+	netif_wake_queue( net_dev );
+
+	spin_unlock( &hpna->hpna_lock );
+}
+
+
+static void tx_timeout( struct net_device *dev )
+{
+	usb_hpna_t	*hpna = dev->priv;
+
+	warn( "%s: Tx timed out. Reseting...", dev->name );
+	hpna->stats.tx_errors++;
+	dev->trans_start = jiffies;
+	netif_wake_queue( dev );
+}
+
+
+static int hpna_start_xmit( struct sk_buff *skb, struct net_device *net_dev )
+{
+	usb_hpna_t	*hpna = (usb_hpna_t *)net_dev->priv;
+	int		count = skb->len+2 % 64 ? skb->len+2 : skb->len+3;
+	int		res;
+
+	spin_lock( &hpna->hpna_lock );
+
+	netif_stop_queue( net_dev );
+	((__u16 *)hpna->tx_buff)[0] = skb->len;
+	memcpy(hpna->tx_buff+2, skb->data, skb->len);
+	(&hpna->tx_urb)->transfer_buffer_length = count;
+	if ( (res = usb_submit_urb( &hpna->tx_urb )) ) {
+		warn("failed tx_urb %d", res);
+		hpna->stats.tx_errors++;
+		netif_start_queue( net_dev );
+	} else {
+		hpna->stats.tx_packets++;
+		hpna->stats.tx_bytes += skb->len;
+		net_dev->trans_start = jiffies;
+	}
+	dev_kfree_skb( skb );
+	spin_unlock( &hpna->hpna_lock );
+	return	0;
+}
+
+
+static struct net_device_stats *hpna_netdev_stats( struct net_device *dev )
+{
+	return	&((usb_hpna_t *)dev->priv)->stats;
+}
+
+static int hpna_open( struct net_device *net_dev )
+{
+	usb_hpna_t *hpna = (usb_hpna_t *)net_dev->priv;
+	int	res;
+
+	if ( hpna->active )
+		return	-EBUSY;
+	else
+		hpna->active = 1;
+
+	if ( start_net(net_dev, hpna->usb_dev) ) {
+		err("can't start_net()");
+		return	-EIO;
+	}
+
+	if ( (res = usb_submit_urb( &hpna->rx_urb )) )
+		warn("failed rx_urb %d", res);
+
+/*	usb_submit_urb( &hpna->intr_urb );*/
+	netif_start_queue( net_dev );
+
+	MOD_INC_USE_COUNT;
+
+	return 0;
+}
+
+
+static int hpna_close( struct net_device *net_dev )
+{
+	usb_hpna_t	*hpna = net_dev->priv;
+
+
+	netif_stop_queue( net_dev );
+
+	usb_unlink_urb( &hpna->rx_urb );
+	usb_unlink_urb( &hpna->tx_urb );
+/*	usb_unlink_urb( hpna->intr_urb );*/
+
+	hpna->active = 0;
+
+	MOD_DEC_USE_COUNT;
+
+	return 0;
+}
+
+
+static int hpna_ioctl( struct net_device *dev, struct ifreq *rq, int cmd )
+{
+	__u16	*data = (__u16 *)&rq->ifr_data;
+	usb_hpna_t	*hpna = dev->priv;
+
+	switch( cmd ) {
+		case SIOCDEVPRIVATE: 
+			data[0] = 1;
+		case SIOCDEVPRIVATE+1:
+			read_phy_word(hpna->usb_dev, data[1] & 0x1f, &data[3]);
+			return	0;
+		case SIOCDEVPRIVATE+2:
+			if ( !capable(CAP_NET_ADMIN) )
+				return	-EPERM;
+			write_phy_word(hpna->usb_dev, data[1] & 0x1f, data[2]);
+			return	0;
+		default:
+			return	-EOPNOTSUPP;
+	}
+}
+
+
+static void set_rx_mode( struct net_device *net_dev )
+{
+	usb_hpna_t	*hpna=net_dev->priv;
+
+	netif_stop_queue( net_dev );
+	
+	if ( net_dev->flags & IFF_PROMISC ) {
+		info("%s: Promiscuous mode enabled", net_dev->name);
+		hpna_set_register( hpna->usb_dev, 2, 0x04 );
+	} else if ((net_dev->mc_count > multicast_filter_limit) ||
+			(net_dev->flags & IFF_ALLMULTI)) {
+		hpna_set_register(hpna->usb_dev, 0, 0xfa);
+		hpna_set_register(hpna->usb_dev, 2, 0);
+	} else {
+		dbg("%s: set Rx mode", net_dev->name);
+	}
+
+	netif_wake_queue( net_dev );
+}
+
+
+static void * usb_hpna_probe( struct usb_device *dev, unsigned int ifnum )
+{
+	struct net_device 		*net_dev;
+	usb_hpna_t			*hpna = &usb_dev_hpna;
+
+
+
+	if ( dev->descriptor.idVendor != ADMTEK_VENDOR_ID ||
+	     dev->descriptor.idProduct != ADMTEK_HPNA_PEGASUS ) {
+		return	NULL;
+	}
+
+	printk("USB HPNA Pegasus found\n");
+
+	if ( usb_set_configuration(dev, dev->config[0].bConfigurationValue)) {
+		err("usb_set_configuration() failed");
+		return NULL;
+	}
+
+	hpna->usb_dev = dev;
+
+	hpna->rx_pipe = usb_rcvbulkpipe(hpna->usb_dev, 1);
+	hpna->tx_pipe = usb_sndbulkpipe(hpna->usb_dev, 2);
+	hpna->intr_pipe = usb_rcvintpipe(hpna->usb_dev, 0);
+
+	if ( reset_mac(dev) ) {
+		err("can't reset MAC");
+	}
+
+	hpna->present = 1;
+
+	if(!(hpna->rx_buff=kmalloc(MAX_MTU, GFP_KERNEL))) {
+		err("not enough mem for out buff");
+		return	NULL;
+	}
+	if(!(hpna->tx_buff=kmalloc(MAX_MTU, GFP_KERNEL))) {
+		kfree_s(hpna->rx_buff, MAX_MTU);
+		err("not enough mem for out buff");
+		return	NULL;
+	}
+
+	net_dev = init_etherdev( 0, 0 );
+	hpna->net_dev = net_dev;
+	net_dev->priv = hpna;
+	net_dev->open = hpna_open;
+	net_dev->stop = hpna_close;
+	net_dev->watchdog_timeo = TX_TIMEOUT;
+	net_dev->tx_timeout = tx_timeout;
+	net_dev->do_ioctl = hpna_ioctl; 
+	net_dev->hard_start_xmit = hpna_start_xmit;
+	net_dev->set_multicast_list = set_rx_mode;
+	net_dev->get_stats = hpna_netdev_stats; 
+	net_dev->mtu = HPNA_MTU;
+	hpna->hpna_lock = SPIN_LOCK_UNLOCKED;
+	
+	FILL_BULK_URB( &hpna->rx_urb, hpna->usb_dev, hpna->rx_pipe, 
+			hpna->rx_buff, MAX_MTU, hpna_read_irq, net_dev );
+	FILL_BULK_URB( &hpna->tx_urb, hpna->usb_dev, hpna->tx_pipe, 
+			hpna->tx_buff, MAX_MTU, hpna_write_irq, net_dev );
+	FILL_INT_URB( &hpna->intr_urb, hpna->usb_dev, hpna->intr_pipe,
+			hpna->intr_buff, 8, hpna_irq, net_dev, 250 );
+	
+/*	list_add( &hpna->list, &hpna_list );*/
+	
+	return	net_dev; 
+}
+
+
+static void usb_hpna_disconnect( struct usb_device *dev, void *ptr )
+{
+	struct net_device	*net_dev = ptr;
+	struct usb_hpna		*hpna = net_dev->priv;
+
+
+	if ( net_dev->flags & IFF_UP )
+		dev_close(net_dev);
+	
+	unregister_netdev( net_dev );
+
+	if ( !hpna ) /* should never happen */
+		return;
+		
+	usb_unlink_urb( &hpna->rx_urb );
+	usb_unlink_urb( &hpna->tx_urb );
+/*	usb_unlink_urb( &hpna->intr_urb );*/
+	kfree_s(hpna->rx_buff, MAX_MTU);
+	kfree_s(hpna->tx_buff, MAX_MTU);
+
+	hpna->usb_dev = NULL;
+	hpna->present = 0;
+
+	printk("USB HPNA disconnected\n");
+}
+
+
+static struct usb_driver usb_hpna_driver = {
+	"ADMtek \"Pegasus\" USB Ethernet",
+	usb_hpna_probe,
+	usb_hpna_disconnect,
+	{NULL, NULL}
+};
+
+
+
+static int  __init start_hpna( void )
+{
+	printk( version );
+	return	usb_register( &usb_hpna_driver );
+}
+
+
+static void __exit stop_hpna( void )
+{
+	usb_deregister( &usb_hpna_driver );
+}
+
+
+module_init( start_hpna );
+module_exit( stop_hpna );
diff --git a/drivers/usb/rio500.c b/drivers/usb/rio500.c
new file mode 100644
index 000000000..e25ba03d3
--- /dev/null
+++ b/drivers/usb/rio500.c
@@ -0,0 +1,455 @@
+/* -*- linux-c -*- */
+
+/* 
+ * Driver for USB Rio 500
+ *
+ * Cesar Miquel (miquel@df.uba.ar)
+ * 
+ * based on hp_scanner.c by David E. Nelson (dnelson@jump.net)
+ * 
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Based upon mouse.c (Brad Keryan) and printer.c (Michael Gee).
+ *
+ * */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/miscdevice.h>
+#include <linux/random.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/malloc.h>
+#include <linux/spinlock.h>
+
+#include "usb.h"
+
+#include "rio500_usb.h"
+
+#define RIO_MINOR   64
+
+/* stall/wait timeout for rio */
+#define NAK_TIMEOUT (HZ)
+
+#define IBUF_SIZE 128
+
+/* Size of the rio buffer */
+#define OBUF_SIZE 0x10000
+
+struct rio_usb_data {
+        struct usb_device *rio_dev;     /* init: probe_rio */
+        unsigned int ifnum;             /* Interface number of the USB device */
+        int isopen;                     /* nz if open */
+        int present;                    /* Device is present on the bus */
+        char *obuf, *ibuf;              /* transfer buffers */
+        char bulk_in_ep, bulk_out_ep;   /* Endpoint assignments */
+        wait_queue_head_t wait_q;       /* for timeouts */
+};
+
+static struct rio_usb_data rio_instance;
+
+static int open_rio(struct inode *inode, struct file *file)
+{
+	struct rio_usb_data *rio = &rio_instance;
+
+	if (rio->isopen || !rio->present) {
+		return -EBUSY;
+	}
+	rio->isopen = 1;
+
+	init_waitqueue_head(&rio->wait_q);
+
+	MOD_INC_USE_COUNT;
+
+	info("Rio opened.");
+
+	return 0;
+}
+
+static int close_rio(struct inode *inode, struct file *file)
+{
+	struct rio_usb_data *rio = &rio_instance;
+
+	rio->isopen = 0;
+
+	MOD_DEC_USE_COUNT;
+
+	info("Rio closed.");
+	return 0;
+}
+
+static int
+ioctl_rio(struct inode *inode, struct file *file, unsigned int cmd,
+	  unsigned long arg)
+{
+	struct RioCommand rio_cmd;
+	struct rio_usb_data *rio = &rio_instance;
+	void *data;
+	unsigned char *buffer;
+	int result, requesttype;
+	int retries;
+
+        /* Sanity check to make sure rio is connected, powered, etc */
+        if ( rio == NULL ||
+             rio->present == 0 ||
+             rio->rio_dev == NULL )
+          return -1;
+
+	switch (cmd) {
+	case RIO_RECV_COMMAND:
+		data = (void *) arg;
+		if (data == NULL)
+			break;
+		copy_from_user_ret(&rio_cmd, data, sizeof(struct RioCommand),
+				   -EFAULT);
+		if (rio_cmd.length > PAGE_SIZE)
+			return -EINVAL;
+		buffer = (unsigned char *) __get_free_page(GFP_KERNEL);
+		if (buffer == NULL)
+			return -ENOMEM;
+		copy_from_user_ret(buffer, rio_cmd.buffer, rio_cmd.length,
+				   -EFAULT);
+
+		requesttype = rio_cmd.requesttype | USB_DIR_IN |
+		    USB_TYPE_VENDOR | USB_RECIP_DEVICE;
+		dbg
+		    ("sending command:reqtype=%0x req=%0x value=%0x index=%0x len=%0x",
+		     requesttype, rio_cmd.request, rio_cmd.value,
+		     rio_cmd.index, rio_cmd.length);
+		/* Send rio control message */
+		retries = 3;
+		while (retries) {
+			result = usb_control_msg(rio->rio_dev,
+						 usb_rcvctrlpipe(rio-> rio_dev, 0),
+						 rio_cmd.request,
+						 requesttype,
+						 rio_cmd.value,
+						 rio_cmd.index, buffer,
+						 rio_cmd.length,
+						 rio_cmd.timeout);
+			if (result == -ETIMEDOUT)
+				retries--;
+			else if (result < 0) {
+				err("Error executing ioctrl. code = %d",
+				     le32_to_cpu(result));
+				retries = 0;
+			} else {
+				dbg("Executed ioctl. Result = %d (data=%04x)",
+				     le32_to_cpu(result),
+				     le32_to_cpu(*((long *) buffer)));
+				copy_to_user_ret(rio_cmd.buffer, buffer,
+						 rio_cmd.length, -EFAULT);
+				retries = 0;
+			}
+
+			/* rio_cmd.buffer contains a raw stream of single byte
+			   data which has been returned from rio.  Data is
+			   interpreted at application level.  For data that
+			   will be cast to data types longer than 1 byte, data
+			   will be little_endian and will potentially need to
+			   be swapped at the app level */
+
+		}
+		free_page((unsigned long) buffer);
+		break;
+
+	case RIO_SEND_COMMAND:
+		data = (void *) arg;
+		if (data == NULL)
+			break;
+		copy_from_user_ret(&rio_cmd, data, sizeof(struct RioCommand),
+				   -EFAULT);
+		if (rio_cmd.length > PAGE_SIZE)
+			return -EINVAL;
+		buffer = (unsigned char *) __get_free_page(GFP_KERNEL);
+		if (buffer == NULL)
+			return -ENOMEM;
+		copy_from_user_ret(buffer, rio_cmd.buffer, rio_cmd.length,
+				   -EFAULT);
+
+		requesttype = rio_cmd.requesttype | USB_DIR_OUT |
+		    USB_TYPE_VENDOR | USB_RECIP_DEVICE;
+		dbg("sending command: reqtype=%0x req=%0x value=%0x index=%0x len=%0x",
+		     requesttype, rio_cmd.request, rio_cmd.value,
+		     rio_cmd.index, rio_cmd.length);
+		/* Send rio control message */
+		retries = 3;
+		while (retries) {
+			result = usb_control_msg(rio->rio_dev,
+						 usb_sndctrlpipe(rio-> rio_dev, 0),
+						 rio_cmd.request,
+						 requesttype,
+						 rio_cmd.value,
+						 rio_cmd.index, buffer,
+						 rio_cmd.length,
+						 rio_cmd.timeout);
+			if (result == -ETIMEDOUT)
+				retries--;
+			else if (result < 0) {
+				err("Error executing ioctrl. code = %d",
+				     le32_to_cpu(result));
+				retries = 0;
+			} else {
+				dbg("Executed ioctl. Result = %d",
+				       le32_to_cpu(result));
+				retries = 0;
+
+			}
+
+		}
+		free_page((unsigned long) buffer);
+		break;
+
+	default:
+		return -ENOIOCTLCMD;
+		break;
+	}
+
+	return 0;
+}
+
+static ssize_t
+write_rio(struct file *file, const char *buffer,
+	  size_t count, loff_t * ppos)
+{
+	struct rio_usb_data *rio = &rio_instance;
+
+	unsigned long copy_size;
+	unsigned long bytes_written = 0;
+	unsigned int partial;
+
+	int result = 0;
+	int maxretry;
+
+        /* Sanity check to make sure rio is connected, powered, etc */
+        if ( rio == NULL ||
+             rio->present == 0 ||
+             rio->rio_dev == NULL )
+          return -1;
+
+	do {
+		unsigned long thistime;
+		char *obuf = rio->obuf;
+
+		thistime = copy_size =
+		    (count >= OBUF_SIZE) ? OBUF_SIZE : count;
+		if (copy_from_user(rio->obuf, buffer, copy_size))
+			return -EFAULT;
+		maxretry = 5;
+		while (thistime) {
+			if (!rio->rio_dev)
+				return -ENODEV;
+			if (signal_pending(current)) {
+				return bytes_written ? bytes_written : -EINTR;
+			}
+
+			result = usb_bulk_msg(rio->rio_dev,
+					 usb_sndbulkpipe(rio->rio_dev, 2),
+					 obuf, thistime, &partial, 5 * HZ);
+
+			dbg("write stats: result:%d thistime:%lu partial:%u",
+			     result, thistime, partial);
+
+			if (result == USB_ST_TIMEOUT) {	/* NAK - so hold for a while */
+				if (!maxretry--) {
+					return -ETIME;
+				}
+				interruptible_sleep_on_timeout(&rio-> wait_q, NAK_TIMEOUT);
+				continue;
+			} else if (!result & partial) {
+				obuf += partial;
+				thistime -= partial;
+			} else
+				break;
+		};
+		if (result) {
+			err("Write Whoops - %x", result);
+			return -EIO;
+		}
+		bytes_written += copy_size;
+		count -= copy_size;
+		buffer += copy_size;
+	} while (count > 0);
+
+	return bytes_written ? bytes_written : -EIO;
+}
+
+static ssize_t
+read_rio(struct file *file, char *buffer, size_t count, loff_t * ppos)
+{
+	struct rio_usb_data *rio = &rio_instance;
+	ssize_t read_count;
+	unsigned int partial;
+	int this_read;
+	int result;
+	int maxretry = 10;
+	char *ibuf = rio->ibuf;
+
+        /* Sanity check to make sure rio is connected, powered, etc */
+        if ( rio == NULL ||
+             rio->present == 0 ||
+             rio->rio_dev == NULL )
+          return -1;
+
+	read_count = 0;
+
+	while (count > 0) {
+		if (signal_pending(current)) {
+			return read_count ? read_count : -EINTR;
+		}
+		if (!rio->rio_dev)
+			return -ENODEV;
+		this_read = (count >= IBUF_SIZE) ? IBUF_SIZE : count;
+
+		result = usb_bulk_msg(rio->rio_dev,
+				      usb_rcvbulkpipe(rio->rio_dev, 1),
+				      ibuf, this_read, &partial,
+				      (int) (HZ * .1));
+
+		dbg(KERN_DEBUG "read stats: result:%d this_read:%u partial:%u",
+		       result, this_read, partial);
+
+		if (partial) {
+			count = this_read = partial;
+		} else if (result == USB_ST_TIMEOUT || result == 15) {	/* FIXME: 15 ??? */
+			if (!maxretry--) {
+				err("read_rio: maxretry timeout");
+				return -ETIME;
+			}
+			interruptible_sleep_on_timeout(&rio->wait_q,
+						       NAK_TIMEOUT);
+			continue;
+		} else if (result != USB_ST_DATAUNDERRUN) {
+			err("Read Whoops - result:%u partial:%u this_read:%u",
+			     result, partial, this_read);
+			return -EIO;
+		} else {
+			return (0);
+		}
+
+		if (this_read) {
+			if (copy_to_user(buffer, ibuf, this_read))
+				return -EFAULT;
+			count -= this_read;
+			read_count += this_read;
+			buffer += this_read;
+		}
+	}
+	return read_count;
+}
+
+static void *probe_rio(struct usb_device *dev, unsigned int ifnum)
+{
+	struct rio_usb_data *rio = &rio_instance;
+
+	if (dev->descriptor.idVendor != 0x841) {
+		return NULL;
+	}
+
+	if (dev->descriptor.idProduct != 0x1 /* RIO 500 */ ) {
+		warn(KERN_INFO "Rio player model not supported/tested.");
+		return NULL;
+	}
+
+	info("USB Rio found at address %d", dev->devnum);
+
+	rio->present = 1;
+	rio->rio_dev = dev;
+
+	if (!(rio->obuf = (char *) kmalloc(OBUF_SIZE, GFP_KERNEL))) {
+		err("probe_rio: Not enough memory for the output buffer");
+		return NULL;
+	}
+	dbg("probe_rio: obuf address:%p", rio->obuf);
+
+	if (!(rio->ibuf = (char *) kmalloc(IBUF_SIZE, GFP_KERNEL))) {
+		err("probe_rio: Not enough memory for the input buffer");
+		kfree(rio->obuf);
+		return NULL;
+	}
+	dbg("probe_rio: ibuf address:%p", rio->ibuf);
+
+	return rio;
+}
+
+static void disconnect_rio(struct usb_device *dev, void *ptr)
+{
+	struct rio_usb_data *rio = (struct rio_usb_data *) ptr;
+
+	if (rio->isopen) {
+		rio->isopen = 0;
+		/* better let it finish - the release will do whats needed */
+		rio->rio_dev = NULL;
+		return;
+	}
+	kfree(rio->ibuf);
+	kfree(rio->obuf);
+
+	info("USB Rio disconnected.");
+
+	rio->present = 0;
+}
+
+static struct
+file_operations usb_rio_fops = {
+	NULL,			/* seek */
+	read_rio,
+	write_rio,
+	NULL,			/* readdir */
+	NULL,			/* poll */
+	ioctl_rio,		/* ioctl */
+	NULL,			/* mmap */
+	open_rio,
+	NULL,			/* flush */
+	close_rio,
+	NULL,
+	NULL,			/* fasync */
+};
+
+static struct
+usb_driver rio_driver = {
+	"rio500",
+	probe_rio,
+	disconnect_rio,
+	{NULL, NULL},
+	&usb_rio_fops,
+	RIO_MINOR
+};
+
+int usb_rio_init(void)
+{
+	if (usb_register(&rio_driver) < 0)
+		return -1;
+
+	info("USB Rio support registered.");
+	return 0;
+}
+
+
+void usb_rio_cleanup(void)
+{
+	struct rio_usb_data *rio = &rio_instance;
+
+	rio->present = 0;
+	usb_deregister(&rio_driver);
+
+
+}
+
+module_init(usb_rio_init);
+module_exit(usb_rio_cleanup);
+
diff --git a/drivers/usb/rio500_usb.h b/drivers/usb/rio500_usb.h
new file mode 100644
index 000000000..9fc712f3d
--- /dev/null
+++ b/drivers/usb/rio500_usb.h
@@ -0,0 +1,37 @@
+/*  ----------------------------------------------------------------------
+
+    Copyright (C) 2000  Cesar Miquel  (miquel@df.uba.ar)
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+    ---------------------------------------------------------------------- */
+
+
+
+#define RIO_SEND_COMMAND			0x1
+#define RIO_RECV_COMMAND			0x2
+
+#define RIO_DIR_OUT               	        0x0
+#define RIO_DIR_IN				0x1
+
+struct RioCommand {
+	short length;
+	int request;
+	int requesttype;
+	int value;
+	int index;
+	void *buffer;
+	int timeout;
+};
diff --git a/drivers/usb/wacom.c b/drivers/usb/wacom.c
new file mode 100644
index 000000000..c67d30a60
--- /dev/null
+++ b/drivers/usb/wacom.c
@@ -0,0 +1,286 @@
+/*
+ *  wacom.c  Version 0.3
+ *
+ *  Copyright (c) 2000 Vojtech Pavlik		<vojtech@suse.cz>
+ *  Copyright (c) 2000 Andreas Bach Aaen	<abach@stofanet.dk>
+ *  Copyright (c) 2000 Clifford Wolf		<clifford@clifford.at>
+ *
+ *  USB Wacom Graphire and Wacom Intuos tablet support
+ *
+ *  Sponsored by SuSE
+ *
+ *  ChangeLog:
+ *      v0.1 (vp)  - Initial release
+ *      v0.2 (aba) - Support for all buttons / combinations
+ *      v0.3 (vp)  - Support for Intuos added
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or 
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * 
+ * Should you need to contact me, the author, you can do so either by
+ * e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
+ * Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
+ */
+
+#include <linux/kernel.h>
+#include <linux/malloc.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include "usb.h"
+
+MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
+
+/*
+ * Wacom Graphire packet:
+ *
+ * The input report:
+ * 
+ * byte 0: report ID (2)
+ * byte 1: bit7 	mouse/pen/rubber near
+ *         bit5-6	0 - pen, 1 - rubber, 2 - mouse
+ * 	   bit4		1 ?
+ *         bit3		0 ?
+ *         bit2		mouse middle button / pen button2
+ *         bit1		mouse right button / pen button1
+ *         bit0		mouse left button / pen tip / rubber
+ * byte 2: X low bits
+ * byte 3: X high bits
+ * byte 4: Y low bits
+ * byte 5: Y high bits
+ * byte 6: pen pressure low bits / mouse wheel
+ * byte 7: pen presure high bits / mouse distance
+ * 
+ * There are also two single-byte feature reports (2 and 3).
+ *
+ * Resolution:
+ * X: 0 - 10206
+ * Y: 0 - 7422
+ * 
+ * (0,0) is upper left corner
+ *
+ * Wacom Intuos packet:
+ *
+ *  byte 0: report ID (2)
+ *  byte 1: bit7	1 ?
+ *          bit6	tilt (pressure?) data valid
+ *          bit5	near
+ *          bit4 	0 ?
+ *          bit3	0 ?
+ *          bit2	pen button
+ *          bit1	first packet (contains other infos)
+ *          bit0	0 ?
+ *  byte 2: X high bits
+ *  byte 3: X low bits
+ *  byte 4: Y high bits
+ *  byte 5: Y low bits
+ *  byte 6: bits 0-7:  pressure (bits 2-9)
+ *  byte 7: bits 6-7:  pressure (bits 0-1)
+ *  byte 7: bits 0-5:  X tilt  (bits 1-6)
+ *  byte 8: bit    7:  X tilt  (bit  0)
+ *  byte 8: bits 0-6:  Y tilt  (bits 0-6)
+ *  byte 9: ?
+ */
+
+#define USB_VENDOR_ID_WACOM		0x056a
+#define USB_DEVICE_ID_WACOM_GRAPHIRE	0x0010
+#define USB_DEVICE_ID_WACOM_INTUOS	0x0021
+
+struct wacom {
+	signed char data[12];
+	struct input_dev dev;
+	struct urb irq;
+};
+
+static void wacom_graphire_irq(struct urb *urb)
+{
+	struct wacom *wacom = urb->context;
+	unsigned char *data = wacom->data;
+	struct input_dev *dev = &wacom->dev;
+
+	if (urb->status) return;
+
+	if (data[0] != 2)
+		dbg("received unknown report #%d", data[0]);
+
+        if ( data[1] & 0x80 ) {
+	        input_report_abs(dev, ABS_X, data[2] | ((__u32)data[3] << 8));
+	        input_report_abs(dev, ABS_Y, 7422 - (data[4] | ((__u32)data[5] << 8)));
+	}
+
+	switch ((data[1] >> 5) & 3) {
+
+		case 0:	/* Pen */
+			input_report_btn(dev, BTN_TOOL_PEN, data[1] & 0x80);
+			input_report_btn(dev, BTN_TOUCH, data[1] & 0x01);
+			input_report_btn(dev, BTN_STYLUS, data[1] & 0x02);
+			input_report_btn(dev, BTN_STYLUS2, data[1] & 0x04);
+			input_report_abs(dev, ABS_PRESSURE, data[6] | ((__u32)data[7] << 8));
+			break;
+
+		case 1: /* Rubber */
+	                input_report_btn(dev, BTN_TOOL_RUBBER, data[1] & 0x80);
+			input_report_btn(dev, BTN_TOUCH, data[1] & 0x01);
+			input_report_btn(dev, BTN_STYLUS, data[1] & 0x02);
+			input_report_btn(dev, BTN_STYLUS2, data[1] & 0x04);
+			input_report_abs(dev, ABS_PRESSURE, data[6] | ((__u32)data[7] << 8));
+			break;
+
+		case 2: /* Mouse */
+	                input_report_btn(dev, BTN_TOOL_MOUSE, data[7] > 24);
+			input_report_btn(dev, BTN_LEFT, data[1] & 0x01);
+			input_report_btn(dev, BTN_RIGHT, data[1] & 0x02);
+			input_report_btn(dev, BTN_MIDDLE, data[1] & 0x04);
+			input_report_abs(dev, ABS_DISTANCE, data[7]);
+			input_report_rel(dev, REL_WHEEL, (signed char) data[6]);
+			break;
+	}
+}
+
+static void wacom_intuos_irq(struct urb *urb)
+{
+	struct wacom *wacom = urb->context;
+	unsigned char *data = wacom->data;
+	struct input_dev *dev = &wacom->dev;
+	unsigned int t;
+
+	if (urb->status) return;
+
+	if (data[0] != 2)
+		dbg("received unknown report #%d", data[0]);
+
+	if (data[1] & 0x02) /* First record, weird data */
+		return;
+	
+	if (data[1] & 0x20) { /* Near */
+		input_report_abs(dev, ABS_X, (((unsigned int) data[2]) << 8) | data[3]);
+		input_report_abs(dev, ABS_Y, 16240 - ((((unsigned int) data[4]) << 8) | data[5]));
+	}
+
+	input_report_btn(dev, BTN_TOOL_PEN, data[1] & 0x20);
+	input_report_btn(dev, BTN_STYLUS, data[1] & 0x04);
+
+	t = (((unsigned int) data[6]) << 2) | ((data[7] & 0xC0) >> 6);
+
+	input_report_btn(dev, BTN_TOUCH, t > 10);
+	input_report_abs(dev, ABS_PRESSURE, t);
+
+	if (data[1] & 0x40) { /* Tilt data */
+		input_report_abs(dev, ABS_TILT_X, ((((unsigned int) data[7]) & 0x3f) << 1) | ((data[8] & 0x80) >> 7));
+		input_report_abs(dev, ABS_TILT_Y, data[8] & 0x7f);
+	}
+}
+
+static void *wacom_probe(struct usb_device *dev, unsigned int ifnum)
+{
+	struct usb_endpoint_descriptor *endpoint;
+	struct wacom *wacom;
+	char *name;
+
+	if (dev->descriptor.idVendor != USB_VENDOR_ID_WACOM ||
+	   (dev->descriptor.idProduct != USB_DEVICE_ID_WACOM_GRAPHIRE &&
+	    dev->descriptor.idProduct != USB_DEVICE_ID_WACOM_INTUOS))
+		return NULL;
+
+	endpoint = dev->config[0].interface[ifnum].altsetting[0].endpoint + 0;
+
+	if (!(wacom = kmalloc(sizeof(struct wacom), GFP_KERNEL))) return NULL;
+	memset(wacom, 0, sizeof(struct wacom));
+
+	switch (dev->descriptor.idProduct) {
+
+		case USB_DEVICE_ID_WACOM_GRAPHIRE:
+
+			wacom->dev.evbit[0] |= BIT(EV_KEY) | BIT(EV_REL) | BIT(EV_ABS);
+			wacom->dev.keybit[LONG(BTN_MOUSE)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT) | BIT(BTN_MIDDLE);
+			wacom->dev.keybit[LONG(BTN_DIGI)] |= BIT(BTN_TOOL_PEN) | BIT(BTN_TOOL_RUBBER) | BIT(BTN_TOOL_MOUSE);
+			wacom->dev.keybit[LONG(BTN_DIGI)] |= BIT(BTN_TOUCH) | BIT(BTN_STYLUS) | BIT(BTN_STYLUS2);
+			wacom->dev.relbit[0] |= BIT(REL_WHEEL);
+			wacom->dev.absbit[0] |= BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE) | BIT(ABS_DISTANCE);
+
+			wacom->dev.absmax[ABS_X] = 10206;
+			wacom->dev.absmax[ABS_Y] = 7422;
+			wacom->dev.absmax[ABS_PRESSURE] = 511;
+			wacom->dev.absmax[ABS_DISTANCE] = 32;
+
+			FILL_INT_URB(&wacom->irq, dev, usb_rcvintpipe(dev, endpoint->bEndpointAddress),
+					wacom->data, 8, wacom_graphire_irq, wacom, endpoint->bInterval);
+
+			name = "Graphire";
+			break;
+
+		case USB_DEVICE_ID_WACOM_INTUOS:
+
+			wacom->dev.evbit[0] |= BIT(EV_KEY) | BIT(EV_ABS);
+			wacom->dev.keybit[LONG(BTN_DIGI)] |= BIT(BTN_TOOL_PEN) | BIT(BTN_TOUCH) | BIT(BTN_STYLUS);
+			wacom->dev.absbit[0] |= BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE);
+			wacom->dev.absbit[0] |= BIT(ABS_TILT_X) | BIT(ABS_TILT_Y);
+
+			wacom->dev.absmax[ABS_X] = 20320;
+			wacom->dev.absmax[ABS_Y] = 16240;
+			wacom->dev.absmax[ABS_PRESSURE] = 1024;
+			wacom->dev.absmax[ABS_TILT_X] = 127;
+			wacom->dev.absmax[ABS_TILT_Y] = 127;
+
+			FILL_INT_URB(&wacom->irq, dev, usb_rcvintpipe(dev, endpoint->bEndpointAddress),
+					wacom->data, 8, wacom_intuos_irq, wacom, endpoint->bInterval);
+
+			name = "Intuos";
+			break;
+
+		default:
+			return NULL;
+	}
+
+	if (usb_submit_urb(&wacom->irq)) {
+		kfree(wacom);
+		return NULL;
+	}
+
+	input_register_device(&wacom->dev);
+
+	printk(KERN_INFO "input%d: Wacom %s\n", wacom->dev.number, name);
+
+	return wacom;
+}
+
+static void wacom_disconnect(struct usb_device *dev, void *ptr)
+{
+	struct wacom *wacom = ptr;
+	usb_unlink_urb(&wacom->irq);
+	input_unregister_device(&wacom->dev);
+	kfree(wacom);
+}
+
+static struct usb_driver wacom_driver = {
+	name:		"wacom",
+	probe:		wacom_probe,
+	disconnect:	wacom_disconnect,
+};
+
+static int __init wacom_init(void)
+{
+	usb_register(&wacom_driver);
+	return 0;
+}
+
+static void __exit wacom_exit(void)
+{
+	usb_deregister(&wacom_driver);
+}
+
+module_init(wacom_init);
+module_exit(wacom_exit);
diff --git a/drivers/video/riva/Makefile b/drivers/video/riva/Makefile
new file mode 100644
index 000000000..87502e25c
--- /dev/null
+++ b/drivers/video/riva/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the Riva framebuffer driver
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+# Note 2! The CFLAGS definitions are now in the main makefile...
+
+O_TARGET := rivafb.o
+O_OBJS   := fbdev.o riva_hw.o
+M_OBJS   := $(O_TARGET)
+
+include $(TOPDIR)/Rules.make
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
new file mode 100644
index 000000000..4e8c4e9d4
--- /dev/null
+++ b/drivers/video/riva/fbdev.c
@@ -0,0 +1,1705 @@
+/*
+ * linux/drivers/video/rivafb.c - nVidia RIVA 128/TNT/TNT2 fb driver
+ *
+ * Copyright 1999 Jeff Garzik <jgarzik@mandrakesoft.com>
+ *
+ * Contributors:
+ *
+ *	Ani Joshi:  Lots of debugging and cleanup work, really helped
+ *	get the driver going
+ *
+ *	Ferenc Bakonyi:  Bug fixes, cleanup, modularization
+ *
+ * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
+ * Includes riva_hw.c from nVidia, see copyright below.
+ * KGI code provided the basis for state storage, init, and mode switching.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file README.legal in the main directory of this archive
+ * for more details.
+ */
+
+/* version number of this driver */
+#define RIVAFB_VERSION "0.7.0"
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/selection.h>
+#include <linux/tty.h>
+#include <linux/malloc.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <video/fbcon.h>
+
+#include "riva_hw.h"
+#include "nv4ref.h"
+#include "nvreg.h"
+#include "../vga.h"
+#include <video/fbcon-cfb4.h>
+#include <video/fbcon-cfb8.h>
+#include <video/fbcon-cfb16.h>
+#include <video/fbcon-cfb32.h>
+
+#ifndef CONFIG_PCI		/* sanity check */
+#error This driver requires PCI support.
+#endif
+
+/*****************************************************************
+ *
+ * various helpful macros and constants
+ *
+ */
+
+/* #define RIVAFBDEBUG */
+#ifdef RIVAFBDEBUG
+#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+#ifndef RIVA_NDEBUG
+#define assert(expr) \
+	if(!(expr)) { \
+        printk( "Assertion failed! %s,%s,%s,line=%d\n",\
+        #expr,__FILE__,__FUNCTION__,__LINE__); \
+	*(int*)0 = 0; \
+        }
+#else
+#define assert(expr)
+#endif
+
+/* GGI compatibility macros */
+#define io_out8			outb
+#define io_in8			inb
+#define NUM_SEQ_REGS		0x05
+#define NUM_CRT_REGS		0x41
+#define NUM_GRC_REGS		0x09
+#define NUM_ATC_REGS		0x15
+
+#define PFX "rivafb: "
+
+#define CNVT_TOHW(val,width)	((((val)<<(width))+0x7FFF-(val))>>16)
+
+/* macro that allows you to set overflow bits */
+#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
+#define SetBit(n)		(1<<(n))
+#define Set8Bits(value)		((value)&0xff)
+
+
+enum riva_chips {
+	CH_RIVA_128 = 0,
+	CH_RIVA_TNT,
+	CH_RIVA_TNT2,
+	CH_RIVA_UTNT2,	/* UTNT2 */
+	CH_RIVA_VTNT2,	/* VTNT2 */
+	CH_RIVA_ITNT2,	/* ITNT2 */
+};
+
+
+/* directly indexed by riva_chips enum, above */
+static struct riva_chip_info {
+	const char *name;
+	unsigned arch_rev;
+} riva_chip_info[] __devinitdata = {
+	{ "RIVA-128", 3 },
+	{ "RIVA-TNT", 4 },
+	{ "RIVA-TNT2", 5 },
+	{ "RIVA-UTNT2", 5 },
+	{ "RIVA-VTNT2", 5 },
+	{ "RIVA-ITNT2", 5 },
+};
+
+
+static struct pci_device_id rivafb_pci_tbl[] __devinitdata = {
+	{ PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 },
+	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT },
+	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 },
+	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 },
+	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
+	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 },
+	{ 0, }, /* terminate list */
+};
+MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
+
+
+/* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
+ * From KGI originally. */
+struct riva_regs {
+	u8 attr[NUM_ATC_REGS];
+	u8 crtc[NUM_CRT_REGS];
+	u8 gra[NUM_GRC_REGS];
+	u8 seq[NUM_SEQ_REGS];
+	u8 misc_output;
+	RIVA_HW_STATE ext;
+};
+
+
+/*
+ * describes the state of a Riva board
+ */
+struct rivafb_par {
+	struct riva_regs state;	/* state of hw board */
+	__u32 visual;		/* FB_VISUAL_xxx */
+	unsigned depth;		/* bpp of current mode */
+};
+
+typedef struct {
+	unsigned char red, green, blue, transp;
+} riva_cfb8_cmap_t;
+
+
+
+struct rivafb_info;
+struct rivafb_info {
+	struct fb_info info;	/* kernel framebuffer info */
+
+	RIVA_HW_INST riva;	/* interface to riva_hw.c */
+
+	const char *drvr_name;	/* Riva hardware board type */
+
+	unsigned long ctrl_base_phys;	/* physical control register base addr */
+	unsigned long fb_base_phys;	/* physical framebuffer base addr */
+
+	caddr_t ctrl_base;	/* virtual control register base addr */
+	caddr_t fb_base;	/* virtual framebuffer base addr */
+
+	unsigned ram_amount;	/* amount of RAM on card, in bytes */
+	unsigned dclk_max;	/* max DCLK */
+
+	struct riva_regs initial_state;	/* initial startup video mode */
+
+	struct display disp;
+	int currcon;
+	struct display *currcon_display;
+
+	struct rivafb_info *next;
+
+	struct pci_dev *pd;	/* pointer to board's pci info */
+	unsigned base0_region_size;	/* size of control register region */
+	unsigned base1_region_size;	/* size of framebuffer region */
+
+	riva_cfb8_cmap_t palette[256];	/* VGA DAC palette cache */
+
+#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
+	union {
+#ifdef FBCON_HAS_CFB16
+		u_int16_t cfb16[16];
+#endif
+#ifdef FBCON_HAS_CFB32
+		u_int32_t cfb32[16];
+#endif
+	} con_cmap;
+#endif				/* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */
+};
+
+/* ------------------- global variables ------------------------ */
+
+
+static struct rivafb_info *riva_boards = NULL;
+
+/* command line data, set in rivafb_setup() */
+static char fontname[40] __initdata;
+#ifndef MODULE
+static char noaccel __initdata;	/* unused */
+static const char *mode_option __initdata;
+#endif
+
+static struct fb_var_screeninfo rivafb_default_var = {
+	/* 640x480-8@60, yres_virtual=2400 (fits for all Riva cards */
+	640, 480, 640, 2400, 0, 0, 8, 0,
+	{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
+	0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
+	0, FB_VMODE_NONINTERLACED
+};
+
+
+/* ------------------- prototypes ------------------------------ */
+
+static int rivafb_open (struct fb_info *info, int user);
+static int rivafb_release (struct fb_info *info, int user);
+static int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con,
+		    struct fb_info *info);
+static int rivafb_get_var (struct fb_var_screeninfo *var, int con,
+		    struct fb_info *info);
+static int rivafb_set_var (struct fb_var_screeninfo *var, int con,
+		    struct fb_info *info);
+static int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
+		     struct fb_info *info);
+static int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
+		     struct fb_info *info);
+static int rivafb_pan_display (struct fb_var_screeninfo *var, int con,
+			struct fb_info *info);
+static int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
+		  unsigned long arg, int con, struct fb_info *info);
+static int rivafb_switch (int con, struct fb_info *info);
+static int rivafb_updatevar (int con, struct fb_info *info);
+static void rivafb_blank (int blank, struct fb_info *info);
+
+static void riva_load_video_mode (struct rivafb_info *rivainfo,
+				  struct fb_var_screeninfo *video_mode);
+static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green,
+			   unsigned *blue, unsigned *transp,
+			   struct fb_info *info);
+static int riva_setcolreg (unsigned regno, unsigned red, unsigned green,
+			   unsigned blue, unsigned transp,
+			   struct fb_info *info);
+static int riva_get_cmap_len (const struct fb_var_screeninfo *var);
+
+static int riva_pci_register (struct pci_dev *pd,
+			      const struct riva_chip_info *rci);
+static int riva_set_fbinfo (struct rivafb_info *rinfo);
+
+static void riva_save_state (struct rivafb_info *rinfo, struct riva_regs *regs);
+static void riva_load_state (struct rivafb_info *rinfo, struct riva_regs *regs);
+static struct rivafb_info *riva_board_list_add (struct rivafb_info *board_list,
+					 struct rivafb_info *new_node);
+static void riva_wclut (unsigned char regnum, unsigned char red,
+			unsigned char green, unsigned char blue);
+
+
+
+
+/* kernel interface */
+static struct fb_ops riva_fb_ops = {
+	rivafb_open,
+	rivafb_release,
+	rivafb_get_fix,
+	rivafb_get_var,
+	rivafb_set_var,
+	rivafb_get_cmap,
+	rivafb_set_cmap,
+	rivafb_pan_display,
+	rivafb_ioctl
+};
+
+
+
+
+/* from GGI */
+static const struct riva_regs reg_template = {
+	{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,	/* ATTR */
+	 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+	 0x41, 0x01, 0x0F, 0x13, 0x00},
+	{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* CRT  */
+	 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
+	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3,	/* 0x10 */
+	 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* 0x20 */
+	 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* 0x30 */
+	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	 0x00,			/* 0x40 */
+	 },
+	{0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,	/* GRA  */
+	 0xFF},
+	{0x03, 0x01, 0x0F, 0x00, 0x0E},	/* SEQ  */
+	0xEB			/* MISC */
+};
+
+
+
+/* ------------------- general utility functions -------------------------- */
+
+/**
+ * riva_set_dispsw
+ * @rivainfo: pointer to internal driver struct for a given Riva card
+ *
+ * DESCRIPTION:
+ * Sets up console Low level operations depending on the current? color depth
+ * of the display
+ */
+
+static void riva_set_dispsw (struct rivafb_info *rinfo)
+{
+	struct display *disp = &rinfo->disp;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rinfo != NULL);
+
+	disp->dispsw_data = NULL;
+
+	switch (disp->var.bits_per_pixel) {
+#ifdef FBCON_HAS_MFB
+	case 1:
+		disp->dispsw = &fbcon_mfb;
+		break;
+#endif
+#ifdef FBCON_HAS_CFB4
+	case 4:
+		disp->dispsw = &fbcon_cfb4;
+		break;
+#endif
+#ifdef FBCON_HAS_CFB8
+	case 8:
+		disp->dispsw = &fbcon_cfb8;
+		break;
+#endif
+#ifdef FBCON_HAS_CFB16
+	case 15:
+	case 16:
+		disp->dispsw = &fbcon_cfb16;
+		disp->dispsw_data = &rinfo->con_cmap.cfb16;
+		break;
+#endif
+#ifdef FBCON_HAS_CFB24
+	case 24:
+		disp->dispsw = &fbcon_cfb24;
+		disp->dispsw_data = rinfo->con_cmap.cfb24;
+		break;
+#endif
+#ifdef FBCON_HAS_CFB32
+	case 32:
+		disp->dispsw = &fbcon_cfb32;
+		disp->dispsw_data = rinfo->con_cmap.cfb32;
+		break;
+#endif
+	default:
+		DPRINTK ("Setting fbcon_dummy renderer\n");
+		disp->dispsw = &fbcon_dummy;
+	}
+
+	DPRINTK ("EXIT\n");
+}
+
+
+
+
+static int riva_init_disp_var (struct rivafb_info *rinfo)
+{
+#ifndef MODULE
+	if (mode_option)
+		fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
+			      NULL, 0, NULL, 8);
+	else
+		fb_find_mode (&rinfo->disp.var, &rinfo->info,
+			      "640x480-8@60", NULL, 0, NULL, 8);
+#endif				/* !MODULE */
+	return 0;
+}
+
+
+
+
+static int __devinit riva_init_disp (struct rivafb_info *rinfo)
+{
+	struct fb_info *info;
+	struct display *disp;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rinfo != NULL);
+
+	info = &rinfo->info;
+	disp = &rinfo->disp;
+
+	disp->var = rivafb_default_var;
+	info->disp = disp;
+
+#warning FIXME: assure that disp->cmap is completely filled out
+
+	disp->screen_base = rinfo->fb_base;
+	disp->visual = FB_VISUAL_PSEUDOCOLOR;
+	disp->type = FB_TYPE_PACKED_PIXELS;
+	disp->type_aux = 0;
+	disp->ypanstep = 1;
+	disp->ywrapstep = 0;
+	disp->next_line = disp->line_length =
+	    (disp->var.xres_virtual * disp->var.bits_per_pixel) >> 3;
+	disp->can_soft_blank = 1;
+	disp->inverse = 0;
+
+	riva_set_dispsw (rinfo);
+
+	disp->scrollmode = 0;
+
+	rinfo->currcon_display = disp;
+
+	if ((riva_init_disp_var (rinfo)) < 0) {	/* must be done last */
+		DPRINTK ("EXIT, returning -1\n");
+		return -1;
+	}
+
+	DPRINTK ("EXIT, returning 0\n");
+	return 0;
+
+}
+
+
+
+static int __devinit riva_set_fbinfo (struct rivafb_info *rinfo)
+{
+	struct fb_info *info;
+
+	assert (rinfo != NULL);
+
+	info = &rinfo->info;
+
+	strcpy (info->modename, rinfo->drvr_name);
+	info->node = -1;
+	info->flags = FBINFO_FLAG_DEFAULT;
+	info->fbops = &riva_fb_ops;
+
+#warning FIXME: set monspecs to what???
+
+	info->display_fg = NULL;	/* FIXME: correct? */
+	strncpy (info->fontname, fontname, sizeof (info->fontname));
+	info->fontname[sizeof (info->fontname) - 1] = 0;
+
+	info->changevar = NULL;	/* FIXME: needed? */
+	info->switch_con = rivafb_switch;
+	info->updatevar = rivafb_updatevar;
+	info->blank = rivafb_blank;
+
+	if (riva_init_disp (rinfo) < 0)	/* must be done last */
+		return -1;
+
+	return 0;
+}
+
+
+
+
+/* ----------------------------- PCI bus ----------------------------- */
+
+
+
+
+static void __devinit riva_init_clut (struct rivafb_info *fb_info)
+{
+	int j, k, red, green, blue;
+
+	for (j = 0; j < 256; j++) {
+		if (j < 16) {
+			/* use default fbcon colors for first 16 */
+			k = color_table[j];
+			red = default_red[k];
+			green = default_grn[k];
+			blue = default_blu[k];
+		} else {
+			/* grey ramp for rest of colors */
+			red = green = blue = j;
+		}
+
+		riva_wclut (j, red, green, blue);
+
+		fb_info->palette[j].red = red;
+		fb_info->palette[j].green = green;
+		fb_info->palette[j].blue = blue;
+	}
+}
+
+
+
+static int __devinit rivafb_init_one (struct pci_dev *pd,
+				      const struct pci_device_id *ent)
+{
+	struct rivafb_info *rinfo;
+	struct riva_chip_info *rci = &riva_chip_info[ent->driver_data];
+
+	assert (pd != NULL);
+	assert (rci != NULL);
+
+	rinfo = kmalloc (sizeof (struct rivafb_info), GFP_KERNEL);
+	if (!rinfo)
+		goto err_out;
+
+	memset (rinfo, 0, sizeof (struct rivafb_info));
+
+	rinfo->drvr_name = rci->name;
+	rinfo->riva.Architecture = rci->arch_rev;
+
+	rinfo->pd = pd;
+	rinfo->base0_region_size = pci_resource_start (pd, 0);
+	rinfo->base1_region_size = pci_resource_start (pd, 1);
+
+	assert (rinfo->base0_region_size >= 0x00800000);	/* from GGI */
+	assert (rinfo->base0_region_size >= 0x01000000);	/* from GGI */
+
+	rinfo->ctrl_base_phys = rinfo->pd->resource[0].start;
+	rinfo->fb_base_phys = rinfo->pd->resource[1].start;
+
+	if (!request_mem_region (rinfo->ctrl_base_phys,
+				 rinfo->base0_region_size, "rivafb")) {
+		printk (KERN_ERR PFX "cannot reserve MMIO region\n");
+		goto err_out_kfree;
+	}
+
+	if (!request_mem_region (rinfo->fb_base_phys,
+				 rinfo->base1_region_size, "rivafb")) {
+		printk (KERN_ERR PFX "cannot reserve FB region\n");
+		goto err_out_free_base0;
+	}
+
+	rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys,
+				    rinfo->base0_region_size);
+	if (!rinfo->ctrl_base) {
+		printk (KERN_ERR PFX "cannot ioremap ctrl base\n");
+		goto err_out_free_base1;
+	}
+	
+	rinfo->fb_base = ioremap (rinfo->fb_base_phys,
+				  rinfo->base1_region_size);
+	if (!rinfo->fb_base) {
+		printk (KERN_ERR PFX "cannot ioremap ctrl base\n");
+		goto err_out_iounmap_ctrl;
+	}
+	
+	rinfo->riva.EnableIRQ = 0;
+	rinfo->riva.IO = (inb (0x3CC) & 0x01) ? 0x3D0 : 0x3B0;
+	rinfo->riva.PRAMDAC = (unsigned *) (rinfo->ctrl_base + 0x00680000);
+	rinfo->riva.PFB = (unsigned *) (rinfo->ctrl_base + 0x00100000);
+	rinfo->riva.PFIFO = (unsigned *) (rinfo->ctrl_base + 0x00002000);
+	rinfo->riva.PGRAPH = (unsigned *) (rinfo->ctrl_base + 0x00400000);
+	rinfo->riva.PEXTDEV = (unsigned *) (rinfo->ctrl_base + 0x00101000);
+	rinfo->riva.PTIMER = (unsigned *) (rinfo->ctrl_base + 0x00009000);
+	rinfo->riva.PMC = (unsigned *) (rinfo->ctrl_base + 0x00000000);
+	rinfo->riva.FIFO = (unsigned *) (rinfo->ctrl_base + 0x00800000);
+
+	switch (rinfo->riva.Architecture) {
+	case 3:
+		rinfo->riva.PRAMIN =
+		    (unsigned *) (rinfo->ctrl_base + 0x00C00000);
+		break;
+	case 4:
+	case 5:
+		rinfo->riva.PCRTC =
+		    (unsigned *) (rinfo->ctrl_base + 0x00600000);
+		rinfo->riva.PRAMIN =
+		    (unsigned *) (rinfo->ctrl_base + 0x00710000);
+		break;
+	}
+
+	RivaGetConfig (&rinfo->riva);
+
+	/* back to normal */
+
+	assert (rinfo->pd != NULL);
+
+	/* unlock io */
+	vga_io_wcrt (0x11, 0xFF);	/* vgaHWunlock() + riva unlock (0x7F) */
+	outb (rinfo->riva.LockUnlockIndex, rinfo->riva.LockUnlockIO);
+	outb (0x57, rinfo->riva.LockUnlockIO + 1);
+
+	memcpy (&rinfo->initial_state, &reg_template,
+		sizeof (reg_template));
+	riva_save_state (rinfo, &rinfo->initial_state);
+
+	rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024;
+	rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000;
+
+	riva_set_fbinfo (rinfo);
+
+	riva_init_clut (rinfo);
+
+	riva_load_video_mode (rinfo, &rinfo->disp.var);
+
+	if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
+		printk (KERN_ERR PFX
+			"error registering riva framebuffer\n");
+		goto err_out_iounmap_fb;
+	}
+
+	pd->driver_data = rinfo;
+
+	printk ("PCI Riva NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n",
+		rinfo->riva.Architecture,
+		RIVAFB_VERSION,
+		rinfo->drvr_name,
+		rinfo->ram_amount / (1024 * 1024) + 1,
+		rinfo->fb_base_phys);
+
+	return 0;
+
+err_out_iounmap_fb:
+	iounmap (rinfo->fb_base);
+err_out_iounmap_ctrl:
+	iounmap (rinfo->ctrl_base);
+err_out_free_base1:
+	release_mem_region (rinfo->fb_base_phys, rinfo->base1_region_size);
+err_out_free_base0:
+	release_mem_region (rinfo->ctrl_base_phys, rinfo->base0_region_size);
+err_out_kfree:
+	kfree (rinfo);
+err_out:
+	return -ENODEV;
+}
+
+
+static void __devexit rivafb_remove_one (struct pci_dev *pd)
+{
+	struct rivafb_info *board = pd->driver_data;
+	
+	if (!board)
+		return;
+		
+	riva_load_state (board, &board->initial_state);
+
+	unregister_framebuffer ((struct fb_info *) board);
+
+	iounmap (board->ctrl_base);
+	iounmap (board->fb_base);
+
+	release_mem_region (board->ctrl_base_phys,
+			    board->base0_region_size);
+	release_mem_region (board->fb_base_phys,
+			    board->base1_region_size);
+
+	kfree (board);
+}
+
+
+/*** riva_wclut - set CLUT entry ***/
+static void riva_wclut (unsigned char regnum, unsigned char red,
+			unsigned char green, unsigned char blue)
+{
+	unsigned int data = VGA_PEL_D;
+
+	/* address write mode register is not translated.. */
+	vga_io_w (VGA_PEL_IW, regnum);
+
+	vga_io_w (data, red);
+	vga_io_w (data, green);
+	vga_io_w (data, blue);
+}
+
+
+
+/* ------------ Hardware Independent Functions ------------ */
+
+#ifndef MODULE
+int __init rivafb_setup (char *options)
+{
+	char *this_opt;
+
+	if (!options || !*options)
+		return 0;
+
+	for (this_opt = strtok (options, ","); this_opt;
+	     this_opt = strtok (NULL, ",")) {
+		if (!strncmp (this_opt, "font:", 5)) {
+			char *p;
+			int i;
+
+			p = this_opt + 5;
+			for (i = 0; i < sizeof (fontname) - 1; i++)
+				if (!*p || *p == ' ' || *p == ',')
+					break;
+			memcpy (fontname, this_opt + 5, i);
+			fontname[i] = 0;
+		}
+
+		else if (!strncmp (this_opt, "noaccel", 7)) {
+			noaccel = 1;
+		}
+
+		else
+			mode_option = this_opt;
+	}
+	return 0;
+}
+#endif				/* !MODULE */
+
+    /*
+     *  Initialization
+     */
+
+/* ------------------------------------------------------------------------- */
+
+
+    /*
+     *  Frame buffer operations
+     */
+
+static int rivafb_open (struct fb_info *info, int user)
+{
+	/* Nothing, only a usage count for the moment */
+	MOD_INC_USE_COUNT;
+	return 0;
+}
+
+static int rivafb_release (struct fb_info *info, int user)
+{
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+
+static int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con,
+		    struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+	struct display *p;
+
+	DPRINTK ("ENTER\n");
+
+	assert (fix != NULL);
+	assert (info != NULL);
+	assert (rivainfo->drvr_name && rivainfo->drvr_name[0]);
+	assert (rivainfo->fb_base_phys > 0);
+	assert (rivainfo->ram_amount > 0);
+
+	p = (con < 0) ? rivainfo->info.disp : &fb_display[con];
+
+	memset (fix, 0, sizeof (struct fb_fix_screeninfo));
+	sprintf (fix->id, "Riva %s", rivainfo->drvr_name);
+
+	fix->smem_start = rivainfo->fb_base_phys;
+	fix->smem_len = rivainfo->ram_amount;
+
+	fix->type = p->type;
+	fix->type_aux = p->type_aux;
+	fix->visual = p->visual;
+
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+	fix->ywrapstep = 0;	/* FIXME: no ywrap for now */
+
+	fix->line_length = p->line_length;
+
+#warning FIXME: set up MMIO region, export via FB_ACCEL_xxx
+	fix->mmio_start = 0;
+	fix->mmio_len = 0;
+	fix->accel = FB_ACCEL_NONE;
+
+	DPRINTK ("EXIT, returning 0\n");
+
+	return 0;
+}
+
+
+static int rivafb_get_var (struct fb_var_screeninfo *var, int con,
+		    struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+
+	DPRINTK ("ENTER\n");
+
+	assert (info != NULL);
+	assert (var != NULL);
+
+	*var = (con < 0) ? rivainfo->disp.var : fb_display[con].var;
+
+	DPRINTK ("EXIT, returning 0\n");
+
+	return 0;
+}
+
+
+
+static int rivafb_set_var (struct fb_var_screeninfo *var, int con,
+		    struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+	struct display *dsp;
+	struct fb_var_screeninfo v;
+	int nom, den;		/* translating from pixels->bytes */
+	int i;
+	unsigned chgvar = 0;
+	static struct {
+		int xres, yres;
+	} modes[] = {
+		{
+		1600, 1280}, {
+		1280, 1024}, {
+		1024, 768}, {
+		800, 600}, {
+		640, 480}, {
+		-1, -1}
+	};
+
+	DPRINTK ("ENTER\n");
+
+	assert (info != NULL);
+	assert (var != NULL);
+
+	DPRINTK ("Requested: %dx%dx%d\n", var->xres, var->yres,
+		 var->bits_per_pixel);
+	DPRINTK ("  virtual: %dx%d\n", var->xres_virtual,
+		 var->yres_virtual);
+	DPRINTK ("   offset: (%d,%d)\n", var->xoffset, var->yoffset);
+	DPRINTK ("grayscale: %d\n", var->grayscale);
+
+	dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
+	assert (dsp != NULL);
+
+	/* if var has changed, we should call changevar() later */
+	if (con >= 0) {
+		chgvar = ((dsp->var.xres != var->xres) ||
+			  (dsp->var.yres != var->yres) ||
+			  (dsp->var.xres_virtual != var->xres_virtual) ||
+			  (dsp->var.yres_virtual != var->yres_virtual) ||
+			  (dsp->var.bits_per_pixel != var->bits_per_pixel)
+			  || memcmp (&dsp->var.red, &var->red,
+				     sizeof (var->red))
+			  || memcmp (&dsp->var.green, &var->green,
+				     sizeof (var->green))
+			  || memcmp (&dsp->var.blue, &var->blue,
+				     sizeof (var->blue)));
+	}
+
+	memcpy (&v, var, sizeof (v));
+
+	switch (v.bits_per_pixel) {
+#ifdef FBCON_HAS_MFB
+	case 1:
+		dsp->dispsw = &fbcon_mfb;
+		dsp->line_length = v.xres_virtual / 8;
+		dsp->visual = FB_VISUAL_MONO10;
+		nom = 4;
+		den = 8;
+		break;
+#endif
+
+#ifdef FBCON_HAS_CFB8
+	case 2 ... 8:
+		v.bits_per_pixel = 8;
+		dsp->dispsw = &fbcon_cfb8;
+		nom = 1;
+		den = 1;
+		dsp->line_length = v.xres_virtual;
+		dsp->visual = FB_VISUAL_PSEUDOCOLOR;
+		v.red.offset = 0;
+		v.red.length = 6;
+		v.green.offset = 0;
+		v.green.length = 6;
+		v.blue.offset = 0;
+		v.blue.length = 6;
+		break;
+#endif
+
+#ifdef FBCON_HAS_CFB16
+	case 9 ... 16:
+		v.bits_per_pixel = 16;
+		dsp->dispsw = &fbcon_cfb16;
+		dsp->dispsw_data = &rivainfo->con_cmap.cfb16;
+		nom = 2;
+		den = 1;
+		dsp->line_length = v.xres_virtual * 2;
+		dsp->visual = FB_VISUAL_DIRECTCOLOR;
+#ifdef CONFIG_PREP
+		v.red.offset = 2;
+		v.green.offset = -3;
+		v.blue.offset = 8;
+#else
+		v.red.offset = 10;
+		v.green.offset = 5;
+		v.blue.offset = 0;
+#endif
+		v.red.length = 5;
+		v.green.length = 5;
+		v.blue.length = 5;
+		break;
+#endif
+
+#ifdef FBCON_HAS_CFB32
+	case 17 ... 32:
+		v.bits_per_pixel = 32;
+		dsp->dispsw = &fbcon_cfb32;
+		dsp->dispsw_data = rivainfo->con_cmap.cfb32;
+		nom = 4;
+		den = 1;
+		dsp->line_length = v.xres_virtual * 4;
+		dsp->visual = FB_VISUAL_DIRECTCOLOR;
+#ifdef CONFIG_PREP
+		v.red.offset = 8;
+		v.green.offset = 16;
+		v.blue.offset = 24;
+#else
+		v.red.offset = 16;
+		v.green.offset = 8;
+		v.blue.offset = 0;
+#endif
+		v.red.length = 8;
+		v.green.length = 8;
+		v.blue.length = 8;
+		break;
+#endif
+
+	default:
+		printk (KERN_ERR PFX
+			"mode %dx%dx%d rejected...color depth not supported.\n",
+			var->xres, var->yres, var->bits_per_pixel);
+		DPRINTK ("EXIT, returning -EINVAL\n");
+		return -EINVAL;
+	}
+
+	if (v.xres * nom / den * v.yres > rivainfo->ram_amount) {
+		printk (KERN_ERR PFX
+			"mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
+			var->xres, var->yres, var->bits_per_pixel);
+		DPRINTK ("EXIT - EINVAL error\n");
+		return -EINVAL;
+	}
+
+	/* use highest possible virtual resolution */
+	if (v.xres_virtual == -1 && v.yres_virtual == -1) {
+		printk (KERN_WARNING PFX
+			"using maximum available virtual resolution\n");
+		for (i = 0; modes[i].xres != -1; i++) {
+			if (modes[i].xres * nom / den * modes[i].yres <
+			    rivainfo->ram_amount / 2)
+				break;
+		}
+		if (modes[i].xres == -1) {
+			printk (KERN_ERR PFX
+				"could not find a virtual resolution that fits into video memory!!\n");
+			DPRINTK ("EXIT - EINVAL error\n");
+			return -EINVAL;
+		}
+		v.xres_virtual = modes[i].xres;
+		v.yres_virtual = modes[i].yres;
+
+		printk (KERN_INFO PFX
+			"virtual resolution set to maximum of %dx%d\n",
+			v.xres_virtual, v.yres_virtual);
+	} else if (v.xres_virtual == -1) {
+		/* FIXME: maximize X virtual resolution only */
+	} else if (v.yres_virtual == -1) {
+		/* FIXME: maximize Y virtual resolution only */
+	}
+
+	if (v.xoffset < 0)
+		v.xoffset = 0;
+	if (v.yoffset < 0)
+		v.yoffset = 0;
+
+	/* truncate xoffset and yoffset to maximum if too high */
+	if (v.xoffset > v.xres_virtual - v.xres)
+		v.xoffset = v.xres_virtual - v.xres - 1;
+
+	if (v.yoffset > v.yres_virtual - v.yres)
+		v.yoffset = v.yres_virtual - v.yres - 1;
+
+	v.red.msb_right =
+	    v.green.msb_right =
+	    v.blue.msb_right =
+	    v.transp.offset = v.transp.length = v.transp.msb_right = 0;
+
+	switch (v.activate & FB_ACTIVATE_MASK) {
+	case FB_ACTIVATE_TEST:
+		DPRINTK ("EXIT - FB_ACTIVATE_TEST\n");
+		return 0;
+	case FB_ACTIVATE_NXTOPEN:	/* ?? */
+	case FB_ACTIVATE_NOW:
+		break;		/* continue */
+	default:
+		DPRINTK ("EXIT - unknown activation type\n");
+		return -EINVAL;	/* unknown */
+	}
+
+	dsp->type = FB_TYPE_PACKED_PIXELS;
+
+#warning FIXME: verify that the above code sets dsp->* fields correctly
+
+	memcpy (&dsp->var, &v, sizeof (v));
+
+	riva_load_video_mode (rivainfo, &v);
+
+	if (chgvar && info && info->changevar)
+		info->changevar (con);
+
+	DPRINTK ("EXIT, returning 0\n");
+	return 0;
+}
+
+
+
+static int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
+		     struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+	struct display *dsp;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+	assert (cmap != NULL);
+
+	dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
+
+	if (con == rivainfo->currcon) {	/* current console? */
+		int rc = fb_get_cmap (cmap, kspc, riva_getcolreg, info);
+		DPRINTK ("EXIT - returning %d\n", rc);
+		return rc;
+	} else if (dsp->cmap.len)	/* non default colormap? */
+		fb_copy_cmap (&dsp->cmap, cmap, kspc ? 0 : 2);
+	else
+		fb_copy_cmap (fb_default_cmap
+			      (riva_get_cmap_len (&dsp->var)), cmap,
+			      kspc ? 0 : 2);
+
+	DPRINTK ("EXIT, returning 0\n");
+
+	return 0;
+}
+
+
+static int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
+		     struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+	struct display *dsp;
+	unsigned int cmap_len;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+	assert (cmap != NULL);
+
+	dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
+
+	cmap_len = riva_get_cmap_len (&dsp->var);
+	if (dsp->cmap.len != cmap_len) {
+		int err = fb_alloc_cmap (&dsp->cmap, cmap_len, 0);
+		if (err) {
+			DPRINTK ("EXIT - returning %d\n", err);
+			return err;
+		}
+	}
+	if (con == rivainfo->currcon) {	/* current console? */
+		int rc = fb_set_cmap (cmap, kspc, riva_setcolreg, info);
+		DPRINTK ("EXIT - returning %d\n", rc);
+		return rc;
+	} else
+		fb_copy_cmap (cmap, &dsp->cmap, kspc ? 0 : 1);
+
+	DPRINTK ("EXIT, returning 0\n");
+
+	return 0;
+}
+
+
+
+/**
+ * rivafb_pan_display
+ * @var: standard kernel fb changeable data
+ * @par: riva-specific hardware info about current video mode
+ * @info: pointer to rivafb_info object containing info for current riva board
+ *
+ * DESCRIPTION:
+ * Pan (or wrap, depending on the `vmode' field) the display using the
+ * `xoffset' and `yoffset' fields of the `var' structure.
+ * If the values don't fit, return -EINVAL.
+ *
+ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
+ */
+
+static int rivafb_pan_display (struct fb_var_screeninfo *var, int con,
+			struct fb_info *info)
+{
+	unsigned int base;
+	struct display *dsp;
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+
+	if (var->xoffset > (var->xres_virtual - var->xres))
+		return -EINVAL;
+	if (var->yoffset > (var->yres_virtual - var->yres))
+		return -EINVAL;
+
+	dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
+
+	if (var->vmode & FB_VMODE_YWRAP) {
+		if (var->yoffset < 0
+		    || var->yoffset >= dsp->var.yres_virtual
+		    || var->xoffset) return -EINVAL;
+	} else {
+		if (var->xoffset + dsp->var.xres > dsp->var.xres_virtual ||
+		    var->yoffset + dsp->var.yres > dsp->var.yres_virtual)
+			return -EINVAL;
+	}
+
+	base = var->yoffset * dsp->line_length + var->xoffset;
+
+	if (con == rivainfo->currcon) {
+		rivainfo->riva.SetStartAddress (&rivainfo->riva, base);
+	}
+
+	dsp->var.xoffset = var->xoffset;
+	dsp->var.yoffset = var->yoffset;
+
+	if (var->vmode & FB_VMODE_YWRAP)
+		dsp->var.vmode |= FB_VMODE_YWRAP;
+	else
+		dsp->var.vmode &= ~FB_VMODE_YWRAP;
+
+	DPRINTK ("EXIT, returning 0\n");
+
+	return 0;
+}
+
+
+static int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
+		  unsigned long arg, int con, struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+
+	/* no rivafb-specific ioctls */
+
+	DPRINTK ("EXIT, returning -EINVAL\n");
+
+	return -EINVAL;
+}
+
+
+static int rivafb_switch (int con, struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+	struct fb_cmap *cmap;
+	struct display *dsp;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+
+	dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
+
+	if (rivainfo->currcon >= 0) {
+		/* Do we have to save the colormap? */
+		cmap = &(rivainfo->currcon_display->cmap);
+		DPRINTK ("switch1: con = %d, cmap.len = %d\n",
+			 rivainfo->currcon, cmap->len);
+
+		if (cmap->len) {
+			DPRINTK ("switch1a: %p %p %p %p\n", cmap->red,
+				 cmap->green, cmap->blue, cmap->transp);
+			fb_get_cmap (cmap, 1, riva_getcolreg, info);
+#ifdef DEBUG
+			if (cmap->red) {
+				DPRINTK ("switch1r: %X\n", cmap->red[0]);
+			}
+#endif
+		}
+	}
+	rivainfo->currcon = con;
+	rivainfo->currcon_display = dsp;
+	dsp->var.activate = FB_ACTIVATE_NOW;
+
+#ifdef riva_DEBUG
+	cmap = &dsp->cmap;
+	DPRINTK ("switch2: con = %d, cmap.len = %d\n", con, cmap->len);
+	DPRINTK ("switch2a: %p %p %p %p\n", cmap->red, cmap->green,
+		 cmap->blue, cmap->transp);
+	if (dsp->cmap.red) {
+		DPRINTK ("switch2r: %X\n", cmap->red[0]);
+	}
+#endif
+
+	rivafb_set_var (&dsp->var, con, info);
+
+#ifdef riva_DEBUG
+	DPRINTK ("switch3: con = %d, cmap.len = %d\n", con, cmap->len);
+	DPRINTK ("switch3a: %p %p %p %p\n", cmap->red, cmap->green,
+		 cmap->blue, cmap->transp);
+	if (dsp->cmap.red) {
+		DPRINTK ("switch3r: %X\n", cmap->red[0]);
+	}
+#endif
+
+	DPRINTK ("EXIT, returning 0\n");
+	return 0;
+}
+
+static int rivafb_updatevar (int con, struct fb_info *info)
+{
+	int rc;
+
+	DPRINTK ("ENTER\n");
+
+	rc = (con <
+		0) ? -EINVAL : rivafb_pan_display (&fb_display[con].var,
+						   con, info);
+	DPRINTK ("EXIT, returning %d\n", rc);
+	return rc;
+}
+
+
+static void rivafb_blank (int blank, struct fb_info *info)
+{
+	unsigned char tmp;
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+
+	tmp = vga_io_rseq (VGA_SEQ_CLOCK_MODE) & ~VGA_SR01_SCREEN_OFF;
+
+	if (blank)
+		tmp |= VGA_SR01_SCREEN_OFF;
+
+	vga_io_wseq (VGA_SEQ_CLOCK_MODE, tmp);
+
+	DPRINTK ("EXIT\n");
+}
+
+
+/* -------------------------------------------------------------------------
+ *
+ * internal fb_ops helper functions
+ *
+ * -------------------------------------------------------------------------
+ */
+
+
+/**
+ * riva_get_cmap_len
+ * @var:
+ *
+ * DESCRIPTION:
+ */
+
+static int riva_get_cmap_len (const struct fb_var_screeninfo *var)
+{
+	int rc = 16;		/* reasonable default */
+
+	assert (var != NULL);
+
+	switch (var->bits_per_pixel) {
+#ifdef FBCON_HAS_CFB4
+	case 4:
+		rc = 16;	/* pseudocolor... 16 entries HW palette */
+		break;
+#endif
+#ifdef FBCON_HAS_CFB8
+	case 8:
+		rc = 256;	/* pseudocolor... 256 entries HW palette */
+		break;
+#endif
+#ifdef FBCON_HAS_CFB16
+	case 16:
+		rc = 16;	/* directcolor... 16 entries SW palette */
+		break;		/* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
+#endif
+#ifdef FBCON_HAS_CFB32
+	case 32:
+		rc = 16;	/* directcolor... 16 entries SW palette */
+		break;		/* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
+#endif
+	default:
+		assert (0);
+		/* should not occur */
+		break;
+	}
+
+	return rc;
+}
+
+
+/**
+ * riva_getcolreg
+ * @regno:
+ * @red:
+ * @green:
+ * @blue:
+ * @transp:
+ * @info: pointer to rivafb_info object containing info for current riva board
+ *
+ * DESCRIPTION:
+ * Read a single color register and split it into colors/transparent.
+ * The return values must have a 16 bit magnitude.
+ * Return != 0 for invalid regno.
+ *
+ * CALLED FROM:
+ * fbcmap.c:fb_get_cmap()
+ *	fbgen.c:fbgen_get_cmap()
+ *	fbgen.c:fbgen_switch()
+ */
+
+static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green,
+			   unsigned *blue, unsigned *transp,
+			   struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+
+	if (regno > 255)
+		return 1;
+
+	*red = rivainfo->palette[regno].red;
+	*green = rivainfo->palette[regno].green;
+	*blue = rivainfo->palette[regno].blue;
+	*transp = 0;
+
+	return 0;
+}
+
+
+/**
+ * riva_setcolreg
+ * @regno:
+ * @red:
+ * @green:
+ * @blue:
+ * @transp:
+ * @info: pointer to rivafb_info object containing info for current riva board
+ *
+ * DESCRIPTION:
+ * Set a single color register. The values supplied have a 16 bit
+ * magnitude.
+ * Return != 0 for invalid regno.
+ *
+ * CALLED FROM:
+ * fbcmap.c:fb_set_cmap()
+ *	fbgen.c:fbgen_get_cmap()
+ *	fbgen.c:fbgen_install_cmap()
+ *		fbgen.c:fbgen_set_var()
+ *		fbgen.c:fbgen_switch()
+ *		fbgen.c:fbgen_blank()
+ *	fbgen.c:fbgen_blank()
+ */
+
+static int riva_setcolreg (unsigned regno, unsigned red, unsigned green,
+			   unsigned blue, unsigned transp,
+			   struct fb_info *info)
+{
+	struct rivafb_info *rivainfo = (struct rivafb_info *) info;
+	struct display *p;
+
+	DPRINTK ("ENTER\n");
+
+	assert (rivainfo != NULL);
+	assert (rivainfo->currcon_display != NULL);
+
+	if (regno > 255)
+		return -EINVAL;
+
+	p = rivainfo->currcon_display;
+	if (p->var.grayscale) {
+		/* gray = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue =
+		    (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+#ifdef FBCON_HAS_CFB8
+	switch (p->var.bits_per_pixel) {
+	case 8:
+		/* "transparent" stuff is completely ignored. */
+		riva_wclut (regno, red >> 10, green >> 10, blue >> 10);
+		break;
+	default:
+		/* do nothing */
+		break;
+	}
+#endif				/* FBCON_HAS_CFB8 */
+
+	rivainfo->palette[regno].red = red;
+	rivainfo->palette[regno].green = green;
+	rivainfo->palette[regno].blue = blue;
+
+	if (regno >= 16)
+		return 0;
+
+	switch (p->var.bits_per_pixel) {
+
+#ifdef FBCON_HAS_CFB16
+	case 16:
+		assert (regno < 16);
+#ifdef CONFIG_PREP
+		rivainfo->con_cmap.cfb16[regno] =
+		    ((red & 0xf800) >> 9) |
+		    ((green & 0xf800) >> 14) |
+		    ((green & 0xf800) << 2) | ((blue & 0xf800) >> 3);
+#else
+		rivainfo->con_cmap.cfb16[regno] =
+		    ((red & 0xf800) >> 1) |
+		    ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
+#endif
+		break;
+#endif				/* FBCON_HAS_CFB16 */
+
+#ifdef FBCON_HAS_CFB32
+	case 32:
+		assert (regno < 16);
+#ifdef CONFIG_PREP
+		rivainfo->con_cmap.cfb32[regno] =
+		    ((red & 0xff00)) |
+		    ((green & 0xff00) << 8) | ((blue & 0xff00) << 16);
+#else
+		rivainfo->con_cmap.cfb32[regno] =
+		    ((red & 0xff00) << 8) |
+		    ((green & 0xff00)) | ((blue & 0xff00) >> 8);
+#endif
+		break;
+#endif				/* FBCON_HAS_CFB32 */
+
+	default:
+		/* do nothing */
+		break;
+	}
+
+	return 0;
+}
+
+
+
+/*
+ * riva_load_video_mode()
+ *
+ * calculate some timings and then send em off to riva_load_state()
+ */
+
+static void riva_load_video_mode (struct rivafb_info *rinfo,
+				  struct fb_var_screeninfo *video_mode)
+{
+	struct riva_regs newmode;
+	int bpp, width, hDisplaySize, hDisplay, hStart,
+	    hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
+
+	/* time to calculate */
+
+	bpp = video_mode->bits_per_pixel;
+	width = hDisplaySize = video_mode->xres;
+	hDisplay = (hDisplaySize / 8) - 1;
+	hStart = (hDisplaySize + video_mode->right_margin) / 8 + 2;
+	hEnd = (hDisplaySize + video_mode->right_margin +
+		video_mode->hsync_len) / 8 - 1;
+	hTotal = (hDisplaySize + video_mode->right_margin +
+		  video_mode->hsync_len + video_mode->left_margin) / 8 - 1;
+	height = video_mode->yres;
+	vDisplay = video_mode->yres - 1;
+	vStart = video_mode->yres + video_mode->lower_margin - 1;
+	vEnd = video_mode->yres + video_mode->lower_margin +
+	    video_mode->vsync_len - 1;
+	vTotal = video_mode->yres + video_mode->lower_margin +
+	    video_mode->vsync_len + video_mode->upper_margin + 2;
+	dotClock = 1000000000 / video_mode->pixclock;
+
+	memcpy (&newmode, &reg_template, sizeof (struct riva_regs));
+
+	newmode.crtc[0x0] = Set8Bits (hTotal - 4);
+	newmode.crtc[0x1] = Set8Bits (hDisplay);
+	newmode.crtc[0x2] = Set8Bits (hDisplay);
+      newmode.crtc[0x3] = SetBitField (hTotal, 4: 0, 4:0) | SetBit (7);
+	newmode.crtc[0x4] = Set8Bits (hStart);
+      newmode.crtc[0x5] = SetBitField (hTotal, 5: 5, 7:7)
+      | SetBitField (hEnd, 4: 0, 4:0);
+      newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
+      newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
+      | SetBitField (vDisplay, 8: 8, 1:1)
+      | SetBitField (vStart, 8: 8, 2:2)
+      | SetBitField (vDisplay, 8: 8, 3:3)
+	    | SetBit (4)
+      | SetBitField (vTotal, 9: 9, 5:5)
+      | SetBitField (vDisplay, 9: 9, 6:6)
+      | SetBitField (vStart, 9: 9, 7:7);
+      newmode.crtc[0x9] = SetBitField (vDisplay, 9: 9, 5:5)
+	    | SetBit (6);
+	newmode.crtc[0x10] = Set8Bits (vStart);
+      newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
+	    | SetBit (5);
+	newmode.crtc[0x12] = Set8Bits (vDisplay);
+	newmode.crtc[0x13] = ((width / 8) * (bpp / 8)) & 0xFF;
+	newmode.crtc[0x15] = Set8Bits (vDisplay);
+	newmode.crtc[0x16] = Set8Bits (vTotal + 1);
+
+	newmode.ext.bpp = bpp;
+	newmode.ext.width = width;
+	newmode.ext.height = height;
+
+	rinfo->riva.CalcStateExt (&rinfo->riva, &newmode.ext, bpp, width,
+				  hDisplaySize, hDisplay, hStart, hEnd,
+				  hTotal, height, vDisplay, vStart, vEnd,
+				  vTotal, dotClock);
+
+	rinfo->initial_state = newmode;
+	riva_load_state (rinfo, &newmode);
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+
+    /*
+     *  Modularization
+     */
+
+static struct pci_driver rivafb_driver = {
+	name:		"rivafb",
+	id_table:	rivafb_pci_tbl,
+	probe:		rivafb_init_one,
+	remove:		rivafb_remove_one,
+};
+
+
+int __init rivafb_init (void)
+{
+	return pci_module_init (&rivafb_driver);
+}
+
+
+static void __exit rivafb_exit (void)
+{
+	pci_unregister_driver (&rivafb_driver);
+}
+
+
+#ifdef MODULE
+module_init(rivafb_init);
+#endif				/* MODULE */
+module_exit(rivafb_exit);
+
+MODULE_AUTHOR("Jeff Garzik <jgarzik@mandrakesoft.com>");
+MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2");
+
+
+/* from GGI */
+static void riva_save_state (struct rivafb_info *rinfo, struct riva_regs *regs)
+{
+	int i;
+
+	outb (rinfo->riva.LockUnlockIndex, rinfo->riva.LockUnlockIO);
+	outb (0x57, rinfo->riva.LockUnlockIO + 1);
+
+	rinfo->riva.UnloadStateExt (&rinfo->riva, &regs->ext);
+
+	regs->misc_output = io_in8 (0x3CC);
+
+	for (i = 0; i < NUM_CRT_REGS; i++) {
+		io_out8 (i, 0x3D4);
+		regs->crtc[i] = io_in8 (0x3D5);
+	}
+
+	for (i = 0; i < NUM_ATC_REGS; i++) {
+		io_out8 (i, 0x3C0);
+		regs->attr[i] = io_in8 (0x3C1);
+	}
+
+	for (i = 0; i < NUM_GRC_REGS; i++) {
+		io_out8 (i, 0x3CE);
+		regs->gra[i] = io_in8 (0x3CF);
+	}
+
+
+	for (i = 0; i < NUM_SEQ_REGS; i++) {
+		io_out8 (i, 0x3C4);
+		regs->seq[i] = io_in8 (0x3C5);
+	}
+}
+
+
+/* from GGI */
+static
+void riva_load_state (struct rivafb_info *rinfo, struct riva_regs *regs)
+{
+	int i;
+	RIVA_HW_STATE *state = &regs->ext;
+
+	io_out8 (0x11, 0x3D4);
+	io_out8 (0x00, 0x3D5);
+
+	outb (rinfo->riva.LockUnlockIndex, rinfo->riva.LockUnlockIO);
+	outb (0x57, rinfo->riva.LockUnlockIO + 1);
+
+	rinfo->riva.LoadStateExt (&rinfo->riva, state);
+
+	io_out8 (regs->misc_output, 0x3C2);
+
+	for (i = 0; i < NUM_CRT_REGS; i++) {
+		if (i < 0x19) {
+			io_out8 (i, 0x3D4);
+			io_out8 (regs->crtc[i], 0x3D5);
+		} else {
+			switch (i) {
+			case 0x19:
+			case 0x20:
+			case 0x21:
+			case 0x22:
+			case 0x23:
+			case 0x24:
+			case 0x25:
+			case 0x26:
+			case 0x27:
+			case 0x28:
+			case 0x29:
+			case 0x2a:
+			case 0x2b:
+			case 0x2c:
+			case 0x2d:
+			case 0x2e:
+			case 0x2f:
+			case 0x30:
+			case 0x31:
+			case 0x32:
+			case 0x33:
+			case 0x34:
+			case 0x35:
+			case 0x36:
+			case 0x37:
+			case 0x38:
+			case 0x39:
+			case 0x3a:
+			case 0x3b:
+			case 0x3c:
+			case 0x3d:
+			case 0x3e:
+			case 0x3f:
+			case 0x40:
+				break;
+			default:
+				io_out8 (i, 0x3D4);
+				io_out8 (regs->crtc[i], 0x3D5);
+			}
+		}
+	}
+
+	for (i = 0; i < NUM_ATC_REGS; i++) {
+		io_out8 (i, 0x3C0);
+		io_out8 (regs->attr[i], 0x3C1);
+	}
+
+	for (i = 0; i < NUM_GRC_REGS; i++) {
+		io_out8 (i, 0x3CE);
+		io_out8 (regs->gra[i], 0x3CF);
+	}
+
+	for (i = 0; i < NUM_SEQ_REGS; i++) {
+		io_out8 (i, 0x3C4);
+		io_out8 (regs->seq[i], 0x3C5);
+	}
+}
+
+
+
+
+/**
+ * riva_board_list_add
+ * @board_list: Root node of list of boards
+ * @new_node: New node to be added
+ *
+ * DESCRIPTION:
+ * Adds @new_node to the list referenced by @board_list
+ *
+ * RETURNS:
+ * New root node
+ */
+static
+struct rivafb_info *riva_board_list_add (struct rivafb_info *board_list,
+					 struct rivafb_info *new_node)
+{
+	struct rivafb_info *i_p = board_list;
+
+	new_node->next = NULL;
+
+	if (board_list == NULL)
+		return new_node;
+
+	while (i_p->next != NULL)
+		i_p = i_p->next;
+	i_p->next = new_node;
+
+	return board_list;
+}
diff --git a/drivers/video/riva/nv4ref.h b/drivers/video/riva/nv4ref.h
new file mode 100644
index 000000000..ffcb4445d
--- /dev/null
+++ b/drivers/video/riva/nv4ref.h
@@ -0,0 +1,2445 @@
+ /***************************************************************************\
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
+|*     international laws.  Users and possessors of this source code are     *|
+|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
+|*     use this code in individual and commercial software.                  *|
+|*                                                                           *|
+|*     Any use of this source code must include,  in the user documenta-     *|
+|*     tion and  internal comments to the code,  notices to the end user     *|
+|*     as follows:                                                           *|
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
+|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
+|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
+|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
+|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
+|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
+|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
+|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
+|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
+|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
+|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
+|*                                                                           *|
+|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
+|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
+|*     consisting  of "commercial  computer  software"  and  "commercial     *|
+|*     computer  software  documentation,"  as such  terms  are  used in     *|
+|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
+|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
+|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
+|*     all U.S. Government End Users  acquire the source code  with only     *|
+|*     those rights set forth herein.                                        *|
+|*                                                                           *|
+ \***************************************************************************/
+
+/*
+ * GPL licensing note -- nVidia is allowing a liberal interpretation of
+ * the documentation restriction above, to merely say that this nVidia's
+ * copyright and disclaimer should be included with all code derived
+ * from this source.  -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 
+ */
+
+ /***************************************************************************\
+|*            Modified 1999 by Fredrik Reite (fredrik@reite.com)             *|
+ \***************************************************************************/
+
+
+#ifndef __NV4REF_H__
+#define __NV4REF_H__
+
+/* Magic values to lock/unlock extended regs */
+#define NV_CIO_SR_LOCK_INDEX				     0x0000001F /*       */
+#define NV_CIO_SR_UNLOCK_RW_VALUE                            0x00000057 /*       */
+#define NV_CIO_SR_UNLOCK_RO_VALUE                            0x00000075 /*       */
+#define NV_CIO_SR_LOCK_VALUE                                 0x00000099 /*       */
+
+#define UNLOCK_EXT_MAGIC 0x57
+#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */
+
+#define LOCK_EXT_INDEX 0x6
+
+#define NV_PCRTC_HORIZ_TOTAL                                 0x00
+#define NV_PCRTC_HORIZ_DISPLAY_END                           0x01
+#define NV_PCRTC_HORIZ_BLANK_START                           0x02
+
+#define NV_PCRTC_HORIZ_BLANK_END                             0x03
+#define NV_PCRTC_HORIZ_BLANK_END_EVRA                        7:7
+#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW            6:5
+#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END             4:0
+
+#define NV_PCRTC_HORIZ_RETRACE_START                         0x04
+
+#define NV_PCRTC_HORIZ_RETRACE_END                           0x05
+#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5         7:7
+#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW        6:5
+#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END         4:0
+
+#define NV_PCRTC_VERT_TOTAL                                  0x06
+
+#define NV_PCRTC_OVERFLOW                                    0x07
+#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9               7:7
+#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9                 6:6
+#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9                       5:5
+#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8                     4:4
+#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8                 3:3
+#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8               2:2
+#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8                 1:1
+#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8                       0:0
+
+#define NV_PCRTC_PRESET_ROW_SCAN                             0x08
+
+#define NV_PCRTC_MAX_SCAN_LINE                               0x09
+#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN                   7:7
+#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9                6:6
+#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9            5:5
+#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE                 4:0
+
+#define NV_PCRTC_CURSOR_START                                0x0A
+#define NV_PCRTC_CURSOR_END                                  0x0B
+#define NV_PCRTC_START_ADDR_HIGH                             0x0C
+#define NV_PCRTC_START_ADDR_LOW                              0x0D
+#define NV_PCRTC_CURSOR_LOCATION_HIGH                        0x0E
+#define NV_PCRTC_CURSOR_LOCATION_LOW                         0x0F
+
+#define NV_PCRTC_VERT_RETRACE_START                          0x10
+#define NV_PCRTC_VERT_RETRACE_END                            0x11
+#define NV_PCRTC_VERT_DISPLAY_END                            0x12
+#define NV_PCRTC_OFFSET                                      0x13
+#define NV_PCRTC_UNDERLINE_LOCATION                          0x14
+#define NV_PCRTC_VERT_BLANK_START                            0x15
+#define NV_PCRTC_VERT_BLANK_END                              0x16
+#define NV_PCRTC_MODE_CONTROL                                0x17
+#define NV_PCRTC_LINE_COMPARE                                0x18
+
+/* Extended offset and start address */
+#define NV_PCRTC_REPAINT0                                    0x19
+#define NV_PCRTC_REPAINT0_OFFSET_10_8                        7:5 
+#define NV_PCRTC_REPAINT0_START_ADDR_20_16                   4:0
+
+/* Horizonal extended bits */
+#define NV_PCRTC_HORIZ_EXTRA                                 0x2d
+#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8              4:4
+#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8           3:3
+#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8             2:2
+#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8                   1:1
+#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8                 0:0
+
+/* Assorted extra bits */
+#define NV_PCRTC_EXTRA                                       0x25
+#define NV_PCRTC_EXTRA_OFFSET_11                             5:5
+#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6                     4:4
+#define NV_PCRTC_EXTRA_VERT_BLANK_START_10                   3:3
+#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10                 2:2
+#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10                   1:1
+#define NV_PCRTC_EXTRA_VERT_TOTAL_10                         0:0
+
+/* Controls how much data the refresh fifo requests */
+#define NV_PCRTC_FIFO_CONTROL                                0x1b
+#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN                 7:7
+#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH                   2:0
+#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8                 0x0
+#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32                0x1
+#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64                0x2
+#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128               0x3
+#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256               0x4
+
+/* When the fifo occupancy falls below *twice* the watermark,
+ * the refresh fifo will start to be refilled. If this value is 
+ * too low, you will get junk on the screen. Too high, and performance
+ * will suffer. Watermark in units of 8 bytes
+ */
+#define NV_PCRTC_FIFO                                        0x20
+#define NV_PCRTC_FIFO_RESET                                  7:7
+#define NV_PCRTC_FIFO_WATERMARK                              5:0
+
+/* Various flags */
+#define NV_PCRTC_REPAINT1                                    0x1a
+#define NV_PCRTC_REPAINT1_HSYNC                              7:7
+#define NV_PCRTC_REPAINT1_HYSNC_DISABLE                      0x01
+#define NV_PCRTC_REPAINT1_HYSNC_ENABLE                       0x00
+#define NV_PCRTC_REPAINT1_VSYNC                              6:6
+#define NV_PCRTC_REPAINT1_VYSNC_DISABLE                      0x01
+#define NV_PCRTC_REPAINT1_VYSNC_ENABLE                       0x00
+#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT                    4:4
+#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE             0x01
+#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE            0x00
+#define NV_PCRTC_REPAINT1_LARGE_SCREEN                       2:2 
+#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE               0x01
+#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE                0x00 /* >=1280 */
+#define NV_PCRTC_REPAINT1_PALETTE_WIDTH                      1:1
+#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS                0x00
+#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS                0x01
+
+#define NV_PCRTC_GRCURSOR0                                   0x30
+#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16                  5:0
+
+#define NV_PCRTC_GRCURSOR1                                   0x31
+#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11                  7:3
+#define NV_PCRTC_GRCURSOR1_SCAN_DBL                          1:1
+#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE                  0
+#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE                   1
+#define NV_PCRTC_GRCURSOR1_CURSOR                            0:0
+#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE                    0 
+#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE                     1
+
+/* Controls what the format of the framebuffer is */
+#define NV_PCRTC_PIXEL                       0x28
+#define NV_PCRTC_PIXEL_MODE                  7:7
+#define NV_PCRTC_PIXEL_MODE_TV               0x01
+#define NV_PCRTC_PIXEL_MODE_VGA              0x00
+#define NV_PCRTC_PIXEL_TV_MODE               6:6
+#define NV_PCRTC_PIXEL_TV_MODE_NTSC          0x00
+#define NV_PCRTC_PIXEL_TV_MODE_PAL           0x01
+#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST       5:3
+#define NV_PCRTC_PIXEL_FORMAT                1:0
+#define NV_PCRTC_PIXEL_FORMAT_VGA            0x00
+#define NV_PCRTC_PIXEL_FORMAT_8BPP           0x01
+#define NV_PCRTC_PIXEL_FORMAT_16BPP          0x02
+#define NV_PCRTC_PIXEL_FORMAT_32BPP          0x03
+
+/* RAMDAC registers and fields */
+#define NV_PRAMDAC                            0x00680FFF:0x00680000 /* RW--D */
+#define NV_PRAMDAC_GRCURSOR_START_POS                    0x00680300 /* RW-4R */
+#define NV_PRAMDAC_GRCURSOR_START_POS_X                        11:0 /* RWXSF */
+#define NV_PRAMDAC_GRCURSOR_START_POS_Y                       27:16 /* RWXSF */
+#define NV_PRAMDAC_NVPLL_COEFF                           0x00680500 /* RW-4R */
+#define NV_PRAMDAC_NVPLL_COEFF_MDIV                             7:0 /* RWIUF */
+#define NV_PRAMDAC_NVPLL_COEFF_NDIV                            15:8 /* RWIUF */
+#define NV_PRAMDAC_NVPLL_COEFF_PDIV                           18:16 /* RWIVF */
+#define NV_PRAMDAC_MPLL_COEFF                            0x00680504 /* RW-4R */
+#define NV_PRAMDAC_MPLL_COEFF_MDIV                              7:0 /* RWIUF */
+#define NV_PRAMDAC_MPLL_COEFF_NDIV                             15:8 /* RWIUF */
+#define NV_PRAMDAC_MPLL_COEFF_PDIV                            18:16 /* RWIVF */
+#define NV_PRAMDAC_VPLL_COEFF                            0x00680508 /* RW-4R */
+#define NV_PRAMDAC_VPLL_COEFF_MDIV                              7:0 /* RWIUF */
+#define NV_PRAMDAC_VPLL_COEFF_NDIV                             15:8 /* RWIUF */
+#define NV_PRAMDAC_VPLL_COEFF_PDIV                            18:16 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT                      0x0068050C /* RW-4R */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS                  4:4 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE     0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE      0x00000001 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE                 8:8 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT  0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG     0x00000001 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS               12:12 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE    0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE     0x00000001 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE               16:16 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT  0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG     0x00000001 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS               20:20 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE    0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE     0x00000001 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE               25:24 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL     0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP      0x00000001 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC  0x00000002 /* RW--V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO                28:28 /* RWIVF */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1       0x00000000 /* RWI-V */
+#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2       0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL                       0x00680600 /* RW-4R */
+#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF                     1:0 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF          0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE                     4:4 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA        0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX        0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE                    8:8 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE       0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL         0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE                   12:12 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL       0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL          0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL                 16:16 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF        0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON         0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION                17:17 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM     0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM     0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_BPC                        20:20 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS             0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS             0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP                  24:24 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS         0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN          0x00000001 /* RW--V */
+#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK                28:28 /* RWIVF */
+#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN        0x00000000 /* RWI-V */
+#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS       0x00000001 /* RW--V */
+
+/* Master Control */
+#define NV_PMC                                0x00000FFF:0x00000000 /* RW--D */
+#define NV_PMC_BOOT_0                                    0x00000000 /* R--4R */
+#define NV_PMC_BOOT_0_MINOR_REVISION                            3:0 /* C--VF */
+#define NV_PMC_BOOT_0_MINOR_REVISION_0                   0x00000000 /* C---V */
+#define NV_PMC_BOOT_0_MAJOR_REVISION                            7:4 /* C--VF */
+#define NV_PMC_BOOT_0_MAJOR_REVISION_A                   0x00000000 /* C---V */
+#define NV_PMC_BOOT_0_MAJOR_REVISION_B                   0x00000001 /* ----V */
+#define NV_PMC_BOOT_0_IMPLEMENTATION                           11:8 /* C--VF */
+#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0               0x00000000 /* C---V */
+#define NV_PMC_BOOT_0_ARCHITECTURE                            15:12 /* C--VF */
+#define NV_PMC_BOOT_0_ARCHITECTURE_NV0                   0x00000000 /* ----V */
+#define NV_PMC_BOOT_0_ARCHITECTURE_NV1                   0x00000001 /* ----V */
+#define NV_PMC_BOOT_0_ARCHITECTURE_NV2                   0x00000002 /* ----V */
+#define NV_PMC_BOOT_0_ARCHITECTURE_NV3                   0x00000003 /* ----V */
+#define NV_PMC_BOOT_0_ARCHITECTURE_NV4                   0x00000004 /* C---V */
+#define NV_PMC_BOOT_0_FIB_REVISION                            19:16 /* C--VF */
+#define NV_PMC_BOOT_0_FIB_REVISION_0                     0x00000000 /* C---V */
+#define NV_PMC_BOOT_0_MASK_REVISION                           23:20 /* C--VF */
+#define NV_PMC_BOOT_0_MASK_REVISION_A                    0x00000000 /* C---V */
+#define NV_PMC_BOOT_0_MASK_REVISION_B                    0x00000001 /* ----V */
+#define NV_PMC_BOOT_0_MANUFACTURER                            27:24 /* C--UF */
+#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA                0x00000000 /* C---V */
+#define NV_PMC_BOOT_0_FOUNDRY                                 31:28 /* C--VF */
+#define NV_PMC_BOOT_0_FOUNDRY_SGS                        0x00000000 /* ----V */
+#define NV_PMC_BOOT_0_FOUNDRY_HELIOS                     0x00000001 /* ----V */
+#define NV_PMC_BOOT_0_FOUNDRY_TSMC                       0x00000002 /* C---V */
+#define NV_PMC_INTR_0                                    0x00000100 /* RW-4R */
+#define NV_PMC_INTR_0_PMEDIA                                    4:4 /* R--VF */
+#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING                 0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PMEDIA_PENDING                     0x00000001 /* R---V */
+#define NV_PMC_INTR_0_PFIFO                                     8:8 /* R--VF */
+#define NV_PMC_INTR_0_PFIFO_NOT_PENDING                  0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PFIFO_PENDING                      0x00000001 /* R---V */
+#define NV_PMC_INTR_0_PGRAPH                                  12:12 /* R--VF */
+#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING                 0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PGRAPH_PENDING                     0x00000001 /* R---V */
+#define NV_PMC_INTR_0_PVIDEO                                  16:16 /* R--VF */
+#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING                 0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PVIDEO_PENDING                     0x00000001 /* R---V */
+#define NV_PMC_INTR_0_PTIMER                                  20:20 /* R--VF */
+#define NV_PMC_INTR_0_PTIMER_NOT_PENDING                 0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PTIMER_PENDING                     0x00000001 /* R---V */
+#define NV_PMC_INTR_0_PCRTC                                   24:24 /* R--VF */
+#define NV_PMC_INTR_0_PCRTC_NOT_PENDING                  0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PCRTC_PENDING                      0x00000001 /* R---V */
+#define NV_PMC_INTR_0_PBUS                                    28:28 /* R--VF */
+#define NV_PMC_INTR_0_PBUS_NOT_PENDING                   0x00000000 /* R---V */
+#define NV_PMC_INTR_0_PBUS_PENDING                       0x00000001 /* R---V */
+#define NV_PMC_INTR_0_SOFTWARE                                31:31 /* RWIVF */
+#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PMC_INTR_0_SOFTWARE_PENDING                   0x00000001 /* RW--V */
+#define NV_PMC_INTR_EN_0                                 0x00000140 /* RW-4R */
+#define NV_PMC_INTR_EN_0_INTA                                   1:0 /* RWIVF */
+#define NV_PMC_INTR_EN_0_INTA_DISABLED                   0x00000000 /* RWI-V */
+#define NV_PMC_INTR_EN_0_INTA_HARDWARE                   0x00000001 /* RW--V */
+#define NV_PMC_INTR_EN_0_INTA_SOFTWARE                   0x00000002 /* RW--V */
+#define NV_PMC_INTR_READ_0                               0x00000160 /* R--4R */
+#define NV_PMC_INTR_READ_0_INTA                                 0:0 /* R--VF */
+#define NV_PMC_INTR_READ_0_INTA_LOW                      0x00000000 /* R---V */
+#define NV_PMC_INTR_READ_0_INTA_HIGH                     0x00000001 /* R---V */
+#define NV_PMC_ENABLE                                    0x00000200 /* RW-4R */
+#define NV_PMC_ENABLE_PMEDIA                                    4:4 /* RWIVF */
+#define NV_PMC_ENABLE_PMEDIA_DISABLED                    0x00000000 /* RWI-V */
+#define NV_PMC_ENABLE_PMEDIA_ENABLED                     0x00000001 /* RW--V */
+#define NV_PMC_ENABLE_PFIFO                                     8:8 /* RWIVF */
+#define NV_PMC_ENABLE_PFIFO_DISABLED                     0x00000000 /* RWI-V */
+#define NV_PMC_ENABLE_PFIFO_ENABLED                      0x00000001 /* RW--V */
+#define NV_PMC_ENABLE_PGRAPH                                  12:12 /* RWIVF */
+#define NV_PMC_ENABLE_PGRAPH_DISABLED                    0x00000000 /* RWI-V */
+#define NV_PMC_ENABLE_PGRAPH_ENABLED                     0x00000001 /* RW--V */
+#define NV_PMC_ENABLE_PPMI                                    16:16 /* RWIVF */
+#define NV_PMC_ENABLE_PPMI_DISABLED                      0x00000000 /* RWI-V */
+#define NV_PMC_ENABLE_PPMI_ENABLED                       0x00000001 /* RW--V */
+#define NV_PMC_ENABLE_PFB                                     20:20 /* RWIVF */
+#define NV_PMC_ENABLE_PFB_DISABLED                       0x00000000 /* RW--V */
+#define NV_PMC_ENABLE_PFB_ENABLED                        0x00000001 /* RWI-V */
+#define NV_PMC_ENABLE_PCRTC                                   24:24 /* RWIVF */
+#define NV_PMC_ENABLE_PCRTC_DISABLED                     0x00000000 /* RW--V */
+#define NV_PMC_ENABLE_PCRTC_ENABLED                      0x00000001 /* RWI-V */
+#define NV_PMC_ENABLE_PVIDEO                                  28:28 /* RWIVF */
+#define NV_PMC_ENABLE_PVIDEO_DISABLED                    0x00000000 /* RWI-V */
+#define NV_PMC_ENABLE_PVIDEO_ENABLED                     0x00000001 /* RW--V */
+
+/* dev_timer.ref */
+#define NV_PTIMER                             0x00009FFF:0x00009000 /* RW--D */
+#define NV_PTIMER_INTR_0                                 0x00009100 /* RW-4R */
+#define NV_PTIMER_INTR_0_ALARM                                  0:0 /* RWXVF */
+#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING               0x00000000 /* R---V */
+#define NV_PTIMER_INTR_0_ALARM_PENDING                   0x00000001 /* R---V */
+#define NV_PTIMER_INTR_0_ALARM_RESET                     0x00000001 /* -W--V */
+#define NV_PTIMER_INTR_EN_0                              0x00009140 /* RW-4R */
+#define NV_PTIMER_INTR_EN_0_ALARM                               0:0 /* RWIVF */
+#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED               0x00000000 /* RWI-V */
+#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED                0x00000001 /* RW--V */
+#define NV_PTIMER_NUMERATOR                              0x00009200 /* RW-4R */
+#define NV_PTIMER_NUMERATOR_VALUE                              15:0 /* RWIUF */
+#define NV_PTIMER_NUMERATOR_VALUE_0                      0x00000000 /* RWI-V */
+#define NV_PTIMER_DENOMINATOR                            0x00009210 /* RW-4R */
+#define NV_PTIMER_DENOMINATOR_VALUE                            15:0 /* RWIUF */
+#define NV_PTIMER_DENOMINATOR_VALUE_0                    0x00000000 /* RWI-V */
+#define NV_PTIMER_TIME_0                                 0x00009400 /* RW-4R */
+#define NV_PTIMER_TIME_0_NSEC                                  31:5 /* RWXUF */
+#define NV_PTIMER_TIME_1                                 0x00009410 /* RW-4R */
+#define NV_PTIMER_TIME_1_NSEC                                  28:0 /* RWXUF */
+#define NV_PTIMER_ALARM_0                                0x00009420 /* RW-4R */
+#define NV_PTIMER_ALARM_0_NSEC                                 31:5 /* RWXUF */
+
+/* dev_fifo.ref */
+#define NV_PFIFO                              0x00003FFF:0x00002000 /* RW--D */
+#define NV_PFIFO_DELAY_0                                 0x00002040 /* RW-4R */
+#define NV_PFIFO_DELAY_0_WAIT_RETRY                             9:0 /* RWIUF */
+#define NV_PFIFO_DELAY_0_WAIT_RETRY_0                    0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_TIMESLICE                           0x00002044 /* RW-4R */
+#define NV_PFIFO_DMA_TIMESLICE_SELECT                          16:0 /* RWIUF */
+#define NV_PFIFO_DMA_TIMESLICE_SELECT_1                  0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K                0x00003fff /* RW--V */
+#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K                0x00007fff /* RW--V */
+#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K                0x0000ffff /* RW--V */
+#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K               0x0001ffff /* RW--V */
+#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT                        24:24 /* RWIUF */
+#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED          0x00000000 /* RW--V */
+#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED           0x00000001 /* RWI-V */
+#define NV_PFIFO_PIO_TIMESLICE                           0x00002048 /* RW-4R */
+#define NV_PFIFO_PIO_TIMESLICE_SELECT                          16:0 /* RWIUF */
+#define NV_PFIFO_PIO_TIMESLICE_SELECT_1                  0x00000000 /* RWI-V */
+#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K                0x00003fff /* RW--V */
+#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K                0x00007fff /* RW--V */
+#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K                0x0000ffff /* RW--V */
+#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K               0x0001ffff /* RW--V */
+#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT                        24:24 /* RWIUF */
+#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED          0x00000000 /* RW--V */
+#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED           0x00000001 /* RWI-V */
+#define NV_PFIFO_TIMESLICE                               0x0000204C /* RW-4R */
+#define NV_PFIFO_TIMESLICE_TIMER                               17:0 /* RWIUF */
+#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED                 0x0003FFFF /* RWI-V */
+#define NV_PFIFO_NEXT_CHANNEL                            0x00002050 /* RW-4R */
+#define NV_PFIFO_NEXT_CHANNEL_CHID                              3:0 /* RWXUF */
+#define NV_PFIFO_NEXT_CHANNEL_MODE                              8:8 /* RWXVF */
+#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO                   0x00000000 /* RW--V */
+#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA                   0x00000001 /* RW--V */
+#define NV_PFIFO_NEXT_CHANNEL_SWITCH                          12:12 /* RWIVF */
+#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING         0x00000000 /* RWI-V */
+#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING             0x00000001 /* RW--V */
+#define NV_PFIFO_DEBUG_0                                 0x00002080 /* R--4R */
+#define NV_PFIFO_DEBUG_0_CACHE_ERROR0                           0:0 /* R-XVF */
+#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING        0x00000000 /* R---V */
+#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING            0x00000001 /* R---V */
+#define NV_PFIFO_DEBUG_0_CACHE_ERROR1                           4:4 /* R-XVF */
+#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING        0x00000000 /* R---V */
+#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING            0x00000001 /* R---V */
+#define NV_PFIFO_INTR_0                                  0x00002100 /* RW-4R */
+#define NV_PFIFO_INTR_0_CACHE_ERROR                             0:0 /* RWXVF */
+#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING          0x00000000 /* R---V */
+#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING              0x00000001 /* R---V */
+#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET                0x00000001 /* -W--V */
+#define NV_PFIFO_INTR_0_RUNOUT                                  4:4 /* RWXVF */
+#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING               0x00000000 /* R---V */
+#define NV_PFIFO_INTR_0_RUNOUT_PENDING                   0x00000001 /* R---V */
+#define NV_PFIFO_INTR_0_RUNOUT_RESET                     0x00000001 /* -W--V */
+#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW                         8:8 /* RWXVF */
+#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING      0x00000000 /* R---V */
+#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING          0x00000001 /* R---V */
+#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET            0x00000001 /* -W--V */
+#define NV_PFIFO_INTR_0_DMA_PUSHER                            12:12 /* RWXVF */
+#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING           0x00000000 /* R---V */
+#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING               0x00000001 /* R---V */
+#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET                 0x00000001 /* -W--V */
+#define NV_PFIFO_INTR_0_DMA_PT                                16:16 /* RWXVF */
+#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING               0x00000000 /* R---V */
+#define NV_PFIFO_INTR_0_DMA_PT_PENDING                   0x00000001 /* R---V */
+#define NV_PFIFO_INTR_0_DMA_PT_RESET                     0x00000001 /* -W--V */
+#define NV_PFIFO_INTR_EN_0                               0x00002140 /* RW-4R */
+#define NV_PFIFO_INTR_EN_0_CACHE_ERROR                          0:0 /* RWIVF */
+#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED          0x00000000 /* RWI-V */
+#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED           0x00000001 /* RW--V */
+#define NV_PFIFO_INTR_EN_0_RUNOUT                               4:4 /* RWIVF */
+#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED               0x00000000 /* RWI-V */
+#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED                0x00000001 /* RW--V */
+#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW                      8:8 /* RWIVF */
+#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED      0x00000000 /* RWI-V */
+#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED       0x00000001 /* RW--V */
+#define NV_PFIFO_INTR_EN_0_DMA_PUSHER                         12:12 /* RWIVF */
+#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED           0x00000000 /* RWI-V */
+#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED            0x00000001 /* RW--V */
+#define NV_PFIFO_INTR_EN_0_DMA_PT                             16:16 /* RWIVF */
+#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED               0x00000000 /* RWI-V */
+#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED                0x00000001 /* RW--V */
+#define NV_PFIFO_RAMHT                                   0x00002210 /* RW-4R */
+#define NV_PFIFO_RAMHT_BASE_ADDRESS                             8:4 /* RWIUF */
+#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000                0x00000010 /* RWI-V */
+#define NV_PFIFO_RAMHT_SIZE                                   17:16 /* RWIUF */
+#define NV_PFIFO_RAMHT_SIZE_4K                           0x00000000 /* RWI-V */
+#define NV_PFIFO_RAMHT_SIZE_8K                           0x00000001 /* RW--V */
+#define NV_PFIFO_RAMHT_SIZE_16K                          0x00000002 /* RW--V */
+#define NV_PFIFO_RAMHT_SIZE_32K                          0x00000003 /* RW--V */
+#define NV_PFIFO_RAMHT_SEARCH                                 25:24 /* RWIUF */
+#define NV_PFIFO_RAMHT_SEARCH_16                         0x00000000 /* RWI-V */
+#define NV_PFIFO_RAMHT_SEARCH_32                         0x00000001 /* RW--V */
+#define NV_PFIFO_RAMHT_SEARCH_64                         0x00000002 /* RW--V */
+#define NV_PFIFO_RAMHT_SEARCH_128                        0x00000003 /* RW--V */
+#define NV_PFIFO_RAMFC                                   0x00002214 /* RW-4R */
+#define NV_PFIFO_RAMFC_BASE_ADDRESS                             8:1 /* RWIUF */
+#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000                0x00000088 /* RWI-V */
+#define NV_PFIFO_RAMRO                                   0x00002218 /* RW-4R */
+#define NV_PFIFO_RAMRO_BASE_ADDRESS                             8:1 /* RWIUF */
+#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200                0x00000089 /* RWI-V */
+#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000                0x00000090 /* RW--V */
+#define NV_PFIFO_RAMRO_SIZE                                   16:16 /* RWIVF */
+#define NV_PFIFO_RAMRO_SIZE_512                          0x00000000 /* RWI-V */
+#define NV_PFIFO_RAMRO_SIZE_8K                           0x00000001 /* RW--V */
+#define NV_PFIFO_CACHES                                  0x00002500 /* RW-4R */
+#define NV_PFIFO_CACHES_REASSIGN                                0:0 /* RWIVF */
+#define NV_PFIFO_CACHES_REASSIGN_DISABLED                0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHES_REASSIGN_ENABLED                 0x00000001 /* RW--V */
+#define NV_PFIFO_CACHES_DMA_SUSPEND                             4:4 /* R--VF */
+#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE                 0x00000000 /* R---V */
+#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY                 0x00000001 /* R---V */
+#define NV_PFIFO_MODE                                    0x00002504 /* RW-4R */
+#define NV_PFIFO_MODE_CHANNEL_0                                 0:0 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_0_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_0_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_1                                 1:1 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_1_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_1_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_2                                 2:2 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_2_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_2_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_3                                 3:3 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_3_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_3_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_4                                 4:4 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_4_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_4_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_5                                 5:5 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_5_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_5_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_6                                 6:6 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_6_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_6_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_7                                 7:7 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_7_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_7_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_8                                 8:8 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_8_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_8_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_9                                 9:9 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_9_PIO                      0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_9_DMA                      0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_10                              10:10 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_10_PIO                     0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_10_DMA                     0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_11                              11:11 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_11_PIO                     0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_11_DMA                     0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_12                              12:12 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_12_PIO                     0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_12_DMA                     0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_13                              13:13 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_13_PIO                     0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_13_DMA                     0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_14                              14:14 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_14_PIO                     0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_14_DMA                     0x00000001 /* RW--V */
+#define NV_PFIFO_MODE_CHANNEL_15                              15:15 /* RWIVF */
+#define NV_PFIFO_MODE_CHANNEL_15_PIO                     0x00000000 /* RWI-V */
+#define NV_PFIFO_MODE_CHANNEL_15_DMA                     0x00000001 /* RW--V */
+#define NV_PFIFO_DMA                                     0x00002508 /* RW-4R */
+#define NV_PFIFO_DMA_CHANNEL_0                                  0:0 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_0_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_1                                  1:1 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_1_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_2                                  2:2 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_2_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_3                                  3:3 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_3_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_4                                  4:4 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_4_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_5                                  5:5 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_5_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_6                                  6:6 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_6_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_7                                  7:7 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_7_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_8                                  8:8 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_8_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_9                                  9:9 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING               0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_9_PENDING                   0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_10                               10:10 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING              0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_10_PENDING                  0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_11                               11:11 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING              0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_11_PENDING                  0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_12                               12:12 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING              0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_12_PENDING                  0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_13                               13:13 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING              0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_13_PENDING                  0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_14                               14:14 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING              0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_14_PENDING                  0x00000001 /* RW--V */
+#define NV_PFIFO_DMA_CHANNEL_15                               15:15 /* RWIVF */
+#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING              0x00000000 /* RWI-V */
+#define NV_PFIFO_DMA_CHANNEL_15_PENDING                  0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE                                    0x0000250C /* RW-4R */
+#define NV_PFIFO_SIZE_CHANNEL_0                                 0:0 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_1                                 1:1 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_2                                 2:2 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_3                                 3:3 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_4                                 4:4 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_5                                 5:5 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_6                                 6:6 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_7                                 7:7 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_8                                 8:8 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_9                                 9:9 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES                0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES                0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_10                              10:10 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES               0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES               0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_11                              11:11 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES               0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES               0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_12                              12:12 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES               0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES               0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_13                              13:13 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES               0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES               0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_14                              14:14 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES               0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES               0x00000001 /* RW--V */
+#define NV_PFIFO_SIZE_CHANNEL_15                              15:15 /* RWIVF */
+#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES               0x00000000 /* RWI-V */
+#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES               0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_PUSH0                            0x00003000 /* RW-4R */
+#define NV_PFIFO_CACHE0_PUSH0_ACCESS                            0:0 /* RWIVF */
+#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED            0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED             0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_PUSH0                            0x00003200 /* RW-4R */
+#define NV_PFIFO_CACHE1_PUSH0_ACCESS                            0:0 /* RWIVF */
+#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED            0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED             0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_PUSH1                            0x00003004 /* RW-4R */
+#define NV_PFIFO_CACHE0_PUSH1_CHID                              3:0 /* RWXUF */
+#define NV_PFIFO_CACHE1_PUSH1                            0x00003204 /* RW-4R */
+#define NV_PFIFO_CACHE1_PUSH1_CHID                              3:0 /* RWXUF */
+#define NV_PFIFO_CACHE1_PUSH1_MODE                              8:8 /* RWIVF */
+#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO                   0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA                   0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_PUSH                         0x00003220 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS                         0:0 /* RWIVF */
+#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED         0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED          0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_STATE                          4:4 /* R--VF */
+#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE              0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY              0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER                         8:8 /* R--VF */
+#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY        0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS                       12:12 /* RWIVF */
+#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING          0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED        0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH                        0x00003224 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG                          7:3 /* RWIUF */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES           0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES          0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES          0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES          0x00000003 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES          0x00000004 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES          0x00000005 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES          0x00000006 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES          0x00000007 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES          0x00000008 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES          0x00000009 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES          0x0000000A /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES          0x0000000B /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES         0x0000000C /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES         0x0000000D /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES         0x0000000E /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES         0x0000000F /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES         0x00000010 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES         0x00000011 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES         0x00000012 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES         0x00000013 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES         0x00000014 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES         0x00000015 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES         0x00000016 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES         0x00000017 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES         0x00000018 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES         0x00000019 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES         0x0000001A /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES         0x0000001B /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES         0x0000001C /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES         0x0000001D /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES         0x0000001E /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES         0x0000001F /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE                        15:13 /* RWIUF */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES          0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES          0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES          0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES         0x00000003 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES         0x00000004 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES         0x00000005 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES         0x00000006 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES         0x00000007 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS                    19:16 /* RWIUF */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0             0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1             0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2             0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3             0x00000003 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4             0x00000004 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5             0x00000005 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6             0x00000006 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7             0x00000007 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8             0x00000008 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9             0x00000009 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10            0x0000000A /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11            0x0000000B /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12            0x0000000C /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13            0x0000000D /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14            0x0000000E /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15            0x0000000F /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_PUT                          0x00003240 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET                         28:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_GET                          0x00003244 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_GET_OFFSET                         28:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_STATE                        0x00003228 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_STATE_METHOD                       12:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL                  15:13 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT                28:18 /* RWIUF */
+#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0         0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_STATE_ERROR                       31:30 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE             0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE        0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION       0x00000003 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_INSTANCE                     0x0000322C /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS                   15:0 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_CTL                          0x00003230 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST                         11:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE                    12:12 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT   0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT       0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY                    13:13 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR    0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR        0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE                   17:16 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI          0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP          0x00000003 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO                       31:31 /* RWIUF */
+#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID          0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID            0x00000001 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_LIMIT                        0x00003234 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET                       28:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_TLB_TAG                      0x00003238 /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS                   28:12 /* RWXUF */
+#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE                       0:0 /* RWIUF */
+#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID        0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID          0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_DMA_TLB_PTE                      0x0000323C /* RW-4R */
+#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS             31:12 /* RWXUF */
+#define NV_PFIFO_CACHE0_PULL0                            0x00003050 /* RW-4R */
+#define NV_PFIFO_CACHE0_PULL0_ACCESS                            0:0 /* RWIVF */
+#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED            0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED             0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_PULL0_HASH                              4:4 /* R-XVF */
+#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED             0x00000000 /* R---V */
+#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED                0x00000001 /* R---V */
+#define NV_PFIFO_CACHE0_PULL0_DEVICE                            8:8 /* R-XVF */
+#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE            0x00000000 /* R---V */
+#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE0_PULL0_HASH_STATE                      12:12 /* R-XVF */
+#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE            0x00000000 /* R---V */
+#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_PULL0                            0x00003250 /* RW-4R */
+#define NV_PFIFO_CACHE1_PULL0_ACCESS                            0:0 /* RWIVF */
+#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED            0x00000000 /* RWI-V */
+#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED             0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_PULL0_HASH                              4:4 /* R-XVF */
+#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED             0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED                0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_PULL0_DEVICE                            8:8 /* R-XVF */
+#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE            0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_PULL0_HASH_STATE                      12:12 /* R-XVF */
+#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE            0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE0_PULL1                            0x00003054 /* RW-4R */
+#define NV_PFIFO_CACHE0_PULL1_ENGINE                            1:0 /* RWXUF */
+#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW                  0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS            0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD                 0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_PULL1                            0x00003254 /* RW-4R */
+#define NV_PFIFO_CACHE1_PULL1_ENGINE                            1:0 /* RWXUF */
+#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW                  0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS            0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD                 0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_HASH                             0x00003058 /* RW-4R */
+#define NV_PFIFO_CACHE0_HASH_INSTANCE                          15:0 /* RWXUF */
+#define NV_PFIFO_CACHE0_HASH_VALID                            16:16 /* RWXVF */
+#define NV_PFIFO_CACHE1_HASH                             0x00003258 /* RW-4R */
+#define NV_PFIFO_CACHE1_HASH_INSTANCE                          15:0 /* RWXUF */
+#define NV_PFIFO_CACHE1_HASH_VALID                            16:16 /* RWXVF */
+#define NV_PFIFO_CACHE0_STATUS                           0x00003014 /* R--4R */
+#define NV_PFIFO_CACHE0_STATUS_LOW_MARK                         4:4 /* R--VF */
+#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY        0x00000000 /* R---V */
+#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK                        8:8 /* R--VF */
+#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL        0x00000000 /* R---V */
+#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_STATUS                           0x00003214 /* R--4R */
+#define NV_PFIFO_CACHE1_STATUS_LOW_MARK                         4:4 /* R--VF */
+#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY        0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK                        8:8 /* R--VF */
+#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL        0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL            0x00000001 /* R---V */
+#define NV_PFIFO_CACHE1_STATUS1                          0x00003218 /* R--4R */
+#define NV_PFIFO_CACHE1_STATUS1_RANOUT                          0:0 /* R-XVF */
+#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE             0x00000000 /* R---V */
+#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE              0x00000001 /* R---V */
+#define NV_PFIFO_CACHE0_PUT                              0x00003010 /* RW-4R */
+#define NV_PFIFO_CACHE0_PUT_ADDRESS                             2:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_PUT                              0x00003210 /* RW-4R */
+#define NV_PFIFO_CACHE1_PUT_ADDRESS                             9:2 /* RWXUF */
+#define NV_PFIFO_CACHE0_GET                              0x00003070 /* RW-4R */
+#define NV_PFIFO_CACHE0_GET_ADDRESS                             2:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_GET                              0x00003270 /* RW-4R */
+#define NV_PFIFO_CACHE1_GET_ADDRESS                             9:2 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE                           0x00003080 /* RW-4R */
+#define NV_PFIFO_CACHE0_ENGINE_0                                1:0 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_0_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_0_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_1                                5:4 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_1_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_1_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_2                                9:8 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_2_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_2_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_3                              13:12 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_3_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_3_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_4                              17:16 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_4_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_4_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_5                              21:20 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_5_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_5_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_6                              25:24 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_6_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_6_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_7                              29:28 /* RWXUF */
+#define NV_PFIFO_CACHE0_ENGINE_7_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE0_ENGINE_7_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE                           0x00003280 /* RW-4R */
+#define NV_PFIFO_CACHE1_ENGINE_0                                1:0 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_0_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_0_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_1                                5:4 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_1_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_1_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_2                                9:8 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_2_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_2_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_3                              13:12 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_3_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_3_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_4                              17:16 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_4_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_4_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_5                              21:20 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_5_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_5_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_6                              25:24 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_6_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_6_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_7                              29:28 /* RWXUF */
+#define NV_PFIFO_CACHE1_ENGINE_7_SW                      0x00000000 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS                0x00000001 /* RW--V */
+#define NV_PFIFO_CACHE1_ENGINE_7_DVD                     0x00000002 /* RW--V */
+#define NV_PFIFO_CACHE0_METHOD(i)                (0x00003100+(i)*8) /* RW-4A */
+#define NV_PFIFO_CACHE0_METHOD__SIZE_1                            1 /*       */
+#define NV_PFIFO_CACHE0_METHOD_ADDRESS                         12:2 /* RWXUF */
+#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL                     15:13 /* RWXUF */
+#define NV_PFIFO_CACHE1_METHOD(i)                (0x00003800+(i)*8) /* RW-4A */
+#define NV_PFIFO_CACHE1_METHOD__SIZE_1                          128 /*       */
+#define NV_PFIFO_CACHE1_METHOD_ADDRESS                         12:2 /* RWXUF */
+#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL                     15:13 /* RWXUF */
+#define NV_PFIFO_CACHE1_METHOD_ALIAS(i)          (0x00003C00+(i)*8) /* RW-4A */
+#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1                    128 /*       */
+#define NV_PFIFO_CACHE0_DATA(i)                  (0x00003104+(i)*8) /* RW-4A */
+#define NV_PFIFO_CACHE0_DATA__SIZE_1                              1 /*       */
+#define NV_PFIFO_CACHE0_DATA_VALUE                             31:0 /* RWXVF */
+#define NV_PFIFO_CACHE1_DATA(i)                  (0x00003804+(i)*8) /* RW-4A */
+#define NV_PFIFO_CACHE1_DATA__SIZE_1                            128 /*       */
+#define NV_PFIFO_CACHE1_DATA_VALUE                             31:0 /* RWXVF */
+#define NV_PFIFO_CACHE1_DATA_ALIAS(i)            (0x00003C04+(i)*8) /* RW-4A */
+#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1                      128 /*       */
+#define NV_PFIFO_DEVICE(i)                       (0x00002800+(i)*4) /* R--4A */
+#define NV_PFIFO_DEVICE__SIZE_1                                 128 /*       */
+#define NV_PFIFO_DEVICE_CHID                                    3:0 /* R--UF */
+#define NV_PFIFO_DEVICE_SWITCH                                24:24 /* R--VF */
+#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE               0x00000000 /* R---V */
+#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE                 0x00000001 /* R---V */
+#define NV_PFIFO_RUNOUT_STATUS                           0x00002400 /* R--4R */
+#define NV_PFIFO_RUNOUT_STATUS_RANOUT                           0:0 /* R--VF */
+#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE              0x00000000 /* R---V */
+#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE               0x00000001 /* R---V */
+#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK                         4:4 /* R--VF */
+#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY        0x00000000 /* R---V */
+#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY            0x00000001 /* R---V */
+#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK                        8:8 /* R--VF */
+#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL        0x00000000 /* R---V */
+#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL            0x00000001 /* R---V */
+#define NV_PFIFO_RUNOUT_PUT                              0x00002410 /* RW-4R */
+#define NV_PFIFO_RUNOUT_PUT_ADDRESS                            12:3 /* RWXUF */
+#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0                     8:3 /* RWXUF */
+#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1                    12:3 /* RWXUF */
+#define NV_PFIFO_RUNOUT_GET                              0x00002420 /* RW-4R */
+#define NV_PFIFO_RUNOUT_GET_ADDRESS                            13:3 /* RWXUF */
+/* dev_graphics.ref */
+#define NV_PGRAPH                             0x00401FFF:0x00400000 /* RW--D */
+#define NV_PGRAPH_DEBUG_0                                0x00400080 /* RW-4R */
+#define NV_PGRAPH_DEBUG_1                                0x00400084 /* RW-4R */
+#define NV_PGRAPH_DEBUG_2                                0x00400088 /* RW-4R */
+#define NV_PGRAPH_DEBUG_3                                0x0040008C /* RW-4R */
+#define NV_PGRAPH_INTR                                   0x00400100 /* RW-4R */
+#define NV_PGRAPH_INTR_NOTIFY                                   0:0 /* RWIVF */
+#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING                0x00000000 /* R-I-V */
+#define NV_PGRAPH_INTR_NOTIFY_PENDING                    0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_NOTIFY_RESET                      0x00000001 /* -W--C */
+#define NV_PGRAPH_INTR_MISSING_HW                               4:4 /* RWIVF */
+#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING            0x00000000 /* R-I-V */
+#define NV_PGRAPH_INTR_MISSING_HW_PENDING                0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_MISSING_HW_RESET                  0x00000001 /* -W--C */
+#define NV_PGRAPH_INTR_TLB_PRESENT_A                            8:8 /* RWIVF */
+#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING         0x00000000 /* R-I-V */
+#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING             0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET               0x00000001 /* -W--C */
+#define NV_PGRAPH_INTR_TLB_PRESENT_B                            9:9 /* RWIVF */
+#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING         0x00000000 /* R-I-V */
+#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING             0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET               0x00000001 /* -W--C */
+#define NV_PGRAPH_INTR_CONTEXT_SWITCH                         12:12 /* RWIVF */
+#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING        0x00000000 /* R-I-V */
+#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING            0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET              0x00000001 /* -W--C */
+#define NV_PGRAPH_INTR_BUFFER_NOTIFY                          16:16 /* RWIVF */
+#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING         0x00000000 /* R-I-V */
+#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING             0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET               0x00000001 /* -W--C */
+#define NV_PGRAPH_NSTATUS                                0x00400104 /* RW-4R */
+#define NV_PGRAPH_NSTATUS_STATE_IN_USE                        11:11 /* RWIVF */
+#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING       0x00000000 /* RWI-V */
+#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING           0x00000001 /* RW--V */
+#define NV_PGRAPH_NSTATUS_INVALID_STATE                       12:12 /* RWIVF */
+#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING      0x00000000 /* RWI-V */
+#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING          0x00000001 /* RW--V */
+#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT                        13:13 /* RWIVF */
+#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING       0x00000000 /* RWI-V */
+#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING           0x00000001 /* RW--V */
+#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT                    14:14 /* RWIVF */
+#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING   0x00000000 /* RWI-V */
+#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING       0x00000001 /* RW--V */
+#define NV_PGRAPH_NSOURCE                                0x00400108 /* R--4R */
+#define NV_PGRAPH_NSOURCE_NOTIFICATION                          0:0 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING       0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING           0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_DATA_ERROR                            1:1 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING         0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING             0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR                      2:2 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING   0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING       0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION                       3:3 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING    0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING        0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_LIMIT_COLOR                           4:4 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING        0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING            0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_                           5:5 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING         0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING             0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD                          6:6 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING       0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING           0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION                      7:7 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING   0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING       0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION                      8:8 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING   0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING       0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION                      9:9 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING   0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING       0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION                     10:10 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING    0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING        0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_STATE_INVALID                       11:11 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING      0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING          0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY                       12:12 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING      0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING          0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE                       13:13 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING      0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING          0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_METHOD_CNT                          14:14 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING         0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING             0x00000001 /* R---V */
+#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION                    15:15 /* R-IVF */
+#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING   0x00000000 /* R-I-V */
+#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING       0x00000001 /* R---V */
+#define NV_PGRAPH_INTR_EN                                0x00400140 /* RW-4R */
+#define NV_PGRAPH_INTR_EN_NOTIFY                                0:0 /* RWIVF */
+#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED                0x00000000 /* RWI-V */
+#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED                 0x00000001 /* RW--V */
+#define NV_PGRAPH_INTR_EN_MISSING_HW                            4:4 /* RWIVF */
+#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED            0x00000000 /* RWI-V */
+#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED             0x00000001 /* RW--V */
+#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A                         8:8 /* RWIVF */
+#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED         0x00000000 /* RWI-V */
+#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED          0x00000001 /* RW--V */
+#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B                         9:9 /* RWIVF */
+#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED         0x00000000 /* RWI-V */
+#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED          0x00000001 /* RW--V */
+#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH                      12:12 /* RWIVF */
+#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED        0x00000000 /* RWI-V */
+#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED         0x00000001 /* RW--V */
+#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY                       16:16 /* RWIVF */
+#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED         0x00000000 /* RWI-V */
+#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED          0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1                            0x00400160 /* RW-4R */
+#define NV_PGRAPH_CTX_SWITCH1_GRCLASS                           7:0 /* RWXVF */
+#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY                      12:12 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE         0x00000000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE          0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP                       13:13 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE          0x00000000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE           0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE                         14:14 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE            0x00000000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE             0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG                    17:15 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND   0x00000000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND       0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND     0x00000002 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY       0x00000003 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE   0x00000004 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE     0x00000005 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS                    24:24 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID       0x00000000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID         0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE                 25:25 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID    0x00000000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID      0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET                  31:31 /* CWIVF */
+#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE      0x00000000 /* CWI-V */
+#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED     0x00000001 /* -W--T */
+#define NV_PGRAPH_CTX_SWITCH2                            0x00400164 /* RW-4R */
+#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT                       1:0 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID              0x00 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1              0x01 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1                0x02 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT                     13:8 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID             0x00 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8               0x01 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8          0x02 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8            0x03 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5         0x06 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5         0x07 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5      0x08 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5        0x09 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5           0x0A /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5        0x0B /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5        0x0C /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8         0x0D /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8         0x0E /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16              0x0F /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16           0x10 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16           0x11 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8       0x12 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8       0x13 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32              0x14 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE                 31:16 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID        0x0000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH3                            0x00400168 /* RW-4R */
+#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0                   15:0 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID         0x0000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1                  31:16 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID         0x0000 /* RW--V */
+#define NV_PGRAPH_CTX_SWITCH4                            0x0040016C /* RW-4R */
+#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE                    15:0 /* RWXUF */
+#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID          0x0000 /* RW--V */
+#define NV_PGRAPH_CTX_CACHE1(i)                  (0x00400180+(i)*4) /* RW-4A */
+#define NV_PGRAPH_CTX_CACHE1__SIZE_1                              8 /*       */
+#define NV_PGRAPH_CTX_CACHE1_GRCLASS                            7:0 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY                       12:12 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_USER_CLIP                        13:13 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_SWIZZLE                          14:14 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG                     19:15 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_SPARE1                           20:20 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS                     24:24 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE                  25:25 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE2(i)                  (0x004001a0+(i)*4) /* RW-4A */
+#define NV_PGRAPH_CTX_CACHE2__SIZE_1                              8 /*       */
+#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT                        1:0 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT                      13:8 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE                  31:16 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE3(i)                  (0x004001c0+(i)*4) /* RW-4A */
+#define NV_PGRAPH_CTX_CACHE3__SIZE_1                              8 /*       */
+#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0                    15:0 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1                   31:16 /* RWXVF */
+#define NV_PGRAPH_CTX_CACHE4(i)                  (0x004001e0+(i)*4) /* RW-4A */
+#define NV_PGRAPH_CTX_CACHE4__SIZE_1                              8 /*       */
+#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE                     15:0 /* RWXVF */
+#define NV_PGRAPH_CTX_CONTROL                            0x00400170 /* RW-4R */
+#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME                      1:0 /* RWIVF */
+#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US          0x00000000 /* RWI-V */
+#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US         0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS           0x00000002 /* RW--V */
+#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS          0x00000003 /* RW--V */
+#define NV_PGRAPH_CTX_CONTROL_TIME                              8:8 /* RWIVF */
+#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED               0x00000000 /* RWI-V */
+#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED           0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_CONTROL_CHID                            16:16 /* RWIVF */
+#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID               0x00000000 /* RWI-V */
+#define NV_PGRAPH_CTX_CONTROL_CHID_VALID                 0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_CONTROL_CHANGE                          20:20 /* R--VF */
+#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE         0x00000000 /* R---V */
+#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE           0x00000001 /* R---V */
+#define NV_PGRAPH_CTX_CONTROL_SWITCHING                       24:24 /* RWIVF */
+#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE             0x00000000 /* RWI-V */
+#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY             0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_CONTROL_DEVICE                          28:28 /* RWIVF */
+#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED            0x00000000 /* RWI-V */
+#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED             0x00000001 /* RW--V */
+#define NV_PGRAPH_CTX_USER                               0x00400174 /* RW-4R */
+#define NV_PGRAPH_CTX_USER_SUBCH                              15:13 /* RWIVF */
+#define NV_PGRAPH_CTX_USER_SUBCH_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_CTX_USER_CHID                               27:24 /* RWIVF */
+#define NV_PGRAPH_CTX_USER_CHID_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_FIFO                                   0x00400720 /* RW-4R */
+#define NV_PGRAPH_FIFO_ACCESS                                   0:0 /* RWIVF */
+#define NV_PGRAPH_FIFO_ACCESS_DISABLED                   0x00000000 /* RW--V */
+#define NV_PGRAPH_FIFO_ACCESS_ENABLED                    0x00000001 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_FIFO_0(i)              (0x00400730+(i)*4) /* RW-4A */
+#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1                          4 /*       */
+#define NV_PGRAPH_FFINTFC_FIFO_0_TAG                            0:0 /* RWXVF */
+#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD                0x00000000 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW                0x00000001 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH                          3:1 /* RWXVF */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0                 0x00000000 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1                 0x00000001 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2                 0x00000002 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3                 0x00000003 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4                 0x00000004 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5                 0x00000005 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6                 0x00000006 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7                 0x00000007 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD                          14:4 /* RWXVF */
+#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH         0x00000000 /* RW--V */
+#define NV_PGRAPH_FFINTFC_FIFO_1(i)              (0x00400740+(i)*4) /* RW-4A */
+#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1                          4 /*       */
+#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT                      31:0 /* RWXVF */
+#define NV_PGRAPH_FFINTFC_FIFO_PTR                       0x00400750 /* RW-4R */
+#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE                        2:0 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0               0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ                         6:4 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0                0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_ST2                            0x00400754 /* RW-4R */
+#define NV_PGRAPH_FFINTFC_ST2_STATUS                            0:0 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID             0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID               0x00000001 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_MTHD                             11:1 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH            0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH                           14:12 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0                    0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1                    0x00000001 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2                    0x00000002 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3                    0x00000003 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4                    0x00000004 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5                    0x00000005 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6                    0x00000006 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7                    0x00000007 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID                            18:15 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_1                     0x00000001 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_2                     0x00000002 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_3                     0x00000003 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_4                     0x00000004 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_5                     0x00000005 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_6                     0x00000006 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_7                     0x00000007 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_8                     0x00000008 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_9                     0x00000009 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_10                    0x0000000A /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_11                    0x0000000B /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_12                    0x0000000C /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_13                    0x0000000D /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_14                    0x0000000E /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_15                    0x0000000F /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS                     19:19 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID        0x00000000 /* RWI-V */
+#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID          0x00000001 /* RW--V */
+#define NV_PGRAPH_FFINTFC_ST2_D                          0x00400758 /* RW-4R */
+#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT                       31:0 /* RWIVF */
+#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0               0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATUS                                 0x00400700 /* R--4R */
+#define NV_PGRAPH_STATUS_STATE                                  0:0 /* R-IVF */
+#define NV_PGRAPH_STATUS_STATE_IDLE                      0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_STATE_BUSY                      0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_XY_LOGIC                               4:4 /* R-IVF */
+#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE                   0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY                   0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_FE                                     5:5 /* R-IVF */
+#define NV_PGRAPH_STATUS_FE_IDLE                         0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_FE_BUSY                         0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_RASTERIZER                             6:6 /* R-IVF */
+#define NV_PGRAPH_STATUS_RASTERIZER_IDLE                 0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_RASTERIZER_BUSY                 0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_PORT_NOTIFY                            8:8 /* R-IVF */
+#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE                0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY                0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_PORT_REGISTER                        12:12 /* R-IVF */
+#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE              0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY              0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_PORT_DMA                             16:16 /* R-IVF */
+#define NV_PGRAPH_STATUS_PORT_DMA_IDLE                   0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_PORT_DMA_BUSY                   0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_DMA_ENGINE                           17:17 /* R-IVF */
+#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE                 0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY                 0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_DMA_NOTIFY                           20:20 /* R-IVF */
+#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE                 0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY                 0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY                    21:21 /* R-IVF */
+#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE          0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY          0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_D3D                                  24:24 /* R-IVF */
+#define NV_PGRAPH_STATUS_D3D_IDLE                        0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_D3D_BUSY                        0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_CACHE                                25:25 /* R-IVF */
+#define NV_PGRAPH_STATUS_CACHE_IDLE                      0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_CACHE_BUSY                      0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_LIGHTING                             26:26 /* R-IVF */
+#define NV_PGRAPH_STATUS_LIGHTING_IDLE                   0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_LIGHTING_BUSY                   0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_PREROP                               27:27 /* R-IVF */
+#define NV_PGRAPH_STATUS_PREROP_IDLE                     0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_PREROP_BUSY                     0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_ROP                                  28:28 /* R-IVF */
+#define NV_PGRAPH_STATUS_ROP_IDLE                        0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_ROP_BUSY                        0x00000001 /* R---V */
+#define NV_PGRAPH_STATUS_PORT_USER                            29:29 /* R-IVF */
+#define NV_PGRAPH_STATUS_PORT_USER_IDLE                  0x00000000 /* R-I-V */
+#define NV_PGRAPH_STATUS_PORT_USER_BUSY                  0x00000001 /* R---V */
+#define NV_PGRAPH_TRAPPED_ADDR                           0x00400704 /* R--4R */
+#define NV_PGRAPH_TRAPPED_ADDR_MTHD                            12:2 /* R-XUF */
+#define NV_PGRAPH_TRAPPED_ADDR_SUBCH                          15:13 /* R-XUF */
+#define NV_PGRAPH_TRAPPED_ADDR_CHID                           27:24 /* R-XUF */
+#define NV_PGRAPH_TRAPPED_DATA                           0x00400708 /* R--4R */
+#define NV_PGRAPH_TRAPPED_DATA_VALUE                           31:0 /* R-XVF */
+#define NV_PGRAPH_SURFACE                                0x0040070C /* RW-4R */
+#define NV_PGRAPH_SURFACE_TYPE                                  1:0 /* RWIVF */
+#define NV_PGRAPH_SURFACE_TYPE_INVALID                   0x00000000 /* RWI-V */
+#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE               0x00000001 /* RW--V */
+#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE                   0x00000002 /* RW--V */
+#define NV_PGRAPH_NOTIFY                                 0x00400714 /* RW-4R */
+#define NV_PGRAPH_NOTIFY_BUFFER_REQ                             0:0 /* RWIVF */
+#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING          0x00000000 /* RWI-V */
+#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING              0x00000001 /* RW--V */
+#define NV_PGRAPH_NOTIFY_BUFFER_STYLE                           8:8 /* RWIVF */
+#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY         0x00000000 /* RWI-V */
+#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN  0x00000001 /* RW--V */
+#define NV_PGRAPH_NOTIFY_REQ                                  16:16 /* RWIVF */
+#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_NOTIFY_REQ_PENDING                     0x00000001 /* RW--V */
+#define NV_PGRAPH_NOTIFY_STYLE                                20:20 /* RWIVF */
+#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY                0x00000000 /* RWI-V */
+#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN         0x00000001 /* RW--V */
+#define NV_PGRAPH_BOFFSET(i)                     (0x00400640+(i)*4) /* RW-4A */
+#define NV_PGRAPH_BOFFSET__SIZE_1                                 6 /*       */
+#define NV_PGRAPH_BOFFSET_LINADRS                              23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET_LINADRS_0                      0x00000000 /* RWI-V */
+#define NV_PGRAPH_BOFFSET0                               0x00400640 /* RW-4R */
+#define NV_PGRAPH_BOFFSET0__ALIAS_1            NV_PGRAPH_BOFFSET(0) /*       */
+#define NV_PGRAPH_BOFFSET0_LINADRS                             23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET0_LINADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BOFFSET1                               0x00400644 /* RW-4R */
+#define NV_PGRAPH_BOFFSET1__ALIAS_1            NV_PGRAPH_BOFFSET(1) /*       */
+#define NV_PGRAPH_BOFFSET1_LINADRS                             23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET1_LINADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BOFFSET2                               0x00400648 /* RW-4R */
+#define NV_PGRAPH_BOFFSET2__ALIAS_1            NV_PGRAPH_BOFFSET(2) /*       */
+#define NV_PGRAPH_BOFFSET2_LINADRS                             23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET2_LINADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BOFFSET3                               0x0040064C /* RW-4R */
+#define NV_PGRAPH_BOFFSET3__ALIAS_1            NV_PGRAPH_BOFFSET(3) /*       */
+#define NV_PGRAPH_BOFFSET3_LINADRS                             23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET3_LINADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BOFFSET4                               0x00400650 /* RW-4R */
+#define NV_PGRAPH_BOFFSET4__ALIAS_1            NV_PGRAPH_BOFFSET(4) /*       */
+#define NV_PGRAPH_BOFFSET4_LINADRS                             23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET4_LINADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BOFFSET5                               0x00400654 /* RW-4R */
+#define NV_PGRAPH_BOFFSET5__ALIAS_1            NV_PGRAPH_BOFFSET(5) /*       */
+#define NV_PGRAPH_BOFFSET5_LINADRS                             23:0 /* RWIUF */
+#define NV_PGRAPH_BOFFSET5_LINADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE(i)                       (0x00400658+(i)*4) /* RW-4A */
+#define NV_PGRAPH_BBASE__SIZE_1                                   6 /*       */
+#define NV_PGRAPH_BBASE_LINADRS                                23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE_LINADRS_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE0                                 0x00400658 /* RW-4R */
+#define NV_PGRAPH_BBASE0__ALIAS_1                NV_PGRAPH_BBASE(0) /*       */
+#define NV_PGRAPH_BBASE0_LINADRS                               23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE0_LINADRS_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE1                                 0x0040065c /* RW-4R */
+#define NV_PGRAPH_BBASE1__ALIAS_1                NV_PGRAPH_BBASE(1) /*       */
+#define NV_PGRAPH_BBASE1_LINADRS                               23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE1_LINADRS_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE2                                 0x00400660 /* RW-4R */
+#define NV_PGRAPH_BBASE2__ALIAS_1                NV_PGRAPH_BBASE(2) /*       */
+#define NV_PGRAPH_BBASE2_LINADRS                               23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE2_LINADRS_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE3                                 0x00400664 /* RW-4R */
+#define NV_PGRAPH_BBASE3__ALIAS_1                NV_PGRAPH_BBASE(3) /*       */
+#define NV_PGRAPH_BBASE3_LINADRS                               23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE3_LINADRS_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE4                                 0x00400668 /* RW-4R */
+#define NV_PGRAPH_BBASE4__ALIAS_1                NV_PGRAPH_BBASE(4) /*       */
+#define NV_PGRAPH_BBASE4_LINADRS                               23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE4_LINADRS_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_BBASE5                                 0x0040066C /* RW-4R */
+#define NV_PGRAPH_BBASE5__ALIAS_1                NV_PGRAPH_BBASE(5) /*       */
+#define NV_PGRAPH_BBASE5_LINADRS                               23:0 /* RWIUF */
+#define NV_PGRAPH_BBASE5_LINADRS_0                       0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPITCH(i)                      (0x00400670+(i)*4) /* RW-4A */
+#define NV_PGRAPH_BPITCH__SIZE_1                                  5 /*       */
+#define NV_PGRAPH_BPITCH_VALUE                                 12:0 /* RWIUF */
+#define NV_PGRAPH_BPITCH_VALUE_0                         0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPITCH0                                0x00400670 /* RW-4R */
+#define NV_PGRAPH_BPITCH0__ALIAS_1              NV_PGRAPH_BPITCH(0) /*       */
+#define NV_PGRAPH_BPITCH0_VALUE                                12:0 /* RWIUF */
+#define NV_PGRAPH_BPITCH0_VALUE_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPITCH1                                0x00400674 /* RW-4R */
+#define NV_PGRAPH_BPITCH1__ALIAS_1              NV_PGRAPH_BPITCH(1) /*       */
+#define NV_PGRAPH_BPITCH1_VALUE                                12:0 /* RWIUF */
+#define NV_PGRAPH_BPITCH1_VALUE_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPITCH2                                0x00400678 /* RW-4R */
+#define NV_PGRAPH_BPITCH2__ALIAS_1              NV_PGRAPH_BPITCH(2) /*       */
+#define NV_PGRAPH_BPITCH2_VALUE                                12:0 /* RWIUF */
+#define NV_PGRAPH_BPITCH2_VALUE_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPITCH3                                0x0040067C /* RW-4R */
+#define NV_PGRAPH_BPITCH3__ALIAS_1              NV_PGRAPH_BPITCH(3) /*       */
+#define NV_PGRAPH_BPITCH3_VALUE                                12:0 /* RWIUF */
+#define NV_PGRAPH_BPITCH3_VALUE_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPITCH4                                0x00400680 /* RW-4R */
+#define NV_PGRAPH_BPITCH4__ALIAS_1              NV_PGRAPH_BPITCH(4) /*       */
+#define NV_PGRAPH_BPITCH4_VALUE                                12:0 /* RWIUF */
+#define NV_PGRAPH_BPITCH4_VALUE_0                        0x00000000 /* RWI-V */
+#define NV_PGRAPH_BLIMIT(i)                      (0x00400684+(i)*4) /* RW-4A */
+#define NV_PGRAPH_BLIMIT__SIZE_1                                  6 /*       */
+#define NV_PGRAPH_BLIMIT_VALUE                                 23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT_TYPE                                 31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY                  0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT_TYPE_NULL                       0x00000001 /* RWI-V */
+#define NV_PGRAPH_BLIMIT0                                0x00400684 /* RW-4R */
+#define NV_PGRAPH_BLIMIT0__ALIAS_1              NV_PGRAPH_BLIMIT(0) /*       */
+#define NV_PGRAPH_BLIMIT0_VALUE                                23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT0_TYPE                                31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY                 0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT0_TYPE_NULL                      0x00000001 /* RWI-V */
+#define NV_PGRAPH_BLIMIT1                                0x00400688 /* RW-4R */
+#define NV_PGRAPH_BLIMIT1__ALIAS_1              NV_PGRAPH_BLIMIT(1) /*       */
+#define NV_PGRAPH_BLIMIT1_VALUE                                23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT1_TYPE                                31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY                 0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT1_TYPE_NULL                      0x00000001 /* RWI-V */
+#define NV_PGRAPH_BLIMIT2                                0x0040068c /* RW-4R */
+#define NV_PGRAPH_BLIMIT2__ALIAS_1              NV_PGRAPH_BLIMIT(2) /*       */
+#define NV_PGRAPH_BLIMIT2_VALUE                                23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT2_TYPE                                31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY                 0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT2_TYPE_NULL                      0x00000001 /* RWI-V */
+#define NV_PGRAPH_BLIMIT3                                0x00400690 /* RW-4R */
+#define NV_PGRAPH_BLIMIT3__ALIAS_1              NV_PGRAPH_BLIMIT(3) /*       */
+#define NV_PGRAPH_BLIMIT3_VALUE                                23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT3_TYPE                                31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY                 0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT3_TYPE_NULL                      0x00000001 /* RWI-V */
+#define NV_PGRAPH_BLIMIT4                                0x00400694 /* RW-4R */
+#define NV_PGRAPH_BLIMIT4__ALIAS_1              NV_PGRAPH_BLIMIT(4) /*       */
+#define NV_PGRAPH_BLIMIT4_VALUE                                23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT4_TYPE                                31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY                 0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT4_TYPE_NULL                      0x00000001 /* RWI-V */
+#define NV_PGRAPH_BLIMIT5                                0x00400698 /* RW-4R */
+#define NV_PGRAPH_BLIMIT5__ALIAS_1              NV_PGRAPH_BLIMIT(5) /*       */
+#define NV_PGRAPH_BLIMIT5_VALUE                                23:0 /* RWXUF */
+#define NV_PGRAPH_BLIMIT5_TYPE                                31:31 /* RWIVF */
+#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY                 0x00000000 /* RW--V */
+#define NV_PGRAPH_BLIMIT5_TYPE_NULL                      0x00000001 /* RWI-V */
+#define NV_PGRAPH_BSWIZZLE2                              0x0040069c /* RW-4R */
+#define NV_PGRAPH_BSWIZZLE2_WIDTH                             19:16 /* RWIUF */
+#define NV_PGRAPH_BSWIZZLE2_WIDTH_0                      0x00000000 /* RWI-V */
+#define NV_PGRAPH_BSWIZZLE2_HEIGHT                            27:24 /* RWIUF */
+#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BSWIZZLE5                              0x004006a0 /* RW-4R */
+#define NV_PGRAPH_BSWIZZLE5_WIDTH                             19:16 /* RWIUF */
+#define NV_PGRAPH_BSWIZZLE5_WIDTH_0                      0x00000000 /* RWI-V */
+#define NV_PGRAPH_BSWIZZLE5_HEIGHT                            27:24 /* RWIUF */
+#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL                                 0x00400724 /* RW-4R */
+#define NV_PGRAPH_BPIXEL_DEPTH0                                 3:0 /* RWIVF */
+#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_Y8                       0x00000001 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5        0x00000002 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5        0x00000003 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5                 0x00000004 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5                   0x00000005 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_Y16                      0x00000006 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8        0x00000007 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8      0x00000008 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8    0x00000009 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8    0x0000000a /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8        0x0000000b /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8                 0x0000000c /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_Y32                      0x0000000d /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8               0x0000000e /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8               0x0000000f /* RW--V */ 
+#define NV_PGRAPH_BPIXEL_DEPTH1                                 7:4 /* RWIVF */
+#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_Y8                       0x00000001 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5        0x00000002 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5        0x00000003 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5                 0x00000004 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5                   0x00000005 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_Y16                      0x00000006 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8        0x00000007 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8      0x00000008 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8    0x00000009 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8    0x0000000a /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8        0x0000000b /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8                 0x0000000c /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_Y32                      0x0000000d /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8               0x0000000e /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8               0x0000000f /* RW--V */ 
+#define NV_PGRAPH_BPIXEL_DEPTH2                                11:8 /* RWIVF */
+#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_Y8                       0x00000001 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5        0x00000002 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5        0x00000003 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5                 0x00000004 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5                   0x00000005 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_Y16                      0x00000006 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8        0x00000007 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8      0x00000008 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8    0x00000009 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8    0x0000000a /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8        0x0000000b /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8                 0x0000000c /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_Y32                      0x0000000d /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8               0x0000000e /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8               0x0000000f /* RW--V */ 
+#define NV_PGRAPH_BPIXEL_DEPTH3                               15:12 /* RWIVF */
+#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_Y8                       0x00000001 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5        0x00000002 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5        0x00000003 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5                 0x00000004 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5                   0x00000005 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_Y16                      0x00000006 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8        0x00000007 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8      0x00000008 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8    0x00000009 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8    0x0000000a /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8        0x0000000b /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8                 0x0000000c /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_Y32                      0x0000000d /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8               0x0000000e /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8               0x0000000f /* RW--V */ 
+#define NV_PGRAPH_BPIXEL_DEPTH4                               19:16 /* RWIVF */
+#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_Y8                       0x00000001 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5        0x00000002 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5        0x00000003 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5                 0x00000004 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5                   0x00000005 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_Y16                      0x00000006 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8        0x00000007 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8      0x00000008 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8    0x00000009 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8    0x0000000a /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8        0x0000000b /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8                 0x0000000c /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_Y32                      0x0000000d /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8               0x0000000e /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8               0x0000000f /* RW--V */ 
+#define NV_PGRAPH_BPIXEL_DEPTH5                               23:20 /* RWIVF */
+#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_Y8                       0x00000001 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5        0x00000002 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5        0x00000003 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5                 0x00000004 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5                   0x00000005 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_Y16                      0x00000006 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8        0x00000007 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8      0x00000008 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8    0x00000009 /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8    0x0000000a /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8        0x0000000b /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8                 0x0000000c /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_Y32                      0x0000000d /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8               0x0000000e /* RW--V */
+#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8               0x0000000f /* RW--V */ 
+#define NV_PGRAPH_LIMIT_VIOL_PIX                         0x00400610 /* RW-4R */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS                          23:0 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT                         29:29 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL            0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL               0x00000001 /* RW--V */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT                        30:30 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL           0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL              0x00000001 /* RW--V */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW                       31:31 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL          0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL             0x00000001 /* RW--V */
+#define NV_PGRAPH_LIMIT_VIOL_Z                           0x00400614 /* RW-4R */
+#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS                            23:0 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0                    0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT                          30:30 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL             0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL                0x00000001 /* RW--V */
+#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW                         31:31 /* RWIVF */
+#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL            0x00000000 /* RWI-V */
+#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL               0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE                                  0x00400710 /* RW-4R */
+#define NV_PGRAPH_STATE_BUFFER_0                                0:0 /* RWIVF */
+#define NV_PGRAPH_STATE_BUFFER_0_INVALID                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_BUFFER_0_VALID                   0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_BUFFER_1                                1:1 /* RWIVF */
+#define NV_PGRAPH_STATE_BUFFER_1_INVALID                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_BUFFER_1_VALID                   0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_BUFFER_2                                2:2 /* RWIVF */
+#define NV_PGRAPH_STATE_BUFFER_2_INVALID                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_BUFFER_2_VALID                   0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_BUFFER_3                                3:3 /* RWIVF */
+#define NV_PGRAPH_STATE_BUFFER_3_INVALID                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_BUFFER_3_VALID                   0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_BUFFER_4                                4:4 /* RWIVF */
+#define NV_PGRAPH_STATE_BUFFER_4_INVALID                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_BUFFER_4_VALID                   0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_BUFFER_5                                5:5 /* RWIVF */
+#define NV_PGRAPH_STATE_BUFFER_5_INVALID                 0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_BUFFER_5_VALID                   0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PITCH_0                                 8:8 /* RWIVF */
+#define NV_PGRAPH_STATE_PITCH_0_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PITCH_0_VALID                    0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PITCH_1                                 9:9 /* RWIVF */
+#define NV_PGRAPH_STATE_PITCH_1_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PITCH_1_VALID                    0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PITCH_2                               10:10 /* RWIVF */
+#define NV_PGRAPH_STATE_PITCH_2_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PITCH_2_VALID                    0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PITCH_3                               11:11 /* RWIVF */
+#define NV_PGRAPH_STATE_PITCH_3_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PITCH_3_VALID                    0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PITCH_4                               12:12 /* RWIVF */
+#define NV_PGRAPH_STATE_PITCH_4_INVALID                  0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PITCH_4_VALID                    0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_CHROMA_COLOR                          16:16 /* RWIVF */
+#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID             0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID               0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_CHROMA_COLORFMT                       17:17 /* RWIVF */
+#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID          0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID            0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_CPATTERN_COLORFMT                     20:20 /* RWIVF */
+#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID        0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID          0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_CPATTERN_MONOFMT                      21:21 /* RWIVF */
+#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID         0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID           0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_CPATTERN_SELECT                       22:22 /* RWIVF */
+#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID          0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID            0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PATTERN_COLOR0                        24:24 /* RWIVF */
+#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID           0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID             0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PATTERN_COLOR1                        25:25 /* RWIVF */
+#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID           0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID             0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PATTERN_PATT0                         26:26 /* RWIVF */
+#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID            0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID              0x00000001 /* RW--V */
+#define NV_PGRAPH_STATE_PATTERN_PATT1                         27:27 /* RWIVF */
+#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID            0x00000000 /* RWI-V */
+#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID              0x00000001 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX                            0x00400728 /* RW-4R */
+#define NV_PGRAPH_CACHE_INDEX_BANK                              2:2 /* RWXVF */
+#define NV_PGRAPH_CACHE_INDEX_BANK_10                    0x00000000 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX_BANK_32                    0x00000001 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX_ADRS                             12:3 /* RWXVF */
+#define NV_PGRAPH_CACHE_INDEX_ADRS_0                     0x00000000 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX_ADRS_1024                  0x00000400 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX_OP                              14:13 /* RWXVF */
+#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE                0x00000000 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE                0x00000001 /* RW--V */
+#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX                0x00000002 /* RW--V */
+#define NV_PGRAPH_CACHE_RAM                              0x0040072c /* RW-4R */
+#define NV_PGRAPH_CACHE_RAM_VALUE                              31:0 /* RWXVF */
+#define NV_PGRAPH_DMA_PITCH                              0x00400760 /* RW-4R */
+#define NV_PGRAPH_DMA_PITCH_S0                                 15:0 /* RWXSF */
+#define NV_PGRAPH_DMA_PITCH_S1                                31:16 /* RWXSF */
+#define NV_PGRAPH_DVD_COLORFMT                           0x00400764 /* RW-4R */
+#define NV_PGRAPH_DVD_COLORFMT_IMAGE                            5:0 /* RWNVF */
+#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID            0x00 /* RWN-V */
+#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8      0x12 /* RW--V */
+#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8      0x13 /* RW--V */
+#define NV_PGRAPH_DVD_COLORFMT_OVLY                             9:8 /* RWNVF */
+#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID             0x00 /* RWN-V */
+#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8         0x01 /* RW--V */
+#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6   0x02 /* RW--V */
+#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT         0x03 /* RW--V */
+#define NV_PGRAPH_SCALED_FORMAT                          0x00400768 /* RW-4R */
+#define NV_PGRAPH_SCALED_FORMAT_ORIGIN                        17:16 /* RWIVF */
+#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID           0x00000000 /* RWI-V */
+#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER            0x00000001 /* RW--V */
+#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER            0x00000002 /* RW--V */
+#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR                  24:24 /* RWIVF */
+#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH         0x00000000 /* RWI-V */
+#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH         0x00000001 /* RW--V */
+#define NV_PGRAPH_PATT_COLOR0                            0x00400800 /* RW-4R */
+#define NV_PGRAPH_PATT_COLOR0_VALUE                            31:0 /* RWXUF */
+#define NV_PGRAPH_PATT_COLOR1                            0x00400804 /* RW-4R */
+#define NV_PGRAPH_PATT_COLOR1_VALUE                            31:0 /* RWXUF */
+#define NV_PGRAPH_PATT_COLORRAM(i)               (0x00400900+(i)*4) /* R--4A */
+#define NV_PGRAPH_PATT_COLORRAM__SIZE_1                          64 /*       */
+#define NV_PGRAPH_PATT_COLORRAM_VALUE                          23:0 /* R--UF */
+#define NV_PGRAPH_PATTERN(i)                     (0x00400808+(i)*4) /* RW-4A */
+#define NV_PGRAPH_PATTERN__SIZE_1                                 2 /*       */
+#define NV_PGRAPH_PATTERN_BITMAP                               31:0 /* RWXVF */
+#define NV_PGRAPH_PATTERN_SHAPE                          0x00400810 /* RW-4R */
+#define NV_PGRAPH_PATTERN_SHAPE_VALUE                           1:0 /* RWXVF */
+#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y              0x00000000 /* RW--V */
+#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y             0x00000001 /* RW--V */
+#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y             0x00000002 /* RW--V */
+#define NV_PGRAPH_PATTERN_SHAPE_SELECT                          4:4 /* RWXVF */
+#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR            0x00000000 /* RW--V */
+#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR         0x00000001 /* RW--V */
+#define NV_PGRAPH_MONO_COLOR0                            0x00400600 /* RW-4R */
+#define NV_PGRAPH_MONO_COLOR0_VALUE                            31:0 /* RWXUF */
+#define NV_PGRAPH_ROP3                                   0x00400604 /* RW-4R */
+#define NV_PGRAPH_ROP3_VALUE                                    7:0 /* RWXVF */
+#define NV_PGRAPH_CHROMA                                 0x00400814 /* RW-4R */
+#define NV_PGRAPH_CHROMA_VALUE                                 31:0 /* RWXUF */
+#define NV_PGRAPH_BETA_AND                               0x00400608 /* RW-4R */
+#define NV_PGRAPH_BETA_AND_VALUE_FRACTION                     30:23 /* RWXUF */
+#define NV_PGRAPH_BETA_PREMULT                           0x0040060c /* RW-4R */
+#define NV_PGRAPH_BETA_PREMULT_VALUE                           31:0 /* RWXUF */
+#define NV_PGRAPH_CONTROL0                               0x00400818 /* RW-4R */
+#define NV_PGRAPH_CONTROL1                               0x0040081c /* RW-4R */
+#define NV_PGRAPH_CONTROL2                               0x00400820 /* RW-4R */
+#define NV_PGRAPH_BLEND                                  0x00400824 /* RW-4R */
+#define NV_PGRAPH_DPRAM_INDEX                            0x00400828 /* RW-4R */
+#define NV_PGRAPH_DPRAM_INDEX_ADRS                              6:0 /* RWIVF */
+#define NV_PGRAPH_DPRAM_INDEX_ADRS_0                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT                           10:8 /* RWIVF */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0              0x00000000 /* RWI-V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1              0x00000001 /* RW--V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0              0x00000002 /* RW--V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1              0x00000003 /* RW--V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0                0x00000004 /* RW--V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1                0x00000005 /* RW--V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0             0x00000006 /* RW--V */
+#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1             0x00000007 /* RW--V */
+#define NV_PGRAPH_DPRAM_DATA                             0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_DATA_VALUE                             31:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_ADRS_0                           0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1        NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_ADRS_0_VALUE                           19:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_ADRS_1                           0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1        NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_ADRS_1_VALUE                           19:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_DATA_0                           0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1        NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_DATA_0_VALUE                           31:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_DATA_1                           0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1        NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_DATA_1_VALUE                           31:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_WE_0                             0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1          NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_WE_0_VALUE                             23:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_WE_1                             0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1          NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_WE_1_VALUE                             23:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_ALPHA_0                          0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1       NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE                          31:0 /* RWXVF */
+#define NV_PGRAPH_DPRAM_ALPHA_1                          0x0040082c /* RW-4R */
+#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1       NV_PGRAPH_DPRAM_DATA /*       */
+#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE                          31:0 /* RWXVF */
+#define NV_PGRAPH_STORED_FMT                             0x00400830 /* RW-4R */
+#define NV_PGRAPH_STORED_FMT_MONO0                              5:0 /* RWXVF */
+#define NV_PGRAPH_STORED_FMT_PATT0                             13:8 /* RWXVF */
+#define NV_PGRAPH_STORED_FMT_PATT1                            21:16 /* RWXVF */
+#define NV_PGRAPH_STORED_FMT_CHROMA                           29:24 /* RWXVF */
+#define NV_PGRAPH_FORMATS                                0x00400618 /* RW-4R */
+#define NV_PGRAPH_FORMATS_ROP                                   2:0 /* R-XVF */
+#define NV_PGRAPH_FORMATS_ROP_Y8                         0x00000000 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_RGB15                      0x00000001 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_RGB16                      0x00000002 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_Y16                        0x00000003 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_INVALID                    0x00000004 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_RGB24                      0x00000005 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_RGB30                      0x00000006 /* -W--V */
+#define NV_PGRAPH_FORMATS_ROP_Y32                        0x00000007 /* -W--V */
+#define NV_PGRAPH_FORMATS_SRC                                   9:4 /* R-XVF */
+#define NV_PGRAPH_FORMATS_SRC_INVALID                    0x00000000 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_Y8                      0x00000001 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8                 0x00000002 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8                   0x00000003 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5                0x00000006 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5                0x00000007 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5             0x00000008 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5               0x00000009 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5                  0x0000000A /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5               0x0000000B /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5               0x0000000C /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8                0x0000000D /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8                0x0000000E /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_Y16                     0x0000000F /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16                  0x00000010 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16                  0x00000011 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8              0x00000012 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8              0x00000013 /* RW--V */
+#define NV_PGRAPH_FORMATS_SRC_LE_Y32                     0x00000014 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB                                  15:12 /* R-XVF */
+#define NV_PGRAPH_FORMATS_FB_INVALID                     0x00000000 /* RWI-V */
+#define NV_PGRAPH_FORMATS_FB_Y8                          0x00000001 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5           0x00000002 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5           0x00000003 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_A1R5G5B5                    0x00000004 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_R5G6B5                      0x00000005 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_Y16                         0x00000006 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8           0x00000007 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8         0x00000008 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8       0x00000009 /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8       0x0000000a /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8           0x0000000b /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_A8R8G8B8                    0x0000000c /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_Y32                         0x0000000d /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8                  0x0000000e /* RW--V */
+#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8                  0x0000000f /* RW--V */ 
+#define NV_PGRAPH_ABS_X_RAM(i)                   (0x00400400+(i)*4) /* RW-4A */
+#define NV_PGRAPH_ABS_X_RAM__SIZE_1                              32 /*       */
+#define NV_PGRAPH_ABS_X_RAM_VALUE                              31:0 /* RWXUF */
+#define NV_PGRAPH_X_RAM_BPORT(i)                 (0x00400c00+(i)*4) /* R--4A */
+#define NV_PGRAPH_X_RAM_BPORT__SIZE_1                            32 /*       */
+#define NV_PGRAPH_X_RAM_BPORT_VALUE                            31:0 /* R--UF */
+#define NV_PGRAPH_ABS_Y_RAM(i)                   (0x00400480+(i)*4) /* RW-4A */
+#define NV_PGRAPH_ABS_Y_RAM__SIZE_1                              32 /*       */
+#define NV_PGRAPH_ABS_Y_RAM_VALUE                              31:0 /* RWXUF */
+#define NV_PGRAPH_Y_RAM_BPORT(i)                 (0x00400c80+(i)*4) /* R--4A */
+#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1                            32 /*       */
+#define NV_PGRAPH_Y_RAM_BPORT_VALUE                            31:0 /* R--UF */
+#define NV_PGRAPH_XY_LOGIC_MISC0                         0x00400514 /* RW-4R */
+#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER                       17:0 /* RWBUF */
+#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0               0x00000000 /* RWB-V */
+#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION                    20:20 /* RWVVF */
+#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO       0x00000000 /* RWV-V */
+#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX                        31:28 /* RWBUF */
+#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0                 0x00000000 /* RWB-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1                         0x00400518 /* RW-4R */
+#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL                        0:0 /* RWNVF */
+#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED          0x00000000 /* RWN-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE            0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX                      4:4 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL       0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY                      5:5 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL       0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX                    12:12 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX         0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX      0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX                    16:16 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX         0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX      0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA                    20:20 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX       0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX      0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC2                         0x0040051C /* RW-4R */
+#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF                        0:0 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE         0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX                      4:4 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL       0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY                      5:5 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL       0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX                    12:12 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX         0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX      0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX                    16:16 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX         0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX      0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA                    20:20 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX       0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX      0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3                         0x00400520 /* RW-4R */
+#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0                     0:0 /* RWXVF */
+#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL         0x00000000 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE         0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY                   4:4 /* RWXVF */
+#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL       0x00000000 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE       0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX                      8:8 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL          0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE          0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG                     12:12 /* RWIVF */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL           0x00000000 /* RWI-V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE           0x00000001 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX                    22:16 /* RWXUF */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0             0x00000000 /* RW--V */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX                   30:24 /* RWXUF */
+#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0            0x00000000 /* RW--V */
+#define NV_PGRAPH_X_MISC                                 0x00400500 /* RW-4R */
+#define NV_PGRAPH_X_MISC_BIT33_0                                0:0 /* RWNVF */
+#define NV_PGRAPH_X_MISC_BIT33_0_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_BIT33_1                                1:1 /* RWNVF */
+#define NV_PGRAPH_X_MISC_BIT33_1_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_BIT33_2                                2:2 /* RWNVF */
+#define NV_PGRAPH_X_MISC_BIT33_2_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_BIT33_3                                3:3 /* RWNVF */
+#define NV_PGRAPH_X_MISC_BIT33_3_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_RANGE_0                                4:4 /* RWNVF */
+#define NV_PGRAPH_X_MISC_RANGE_0_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_RANGE_1                                5:5 /* RWNVF */
+#define NV_PGRAPH_X_MISC_RANGE_1_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_RANGE_2                                6:6 /* RWNVF */
+#define NV_PGRAPH_X_MISC_RANGE_2_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_RANGE_3                                7:7 /* RWNVF */
+#define NV_PGRAPH_X_MISC_RANGE_3_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_X_MISC_ADDER_OUTPUT                         29:28 /* RWXVF */
+#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0               0x00000000 /* RW--V */
+#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0               0x00000001 /* RW--V */
+#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0               0x00000002 /* RW--V */
+#define NV_PGRAPH_Y_MISC                                 0x00400504 /* RW-4R */
+#define NV_PGRAPH_Y_MISC_BIT33_0                                0:0 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_BIT33_0_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_BIT33_1                                1:1 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_BIT33_1_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_BIT33_2                                2:2 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_BIT33_2_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_BIT33_3                                3:3 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_BIT33_3_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_RANGE_0                                4:4 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_RANGE_0_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_RANGE_1                                5:5 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_RANGE_1_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_RANGE_2                                6:6 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_RANGE_2_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_RANGE_3                                7:7 /* RWNVF */
+#define NV_PGRAPH_Y_MISC_RANGE_3_0                       0x00000000 /* RWN-V */
+#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT                         29:28 /* RWXVF */
+#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0               0x00000000 /* RW--V */
+#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0               0x00000001 /* RW--V */
+#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0               0x00000002 /* RW--V */
+#define NV_PGRAPH_ABS_UCLIP_XMIN                         0x0040053C /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE                         15:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIP_XMAX                         0x00400544 /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE                         17:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIP_YMIN                         0x00400540 /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE                         15:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIP_YMAX                         0x00400548 /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE                         17:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIPA_XMIN                        0x00400560 /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE                        15:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIPA_XMAX                        0x00400568 /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE                        17:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIPA_YMIN                        0x00400564 /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE                        15:0 /* RWXSF */
+#define NV_PGRAPH_ABS_UCLIPA_YMAX                        0x0040056C /* RW-4R */
+#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE                        17:0 /* RWXSF */
+#define NV_PGRAPH_SOURCE_COLOR                           0x0040050C /* RW-4R */
+#define NV_PGRAPH_SOURCE_COLOR_VALUE                           31:0 /* RWNVF */
+#define NV_PGRAPH_SOURCE_COLOR_VALUE_0                   0x00000000 /* RWN-V */
+#define NV_PGRAPH_VALID1                                 0x00400508 /* RW-4R */
+#define NV_PGRAPH_VALID1_VLD                                   22:0 /* RWNVF */
+#define NV_PGRAPH_VALID1_VLD_0                           0x00000000 /* RWN-V */
+#define NV_PGRAPH_VALID1_CLIP_MIN                             28:28 /* RWIVF */
+#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR               0x00000000 /* RWI-V */
+#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY                   0x00000001 /* RW--V */
+#define NV_PGRAPH_VALID1_CLIPA_MIN                            29:29 /* RWIVF */
+#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR              0x00000000 /* RWI-V */
+#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY                  0x00000001 /* RW--V */
+#define NV_PGRAPH_VALID1_CLIP_MAX                             30:30 /* RWIVF */
+#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR               0x00000000 /* RWI-V */
+#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY                   0x00000001 /* RW--V */
+#define NV_PGRAPH_VALID1_CLIPA_MAX                            31:31 /* RWIVF */
+#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR              0x00000000 /* RWI-V */
+#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY                  0x00000001 /* RW--V */
+#define NV_PGRAPH_VALID2                                 0x00400578 /* RW-4R */
+#define NV_PGRAPH_VALID2_VLD2                                  28:0 /* RWNVF */
+#define NV_PGRAPH_VALID2_VLD2_0                          0x00000000 /* RWN-V */
+#define NV_PGRAPH_ABS_ICLIP_XMAX                         0x00400534 /* RW-4R */
+#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE                         17:0 /* RWXSF */
+#define NV_PGRAPH_ABS_ICLIP_YMAX                         0x00400538 /* RW-4R */
+#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE                         17:0 /* RWXSF */
+#define NV_PGRAPH_CLIPX_0                                0x00400524 /* RW-4R */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MIN                             1:0 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MAX                             3:2 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MIN                             5:4 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MAX                             7:6 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MIN                             9:8 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MAX                           11:10 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MIN                           13:12 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MAX                           15:14 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MIN                           17:16 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MAX                           19:18 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MIN                           21:20 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MAX                           23:22 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MIN                           25:24 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MAX                           27:26 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MIN                           29:28 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MAX                           31:30 /* RWNVF */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1                                0x00400528 /* RW-4R */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MIN                             1:0 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MAX                             3:2 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MIN                             5:4 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MAX                             7:6 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MIN                            9:8 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MAX                          11:10 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MIN                          13:12 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MAX                          15:14 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MIN                          17:16 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MAX                          19:18 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MIN                          21:20 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MAX                          23:22 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MIN                          25:24 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MAX                          27:26 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MIN                          29:28 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MAX                          31:30 /* RWNVF */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0                                0x0040052c /* RW-4R */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MIN                             1:0 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MAX                             3:2 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MIN                             5:4 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MAX                             7:6 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MIN                             9:8 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MAX                           11:10 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MIN                           13:12 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MAX                           15:14 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MIN                           17:16 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MAX                           19:18 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MIN                           21:20 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MAX                           23:22 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MIN                           25:24 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MAX                           27:26 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MIN                           29:28 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MAX                           31:30 /* RWNVF */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1                                0x00400530 /* RW-4R */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MIN                             1:0 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MAX                             3:2 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MIN                             5:4 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MAX                             7:6 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT                   0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT                   0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MIN                            9:8 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MAX                          11:10 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MIN                          13:12 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ                   0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MAX                          15:14 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MIN                          17:16 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MAX                          19:18 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MIN                          21:20 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MAX                          23:22 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MIN                          25:24 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MAX                          27:26 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MIN                          29:28 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MAX                          31:30 /* RWNVF */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT                  0x00000000 /* RW--V */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT                  0x00000001 /* RWN-V */
+#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ                  0x00000002 /* RW--V */
+#define NV_PGRAPH_MISC24_0                               0x00400510 /* RW-4R */
+#define NV_PGRAPH_MISC24_0_VALUE                               23:0 /* RWXUF */
+#define NV_PGRAPH_MISC24_1                               0x00400570 /* RW-4R */
+#define NV_PGRAPH_MISC24_1_VALUE                               23:0 /* RWXUF */
+#define NV_PGRAPH_MISC24_2                               0x00400574 /* RW-4R */
+#define NV_PGRAPH_MISC24_2_VALUE                               23:0 /* RWXUF */
+#define NV_PGRAPH_PASSTHRU_0                             0x0040057C /* RW-4R */
+#define NV_PGRAPH_PASSTHRU_0_VALUE                             31:0 /* RWXUF */
+#define NV_PGRAPH_PASSTHRU_1                             0x00400580 /* RW-4R */
+#define NV_PGRAPH_PASSTHRU_1_VALUE                             31:0 /* RWXUF */
+#define NV_PGRAPH_PASSTHRU_2                             0x00400584 /* RW-4R */
+#define NV_PGRAPH_PASSTHRU_2_VALUE                             31:0 /* RWXUF */
+#define NV_PGRAPH_U_RAM(i)                       (0x00400d00+(i)*4) /* RW-4A */
+#define NV_PGRAPH_U_RAM__SIZE_1                                  16 /*       */
+#define NV_PGRAPH_U_RAM_VALUE                                  31:6 /* RWXFF */
+#define NV_PGRAPH_V_RAM(i)                       (0x00400d40+(i)*4) /* RW-4A */
+#define NV_PGRAPH_V_RAM__SIZE_1                                  16 /*       */
+#define NV_PGRAPH_V_RAM_VALUE                                  31:6 /* RWXFF */
+#define NV_PGRAPH_M_RAM(i)                       (0x00400d80+(i)*4) /* RW-4A */
+#define NV_PGRAPH_M_RAM__SIZE_1                                  16 /*       */
+#define NV_PGRAPH_M_RAM_VALUE                                  31:6 /* RWXFF */
+#define NV_PGRAPH_DMA_START_0                            0x00401000 /* RW-4R */
+#define NV_PGRAPH_DMA_START_0_VALUE                            31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_START_1                            0x00401004 /* RW-4R */
+#define NV_PGRAPH_DMA_START_1_VALUE                            31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_LENGTH                             0x00401008 /* RW-4R */
+#define NV_PGRAPH_DMA_LENGTH_VALUE                             21:0 /* RWXUF */
+#define NV_PGRAPH_DMA_MISC                               0x0040100C /* RW-4R */
+#define NV_PGRAPH_DMA_MISC_COUNT                               15:0 /* RWXUF */
+#define NV_PGRAPH_DMA_MISC_FMT_SRC                            18:16 /* RWXVF */
+#define NV_PGRAPH_DMA_MISC_FMT_DST                            22:20 /* RWXVF */
+#define NV_PGRAPH_DMA_DATA_0                             0x00401020 /* RW-4R */
+#define NV_PGRAPH_DMA_DATA_0_VALUE                             31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_DATA_1                             0x00401024 /* RW-4R */
+#define NV_PGRAPH_DMA_DATA_1_VALUE                             31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_RM                                 0x00401030 /* RW-4R */
+#define NV_PGRAPH_DMA_RM_ASSIST_A                               0:0 /* RWIVF */
+#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING            0x00000000 /* R-I-V */
+#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING                0x00000001 /* R---V */
+#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET                  0x00000001 /* -W--C */
+#define NV_PGRAPH_DMA_RM_ASSIST_B                               1:1 /* RWIVF */
+#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING            0x00000000 /* R-I-V */
+#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING                0x00000001 /* R---V */
+#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET                  0x00000001 /* -W--C */
+#define NV_PGRAPH_DMA_RM_WRITE_REQ                              4:4 /* CWIVF */
+#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING           0x00000000 /* CWI-V */
+#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING               0x00000001 /* -W--T */
+#define NV_PGRAPH_DMA_A_XLATE_INST                       0x00401040 /* RW-4R */
+#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE                       15:0 /* RWXUF */
+#define NV_PGRAPH_DMA_A_CONTROL                          0x00401044 /* RW-4R */
+#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE                    12:12 /* RWIVF */
+#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT   0x00000000 /* RWI-V */
+#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT       0x00000001 /* RW--V */
+#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY                    13:13 /* RWXVF */
+#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR    0x00000000 /* RW--V */
+#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR        0x00000001 /* RW--V */
+#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE                   17:16 /* RWXUF */
+#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM          0x00000000 /* RW--V */
+#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI          0x00000002 /* RW--V */
+#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP          0x00000003 /* RW--V */
+#define NV_PGRAPH_DMA_A_CONTROL_ADJUST                        31:20 /* RWXUF */
+#define NV_PGRAPH_DMA_A_LIMIT                            0x00401048 /* RW-4R */
+#define NV_PGRAPH_DMA_A_LIMIT_OFFSET                           31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_A_TLB_PTE                          0x0040104C /* RW-4R */
+#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS                          1:1 /* RWXVF */
+#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY         0x00000000 /* RW--V */
+#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE        0x00000001 /* RW--V */
+#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS                 31:12 /* RWXUF */
+#define NV_PGRAPH_DMA_A_TLB_TAG                          0x00401050 /* RW-4R */
+#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS                       31:12 /* RWXUF */
+#define NV_PGRAPH_DMA_A_ADJ_OFFSET                       0x00401054 /* RW-4R */
+#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE                       31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_A_OFFSET                           0x00401058 /* RW-4R */
+#define NV_PGRAPH_DMA_A_OFFSET_VALUE                           31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_A_SIZE                             0x0040105C /* RW-4R */
+#define NV_PGRAPH_DMA_A_SIZE_VALUE                             24:0 /* RWXUF */
+#define NV_PGRAPH_DMA_A_Y_SIZE                           0x00401060 /* RW-4R */
+#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE                           10:0 /* RWXUF */
+#define NV_PGRAPH_DMA_B_XLATE_INST                       0x00401080 /* RW-4R */
+#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE                       15:0 /* RWXUF */
+#define NV_PGRAPH_DMA_B_CONTROL                          0x00401084 /* RW-4R */
+#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE                    12:12 /* RWIVF */
+#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT   0x00000000 /* RWI-V */
+#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT       0x00000001 /* RW--V */
+#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY                    13:13 /* RWXVF */
+#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR    0x00000000 /* RW--V */
+#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR        0x00000001 /* RW--V */
+#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE                   17:16 /* RWXUF */
+#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM          0x00000000 /* RW--V */
+#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI          0x00000002 /* RW--V */
+#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP          0x00000003 /* RW--V */
+#define NV_PGRAPH_DMA_B_CONTROL_ADJUST                        31:20 /* RWXUF */
+#define NV_PGRAPH_DMA_B_LIMIT                            0x00401088 /* RW-4R */
+#define NV_PGRAPH_DMA_B_LIMIT_OFFSET                           31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_B_TLB_PTE                          0x0040108C /* RW-4R */
+#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS                          1:1 /* RWXVF */
+#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY         0x00000000 /* RW--V */
+#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE        0x00000001 /* RW--V */
+#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS                 31:12 /* RWXUF */
+#define NV_PGRAPH_DMA_B_TLB_TAG                          0x00401090 /* RW-4R */
+#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS                       31:12 /* RWXUF */
+#define NV_PGRAPH_DMA_B_ADJ_OFFSET                       0x00401094 /* RW-4R */
+#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE                       31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_B_OFFSET                           0x00401098 /* RW-4R */
+#define NV_PGRAPH_DMA_B_OFFSET_VALUE                           31:0 /* RWXUF */
+#define NV_PGRAPH_DMA_B_SIZE                             0x0040109C /* RW-4R */
+#define NV_PGRAPH_DMA_B_SIZE_VALUE                             24:0 /* RWXUF */
+#define NV_PGRAPH_DMA_B_Y_SIZE                           0x004010A0 /* RW-4R */
+#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE                           10:0 /* RWXUF */
+
+/* Framebuffer registers */
+#define NV_PFB                                0x00100FFF:0x00100000 /* RW--D */
+#define NV_PFB_BOOT_0                                    0x00100000 /* RW-4R */
+#define NV_PFB_BOOT_0_RAM_AMOUNT                                1:0 /* RW-VF */
+#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB                    0x00000000 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB                     0x00000001 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB                     0x00000002 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB                    0x00000003 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_WIDTH_128                             2:2 /* RW-VF */
+#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF                  0x00000000 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON                   0x00000001 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_TYPE                                  4:3 /* RW-VF */
+#define NV_PFB_BOOT_0_RAM_TYPE_256K                      0x00000000 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK                0x00000001 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK                0x00000002 /* RW--V */
+#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK               0x00000003 /* RW--V */
+#define NV_PFB_CONFIG_0                                  0x00100200 /* RW-4R */
+#define NV_PFB_CONFIG_0_TYPE                                   14:0 /* RWIVF */
+#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP          0x00000120 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP         0x00000220 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP         0x00000320 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP            0x00004120 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP           0x00004220 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP           0x00004320 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_TETRIS                      0x00002000 /* RW--V */
+#define NV_PFB_CONFIG_0_TYPE_NOTILING                    0x00001114 /* RWI-V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE                           17:15 /* RWI-F */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS                 0x00000000 /* RWI-V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_1                    0x00000001 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_2                    0x00000002 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_3                    0x00000003 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_4                    0x00000004 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_5                    0x00000005 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_6                    0x00000006 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_MODE_7                    0x00000007 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_SHIFT                          19:18 /* RWI-F */
+#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0                   0x00000000 /* RWI-V */
+#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1                   0x00000001 /* RW--V */
+#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2                   0x00000002 /* RW--V */
+#define NV_PFB_CONFIG_0_BANK_SWAP                             22:20 /* RWI-F */
+#define NV_PFB_CONFIG_0_BANK_SWAP_OFF                    0x00000000 /* RWI-V */
+#define NV_PFB_CONFIG_0_BANK_SWAP_1M                     0x00000001 /* RW--V */
+#define NV_PFB_CONFIG_0_BANK_SWAP_2M                     0x00000005 /* RW--V */
+#define NV_PFB_CONFIG_0_BANK_SWAP_4M                     0x00000007 /* RW--V */
+#define NV_PFB_CONFIG_0_UNUSED                                23:23 /* RW-VF */
+#define NV_PFB_CONFIG_0_SCRAMBLE_EN                           29:29 /* RWIVF */
+#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT                 0x00000000 /* RW--V */
+#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE                  0x00000001 /* RW--V */
+#define NV_PFB_CONFIG_0_PRAMIN_WR                             28:28 /* RWIVF */
+#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT                   0x00000000 /* RW--V */
+#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED               0x00000001 /* RW--V */
+#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK                        27:24 /* RWIVF */
+#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT              0x00000000 /* RWI-V */
+#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR             0x0000000f /* RWI-V */
+#define NV_PFB_CONFIG_1                                  0x00100204 /* RW-4R */
+#define NV_PFB_RTL                                       0x00100300 /* RW-4R */
+#define NV_PFB_RTL_H                                            0:0 /* RWIUF */
+#define NV_PFB_RTL_H_DEFAULT                             0x00000000 /* RWI-V */
+#define NV_PFB_RTL_MC                                           1:1 /* RWIUF */
+#define NV_PFB_RTL_MC_DEFAULT                            0x00000000 /* RWI-V */
+#define NV_PFB_RTL_V                                            2:2 /* RWIUF */
+#define NV_PFB_RTL_V_DEFAULT                             0x00000000 /* RWI-V */
+#define NV_PFB_RTL_G                                            3:3 /* RWIUF */
+#define NV_PFB_RTL_G_DEFAULT                             0x00000000 /* RWI-V */
+#define NV_PFB_RTL_GB                                           4:4 /* RWIUF */
+#define NV_PFB_RTL_GB_DEFAULT                            0x00000000 /* RWI-V */
+#define NV_PFB_CONFIG_0_RESOLUTION                              5:0 /* RWIVF */
+#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS            0x0000000a /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS            0x0000000d /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS            0x0000000f /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS            0x00000010 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS            0x00000014 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS            0x00000019 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS            0x0000001e /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS           0x00000020 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS           0x00000024 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS           0x00000028 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS           0x00000032 /* RW--V */
+#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT               0x00000014 /* RWI-V */
+#define NV_PFB_CONFIG_0_PIXEL_DEPTH                             9:8 /* RWIVF */
+#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS               0x00000001 /* RW--V */
+#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS              0x00000002 /* RW--V */
+#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS              0x00000003 /* RW--V */
+#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT              0x00000001 /* RWI-V */
+#define NV_PFB_CONFIG_0_TILING                                12:12 /* RWIVF */
+#define NV_PFB_CONFIG_0_TILING_ENABLED                   0x00000000 /* RW--V */
+#define NV_PFB_CONFIG_0_TILING_DISABLED                  0x00000001 /* RWI-V */
+#define NV_PFB_CONFIG_1_SGRAM100                                3:3 /* RWIVF */
+#define NV_PFB_CONFIG_1_SGRAM100_ENABLED                 0x00000000 /* RWI-V */
+#define NV_PFB_CONFIG_1_SGRAM100_DISABLED                0x00000001 /* RW--V */
+#define NV_PFB_DEBUG_0_CKE_ALWAYSON                           29:29 /* RWIVF */
+#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF                  0x00000000 /* RW--V */
+#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON                   0x00000001 /* RWI-V */
+
+#define NV_PEXTDEV                            0x00101FFF:0x00101000 /* RW--D */
+#define NV_PEXTDEV_BOOT_0                                0x00101000 /* R--4R */
+#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED                       0:0 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ          0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ          0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR                      1:1 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS       0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS          0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE                        3:2 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K      0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK     0x00000003 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH                       4:4 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64             0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128            0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE                        5:5 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI             0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP             0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL                         6:6 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K           0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180         0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE                          8:7 /* R-XVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM             0x00000000 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC              0x00000001 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL               0x00000002 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED          0x00000003 /* R---V */
+#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE                     11:11 /* RWIVF */
+#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED       0x00000000 /* RWI-V */
+#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED        0x00000001 /* RW--V */
+
+/* Extras */
+#define NV_PRAMIN                             0x007FFFFF:0x00700000 /* RW--M */
+/*#define NV_PRAMIN                             0x00FFFFFF:0x00C00000*/
+#define NV_PNVM                               0x01FFFFFF:0x01000000 /* RW--M */
+/*#define NV_PNVM                               0x00BFFFFF:0x00800000*/
+#define NV_CHAN0                              0x0080ffff:0x00800000
+
+/* FIFO subchannels */
+#define NV_UROP                               0x43
+#define NV_UCHROMA                            0x57
+#define NV_UCLIP                              0x19
+#define NV_UPATT                              0x18
+#define NV_ULIN                               0x5C
+#define NV_UTRI                               0x5D
+#define NV_URECT                              0x5E
+#define NV_UBLIT                              0x5F
+#define NV_UGLYPH                             0x4B
+
+#endif /*__NV4REF_H__*/
+
diff --git a/drivers/video/riva/nvreg.h b/drivers/video/riva/nvreg.h
new file mode 100644
index 000000000..abfc167ae
--- /dev/null
+++ b/drivers/video/riva/nvreg.h
@@ -0,0 +1,188 @@
+/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
+/*
+ * Copyright 1996-1997  David J. McKay
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
+
+#ifndef __NVREG_H_
+#define __NVREG_H_
+
+/* Little macro to construct bitmask for contiguous ranges of bits */
+#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
+#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
+
+/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
+#define SetBF(mask,value) ((value) << (0?mask))
+#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
+
+#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
+                                             | SetBF(mask,value)))
+
+#define DEVICE_BASE(device) (0?NV##_##device)
+#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
+
+/* This is where we will have to have conditional compilation */
+#define DEVICE_ACCESS(device,reg) \
+  nvCONTROL[(NV_##device##_##reg)/4]
+
+#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
+#define DEVICE_READ(device,reg)        DEVICE_ACCESS(device,reg)
+#define DEVICE_PRINT(device,reg) \
+  ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
+#define DEVICE_DEF(device,mask,value) \
+  SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
+#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
+#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
+
+#define PDAC_Write(reg,value)           DEVICE_WRITE(PDAC,reg,value)
+#define PDAC_Read(reg)                  DEVICE_READ(PDAC,reg)
+#define PDAC_Print(reg)                 DEVICE_PRINT(PDAC,reg)
+#define PDAC_Def(mask,value)            DEVICE_DEF(PDAC,mask,value)
+#define PDAC_Val(mask,value)            DEVICE_VALUE(PDAC,mask,value)
+#define PDAC_Mask(mask)                 DEVICE_MASK(PDAC,mask)
+
+#define PFB_Write(reg,value)            DEVICE_WRITE(PFB,reg,value)
+#define PFB_Read(reg)                   DEVICE_READ(PFB,reg)
+#define PFB_Print(reg)                  DEVICE_PRINT(PFB,reg)
+#define PFB_Def(mask,value)             DEVICE_DEF(PFB,mask,value)
+#define PFB_Val(mask,value)             DEVICE_VALUE(PFB,mask,value)
+#define PFB_Mask(mask)                  DEVICE_MASK(PFB,mask)
+
+#define PRM_Write(reg,value)            DEVICE_WRITE(PRM,reg,value)
+#define PRM_Read(reg)                   DEVICE_READ(PRM,reg)
+#define PRM_Print(reg)                  DEVICE_PRINT(PRM,reg)
+#define PRM_Def(mask,value)             DEVICE_DEF(PRM,mask,value)
+#define PRM_Val(mask,value)             DEVICE_VALUE(PRM,mask,value)
+#define PRM_Mask(mask)                  DEVICE_MASK(PRM,mask)
+
+#define PGRAPH_Write(reg,value)         DEVICE_WRITE(PGRAPH,reg,value)
+#define PGRAPH_Read(reg)                DEVICE_READ(PGRAPH,reg)
+#define PGRAPH_Print(reg)               DEVICE_PRINT(PGRAPH,reg)
+#define PGRAPH_Def(mask,value)          DEVICE_DEF(PGRAPH,mask,value)
+#define PGRAPH_Val(mask,value)          DEVICE_VALUE(PGRAPH,mask,value)
+#define PGRAPH_Mask(mask)               DEVICE_MASK(PGRAPH,mask)
+
+#define PDMA_Write(reg,value)           DEVICE_WRITE(PDMA,reg,value)
+#define PDMA_Read(reg)                  DEVICE_READ(PDMA,reg)
+#define PDMA_Print(reg)                 DEVICE_PRINT(PDMA,reg)
+#define PDMA_Def(mask,value)            DEVICE_DEF(PDMA,mask,value)
+#define PDMA_Val(mask,value)            DEVICE_VALUE(PDMA,mask,value)
+#define PDMA_Mask(mask)                 DEVICE_MASK(PDMA,mask)
+
+#define PTIMER_Write(reg,value)         DEVICE_WRITE(PTIMER,reg,value)
+#define PTIMER_Read(reg)                DEVICE_READ(PTIMER,reg)
+#define PTIMER_Print(reg)               DEVICE_PRINT(PTIMER,reg)
+#define PTIMER_Def(mask,value)          DEVICE_DEF(PTIMER,mask,value)
+#define PTIMER_Val(mask,value)          DEVICE_VALUE(PTIEMR,mask,value)
+#define PTIMER_Mask(mask)               DEVICE_MASK(PTIMER,mask)
+
+#define PEXTDEV_Write(reg,value)         DEVICE_WRITE(PEXTDEV,reg,value)
+#define PEXTDEV_Read(reg)                DEVICE_READ(PEXTDEV,reg)
+#define PEXTDEV_Print(reg)               DEVICE_PRINT(PEXTDEV,reg)
+#define PEXTDEV_Def(mask,value)          DEVICE_DEF(PEXTDEV,mask,value)
+#define PEXTDEV_Val(mask,value)          DEVICE_VALUE(PEXTDEV,mask,value)
+#define PEXTDEV_Mask(mask)               DEVICE_MASK(PEXTDEV,mask)
+
+#define PFIFO_Write(reg,value)          DEVICE_WRITE(PFIFO,reg,value)
+#define PFIFO_Read(reg)                 DEVICE_READ(PFIFO,reg)
+#define PFIFO_Print(reg)                DEVICE_PRINT(PFIFO,reg)
+#define PFIFO_Def(mask,value)           DEVICE_DEF(PFIFO,mask,value)
+#define PFIFO_Val(mask,value)           DEVICE_VALUE(PFIFO,mask,value)
+#define PFIFO_Mask(mask)                DEVICE_MASK(PFIFO,mask)
+
+#define PRAM_Write(reg,value)           DEVICE_WRITE(PRAM,reg,value)
+#define PRAM_Read(reg)                  DEVICE_READ(PRAM,reg)
+#define PRAM_Print(reg)                 DEVICE_PRINT(PRAM,reg)
+#define PRAM_Def(mask,value)            DEVICE_DEF(PRAM,mask,value)
+#define PRAM_Val(mask,value)            DEVICE_VALUE(PRAM,mask,value)
+#define PRAM_Mask(mask)                 DEVICE_MASK(PRAM,mask)
+
+#define PRAMFC_Write(reg,value)         DEVICE_WRITE(PRAMFC,reg,value)
+#define PRAMFC_Read(reg)                DEVICE_READ(PRAMFC,reg)
+#define PRAMFC_Print(reg)               DEVICE_PRINT(PRAMFC,reg)
+#define PRAMFC_Def(mask,value)          DEVICE_DEF(PRAMFC,mask,value)
+#define PRAMFC_Val(mask,value)          DEVICE_VALUE(PRAMFC,mask,value)
+#define PRAMFC_Mask(mask)               DEVICE_MASK(PRAMFC,mask)
+
+#define PMC_Write(reg,value)            DEVICE_WRITE(PMC,reg,value)
+#define PMC_Read(reg)                   DEVICE_READ(PMC,reg)
+#define PMC_Print(reg)                  DEVICE_PRINT(PMC,reg)
+#define PMC_Def(mask,value)             DEVICE_DEF(PMC,mask,value)
+#define PMC_Val(mask,value)             DEVICE_VALUE(PMC,mask,value)
+#define PMC_Mask(mask)                  DEVICE_MASK(PMC,mask)
+
+#define PMC_Write(reg,value)            DEVICE_WRITE(PMC,reg,value)
+#define PMC_Read(reg)                   DEVICE_READ(PMC,reg)
+#define PMC_Print(reg)                  DEVICE_PRINT(PMC,reg)
+#define PMC_Def(mask,value)             DEVICE_DEF(PMC,mask,value)
+#define PMC_Val(mask,value)             DEVICE_VALUE(PMC,mask,value)
+#define PMC_Mask(mask)                  DEVICE_MASK(PMC,mask)
+
+
+#define PBUS_Write(reg,value)         DEVICE_WRITE(PBUS,reg,value)
+#define PBUS_Read(reg)                DEVICE_READ(PBUS,reg)
+#define PBUS_Print(reg)               DEVICE_PRINT(PBUS,reg)
+#define PBUS_Def(mask,value)          DEVICE_DEF(PBUS,mask,value)
+#define PBUS_Val(mask,value)          DEVICE_VALUE(PBUS,mask,value)
+#define PBUS_Mask(mask)               DEVICE_MASK(PBUS,mask)
+
+
+#define PRAMDAC_Write(reg,value)         DEVICE_WRITE(PRAMDAC,reg,value)
+#define PRAMDAC_Read(reg)                DEVICE_READ(PRAMDAC,reg)
+#define PRAMDAC_Print(reg)               DEVICE_PRINT(PRAMDAC,reg)
+#define PRAMDAC_Def(mask,value)          DEVICE_DEF(PRAMDAC,mask,value)
+#define PRAMDAC_Val(mask,value)          DEVICE_VALUE(PRAMDAC,mask,value)
+#define PRAMDAC_Mask(mask)               DEVICE_MASK(PRAMDAC,mask)
+
+
+#define PDAC_ReadExt(reg) \
+  ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
+  (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
+  (PDAC_Read(INDEX_DATA)))
+
+#define PDAC_WriteExt(reg,value)\
+  ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
+  (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
+  (PDAC_Write(INDEX_DATA,(value))))
+
+#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5)
+#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5))
+
+#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
+#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
+
+#define PCRTC_Def(mask,value)          DEVICE_DEF(PCRTC,mask,value)
+#define PCRTC_Val(mask,value)          DEVICE_VALUE(PCRTC,mask,value)
+#define PCRTC_Mask(mask)               DEVICE_MASK(PCRTC,mask)
+
+#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
+#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
+
+extern volatile unsigned  *nvCONTROL;
+
+typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;
+
+NVChipType GetChipType(void);
+
+#endif
+
+
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
new file mode 100644
index 000000000..1bd904c8e
--- /dev/null
+++ b/drivers/video/riva/riva_hw.c
@@ -0,0 +1,1426 @@
+ /***************************************************************************\
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
+|*     international laws.  Users and possessors of this source code are     *|
+|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
+|*     use this code in individual and commercial software.                  *|
+|*                                                                           *|
+|*     Any use of this source code must include,  in the user documenta-     *|
+|*     tion and  internal comments to the code,  notices to the end user     *|
+|*     as follows:                                                           *|
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
+|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
+|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
+|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
+|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
+|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
+|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
+|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
+|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
+|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
+|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
+|*                                                                           *|
+|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
+|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
+|*     consisting  of "commercial  computer  software"  and  "commercial     *|
+|*     computer  software  documentation,"  as such  terms  are  used in     *|
+|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
+|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
+|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
+|*     all U.S. Government End Users  acquire the source code  with only     *|
+|*     those rights set forth herein.                                        *|
+|*                                                                           *|
+ \***************************************************************************/
+/* 
+ * GPL licensing note -- nVidia is allowing a liberal interpretation of 
+ * the documentation restriction above, to merely say that this nVidia's
+ * copyright and disclaimer should be included with all code derived 
+ * from this source.  -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99
+ */
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.c,v 1.1.2.3 1998/12/26 00:12:39 dawes Exp $ */
+
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include "riva_hw.h"
+#include "riva_tbl.h"
+
+
+/*
+ * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
+ * operate identically (except TNT has more memory and better 3D quality.
+ */
+
+static int nv3Busy
+(
+    RIVA_HW_INST *chip
+)
+{
+    return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x000006B0/4] & 0x01));
+}
+static int nv4Busy
+(
+    RIVA_HW_INST *chip
+)
+{
+    return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x00000700/4] & 0x01));
+}
+static int ShowHideCursor
+(
+    RIVA_HW_INST *chip,
+    int           ShowHide
+)
+{
+    int xcurrent;
+    xcurrent                     =  chip->CurrentState->cursor1;
+    chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | (ShowHide & 0x01);
+    outb(0x31, 0x3D4);
+    outb(chip->CurrentState->cursor1, 0x3D5);
+    return (xcurrent & 0x01);
+}
+
+/****************************************************************************\
+*                                                                            *
+* The video arbitration routines calculate some "magic" numbers.  Fixes      *
+* the snow seen when accessing the framebuffer without it.                   *
+* It just works (I hope).                                                    *
+*                                                                            *
+\****************************************************************************/
+
+#define DEFAULT_GR_LWM 100
+#define DEFAULT_VID_LWM 100
+#define DEFAULT_GR_BURST_SIZE 256
+#define DEFAULT_VID_BURST_SIZE 128
+#define VIDEO		0
+#define GRAPHICS	1
+#define MPORT		2
+#define ENGINE		3
+#define GFIFO_SIZE	320
+#define GFIFO_SIZE_128	256
+#define MFIFO_SIZE	120
+#define VFIFO_SIZE	256
+#define	ABS(a)	(a>0?a:-a)
+typedef struct {
+  int gdrain_rate;
+  int vdrain_rate;
+  int mdrain_rate;
+  int gburst_size;
+  int vburst_size;
+  char vid_en;
+  char gr_en;
+  int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
+  int by_gfacc;
+  char vid_only_once;
+  char gr_only_once;
+  char first_vacc;
+  char first_gacc;
+  char first_macc;
+  int vocc;
+  int gocc;
+  int mocc;
+  char cur;
+  char engine_en;
+  char converged;
+  int priority;
+} nv3_arb_info;
+typedef struct {
+  int graphics_lwm;
+  int video_lwm;
+  int graphics_burst_size;
+  int video_burst_size;
+  int graphics_hi_priority;
+  int media_hi_priority;
+  int rtl_values;
+  int valid;
+} nv3_fifo_info;
+typedef struct {
+  char pix_bpp;
+  char enable_video;
+  char gr_during_vid;
+  char enable_mp;
+  int memory_width;
+  int video_scale;
+  int pclk_khz;
+  int mclk_khz;
+  int mem_page_miss;
+  int mem_latency;
+  char mem_aligned;
+} nv3_sim_state;
+typedef struct {
+  int graphics_lwm;
+  int video_lwm;
+  int graphics_burst_size;
+  int video_burst_size;
+  int valid;
+} nv4_fifo_info;
+typedef struct {
+  int pclk_khz;
+  int mclk_khz;
+  int nvclk_khz;
+  char mem_page_miss;
+  char mem_latency;
+  int memory_width;
+  char enable_video;
+  char gr_during_vid;
+  char pix_bpp;
+  char mem_aligned;
+  char enable_mp;
+} nv4_sim_state;
+static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
+{
+    int iter = 0;
+    int tmp;
+    int vfsize, mfsize, gfsize;
+    int mburst_size = 32;
+    int mmisses, gmisses, vmisses;
+    int misses;
+    int vlwm, glwm, mlwm;
+    int last, next, cur;
+    int max_gfsize ;
+    long ns;
+
+    vlwm = 0;
+    glwm = 0;
+    mlwm = 0;
+    vfsize = 0;
+    gfsize = 0;
+    cur = ainfo->cur;
+    mmisses = 2;
+    gmisses = 2;
+    vmisses = 2;
+    if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
+    else  max_gfsize = GFIFO_SIZE;
+    max_gfsize = GFIFO_SIZE;
+    while (1)
+    {
+        if (ainfo->vid_en)
+        {
+            if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
+            if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
+            ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
+            vfsize = ns * ainfo->vdrain_rate / 1000000;
+            vfsize =  ainfo->wcvlwm - ainfo->vburst_size + vfsize;
+        }
+        if (state->enable_mp)
+        {
+            if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
+        }
+        if (ainfo->gr_en)
+        {
+            if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
+            if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
+            ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
+            gfsize = ns *ainfo->gdrain_rate/1000000;
+            gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
+        }
+        mfsize = 0;
+        if (!state->gr_during_vid && ainfo->vid_en)
+            if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
+                next = VIDEO;
+            else if (ainfo->mocc < 0)
+                next = MPORT;
+            else if (ainfo->gocc< ainfo->by_gfacc)
+                next = GRAPHICS;
+            else return (0);
+        else switch (ainfo->priority)
+            {
+                case VIDEO:
+                    if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
+                        next = VIDEO;
+                    else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
+                        next = GRAPHICS;
+                    else if (ainfo->mocc<0)
+                        next = MPORT;
+                    else    return (0);
+                    break;
+                case GRAPHICS:
+                    if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
+                        next = GRAPHICS;
+                    else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
+                        next = VIDEO;
+                    else if (ainfo->mocc<0)
+                        next = MPORT;
+                    else    return (0);
+                    break;
+                default:
+                    if (ainfo->mocc<0)
+                        next = MPORT;
+                    else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
+                        next = GRAPHICS;
+                    else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
+                        next = VIDEO;
+                    else    return (0);
+                    break;
+            }
+        last = cur;
+        cur = next;
+        iter++;
+        switch (cur)
+        {
+            case VIDEO:
+                if (last==cur)    misses = 0;
+                else if (ainfo->first_vacc)   misses = vmisses;
+                else    misses = 1;
+                ainfo->first_vacc = 0;
+                if (last!=cur)
+                {
+                    ns =  1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 
+                    vlwm = ns * ainfo->vdrain_rate/ 1000000;
+                    vlwm = ainfo->vocc - vlwm;
+                }
+                ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
+                ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
+                ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
+                ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
+                break;
+            case GRAPHICS:
+                if (last==cur)    misses = 0;
+                else if (ainfo->first_gacc)   misses = gmisses;
+                else    misses = 1;
+                ainfo->first_gacc = 0;
+                if (last!=cur)
+                {
+                    ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
+                    glwm = ns * ainfo->gdrain_rate/1000000;
+                    glwm = ainfo->gocc - glwm;
+                }
+                ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
+                ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
+                ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
+                ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
+                break;
+            default:
+                if (last==cur)    misses = 0;
+                else if (ainfo->first_macc)   misses = mmisses;
+                else    misses = 1;
+                ainfo->first_macc = 0;
+                ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
+                ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
+                ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
+                ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
+                break;
+        }
+        if (iter>100)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
+        tmp = ns * ainfo->gdrain_rate/1000000;
+        if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7)    - tmp > max_gfsize)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
+        tmp = ns * ainfo->vdrain_rate/1000000;
+        if (ABS(ainfo->vburst_size) + (ABS(ainfo->wcvlwm + 32) & ~0xf)  - tmp> VFIFO_SIZE)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        if (ABS(ainfo->gocc) > max_gfsize)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        if (ABS(ainfo->vocc) > VFIFO_SIZE)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        if (ABS(ainfo->mocc) > MFIFO_SIZE)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        if (ABS(vfsize) > VFIFO_SIZE)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        if (ABS(gfsize) > max_gfsize)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+        if (ABS(mfsize) > MFIFO_SIZE)
+        {
+            ainfo->converged = 0;
+            return (1);
+        }
+    }
+}
+static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state,  nv3_arb_info *ainfo) 
+{
+    long ens, vns, mns, gns;
+    int mmisses, gmisses, vmisses, eburst_size, mburst_size;
+    int refresh_cycle;
+
+    refresh_cycle = 0;
+    refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
+    mmisses = 2;
+    if (state->mem_aligned) gmisses = 2;
+    else    gmisses = 3;
+    vmisses = 2;
+    eburst_size = state->memory_width * 1;
+    mburst_size = 32;
+    gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
+    ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
+    ainfo->wcmocc = 0;
+    ainfo->wcgocc = 0;
+    ainfo->wcvocc = 0;
+    ainfo->wcvlwm = 0;
+    ainfo->wcglwm = 0;
+    ainfo->engine_en = 1;
+    ainfo->converged = 1;
+    if (ainfo->engine_en)
+    {
+        ens =  1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
+        ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
+        ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
+        ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
+        ainfo->cur = ENGINE;
+        ainfo->first_vacc = 1;
+        ainfo->first_gacc = 1;
+        ainfo->first_macc = 1;
+        nv3_iterate(res_info, state,ainfo);
+    }
+    if (state->enable_mp)
+    {
+        mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
+        ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
+        ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
+        ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
+        ainfo->cur = MPORT;
+        ainfo->first_vacc = 1;
+        ainfo->first_gacc = 1;
+        ainfo->first_macc = 0;
+        nv3_iterate(res_info, state,ainfo);
+    }
+    if (ainfo->gr_en)
+    {
+        ainfo->first_vacc = 1;
+        ainfo->first_gacc = 0;
+        ainfo->first_macc = 1;
+        gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
+        ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
+        ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
+        ainfo->mocc = state->enable_mp ?  0-gns*ainfo->mdrain_rate/1000000: 0;
+        ainfo->cur = GRAPHICS;
+        nv3_iterate(res_info, state,ainfo);
+    }
+    if (ainfo->vid_en)
+    {
+        ainfo->first_vacc = 0;
+        ainfo->first_gacc = 1;
+        ainfo->first_macc = 1;
+        vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
+        ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
+        ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
+        ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
+        ainfo->cur = VIDEO;
+        nv3_iterate(res_info, state, ainfo);
+    }
+    if (ainfo->converged)
+    {
+        res_info->graphics_lwm = (int)ABS(ainfo->wcglwm) + 16;
+        res_info->video_lwm = (int)ABS(ainfo->wcvlwm) + 32;
+        res_info->graphics_burst_size = ainfo->gburst_size;
+        res_info->video_burst_size = ainfo->vburst_size;
+        res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
+        res_info->media_hi_priority = (ainfo->priority == MPORT);
+        if (res_info->video_lwm > 160)
+        {
+            res_info->graphics_lwm = 256;
+            res_info->video_lwm = 128;
+            res_info->graphics_burst_size = 64;
+            res_info->video_burst_size = 64;
+            res_info->graphics_hi_priority = 0;
+            res_info->media_hi_priority = 0;
+            ainfo->converged = 0;
+            return (0);
+        }
+        if (res_info->video_lwm > 128)
+        {
+            res_info->video_lwm = 128;
+        }
+        return (1);
+    }
+    else
+    {
+        res_info->graphics_lwm = 256;
+        res_info->video_lwm = 128;
+        res_info->graphics_burst_size = 64;
+        res_info->video_burst_size = 64;
+        res_info->graphics_hi_priority = 0;
+        res_info->media_hi_priority = 0;
+        return (0);
+    }
+}
+static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
+{
+    int done, g,v, p;
+    
+    done = 0;
+    if (state->gr_during_vid && ainfo->vid_en)
+        ainfo->priority = MPORT;
+    else
+        ainfo->priority = ainfo->gdrain_rate < ainfo->vdrain_rate ? VIDEO: GRAPHICS;
+    for (p=0; p < 2 && done != 1; p++)
+    {
+        for (g=128 ; (g > 32) && (done != 1); g= g>> 1)
+        {
+            for (v=128; (v >=32) && (done !=1); v = v>> 1)
+            {
+                ainfo->priority = p;
+                ainfo->gburst_size = g;     
+                ainfo->vburst_size = v;
+                done = nv3_arb(res_info, state,ainfo);
+                if (g==128)
+                {
+                    if ((res_info->graphics_lwm + g) > 256)
+                        done = 0;
+                }
+            }
+        }
+    }
+    if (!done)
+        return (0);
+    else
+        return (1);
+}
+static void nv3CalcArbitration 
+(
+    nv3_fifo_info * res_info,
+    nv3_sim_state * state
+)
+{
+    nv3_fifo_info save_info;
+    nv3_arb_info ainfo;
+    char   res_gr, res_vid;
+
+    ainfo.gr_en = 1;
+    ainfo.vid_en = state->enable_video;
+    ainfo.vid_only_once = 0;
+    ainfo.gr_only_once = 0;
+    ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8;
+    ainfo.vdrain_rate = (int) state->pclk_khz * 2;
+    if (state->video_scale != 0)
+        ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
+    ainfo.mdrain_rate = 33000;
+    res_info->rtl_values = 0;
+    if (!state->gr_during_vid && state->enable_video)
+    {
+        ainfo.gr_only_once = 1;
+        ainfo.gr_en = 1;
+        ainfo.gdrain_rate = 0;
+        res_vid = nv3_get_param(res_info, state,  &ainfo);
+        res_vid = ainfo.converged;
+        save_info.video_lwm = res_info->video_lwm;
+        save_info.video_burst_size = res_info->video_burst_size;
+        ainfo.vid_en = 1;
+        ainfo.vid_only_once = 1;
+        ainfo.gr_en = 1;
+        ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8;
+        ainfo.vdrain_rate = 0;
+        res_gr = nv3_get_param(res_info, state,  &ainfo);
+        res_gr = ainfo.converged;
+        res_info->video_lwm = save_info.video_lwm;
+        res_info->video_burst_size = save_info.video_burst_size;
+        res_info->valid = res_gr & res_vid;
+    }
+    else
+    {
+        if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
+        if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
+        res_gr = nv3_get_param(res_info, state,  &ainfo);
+        res_info->valid = ainfo.converged;
+    }
+}
+void nv3UpdateArbitrationSettings
+(
+    unsigned      VClk, 
+    unsigned      pixelDepth, 
+    unsigned     *burst,
+    unsigned     *lwm,
+    RIVA_HW_INST *chip
+)
+{
+    nv3_fifo_info fifo_data;
+    nv3_sim_state sim_data;
+    unsigned int M, N, P, pll, MClk;
+    
+    pll = chip->PRAMDAC[0x00000504/4];
+    M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
+    MClk = (N * chip->CrystalFreqKHz / M) >> P;
+    sim_data.pix_bpp        = (char)pixelDepth;
+    sim_data.enable_video   = 0;
+    sim_data.enable_mp      = 0;
+    sim_data.video_scale    = 1;
+    sim_data.memory_width   = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
+    sim_data.memory_width   = 128;
+    sim_data.mem_latency    = 11;
+    sim_data.mem_aligned    = 1;
+    sim_data.mem_page_miss  = 9;
+    sim_data.gr_during_vid  = 0;
+    sim_data.pclk_khz       = VClk;
+    sim_data.mclk_khz       = MClk;
+    nv3CalcArbitration(&fifo_data, &sim_data);
+    if (fifo_data.valid)
+    {
+        int  b = fifo_data.graphics_burst_size >> 4;
+        *burst = 0;
+        while (b >>= 1) (*burst)++;
+        *lwm   = fifo_data.graphics_lwm >> 3;
+    }
+    else
+    {
+        *lwm   = 0x24;
+        *burst = 0x02;
+    }
+}
+static void nv4CalcArbitration 
+(
+    nv4_fifo_info *fifo,
+    nv4_sim_state *arb
+)
+{
+    int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
+    int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
+    int found, mclk_extra, mclk_loop, cbs, m1, p1;
+    int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
+    int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
+    int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
+    int craw, vraw;
+
+    fifo->valid = 1;
+    pclk_freq = arb->pclk_khz;
+    mclk_freq = arb->mclk_khz;
+    nvclk_freq = arb->nvclk_khz;
+    pagemiss = arb->mem_page_miss;
+    cas = arb->mem_latency;
+    width = arb->memory_width >> 6;
+    video_enable = arb->enable_video;
+    color_key_enable = arb->gr_during_vid;
+    bpp = arb->pix_bpp;
+    align = arb->mem_aligned;
+    mp_enable = arb->enable_mp;
+    clwm = 0;
+    vlwm = 0;
+    cbs = 128;
+    pclks = 2;
+    nvclks = 2;
+    nvclks += 2;
+    nvclks += 1;
+    mclks = 5;
+    mclks += 3;
+    mclks += 1;
+    mclks += cas;
+    mclks += 1;
+    mclks += 1;
+    mclks += 1;
+    mclks += 1;
+    mclk_extra = 3;
+    nvclks += 2;
+    nvclks += 1;
+    nvclks += 1;
+    nvclks += 1;
+    if (mp_enable)
+        mclks+=4;
+    nvclks += 0;
+    pclks += 0;
+    found = 0;
+    while (found != 1)
+    {
+        fifo->valid = 1;
+        found = 1;
+        mclk_loop = mclks+mclk_extra;
+        us_m = mclk_loop *1000*1000 / mclk_freq;
+        us_n = nvclks*1000*1000 / nvclk_freq;
+        us_p = nvclks*1000*1000 / pclk_freq;
+        if (video_enable)
+        {
+            video_drain_rate = pclk_freq * 2;
+            crtc_drain_rate = pclk_freq * bpp/8;
+            vpagemiss = 2;
+            vpagemiss += 1;
+            crtpagemiss = 2;
+            vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
+            if (nvclk_freq * 2 > mclk_freq * width)
+                video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
+            else
+                video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
+            us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
+            vlwm = us_video * video_drain_rate/(1000*1000);
+            vlwm++;
+            vbs = 128;
+            if (vlwm > 128) vbs = 64;
+            if (vlwm > (256-64)) vbs = 32;
+            if (nvclk_freq * 2 > mclk_freq * width)
+                video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
+            else
+                video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
+            cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
+            us_crt =
+            us_video
+            +video_fill_us
+            +cpm_us
+            +us_m + us_n +us_p
+            ;
+            clwm = us_crt * crtc_drain_rate/(1000*1000);
+            clwm++;
+        }
+        else
+        {
+            crtc_drain_rate = pclk_freq * bpp/8;
+            crtpagemiss = 2;
+            crtpagemiss += 1;
+            cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
+            us_crt =  cpm_us + us_m + us_n + us_p ;
+            clwm = us_crt * crtc_drain_rate/(1000*1000);
+            clwm++;
+        }
+        m1 = clwm + cbs - 512;
+        p1 = m1 * pclk_freq / mclk_freq;
+        p1 = p1 * bpp / 8;
+        if ((p1 < m1) && (m1 > 0))
+        {
+            fifo->valid = 0;
+            found = 0;
+            if (mclk_extra ==0)   found = 1;
+            mclk_extra--;
+        }
+        else if (video_enable)
+        {
+            if ((clwm > 511) || (vlwm > 255))
+            {
+                fifo->valid = 0;
+                found = 0;
+                if (mclk_extra ==0)   found = 1;
+                mclk_extra--;
+            }
+        }
+        else
+        {
+            if (clwm > 519)
+            {
+                fifo->valid = 0;
+                found = 0;
+                if (mclk_extra ==0)   found = 1;
+                mclk_extra--;
+            }
+        }
+        craw = clwm;
+        vraw = vlwm;
+        if (clwm < 384) clwm = 384;
+        if (vlwm < 128) vlwm = 128;
+        data = (int)(clwm);
+        fifo->graphics_lwm = data;
+        fifo->graphics_burst_size = 128;
+        data = (int)((vlwm+15));
+        fifo->video_lwm = data;
+        fifo->video_burst_size = vbs;
+    }
+}
+static void nv4UpdateArbitrationSettings
+(
+    unsigned      VClk, 
+    unsigned      pixelDepth, 
+    unsigned     *burst,
+    unsigned     *lwm,
+    RIVA_HW_INST *chip
+)
+{
+    nv4_fifo_info fifo_data;
+    nv4_sim_state sim_data;
+    unsigned int M, N, P, pll, MClk, NVClk, cfg1;
+
+    pll = chip->PRAMDAC[0x00000504/4];
+    M = (pll >> 0)  & 0xFF; N = (pll >> 8)  & 0xFF; P = (pll >> 16) & 0x0F;
+    MClk  = (N * chip->CrystalFreqKHz / M) >> P;
+    pll = chip->PRAMDAC[0x00000500/4];
+    M = (pll >> 0)  & 0xFF; N = (pll >> 8)  & 0xFF; P = (pll >> 16) & 0x0F;
+    NVClk  = (N * chip->CrystalFreqKHz / M) >> P;
+    cfg1 = chip->PFB[0x00000204/4];
+    sim_data.pix_bpp        = (char)pixelDepth;
+    sim_data.enable_video   = 0;
+    sim_data.enable_mp      = 0;
+    sim_data.memory_width   = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
+    sim_data.mem_latency    = (char)cfg1 & 0x0F;
+    sim_data.mem_aligned    = 1;
+    sim_data.mem_page_miss  = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
+    sim_data.gr_during_vid  = 0;
+    sim_data.pclk_khz       = VClk;
+    sim_data.mclk_khz       = MClk;
+    sim_data.nvclk_khz      = NVClk;
+    nv4CalcArbitration(&fifo_data, &sim_data);
+    if (fifo_data.valid)
+    {
+        int  b = fifo_data.graphics_burst_size >> 4;
+        *burst = 0;
+        while (b >>= 1) (*burst)++;
+        *lwm   = fifo_data.graphics_lwm >> 3;
+    }
+}
+
+/****************************************************************************\
+*                                                                            *
+*                          RIVA Mode State Routines                          *
+*                                                                            *
+\****************************************************************************/
+
+/*
+ * Calculate the Video Clock parameters for the PLL.
+ */
+static int CalcVClock
+(
+    int           clockIn,
+    int          *clockOut,
+    int          *mOut,
+    int          *nOut,
+    int          *pOut,
+    RIVA_HW_INST *chip
+)
+{
+    unsigned lowM, highM, highP;
+    unsigned DeltaNew, DeltaOld;
+    unsigned VClk, Freq;
+    unsigned M, N, P;
+    
+    DeltaOld = 0xFFFFFFFF;
+    VClk     = (unsigned)clockIn;
+    if (chip->CrystalFreqKHz == 14318)
+    {
+        lowM  = 8;
+        highM = 14 - (chip->Architecture == 3);
+    }
+    else
+    {
+        lowM  = 7;
+        highM = 13 - (chip->Architecture == 3);
+    }                      
+    highP = 4 - (chip->Architecture == 3);
+    for (P = 0; P <= highP; P ++)
+    {
+        Freq = VClk << P;
+        if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
+        {
+            for (M = lowM; M <= highM; M++)
+            {
+                N    = (VClk * M / chip->CrystalFreqKHz) << P;
+                Freq = (chip->CrystalFreqKHz * N / M) >> P;
+                if (Freq > VClk)
+                    DeltaNew = Freq - VClk;
+                else
+                    DeltaNew = VClk - Freq;
+                if (DeltaNew < DeltaOld)
+                {
+                    *mOut     = M;
+                    *nOut     = N;
+                    *pOut     = P;
+                    *clockOut = Freq;
+                    DeltaOld  = DeltaNew;
+                }
+            }
+        }
+    }
+    return (DeltaOld != 0xFFFFFFFF);
+}
+/*
+ * Calculate extended mode parameters (SVGA) and save in a 
+ * mode state structure.
+ */
+static void CalcStateExt
+(
+    RIVA_HW_INST  *chip,
+    RIVA_HW_STATE *state,
+    int            bpp,
+    int            width,
+    int            hDisplaySize,
+    int            hDisplay,
+    int            hStart,
+    int            hEnd,
+    int            hTotal,
+    int            height,
+    int            vDisplay,
+    int            vStart,
+    int            vEnd,
+    int            vTotal,
+    int            dotClock
+)
+{
+    int pixelDepth, VClk, m, n, p;
+    /*
+     * Save mode parameters.
+     */
+    state->bpp    = bpp;
+    state->width  = width;
+    state->height = height;
+    /*
+     * Extended RIVA registers.
+     */
+    pixelDepth = (bpp + 1)/8;
+    CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
+    switch (chip->Architecture)
+    {
+	    case 3:
+            nv3UpdateArbitrationSettings(VClk, 
+                                         pixelDepth * 8, 
+                                        &(state->arbitration0),
+                                        &(state->arbitration1),
+                                         chip);
+            state->cursor0  = 0x00;
+            state->cursor1  = 0x78;
+            state->cursor2  = 0x00000000;
+            state->pllsel   = 0x10010100;
+            state->config   = ((width + 31)/32)
+                            | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
+                            | 0x1000;
+            state->general  = 0x00000100;
+            state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
+            break;
+	    case 4:
+	    case 5:
+            nv4UpdateArbitrationSettings(VClk, 
+                                         pixelDepth * 8, 
+                                        &(state->arbitration0),
+                                        &(state->arbitration1),
+                                         chip);
+            state->cursor0  = 0x00;
+            state->cursor1  = 0xFC;
+            state->cursor2  = 0x00000000;
+            state->pllsel   = 0x10000700;
+            state->config   = 0x00001114;
+            state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
+            state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
+            break;
+    }
+    state->vpll     = (p << 16) | (n << 8) | m;
+    state->screen   = ((hTotal   & 0x040) >> 2)
+                    | ((vDisplay & 0x400) >> 7)
+                    | ((vStart   & 0x400) >> 8)
+                    | ((vDisplay & 0x400) >> 9)
+                    | ((vTotal   & 0x400) >> 10);
+    state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
+    state->horiz    = hTotal     < 260 ? 0x00 : 0x01;
+    state->pixel    = (pixelDepth > 2 ? 3 : pixelDepth) | 0x40;
+    state->offset0  =
+    state->offset1  =
+    state->offset2  =
+    state->offset3  = 0;
+    state->pitch0   =
+    state->pitch1   =
+    state->pitch2   =
+    state->pitch3   = pixelDepth * width;
+}
+/*
+ * Load fixed function state and pre-calculated/stored state.
+ */
+#define LOAD_FIXED_STATE(tbl,dev)                                       \
+    for (i = 0; i < sizeof(tbl##Table##dev)/8; i++)                 \
+        chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
+#define LOAD_FIXED_STATE_8BPP(tbl,dev)                                  \
+    for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++)            \
+        chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
+#define LOAD_FIXED_STATE_15BPP(tbl,dev)                                 \
+    for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++)           \
+        chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
+#define LOAD_FIXED_STATE_16BPP(tbl,dev)                                 \
+    for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++)           \
+        chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
+#define LOAD_FIXED_STATE_32BPP(tbl,dev)                                 \
+    for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++)           \
+        chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
+static void LoadStateExt
+(
+    RIVA_HW_INST  *chip,
+    RIVA_HW_STATE *state
+)
+{
+    int i;
+    /*
+     * Load HW fixed function state.
+     */
+    LOAD_FIXED_STATE(Riva,PMC);
+    LOAD_FIXED_STATE(Riva,PTIMER);
+    /*
+     * Make sure frame buffer config gets set before loading PRAMIN.
+     */
+    chip->PFB[0x00000200/4] = state->config;
+    switch (chip->Architecture)
+    {
+        case 3:
+            LOAD_FIXED_STATE(nv3,PFIFO);
+            LOAD_FIXED_STATE(nv3,PRAMIN);
+            LOAD_FIXED_STATE(nv3,PGRAPH);
+            switch (state->bpp)
+            {
+                case 15:
+                case 16:
+                    LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
+                    LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
+                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
+                    break;
+                case 24:
+                case 32:
+                    LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
+                    LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
+                    chip->Tri03 = 0L;
+                    break;
+                case 8:
+                default:
+                    LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
+                    LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
+                    chip->Tri03 = 0L;
+                    break;
+            }
+            for (i = 0x00000; i < 0x00800; i++)
+                chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
+            chip->PGRAPH[0x00000630/4] = state->offset0;
+            chip->PGRAPH[0x00000634/4] = state->offset1;
+            chip->PGRAPH[0x00000638/4] = state->offset2;
+            chip->PGRAPH[0x0000063C/4] = state->offset3;
+            chip->PGRAPH[0x00000650/4] = state->pitch0;
+            chip->PGRAPH[0x00000654/4] = state->pitch1;
+            chip->PGRAPH[0x00000658/4] = state->pitch2;
+            chip->PGRAPH[0x0000065C/4] = state->pitch3;
+            break;
+	    case 4:
+	    case 5:
+            LOAD_FIXED_STATE(nv4,PFIFO);
+            LOAD_FIXED_STATE(nv4,PRAMIN);
+            LOAD_FIXED_STATE(nv4,PGRAPH);
+            switch (state->bpp)
+            {
+                case 15:
+                    LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
+                    LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
+                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
+                    break;
+                case 16:
+                    LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
+                    LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
+                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
+                    break;
+                case 24:
+                case 32:
+                    LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
+                    LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
+                    chip->Tri03 = 0L;
+                    break;
+                case 8:
+                default:
+                    LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
+                    LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
+                    chip->Tri03 = 0L;
+                    break;
+            }
+            chip->PGRAPH[0x00000640/4] = state->offset0;
+            chip->PGRAPH[0x00000644/4] = state->offset1;
+            chip->PGRAPH[0x00000648/4] = state->offset2;
+            chip->PGRAPH[0x0000064C/4] = state->offset3;
+            chip->PGRAPH[0x00000670/4] = state->pitch0;
+            chip->PGRAPH[0x00000674/4] = state->pitch1;
+            chip->PGRAPH[0x00000678/4] = state->pitch2;
+            chip->PGRAPH[0x0000067C/4] = state->pitch3;
+            break;
+    }
+//NOTICE("8");
+//    LOAD_FIXED_STATE(Riva,FIFO); /* FIX ME*/
+//NOTICE("9");
+    /*
+     * Load HW mode state.
+     */
+    outb(0x19, 0x3D4); outb(state->repaint0, 0x3D5);
+    outb(0x1A, 0x3D4); outb(state->repaint1, 0x3D5);
+    outb(0x25, 0x3D4); outb(state->screen, 0x3D5);
+    outb(0x28, 0x3D4); outb(state->pixel, 0x3D5);
+    outb(0x2D, 0x3D4); outb(state->horiz, 0x3D5);
+    outb(0x1B, 0x3D4); outb(state->arbitration0, 0x3D5);
+    outb(0x20, 0x3D4); outb(state->arbitration1, 0x3D5);
+    outb(0x30, 0x3D4); outb(state->cursor0, 0x3D5);
+    outb(0x31, 0x3D4); outb(state->cursor1, 0x3D5);
+    chip->PRAMDAC[0x00000300/4]  = state->cursor2;
+    chip->PRAMDAC[0x00000508/4]  = state->vpll;
+    chip->PRAMDAC[0x0000050C/4]  = state->pllsel;
+    chip->PRAMDAC[0x00000600/4]  = state->general;
+    /*
+     * Turn off VBlank enable and reset.
+     */
+//    *(chip->VBLANKENABLE) = 0;		/* FIXME*/
+//    *(chip->VBLANK)       = chip->VBlankBit; /*FIXME*/
+    /*
+     * Set interrupt enable.
+     */    
+    chip->PMC[0x00000140/4]  = chip->EnableIRQ & 0x01;
+    /*
+     * Set current state pointer.
+     */
+    chip->CurrentState = state;
+    /*
+     * Reset FIFO free count.
+     */
+    chip->FifoFreeCount = 0;
+}
+static void UnloadStateExt
+(
+    RIVA_HW_INST  *chip,
+    RIVA_HW_STATE *state
+)
+{
+    /*
+     * Save current HW state.
+     */
+    outb(0x19, 0x3D4); state->repaint0     = inb(0x3D5);
+    outb(0x1A, 0x3D4); state->repaint1     = inb(0x3D5);
+    outb(0x25, 0x3D4); state->screen       = inb(0x3D5);
+    outb(0x28, 0x3D4); state->pixel        = inb(0x3D5);
+    outb(0x2D, 0x3D4); state->horiz        = inb(0x3D5);
+    outb(0x1B, 0x3D4); state->arbitration0 = inb(0x3D5);
+    outb(0x20, 0x3D4); state->arbitration1 = inb(0x3D5);
+    outb(0x30, 0x3D4); state->cursor0      = inb(0x3D5);
+    outb(0x31, 0x3D4); state->cursor1      = inb(0x3D5);
+                      state->cursor2      = chip->PRAMDAC[0x00000300/4];
+                      state->vpll         = chip->PRAMDAC[0x00000508/4];
+                      state->pllsel       = chip->PRAMDAC[0x0000050C/4];
+                      state->general      = chip->PRAMDAC[0x00000600/4];
+                      state->config       = chip->PFB[0x00000200/4];
+                      switch (chip->Architecture)
+                      {
+			      case 3:
+                              state->offset0  = chip->PGRAPH[0x00000630/4];
+                              state->offset1  = chip->PGRAPH[0x00000634/4];
+                              state->offset2  = chip->PGRAPH[0x00000638/4];
+                              state->offset3  = chip->PGRAPH[0x0000063C/4];
+                              state->pitch0   = chip->PGRAPH[0x00000650/4];
+                              state->pitch1   = chip->PGRAPH[0x00000654/4];
+                              state->pitch2   = chip->PGRAPH[0x00000658/4];
+                              state->pitch3   = chip->PGRAPH[0x0000065C/4];
+                              break;
+			      case 4:
+			      case 5:
+                              state->offset0  = chip->PGRAPH[0x00000640/4];
+                              state->offset1  = chip->PGRAPH[0x00000644/4];
+                              state->offset2  = chip->PGRAPH[0x00000648/4];
+                              state->offset3  = chip->PGRAPH[0x0000064C/4];
+                              state->pitch0   = chip->PGRAPH[0x00000670/4];
+                              state->pitch1   = chip->PGRAPH[0x00000674/4];
+                              state->pitch2   = chip->PGRAPH[0x00000678/4];
+                              state->pitch3   = chip->PGRAPH[0x0000067C/4];
+                              break;
+                      }
+}
+static void SetStartAddress
+(
+    RIVA_HW_INST *chip,
+    unsigned      start
+)
+{
+    int offset = start >> 2;
+    int pan    = (start & 3) << 1;
+    unsigned char tmp;
+
+    /*
+     * Unlock extended registers.
+     */
+    outb(chip->LockUnlockIndex, chip->LockUnlockIO);
+    outb(0x57, chip->LockUnlockIO + 1);
+    /*
+     * Set start address.
+     */
+    outb(0x0D, 0x3D4);
+    outb(offset, 0x3D5);
+    outb(0x0C, 0x3D4);
+    outb(offset >> 8, 0x3D5);
+    outb(0x19, 0x3D4);
+    tmp = inb(0x3D5);
+    outb(((offset >> 16) & 0x0F) | (tmp & 0xF0), 0x3D5);
+    /*
+     * 4 pixel pan register.
+     */
+    offset = inb(chip->IO + 0x0A);
+    outb(0x13, 0x3C0);
+    outb(pan, 0x3C0);
+}
+static void nv3SetSurfaces2D
+(
+    RIVA_HW_INST *chip,
+    unsigned     surf0,
+    unsigned     surf1
+)
+{
+    while (nv3Busy(chip));
+    chip->PGRAPH[0x00000630/4] = surf0;
+    chip->PGRAPH[0x00000634/4] = surf1;
+}
+static void nv4SetSurfaces2D
+(
+    RIVA_HW_INST *chip,
+    unsigned     surf0,
+    unsigned     surf1
+)
+{
+    while (nv4Busy(chip));
+    chip->PGRAPH[0x00000640/4] = surf0;
+    chip->PGRAPH[0x00000644/4] = surf1;
+}
+static void nv3SetSurfaces3D
+(
+    RIVA_HW_INST *chip,
+    unsigned     surf0,
+    unsigned     surf1
+)
+{
+    while (nv3Busy(chip));
+    chip->PGRAPH[0x00000638/4] = surf0;
+    chip->PGRAPH[0x0000063C/4] = surf1;
+}
+static void nv4SetSurfaces3D
+(
+    RIVA_HW_INST *chip,
+    unsigned     surf0,
+    unsigned     surf1
+)
+{
+    while (nv4Busy(chip));
+    chip->PGRAPH[0x00000648/4] = surf0;
+    chip->PGRAPH[0x0000064C/4] = surf1;
+}
+
+/****************************************************************************\
+*                                                                            *
+*                      Probe RIVA Chip Configuration                         *
+*                                                                            *
+\****************************************************************************/
+
+void nv3GetConfig
+(
+    RIVA_HW_INST *chip
+)
+{
+    /*
+     * Fill in chip configuration.
+     */
+    if (chip->PFB[0x00000000/4] & 0x00000020)
+    {
+        if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
+         && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
+        {        
+            /*
+             * SDRAM 128 ZX.
+             */
+            chip->RamBandwidthKBytesPerSec = 800000;
+            switch (chip->PFB[0x00000000/4] & 0x03)
+            {
+                case 2:
+                    chip->RamAmountKBytes = 1024 * 4 - 32;
+                    break;
+                case 1:
+                    chip->RamAmountKBytes = 1024 * 2 - 32;
+                    break;
+                default:
+                    chip->RamAmountKBytes = 1024 * 8 - 32;
+                    break;
+            }
+        }            
+        else            
+        {
+            chip->RamBandwidthKBytesPerSec = 1000000;
+            chip->RamAmountKBytes          = 1024 * 8 - 32;
+        }            
+    }
+    else
+    {
+        /*
+         * SGRAM 128.
+         */
+        chip->RamBandwidthKBytesPerSec = 1000000;
+        switch (chip->PFB[0x00000000/4] & 0x00000003)
+        {
+            case 0:
+                chip->RamAmountKBytes = 1024 * 8 - 32;
+                break;
+            case 2:
+                chip->RamAmountKBytes = 1024 * 4 - 32;
+                break;
+            default:
+                chip->RamAmountKBytes = 1024 * 2 - 32;
+                break;
+        }
+    }        
+    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000020) ? 14318 : 13500;
+    chip->CURSOR           = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
+    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
+    chip->VBLANKENABLE     = &(chip->PGRAPH[0x0140/4]);
+    chip->VBLANK           = &(chip->PGRAPH[0x0100/4]);
+    chip->VBlankBit        = 0x00000100;
+    chip->MaxVClockFreqKHz = 230000;
+    chip->LockUnlockIO     = 0x3C4;
+    chip->LockUnlockIndex  = 0x06;
+    /*
+     * Set chip functions.
+     */
+    chip->Busy            = nv3Busy;
+    chip->ShowHideCursor  = ShowHideCursor;
+    chip->CalcStateExt    = CalcStateExt;
+    chip->LoadStateExt    = LoadStateExt;
+    chip->UnloadStateExt  = UnloadStateExt;
+    chip->SetStartAddress = SetStartAddress;
+    chip->SetSurfaces2D   = nv3SetSurfaces2D;
+    chip->SetSurfaces3D   = nv3SetSurfaces3D;
+}
+
+void nv4GetConfig
+(
+    RIVA_HW_INST *chip
+)
+{
+    /*
+     * Fill in chip configuration.
+     */
+    switch (chip->PFB[0x00000000/4] & 0x00000003)
+    {
+        case 0:
+            chip->RamAmountKBytes = 1024 * 32 - 128;
+            break;
+        case 1:
+            chip->RamAmountKBytes = 1024 * 4 - 128;
+            break;
+        case 2:
+            chip->RamAmountKBytes = 1024 * 8 - 128;
+            break;
+        case 3:
+        default:
+            chip->RamAmountKBytes = 1024 * 16 - 128;
+            break;
+    }
+    switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
+    {
+        case 3:
+            chip->RamBandwidthKBytesPerSec = 800000;
+            break;
+        default:
+            chip->RamBandwidthKBytesPerSec = 1000000;
+            break;
+    }
+    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
+    chip->CURSOR           = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
+    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
+    chip->VBLANKENABLE     = &(chip->PCRTC[0x0140/4]);
+    chip->VBLANK           = &(chip->PCRTC[0x0100/4]);
+    chip->VBlankBit        = 0x00000001;
+    chip->MaxVClockFreqKHz = 250000;
+    chip->LockUnlockIO     = 0x3D4;
+    chip->LockUnlockIndex  = 0x1F;
+    /*
+     * Set chip functions.
+     */
+    chip->Busy            = nv4Busy;
+    chip->ShowHideCursor  = ShowHideCursor;
+    chip->CalcStateExt    = CalcStateExt;
+    chip->LoadStateExt    = LoadStateExt;
+    chip->UnloadStateExt  = UnloadStateExt;
+    chip->SetStartAddress = SetStartAddress;
+    chip->SetSurfaces2D   = nv4SetSurfaces2D;
+    chip->SetSurfaces3D   = nv4SetSurfaces3D;
+}
+
+void nv5GetConfig
+(
+    RIVA_HW_INST *chip
+)
+{
+    /*
+     * Fill in chip configuration.
+     */
+    switch (chip->PFB[0x00000000/4] & 0x00000003)
+    {
+        case 0:
+            chip->RamAmountKBytes = 1024 * 32 - 128;
+            break;
+        case 1:
+            chip->RamAmountKBytes = 1024 * 4 - 128;
+            break;
+        case 2:
+            chip->RamAmountKBytes = 1024 * 8 - 128;
+            break;
+        case 3:
+        default:
+            chip->RamAmountKBytes = 1024 * 16 - 128;
+            break;
+    }
+    switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
+    {
+        case 3:
+            chip->RamBandwidthKBytesPerSec = 800000;
+            break;
+        default:
+            chip->RamBandwidthKBytesPerSec = 1000000;
+            break;
+    }
+    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
+    chip->CURSOR           = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
+    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
+    chip->VBLANKENABLE     = &(chip->PCRTC[0x0140/4]);
+    chip->VBLANK           = &(chip->PCRTC[0x0100/4]);
+    chip->VBlankBit        = 0x00000001;
+    chip->MaxVClockFreqKHz = 250000;
+    chip->LockUnlockIO     = 0x3D4;
+    chip->LockUnlockIndex  = 0x1F;
+    /*
+     * Set chip functions.
+     */
+    chip->Busy            = nv4Busy;
+    chip->ShowHideCursor  = ShowHideCursor;
+    chip->CalcStateExt    = CalcStateExt;
+    chip->LoadStateExt    = LoadStateExt;
+    chip->UnloadStateExt  = UnloadStateExt;
+    chip->SetStartAddress = SetStartAddress;
+    chip->SetSurfaces2D   = nv4SetSurfaces2D;
+    chip->SetSurfaces3D   = nv4SetSurfaces3D;
+}
+
+int RivaGetConfig
+(
+    RIVA_HW_INST *chip
+)
+{
+    /*
+     * Save this so future SW know whats it's dealing with.
+     */
+    chip->Version = RIVA_SW_VERSION;
+    /*
+     * Chip specific configuration.
+     */
+    switch (chip->Architecture)
+    {
+        case 3:
+            nv3GetConfig(chip);
+            break;
+        case 4:
+            nv4GetConfig(chip);
+            break;
+	    case 5:
+	    nv5GetConfig(chip);
+        default:
+            return (-1);
+    }
+    /*
+     * Fill in FIFO pointers.
+     */
+    chip->Rop    = (RivaRop                 *)&(chip->FIFO[0x00000000/4]);
+    chip->Clip   = (RivaClip                *)&(chip->FIFO[0x00002000/4]);
+    chip->Patt   = (RivaPattern             *)&(chip->FIFO[0x00004000/4]);
+    chip->Pixmap = (RivaPixmap              *)&(chip->FIFO[0x00006000/4]);
+    chip->Blt    = (RivaScreenBlt           *)&(chip->FIFO[0x00008000/4]);
+    chip->Bitmap = (RivaBitmap              *)&(chip->FIFO[0x0000A000/4]);
+    chip->Tri03  = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
+    return (0);
+}
+
diff --git a/drivers/video/riva/riva_hw.h b/drivers/video/riva/riva_hw.h
new file mode 100644
index 000000000..6ab8395e5
--- /dev/null
+++ b/drivers/video/riva/riva_hw.h
@@ -0,0 +1,343 @@
+/***************************************************************************\
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
+|*     international laws.  Users and possessors of this source code are     *|
+|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
+|*     use this code in individual and commercial software.                  *|
+|*                                                                           *|
+|*     Any use of this source code must include,  in the user documenta-     *|
+|*     tion and  internal comments to the code,  notices to the end user     *|
+|*     as follows:                                                           *|
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
+|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
+|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
+|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
+|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
+|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
+|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
+|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
+|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
+|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
+|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
+|*                                                                           *|
+|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
+|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
+|*     consisting  of "commercial  computer  software"  and  "commercial     *|
+|*     computer  software  documentation,"  as such  terms  are  used in     *|
+|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
+|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
+|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
+|*     all U.S. Government End Users  acquire the source code  with only     *|
+|*     those rights set forth herein.                                        *|
+|*                                                                           *|
+\***************************************************************************/
+/* 
+ * GPL licensing note -- nVidia is allowing a liberal interpretation of 
+ * the documentation restriction above, to merely say that this nVidia's
+ * copyright and disclaimer should be included with all code derived 
+ * from this source.  -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99
+ */
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.h,v 1.1.2.2 1998/12/22 16:33:19 hohndel Exp $ */
+#ifndef __RIVA_HW_H__
+#define __RIVA_HW_H__
+#define RIVA_SW_VERSION 0x00010000
+
+/***************************************************************************\
+*                                                                           *
+*                             FIFO registers.                               *
+*                                                                           *
+\***************************************************************************/
+
+/*
+ * Raster OPeration. Windows style ROP3.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop;
+    unsigned reserved01[0x0BB];
+    unsigned Rop3;
+} RivaRop;
+/*
+ * 8X8 Monochrome pattern.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop;
+    unsigned reserved01[0x0BD];
+    unsigned Shape;
+    unsigned reserved03[0x001];
+    unsigned Color0;
+    unsigned Color1;
+    unsigned Monochrome[2];
+} RivaPattern;
+/*
+ * Scissor clip rectangle.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop;
+    unsigned reserved01[0x0BB];
+    unsigned TopLeft;
+    unsigned WidthHeight;
+} RivaClip;
+/*
+ * 2D filled rectangle.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop[1];
+    unsigned reserved01[0x0BC];
+    unsigned Color;
+    unsigned reserved03[0x03E];
+    unsigned TopLeft;
+    unsigned WidthHeight;
+} RivaRectangle;
+/*
+ * 2D screen-screen BLT.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop;
+    unsigned reserved01[0x0BB];
+    unsigned TopLeftSrc;
+    unsigned TopLeftDst;
+    unsigned WidthHeight;
+} RivaScreenBlt;
+/*
+ * 2D pixel BLT.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop[1];
+    unsigned reserved01[0x0BC];
+    unsigned TopLeft;
+    unsigned WidthHeight;
+    unsigned WidthHeightIn;
+    unsigned reserved02[0x03C];
+    unsigned Pixels;
+} RivaPixmap;
+/*
+ * Filled rectangle combined with monochrome expand.  Useful for glyphs.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop;
+    unsigned reserved01[0x0BB];
+    unsigned reserved03[(0x040)-1];
+    unsigned Color1A;
+    struct
+    {
+        unsigned TopLeft;
+        unsigned WidthHeight;
+    } UnclippedRectangle[64];
+    unsigned reserved04[(0x080)-3];
+    struct
+    {
+        unsigned TopLeft;
+        unsigned BottomRight;
+    } ClipB;
+    unsigned Color1B;
+    struct
+    {
+        unsigned TopLeft;
+        unsigned BottomRight;
+    } ClippedRectangle[64];
+    unsigned reserved05[(0x080)-5];
+    struct
+    {
+        unsigned TopLeft;
+        unsigned BottomRight;
+    } ClipC;
+    unsigned Color1C;
+    unsigned WidthHeightC;
+    unsigned PointC;
+    unsigned MonochromeData1C;
+    unsigned reserved06[(0x080)+121];
+    struct
+    {
+        unsigned TopLeft;
+        unsigned BottomRight;
+    } ClipD;
+    unsigned Color1D;
+    unsigned WidthHeightInD;
+    unsigned WidthHeightOutD;
+    unsigned PointD;
+    unsigned MonochromeData1D;
+    unsigned reserved07[(0x080)+120];
+    struct
+    {
+        unsigned TopLeft;
+        unsigned BottomRight;
+    } ClipE;
+    unsigned Color0E;
+    unsigned Color1E;
+    unsigned WidthHeightInE;
+    unsigned WidthHeightOutE;
+    unsigned PointE;
+    unsigned MonochromeData01E;
+} RivaBitmap;
+/*
+ * 3D textured, Z buffered triangle.
+ */
+typedef volatile struct
+{
+    unsigned reserved00[4];
+    unsigned short FifoFree;
+    unsigned short Nop;
+    unsigned reserved01[0x0BC];
+    unsigned TextureOffset;
+    unsigned TextureFormat;
+    unsigned TextureFilter;
+    unsigned FogColor;
+    unsigned Control;
+    unsigned AlphaTest;
+    unsigned reserved02[0x339];
+    unsigned FogAndIndex;
+    unsigned Color;
+    float ScreenX;
+    float ScreenY;
+    float ScreenZ;
+    float EyeM;
+    float TextureS;
+    float TextureT;
+} RivaTexturedTriangle03;
+
+/***************************************************************************\
+*                                                                           *
+*                        Virtualized RIVA H/W interface.                    *
+*                                                                           *
+\***************************************************************************/
+
+struct _riva_hw_inst;
+struct _riva_hw_state;
+/*
+ * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
+ */
+typedef struct _riva_hw_inst
+{
+    /*
+     * Chip specific settings.
+     */
+    unsigned Architecture;
+    unsigned Version;
+    unsigned CrystalFreqKHz;
+    unsigned RamAmountKBytes;
+    unsigned MaxVClockFreqKHz;
+    unsigned RamBandwidthKBytesPerSec;
+    unsigned EnableIRQ;
+    unsigned IO;
+    unsigned LockUnlockIO;
+    unsigned LockUnlockIndex;
+    unsigned VBlankBit;
+    unsigned FifoFreeCount;
+    /*
+     * Non-FIFO registers.
+     */
+    volatile unsigned *PCRTC;
+    volatile unsigned *PRAMDAC;
+    volatile unsigned *PFB;
+    volatile unsigned *PFIFO;
+    volatile unsigned *PGRAPH;
+    volatile unsigned *PEXTDEV;
+    volatile unsigned *PTIMER;
+    volatile unsigned *PMC;
+    volatile unsigned *PRAMIN;
+    volatile unsigned *FIFO;
+    volatile unsigned *CURSOR;
+    volatile unsigned *CURSORPOS;
+    volatile unsigned *VBLANKENABLE;
+    volatile unsigned *VBLANK;
+    /*
+     * Common chip functions.
+     */
+    int  (*Busy)(struct _riva_hw_inst *);
+    void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int);
+    void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
+    void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
+    void (*SetStartAddress)(struct _riva_hw_inst *,unsigned);
+    void (*SetSurfaces2D)(struct _riva_hw_inst *,unsigned,unsigned);
+    void (*SetSurfaces3D)(struct _riva_hw_inst *,unsigned,unsigned);
+    int  (*ShowHideCursor)(struct _riva_hw_inst *,int);
+    /*
+     * Current extended mode settings.
+     */
+    struct _riva_hw_state *CurrentState;
+    /*
+     * FIFO registers.
+     */
+    RivaRop                 *Rop;
+    RivaPattern             *Patt;
+    RivaClip                *Clip;
+    RivaPixmap              *Pixmap;
+    RivaScreenBlt           *Blt;
+    RivaBitmap              *Bitmap;
+    RivaTexturedTriangle03  *Tri03;
+} RIVA_HW_INST;
+/*
+ * Extended mode state information.
+ */
+typedef struct _riva_hw_state
+{
+    unsigned bpp;
+    unsigned width;
+    unsigned height;
+    unsigned repaint0;
+    unsigned repaint1;
+    unsigned screen;
+    unsigned pixel;
+    unsigned horiz;
+    unsigned arbitration0;
+    unsigned arbitration1;
+    unsigned vpll;
+    unsigned pllsel;
+    unsigned general;
+    unsigned config;
+    unsigned cursor0;
+    unsigned cursor1;
+    unsigned cursor2;
+    unsigned offset0;
+    unsigned offset1;
+    unsigned offset2;
+    unsigned offset3;
+    unsigned pitch0;
+    unsigned pitch1;
+    unsigned pitch2;
+    unsigned pitch3;
+} RIVA_HW_STATE;
+/*
+ * External routines.
+ */
+int RivaGetConfig(RIVA_HW_INST *);
+/*
+ * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
+ */
+#define RIVA_FIFO_FREE(hwinst,hwptr,cnt)                                    \
+{                                                                           \
+while ((hwinst).FifoFreeCount < (cnt))                                      \
+{                                                                           \
+    (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2;                 \
+}                                                                           \
+(hwinst).FifoFreeCount -= (cnt);                                            \
+}
+#endif /* __RIVA_HW_H__ */
+
diff --git a/drivers/video/riva/riva_tbl.h b/drivers/video/riva/riva_tbl.h
new file mode 100644
index 000000000..8188c0fd8
--- /dev/null
+++ b/drivers/video/riva/riva_tbl.h
@@ -0,0 +1,402 @@
+ /***************************************************************************\
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
+|*     international laws.  Users and possessors of this source code are     *|
+|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
+|*     use this code in individual and commercial software.                  *|
+|*                                                                           *|
+|*     Any use of this source code must include,  in the user documenta-     *|
+|*     tion and  internal comments to the code,  notices to the end user     *|
+|*     as follows:                                                           *|
+|*                                                                           *|
+|*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
+|*                                                                           *|
+|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
+|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
+|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
+|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
+|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
+|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
+|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
+|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
+|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
+|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
+|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
+|*                                                                           *|
+|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
+|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
+|*     consisting  of "commercial  computer  software"  and  "commercial     *|
+|*     computer  software  documentation,"  as such  terms  are  used in     *|
+|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
+|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
+|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
+|*     all U.S. Government End Users  acquire the source code  with only     *|
+|*     those rights set forth herein.                                        *|
+|*                                                                           *|
+ \***************************************************************************/
+/* 
+ * GPL licensing note -- nVidia is allowing a liberal interpretation of 
+ * the documentation restriction above, to merely say that this nVidia's
+ * copyright and disclaimer should be included with all code derived 
+ * from this source.  -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99
+ */
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_tbl.h,v 1.1.2.2 1998/12/22 16:33:20 hohndel Exp $ */
+/*
+ * RIVA Fixed Functionality Init Tables.
+ */
+static unsigned RivaTablePMC[][2] =
+{
+    {0x00000050, 0x00000000},
+    {0x00000080, 0xFFFF00FF},
+    {0x00000080, 0xFFFFFFFF}
+};
+static unsigned RivaTablePTIMER[][2] =
+{
+    {0x00000080, 0x00000008},
+    {0x00000084, 0x00000003},
+    {0x00000050, 0x00000000},
+    {0x00000040, 0xFFFFFFFF}
+};
+static unsigned RivaTableFIFO[][2] =
+{
+    {0x00000000, 0x80000000},
+    {0x00000800, 0x80000001},
+    {0x00001000, 0x80000002},
+    {0x00001800, 0x80000010},
+    {0x00002000, 0x80000011},
+    {0x00002800, 0x80000012},
+    {0x00003800, 0x80000013}
+};
+static unsigned nv3TablePFIFO[][2] =
+{
+    {0x00000140, 0x00000000},
+    {0x00000480, 0x00000000},
+    {0x00000490, 0x00000000},
+    {0x00000494, 0x00000000},
+    {0x00000481, 0x00000000},
+    {0x00000084, 0x00000000},
+    {0x00000086, 0x00002000},
+    {0x00000085, 0x00002200},
+    {0x00000484, 0x00000000},
+    {0x0000049C, 0x00000000},
+    {0x00000104, 0x00000000},
+    {0x00000108, 0x00000000},
+    {0x00000100, 0x00000000},
+    {0x000004A0, 0x00000000},
+    {0x000004A4, 0x00000000},
+    {0x000004A8, 0x00000000},
+    {0x000004AC, 0x00000000},
+    {0x000004B0, 0x00000000},
+    {0x000004B4, 0x00000000},
+    {0x000004B8, 0x00000000},
+    {0x000004BC, 0x00000000},
+    {0x00000050, 0x00000000},
+    {0x00000040, 0xFFFFFFFF},
+    {0x00000480, 0x00000001},
+    {0x00000490, 0x00000001},
+    {0x00000140, 0x00000001}
+};
+static unsigned nv3TablePGRAPH[][2] =
+{
+    {0x00000020, 0x1230001F},
+    {0x00000021, 0x10113000},
+    {0x00000022, 0x1131F101},
+    {0x00000023, 0x0100F531},
+    {0x00000060, 0x00000000},
+    {0x00000065, 0x00000000},
+    {0x00000068, 0x00000000},
+    {0x00000069, 0x00000000},
+    {0x0000006A, 0x00000000},
+    {0x0000006B, 0x00000000},
+    {0x0000006C, 0x00000000},
+    {0x0000006D, 0x00000000},
+    {0x0000006E, 0x00000000},
+    {0x0000006F, 0x00000000},
+    {0x000001A8, 0x00000000},
+    {0x00000440, 0xFFFFFFFF},
+    {0x00000480, 0x00000001},
+    {0x000001A0, 0x00000000},
+    {0x000001A2, 0x00000000},
+    {0x0000018A, 0xFFFFFFFF},
+    {0x00000190, 0x00000000},
+    {0x00000142, 0x00000000},
+    {0x00000154, 0x00000000},
+    {0x00000155, 0xFFFFFFFF},
+    {0x00000156, 0x00000000},
+    {0x00000157, 0xFFFFFFFF},
+    {0x00000064, 0x10010002},
+    {0x00000050, 0x00000000},
+    {0x00000051, 0x00000000},
+    {0x00000040, 0xFFFFFFFF},
+    {0x00000041, 0xFFFFFFFF},
+    {0x00000440, 0xFFFFFFFF},
+    {0x000001A9, 0x00000001}
+};
+static unsigned nv3TablePGRAPH_8BPP[][2] =
+{
+    {0x000001AA, 0x00001111}
+};
+static unsigned nv3TablePGRAPH_15BPP[][2] =
+{
+    {0x000001AA, 0x00002222}
+};
+static unsigned nv3TablePGRAPH_32BPP[][2] =
+{
+    {0x000001AA, 0x00003333}
+};
+static unsigned nv3TablePRAMIN[][2] =
+{
+    {0x00000500, 0x00010000},
+    {0x00000501, 0x007FFFFF},
+    {0x00000200, 0x80000000},
+    {0x00000201, 0x00C20341},
+    {0x00000204, 0x80000001},
+    {0x00000205, 0x00C50342},
+    {0x00000208, 0x80000002},
+    {0x00000209, 0x00C60343},
+    {0x00000240, 0x80000010},
+    {0x00000241, 0x00D10344},
+    {0x00000244, 0x80000011},
+    {0x00000245, 0x00D00345},
+    {0x00000248, 0x80000012},
+    {0x00000249, 0x00CC0346},
+    {0x0000024C, 0x80000013},
+    {0x0000024D, 0x00D70347},
+    {0x00000D05, 0x00000000},
+    {0x00000D06, 0x00000000},
+    {0x00000D07, 0x00000000},
+    {0x00000D09, 0x00000000},
+    {0x00000D0A, 0x00000000},
+    {0x00000D0B, 0x00000000},
+    {0x00000D0D, 0x00000000},
+    {0x00000D0E, 0x00000000},
+    {0x00000D0F, 0x00000000},
+    {0x00000D11, 0x00000000},
+    {0x00000D12, 0x00000000},
+    {0x00000D13, 0x00000000},
+    {0x00000D15, 0x00000000},
+    {0x00000D16, 0x00000000},
+    {0x00000D17, 0x00000000},
+    {0x00000D19, 0x00000000},
+    {0x00000D1A, 0x00000000},
+    {0x00000D1B, 0x00000000},
+    {0x00000D1D, 0x00000140},
+    {0x00000D1E, 0x00000000},
+    {0x00000D1F, 0x00000000}
+};
+static unsigned nv3TablePRAMIN_8BPP[][2] =
+{
+    {0x00000D04, 0x10110203},
+    {0x00000D08, 0x10110203},
+    {0x00000D0C, 0x10110203},
+    {0x00000D10, 0x10118203},
+    {0x00000D14, 0x10110203},
+    {0x00000D18, 0x10110203},
+    {0x00000D1C, 0x10419208}
+};
+static unsigned nv3TablePRAMIN_15BPP[][2] =
+{
+    {0x00000D04, 0x10110200},
+    {0x00000D08, 0x10110200},
+    {0x00000D0C, 0x10110200},
+    {0x00000D10, 0x10118200},
+    {0x00000D14, 0x10110200},
+    {0x00000D18, 0x10110200},
+    {0x00000D1C, 0x10419208}
+};
+static unsigned nv3TablePRAMIN_32BPP[][2] =
+{
+    {0x00000D04, 0x10110201},
+    {0x00000D08, 0x10110201},
+    {0x00000D0C, 0x10110201},
+    {0x00000D10, 0x10118201},
+    {0x00000D14, 0x10110201},
+    {0x00000D18, 0x10110201},
+    {0x00000D1C, 0x10419208}
+};
+static unsigned nv4TablePFIFO[][2] =
+{
+    {0x00000140, 0x00000000},
+    {0x00000480, 0x00000000},
+    {0x00000494, 0x00000000},
+    {0x00000400, 0x00000000},
+    {0x00000414, 0x00000000},
+    {0x00000084, 0x03000100},  
+    {0x00000085, 0x00000110},
+    {0x00000086, 0x00000112},  
+    {0x00000143, 0x0000FFFF},
+    {0x00000496, 0x0000FFFF},
+    {0x00000050, 0x00000000},
+    {0x00000040, 0xFFFFFFFF},
+    {0x00000415, 0x00000001},
+    {0x00000480, 0x00000001},
+    {0x00000494, 0x00000001},
+    {0x00000495, 0x00000001},
+    {0x00000140, 0x00000001}
+};
+static unsigned nv4TablePGRAPH[][2] =
+{
+    {0x00000020, 0x1231C001},
+    {0x00000021, 0x72111101},
+    {0x00000022, 0x11D5F071},
+    {0x00000023, 0x10D4FF31},
+    {0x00000060, 0x00000000},
+    {0x00000068, 0x00000000},
+    {0x00000070, 0x00000000},
+    {0x00000078, 0x00000000},
+    {0x00000061, 0x00000000},
+    {0x00000069, 0x00000000},
+    {0x00000071, 0x00000000},
+    {0x00000079, 0x00000000},
+    {0x00000062, 0x00000000},
+    {0x0000006A, 0x00000000},
+    {0x00000072, 0x00000000},
+    {0x0000007A, 0x00000000},
+    {0x00000063, 0x00000000},
+    {0x0000006B, 0x00000000},
+    {0x00000073, 0x00000000},
+    {0x0000007B, 0x00000000},
+    {0x00000064, 0x00000000},
+    {0x0000006C, 0x00000000},
+    {0x00000074, 0x00000000},
+    {0x0000007C, 0x00000000},
+    {0x00000065, 0x00000000},
+    {0x0000006D, 0x00000000},
+    {0x00000075, 0x00000000},
+    {0x0000007D, 0x00000000},
+    {0x00000066, 0x00000000},
+    {0x0000006E, 0x00000000},
+    {0x00000076, 0x00000000},
+    {0x0000007E, 0x00000000},
+    {0x00000067, 0x00000000},
+    {0x0000006F, 0x00000000},
+    {0x00000077, 0x00000000},
+    {0x0000007F, 0x00000000},
+    {0x00000058, 0x00000000},
+    {0x00000059, 0x00000000},
+    {0x0000005A, 0x00000000},
+    {0x0000005B, 0x00000000},
+    {0x00000196, 0x00000000},
+    {0x000001A1, 0x00FFFFFF},
+    {0x00000197, 0x00000000},
+    {0x000001A2, 0x00FFFFFF},
+    {0x00000198, 0x00000000},
+    {0x000001A3, 0x00FFFFFF},
+    {0x00000199, 0x00000000},
+    {0x000001A4, 0x00FFFFFF},
+    {0x00000050, 0x00000000},
+    {0x00000040, 0xFFFFFFFF},
+    {0x0000005C, 0x10010100},
+    {0x000001C8, 0x00000001}
+};
+static unsigned nv4TablePGRAPH_8BPP[][2] =
+{
+    {0x000001C4, 0xFFFFFFFF},
+    {0x000001C9, 0x00111111},
+    {0x00000186, 0x00001010},
+    {0x0000020C, 0x01010101}
+};
+static unsigned nv4TablePGRAPH_15BPP[][2] =
+{
+    {0x000001C4, 0xFFFFFFFF},
+    {0x000001C9, 0x00226222},
+    {0x00000186, 0x00002071},
+    {0x0000020C, 0x09090909}
+};
+static unsigned nv4TablePGRAPH_16BPP[][2] =
+{
+    {0x000001C4, 0xFFFFFFFF},
+    {0x000001C9, 0x00556555},
+    {0x00000186, 0x000050C2},
+    {0x0000020C, 0x0C0C0C0C}
+};
+static unsigned nv4TablePGRAPH_32BPP[][2] =
+{
+    {0x000001C4, 0xFFFFFFFF},
+    {0x000001C9, 0x0077D777},
+    {0x00000186, 0x000070E5},
+    {0x0000020C, 0x07070707}
+};
+static unsigned nv4TablePRAMIN[][2] =
+{
+    {0x00000000, 0x80000010},
+    {0x00000001, 0x80011145},
+    {0x00000002, 0x80000011},
+    {0x00000003, 0x80011146},
+    {0x00000004, 0x80000012},
+    {0x00000005, 0x80011147},
+    {0x00000006, 0x80000013},
+    {0x00000007, 0x80011148},
+    {0x00000020, 0x80000000},
+    {0x00000021, 0x80011142},
+    {0x00000022, 0x80000001},
+    {0x00000023, 0x80011143},
+    {0x00000024, 0x80000002},
+    {0x00000025, 0x80011144}, 
+    {0x00000500, 0x00003000},
+    {0x00000501, 0x02FFFFFF},
+    {0x00000502, 0x00000002},
+    {0x00000503, 0x00000002},
+    {0x00000508, 0x01008043},
+    {0x0000050A, 0x00000000},
+    {0x0000050B, 0x00000000},
+    {0x0000050C, 0x01008019},
+    {0x0000050E, 0x00000000},
+    {0x0000050F, 0x00000000},
+    {0x00000510, 0x01008018},
+    {0x00000512, 0x00000000},
+    {0x00000513, 0x00000000},
+    {0x00000514, 0x0100A033},
+    {0x00000516, 0x00000000},
+    {0x00000517, 0x00000000},
+    {0x00000518, 0x0100805F},
+    {0x0000051A, 0x00000000},
+    {0x0000051B, 0x00000000},
+    {0x0000051C, 0x0100804B},
+    {0x0000051E, 0x00000000},
+    {0x0000051F, 0x00000000},
+    {0x00000520, 0x0100A048},
+    {0x00000521, 0x00000D01},
+    {0x00000522, 0x11401140},
+    {0x00000523, 0x00000000}
+};
+static unsigned nv4TablePRAMIN_8BPP[][2] =
+{
+    {0x00000509, 0x00000301},
+    {0x0000050D, 0x00000301},
+    {0x00000511, 0x00000301},
+    {0x00000515, 0x00000301},
+    {0x00000519, 0x00000301},
+    {0x0000051D, 0x00000301}
+};
+static unsigned nv4TablePRAMIN_15BPP[][2] =
+{
+    {0x00000509, 0x00000901},
+    {0x0000050D, 0x00000901},
+    {0x00000511, 0x00000901},
+    {0x00000515, 0x00000901},
+    {0x00000519, 0x00000901},
+    {0x0000051D, 0x00000901}
+};
+static unsigned nv4TablePRAMIN_16BPP[][2] =
+{
+    {0x00000509, 0x00000C01},
+    {0x0000050D, 0x00000C01},
+    {0x00000511, 0x00000C01},
+    {0x00000515, 0x00000C01},
+    {0x00000519, 0x00000C01},
+    {0x0000051D, 0x00000C01}
+};
+static unsigned nv4TablePRAMIN_32BPP[][2] =
+{
+    {0x00000509, 0x00000E01},
+    {0x0000050D, 0x00000E01},
+    {0x00000511, 0x00000E01},
+    {0x00000515, 0x00000E01},
+    {0x00000519, 0x00000E01},
+    {0x0000051D, 0x00000E01}
+};
+
diff --git a/include/asm-arm/arch-nexuspci/ide.h b/include/asm-arm/arch-nexuspci/ide.h
new file mode 100644
index 000000000..cb1eac75a
--- /dev/null
+++ b/include/asm-arm/arch-nexuspci/ide.h
@@ -0,0 +1,36 @@
+/*
+ * linux/include/asm-arm/arch-nexuspci/ide.h
+ *
+ * Copyright (c) 1998 Russell King
+ *
+ * Modifications:
+ *  29-07-1998	RMK	Major re-work of IDE architecture specific code
+ */
+#include <asm/irq.h>
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+static __inline__ void
+ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int irq)
+{
+	ide_ioreg_t reg = (ide_ioreg_t) data_port;
+	int i;
+
+	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+		hw->io_ports[i] = reg;
+		reg += 1;
+	}
+	hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
+	hw->irq = irq;
+}
+
+/*
+ * This registers the standard ports for this architecture with the IDE
+ * driver.
+ */
+static __inline__ void ide_init_default_hwifs(void)
+{
+	/* There are no standard ports */
+}
diff --git a/include/asm-arm/arch-nexuspci/keyboard.h b/include/asm-arm/arch-nexuspci/keyboard.h
new file mode 100644
index 000000000..633405d55
--- /dev/null
+++ b/include/asm-arm/arch-nexuspci/keyboard.h
@@ -0,0 +1,29 @@
+/*
+ * linux/include/asm-arm/arch-nexuspci/keyboard.h
+ *
+ * Driver definitions for PCI card dummy keyboard.
+ *
+ * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998 Philip Blundell
+ */
+
+#define NR_SCANCODES 128
+
+#define kbd_setkeycode(sc,kc)		(-EINVAL)
+#define kbd_getkeycode(sc)		(-EINVAL)
+
+/* Prototype: int kbd_pretranslate(scancode, raw_mode)
+ * Returns  : 0 to ignore scancode
+ */
+#define kbd_pretranslate(sc,rm)	(1)
+
+/* Prototype: int kbd_translate(scancode, *keycode, *up_flag, raw_mode)
+ * Returns  : 0 to ignore scancode, *keycode set to keycode, *up_flag
+ *            set to 0200 if scancode indicates release
+ */
+#define kbd_translate(sc, kcp, rm) 0
+#define kbd_unexpected_up(kc)		(0200)
+#define kbd_leds(leds)			do { } while (0)
+#define kbd_init_hw()			do { } while (0)
+#define kbd_disable_irq()		do { } while (0)
+#define kbd_enable_irq()		do { } while (0)
diff --git a/include/linux/brlock.h b/include/linux/brlock.h
new file mode 100644
index 000000000..f28ac1eb7
--- /dev/null
+++ b/include/linux/brlock.h
@@ -0,0 +1,207 @@
+#ifndef __LINUX_BRLOCK_H
+#define __LINUX_BRLOCK_H
+
+/*
+ * 'Big Reader' read-write spinlocks.
+ *
+ * super-fast read/write locks, with write-side penalty. The point
+ * is to have a per-CPU read/write lock. Readers lock their CPU-local
+ * readlock, writers must lock all locks to get write access. These
+ * CPU-read-write locks are semantically identical to normal rwlocks.
+ * Memory usage is higher as well. (NR_CPUS*L1_CACHE_BYTES bytes)
+ *
+ * The most important feature is that these spinlocks do not cause
+ * cacheline ping-pong in the 'most readonly data' case.
+ *
+ * Copyright 2000, Ingo Molnar <mingo@redhat.com>
+ *
+ * Registry idea and naming [ crutial! :-) ] by:
+ *
+ *                 David S. Miller <davem@redhat.com>
+ *
+ * David has an implementation that doesnt use atomic operations in
+ * the read branch via memory ordering tricks - i guess we need to
+ * split this up into a per-arch thing? The atomicity issue is a
+ * secondary item in profiles, at least on x86 platforms.
+ *
+ * The atomic op version overhead is indeed a big deal on
+ * load-locked/store-conditional cpus (ALPHA/MIPS/PPC) and
+ * compare-and-swap cpus (Sparc64).  So we control which
+ * implementation to use with a __BRLOCK_USE_ATOMICS define. -DaveM
+ */
+
+/* Register bigreader lock indices here. */
+enum brlock_indices {
+	BR_GLOBALIRQ_LOCK,
+	BR_NETPROTO_LOCK,
+
+	__BR_END
+};
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SMP
+
+#include <linux/cache.h>
+#include <linux/spinlock.h>
+
+#if defined(__i386__)
+#define __BRLOCK_USE_ATOMICS
+#else
+#undef __BRLOCK_USE_ATOMICS
+#endif
+
+#ifdef __BRLOCK_USE_ATOMICS
+typedef rwlock_t	brlock_read_lock_t;
+#else
+typedef unsigned int	brlock_read_lock_t;
+#endif
+
+/*
+ * align last allocated index to the next cacheline:
+ */
+#define __BR_IDX_MAX \
+	(((sizeof(brlock_read_lock_t)*__BR_END + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1)) / sizeof(brlock_read_lock_t))
+
+extern brlock_read_lock_t __brlock_array[NR_CPUS][__BR_IDX_MAX];
+
+#ifndef __BRLOCK_USE_ATOMICS
+struct br_wrlock {
+	spinlock_t lock;
+} __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
+
+extern struct br_wrlock __br_write_locks[__BR_IDX_MAX];
+#endif
+
+extern void __br_lock_usage_bug (void);
+
+#ifdef __BRLOCK_USE_ATOMICS
+
+extern inline void br_read_lock (enum brlock_indices idx)
+{
+	/*
+	 * This causes a link-time bug message if an
+	 * invalid index is used:
+	 */
+	if (idx >= __BR_END)
+		__br_lock_usage_bug();
+
+	read_lock(&__brlock_array[smp_processor_id()][idx]);
+}
+
+extern inline void br_read_unlock (enum brlock_indices idx)
+{
+	if (idx >= __BR_END)
+		__br_lock_usage_bug();
+
+	read_unlock(&__brlock_array[smp_processor_id()][idx]);
+}
+
+#else /* ! __BRLOCK_USE_ATOMICS */
+extern inline void br_read_lock (enum brlock_indices idx)
+{
+	unsigned int *ctr;
+	spinlock_t *lock;
+
+	/*
+	 * This causes a link-time bug message if an
+	 * invalid index is used:
+	 */
+	if (idx >= __BR_END)
+		__br_lock_usage_bug();
+
+	ctr = &__brlock_array[smp_processor_id()][idx];
+	lock = &__br_write_locks[idx].lock;
+again:
+	(*ctr)++;
+	rmb();
+	if (spin_is_locked(lock)) {
+		(*ctr)--;
+		rmb();
+		while (spin_is_locked(lock))
+			barrier();
+		goto again;
+	}
+}
+
+extern inline void br_read_unlock (enum brlock_indices idx)
+{
+	unsigned int *ctr;
+
+	if (idx >= __BR_END)
+		__br_lock_usage_bug();
+
+	ctr = &__brlock_array[smp_processor_id()][idx];
+
+	wmb();
+	(*ctr)--;
+}
+#endif /* __BRLOCK_USE_ATOMICS */
+
+/* write path not inlined - it's rare and larger */
+
+extern void FASTCALL(__br_write_lock (enum brlock_indices idx));
+extern void FASTCALL(__br_write_unlock (enum brlock_indices idx));
+
+extern inline void br_write_lock (enum brlock_indices idx)
+{
+	if (idx >= __BR_END)
+		__br_lock_usage_bug();
+	__br_write_lock(idx);
+}
+
+extern inline void br_write_unlock (enum brlock_indices idx)
+{
+	if (idx >= __BR_END)
+		__br_lock_usage_bug();
+	__br_write_unlock(idx);
+}
+
+#else
+# define br_read_lock(idx)	((void)(idx))
+# define br_read_unlock(idx)	((void)(idx))
+# define br_write_lock(idx)	((void)(idx))
+# define br_write_unlock(idx)	((void)(idx))
+#endif
+
+/*
+ * Now enumerate all of the possible sw/hw IRQ protected
+ * versions of the interfaces.
+ */
+#define br_read_lock_irqsave(idx, flags) \
+	do { local_irq_save(flags); br_read_lock(idx); } while (0)
+
+#define br_read_lock_irq(idx) \
+	do { local_irq_disable(); br_read_lock(idx); } while (0)
+
+#define br_read_lock_bh(idx) \
+	do { local_bh_disable(); br_read_lock(idx); } while (0)
+
+#define br_write_lock_irqsave(idx, flags) \
+	do { local_irq_save(flags); br_write_lock(idx); } while (0)
+
+#define br_write_lock_irq(idx) \
+	do { local_irq_disable(); br_write_lock(idx); } while (0)
+
+#define br_write_lock_bh(idx) \
+	do { local_bh_disable(); br_write_lock(idx); } while (0)
+
+#define br_read_unlock_irqrestore(idx, flags) \
+	do { br_read_unlock(irx); local_irq_restore(flags); } while (0)
+
+#define br_read_unlock_irq(idx) \
+	do { br_read_unlock(idx); local_irq_enable(); } while (0)
+
+#define br_read_unlock_bh(idx) \
+	do { br_read_unlock(idx); local_bh_enable(); } while (0)
+
+#define br_write_unlock_irqrestore(idx, flags) \
+	do { br_write_unlock(irx); local_irq_restore(flags); } while (0)
+
+#define br_write_unlock_irq(idx) \
+	do { br_write_unlock(idx); local_irq_enable(); } while (0)
+
+#define br_write_unlock_bh(idx) \
+	do { br_write_unlock(idx); local_bh_enable(); } while (0)
+
+#endif /* __LINUX_BRLOCK_H */
diff --git a/include/linux/if_bonding.h b/include/linux/if_bonding.h
new file mode 100644
index 000000000..d077aeb57
--- /dev/null
+++ b/include/linux/if_bonding.h
@@ -0,0 +1,33 @@
+/*
+ * Bond several ethernet interfaces into a Cisco, running 'Etherchannel'.
+ *
+ * 
+ * Portions are (c) Copyright 1995 Simon "Guru Aleph-Null" Janes
+ * NCM: Network and Communications Management, Inc.
+ *
+ * BUT, I'm the one who modified it for ethernet, so:
+ * (c) Copyright 1999, Thomas Davis, tadavis@lbl.gov
+ *
+ *	This software may be used and distributed according to the terms
+ *	of the GNU Public License, incorporated herein by reference.
+ * 
+ */
+
+#ifndef _LINUX_IF_BONDING_H
+#define _LINUX_IF_BONDING_H
+
+#define BOND_ENSLAVE     (SIOCDEVPRIVATE)
+#define BOND_RELEASE     (SIOCDEVPRIVATE + 1)
+#define BOND_SETHWADDR   (SIOCDEVPRIVATE + 2)
+
+#endif /* _LINUX_BOND_H */
+
+/*
+ * Local variables:
+ *  version-control: t
+ *  kept-new-versions: 5
+ *  c-indent-level: 8
+ *  c-basic-offset: 8
+ *  tab-width: 8
+ * End:
+ */
diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h
new file mode 100644
index 000000000..be5ea2afa
--- /dev/null
+++ b/include/linux/netfilter_ipv6.h
@@ -0,0 +1,57 @@
+#ifndef __LINUX_IP6_NETFILTER_H
+#define __LINUX_IP6_NETFILTER_H
+
+/* IPv6-specific defines for netfilter. 
+ * (C)1998 Rusty Russell -- This code is GPL.
+ * (C)1999 David Jeffery
+ *   this header was blatantly ripped from netfilter_ipv4.h 
+ *   it's amazing what adding a bunch of 6s can do =8^)
+ */
+
+#include <linux/netfilter.h>
+
+/* IP Cache bits. */
+/* Src IP address. */
+#define NFC_IP6_SRC              0x0001
+/* Dest IP address. */
+#define NFC_IP6_DST              0x0002
+/* Input device. */
+#define NFC_IP6_IF_IN            0x0004
+/* Output device. */
+#define NFC_IP6_IF_OUT           0x0008
+/* TOS. */
+#define NFC_IP6_TOS              0x0010
+/* Protocol. */
+#define NFC_IP6_PROTO            0x0020
+/* IP options. */
+#define NFC_IP6_OPTIONS          0x0040
+/* Frag & flags. */
+#define NFC_IP6_FRAG             0x0080
+
+
+/* Per-protocol information: only matters if proto match. */
+/* TCP flags. */
+#define NFC_IP6_TCPFLAGS         0x0100
+/* Source port. */
+#define NFC_IP6_SRC_PT           0x0200
+/* Dest port. */
+#define NFC_IP6_DST_PT           0x0400
+/* Something else about the proto */
+#define NFC_IP6_PROTO_UNKNOWN    0x2000
+
+
+/* IP6 Hooks */
+/* After promisc drops, checksum checks. */
+#define NF_IP6_PRE_ROUTING	0
+/* If the packet is destined for this box. */
+#define NF_IP6_LOCAL_IN		1
+/* If the packet is destined for another interface. */
+#define NF_IP6_FORWARD		2
+/* Packets coming from a local process. */
+#define NF_IP6_LOCAL_OUT		3
+/* Packets about to hit the wire. */
+#define NF_IP6_POST_ROUTING	4
+#define NF_IP6_NUMHOOKS		5
+
+
+#endif /*__LINUX_IP6_NETFILTER_H*/
diff --git a/lib/brlock.c b/lib/brlock.c
new file mode 100644
index 000000000..3c3577309
--- /dev/null
+++ b/lib/brlock.c
@@ -0,0 +1,65 @@
+/*
+ *
+ * linux/lib/brlock.c
+ *
+ * 'Big Reader' read-write spinlocks.  See linux/brlock.h for details.
+ *
+ * Copyright 2000, Ingo Molnar <mingo@redhat.com>
+ * Copyright 2000, David S. Miller <davem@redhat.com>
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SMP
+
+#include <linux/sched.h>
+#include <linux/brlock.h>
+
+#ifdef __BRLOCK_USE_ATOMICS
+
+brlock_read_lock_t __brlock_array[NR_CPUS][__BR_IDX_MAX] =
+   { [0 ... NR_CPUS-1] = { [0 ... __BR_IDX_MAX-1] = RW_LOCK_UNLOCKED } };
+
+void __br_write_lock (enum brlock_indices idx)
+{
+	int i;
+
+	for (i = 0; i < smp_num_cpus; i++)
+		write_lock(__brlock_array[idx] + i);
+}
+
+void __br_write_unlock (enum brlock_indices idx)
+{
+	int i;
+
+	for (i = 0; i < smp_num_cpus; i++)
+		write_unlock(__brlock_array[idx] + i);
+}
+
+#else /* ! __BRLOCK_USE_ATOMICS */
+
+brlock_read_lock_t __brlock_array[NR_CPUS][__BR_IDX_MAX] =
+   { [0 ... NR_CPUS-1] = { [0 ... __BR_IDX_MAX-1] = 0 } };
+
+struct br_wrlock __br_write_locks[__BR_IDX_MAX] =
+   { [0 ... __BR_IDX_MAX-1] = { SPIN_LOCK_UNLOCKED } };
+
+void __br_write_lock (enum brlock_indices idx)
+{
+	int i;
+
+	spin_lock(&__br_write_locks[idx].lock);
+again:
+	for (i = 0; i < smp_num_cpus; i++)
+		if (__brlock_array[i][idx] != 0)
+			goto again;
+}
+
+void __br_write_unlock (enum brlock_indices idx)
+{
+	spin_unlock(&__br_write_locks[idx].lock);
+}
+
+#endif /* __BRLOCK_USE_ATOMICS */
+
+#endif /* CONFIG_SMP */