diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-02-05 01:33:01 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-02-05 01:33:01 +0000 |
| commit | 222ce6477d35d0b51fe9d5fb16ada90ac3341500 (patch) | |
| tree | 33dc535dde84fab2a5cd175e0bfda393d5970f42 /arch/mips/gt64120/momenco_ocelot/int-handler.S | |
| parent | 41f766e193858f7b5d1f9e81f50f392c1bd40f32 (diff) | |
Start of an attempt to unify support for GT64120 based boards.
Diffstat (limited to 'arch/mips/gt64120/momenco_ocelot/int-handler.S')
| -rw-r--r-- | arch/mips/gt64120/momenco_ocelot/int-handler.S | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/mips/gt64120/momenco_ocelot/int-handler.S b/arch/mips/gt64120/momenco_ocelot/int-handler.S new file mode 100644 index 000000000..df0525833 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/int-handler.S @@ -0,0 +1,89 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for ocelot board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/config.h> +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + +/* + * first level interrupt dispatcher for ocelot board - + * We check for the timer first, then check PCI ints A and D. + * Then check for serial IRQ and fall through. + */ + .align 5 + NESTED(ocelot_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP2 /* int0 hardware line */ + bnez t1, ll_pri_enet_irq + andi t1, t0, STATUSF_IP3 /* int1 hardware line */ + bnez t1, ll_sec_enet_irq + andi t1, t0, STATUSF_IP4 /* int2 hardware line */ + bnez t1, ll_uart1_irq + andi t1, t0, STATUSF_IP5 /* int3 hardware line */ + bnez t1, ll_cpci_irq + andi t1, t0, STATUSF_IP6 /* int4 hardware line */ + bnez t1, ll_galileo_irq + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cputimer_irq + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ocelot_handle_int) + + .align 5 +ll_pri_enet_irq: + li a0, 2 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_sec_enet_irq: + li a0, 3 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_uart1_irq: + li a0, 4 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpci_irq: + li a0, 5 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_galileo_irq: + li a0, 6 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cputimer_irq: + li a0, 7 + move a1, sp + jal do_IRQ + j ret_from_irq + |