diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-03-11 21:52:24 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-03-11 21:52:24 +0000 |
| commit | 34b560ff2837a78a20af84d332d59ea8a68f277e (patch) | |
| tree | f6f438e7d29711555e773c6db0200f5d11bc25ad /arch/mips/gt64120 | |
| parent | dd422013dc7f307f70a893fcf18b95c47b144823 (diff) | |
Replace set_cp0_status / set_cp0_config by three functions, clear_cp0_*,
set_cp0_* and change_cp0_* which makes the kernel code somewhat more
readable. Going through the kernel code I notices some stupid abuse of
the old function like set_cp0_status(ST0_BEV, 1) - this clear ST0_BEV
but actually looks like attempting to set it and other abuses, so will
people please look over their code again.
Diffstat (limited to 'arch/mips/gt64120')
| -rw-r--r-- | arch/mips/gt64120/momenco_ocelot/irq.c | 6 | ||||
| -rw-r--r-- | arch/mips/gt64120/momenco_ocelot/reset.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c index 407031e6a..d93b86a7b 100644 --- a/arch/mips/gt64120/momenco_ocelot/irq.c +++ b/arch/mips/gt64120/momenco_ocelot/irq.c @@ -129,9 +129,9 @@ void momenco_ocelot_irq_setup(void) /* * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap */ - set_cp0_status(ST0_IM, 0); - set_cp0_status(ST0_BEV, 1); /* int-handler is not on bootstrap */ + clear_cp0_status(ST0_IM | ST0_BEV); /* Sets the first-level interrupt dispatcher. */ set_except_vector(0, ocelot_handle_int); @@ -142,7 +142,7 @@ void momenco_ocelot_irq_setup(void) * Enable timer. Other interrupts will be enabled as they are * registered. */ - // set_cp0_status(ST0_IM, IE_IRQ4); + // change_cp0_status(ST0_IM, IE_IRQ4); #ifdef CONFIG_REMOTE_DEBUG diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c index 0f4c7fee6..a54b9d6ff 100644 --- a/arch/mips/gt64120/momenco_ocelot/reset.c +++ b/arch/mips/gt64120/momenco_ocelot/reset.c @@ -26,7 +26,7 @@ void momenco_ocelot_restart(char *command) * kernel in the flush locks up somewhen during of after the PCI * detection stuff. */ - set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); + clear_cp0_status(ST0_BEV | ST0_ERL); set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); flush_cache_all(); write_32bit_cp0_register(CP0_WIRED, 0); |