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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>1997-07-29 22:54:51 +0000
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>1997-07-29 22:54:51 +0000
commit4cb06d704b3e730c2517ec5c6b55010d93be4b0a (patch)
tree8ed949a465a4d6e5120eea3ba29ec6a4c3408ddf /arch/mips/mm/andes.c
parent567a5f5384cdc20afe9d10f5147c9b3e1ad6fb5c (diff)
added add_wired_entry(); at the moment it's only implemented in r4xx0.c
Diffstat (limited to 'arch/mips/mm/andes.c')
-rw-r--r--arch/mips/mm/andes.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/mips/mm/andes.c b/arch/mips/mm/andes.c
index ee0771a74..4ef02dfa0 100644
--- a/arch/mips/mm/andes.c
+++ b/arch/mips/mm/andes.c
@@ -1,4 +1,4 @@
-/* $Id: andes.c,v 1.3 1996/07/29 11:10:06 dm Exp $
+/* $Id: andes.c,v 1.1.1.1 1997/06/01 03:16:38 ralf Exp $
* andes.c: MMU and cache operations for the R10000 (ANDES).
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
@@ -79,6 +79,12 @@ static void andes_pgd_init(unsigned long page)
{
}
+static void andes_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+ unsigned long entryhi, unsigned long pagemask)
+{
+ /* XXX */
+}
+
void ld_mmu_andes(void)
{
flush_cache_all = andes_flush_cache_all;
@@ -92,6 +98,8 @@ void ld_mmu_andes(void)
flush_tlb_mm = andes_flush_tlb_mm;
flush_tlb_range = andes_flush_tlb_range;
flush_tlb_page = andes_flush_tlb_page;
+
+ add_wired_entry = andes_add_wired_entry;
load_pgd = andes_load_pgd;
pgd_init = andes_pgd_init;