Merge with Linux 2.3.23. The new bootmem stuff has broken various

platforms.  At this time I've only verified that IP22 support compiles
and IP27 actually works.

1 files changed, 82 insertions, 2 deletions

diff --git a/arch/mips/mm/andes.c b/arch/mips/mm/andes.c
index 05a722cf3..3230106b8 100644
--- a/arch/mips/mm/andes.c
+++ b/arch/mips/mm/andes.c
@@ -1,4 +1,4 @@
-/* $Id: andes.c,v 1.7 1999/08/09 19:43:16 harald Exp $
+/* $Id: andes.c,v 1.8 1999/10/09 00:00:58 ralf Exp $
  *
  * andes.c: MMU and cache operations for the R10000 (ANDES).
  *
@@ -14,6 +14,83 @@
 #include <asm/sgialib.h>
 #include <asm/mmu_context.h>
 
+/* page functions */
+void andes_clear_page(void * page)
+{
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		"addiu\t$1,%0,%2\n"
+		"1:\tsw\t$0,(%0)\n\t"
+		"sw\t$0,4(%0)\n\t"
+		"sw\t$0,8(%0)\n\t"
+		"sw\t$0,12(%0)\n\t"
+		"addiu\t%0,32\n\t"
+		"sw\t$0,-16(%0)\n\t"
+		"sw\t$0,-12(%0)\n\t"
+		"sw\t$0,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t$0,-4(%0)\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (page)
+		:"0" (page),
+		 "I" (PAGE_SIZE)
+		:"$1","memory");
+}
+
+static void andes_copy_page(void * to, void * from)
+{
+	unsigned long dummy1, dummy2;
+	unsigned long reg1, reg2, reg3, reg4;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		"addiu\t$1,%0,%8\n"
+		"1:\tlw\t%2,(%1)\n\t"
+		"lw\t%3,4(%1)\n\t"
+		"lw\t%4,8(%1)\n\t"
+		"lw\t%5,12(%1)\n\t"
+		"sw\t%2,(%0)\n\t"
+		"sw\t%3,4(%0)\n\t"
+		"sw\t%4,8(%0)\n\t"
+		"sw\t%5,12(%0)\n\t"
+		"lw\t%2,16(%1)\n\t"
+		"lw\t%3,20(%1)\n\t"
+		"lw\t%4,24(%1)\n\t"
+		"lw\t%5,28(%1)\n\t"
+		"sw\t%2,16(%0)\n\t"
+		"sw\t%3,20(%0)\n\t"
+		"sw\t%4,24(%0)\n\t"
+		"sw\t%5,28(%0)\n\t"
+		"addiu\t%0,64\n\t"
+		"addiu\t%1,64\n\t"
+		"lw\t%2,-32(%1)\n\t"
+		"lw\t%3,-28(%1)\n\t"
+		"lw\t%4,-24(%1)\n\t"
+		"lw\t%5,-20(%1)\n\t"
+		"sw\t%2,-32(%0)\n\t"
+		"sw\t%3,-28(%0)\n\t"
+		"sw\t%4,-24(%0)\n\t"
+		"sw\t%5,-20(%0)\n\t"
+		"lw\t%2,-16(%1)\n\t"
+		"lw\t%3,-12(%1)\n\t"
+		"lw\t%4,-8(%1)\n\t"
+		"lw\t%5,-4(%1)\n\t"
+		"sw\t%2,-16(%0)\n\t"
+		"sw\t%3,-12(%0)\n\t"
+		"sw\t%4,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t%5,-4(%0)\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (dummy1), "=r" (dummy2),
+		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
+		:"0" (to), "1" (from),
+		 "I" (PAGE_SIZE));
+}
+
 /* Cache operations. XXX Write these dave... */
 static inline void andes_flush_cache_all(void)
 {
@@ -38,7 +115,7 @@ static void andes_flush_cache_page(struct vm_area_struct *vma,
 	/* XXX */
 }
 
-static void andes_flush_page_to_ram(unsigned long page)
+static void andes_flush_page_to_ram(struct page * page)
 {
 	/* XXX */
 }
@@ -86,6 +163,9 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 
 void __init ld_mmu_andes(void)
 {
+	clear_page = andes_clear_page;
+	copy_page = andes_copy_page;
+
 	flush_cache_all = andes_flush_cache_all;
 	flush_cache_mm = andes_flush_cache_mm;
 	flush_cache_range = andes_flush_cache_range;