diff options
author | Harald Koerfgen <hkoerfg@web.de> | 1999-08-09 19:43:13 +0000 |
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committer | Harald Koerfgen <hkoerfg@web.de> | 1999-08-09 19:43:13 +0000 |
commit | f67e4ffc79905482c3b9b8c8dd65197bac7eb508 (patch) | |
tree | c88163a075d06cf625e7f7aa69572144806d1175 /arch/mips/mm/andes.c | |
parent | 920be6021d3cd30ce10b1423b565f304736bf899 (diff) |
My proposal for non-generic kernels:
o only code for the configured CPU is compiled
and linked (saves ~100k for R3000 kernels!)
o removed a lot of indirect function calls
o removed Ralf's "cowboy patch"
o added sanity check for DECstations (print warning
if the kernel is configured for the wrong CPU)
Diffstat (limited to 'arch/mips/mm/andes.c')
-rw-r--r-- | arch/mips/mm/andes.c | 36 |
1 files changed, 8 insertions, 28 deletions
diff --git a/arch/mips/mm/andes.c b/arch/mips/mm/andes.c index c0653eb64..4663ad657 100644 --- a/arch/mips/mm/andes.c +++ b/arch/mips/mm/andes.c @@ -1,4 +1,4 @@ -/* $Id: andes.c,v 1.5 1998/05/04 09:12:55 ralf Exp $ +/* $Id: andes.c,v 1.6 1999/01/04 16:03:52 ralf Exp $ * * andes.c: MMU and cache operations for the R10000 (ANDES). * @@ -14,8 +14,6 @@ #include <asm/sgialib.h> #include <asm/mmu_context.h> -extern unsigned long mips_tlb_entries; - /* Cache operations. XXX Write these dave... */ static inline void andes_flush_cache_all(void) { @@ -51,46 +49,41 @@ static void andes_flush_cache_sigtramp(unsigned long page) } /* TLB operations. XXX Write these dave... */ -static inline void andes_flush_tlb_all(void) +inline void flush_tlb_all(void) { /* XXX */ } -static void andes_flush_tlb_mm(struct mm_struct *mm) +void flush_tlb_mm(struct mm_struct *mm) { /* XXX */ } -static void andes_flush_tlb_range(struct mm_struct *mm, unsigned long start, +void flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) { /* XXX */ } -static void andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { /* XXX */ } -static void andes_load_pgd(unsigned long pg_dir) +void load_pgd(unsigned long pg_dir) { } -static void andes_pgd_init(unsigned long page) +void pgd_init(unsigned long page) { } -static void andes_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask) { /* XXX */ } -static int andes_user_mode(struct pt_regs *regs) -{ - return (regs->cp0_status & ST0_KSU) == KSU_USER; -} - __initfunc(void ld_mmu_andes(void)) { flush_cache_all = andes_flush_cache_all; @@ -100,19 +93,6 @@ __initfunc(void ld_mmu_andes(void)) flush_cache_sigtramp = andes_flush_cache_sigtramp; flush_page_to_ram = andes_flush_page_to_ram; - flush_tlb_all = andes_flush_tlb_all; - flush_tlb_mm = andes_flush_tlb_mm; - flush_tlb_range = andes_flush_tlb_range; - flush_tlb_page = andes_flush_tlb_page; - andes_asid_setup(); - - add_wired_entry = andes_add_wired_entry; - - user_mode = andes_user_mode; - - load_pgd = andes_load_pgd; - pgd_init = andes_pgd_init; - flush_cache_all(); flush_tlb_all(); } |