diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
| commit | 93f107ba6cceee2c35d207349976936da48393bc (patch) | |
| tree | c33ea3d9e7e92245d6593b694cb514c8db5ff05d /arch/mips/mm/loadmmu.c | |
| parent | f79c44e04169d10b07b53d4a524c8c41ea5504d5 (diff) | |
Add code to support the SB1 core, including mmu routines, processor
detection. This also tweaks cpu_probe() to use bits 15:8 of PRId as
a company ID, as per the mips32/mips64 specs, and use bits 7:0 as the
processor ID within the company. Patch from Justin with mods and some
additional bits by me.
Diffstat (limited to 'arch/mips/mm/loadmmu.c')
| -rw-r--r-- | arch/mips/mm/loadmmu.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/mm/loadmmu.c b/arch/mips/mm/loadmmu.c index 5bdcb38ab..69740ad78 100644 --- a/arch/mips/mm/loadmmu.c +++ b/arch/mips/mm/loadmmu.c @@ -45,6 +45,7 @@ extern void ld_mmu_r6000(void); extern void ld_mmu_rm7k(void); extern void ld_mmu_tfp(void); extern void ld_mmu_andes(void); +extern void ld_mmu_sb1(void); extern void ld_mmu_mips32(void); void __init loadmmu(void) @@ -85,14 +86,19 @@ void __init loadmmu(void) ld_mmu_r2300(); break; #endif - + #ifdef CONFIG_CPU_R10000 case CPU_R10000: printk("Loading R10000 MMU routines.\n"); ld_mmu_andes(); break; #endif - +#ifdef CONFIG_CPU_SB1 + case CPU_SB1: + printk("Loading SB1 MMU routines.\n"); + ld_mmu_sb1(); + break; +#endif default: panic("Yeee, unsupported mmu/cache architecture."); } |