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authorRalf Baechle <ralf@linux-mips.org>2000-11-25 04:49:46 +0000
committerRalf Baechle <ralf@linux-mips.org>2000-11-25 04:49:46 +0000
commit4c55adaa6d06e5533aebaceea7640ecf10952231 (patch)
tree0f2e4190d1e9db004e50c7f33a1fe46337fd1885 /arch/mips/mm/r4xx0.c
parent4c86076eb07eb647b1080355e18dc9d4c49bf7e1 (diff)
Kernel FPU emulator, chain saw edition.
Diffstat (limited to 'arch/mips/mm/r4xx0.c')
-rw-r--r--arch/mips/mm/r4xx0.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/mm/r4xx0.c b/arch/mips/mm/r4xx0.c
index 6f9718bea..b5bdafed4 100644
--- a/arch/mips/mm/r4xx0.c
+++ b/arch/mips/mm/r4xx0.c
@@ -19,12 +19,13 @@
#include <linux/sched.h>
#include <linux/mm.h>
+#include <asm/bootinfo.h>
+#include <asm/cpu.h>
#include <asm/bcache.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
-#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
/* CP0 hazard avoidance. */
@@ -2699,7 +2700,7 @@ void __init ld_mmu_r4xx0(void)
probe_dcache(config);
setup_scache(config);
- switch(mips_cputype) {
+ switch(mips_cpu.cputype) {
case CPU_R4600: /* QED style two way caches? */
case CPU_R4700:
case CPU_R5000: