Merge with Linux 2.1.131 and more MIPS goodies.

(Did I mention that CVS is buggy ...)

7 files changed, 193 insertions, 298 deletions

diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index 84622b55f..f3bb81704 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -1,3 +1,4 @@
+# $Id: Makefile,v 1.3 1998/10/28 12:38:16 ralf Exp $
 #
 # Makefile for the SNI specific part of the kernel
 #
@@ -5,8 +6,6 @@
 # removes any old dependencies. DON'T put your own dependencies here
 # unless it's something special (ie not a .c file).
 #
-# $Id: Makefile,v 1.2 1997/12/20 13:27:14 ralf Exp $
-#
 
 .S.s:
 	$(CPP) $(CFLAGS) $< -o $*.s
@@ -15,7 +14,7 @@
 
 all: sni.o
 O_TARGET := sni.o
-O_OBJS	 := hw-access.o int-handler.o io.o pci.o pcimt_scache.o reset.o setup.o
+O_OBJS	 := int-handler.o io.o pci.o pcimt_scache.o reset.o setup.o
 
 int-handler.o: int-handler.S
 
diff --git a/arch/mips/sni/hw-access.c b/arch/mips/sni/hw-access.c
deleted file mode 100644
index c2c121318..000000000
--- a/arch/mips/sni/hw-access.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $Id: hw-access.c,v 1.6 1998/06/30 00:21:59 ralf Exp $
- *
- * Low-level hardware access stuff for SNI RM200 PCI
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
- */
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/kbd_ll.h>
-#include <linux/kbdcntrlr.h>
-#include <linux/kernel.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <asm/bootinfo.h>
-#include <asm/cachectl.h>
-#include <asm/dma.h>
-#include <asm/keyboard.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mc146818rtc.h>
-#include <asm/pgtable.h>
-#include <asm/sni.h>
-
-#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
-
-static unsigned char sni_read_input(void)
-{
-	return inb(KBD_DATA_REG);
-}
-
-static void sni_write_output(unsigned char val)
-{
-	int status;
-
-	do {
-		status = inb(KBD_CNTL_REG);
-	} while (status & KBD_STAT_IBF);
-	outb(val, KBD_DATA_REG);
-}
-
-static void sni_write_command(unsigned char val)
-{
-	int status;
-
-	do {
-		status = inb(KBD_CNTL_REG);
-	} while (status & KBD_STAT_IBF);
-	outb(val, KBD_CNTL_REG);
-}
-
-static unsigned char sni_read_status(void)
-{
-	return inb(KBD_STATUS_REG);
-}
-
-__initfunc(void sni_rm200_keyboard_setup(void))
-{
-	kbd_read_input = sni_read_input;
-	kbd_write_output = sni_write_output;
-	kbd_write_command = sni_write_command;
-	kbd_read_status = sni_read_status;
-	request_irq(PCIMT_KEYBOARD_IRQ, keyboard_interrupt,
-	            0, "keyboard", NULL);
-	request_region(0x60, 16, "keyboard");
-}
diff --git a/arch/mips/sni/int-handler.S b/arch/mips/sni/int-handler.S
index 3c920954d..fbda9cb26 100644
--- a/arch/mips/sni/int-handler.S
+++ b/arch/mips/sni/int-handler.S
@@ -1,17 +1,22 @@
-/* $Id: int-handler.S,v 1.2 1997/12/01 17:57:40 ralf Exp $
+/* $Id: int-handler.S,v 1.3 1998/05/07 23:44:01 ralf Exp $
  *
  * SNI RM200 PCI specific interrupt handler code.
  *
  * Copyright (C) 1994 - 1997 by Ralf Baechle
  */
 #include <asm/asm.h>
-#include <linux/config.h>
 #include <asm/mipsconfig.h>
 #include <asm/mipsregs.h>
 #include <asm/regdef.h>
 #include <asm/sni.h>
 #include <asm/stackframe.h>
 
+/* The PCI ASIC has the nasty property that it may delay writes if it is busy.
+   As a consequence from writes that have not graduated when we exit from the
+   interrupt handler we might catch a spurious interrupt.  To avoid this we
+   force the PCI ASIC to graduate all writes by executing a read from the
+   PCI bus.  */
+
 		.set	noreorder
 		.set	noat
 		.align	5
@@ -20,34 +25,38 @@
 		CLI
 		.set	at
 
-		lb	t0,led_cache
-		addiu	t0,1
-		sb	t0,led_cache
-		sb	t0,PCIMT_CSLED
+		/* Blinken light ...  */
+		lb	t0, led_cache
+		addiu	t0, 1
+		sb	t0, led_cache
+		sb	t0, PCIMT_CSLED			# write only register
 		.data
 led_cache:	.byte	0
 		.text
 
-		mfc0	t0,CP0_STATUS
-		mfc0	t1,CP0_CAUSE
-		and	t0,t1
-
-		 andi	t1,t0,0x0800			# hardware interrupt 1
-		bnez	t1,hwint1
-		 andi	t1,t0,0x4000			# hardware interrupt 4
-		bnez	t1,eth_int
-
-		 andi	t1,t0,0x1000			# hardware interrupt 2
-		bnez	t1,hwint2
-		 andi	t1,t0,0x2000			# hardware interrupt 3
-		bnez	t1,hwint3
-		 andi	t1,t0,0x8000			# hardware interrupt 5
-		bnez	t1,hwint5
-		 andi	t1,t0,0x0400			# hardware interrupt 0
-		bnez	t1,hwint0
+		mfc0	t0, CP0_STATUS
+		mfc0	t1, CP0_CAUSE
+		and	t0, t1
+
+		/* The following interrupt dispatch tests for hwint 1 /
+		   EISA bridge first such that the timer interrupt get the
+		   highest priority.  */
+		 andi	t1, t0, 0x0800			# hardware interrupt 1
+		bnez	t1, hwint1
+		 andi	t1, t0, 0x4000			# hardware interrupt 4
+		bnez	t1, hwint4
+
+		 andi	t1, t0, 0x1000			# hardware interrupt 2
+		bnez	t1, hwint2
+		 andi	t1, t0, 0x2000			# hardware interrupt 3
+		bnez	t1, hwint3
+		 andi	t1, t0, 0x8000			# hardware interrupt 5
+		bnez	t1, hwint5
+		 andi	t1, t0, 0x0400			# hardware interrupt 0
+		bnez	t1, hwint0
 		 nop
 
-		j	spurious_interrupt		# Nothing up ...
+		j	return				# spurious interrupt
 		 nop
 
  ##############################################################################
@@ -57,146 +66,61 @@ swint1:		PANIC("swint1")
 
  /* ------------------------------------------------------------------------ */
 
-hwint1:		lbu	t0,PCIMT_CSITPEND
-
-		 andi	t1,t0,0x20
-		bnez	t1,eisa_int
-
-#ifdef CONFIG_SCSI_NCR53C8XX
-		 andi	t1,t0,0x40
-		beqz	t1,scsi_int
-#endif
-		 nop
-
-		j	spurious_interrupt
-		 nop
-
- /* ------------------------------------------------------------------------ */
-
-hwint0:		lbu	t0,PCIMT_CSITPEND
-
-		 andi	t1,t0,0x01
-		beqz	t1,int2
+/* hwint1 deals with EISA and SCSI interrupts.  */
+hwint1:		lbu	s0, PCIMT_CSITPEND
 
-go_spurious:	j	spurious_interrupt		# we got fooled
+		andi	t1, s0, 0x20
+		beqz	t1, 1f
+		 andi	s1, s0, 0x40
+		lbu	a0, PCIMT_INT_ACKNOWLEDGE	# IACK cycle
+		xori	t0, a0, 0xff
+		beqz	t0, 1f				# spurious interrupt?
 		 nop
+		jal	i8259_do_irq			# call real handler
+		 move	a1, sp
 
-eisa_int:	lui	s0,%hi(SNI_PORT_BASE)
-		li	a0,0x0f
-		sb	a0,%lo(SNI_PORT_BASE+0x20)(s0)	# poll command
-		lb	a0,%lo(SNI_PORT_BASE+0x20)(s0)	# read result
-		bgtz	a0,poll_second
-		 andi	a0,7
-		beq	a0,2,poll_second		# cascade?
-		 li	s1,1
-		/*
-		 * Acknowledge first pic
-		 */
-		lb	t2,%lo(SNI_PORT_BASE+0x21)(s0)
-		lui	s4,%hi(cache_21)
-		lb	t0,%lo(cache_21)(s4)
-		sllv	s1,s1,a0
-		or	t0,s1
-		sb	t0,%lo(cache_21)(s4)
-		sb	t0,%lo(SNI_PORT_BASE+0x21)(s0)
-		li	t2,0x20
-		sb	t2,%lo(SNI_PORT_BASE+0x20)(s0)
-		/*
-		 * Now call the real handler
-		 */
+1:		bnez	s1, 1f
+		 li	a0, PCIMT_IRQ_SCSI
 		jal	do_IRQ
-		 move	a1,sp
-		/*
-		 * Unblock first pic
-		 */
-		lbu	t1,%lo(SNI_PORT_BASE+0x21)(s0)
-		lb	t1,%lo(cache_21)(s4)
-		nor	s1,zero,s1
-		and	t1,s1
-		sb	t1,%lo(cache_21)(s4)
-		j	ret_from_irq
-		 sb	t1,%lo(SNI_PORT_BASE+0x21)(s0)
+		 move	a1, sp
 
-		/*
-		 * Cascade interrupt from second PIC
-		 */
-		.align	5
-poll_second:	li	a0,0x0f
-		sb	a0,%lo(SNI_PORT_BASE+0xa0)(s0)	# poll command
-		lb	a0,%lo(SNI_PORT_BASE+0xa0)(s0)	# read result
-		bgtz	a0,go_spurious
-		 andi	a0,7
-		/*
-		 * Acknowledge second pic
-		 */
-		lbu	t2,%lo(SNI_PORT_BASE+0xa1)(s0)
-		lui	s4,%hi(cache_A1)
-		lb	t3,%lo(cache_A1)(s4)
-		sllv	s1,s1,a0
-		or	t3,s1
-		sb	t3,%lo(cache_A1)(s4)
-		sb	t3,%lo(SNI_PORT_BASE+0xa1)(s0)
-		li	t3,0x20
-		sb	t3,%lo(SNI_PORT_BASE+0xa0)(s0)
-		sb	t3,%lo(SNI_PORT_BASE+0x20)(s0)
-		/*
-		 * Now call the real handler
-		 */
-		addiu	a0,8
-		jal	do_IRQ
-		 move	a1,sp
-		/*
-		 * Unblock second pic
-		 */
-		lb	t1,%lo(SNI_PORT_BASE+0xa1)(s0)
-		lb	t1,%lo(cache_A1)(s4)
-		subu	t0,1
-		nor	s1,zero,s1
-		and	t1,t1,s1
-		sb	t1,%lo(cache_A1)(s4)
+1:		lui	t0, %hi(PCIMT_CSITPEND)
 		j	ret_from_irq
-		 sb	t1,%lo(SNI_PORT_BASE+0xa1)(s0)
-
-/*
- * ... check if we were interrupted by the Lance ...
- */
-eth_int:	mfc0	s0,CP0_STATUS
-		ori	t0,s0,0x4000
-		xori	t0,0x4000
-		mtc0	t0,CP0_STATUS
+		 lbu	zero, %lo(PCIMT_CSITPEND)(t0)
 
-		li	a0,PCIMT_IRQ_ETHERNET
-		jal	do_IRQ
-		 move	a1,sp
+ /* ------------------------------------------------------------------------ */
 
-		mtc0	s0,CP0_STATUS
+/* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
+   button interrupts.  */
+hwint0:		PANIC("Received int0 but no handler yet ...\n")
+1:		j	1b
+		 nop
 
-		j	ret_from_irq
+go_spurious:	j	spurious_interrupt		# we got fooled
 		 nop
 
-#ifdef CONFIG_SCSI_NCR53C8XX
+/* hwint4 is used for only the onboard PCnet 32.  */
+hwint4:		mfc0	s0, CP0_STATUS
+		ori	t0, s0, 0x4000
+		xori	t0, 0x4000
+		mtc0	t0, CP0_STATUS
 
-/*
- * ... check if we were interrupted by the NCR ...
- */
-scsi_int:	li	a0,PCIMT_IRQ_SCSI
+		li	a0, PCIMT_IRQ_ETHERNET
 		jal	do_IRQ
-		 move	a1,sp
-		j	ret_from_irq
-		 nop
-
-#endif /* CONFIG_SCSI_NCR53C8XX */
+		 move	a1, sp
 
-pci_int:	PANIC("Received PCI interrupt but no handler yet ...\n")
-1:		j	1b
-		 nop
+		mtc0	s0, CP0_STATUS
 
-int2:		PANIC("Received int2 but no handler yet ...\n")
-1:		j	1b
+		j	ret_from_irq
 		 nop
 
+/* This interrupt was used for the com1 console on the first prototypes.  */
 hwint2:		PANIC("hwint2 and no handler yet")
+
+/* hwint3 should deal with the PCI A - D interrupts.  */
 hwint3:		PANIC("hwint3 and no handler yet")
+
+/* hwint5 is the r4k count / compare interrupt  */
 hwint5:		PANIC("hwint5 and no handler yet")
 
 		END(sni_rm200_pci_handle_int)
diff --git a/arch/mips/sni/io.c b/arch/mips/sni/io.c
index 8a97b80a8..a59df4565 100644
--- a/arch/mips/sni/io.c
+++ b/arch/mips/sni/io.c
@@ -1,11 +1,10 @@
-/*
+/* $Id: io.c,v 1.2 1998/04/05 11:24:06 ralf Exp $
+ *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Low level I/O functions for SNI.
- *
- * $Id: io.c,v 1.2 1998/03/27 08:53:50 ralf Exp $
  */
 #include <linux/string.h>
 #include <asm/mipsconfig.h>
@@ -14,46 +13,42 @@
 #include <asm/spinlock.h>
 #include <asm/sni.h>
 
-unsigned char sni_map_isa_cache;
-
-#define unused __attribute__((unused))
-
-/*
- * The PCIMT_CSMAPISA is shared by all processors; we need locking.
- *
- * XXX It's legal to use all the I/O memory access functions in interrupt
- * code, so we need to use the _irq locking stuff which may result in
- * significant IRQ latencies.
- */
-static spinlock_t csmapisa_lock unused = SPIN_LOCK_UNLOCKED;
-
 /*
  * Urgs...  We only can see a 16mb window of the 4gb EISA address space
  * at PCIMT_EISA_BASE.  Maladia segmentitis ...
  *
- * XXX Check out if accessing PCIMT_CSMAPISA really is slow.
- * For now assume so.
+ * To avoid locking and all the related headacke we implement this such
+ * that accessing the bus address space nests, so we're treating this
+ * correctly even for interrupts.  This is going to suck seriously for
+ * the SMP members of the RM family.
+ *
+ * Making things worse the PCIMT_CSMAPISA register resides on the X bus with
+ * it's unbeatable 1.4 mb/s transfer rate.
  */
-static inline void update_isa_cache(unsigned long address)
+
+static inline void eisa_map(unsigned long address)
 {
 	unsigned char upper;
 
 	upper = address >> 24;
-	if (sni_map_isa_cache != upper) {
-		sni_map_isa_cache = upper;
-		*(volatile unsigned char *)PCIMT_CSMAPISA = ~upper;
-	}
+	*(volatile unsigned char *)PCIMT_CSMAPISA = ~upper;
 }
 
+#define save_eisa_map()							\
+	(*(volatile unsigned char *)PCIMT_CSMAPISA)
+#define restore_eisa_map(val)						\
+	do { (*(volatile unsigned char *)PCIMT_CSMAPISA) = val; } while(0)
+
 static unsigned char sni_readb(unsigned long addr)
 {
 	unsigned char res;
+	unsigned int save_map;
 
-	spin_lock_irq(&csmapisa_lock);
-	update_isa_cache(addr);
+	save_map = save_eisa_map();
+	eisa_map(addr);
 	addr &= 0xffffff;
 	res = *(volatile unsigned char *) (PCIMT_EISA_BASE + addr);
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 
 	return res;
 }
@@ -61,12 +56,13 @@ static unsigned char sni_readb(unsigned long addr)
 static unsigned short sni_readw(unsigned long addr)
 {
 	unsigned short res;
+	unsigned int save_map;
 
-	spin_lock_irq(&csmapisa_lock);
-	update_isa_cache(addr);
+	save_map = save_eisa_map();
+	eisa_map(addr);
 	addr &= 0xffffff;
 	res = *(volatile unsigned char *) (PCIMT_EISA_BASE + addr);
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 
 	return res;
 }
@@ -74,101 +70,111 @@ static unsigned short sni_readw(unsigned long addr)
 static unsigned int sni_readl(unsigned long addr)
 {
 	unsigned int res;
+	unsigned int save_map;
 
-	spin_lock_irq(&csmapisa_lock);
-	update_isa_cache(addr);
+	save_map = save_eisa_map();
+	eisa_map(addr);
 	addr &= 0xffffff;
 	res = *(volatile unsigned char *) (PCIMT_EISA_BASE + addr);
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 
 	return res;
 }
 
 static void sni_writeb(unsigned char val, unsigned long addr)
 {
-	spin_lock_irq(&csmapisa_lock);
-	update_isa_cache(addr);
+	unsigned int save_map;
+
+	save_map = save_eisa_map();
+	eisa_map(addr);
 	addr &= 0xffffff;
 	*(volatile unsigned char *) (PCIMT_EISA_BASE + addr) = val;
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 }
 
 static void sni_writew(unsigned short val, unsigned long addr)
 {
-	spin_lock_irq(&csmapisa_lock);
-	update_isa_cache(addr);
+	unsigned int save_map;
+
+	save_map = save_eisa_map();
+	eisa_map(addr);
 	addr &= 0xffffff;
 	*(volatile unsigned char *) (PCIMT_EISA_BASE + addr) = val;
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 }
 
 static void sni_writel(unsigned int val, unsigned long addr)
 {
-	spin_lock_irq(&csmapisa_lock);
-	update_isa_cache(addr);
+	unsigned int save_map;
+
+	save_map = save_eisa_map();
+	eisa_map(addr);
 	addr &= 0xffffff;
 	*(volatile unsigned char *) (PCIMT_EISA_BASE + addr) = val;
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 }
 
 static void sni_memset_io(unsigned long addr, int val, unsigned long len)
 {
 	unsigned long waddr;
+	unsigned int save_map;
 
+	save_map = save_eisa_map();
 	waddr = PCIMT_EISA_BASE | (addr & 0xffffff);
-	spin_lock_irq(&csmapisa_lock);
 	while(len) {
 		unsigned long fraglen;
 
 		fraglen = (~addr + 1) & 0xffffff;
 		fraglen = (fraglen < len) ? fraglen : len;
-		update_isa_cache(addr);
+		eisa_map(addr);
 		memset((char *)waddr, val, fraglen);
 		addr += fraglen;
 		waddr = waddr + fraglen - 0x1000000;
 		len -= fraglen;
 	}
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 }
 
 static void sni_memcpy_fromio(unsigned long to, unsigned long from, unsigned long len)
 {
 	unsigned long waddr;
+	unsigned int save_map;
 
+	save_map = save_eisa_map();
 	waddr = PCIMT_EISA_BASE | (from & 0xffffff);
-	spin_lock_irq(&csmapisa_lock);
 	while(len) {
 		unsigned long fraglen;
 
 		fraglen = (~from + 1) & 0xffffff;
 		fraglen = (fraglen < len) ? fraglen : len;
-		update_isa_cache(from);
+		eisa_map(from);
 		memcpy((void *)to, (void *)waddr, fraglen);
 		to += fraglen;
 		from += fraglen;
 		waddr = waddr + fraglen - 0x1000000;
 		len -= fraglen;
 	}
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 }
 
 static void sni_memcpy_toio(unsigned long to, unsigned long from, unsigned long len)
 {
 	unsigned long waddr;
+	unsigned int save_map;
 
+	save_map = save_eisa_map();
 	waddr = PCIMT_EISA_BASE | (to & 0xffffff);
-	spin_lock_irq(&csmapisa_lock);
 	while(len) {
 		unsigned long fraglen;
 
 		fraglen = (~to + 1) & 0xffffff;
 		fraglen = (fraglen < len) ? fraglen : len;
-		update_isa_cache(to);
+		eisa_map(to);
 		memcpy((char *)to + PCIMT_EISA_BASE, (void *)from, fraglen);
 		to += fraglen;
 		from += fraglen;
 		waddr = waddr + fraglen - 0x1000000;
 		len -= fraglen;
 	}
-	spin_unlock_irq(&csmapisa_lock);
+	restore_eisa_map(save_map);
 }
diff --git a/arch/mips/sni/pci.c b/arch/mips/sni/pci.c
index fe538d277..0da6b8004 100644
--- a/arch/mips/sni/pci.c
+++ b/arch/mips/sni/pci.c
@@ -1,4 +1,4 @@
-/* $Id: pci.c,v 1.5 1998/05/07 02:57:22 ralf Exp $
+/* $Id: pci.c,v 1.6 1998/05/07 23:44:02 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -9,6 +9,7 @@
  * Copyright (C) 1997, 1998 Ralf Baechle
  */
 #include <linux/config.h>
+#include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>
@@ -28,13 +29,37 @@ do {                                                                         \
 
 static void sni_rm200_pcibios_fixup (void)
 {
-	/*
-	 * TODO: Fix PCI_INTERRUPT_LINE register for onboard cards.
-	 * Take care of RM300 revision D boards for where the network
-	 * slot became an ordinary PCI slot.
-	 */
-	pcibios_write_config_byte(0, PCI_DEVFN(1, 0), PCI_INTERRUPT_LINE,
-	                          PCIMT_IRQ_SCSI);
+	struct pci_dev *dev;
+
+	for (dev=pci_devices; dev; dev=dev->next) {
+		/*
+		 * TODO: Take care of RM300 revision D boards for where the
+		 * network slot became an ordinary PCI slot.
+		 */
+		if (dev->devfn == PCI_DEVFN(1, 0)) {
+			/* Evil hack ...  */
+			set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NO_WA);
+			dev->irq = PCIMT_IRQ_SCSI;
+			continue;
+		}
+		if (dev->devfn == PCI_DEVFN(2, 0)) {
+			dev->irq = PCIMT_IRQ_ETHERNET;
+			continue;
+		}
+
+		switch(dev->irq) {
+		case 1 ... 4:
+			dev->irq += PCIMT_IRQ_INTA - 1;
+			break;
+		case 0:
+			break;
+		default:
+			printk("PCI device on bus %d, dev %d, function %d "
+			       "impossible interrupt configured.\n",
+			       dev->bus->number, PCI_SLOT(dev->devfn),
+			       PCI_SLOT(dev->devfn));
+		}
+	}
 }
 
 /*
diff --git a/arch/mips/sni/pcimt_scache.c b/arch/mips/sni/pcimt_scache.c
index feec16967..55c96b939 100644
--- a/arch/mips/sni/pcimt_scache.c
+++ b/arch/mips/sni/pcimt_scache.c
@@ -1,35 +1,38 @@
-/*
+/* $Id: pcimt_scache.c,v 1.3 1998/08/25 09:14:51 ralf Exp $
+ *
  * arch/mips/sni/pcimt_scache.c
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1997 by Ralf Baechle
- *
- * $Id: pcimt_scache.c,v 1.2 1998/05/28 03:18:02 ralf Exp $
+ * Copyright (c) 1997, 1998 by Ralf Baechle
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <asm/bcache.h>
 #include <asm/sni.h>
 
+#define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF)
+#define invspace (*(volatile unsigned int *)PCIMT_INVSPACE)
+
 __initfunc(void sni_pcimt_sc_init(void))
 {
-	unsigned int cacheconf, sc_size;
+	unsigned int scsiz, sc_size;
 
-	cacheconf = *(volatile unsigned int *)PCIMT_CACHECONF;
-	if ((cacheconf & 7) == 0) {
-		printk("No second level cache detected\n");
-		printk("WARNING: not activating second level cache, "
-		       "tell ralf@gnu.org\n");
+	scsiz = cacheconf & 7;
+	if (scsiz == 0) {
+		printk("Second level cache is deactived.\n");
 		return;
 	}
-	if ((cacheconf & 7) >= 6) {
-		printk("Invalid second level cache size detected\n");
+	if (scsiz >= 6) {
+		printk("Invalid second level cache size configured, "
+		       "deactivating second level cache.\n");
+		cacheconf = 0;
 		return;
 	}
-	
-	sc_size = 128 << (cacheconf & 7);
-	printk("%dkb second level cache detected.\n", sc_size);
+
+	sc_size = 128 << scsiz;
+	printk("%dkb second level cache detected, deactivating.\n", sc_size);
+	cacheconf = 0;
 }
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 2f3499707..0652c171b 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -1,4 +1,4 @@
-/* $Id: setup.c,v 1.13 1998/08/17 13:57:45 ralf Exp $
+/* $Id: setup.c,v 1.9 1998/08/25 09:14:51 ralf Exp $
  *
  * Setup pointers to hardware-dependent routines.
  *
@@ -17,6 +17,11 @@
 #include <linux/interrupt.h>
 #include <linux/timex.h>
 #include <linux/pci.h>
+#include <linux/mc146818rtc.h>
+#include <linux/console.h>
+#include <linux/fb.h>
+#include <linux/pc_keyb.h>
+
 #include <asm/bcache.h>
 #include <asm/bootinfo.h>
 #include <asm/keyboard.h>
@@ -39,7 +44,6 @@ static void no_action(int cpl, void *dev_id, struct pt_regs *regs) { }
 static struct irqaction irq2  = { no_action, 0, 0, "cascade", NULL, NULL};
 
 extern asmlinkage void sni_rm200_pci_handle_int(void);
-extern void sni_rm200_keyboard_setup(void);
 
 extern void sni_machine_restart(char *command);
 extern void sni_machine_halt(void);
@@ -47,19 +51,20 @@ extern void sni_machine_power_off(void);
 
 extern struct ide_ops std_ide_ops;
 extern struct rtc_ops std_rtc_ops;
+extern struct kbd_ops std_kbd_ops;
 
 __initfunc(static void sni_irq_setup(void))
 {
 	set_except_vector(0, sni_rm200_pci_handle_int);
 	request_region(0x20,0x20, "pic1");
 	request_region(0xa0,0x20, "pic2");	
-	setup_x86_irq(2, &irq2);
+	i8259_setup_irq(2, &irq2);
 	/*
 	 * IRQ0 seems to be the irq for PC style stuff.
 	 * I don't know how to handle the debug button interrupt, so
 	 * don't use this button yet or bad things happen ...
 	 */
-	set_cp0_status(ST0_IM, IE_IRQ1 | IE_IRQ4);
+	set_cp0_status(ST0_IM, IE_IRQ1 | IE_IRQ3 | IE_IRQ4);
 }
 
 void (*board_time_init)(struct irqaction *irq);
@@ -70,7 +75,7 @@ __initfunc(static void sni_rm200_pci_time_init(struct irqaction *irq))
 	outb_p(0x34,0x43);		/* binary, mode 2, LSB/MSB, ch 0 */
 	outb_p(LATCH & 0xff , 0x40);	/* LSB */
 	outb(LATCH >> 8 , 0x40);	/* MSB */
-	setup_x86_irq(0, irq);
+	i8259_setup_irq(0, irq);
 }
 
 unsigned char aux_device_present;
@@ -132,7 +137,6 @@ __initfunc(void sni_rm200_pci_setup(void))
 
 	irq_setup = sni_irq_setup;
 	mips_io_port_base = SNI_PORT_BASE;
-	keyboard_setup = sni_rm200_keyboard_setup;
 
 	/*
 	 * Setup (E)ISA I/O memory access stuff
@@ -165,6 +169,10 @@ __initfunc(void sni_rm200_pci_setup(void))
 #ifdef CONFIG_BLK_DEV_IDE
 	ide_ops = &std_ide_ops;
 #endif
-
+	conswitchp = &vga_con;
 	rtc_ops = &std_rtc_ops;
+	kbd_ops = &std_kbd_ops;
+#ifdef CONFIG_PSMOUSE
+	aux_device_present = 0xaa;
+#endif
 }