diff options
| author | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-06-13 23:48:20 +0000 |
|---|---|---|
| committer | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-06-13 23:48:20 +0000 |
| commit | 6c9bc059cf73540f65fa2524c876ea96fc68edac (patch) | |
| tree | 14211a32f2e3bdcbd7be3949bc5ad9b493407a39 /arch/mips64/kernel/r4k_tlb_glue.S | |
| parent | 2b8295855d98d74c709e56f05949fd7cc9130fb8 (diff) | |
The tlb mod/load/store exception handlers _have_ to go to do_page_fault,
and can not do with pte bit twiddling without grabbing page_table_lock.
Reinstate most of the old code, after disposing of an extra jump.
Diffstat (limited to 'arch/mips64/kernel/r4k_tlb_glue.S')
| -rw-r--r-- | arch/mips64/kernel/r4k_tlb_glue.S | 27 |
1 files changed, 8 insertions, 19 deletions
diff --git a/arch/mips64/kernel/r4k_tlb_glue.S b/arch/mips64/kernel/r4k_tlb_glue.S index 857a92126..8713172df 100644 --- a/arch/mips64/kernel/r4k_tlb_glue.S +++ b/arch/mips64/kernel/r4k_tlb_glue.S @@ -13,16 +13,6 @@ #include <asm/regdef.h> #include <asm/stackframe.h> - __INIT -NESTED(__xtlb_refill_debug_tramp, PT_SIZE, sp) - j __xtlb_refill_debug - END(__xtlb_refill_debug_tramp) - -NESTED(__tlb_refill_debug_tramp, PT_SIZE, sp) - j __tlb_refill_debug - END(__tlb_refill_debug_tramp) - __FINIT - .macro __BUILD_cli CLI .endm @@ -31,7 +21,7 @@ NESTED(__tlb_refill_debug_tramp, PT_SIZE, sp) STI .endm - .macro tlb_handler name interruptible + .macro tlb_handler name interruptible writebit NESTED(__\name, PT_SIZE, sp) SAVE_ALL #if DEBUG_MIPS64 @@ -43,16 +33,15 @@ ld $7, PT_R7(sp) ld $2, PT_R2(sp) #endif __BUILD_\interruptible - dmfc0 t0, CP0_BADVADDR - sd t0, PT_BVADDR(sp) + dmfc0 a2, CP0_BADVADDR + li a1, \writebit + sd a2, PT_BVADDR(sp) move a0, sp - jal \name + jal do_page_fault j ret_from_sys_call END(__\name) .endm - tlb_handler tlb_refill_debug cli - tlb_handler xtlb_refill_debug cli - tlb_handler xtlb_mod_debug sti - tlb_handler xtlb_tlbl_debug sti - tlb_handler xtlb_tlbs_debug sti + tlb_handler xtlb_mod sti 1 + tlb_handler xtlb_tlbl sti 0 + tlb_handler xtlb_tlbs sti 1 |