scall_64.S: Move to kernel mode and enable intrs properly.

r4k_tlb_glue.S: The fast handlers must work with intrs disabled, since we
can not risk changes in entryhi/lo/tlbregisters. do_page_fault() _must_ work
with intrs enabled, to prevent deadlocks in the intercpu tlbflush code.
andes.c/r4xx0.c: Make tlb register accesses conservatively safe from intrs
coming in and changing register contents.

1 files changed, 7 insertions, 7 deletions

diff --git a/arch/mips64/mm/andes.c b/arch/mips64/mm/andes.c
index 91244d64c..aad9bbb23 100644
--- a/arch/mips64/mm/andes.c
+++ b/arch/mips64/mm/andes.c
@@ -250,11 +250,11 @@ static void andes_flush_tlb_mm(struct mm_struct *mm)
 #ifdef DEBUG_TLB
 		printk("[tlbmm<%d>]", mm->context);
 #endif
-		save_and_cli(flags);
+		__save_and_cli(flags);
 		get_new_mmu_context(mm);
 		if(mm == current->mm)
 			set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff);
-		restore_flags(flags);
+		__restore_flags(flags);
 	}
 }
 
@@ -270,7 +270,7 @@ andes_flush_tlb_range(struct mm_struct *mm, unsigned long start,
 		printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff),
 		       start, end);
 #endif
-		save_and_cli(flags);
+		__save_and_cli(flags);
 		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 		size = (size + 1) >> 1;
 		if(size <= NTLB_ENTRIES_HALF) {
@@ -305,7 +305,7 @@ andes_flush_tlb_range(struct mm_struct *mm, unsigned long start,
 				set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 
 									0xff);
 		}
-		restore_flags(flags);
+		__restore_flags(flags);
 	}
 }
 
@@ -321,7 +321,7 @@ andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 #endif
 		newpid = (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff);
 		page &= (PAGE_MASK << 1);
-		save_and_cli(flags);
+		__save_and_cli(flags);
 		oldpid = (get_entryhi() & 0xff);
 		set_entryhi(page | newpid);
 		BARRIER;
@@ -339,7 +339,7 @@ andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 	finish:
 		BARRIER;
 		set_entryhi(oldpid);
-		restore_flags(flags);
+		__restore_flags(flags);
 	}
 }
 
@@ -355,6 +355,7 @@ static void andes_update_mmu_cache(struct vm_area_struct * vma,
 	pte_t *ptep;
 	int idx, pid;
 
+	__save_and_cli(flags);
 	pid = get_entryhi() & 0xff;
 
 	if((pid != (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff)) ||
@@ -364,7 +365,6 @@ static void andes_update_mmu_cache(struct vm_area_struct * vma,
 			vma->vm_mm) & 0xff), pid);
 	}
 
-	__save_and_cli(flags);
 	address &= (PAGE_MASK << 1);
 	set_entryhi(address | (pid));
 	pgdp = pgd_offset(vma->vm_mm, address);