diff options
author | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-04-23 19:50:48 +0000 |
---|---|---|
committer | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-04-23 19:50:48 +0000 |
commit | 2bba74b71906107e5bce42b542b862f90cf048b3 (patch) | |
tree | 9d21eec33efcbabb5666ac9fc4daa6fcc396089f /arch/mips64/mm | |
parent | b9e55bb180a44f990e201c771c103469f6fb08ca (diff) |
scall_64.S: Move to kernel mode and enable intrs properly.
r4k_tlb_glue.S: The fast handlers must work with intrs disabled, since we
can not risk changes in entryhi/lo/tlbregisters. do_page_fault() _must_ work
with intrs enabled, to prevent deadlocks in the intercpu tlbflush code.
andes.c/r4xx0.c: Make tlb register accesses conservatively safe from intrs
coming in and changing register contents.
Diffstat (limited to 'arch/mips64/mm')
-rw-r--r-- | arch/mips64/mm/andes.c | 14 | ||||
-rw-r--r-- | arch/mips64/mm/r4xx0.c | 16 |
2 files changed, 15 insertions, 15 deletions
diff --git a/arch/mips64/mm/andes.c b/arch/mips64/mm/andes.c index 91244d64c..aad9bbb23 100644 --- a/arch/mips64/mm/andes.c +++ b/arch/mips64/mm/andes.c @@ -250,11 +250,11 @@ static void andes_flush_tlb_mm(struct mm_struct *mm) #ifdef DEBUG_TLB printk("[tlbmm<%d>]", mm->context); #endif - save_and_cli(flags); + __save_and_cli(flags); get_new_mmu_context(mm); if(mm == current->mm) set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff); - restore_flags(flags); + __restore_flags(flags); } } @@ -270,7 +270,7 @@ andes_flush_tlb_range(struct mm_struct *mm, unsigned long start, printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), start, end); #endif - save_and_cli(flags); + __save_and_cli(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; if(size <= NTLB_ENTRIES_HALF) { @@ -305,7 +305,7 @@ andes_flush_tlb_range(struct mm_struct *mm, unsigned long start, set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff); } - restore_flags(flags); + __restore_flags(flags); } } @@ -321,7 +321,7 @@ andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) #endif newpid = (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff); page &= (PAGE_MASK << 1); - save_and_cli(flags); + __save_and_cli(flags); oldpid = (get_entryhi() & 0xff); set_entryhi(page | newpid); BARRIER; @@ -339,7 +339,7 @@ andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: BARRIER; set_entryhi(oldpid); - restore_flags(flags); + __restore_flags(flags); } } @@ -355,6 +355,7 @@ static void andes_update_mmu_cache(struct vm_area_struct * vma, pte_t *ptep; int idx, pid; + __save_and_cli(flags); pid = get_entryhi() & 0xff; if((pid != (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff)) || @@ -364,7 +365,6 @@ static void andes_update_mmu_cache(struct vm_area_struct * vma, vma->vm_mm) & 0xff), pid); } - __save_and_cli(flags); address &= (PAGE_MASK << 1); set_entryhi(address | (pid)); pgdp = pgd_offset(vma->vm_mm, address); diff --git a/arch/mips64/mm/r4xx0.c b/arch/mips64/mm/r4xx0.c index 059774231..d2bd99982 100644 --- a/arch/mips64/mm/r4xx0.c +++ b/arch/mips64/mm/r4xx0.c @@ -2024,7 +2024,7 @@ static inline void r4k_flush_tlb_all(void) printk("[tlball]"); #endif - save_and_cli(flags); + __save_and_cli(flags); /* Save old context and create impossible VPN2 value */ old_ctx = (get_entryhi() & 0xff); set_entryhi(KSEG0); @@ -2044,7 +2044,7 @@ static inline void r4k_flush_tlb_all(void) } BARRIER; set_entryhi(old_ctx); - restore_flags(flags); + __restore_flags(flags); } static void r4k_flush_tlb_mm(struct mm_struct *mm) @@ -2055,11 +2055,11 @@ static void r4k_flush_tlb_mm(struct mm_struct *mm) #ifdef DEBUG_TLB printk("[tlbmm<%d>]", mm->context); #endif - save_and_cli(flags); + __save_and_cli(flags); get_new_mmu_context(mm); if(mm == current->mm) set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff); - restore_flags(flags); + __restore_flags(flags); } } @@ -2074,7 +2074,7 @@ static void r4k_flush_tlb_range(struct mm_struct *mm, unsigned long start, printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), start, end); #endif - save_and_cli(flags); + __save_and_cli(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; if(size <= NTLB_ENTRIES_HALF) { @@ -2124,7 +2124,7 @@ static void r4k_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) #endif newpid = (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff); page &= (PAGE_MASK << 1); - save_and_cli(flags); + __save_and_cli(flags); oldpid = (get_entryhi() & 0xff); set_entryhi(page | newpid); BARRIER; @@ -2142,7 +2142,7 @@ static void r4k_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: BARRIER; set_entryhi(oldpid); - restore_flags(flags); + __restore_flags(flags); } } @@ -2165,6 +2165,7 @@ static void r4k_update_mmu_cache(struct vm_area_struct * vma, pte_t *ptep; int idx, pid; + __save_and_cli(flags); pid = (get_entryhi() & 0xff); #ifdef DEBUG_TLB @@ -2176,7 +2177,6 @@ static void r4k_update_mmu_cache(struct vm_area_struct * vma, } #endif - __save_and_cli(flags); address &= (PAGE_MASK << 1); set_entryhi(address | (pid)); pgdp = pgd_offset(vma->vm_mm, address); |