Merge with Linux 2.1.55. More bugfixes and goodies from my private

CVS archive.

1 files changed, 117 insertions, 108 deletions

diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index 4daf30e21..e10480454 100644
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -1,4 +1,4 @@
-/* $Id: etrap.S,v 1.30 1997/06/30 10:31:37 jj Exp $
+/* $Id: etrap.S,v 1.37 1997/08/21 09:13:18 davem Exp $
  * etrap.S: Preparing for entry into the kernel on Sparc V9.
  *
  * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -15,118 +15,127 @@
 #define		FPUREG_SZ		((64 * 4) + (2 * 8))
 #define		TASK_REGOFF		((((PAGE_SIZE<<1)-FPUREG_SZ)&~(64-1)) - \
 					 TRACEREG_SZ-REGWIN_SZ)
+#define		FPU_OFF			(STACK_BIAS + REGWIN_SZ + TRACEREG_SZ)
+
+/*
+ * On entry, %g7 is return address - 0x4.
+ * %g4 and %g5 will be preserved %l4 and %l5 respectively.
+ */
 
 		.text
 		.align			32
+etrap_priv:	or			%g1, %g3, %g1						! IEU0		Group
+		rd			%fprs, %g3						! Single	Group+4bubbles
+		sub			%sp, REGWIN_SZ + TRACEREG_SZ - STACK_BIAS, %g2		! IEU0		Group
+		andcc			%g3, FPRS_FEF, %g0					! IEU1
+		add			%g2, REGWIN_SZ + TRACEREG_SZ - FPUREG_SZ, %g3		! IEU0		Group
+		be,pt			%icc, 1f						! CTI
+		 andcc			%g1, TSTATE_PRIV, %g0					! IEU1
+		andn			%g3, (64 - 1), %g3					! IEU0		Group
+		ba,pt			%xcc, 1f						! CTI
+		 sub			%g3, REGWIN_SZ + TRACEREG_SZ, %g2			! IEU0		Group
+		
+		.align			32
 		.globl			etrap, etrap_irq, etraptl1
 
-etrap:		rdpr			%pil, %g2
-etrap_irq:	rdpr			%tstate, %g1
-		sllx			%g2, 20, %g2
-		or			%g1, %g2, %g1
-		andcc			%g1, TSTATE_PRIV, %g0
-		bne,pn			%xcc, etrap_maybe_fpu
-		 sub			%sp, REGWIN_SZ + TRACEREG_SZ - STACK_BIAS, %g2
-		sethi			%hi(TASK_REGOFF), %g2
-
-		or			%g2, %lo(TASK_REGOFF), %g2
-		add			%g6, %g2, %g2
-etrap_maybe_fpu:rd			%fprs, %g3
-		brnz,pn			%g3, etrap_save_fpu
-		 st			%g0, [%g2 + REGWIN_SZ + PT_V9_FPRS]
-etrap_after_fpu:rdpr			%tpc, %g3
-		stx			%g1, [%g2 + REGWIN_SZ + PT_V9_TSTATE]
-		rdpr			%tnpc, %g1
-
-		stx			%g3, [%g2 + REGWIN_SZ + PT_V9_TPC]
-		rd			%y, %g3
-		stx			%g1, [%g2 + REGWIN_SZ + PT_V9_TNPC]
-		st			%g3, [%g2 + REGWIN_SZ + PT_V9_Y]
-		save			%g2, -STACK_BIAS, %sp	! The ordering here is
-		rdpr			%pstate, %g1		! critical, see winfixup
-		bne,pn			%xcc, 2f
-		 rdpr			%canrestore, %g3
-
-		rdpr			%wstate, %g2
-		wrpr			%g0, 7, %cleanwin
-		wrpr			%g0, 0, %canrestore
-		sll			%g2, 3, %g2
-		wrpr			%g3, 0, %otherwin
-		wrpr			%g2, 0, %wstate
-		wr			%g0, ASI_DMMU, %asi
-		ldxa			[%g0 + PRIMARY_CONTEXT] %asi, %g2
-
-		stxa			%g0, [%g0 + PRIMARY_CONTEXT] %asi
-		stxa			%g2, [%g0 + SECONDARY_CONTEXT] %asi
-		flush			%g6
-2:		wrpr			%g0, 0x0, %tl
-		or			%g1, 0, %l1
-		add			%g4, 0, %l4
-		or			%g5, 0, %l5
-		add			%g7, 0, %l2
-
-		or			%g6, 0, %l6
-		wrpr			%l1, (PSTATE_AG|PSTATE_RMO), %pstate
-		stx			%g1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G1]
-		stx			%g2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G2]
-		stx			%g3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G3]
-		stx			%g4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G4]
-		stx			%g5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G5]
-		stx			%g6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G6]
-
-		stx			%g7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G7]
-		stx			%i0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I0]
-		stx			%i1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I1]
-		stx			%i2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I2]
-		stx			%i3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I3]
-		stx			%i4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I4]
-		sethi			%uhi(PAGE_OFFSET), %g4
-		stx			%i5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I5]
-
-		stx			%i6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I6]
-		sllx			%g4, 32, %g4
-		stx			%i7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I7]
-		wrpr			%l1, (PSTATE_IE|PSTATE_AG|PSTATE_RMO), %pstate
-		jmpl			%l2 + 0x4, %g0
-		 mov			%l6, %g6
-etrap_save_fpu:	and			%g3, FPRS_FEF, %g3
-		brz,pn			%g3, 2f
-
-		 nop
-		be,a,pt			%xcc, 3f
-		 add			%g2, (TRACEREG_SZ + REGWIN_SZ), %g2
-		wr			%g0, ASI_BLK_P, %asi
-		add			%g2, ((TRACEREG_SZ+REGWIN_SZ)-FPUREG_SZ), %g2
-		andn			%g2, (64 - 1), %g2
-1:		st			%g3, [%g2 - 0x4 /*REGWIN_SZ + PT_V9_FPRS*/]
-		rd			%gsr, %g3
-
-		stx			%fsr, [%g2 + 0x100]
-		stx			%g3,  [%g2 + 0x108]
-		membar			#StoreStore | #LoadStore
-		stda			%f0,  [%g2 + 0x000] %asi
-		stda			%f16, [%g2 + 0x040] %asi
-		stda			%f32, [%g2 + 0x080] %asi
-		stda			%f48, [%g2 + 0x0c0] %asi
-		membar			#Sync
-
-		sub			%g2, (TRACEREG_SZ + REGWIN_SZ), %g2
-2:		b,pt			%xcc, etrap_after_fpu
-		 wr			%g0, 0, %fprs
-3:		/* Because Ultra lacks ASI_BLK_NUCLEUS a hack has to take place. */
-		mov			SECONDARY_CONTEXT, %g3
-		stxa			%g0, [%g3] ASI_DMMU
-		flush			%g2
-		wr			%g0, ASI_BLK_S, %asi
-		nop
+etrap:		rdpr			%pil, %g2						! Single 	Group
+etrap_irq:	rdpr			%tstate, %g1						! Single 	Group
+		sllx			%g2, 20, %g3						! IEU0		Group
+		andcc			%g1, TSTATE_PRIV, %g0					! IEU1
+		bne,pn			%xcc, etrap_priv					! CTI
+		 sethi			%hi(TASK_REGOFF), %g2					! IEU0		Group
+		or			%g1, %g3, %g1						! IEU1
+		or			%g2, %lo(TASK_REGOFF), %g2				! IEU0		Group
+		add			%g6, %g2, %g2						! IEU0		Group
+1:		rdpr			%tpc, %g3						! Single	Group
+		stx			%g1, [%g2 + REGWIN_SZ + PT_V9_TSTATE]			! Store		Group
+		rdpr			%tnpc, %g1						! Single	Group
+		stx			%g3, [%g2 + REGWIN_SZ + PT_V9_TPC]			! Store		Group
+		rd			%y, %g3							! Single	Group+4bubbles
+		stx			%g1, [%g2 + REGWIN_SZ + PT_V9_TNPC]			! Store		Group
+		st			%g3, [%g2 + REGWIN_SZ + PT_V9_Y]			! Store		Group
+		save			%g2, -STACK_BIAS, %sp	! The ordering here is		! Single	Group
+		rdpr			%pstate, %g1		! critical, see winfixup	! Single	Group+9bubbles
+		bne,pn			%xcc, 2f						! CTI		Group
+		 sethi			%hi(TSTATE_PEF), %l2					! IEU0
+		mov			PRIMARY_CONTEXT, %l4					! IEU1
+		rdpr			%canrestore, %g3					! Single	Group+4bubbles
+		rdpr			%wstate, %g2						! Single	Group+4bubbles
+		wrpr			%g0, 7, %cleanwin					! Single	Group+4bubbles
+		wrpr			%g0, 0, %canrestore					! Single	Group+4bubbles
+		sll			%g2, 3, %g2						! IEU0		Group
+		mov			SECONDARY_CONTEXT, %l5					! IEU1
+		wrpr			%g3, 0, %otherwin					! Single	Group+4bubbles
+		wrpr			%g2, 0, %wstate						! Single	Group+4bubbles
+		rdpr			%tstate, %l3						! Single	Group
+		ldxa			[%l4] ASI_DMMU, %g2					! Load		Group
+		stxa			%g0, [%l4] ASI_DMMU					! Store		Group
+		stxa			%g2, [%l5] ASI_DMMU					! Store		Group
+		flush			%g6							! Single	Group+9bubbles
+		andcc			%l3, %l2, %g0						! IEU1		Group
+		be,a,pt			%icc, 6f						! CTI
+		 st			%g0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_FPRS]	! Store
+		rd			%fprs, %l0						! Single	Group+4bubbles
+		andcc			%l0, FPRS_FEF, %g0					! IEU1		Group
+		be,pn			%icc, 6f						! CTI
+		 st			%l0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_FPRS]	! Store
+		ld			[%g6 + AOFF_task_tss + AOFF_thread_flags], %l4		! Load		Group
+		stx			%fsr, [%sp + FPU_OFF + 0x100] 				! Single	Group
+		or			%l4, %l0, %l4						! IEU0		Group
+		ba,pt			%xcc, 3f						! CTI
+		 st			%l4, [%g6 + AOFF_task_tss + AOFF_thread_flags]		! Store
+2:		rd			%fprs, %l0						! Single	Group+4bubbles
+		andcc			%l0, FPRS_FEF, %g0					! IEU1		Group
+		be,pn			%icc, 6f						! CTI
+		 st			%l0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_FPRS]	! Store
+		stx			%fsr, [%sp + FPU_OFF + 0x100] 				! Single	Group
+3:		rd			%gsr, %l7						! Single	Group+4bubbles
+		cmp			%l0, FPRS_FEF						! IEU1		Group
+		be,pn			%icc, 6f						! CTI
+		 stx			%l7, [%sp + FPU_OFF + 0x108]				! Store		
+		wr			%g0, ASI_BLK_P, %asi					! Singe		Group+4bubbles
+		andcc			%l0, FPRS_DL, %g0					! IEU1		Group
+		be,pn			%icc, 4f						! CTI
+		 membar			#StoreStore | #LoadStore				! Memory	
+		stda			%f0, [%sp + FPU_OFF + 0x000] %asi			! Store		Group
+		stda			%f16, [%sp + FPU_OFF + 0x040] %asi			! Store		Group
+		andcc			%l0, FPRS_DU, %g0					! IEU1
+		be,pn			%icc, 5f						! CTI
+		 nop										! IEU0		Group
+4:		stda			%f32, [%sp + FPU_OFF + 0x080] %asi			! Store		Group
+		stda			%f48, [%sp + FPU_OFF + 0x0c0] %asi			! Store		Group
+5:		membar			#Sync							! Memory	
+6:		wr			%g0, 0x0, %fprs						! Single	Group+4bubbles
+		wrpr			%g0, 0x0, %tl						! Single	Group+4bubbles
+		mov			%g1, %l1						! IEU0		Group
+		mov			%g4, %l4						! IEU1
+		mov			%g5, %l5						! IEU0		Group
+		mov			%g7, %l2						! IEU1
+		mov			%g6, %l6						! IEU0		Group
+		wrpr			%l1, (PSTATE_AG|PSTATE_RMO), %pstate			! Single	Group+4bubbles
+		stx			%g1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G1]		! Store		Group
+		stx			%g2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G2]		! Store		Group
+		stx			%g3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G3]		! Store		Group
+		stx			%g4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G4]		! Store		Group
+		stx			%g5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G5]		! Store		Group
+		stx			%g6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G6]		! Store		Group
+		stx			%g7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G7]		! Store		Group
+		stx			%i0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I0]		! Store		Group
+		stx			%i1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I1]		! Store		Group
+		stx			%i2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I2]		! Store		Group
+		stx			%i3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I3]		! Store		Group
+		stx			%i4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I4]		! Store		Group
+		sethi			%uhi(PAGE_OFFSET), %g4					! IEU0
+		stx			%i5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I5]		! Store		Group
+		stx			%i6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I6]		! Store		Group
+		sllx			%g4, 32, %g4						! IEU0
+		stx			%i7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I7]		! Store		Group
+		wrpr			%l1, (PSTATE_IE|PSTATE_AG|PSTATE_RMO), %pstate		! Single	Group+4bubbles
+		jmpl			%l2 + 0x4, %g0						! CTI		Group
+		 mov			%l6, %g6						! IEU0
 
-		b,pt			%xcc, 1b
-		 mov			FPRS_FEF, %g3
-		nop
-etraptl1:	rdpr			%tstate, %g1
-		sub			%sp, REGWIN_SZ + TRACEREG_SZ - STACK_BIAS, %g2
-		ba,pt			%xcc, etrap_maybe_fpu
-		 andcc			%g1, TSTATE_PRIV, %g0
-		nop
+etraptl1:	rdpr			%tstate, %g1						! Single	Group+4bubbles
+		ba,pt			%xcc, etrap_priv					! CTI		Group
+		 clr			%g3							! IEU0
 #undef TASK_REGOFF
 #undef FPUREG_SZ