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authorKanoj Sarcar <kanoj@engr.sgi.com>2000-03-13 22:43:25 +0000
committerKanoj Sarcar <kanoj@engr.sgi.com>2000-03-13 22:43:25 +0000
commitbfafcf238b52595f9c6f202049e0a6cfe8f50419 (patch)
treeb477f57e6f86505797478370d253460e851f73c2 /arch
parent974d7a857bcfb0ad828852f14f20ec56fc91a2bb (diff)
TLB pid allocation fix. Still not sure about the complete algorithm.
Turn on TLB pid checks.
Diffstat (limited to 'arch')
-rw-r--r--arch/mips64/mm/andes.c4
-rw-r--r--arch/mips64/mm/fault.c4
2 files changed, 3 insertions, 5 deletions
diff --git a/arch/mips64/mm/andes.c b/arch/mips64/mm/andes.c
index 401e07472..3c76b0402 100644
--- a/arch/mips64/mm/andes.c
+++ b/arch/mips64/mm/andes.c
@@ -1,4 +1,4 @@
-/* $Id: andes.c,v 1.5 2000/01/27 01:05:24 ralf Exp $
+/* $Id: andes.c,v 1.6 2000/02/24 00:12:41 ralf Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@@ -356,13 +356,11 @@ static void andes_update_mmu_cache(struct vm_area_struct * vma,
pid = get_entryhi() & 0xff;
-#ifdef DEBUG_TLB
if((pid != (vma->vm_mm->context & 0xff)) ||
(vma->vm_mm->context == 0)) {
printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n",
(int) (vma->vm_mm->context & 0xff), pid);
}
-#endif
__save_and_cli(flags);
address &= (PAGE_MASK << 1);
diff --git a/arch/mips64/mm/fault.c b/arch/mips64/mm/fault.c
index b7a9e2b8f..761f68a65 100644
--- a/arch/mips64/mm/fault.c
+++ b/arch/mips64/mm/fault.c
@@ -1,4 +1,4 @@
-/* $Id: fault.c,v 1.5 2000/02/04 07:40:24 ralf Exp $
+/* $Id: fault.c,v 1.6 2000/02/18 00:24:31 ralf Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@@ -32,7 +32,7 @@
extern void die(char *, struct pt_regs *, unsigned long write);
-unsigned long asid_cache;
+unsigned long asid_cache = ASID_FIRST_VERSION;
/*
* Macro for exception fixup code to access integer registers.