summaryrefslogtreecommitdiffstats
path: root/drivers/char/agp
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2001-01-10 17:17:53 +0000
committerRalf Baechle <ralf@linux-mips.org>2001-01-10 17:17:53 +0000
commitb2ad5f821b1381492d792ca10b1eb7a107b48f14 (patch)
tree954a648692e7da983db1d2470953705f6a729264 /drivers/char/agp
parentc9c06167e7933d93a6e396174c68abf242294abb (diff)
Merge with Linux 2.4.0-prerelease. Big Makefile rewrite, test your
Makefiles.
Diffstat (limited to 'drivers/char/agp')
-rw-r--r--drivers/char/agp/Makefile20
-rw-r--r--drivers/char/agp/agp.h7
-rw-r--r--drivers/char/agp/agpgart_be.c71
3 files changed, 84 insertions, 14 deletions
diff --git a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile
index d20869b0e..3e726b314 100644
--- a/drivers/char/agp/Makefile
+++ b/drivers/char/agp/Makefile
@@ -5,18 +5,14 @@
O_TARGET := agp.o
-ifeq ($(CONFIG_AGP),y)
- O_OBJS += agpgart_fe.o
- OX_OBJS += agpgart_be.o
-else
- ifeq ($(CONFIG_AGP), m)
- MI_OBJS += agpgart_fe.o
- MIX_OBJS += agpgart_be.o
- M_OBJS += agpgart.o
- endif
-endif
+export-objs := agpgart_be.o
+
+multi-objs := agpgart.o
+agpgart-objs := agpgart_fe.o agpgart_be.o
+
+obj-$(CONFIG_AGP) += agpgart.o
include $(TOPDIR)/Rules.make
-agpgart.o: agpgart_be.o agpgart_fe.o
- $(LD) $(LD_RFLAG) -r -o $@ agpgart_be.o agpgart_fe.o
+agpgart.o: $(agpgart-objs)
+ $(LD) $(LD_RFLAG) -r -o $@ $(agpgart-objs)
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index a054af745..33743376a 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -164,6 +164,9 @@ struct agp_bridge_data {
#ifndef PCI_DEVICE_ID_INTEL_840_0
#define PCI_DEVICE_ID_INTEL_840_0 0x1a21
#endif
+#ifndef PCI_DEVICE_ID_INTEL_850_0
+#define PCI_DEVICE_ID_INTEL_850_0 0x2530
+#endif
#ifndef PCI_DEVICE_ID_INTEL_810_DC100_0
#define PCI_DEVICE_ID_INTEL_810_DC100_0 0x7122
#endif
@@ -213,6 +216,10 @@ struct agp_bridge_data {
#define INTEL_I840_MCHCFG 0x50
#define INTEL_I840_ERRSTS 0xc8
+/* intel i850 registers */
+#define INTEL_I850_MCHCFG 0x50
+#define INTEL_I850_ERRSTS 0xc8
+
/* intel i810 registers */
#define I810_GMADDR 0x10
#define I810_MMADDR 0x14
diff --git a/drivers/char/agp/agpgart_be.c b/drivers/char/agp/agpgart_be.c
index 5d2b3de61..942142832 100644
--- a/drivers/char/agp/agpgart_be.c
+++ b/drivers/char/agp/agpgart_be.c
@@ -415,8 +415,9 @@ int agp_unbind_memory(agp_memory * curr)
/*
* Driver routines - start
* Currently this module supports the following chipsets:
- * i810, 440lx, 440bx, 440gx, via vp3, via mvp3, via kx133, via kt133,
- * amd irongate, ALi M1541, and generic support for the SiS chipsets.
+ * i810, 440lx, 440bx, 440gx, i840, i850, via vp3, via mvp3, via kx133,
+ * via kt133, amd irongate, ALi M1541, and generic support for the SiS
+ * chipsets.
*/
/* Generic Agp routines - Start */
@@ -1191,6 +1192,38 @@ static int intel_840_configure(void)
return 0;
}
+static int intel_850_configure(void)
+{
+ u32 temp;
+ u16 temp2;
+ aper_size_info_16 *current_size;
+
+ current_size = A_SIZE_16(agp_bridge.current_size);
+
+ /* aperture size */
+ pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
+ (char)current_size->size_value);
+
+ /* address to map to */
+ pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
+ agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+
+ /* attbase - aperture base */
+ pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE,
+ agp_bridge.gatt_bus_addr);
+
+ /* agpctrl */
+ pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+
+ /* mcgcfg */
+ pci_read_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge.dev, INTEL_I850_MCHCFG,
+ temp2 | (1 << 9));
+ /* clear any possible AGP-related error conditions */
+ pci_write_config_word(agp_bridge.dev, INTEL_I850_ERRSTS, 0x001c);
+ return 0;
+}
+
static unsigned long intel_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
@@ -1272,6 +1305,34 @@ static int __init intel_840_setup (struct pci_dev *pdev)
(void) pdev; /* unused */
}
+static int __init intel_850_setup (struct pci_dev *pdev)
+{
+ agp_bridge.masks = intel_generic_masks;
+ agp_bridge.num_of_masks = 1;
+ agp_bridge.aperture_sizes = (void *) intel_generic_sizes;
+ agp_bridge.size_type = U16_APER_SIZE;
+ agp_bridge.num_aperture_sizes = 7;
+ agp_bridge.dev_private_data = NULL;
+ agp_bridge.needs_scratch_page = FALSE;
+ agp_bridge.configure = intel_850_configure;
+ agp_bridge.fetch_size = intel_fetch_size;
+ agp_bridge.cleanup = intel_cleanup;
+ agp_bridge.tlb_flush = intel_tlbflush;
+ agp_bridge.mask_memory = intel_mask_memory;
+ agp_bridge.agp_enable = agp_generic_agp_enable;
+ agp_bridge.cache_flush = global_cache_flush;
+ agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge.insert_memory = agp_generic_insert_memory;
+ agp_bridge.remove_memory = agp_generic_remove_memory;
+ agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge.free_by_type = agp_generic_free_by_type;
+
+ return 0;
+
+ (void) pdev; /* unused */
+}
+
#endif /* CONFIG_AGP_INTEL */
#ifdef CONFIG_AGP_VIA
@@ -2070,6 +2131,12 @@ static struct {
"Intel",
"i840",
intel_840_setup },
+ { PCI_DEVICE_ID_INTEL_850_0,
+ PCI_VENDOR_ID_INTEL,
+ INTEL_I850,
+ "Intel",
+ "i850",
+ intel_850_setup },
{ 0,
PCI_VENDOR_ID_INTEL,
INTEL_GENERIC,