Import of Linux/MIPS 2.1.36

1 files changed, 106 insertions, 31 deletions

diff --git a/drivers/scsi/esp.h b/drivers/scsi/esp.h
index 91171bba9..23a7e35e3 100644
--- a/drivers/scsi/esp.h
+++ b/drivers/scsi/esp.h
@@ -49,6 +49,7 @@ struct Sparc_ESP_regs {
     volatile unchar esp_cfg1;   /* rw  First configuration register   0x20   */
                                 unchar cfpad[3];
     volatile unchar esp_cfact;  /* wo  Clock conversion factor        0x24   */
+#define esp_status2 esp_cfact   /* ro  HME status2 register           0x24   */
                                 unchar ctpad[3];
     volatile unchar esp_ctest;  /* wo  Chip test register             0x28   */
                                 unchar cf2pd[3];
@@ -62,24 +63,27 @@ struct Sparc_ESP_regs {
     /* The following is found on all chips except the NCR53C90 (ESP100) */
     volatile unchar esp_tchi;   /* rw  High bits of transfer count    0x38  */
 #define esp_uid     esp_tchi    /* ro  Unique ID code                 0x38  */
+#define fas_rlo     esp_tchi    /* rw  HME extended counter           0x38  */
                                 unchar fgpad[3];
     volatile unchar esp_fgrnd;  /* rw  Data base for fifo             0x3c  */
+#define fas_rhi     esp_fgrnd   /* rw  HME extended counter           0x3c  */
 };
 
 /* Various revisions of the ESP board. */
 enum esp_rev {
-  esp100     = 0x00,  /* NCR53C90  */
+  esp100     = 0x00,  /* NCR53C90 - very broken */
   esp100a    = 0x01,  /* NCR53C90A */
   esp236     = 0x02,
   fas236     = 0x03,
   fas100a    = 0x04,
   fast       = 0x05,
-  espunknown = 0x06
+  fashme     = 0x06,
+  espunknown = 0x07
 };
 
 /* We get one of these for each ESP probed. */
 struct Sparc_ESP {
-  struct Sparc_ESP *next;           /* Next ESP on probed or NULL */
+  struct Sparc_ESP *next;                 /* Next ESP on probed or NULL */
   struct Sparc_ESP_regs *eregs;           /* All esp registers */
   struct Linux_SBus_DMA *dma;             /* Who I do transfers with. */
   struct sparc_dma_registers *dregs;      /* And his registers. */
@@ -88,23 +92,28 @@ struct Sparc_ESP {
   struct linux_sbus_device *edev;         /* Pointer to SBus entry */
   char prom_name[64];                     /* Name of ESP device from prom */
   int prom_node;                          /* Prom node where ESP found */
-  int esp_id;                             /* Same as esphost->host_id */
+  int esp_id;                             /* Unique per-ESP ID number */
 
   /* ESP Configuration Registers */
   unsigned char config1;                  /* Copy of the 1st config register */
   unsigned char config2;                  /* Copy of the 2nd config register */
-  unsigned char config3[8];               /* Copy of the 3rd config register */
+  unsigned char config3[16];              /* Copy of the 3rd config register */
 
   /* The current command we are sending to the ESP chip.  This esp_command
    * ptr needs to be mapped in DVMA area so we can send commands and read
    * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
-   * sucks when we have the DVMA to do it for us.
+   * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
+   * only send out 6, 10, and 12 byte SCSI commands, others we need to send
+   * one byte at a time.  esp_slowcmd being set says that we are doing one
+   * of the command types ESP doesn't understand, esp_scmdp keeps track of
+   * which byte we are sending, esp_scmdleft says how many bytes to go.
    */
-  volatile unchar *esp_command;           /* Location of command */
-  int esp_clen;                           /* Length of this command */
-
-  /* To hold onto the dvma buffer ptr. */
-  char *dvma_hold;
+  volatile unchar *esp_command;           /* Location of command (CPU view)  */
+  __u32            esp_command_dvma;      /* Location of command (DVMA view) */
+  unsigned char esp_clen;                 /* Length of this command */
+  unsigned char esp_slowcmd;
+  unsigned char *esp_scmdp;
+  unsigned char esp_scmdleft;
 
   /* The following are used to determine the cause of an IRQ. Upon every
    * IRQ entry we synchronize these with the hardware registers.
@@ -112,20 +121,45 @@ struct Sparc_ESP {
   unchar ireg;                            /* Copy of ESP interrupt register */
   unchar sreg;                            /* Same for ESP status register */
   unchar seqreg;                          /* The ESP sequence register */
+  unchar sreg2;                           /* Copy of HME status2 register */
+
+  /* The HME is the biggest piece of shit I have ever seen. */
+  unchar hme_fifo_workaround_buffer[16 * 2]; /* 16-bit/entry fifo for wide scsi */
+  unchar hme_fifo_workaround_count;
 
   /* Clock periods, frequencies, synchronization, etc. */
   unsigned int cfreq;                    /* Clock frequency in HZ */
   unsigned int cfact;                    /* Clock conversion factor */
   unsigned int ccycle;                   /* One ESP clock cycle */
   unsigned int ctick;                    /* One ESP clock time */
-  unsigned int sync_defp;                /* Default negotiation period */
+  unsigned int radelay;                  /* FAST chip req/ack delay */
+  unsigned int neg_defp;                 /* Default negotiation period */
+  unsigned int sync_defp;                /* Default sync transfer period */
+  unsigned int max_period;               /* longest our period can be */
+  unsigned int min_period;               /* shortest period we can withstand */
+  /* For slow to medium speed input clock rates we shoot for 5mb/s,
+   * but for high input clock rates we try to do 10mb/s although I
+   * don't think a transfer can even run that fast with an ESP even
+   * with DMA2 scatter gather pipelining.
+   */
+#define SYNC_DEFP_SLOW            0x32   /* 5mb/s  */
+#define SYNC_DEFP_FAST            0x19   /* 10mb/s */
+
+  unsigned int snip;                      /* Sync. negotiation in progress */
+  unsigned int wnip;                      /* WIDE negotiation in progress */
+  unsigned int targets_present;           /* targets spoken to before */
+
+  int current_transfer_size;              /* Set at beginning of data dma */
+
+  unchar espcmdlog[32];                   /* Log of current esp cmds sent. */
+  unchar espcmdent;                       /* Current entry in esp cmd log. */
 
   /* Misc. info about this ESP */
   enum esp_rev erev;                      /* ESP revision */
   int irq;                                /* SBus IRQ for this ESP */
   int scsi_id;                            /* Who am I as initiator? */
   int scsi_id_mask;                       /* Bitmask of 'me'. */
-  int diff;                               /* Differential SCSI? */
+  int diff;                               /* Differential SCSI bus? */
   int bursts;                             /* Burst sizes our DVMA supports */
 
   /* Our command queues, only one cmd lives in the current_SC queue. */
@@ -133,12 +167,17 @@ struct Sparc_ESP {
   Scsi_Cmnd *current_SC;         /* Who is currently working the bus */
   Scsi_Cmnd *disconnected_SC;    /* Commands disconnected from the bus */
 
-#ifdef THREADED_ESP_DRIVER
-  Scsi_Cmnd *eatme_SC;           /* Cmds waiting for esp thread to process. */
-#endif
+  /* Message goo */
+  unchar cur_msgout[16];
+  unchar cur_msgin[16];
+  unchar prevmsgout, prevmsgin;
+  unchar msgout_len, msgin_len;
+  unchar msgout_ctr, msgin_ctr;
 
-  /* Abortion status */
-  int aborting, abortion_complete, abort_result;
+  /* States that we cannot keep in the per cmd structure because they
+   * cannot be assosciated with any specific command.
+   */
+  unchar resetting_bus;
 };
 
 /* Bitfield meanings for the above registers. */
@@ -152,30 +191,37 @@ struct Sparc_ESP {
 #define ESP_CONFIG1_SLCABLE   0x80             /* Enable slow cable mode */
 
 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
-#define ESP_CONFIG2_DMAPARITY 0x01             /* Parity DMA err (200,236) */
-#define ESP_CONFIG2_REGPARITY 0x02             /* Parity reg err (200,236) */
+#define ESP_CONFIG2_DMAPARITY 0x01             /* enable DMA Parity (200,236) */
+#define ESP_CONFIG2_REGPARITY 0x02             /* enable reg Parity (200,236) */
 #define ESP_CONFIG2_BADPARITY 0x04             /* Bad parity target abort  */
-#define ESP_CONFIG2_SCSI2ENAB 0x08             /* Enable SCSI-2 features   */
+#define ESP_CONFIG2_SCSI2ENAB 0x08             /* Enable SCSI-2 features (tmode only) */
 #define ESP_CONFIG2_HI        0x10             /* High Impedance DREQ ???  */
+#define ESP_CONFIG2_HMEFENAB  0x10             /* HME features enable */
 #define ESP_CONFIG2_BCM       0x20             /* Enable byte-ctrl (236)   */
+#define ESP_CONFIG2_DISPINT   0x20             /* Disable pause irq (hme) */
 #define ESP_CONFIG2_FENAB     0x40             /* Enable features (fas100,esp216)      */
 #define ESP_CONFIG2_SPL       0x40             /* Enable status-phase latch (esp236)   */
+#define ESP_CONFIG2_MKDONE    0x40             /* HME magic feature */
+#define ESP_CONFIG2_HME32     0x80             /* HME 32 extended */
 #define ESP_CONFIG2_MAGIC     0xe0             /* Invalid bits... */
 
-/* ESP config register 3 read-write, found only esp236+fas236+fas100a chips */
-#define ESP_CONFIG3_FCLOCK    0x01             /* FAST SCSI clock rate (esp100a)     */
+/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
+#define ESP_CONFIG3_FCLOCK    0x01             /* FAST SCSI clock rate (esp100a/hme) */
 #define ESP_CONFIG3_TEM       0x01             /* Enable thresh-8 mode (esp/fas236)  */
-#define ESP_CONFIG3_FAST      0x02             /* Enable FAST SCSI     (esp100a)     */
+#define ESP_CONFIG3_FAST      0x02             /* Enable FAST SCSI     (esp100a/hme) */
 #define ESP_CONFIG3_ADMA      0x02             /* Enable alternate-dma (esp/fas236)  */
-#define ESP_CONFIG3_TENB      0x04             /* group2 SCSI2 support (esp100a)     */
+#define ESP_CONFIG3_TENB      0x04             /* group2 SCSI2 support (esp100a/hme) */
 #define ESP_CONFIG3_SRB       0x04             /* Save residual byte   (esp/fas236)  */
-#define ESP_CONFIG3_TMS       0x08             /* Three-byte msg's ok  (esp100a)     */
+#define ESP_CONFIG3_TMS       0x08             /* Three-byte msg's ok  (esp100a/hme) */
 #define ESP_CONFIG3_FCLK      0x08             /* Fast SCSI clock rate (esp/fas236)  */
-#define ESP_CONFIG3_IDMSG     0x10             /* ID message checking  (esp100a)     */
+#define ESP_CONFIG3_IDMSG     0x10             /* ID message checking  (esp100a/hme) */
 #define ESP_CONFIG3_FSCSI     0x10             /* Enable FAST SCSI     (esp/fas236)  */
 #define ESP_CONFIG3_GTM       0x20             /* group2 SCSI2 support (esp/fas236)  */
+#define ESP_CONFIG3_BIGID     0x20             /* SCSI-ID's are 4bits  (hme)         */
 #define ESP_CONFIG3_TBMS      0x40             /* Three-byte msg's ok  (esp/fas236)  */
+#define ESP_CONFIG3_EWIDE     0x40             /* Enable Wide-SCSI     (hme)         */
 #define ESP_CONFIG3_IMS       0x80             /* ID msg chk'ng        (esp/fas236)  */
+#define ESP_CONFIG3_OBPUSH    0x80             /* Push odd-byte to dma (hme)         */
 
 /* ESP command register read-write */
 /* Group 1 commands:  These may be sent at any point in time to the ESP
@@ -244,6 +290,16 @@ struct Sparc_ESP {
  */
 #define ESP_STAT_INTR         0x80             /* Interrupt */
 
+/* HME only: status 2 register */
+#define ESP_STAT2_SCHBIT      0x01 /* Upper bits 3-7 of sstep enabled */
+#define ESP_STAT2_FFLAGS      0x02 /* The fifo flags are now latched */
+#define ESP_STAT2_XCNT        0x04 /* The transfer counter is latched */
+#define ESP_STAT2_CREGA       0x08 /* The command reg is active now */
+#define ESP_STAT2_WIDE        0x10 /* Interface on this adapter is wide */
+#define ESP_STAT2_F1BYTE      0x20 /* There is one byte at top of fifo */
+#define ESP_STAT2_FMSB        0x40 /* Next byte in fifo is most significant */
+#define ESP_STAT2_FEMPTY      0x80 /* FIFO is empty */
+
 /* The status register can be masked with ESP_STAT_PMASK and compared
  * with the following values to determine the current phase the ESP
  * (at least thinks it) is in.  For our purposes we also add our own
@@ -283,7 +339,12 @@ struct Sparc_ESP {
 #define ESP_STEP_PPC          0x03             /* Early phase chg caused cmnd
                                                 * bytes to be lost
                                                 */
-#define ESP_STEP_FINI         0x04             /* Command was sent ok */
+#define ESP_STEP_FINI4        0x04             /* Command was sent ok */
+
+/* Ho hum, some ESP's set the step register to this as well... */
+#define ESP_STEP_FINI5        0x05
+#define ESP_STEP_FINI6        0x06
+#define ESP_STEP_FINI7        0x07
 
 /* ESP chip-test register read-write */
 #define ESP_TEST_TARG         0x01             /* Target test mode */
@@ -299,6 +360,7 @@ struct Sparc_ESP {
 /* ESP fifo flags register read-only */
 /* Note that the following implies a 16 byte FIFO on the ESP. */
 #define ESP_FF_FBYTES         0x1f             /* Num bytes in FIFO */
+#define ESP_FF_ONOTZERO       0x20             /* offset ctr not zero (esp100) */
 #define ESP_FF_SSTEP          0xe0             /* Sequence step */
 
 /* ESP clock conversion factor register write-only */
@@ -311,20 +373,33 @@ struct Sparc_ESP {
 #define ESP_CCF_F6            0x06             /* 25.01MHz - 30MHz */
 #define ESP_CCF_F7            0x07             /* 30.01MHz - 35MHz */
 
+/* HME only... */
+#define ESP_BUSID_RESELID     0x10
+#define ESP_BUSID_CTR32BIT    0x40
+
+#define ESP_BUS_TIMEOUT        275             /* In milli-seconds */
+#define ESP_TIMEO_CONST       8192
+#define ESP_NEG_DEFP(mhz, cfact) \
+        ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
+#define ESP_MHZ_TO_CYCLE(mhertz)  ((1000000000) / ((mhertz) / 1000))
+#define ESP_TICK(ccf, cycle)  ((7682 * (ccf) * (cycle) / 1000))
+
 extern int esp_detect(struct SHT *);
 extern const char *esp_info(struct Scsi_Host *);
 extern int esp_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
 extern int esp_command(Scsi_Cmnd *);
 extern int esp_abort(Scsi_Cmnd *);
 extern int esp_reset(Scsi_Cmnd *, unsigned int);
+extern int esp_proc_info(char *buffer, char **start, off_t offset, int length,
+			 int hostno, int inout);
 
 extern struct proc_dir_entry proc_scsi_esp;
 
 #define SCSI_SPARC_ESP {                                                               \
 /* struct SHT *next */                                         NULL,                   \
-/* long *usage_count */                                        NULL,                   \
+/* struct module *module */                                    NULL,                   \
 /* struct proc_dir_entry *proc_dir */                          &proc_scsi_esp,         \
-/* int (*proc_info)(char *, char **, off_t, int, int, int) */  NULL,                   \
+/* int (*proc_info)(char *, char **, off_t, int, int, int) */  &esp_proc_info,         \
 /* const char *name */                                         "Sun ESP 100/100a/200", \
 /* int detect(struct SHT *) */                                 esp_detect,             \
 /* int release(struct Scsi_Host *) */                          NULL,                   \
@@ -335,7 +410,7 @@ extern struct proc_dir_entry proc_scsi_esp;
 /* int reset(Scsi_Cmnd *, int) */                              esp_reset,              \
 /* int slave_attach(int, int) */                               NULL,                   \
 /* int bios_param(Disk *, kdev_t, int[]) */                    NULL,                   \
-/* int can_queue */                                            10,                     \
+/* int can_queue */                                            7,                      \
 /* int this_id */                                              7,                      \
 /* short unsigned int sg_tablesize */                          SG_ALL,                 \
 /* short cmd_per_lun */                                        1,                      \