diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2000-01-29 01:41:54 +0000 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2000-01-29 01:41:54 +0000 |
commit | f969d69ba9f952e5bdd38278e25e26a3e4a61a70 (patch) | |
tree | b3530d803df59d726afaabebc6626987dee1ca05 /drivers/video | |
parent | a10ce7ef2066b455d69187643ddf2073bfc4db24 (diff) |
Merge with 2.3.27.
Diffstat (limited to 'drivers/video')
-rw-r--r-- | drivers/video/Config.in | 70 | ||||
-rw-r--r-- | drivers/video/Makefile | 4 | ||||
-rw-r--r-- | drivers/video/acornfb.c | 658 | ||||
-rw-r--r-- | drivers/video/acornfb.h | 200 | ||||
-rw-r--r-- | drivers/video/atafb.c | 10 | ||||
-rw-r--r-- | drivers/video/atyfb.c | 23 | ||||
-rw-r--r-- | drivers/video/clgenfb.c | 2 | ||||
-rw-r--r-- | drivers/video/cyber2000fb.c | 1008 | ||||
-rw-r--r-- | drivers/video/cyber2000fb.h | 54 | ||||
-rw-r--r-- | drivers/video/fbcon-mac.c | 2 | ||||
-rw-r--r-- | drivers/video/fbmem.c | 31 | ||||
-rw-r--r-- | drivers/video/igafb.c | 12 | ||||
-rw-r--r-- | drivers/video/nv4ref.h | 2445 | ||||
-rw-r--r-- | drivers/video/nvreg.h | 188 | ||||
-rw-r--r-- | drivers/video/riva_hw.c | 1429 | ||||
-rw-r--r-- | drivers/video/riva_hw.h | 343 | ||||
-rw-r--r-- | drivers/video/riva_tbl.h | 402 | ||||
-rw-r--r-- | drivers/video/rivafb.c | 1890 | ||||
-rw-r--r-- | drivers/video/sbusfb.c | 17 | ||||
-rw-r--r-- | drivers/video/sgivwfb.c | 7 | ||||
-rw-r--r-- | drivers/video/tdfxfb.c | 1461 |
21 files changed, 8787 insertions, 1469 deletions
diff --git a/drivers/video/Config.in b/drivers/video/Config.in index 77d72f3f3..e9ab31ccb 100644 --- a/drivers/video/Config.in +++ b/drivers/video/Config.in @@ -10,6 +10,9 @@ bool 'Support for frame buffer devices (EXPERIMENTAL)' CONFIG_FB if [ "$CONFIG_FB" = "y" ]; then define_bool CONFIG_DUMMY_CONSOLE y if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then + if [ "$CONFIG_PCI" = "y" ]; then + bool ' nVidia Riva support (EXPERIMENTAL)' CONFIG_FB_RIVA + fi if [ "$CONFIG_AMIGA" = "y" -o "$CONFIG_PCI" = "y" ]; then tristate ' Cirrus Logic suport (EXPERIMENTAL)' CONFIG_FB_CLGEN tristate ' Permedia2 support (EXPERIMENTAL)' CONFIG_FB_PM2 @@ -162,25 +165,25 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_MAC" = "y" -o "$CONFIG_FB_RETINAZ3" = "y" -o \ "$CONFIG_FB_VIRGE" = "y" -o "$CONFIG_FB_VIRTUAL" = "y" -o \ "$CONFIG_FB_BWTWO" = "y" -o "$CONFIG_FB_CLGEN" = "y" ]; then - define_bool CONFIG_FBCON_MFB y + define_tristate CONFIG_FBCON_MFB y else if [ "$CONFIG_FB_ACORN" = "m" -o "$CONFIG_FB_AMIGA" = "m" -o \ "$CONFIG_FB_ATARI" = "m" -o "$CONFIG_FB_CYBER" = "m" -o \ "$CONFIG_FB_MAC" = "m" -o "$CONFIG_FB_RETINAZ3" = "m" -o \ "$CONFIG_FB_VIRGE" = "m" -o "$CONFIG_FB_VIRTUAL" = "m" -o \ "$CONFIG_FB_BWTWO" = "m" -o "$CONFIG_FB_CLGEN" = "m" ]; then - define_bool CONFIG_FBCON_MFB m + define_tristate CONFIG_FBCON_MFB m fi fi if [ "$CONFIG_FB_ACORN" = "y" -o "$CONFIG_FB_MAC" = "y" -o \ "$CONFIG_FB_VIRTUAL" = "y" ]; then - define_bool CONFIG_FBCON_CFB2 y - define_bool CONFIG_FBCON_CFB4 y + define_tristate CONFIG_FBCON_CFB2 y + define_tristate CONFIG_FBCON_CFB4 y else if [ "$CONFIG_FB_ACORN" = "m" -o "$CONFIG_FB_MAC" = "m" -o \ "$CONFIG_FB_VIRTUAL" = "m" ]; then - define_bool CONFIG_FBCON_CFB2 m - define_bool CONFIG_FBCON_CFB4 m + define_tristate CONFIG_FBCON_CFB2 m + define_tristate CONFIG_FBCON_CFB4 m fi fi if [ "$CONFIG_FB_ACORN" = "y" -o "$CONFIG_FB_ATARI" = "y" -o \ @@ -195,9 +198,10 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_IGA" = "y" -o "$CONFIG_FB_MATROX" = "y" -o \ "$CONFIG_FB_CT65550" = "y" -o "$CONFIG_FB_PM2" = "y" -o \ "$CONFIG_FB_P9100" = "y" -o \ + "$CONFIG_FB_RIVA" = "y" -o \ "$CONFIG_FB_SGIVW" = "y" -o "$CONFIG_FB_CYBER2000" = "y" -o \ "$CONFIG_FB_3DFX" = "y" ]; then - define_bool CONFIG_FBCON_CFB8 y + define_tristate CONFIG_FBCON_CFB8 y else if [ "$CONFIG_FB_ACORN" = "m" -o "$CONFIG_FB_ATARI" = "m" -o \ "$CONFIG_FB_ATY" = "m" -o "$CONFIG_FB_MAC" = "m" -o \ @@ -212,7 +216,7 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_CT65550" = "m" -o "$CONFIG_FB_PM2" = "m" -o \ "$CONFIG_FB_P9100" = "m" -o \ "$CONFIG_FB_SGIVW" = "m" -o "$CONFIG_FB_CYBER2000" = "m" ]; then - define_bool CONFIG_FBCON_CFB8 m + define_tristate CONFIG_FBCON_CFB8 m fi fi if [ "$CONFIG_FB_ATARI" = "y" -o "$CONFIG_FB_ATY" = "y" -o \ @@ -224,8 +228,9 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_VALKYRIE" = "y" -o "$CONFIG_FB_PLATINUM" = "y" -o \ "$CONFIG_FB_CT65550" = "y" -o "$CONFIG_FB_MATROX" = "y" -o \ "$CONFIG_FB_PM2" = "y" -o "$CONFIG_FB_SGIVW" = "y" -o \ + "$CONFIG_FB_RIVA" = "y" -o \ "$CONFIG_FB_CYBER2000" = "y" -o "$CONFIG_FB_3DFX" = "y" ]; then - define_bool CONFIG_FBCON_CFB16 y + define_tristate CONFIG_FBCON_CFB16 y else if [ "$CONFIG_FB_ATARI" = "m" -o "$CONFIG_FB_ATY" = "m" -o \ "$CONFIG_FB_MAC" = "m" -o "$CONFIG_FB_VESA" = "m" -o \ @@ -237,20 +242,20 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_CT65550" = "m" -o "$CONFIG_FB_MATROX" = "m" -o \ "$CONFIG_FB_PM2" = "y" -o "$CONFIG_FB_SGIVW" = "m" -o \ "$CONFIG_FB_CYBER2000" = "m" ]; then - define_bool CONFIG_FBCON_CFB16 m + define_tristate CONFIG_FBCON_CFB16 m fi fi if [ "$CONFIG_FB_ATY" = "y" -o "$CONFIG_FB_VIRTUAL" = "y" -o \ "$CONFIG_FB_CLGEN" = "y" -o "$CONFIG_FB_VESA" = "y" -o \ "$CONFIG_FB_MATROX" = "y" -o "$CONFIG_FB_PM2" = "y" -o \ "$CONFIG_FB_CYBER2000" = "y" ]; then - define_bool CONFIG_FBCON_CFB24 y + define_tristate CONFIG_FBCON_CFB24 y else if [ "$CONFIG_FB_ATY" = "m" -o "$CONFIG_FB_VIRTUAL" = "m" -o \ "$CONFIG_FB_CLGEN" = "m" -o "$CONFIG_FB_VESA" = "m" -o \ "$CONFIG_FB_MATROX" = "m" -o "$CONFIG_FB_PM2" = "m" -o \ "$CONFIG_FB_CYBER2000" = "m" ]; then - define_bool CONFIG_FBCON_CFB24 m + define_tristate CONFIG_FBCON_CFB24 m fi fi if [ "$CONFIG_FB_ATARI" = "y" -o "$CONFIG_FB_ATY" = "y" -o \ @@ -258,9 +263,10 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_CONTROL" = "y" -o "$CONFIG_FB_CLGEN" = "y" -o \ "$CONFIG_FB_TGA" = "y" -o "$CONFIG_FB_PLATINUM" = "y" -o \ "$CONFIG_FB_MATROX" = "y" -o "$CONFIG_FB_PM2" = "y" -o \ + "$CONFIG_FB_RIVA" = "y" -o \ "$CONFIG_FB_FM2" = "y" -o "$CONFIG_FB_SGIVW" = "y" -o \ "$CONFIG_FB_3DFX" = "y" ]; then - define_bool CONFIG_FBCON_CFB32 y + define_tristate CONFIG_FBCON_CFB32 y else if [ "$CONFIG_FB_ATARI" = "m" -o "$CONFIG_FB_ATY" = "m" -o \ "$CONFIG_FB_VESA" = "m" -o "$CONFIG_FB_VIRTUAL" = "m" -o \ @@ -268,50 +274,50 @@ if [ "$CONFIG_FB" = "y" ]; then "$CONFIG_FB_TGA" = "m" -o "$CONFIG_FB_PLATINUM" = "m" -o \ "$CONFIG_FB_MATROX" = "m" -o "$CONFIG_FB_PM2" = "m" -o \ "$CONFIG_FB_SGIVW" = "m" ]; then - define_bool CONFIG_FBCON_CFB32 m + define_tristate CONFIG_FBCON_CFB32 m fi fi if [ "$CONFIG_FB_AMIGA" = "y" ]; then - define_bool CONFIG_FBCON_AFB y - define_bool CONFIG_FBCON_ILBM y + define_tristate CONFIG_FBCON_AFB y + define_tristate CONFIG_FBCON_ILBM y else if [ "$CONFIG_FB_AMIGA" = "m" ]; then - define_bool CONFIG_FBCON_AFB m - define_bool CONFIG_FBCON_ILBM m + define_tristate CONFIG_FBCON_AFB m + define_tristate CONFIG_FBCON_ILBM m fi fi if [ "$CONFIG_FB_ATARI" = "y" ]; then - define_bool CONFIG_FBCON_IPLAN2P2 y - define_bool CONFIG_FBCON_IPLAN2P4 y - define_bool CONFIG_FBCON_IPLAN2P8 y -# define_bool CONFIG_FBCON_IPLAN2P16 y + define_tristate CONFIG_FBCON_IPLAN2P2 y + define_tristate CONFIG_FBCON_IPLAN2P4 y + define_tristate CONFIG_FBCON_IPLAN2P8 y +# define_tristate CONFIG_FBCON_IPLAN2P16 y else if [ "$CONFIG_FB_ATARI" = "m" ]; then - define_bool CONFIG_FBCON_IPLAN2P2 m - define_bool CONFIG_FBCON_IPLAN2P4 m - define_bool CONFIG_FBCON_IPLAN2P8 m -# define_bool CONFIG_FBCON_IPLAN2P16 m + define_tristate CONFIG_FBCON_IPLAN2P2 m + define_tristate CONFIG_FBCON_IPLAN2P4 m + define_tristate CONFIG_FBCON_IPLAN2P8 m +# define_tristate CONFIG_FBCON_IPLAN2P16 m fi fi if [ "$CONFIG_FB_MAC" = "y" -o "$CONFIG_FB_VIRTUAL" = "y" ]; then - define_bool CONFIG_FBCON_MAC y + define_tristate CONFIG_FBCON_MAC y else if [ "$CONFIG_FB_MAC" = "m" -o "$CONFIG_FB_VIRTUAL" = "m" ]; then - define_bool CONFIG_FBCON_MAC m + define_tristate CONFIG_FBCON_MAC m fi fi if [ "$CONFIG_FB_VGA16" = "y" ]; then - define_bool CONFIG_FBCON_VGA_PLANES y + define_tristate CONFIG_FBCON_VGA_PLANES y else if [ "$CONFIG_FB_VGA16" = "m" ]; then - define_bool CONFIG_FBCON_VGA_PLANES m + define_tristate CONFIG_FBCON_VGA_PLANES m fi fi if [ "$CONFIG_FB_MDA" = "y" -o "$CONFIG_FB_VGA" = "y" ]; then - define_bool CONFIG_FBCON_VGA y + define_tristate CONFIG_FBCON_VGA y else if [ "$CONFIG_FB_MDA" = "m" -o "$CONFIG_FB_VGA" = "m" ]; then - define_bool CONFIG_FBCON_VGA m + define_tristate CONFIG_FBCON_VGA m fi fi fi diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 5c85927cb..9551de6bb 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -161,6 +161,10 @@ else endif endif +ifeq ($(CONFIG_FB_RIVA),y) +L_OBJS += rivafb.o riva_hw.o +endif + ifeq ($(CONFIG_FB_3DFX),y) L_OBJS += tdfxfb.o endif diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c index 8efdcbe59..eec19a285 100644 --- a/drivers/video/acornfb.c +++ b/drivers/video/acornfb.c @@ -1,5 +1,5 @@ /* - * linux/drivers/video/acorn.c + * linux/drivers/video/acornfb.c * * Copyright (C) 1998,1999 Russell King * @@ -36,6 +36,8 @@ #include <video/fbcon-cfb16.h> #include <video/fbcon-cfb32.h> +#include "acornfb.h" + /* * Default resolution. * NOTE that it has to be supported in the table towards @@ -43,78 +45,40 @@ */ #define DEFAULT_XRES 640 #define DEFAULT_YRES 480 - /* - * define this to debug the video mode selection + * The order here defines which BPP we + * pick depending on which resolutions + * we have configured. */ -#undef DEBUG_MODE_SELECTION - -#if defined(HAS_VIDC20) -#define VIDC_PALETTE_SIZE 256 -#define VIDC_NAME "VIDC20" -#elif defined(HAS_VIDC) -#include <asm/memc.h> -#define VIDC_PALETTE_SIZE 16 -#define VIDC_NAME "VIDC" +#if defined(FBCON_HAS_CFB4) +# define DEFAULT_BPP 4 +#elif defined(FBCON_HAS_CFB8) +# define DEFAULT_BPP 8 +#elif defined(FBCON_HAS_CFB16) +# define DEFAULT_BPP 16 +#elif defined(FBCON_HAS_CFB2) +# define DEFAULT_BPP 2 +#elif defined(FBCON_HAS_MFB) +# define DEFAULT_BPP 1 +#else +#error No suitable framebuffers configured #endif -#define EXTEND8(x) ((x)|(x)<<8) -#define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12) - -struct vidc20_palette { - u_int red:8; - u_int green:8; - u_int blue:8; - u_int ext:4; - u_int unused:4; -}; - -struct vidc_palette { - u_int red:4; - u_int green:4; - u_int blue:4; - u_int trans:1; - u_int sbz1:13; - u_int reg:4; - u_int sbz2:2; -}; - -union palette { - struct vidc20_palette vidc20; - struct vidc_palette vidc; - u_int p; -}; -struct acornfb_par { - unsigned long screen_base; - unsigned long screen_base_p; - unsigned long screen_end; - unsigned long screen_size; - unsigned int dram_size; - unsigned int vram_half_sam; - unsigned int palette_size; - signed int montype; - signed int currcon; - unsigned int allow_modeset : 1; - unsigned int using_vram : 1; - unsigned int dpms : 1; - - union palette palette[VIDC_PALETTE_SIZE]; - - union { - unsigned short cfb16[16]; - unsigned long cfb32[16]; - } cmap; -}; +/* + * define this to debug the video mode selection + */ +#undef DEBUG_MODE_SELECTION /* * Translation from RISC OS monitor types to actual * HSYNC and VSYNC frequency ranges. These are - * probably not right... + * probably not right, but they're the best info I + * have. Allow 1% either way on the nominal for TVs. */ #define NR_MONTYPES 6 static struct fb_monspecs monspecs[NR_MONTYPES] __initdata = { - { 15625, 15625, 50, 50, 0 }, /* TV */ + { 15469, 15781, 49, 51, 0 }, /* TV */ { 0, 99999, 0, 99, 0 }, /* Multi Freq */ { 58608, 58608, 64, 64, 0 }, /* Hi-res mono */ { 30000, 70000, 60, 60, 0 }, /* VGA */ @@ -125,56 +89,14 @@ static struct fb_monspecs monspecs[NR_MONTYPES] __initdata = { static struct display global_disp; static struct fb_info fb_info; static struct acornfb_par current_par; +static struct vidc_timing current_vidc; static struct fb_var_screeninfo __initdata init_var = {}; extern int acornfb_depth; /* set by setup.c */ extern unsigned int vram_size; /* set by setup.c */ - -static struct vidc_timing { - u_int h_cycle; - u_int h_sync_width; - u_int h_border_start; - u_int h_display_start; - u_int h_display_end; - u_int h_border_end; - u_int h_interlace; - - u_int v_cycle; - u_int v_sync_width; - u_int v_border_start; - u_int v_display_start; - u_int v_display_end; - u_int v_border_end; - - u_int control; - - /* VIDC20 only */ - u_int pll_ctl; -} current_vidc; - #ifdef HAS_VIDC -#define VID_CTL_VS_NVSYNC (1 << 3) -#define VID_CTL_HS_NHSYNC (1 << 2) -#define VID_CTL_24MHz (0) -#define VID_CTL_25MHz (1) -#define VID_CTL_36MHz (2) - -#define VIDC_CTRL_INTERLACE (1 << 6) -#define VIDC_CTRL_FIFO_0_4 (0 << 4) -#define VIDC_CTRL_FIFO_1_5 (1 << 4) -#define VIDC_CTRL_FIFO_2_6 (2 << 4) -#define VIDC_CTRL_FIFO_3_7 (3 << 4) -#define VIDC_CTRL_1BPP (0 << 2) -#define VIDC_CTRL_2BPP (1 << 2) -#define VIDC_CTRL_4BPP (2 << 2) -#define VIDC_CTRL_8BPP (3 << 2) -#define VIDC_CTRL_DIV3 (0 << 0) -#define VIDC_CTRL_DIV2 (1 << 0) -#define VIDC_CTRL_DIV1_5 (2 << 0) -#define VIDC_CTRL_DIV1 (3 << 0) - /* CTL VIDC Actual * 24.000 0 8.000 * 25.175 0 8.392 @@ -411,162 +333,7 @@ acornfb_palette_decode(u_int regno, u_int *red, u_int *green, u_int *blue, #endif #ifdef HAS_VIDC20 -/* - * VIDC20 registers - */ -#define VIDC20_CTRL 0xe0000000 -#define VIDC20_CTRL_PIX_VCLK (0 << 0) -#define VIDC20_CTRL_PIX_HCLK (1 << 0) -#define VIDC20_CTRL_PIX_RCLK (2 << 0) -#define VIDC20_CTRL_PIX_CK (0 << 2) -#define VIDC20_CTRL_PIX_CK2 (1 << 2) -#define VIDC20_CTRL_PIX_CK3 (2 << 2) -#define VIDC20_CTRL_PIX_CK4 (3 << 2) -#define VIDC20_CTRL_PIX_CK5 (4 << 2) -#define VIDC20_CTRL_PIX_CK6 (5 << 2) -#define VIDC20_CTRL_PIX_CK7 (6 << 2) -#define VIDC20_CTRL_PIX_CK8 (7 << 2) -#define VIDC20_CTRL_1BPP (0 << 5) -#define VIDC20_CTRL_2BPP (1 << 5) -#define VIDC20_CTRL_4BPP (2 << 5) -#define VIDC20_CTRL_8BPP (3 << 5) -#define VIDC20_CTRL_16BPP (4 << 5) -#define VIDC20_CTRL_32BPP (6 << 5) -#define VIDC20_CTRL_FIFO_NS (0 << 8) -#define VIDC20_CTRL_FIFO_4 (1 << 8) -#define VIDC20_CTRL_FIFO_8 (2 << 8) -#define VIDC20_CTRL_FIFO_12 (3 << 8) -#define VIDC20_CTRL_FIFO_16 (4 << 8) -#define VIDC20_CTRL_FIFO_20 (5 << 8) -#define VIDC20_CTRL_FIFO_24 (6 << 8) -#define VIDC20_CTRL_FIFO_28 (7 << 8) -#define VIDC20_CTRL_INT (1 << 12) -#define VIDC20_CTRL_DUP (1 << 13) -#define VIDC20_CTRL_PDOWN (1 << 14) - -#define VIDC20_ECTL 0xc0000000 -#define VIDC20_ECTL_REG(x) ((x) & 0xf3) -#define VIDC20_ECTL_ECK (1 << 2) -#define VIDC20_ECTL_REDPED (1 << 8) -#define VIDC20_ECTL_GREENPED (1 << 9) -#define VIDC20_ECTL_BLUEPED (1 << 10) -#define VIDC20_ECTL_DAC (1 << 12) -#define VIDC20_ECTL_LCDGS (1 << 13) -#define VIDC20_ECTL_HRM (1 << 14) - -#define VIDC20_ECTL_HS_MASK (3 << 16) -#define VIDC20_ECTL_HS_HSYNC (0 << 16) -#define VIDC20_ECTL_HS_NHSYNC (1 << 16) -#define VIDC20_ECTL_HS_CSYNC (2 << 16) -#define VIDC20_ECTL_HS_NCSYNC (3 << 16) - -#define VIDC20_ECTL_VS_MASK (3 << 18) -#define VIDC20_ECTL_VS_VSYNC (0 << 18) -#define VIDC20_ECTL_VS_NVSYNC (1 << 18) -#define VIDC20_ECTL_VS_CSYNC (2 << 18) -#define VIDC20_ECTL_VS_NCSYNC (3 << 18) - -#define VIDC20_DCTL 0xf0000000 -/* 0-9 = number of words in scanline */ -#define VIDC20_DCTL_SNA (1 << 12) -#define VIDC20_DCTL_HDIS (1 << 13) -#define VIDC20_DCTL_BUS_NS (0 << 16) -#define VIDC20_DCTL_BUS_D31_0 (1 << 16) -#define VIDC20_DCTL_BUS_D63_32 (2 << 16) -#define VIDC20_DCTL_BUS_D63_0 (3 << 16) -#define VIDC20_DCTL_VRAM_DIS (0 << 18) -#define VIDC20_DCTL_VRAM_PXCLK (1 << 18) -#define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18) -#define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18) - -#define acornfb_valid_pixrate(rate) (1) - -/* - * Try to find the best PLL parameters for the pixel clock. - * This algorithm seems to give best predictable results, - * and produces the same values as detailed in the VIDC20 - * data sheet. - */ -static inline u_int -acornfb_vidc20_find_pll(u_int pixclk) -{ - u_int r, best_r = 2, best_v = 2; - int best_d = 0x7fffffff; - - for (r = 2; r <= 32; r++) { - u_int rr, v, p; - int d; - - rr = 41667 * r; - - v = (rr + pixclk / 2) / pixclk; - - if (v > 32 || v < 2) - continue; - - p = (rr + v / 2) / v; - - d = pixclk - p; - - if (d < 0) - d = -d; - - if (d < best_d) { - best_d = d; - best_v = v - 1; - best_r = r - 1; - } - - if (d == 0) - break; - } - - return best_v << 8 | best_r; -} - -static inline void -acornfb_vidc20_find_rates(struct vidc_timing *vidc, - struct fb_var_screeninfo *var) -{ - u_int div, bandwidth; - - /* Select pixel-clock divisor to keep PLL in range */ - div = var->pixclock / 9090; /*9921*/ - - /* Limit divisor */ - if (div == 0) - div = 1; - if (div > 8) - div = 8; - - /* Encode divisor to VIDC20 setting */ - switch (div) { - case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; - case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; - case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; - case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; - case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; - case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; - case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; - case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; - } - - /* Calculate bandwidth */ - bandwidth = var->pixclock * 8 / var->bits_per_pixel; - - /* Encode bandwidth as VIDC20 setting */ - if (bandwidth > 33334) - vidc->control |= VIDC20_CTRL_FIFO_16; /* < 30.0MB/s */ - else if (bandwidth > 26666) - vidc->control |= VIDC20_CTRL_FIFO_20; /* < 37.5MB/s */ - else if (bandwidth > 22222) - vidc->control |= VIDC20_CTRL_FIFO_24; /* < 45.0MB/s */ - else - vidc->control |= VIDC20_CTRL_FIFO_28; /* > 45.0MB/s */ - - /* Find the PLL values */ - vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); -} +#include <asm/arch/acornfb.h> /* VIDC20 has a different set of rules from the VIDC: * hcr : must be multiple of 4 @@ -600,7 +367,7 @@ acornfb_set_timing(struct fb_var_screeninfo *var) vidc.v_display_start = vidc.v_border_start; vidc.v_display_end = vidc.v_display_start + var->yres; vidc.v_border_end = vidc.v_display_end; - vidc.control = VIDC20_CTRL_PIX_VCLK; + vidc.control = acornfb_default_control(); vcr = var->vsync_len + var->upper_margin + var->yres + var->lower_margin; @@ -649,7 +416,7 @@ acornfb_set_timing(struct fb_var_screeninfo *var) outl(fsize, IOMD_FSIZE); - ext_ctl = VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3); + ext_ctl = acornfb_default_econtrol(); if (var->sync & FB_SYNC_HOR_HIGH_ACT) ext_ctl |= VIDC20_ECTL_HS_HSYNC; @@ -744,7 +511,7 @@ acornfb_palette_decode(u_int regno, u_int *red, u_int *green, u_int *blue, * the resolution to fit the rules. */ static int -acornfb_pre_adjust_timing(struct fb_var_screeninfo *var, int con) +acornfb_adjust_timing(struct fb_var_screeninfo *var, int con) { u_int font_line_len; u_int fontht; @@ -828,17 +595,7 @@ acornfb_pre_adjust_timing(struct fb_var_screeninfo *var, int con) if (var->yoffset + var->yres > var->yres_virtual) var->yoffset = var->yres_virtual - var->yres; } - return 0; -} -/* - * After selecting the timing parameters, adjust - * the timing to suit the chip. - * NOTE! Only minor adjustments should be made here. - */ -static void -acornfb_post_adjust_timing(struct fb_var_screeninfo *var) -{ /* hsync_len must be even */ var->hsync_len = (var->hsync_len + 1) & ~1; @@ -865,6 +622,31 @@ acornfb_post_adjust_timing(struct fb_var_screeninfo *var) if (var->vsync_len < 1) var->vsync_len = 1; + + return 0; +} + +static int +acornfb_validate_timing(struct fb_var_screeninfo *var, + struct fb_monspecs *monspecs) +{ + unsigned long hs, vs; + + /* + * hs(Hz) = 10^12 / (pixclock * xtotal) + * vs(Hz) = hs(Hz) / ytotal + * + * No need to do long long divisions or anything + * like that if you factor it correctly + */ + hs = 1953125000 / var->pixclock; + hs = hs * 512 / + (var->xres + var->left_margin + var->right_margin + var->hsync_len); + vs = hs / + (var->yres + var->upper_margin + var->lower_margin + var->vsync_len); + + return (vs >= monspecs->vfmin && vs <= monspecs->vfmax && + hs >= monspecs->hfmin && hs <= monspecs->hfmax) ? 0 : -EINVAL; } static inline void @@ -1064,10 +846,18 @@ acornfb_decode_var(struct fb_var_screeninfo *var, int con, int *visual) return -EINVAL; /* - * Validate and adjust the resolution - * before using it. + * Validate and adjust the resolution to + * match the video generator hardware. + */ + err = acornfb_adjust_timing(var, con); + if (err) + return err; + + /* + * Validate the timing against the + * monitor hardware. */ - err = acornfb_pre_adjust_timing(var, con); + err = acornfb_validate_timing(var, &fb_info.monspecs); if (err) return err; @@ -1110,11 +900,6 @@ acornfb_decode_var(struct fb_var_screeninfo *var, int con, int *visual) var->blue = var->red; var->transp.length = 1; #endif - /* - * Now adjust the timing parameters - */ - acornfb_post_adjust_timing(var); - return 0; } @@ -1403,7 +1188,9 @@ acornfb_blank(int blank, struct fb_info *info) acornfb_palette_write(i, p); } - } else { + } +#ifdef FBCON_HAS_CFB16 + else { p.p = 0; for (i = 0; i < 256; i++) { @@ -1417,220 +1204,68 @@ acornfb_blank(int blank, struct fb_info *info) acornfb_palette_write(i, current_par.palette[i]); } } +#endif } /* * Everything after here is initialisation!!! */ -struct modey_params { - u_int y_res; - u_int u_margin; - u_int b_margin; - u_int vsync_len; - u_int vf; -}; - -struct modex_params { - u_int x_res; - u_int l_margin; - u_int r_margin; - u_int hsync_len; - u_int clock; - u_int hf; - const struct modey_params *modey; -}; - -static const struct modey_params modey_640_15600[] __initdata = { - { 250, 38, 21, 3, 50 }, /* 640x 250, 50Hz */ - { 256, 35, 18, 3, 50 }, /* 640x 256, 50Hz */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_640_26800[] __initdata = { - { 512, 18, 1, 3, 50 }, /* 640x 512, 50Hz */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_640_31500[] __initdata = { - { 250, 109, 88, 2, 70 }, /* 640x 250, 70Hz */ - { 256, 106, 85, 2, 70 }, /* 640x 256, 70Hz */ - { 352, 58, 37, 2, 70 }, /* 640x 352, 70Hz */ - { 480, 32, 11, 2, 60 }, /* 640x 480, 60Hz */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_800_35200[] __initdata = { - { 600, 22, 1, 2, 56 }, /* 800x 600, 56Hz */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_896_21800[] __initdata = { - { 352, 9, 0, 3, 60 }, /* 896x 352, 60Hz */ - { 0, 0, 0, 0, 0 } -}; - -/* everything after here is not supported */ -static const struct modey_params modey_1024_uk[] __initdata = { - { 768, 0, 0, 0, 0 }, /* 1024x 768 */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_1056_uk[] __initdata = { - { 250, 0, 0, 0, 0 }, /* 1056x 250 */ - { 256, 0, 0, 0, 0 }, /* 1056x 256 */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_1152_uk[] __initdata = { - { 896, 0, 0, 0, 0 }, /* 1152x 896 */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_1280_63600[] __initdata = { - { 1024, 0, 0, 0, 60 }, /* 1280x1024, 60Hz */ - { 0, 0, 0, 0, 0 } -}; - -static const struct modey_params modey_1600_uk[] __initdata = { - { 1280, 0, 0, 0, 0 }, /* 1600x1280 */ - { 0, 0, 0, 0, 0 } -}; - -/* - * Horizontal video programming requirements. - * This table is searched for the required horizontal - * and required frequency, and then the tables above - * are then searched for the required vertical - * resolution. - * - * NOTE! we can match multiple entries, so we search - * all horizontal entries for which the hfreq is within - * the monitor's range. - */ -static const struct modex_params modex_params[] __initdata = { - { /* X: 640, 15.6kHz */ - 640, 185, 123, 76, 16000, 15625, modey_640_15600 - }, - { /* X: 640, 26.8kHz */ - 640, 113, 87, 56, 24000, 26800, modey_640_26800 - }, - { /* X: 640, 31.5kHz */ - 640, 48, 16, 96, 25175, 31500, modey_640_31500 - }, - { /* X: 800, 35.2kHz */ - 800, 101, 23, 100, 36000, 35200, modey_800_35200 - }, - { /* X: 896, 21.8kHz */ - 896, 59, 27, 118, 24000, 21800, modey_896_21800 - }, - { /* X: 1024 */ - 1024, 0, 0, 0, 0, 0, modey_1024_uk - }, - { /* X: 1056 */ - 1056, 0, 0, 0, 0, 0, modey_1056_uk - }, - { /* X: 1152 */ - 1152, 0, 0, 0, 0, 0, modey_1152_uk - }, - { /* X: 1280, 63.6kHz */ - 1280, 0, 0, 0, 0, 63600, modey_1280_63600 - }, - { /* X: 1600 */ - 1600, 0, 0, 0, 0, 0, modey_1600_uk - }, - { +static struct fb_videomode modedb[] __initdata = { + { /* 640x250 @ 50Hz, 15.6 kHz hsync */ + NULL, 50, 640, 250, 62500, 185, 123, 38, 21, 76, 3, 0, - } + FB_VMODE_NONINTERLACED + }, { /* 640x256 @ 50Hz, 15.6 kHz hsync */ + NULL, 50, 640, 256, 62500, 185, 123, 35, 18, 76, 3, + 0, + FB_VMODE_NONINTERLACED + }, { /* 640x512 @ 50Hz, 26.8 kHz hsync */ + NULL, 50, 640, 512, 41667, 113, 87, 18, 1, 56, 3, + 0, + FB_VMODE_NONINTERLACED + }, { /* 640x250 @ 70Hz, 31.5 kHz hsync */ + NULL, 70, 640, 250, 39722, 48, 16, 109, 88, 96, 2, + 0, + FB_VMODE_NONINTERLACED + }, { /* 640x256 @ 70Hz, 31.5 kHz hsync */ + NULL, 70, 640, 256, 39722, 48, 16, 106, 85, 96, 2, + 0, + FB_VMODE_NONINTERLACED + }, { /* 640x352 @ 70Hz, 31.5 kHz hsync */ + NULL, 70, 640, 352, 39722, 48, 16, 58, 37, 96, 2, + 0, + FB_VMODE_NONINTERLACED + }, { /* 640x480 @ 60Hz, 31.5 kHz hsync */ + NULL, 60, 640, 480, 39722, 48, 16, 32, 11, 96, 2, + 0, + FB_VMODE_NONINTERLACED + }, { /* 800x600 @ 56Hz, 35.2 kHz hsync */ + NULL, 56, 800, 600, 27778, 101, 23, 22, 1, 100, 2, + 0, + FB_VMODE_NONINTERLACED + }, { /* 896x352 @ 60Hz, 21.8 kHz hsync */ + NULL, 60, 896, 352, 41667, 59, 27, 9, 0, 118, 3, + 0, + FB_VMODE_NONINTERLACED + }, }; -static int __init -acornfb_lookup_timing(struct fb_var_screeninfo *var) -{ - const struct modex_params *x; - const struct modey_params *y; - - /* - * We must adjust the resolution parameters - * before selecting the timing parameters. - */ - acornfb_pre_adjust_timing(var, -1); - - for (x = modex_params; x->x_res; x++) { - - /* - * Is this resolution one we're looking for? - */ - if (x->x_res != var->xres) - continue; - - /* - * Is the hsync frequency ok for our monitor? - */ - if (x->hf > fb_info.monspecs.hfmax || - x->hf < fb_info.monspecs.hfmin) - continue; - - /* - * Try to find a vertical resolution - */ - for (y = x->modey; y->y_res; y++) { - /* - * Is this resolution one we're looking for? - */ - if (y->y_res != var->yres) - continue; - - /* - * Is the vsync frequency ok for our monitor? - */ - if (y->vf > fb_info.monspecs.vfmax || - y->vf < fb_info.monspecs.vfmin) - continue; - - goto found; - } - } - - var->pixclock = 0; - - return -EINVAL; - -found: - /* - * Why is pixclock in picoseconds? - */ - switch (x->clock) { - case 36000: var->pixclock = 27778; break; - case 25175: var->pixclock = 39722; break; - case 24000: var->pixclock = 41667; break; - case 16000: var->pixclock = 62500; break; - case 12000: var->pixclock = 83333; break; - case 8000: var->pixclock = 125000; break; - default: var->pixclock = 0; break; - } - -#ifdef DEBUG_MODE_SELECTION - printk(KERN_DEBUG "Found %dx%d at %d.%3dkHz, %dHz, pix %d\n", - x->x_res, y->y_res, - x->hf / 1000, x->hf % 1000, - y->vf, var->pixclock); -#endif - - var->left_margin = x->l_margin; - var->right_margin = x->r_margin; - var->upper_margin = y->u_margin; - var->lower_margin = y->b_margin; - var->hsync_len = x->hsync_len; - var->vsync_len = y->vsync_len; - var->sync = 0; - - /* - * Now adjust the parameters we found - */ - acornfb_post_adjust_timing(var); - - return 0; -} +static struct fb_videomode __initdata +acornfb_default_mode = { + name: NULL, + refresh: 60, + xres: 640, + yres: 480, + pixclock: 39722, + left_margin: 56, + right_margin: 16, + upper_margin: 34, + lower_margin: 9, + hsync_len: 88, + vsync_len: 2, + sync: 0, + vmode: FB_VMODE_NONINTERLACED +}; static void __init acornfb_init_fbinfo(void) @@ -1659,20 +1294,6 @@ acornfb_init_fbinfo(void) * setup initial parameters */ memset(&init_var, 0, sizeof(init_var)); - init_var.xres = DEFAULT_XRES; - init_var.yres = DEFAULT_YRES; - -#if defined(FBCON_HAS_CFB4) - init_var.bits_per_pixel = 4; -#elif defined(FBCON_HAS_CFB8) - init_var.bits_per_pixel = 8; -#elif defined(FBCON_HAS_CFB2) - init_var.bits_per_pixel = 2; -#elif defined(FBCON_HAS_MFB) - init_var.bits_per_pixel = 1; -#else -#error No suitable framebuffers configured -#endif #if defined(HAS_VIDC20) init_var.red.length = 8; @@ -1922,6 +1543,7 @@ acornfb_init(void) { unsigned long size; u_int h_sync, v_sync; + int rc, i; acornfb_init_fbinfo(); @@ -1934,6 +1556,26 @@ acornfb_init(void) fb_info.monspecs = monspecs[current_par.montype]; fb_info.monspecs.dpms = current_par.dpms; + /* + * Try to select a suitable default mode + */ + for (i = 0; i < sizeof(modedb) / sizeof(*modedb); i++) { + unsigned long hs; + + hs = modedb[i].refresh * + (modedb[i].yres + modedb[i].upper_margin + + modedb[i].lower_margin + modedb[i].vsync_len); + if (modedb[i].xres == DEFAULT_XRES && + modedb[i].yres == DEFAULT_YRES && + modedb[i].refresh >= fb_info.monspecs.vfmin && + modedb[i].refresh <= fb_info.monspecs.vfmax && + hs >= fb_info.monspecs.hfmin && + hs <= fb_info.monspecs.hfmax) { + acornfb_default_mode = modedb[i]; + break; + } + } + current_par.currcon = -1; current_par.screen_base = SCREEN2_BASE; current_par.screen_base_p = SCREEN_START; @@ -1972,7 +1614,7 @@ acornfb_init(void) if (current_par.screen_base == 0) { printk(KERN_ERR "acornfb: unable to allocate screen " "memory\n"); - return; + return -ENOMEM; } top = current_par.screen_base + (PAGE_SIZE * (1 << order)); /* Mark the framebuffer pages as reserved so mmap will work. */ @@ -2010,8 +1652,14 @@ acornfb_init(void) * find it, then we can't restore it if we change * the resolution, so we disable this feature. */ - if (acornfb_lookup_timing(&init_var)) - current_par.allow_modeset = 0; + rc = fb_find_mode(&init_var, &fb_info, NULL, modedb, + sizeof(modedb) / sizeof(*modedb), + &acornfb_default_mode, DEFAULT_BPP); + + if (!rc && fb_find_mode(&init_var, &fb_info, NULL, NULL, 0, + &acornfb_default_mode, DEFAULT_BPP)) { + printk("Acornfb: no valid mode found\n"); + } /* * Again, if this does not succeed, then we disallow diff --git a/drivers/video/acornfb.h b/drivers/video/acornfb.h new file mode 100644 index 000000000..fdd7d1b02 --- /dev/null +++ b/drivers/video/acornfb.h @@ -0,0 +1,200 @@ +/* + * linux/drivers/video/acornfb.h + * + * Copyright (C) 1998,1999 Russell King + * + * Frame buffer code for Acorn platforms + */ +#if defined(HAS_VIDC20) +#include <asm/iomd.h> +#define VIDC_PALETTE_SIZE 256 +#define VIDC_NAME "VIDC20" +#elif defined(HAS_VIDC) +#include <asm/memc.h> +#define VIDC_PALETTE_SIZE 16 +#define VIDC_NAME "VIDC" +#endif + +#define EXTEND8(x) ((x)|(x)<<8) +#define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12) + +struct vidc20_palette { + u_int red:8; + u_int green:8; + u_int blue:8; + u_int ext:4; + u_int unused:4; +}; + +struct vidc_palette { + u_int red:4; + u_int green:4; + u_int blue:4; + u_int trans:1; + u_int sbz1:13; + u_int reg:4; + u_int sbz2:2; +}; + +union palette { + struct vidc20_palette vidc20; + struct vidc_palette vidc; + u_int p; +}; + +struct acornfb_par { + unsigned long screen_base; + unsigned long screen_base_p; + unsigned long screen_end; + unsigned long screen_size; + unsigned int dram_size; + unsigned int vram_half_sam; + unsigned int palette_size; + signed int montype; + signed int currcon; + unsigned int allow_modeset : 1; + unsigned int using_vram : 1; + unsigned int dpms : 1; + + union palette palette[VIDC_PALETTE_SIZE]; + + union { + unsigned short cfb16[16]; + unsigned long cfb32[16]; + } cmap; +}; + +struct vidc_timing { + u_int h_cycle; + u_int h_sync_width; + u_int h_border_start; + u_int h_display_start; + u_int h_display_end; + u_int h_border_end; + u_int h_interlace; + + u_int v_cycle; + u_int v_sync_width; + u_int v_border_start; + u_int v_display_start; + u_int v_display_end; + u_int v_border_end; + + u_int control; + + /* VIDC20 only */ + u_int pll_ctl; +}; + +struct modey_params { + u_int y_res; + u_int u_margin; + u_int b_margin; + u_int vsync_len; + u_int vf; +}; + +struct modex_params { + u_int x_res; + u_int l_margin; + u_int r_margin; + u_int hsync_len; + u_int clock; + u_int hf; + const struct modey_params *modey; +}; + +#ifdef HAS_VIDC + +#define VID_CTL_VS_NVSYNC (1 << 3) +#define VID_CTL_HS_NHSYNC (1 << 2) +#define VID_CTL_24MHz (0) +#define VID_CTL_25MHz (1) +#define VID_CTL_36MHz (2) + +#define VIDC_CTRL_INTERLACE (1 << 6) +#define VIDC_CTRL_FIFO_0_4 (0 << 4) +#define VIDC_CTRL_FIFO_1_5 (1 << 4) +#define VIDC_CTRL_FIFO_2_6 (2 << 4) +#define VIDC_CTRL_FIFO_3_7 (3 << 4) +#define VIDC_CTRL_1BPP (0 << 2) +#define VIDC_CTRL_2BPP (1 << 2) +#define VIDC_CTRL_4BPP (2 << 2) +#define VIDC_CTRL_8BPP (3 << 2) +#define VIDC_CTRL_DIV3 (0 << 0) +#define VIDC_CTRL_DIV2 (1 << 0) +#define VIDC_CTRL_DIV1_5 (2 << 0) +#define VIDC_CTRL_DIV1 (3 << 0) + +#endif + +#ifdef HAS_VIDC20 +/* + * VIDC20 registers + */ +#define VIDC20_CTRL 0xe0000000 +#define VIDC20_CTRL_PIX_VCLK (0 << 0) +#define VIDC20_CTRL_PIX_HCLK (1 << 0) +#define VIDC20_CTRL_PIX_RCLK (2 << 0) +#define VIDC20_CTRL_PIX_CK (0 << 2) +#define VIDC20_CTRL_PIX_CK2 (1 << 2) +#define VIDC20_CTRL_PIX_CK3 (2 << 2) +#define VIDC20_CTRL_PIX_CK4 (3 << 2) +#define VIDC20_CTRL_PIX_CK5 (4 << 2) +#define VIDC20_CTRL_PIX_CK6 (5 << 2) +#define VIDC20_CTRL_PIX_CK7 (6 << 2) +#define VIDC20_CTRL_PIX_CK8 (7 << 2) +#define VIDC20_CTRL_1BPP (0 << 5) +#define VIDC20_CTRL_2BPP (1 << 5) +#define VIDC20_CTRL_4BPP (2 << 5) +#define VIDC20_CTRL_8BPP (3 << 5) +#define VIDC20_CTRL_16BPP (4 << 5) +#define VIDC20_CTRL_32BPP (6 << 5) +#define VIDC20_CTRL_FIFO_NS (0 << 8) +#define VIDC20_CTRL_FIFO_4 (1 << 8) +#define VIDC20_CTRL_FIFO_8 (2 << 8) +#define VIDC20_CTRL_FIFO_12 (3 << 8) +#define VIDC20_CTRL_FIFO_16 (4 << 8) +#define VIDC20_CTRL_FIFO_20 (5 << 8) +#define VIDC20_CTRL_FIFO_24 (6 << 8) +#define VIDC20_CTRL_FIFO_28 (7 << 8) +#define VIDC20_CTRL_INT (1 << 12) +#define VIDC20_CTRL_DUP (1 << 13) +#define VIDC20_CTRL_PDOWN (1 << 14) + +#define VIDC20_ECTL 0xc0000000 +#define VIDC20_ECTL_REG(x) ((x) & 0xf3) +#define VIDC20_ECTL_ECK (1 << 2) +#define VIDC20_ECTL_REDPED (1 << 8) +#define VIDC20_ECTL_GREENPED (1 << 9) +#define VIDC20_ECTL_BLUEPED (1 << 10) +#define VIDC20_ECTL_DAC (1 << 12) +#define VIDC20_ECTL_LCDGS (1 << 13) +#define VIDC20_ECTL_HRM (1 << 14) + +#define VIDC20_ECTL_HS_MASK (3 << 16) +#define VIDC20_ECTL_HS_HSYNC (0 << 16) +#define VIDC20_ECTL_HS_NHSYNC (1 << 16) +#define VIDC20_ECTL_HS_CSYNC (2 << 16) +#define VIDC20_ECTL_HS_NCSYNC (3 << 16) + +#define VIDC20_ECTL_VS_MASK (3 << 18) +#define VIDC20_ECTL_VS_VSYNC (0 << 18) +#define VIDC20_ECTL_VS_NVSYNC (1 << 18) +#define VIDC20_ECTL_VS_CSYNC (2 << 18) +#define VIDC20_ECTL_VS_NCSYNC (3 << 18) + +#define VIDC20_DCTL 0xf0000000 +/* 0-9 = number of words in scanline */ +#define VIDC20_DCTL_SNA (1 << 12) +#define VIDC20_DCTL_HDIS (1 << 13) +#define VIDC20_DCTL_BUS_NS (0 << 16) +#define VIDC20_DCTL_BUS_D31_0 (1 << 16) +#define VIDC20_DCTL_BUS_D63_32 (2 << 16) +#define VIDC20_DCTL_BUS_D63_0 (3 << 16) +#define VIDC20_DCTL_VRAM_DIS (0 << 18) +#define VIDC20_DCTL_VRAM_PXCLK (1 << 18) +#define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18) +#define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18) + +#endif diff --git a/drivers/video/atafb.c b/drivers/video/atafb.c index 8f163cd8c..51d1cb05e 100644 --- a/drivers/video/atafb.c +++ b/drivers/video/atafb.c @@ -464,7 +464,7 @@ static int tt_encode_fix( struct fb_fix_screeninfo *fix, int mode; strcpy(fix->id,"Atari Builtin"); - fix->smem_start = real_screen_base; + fix->smem_start = (unsigned long)real_screen_base; fix->smem_len = screen_len; fix->type=FB_TYPE_INTERLEAVED_PLANES; fix->type_aux=2; @@ -797,7 +797,7 @@ static int falcon_encode_fix( struct fb_fix_screeninfo *fix, struct atafb_par *par ) { strcpy(fix->id, "Atari Builtin"); - fix->smem_start = real_screen_base; + fix->smem_start = (unsigned long)real_screen_base; fix->smem_len = screen_len; fix->type = FB_TYPE_INTERLEAVED_PLANES; fix->type_aux = 2; @@ -1760,7 +1760,7 @@ static int stste_encode_fix( struct fb_fix_screeninfo *fix, int mode; strcpy(fix->id,"Atari Builtin"); - fix->smem_start = real_screen_base; + fix->smem_start = (unsigned long)real_screen_base; fix->smem_len = screen_len; fix->type = FB_TYPE_INTERLEAVED_PLANES; fix->type_aux = 2; @@ -2104,7 +2104,7 @@ static int ext_encode_fix( struct fb_fix_screeninfo *fix, { strcpy(fix->id,"Unknown Extern"); - fix->smem_start=external_addr; + fix->smem_start = (unsigned long)external_addr; fix->smem_len = PAGE_ALIGN(external_len); if (external_depth == 1) { fix->type = FB_TYPE_PACKED_PIXELS; @@ -2488,7 +2488,7 @@ atafb_set_disp(int con, struct fb_info *info) atafb_get_var(&var, con, info); if (con == -1) con=0; - display->screen_base = fix.smem_start; + display->screen_base = (void *)fix.smem_start; display->visual = fix.visual; display->type = fix.type; display->type_aux = fix.type_aux; diff --git a/drivers/video/atyfb.c b/drivers/video/atyfb.c index db21bfc6b..b6163def3 100644 --- a/drivers/video/atyfb.c +++ b/drivers/video/atyfb.c @@ -3048,21 +3048,26 @@ static int atyfb_mmap(struct fb_info *info, struct file *file, struct fb_info_aty *fb = (struct fb_info_aty *)info; unsigned int size, page, map_size = 0; unsigned long map_offset = 0; + unsigned long off; int i; if (!fb->mmap_map) return -ENXIO; + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) + return -EINVAL; + + off = vma->vm_pgoff << PAGE_SHIFT; size = vma->vm_end - vma->vm_start; - if (vma->vm_offset & ~PAGE_MASK) - return -ENXIO; /* To stop the swapper from even considering these pages. */ vma->vm_flags |= (VM_SHM | VM_LOCKED); - if (((vma->vm_offset == 0) && (size == fb->total_vram)) || - ((vma->vm_offset == fb->total_vram) && (size == PAGE_SIZE))) - vma->vm_offset += 0x8000000000000000UL; + if (((vma->vm_pgoff == 0) && (size == fb->total_vram)) || + ((off == fb->total_vram) && (size == PAGE_SIZE))) + off += 0x8000000000000000UL; + + vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */ #ifdef __sparc_v9__ /* Align it as much as desirable */ @@ -3070,9 +3075,9 @@ static int atyfb_mmap(struct fb_info *info, struct file *file, unsigned long j, align; int max = -1; - map_offset = vma->vm_offset+size; + map_offset = off + size; for (i = 0; fb->mmap_map[i].size; i++) { - if (fb->mmap_map[i].voff < vma->vm_offset) + if (fb->mmap_map[i].voff < off) continue; if (fb->mmap_map[i].voff >= map_offset) break; @@ -3092,7 +3097,7 @@ static int atyfb_mmap(struct fb_info *info, struct file *file, j = align; align = j - ((vma->vm_start + fb->mmap_map[max].voff - - vma->vm_offset) & (j - 1)); + - off) & (j - 1)); if (align != j) { struct vm_area_struct *vmm; @@ -3115,7 +3120,7 @@ static int atyfb_mmap(struct fb_info *info, struct file *file, for (i = 0; fb->mmap_map[i].size; i++) { unsigned long start = fb->mmap_map[i].voff; unsigned long end = start + fb->mmap_map[i].size; - unsigned long offset = vma->vm_offset + page; + unsigned long offset = off + page; if (start > offset) continue; diff --git a/drivers/video/clgenfb.c b/drivers/video/clgenfb.c index 23e0f64dc..48e27945b 100644 --- a/drivers/video/clgenfb.c +++ b/drivers/video/clgenfb.c @@ -2476,7 +2476,7 @@ static void __init get_of_addrs (const struct device_node *dp, for (i = 0; i < dp->n_addrs; ++i) { unsigned long addr = dp->addrs[i].address; unsigned long size = dp->addrs[i].size; - printk ("dp->addrs[%d].address = $lx, dp->addrs[%d].size = %lx\n", + printk ("dp->addrs[%d].address = %lx, dp->addrs[%d].size = %lx\n", i, addr, i, size); if (size >= 0x800000) { *display = addr; diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c index cedb41c2a..5568355a7 100644 --- a/drivers/video/cyber2000fb.c +++ b/drivers/video/cyber2000fb.c @@ -35,7 +35,9 @@ #define DEFAULT_YRES 480 #define DEFAULT_BPP 8 -static volatile unsigned char *CyberRegs; +#define MMIO_SIZE 0x000c0000 + +static char *CyberRegs; #include "cyber2000fb.h" @@ -45,7 +47,7 @@ static struct cyber2000fb_par current_par; static struct display_switch *dispsw; static struct fb_var_screeninfo __initdata init_var = {}; -#ifdef DEBUG +#if defined(DEBUG) && defined(CONFIG_DEBUG_LL) static void debug_printf(char *fmt, ...) { char buffer[128]; @@ -61,168 +63,6 @@ static void debug_printf(char *fmt, ...) #define debug_printf(x...) do { } while (0) #endif -/* - * Predefined Video Modes - */ -static const struct res cyber2000_res[] = { - { - 640, 480, - { - 0x5f, 0x4f, 0x50, 0x80, 0x52, 0x9d, 0x0b, 0x3e, - 0x00, 0x40, - 0xe9, 0x8b, 0xdf, 0x50, 0x00, 0xe6, 0x04, 0xc3 - }, - 0x00, - { 0xd2, 0xce, 0xdb, 0x54 } - }, - - { - 800, 600, - { - 0x7f, 0x63, 0x64, 0x00, 0x66, 0x10, 0x6f, 0xf0, - 0x00, 0x60, - 0x5b, 0x8f, 0x57, 0x64, 0x00, 0x59, 0x6e, 0xe3 - }, - 0x00, - { 0x52, 0x85, 0xdb, 0x54 } - }, - - { - 1024, 768, - { - 0x9f, 0x7f, 0x80, 0x80, 0x8b, 0x94, 0x1e, 0xfd, - 0x00, 0x60, - 0x03, 0x86, 0xff, 0x80, 0x0f, 0x00, 0x1e, 0xe3 - }, - 0x00, - { 0xd0, 0x52, 0xdb, 0x54 } - }, -#if 0 - { - 1152, 886, - { - }, - { - } - }, -#endif - { - 1280, 1024, - { - 0xce, 0x9f, 0xa0, 0x8f, 0xa2, 0x1f, 0x28, 0x52, - 0x00, 0x40, - 0x08, 0x8f, 0xff, 0xa0, 0x00, 0x03, 0x27, 0xe3 - }, - 0x1d, - { 0xb4, 0x4b, 0xdb, 0x54 } - }, - - { - 1600, 1200, - { - 0xff, 0xc7, 0xc9, 0x9f, 0xcf, 0xa0, 0xfe, 0x10, - 0x00, 0x40, - 0xcf, 0x89, 0xaf, 0xc8, 0x00, 0xbc, 0xf1, 0xe3 - }, - 0x1f, - { 0xbd, 0x10, 0xdb, 0x54 } - } -}; - -#define NUM_TOTAL_MODES arraysize(cyber2000_res) - -static const char igs_regs[] = { - 0x10, 0x10, 0x12, 0x00, 0x13, 0x00, - 0x30, 0x21, 0x31, 0x00, 0x32, 0x00, 0x33, 0x01, - 0x50, 0x00, 0x51, 0x00, 0x52, 0x00, 0x53, 0x00, - 0x54, 0x00, 0x55, 0x00, 0x56, 0x00, 0x57, 0x01, - 0x58, 0x00, 0x59, 0x00, 0x5a, 0x00, - 0x70, 0x0b, 0x71, 0x10, 0x72, 0x45, 0x73, 0x30, - 0x74, 0x1b, 0x75, 0x1e, 0x76, 0x00, 0x7a, 0xc8 -}; - -static const char crtc_idx[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 -}; - -static void cyber2000_init_hw(const struct res *res) -{ - int i; - - debug_printf("init vga hw for %dx%d\n", res->xres, res->yres); - - cyber2000_outb(0xef, 0x3c2); - cyber2000_crtcw(0x11, 0x0b); - cyber2000_attrw(0x11, 0x00); - - cyber2000_seqw(0x00, 0x01); - cyber2000_seqw(0x01, 0x01); - cyber2000_seqw(0x02, 0x0f); - cyber2000_seqw(0x03, 0x00); - cyber2000_seqw(0x04, 0x0e); - cyber2000_seqw(0x00, 0x03); - - for (i = 0; i < sizeof(crtc_idx); i++) - cyber2000_crtcw(crtc_idx[i], res->crtc_regs[i]); - - for (i = 0x0a; i < 0x10; i++) - cyber2000_crtcw(i, 0); - - cyber2000_crtcw(0x18, 0xff); - - cyber2000_grphw(0x00, 0x00); - cyber2000_grphw(0x01, 0x00); - cyber2000_grphw(0x02, 0x00); - cyber2000_grphw(0x03, 0x00); - cyber2000_grphw(0x04, 0x00); - cyber2000_grphw(0x05, 0x60); - cyber2000_grphw(0x06, 0x05); - cyber2000_grphw(0x07, 0x0f); - cyber2000_grphw(0x08, 0xff); - - for (i = 0; i < 16; i++) - cyber2000_attrw(i, i); - - cyber2000_attrw(0x10, 0x01); - cyber2000_attrw(0x11, 0x00); - cyber2000_attrw(0x12, 0x0f); - cyber2000_attrw(0x13, 0x00); - cyber2000_attrw(0x14, 0x00); - - for (i = 0; i < sizeof(igs_regs); i += 2) - cyber2000_grphw(igs_regs[i], igs_regs[i+1]); - - cyber2000_grphw(0x11, res->crtc_ofl); - - for (i = 0; i < 4; i += 1) - cyber2000_grphw(0xb0 + i, res->clk_regs[i]); - - cyber2000_grphw(0x90, 0x01); - cyber2000_grphw(0xb9, 0x80); - cyber2000_grphw(0xb9, 0x00); - - cyber2000_outb(0x56, 0x3ce); - i = cyber2000_inb(0x3cf); - cyber2000_outb(i | 4, 0x3cf); - cyber2000_outb(0x04, 0x3c6); - cyber2000_outb(i, 0x3cf); - - cyber2000_outb(0x20, 0x3c0); - cyber2000_outb(0xff, 0x3c6); - - for (i = 0; i < 256; i++) { - cyber2000_outb(i, 0x3c8); - cyber2000_outb(0, 0x3c9); - cyber2000_outb(0, 0x3c9); - cyber2000_outb(0, 0x3c9); - } -} - - -static struct fb_ops cyber2000fb_ops; - /* -------------------- Hardware specific routines ------------------------- */ /* @@ -232,10 +72,10 @@ static void cyber2000_accel_wait(void) { int count = 10000; - while (cyber2000_inb(0xbf011) & 0x80) { + while (cyber2000_inb(CO_REG_CONTROL) & 0x80) { if (!count--) { debug_printf("accel_wait timed out\n"); - cyber2000_outb(0, 0xbf011); + cyber2000_outb(0, CO_REG_CONTROL); return; } udelay(10); @@ -252,45 +92,54 @@ static void cyber2000_accel_bmove(struct display *p, int sy, int sx, int dy, int dx, int height, int width) { - unsigned long src, dst, chwidth = p->var.xres_virtual * fontheight(p); - int v = 0x8000; + unsigned long src, dst; + unsigned int fh, fw; + int cmd = CO_CMD_L_PATTERN_FGCOL; + + fw = fontwidth(p); + sx *= fw; + dx *= fw; + width *= fw; + width -= 1; if (sx < dx) { - sx += width - 1; - dx += width - 1; - v |= 4; + sx += width; + dx += width; + cmd |= CO_CMD_L_INC_LEFT; } + fh = fontheight(p); + sy *= fh; + dy *= fh; + height *= fh; + height -= 1; + if (sy < dy) { - sy += height - 1; - dy += height - 1; - v |= 2; + sy += height; + dy += height; + cmd |= CO_CMD_L_INC_UP; } - sx *= fontwidth(p); - dx *= fontwidth(p); - src = sx + sy * chwidth; - dst = dx + dy * chwidth; - width = width * fontwidth(p) - 1; - height = height * fontheight(p) - 1; + src = sx + sy * p->var.xres_virtual; + dst = dx + dy * p->var.xres_virtual; cyber2000_accel_wait(); - cyber2000_outb(0x00, 0xbf011); - cyber2000_outb(0x03, 0xbf048); - cyber2000_outw(width, 0xbf060); + cyber2000_outb(0x00, CO_REG_CONTROL); + cyber2000_outb(0x03, CO_REG_FORE_MIX); + cyber2000_outw(width, CO_REG_WIDTH); if (p->var.bits_per_pixel != 24) { - cyber2000_outl(dst, 0xbf178); - cyber2000_outl(src, 0xbf170); + cyber2000_outl(dst, CO_REG_DEST_PTR); + cyber2000_outl(src, CO_REG_SRC_PTR); } else { - cyber2000_outl(dst * 3, 0xbf178); - cyber2000_outb(dst, 0xbf078); - cyber2000_outl(src * 3, 0xbf170); + cyber2000_outl(dst * 3, CO_REG_DEST_PTR); + cyber2000_outb(dst, CO_REG_X_PHASE); + cyber2000_outl(src * 3, CO_REG_SRC_PTR); } - cyber2000_outw(height, 0xbf062); - cyber2000_outw(v, 0xbf07c); - cyber2000_outw(0x2800, 0xbf07e); + cyber2000_outw(height, CO_REG_HEIGHT); + cyber2000_outw(cmd, CO_REG_CMD_L); + cyber2000_outw(0x2800, CO_REG_CMD_H); } static void @@ -298,36 +147,40 @@ cyber2000_accel_clear(struct vc_data *conp, struct display *p, int sy, int sx, int height, int width) { unsigned long dst; + unsigned int fw, fh; u32 bgx = attr_bgcol_ec(p, conp); - dst = sx * fontwidth(p) + sy * p->var.xres_virtual * fontheight(p); - width = width * fontwidth(p) - 1; - height = height * fontheight(p) - 1; + fw = fontwidth(p); + fh = fontheight(p); + + dst = sx * fw + sy * p->var.xres_virtual * fh; + width = width * fw - 1; + height = height * fh - 1; cyber2000_accel_wait(); - cyber2000_outb(0x00, 0xbf011); - cyber2000_outb(0x03, 0xbf048); - cyber2000_outw(width, 0xbf060); - cyber2000_outw(height, 0xbf062); + cyber2000_outb(0x00, CO_REG_CONTROL); + cyber2000_outb(0x03, CO_REG_FORE_MIX); + cyber2000_outw(width, CO_REG_WIDTH); + cyber2000_outw(height, CO_REG_HEIGHT); switch (p->var.bits_per_pixel) { case 15: case 16: bgx = ((u16 *)p->dispsw_data)[bgx]; case 8: - cyber2000_outl(dst, 0xbf178); + cyber2000_outl(dst, CO_REG_DEST_PTR); break; case 24: - cyber2000_outl(dst * 3, 0xbf178); - cyber2000_outb(dst, 0xbf078); + cyber2000_outl(dst * 3, CO_REG_DEST_PTR); + cyber2000_outb(dst, CO_REG_X_PHASE); bgx = ((u32 *)p->dispsw_data)[bgx]; break; } - cyber2000_outl(bgx, 0xbf058); - cyber2000_outw(0x8000, 0xbf07c); - cyber2000_outw(0x0800, 0xbf07e); + cyber2000_outl(bgx, CO_REG_FOREGROUND); + cyber2000_outw(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L); + cyber2000_outw(0x0800, CO_REG_CMD_H); } static void @@ -478,183 +331,136 @@ cyber2000_setcolreg(u_int regno, u_int red, u_int green, u_int blue, return 0; } -static void cyber2000fb_calculate_timing(unsigned char *v, struct fb_var_screeninfo *var) -{ - int Htotal, Hdispend, Hblankstart, Hblankend, Hsyncstart, Hsyncend; - int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; -#define BIT(v,b1,m,b2) (((v >> b1) & m) << b2) - - Hdispend = var->xres; - Hsyncstart = var->xres + var->right_margin; - Hsyncend = var->xres + var->right_margin + var->hsync_len; - Htotal = var->xres + var->right_margin + var->hsync_len + var->left_margin; - - Hblankstart = var->xres; - Hblankend = Htotal - 4*8; +struct par_info { + /* + * Hardware + */ + unsigned char clock_mult; + unsigned char clock_div; + unsigned char visualid; + unsigned char pixformat; + unsigned char crtc_ofl; + unsigned char crtc[19]; + unsigned int width; + unsigned int pitch; - Vdispend = var->yres; - Vsyncstart = var->yres + var->lower_margin; - Vsyncend = var->yres + var->lower_margin + var->vsync_len; - Vtotal = var->yres + var->lower_margin + var->vsync_len + var->upper_margin; - - Vblankstart = var->yres + 7; - Vblankend = Vtotal - 11; - - Hdispend >>= 3; - Hsyncstart >>= 3; - Hsyncend >>= 3; - Htotal >>= 3; - Hblankstart >>= 3; - Hblankend >>= 3; - - Htotal -= 5; - Hdispend -= 1; - Vtotal -= 2; - Vdispend -= 1; - Vblankstart -= 1; - Vblankend -= 1; - - v[0] = Htotal; - v[1] = Hdispend; - v[2] = Hblankstart; - v[3] = BIT(Hblankend, 0, 0x1f, 0) | - BIT(1, 0, 0x01, 7); - v[4] = Hsyncstart; - v[5] = BIT(Hsyncend, 0, 0x1f, 0) | - BIT(Hblankend, 5, 0x01, 7); - - v[6] = Vtotal; - v[7] = BIT(Vtotal, 8, 0x01, 0) | - BIT(Vdispend, 8, 0x01, 1) | - BIT(Vsyncstart, 8, 0x01, 2) | - BIT(Vblankstart,8, 0x01, 3) | - BIT(1, 0, 0x01, 4) | - BIT(Vtotal, 9, 0x01, 5) | - BIT(Vdispend, 9, 0x01, 6) | - BIT(Vsyncstart, 9, 0x01, 7); - v[8] = 0; - v[9] = BIT(0, 0, 0x1f, 0) | - BIT(Vblankstart,9, 0x01, 5) | - BIT(1, 0, 0x01, 6); - v[10] = Vsyncstart; - v[11] = BIT(Vsyncend, 0, 0x0f, 0) | - BIT(1, 0, 0x01, 7); - v[12] = Vdispend; - v[14] = 0; - v[15] = Vblankstart; - v[16] = Vblankend; - v[17] = 0xe3; + /* + * Other + */ + unsigned int visual; +}; - /* overflow - graphics reg 0x11 */ - v[18] = BIT(Vtotal, 10, 0x01, 0) | /* guess */ - BIT(Vdispend, 10, 0x01, 1) | - BIT(Vsyncstart, 10, 0x01, 2) | /* guess */ - BIT(Vblankstart,10, 0x01, 3) | /* guess */ - BIT(Hblankend, 6, 0x01, 4); /* guess */ -} +static const char crtc_idx[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18 +}; -static void cyber2000fb_set_timing(struct fb_var_screeninfo *var) +static void cyber2000fb_set_timing(struct par_info *hw) { - unsigned int width = var->xres_virtual; - unsigned int scr_pitch, fetchrow, i; - char b, graph_r77, crtc[32]; + unsigned int fetchrow, i; - switch (var->bits_per_pixel) { - case 8: /* PSEUDOCOLOUR, 256 */ - b = 0; - graph_r77 = 1; - scr_pitch = width; - break; + /* + * Blank palette + */ + for (i = 0; i < 256; i++) { + cyber2000_outb(i, 0x3c8); + cyber2000_outb(0, 0x3c9); + cyber2000_outb(0, 0x3c9); + cyber2000_outb(0, 0x3c9); + } - case 15:/* DIRECTCOLOUR, 32k */ - b = 1; - graph_r77 = 6; - scr_pitch = width * 2; - break; + cyber2000_outb(0xef, 0x3c2); + cyber2000_crtcw(0x11, 0x0b); + cyber2000_attrw(0x11, 0x00); - case 16:/* DIRECTCOLOUR, 64k */ - b = 1; - graph_r77 = 2; - scr_pitch = width * 2; - break; + cyber2000_seqw(0x00, 0x01); + cyber2000_seqw(0x01, 0x01); + cyber2000_seqw(0x02, 0x0f); + cyber2000_seqw(0x03, 0x00); + cyber2000_seqw(0x04, 0x0e); + cyber2000_seqw(0x00, 0x03); - case 24:/* TRUECOLOUR, 16m */ - b = 2; - graph_r77 = 4; - width *= 3; - scr_pitch = width; - break; + for (i = 0; i < sizeof(crtc_idx); i++) + cyber2000_crtcw(crtc_idx[i], hw->crtc[i]); - default: - return; - } + for (i = 0x0a; i < 0x10; i++) + cyber2000_crtcw(i, 0); - width -= 1; - scr_pitch >>= 3; - fetchrow = scr_pitch + 1; + cyber2000_grphw(0x11, hw->crtc_ofl); + cyber2000_grphw(0x00, 0x00); + cyber2000_grphw(0x01, 0x00); + cyber2000_grphw(0x02, 0x00); + cyber2000_grphw(0x03, 0x00); + cyber2000_grphw(0x04, 0x00); + cyber2000_grphw(0x05, 0x60); + cyber2000_grphw(0x06, 0x05); + cyber2000_grphw(0x07, 0x0f); + cyber2000_grphw(0x08, 0xff); - cyber2000fb_calculate_timing(crtc, var); + /* Attribute controller registers */ + for (i = 0; i < 16; i++) + cyber2000_attrw(i, i); - for (i = 0; i < NUM_TOTAL_MODES; i++) - if (var->xres == cyber2000_res[i].xres && - var->yres == cyber2000_res[i].yres) - break; + cyber2000_attrw(0x10, 0x01); + cyber2000_attrw(0x11, 0x00); + cyber2000_attrw(0x12, 0x0f); + cyber2000_attrw(0x13, 0x00); + cyber2000_attrw(0x14, 0x00); - if (i < NUM_TOTAL_MODES) - cyber2000_init_hw(cyber2000_res + i); + /* PLL registers */ + cyber2000_grphw(0xb0, hw->clock_mult); + cyber2000_grphw(0xb1, hw->clock_div); + cyber2000_grphw(0xb2, 0xdb); + cyber2000_grphw(0xb3, 0x54); /* MCLK: 75MHz */ + cyber2000_grphw(0x90, 0x01); + cyber2000_grphw(0xb9, 0x80); + cyber2000_grphw(0xb9, 0x00); - crtc[13] = scr_pitch; + cyber2000_outb(0x56, 0x3ce); + i = cyber2000_inb(0x3cf); + cyber2000_outb(i | 4, 0x3cf); + cyber2000_outb(0x04, 0x3c6); + cyber2000_outb(i, 0x3cf); - /* - * reprogram the CRTC with the values we calculated - * above. This should be cleaned up once we're - * confident that we're generating the correct - * values. Disable this if you're having problems, - * and report the values obtained from the kernel - * messages. - */ -#if 1 - cyber2000_crtcw(0x11, 0x0b); - for (i = 0; i < sizeof(crtc_idx); i++) - cyber2000_crtcw(crtc_idx[i], crtc[i]); -#else - cyber2000_crtcw(0x13, crtc[13]); -#endif + cyber2000_outb(0x20, 0x3c0); + cyber2000_outb(0xff, 0x3c6); + fetchrow = hw->pitch + 1; cyber2000_grphw(0x14, fetchrow); - /* FIXME: is this the right way round? */ - cyber2000_grphw(0x15, ((fetchrow >> 4) & 0xf0) | ((scr_pitch >> 8) & 0x0f)); - cyber2000_grphw(0x77, graph_r77); + /* FIXME: is this the right way round? */ + cyber2000_grphw(0x15, ((fetchrow >> 4) & 0xf0) | ((hw->pitch >> 8) & 0x0f)); + cyber2000_grphw(0x77, hw->visualid); cyber2000_grphw(0x33, 0x1c); - cyber2000_outw(width, 0xbf018); - cyber2000_outw(width, 0xbf218); - cyber2000_outb(b, 0xbf01c); - -#if 0 -{ int j; i = 0; - printk(KERN_DEBUG); - for (j = 0; j < 19; j++) printk("%2d ", j); printk("\n"KERN_DEBUG); - for (j = 0; j < 19; j++) printk("%02X ", crtc[j]); printk("\n"KERN_DEBUG); - for (j = 0; j < 18; j++) printk("%02X ", cyber2000_res[i].crtc_regs[j]); - printk("%02X\n", cyber2000_res[i].crtc_ofl); -} -#endif + /* + * Set up accelerator registers + */ + cyber2000_outw(hw->width, CO_REG_SRC_WIDTH); + cyber2000_outw(hw->width, CO_REG_DEST_WIDTH); + cyber2000_outb(hw->pixformat, CO_REG_PIX_FORMAT); } -static inline void +static inline int cyber2000fb_update_start(struct fb_var_screeninfo *var) { -#if 0 unsigned int base; base = var->yoffset * var->xres_virtual + var->xoffset; - cyber2000_crtcw(0x0c, base); - cyber2000_crtcw(0x0d, base >> 8); - /* FIXME: need the upper bits of the start offset */ -/* cyber2000_crtcw(0x??, base >> 16);*/ -#endif + base >>= 2; + + if (base >= 1 << 20) + return -EINVAL; + + /* + * FIXME: need the upper bits of the start offset + */ + cyber2000_grphw(0x10, base >> 16 | 0x10); + cyber2000_crtcw(0x0c, base >> 8); + cyber2000_crtcw(0x0d, base); + + return 0; } /* @@ -723,30 +529,230 @@ cyber2000fb_set_cmap(struct fb_cmap *cmap, int kspc, int con, return err; } +static int cyber2000fb_decode_crtc(struct par_info *hw, struct fb_var_screeninfo *var) +{ + unsigned int Htotal, Hblankend, Hsyncend; + unsigned int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; +#define BIT(v,b1,m,b2) (((v >> b1) & m) << b2) + + hw->crtc[13] = hw->pitch; + hw->crtc[17] = 0xe3; + hw->crtc[14] = 0; + hw->crtc[8] = 0; + + Htotal = var->xres + var->right_margin + var->hsync_len + var->left_margin; + if (Htotal > 2080) + return -EINVAL; + + hw->crtc[0] = (Htotal >> 3) - 5; /* Htotal */ + hw->crtc[1] = (var->xres >> 3) - 1; /* Hdispend */ + hw->crtc[2] = var->xres >> 3; /* Hblankstart */ + hw->crtc[4] = (var->xres + var->right_margin) >> 3; /* Hsyncstart */ + + Hblankend = (Htotal - 4*8) >> 3; + + hw->crtc[3] = BIT(Hblankend, 0, 0x1f, 0) | /* Hblankend */ + BIT(1, 0, 0x01, 7); + + Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3; + + hw->crtc[5] = BIT(Hsyncend, 0, 0x1f, 0) | /* Hsyncend */ + BIT(Hblankend, 5, 0x01, 7); + + Vdispend = var->yres - 1; + Vsyncstart = var->yres + var->lower_margin; + Vsyncend = var->yres + var->lower_margin + var->vsync_len; + Vtotal = var->yres + var->lower_margin + var->vsync_len + var->upper_margin - 2; + + if (Vtotal > 2047) + return -EINVAL; + + Vblankstart = var->yres + 6; + Vblankend = Vtotal - 10; + + hw->crtc[6] = Vtotal; + hw->crtc[7] = BIT(Vtotal, 8, 0x01, 0) | + BIT(Vdispend, 8, 0x01, 1) | + BIT(Vsyncstart, 8, 0x01, 2) | + BIT(Vblankstart,8, 0x01, 3) | + BIT(1, 0, 0x01, 4) | + BIT(Vtotal, 9, 0x01, 5) | + BIT(Vdispend, 9, 0x01, 6) | + BIT(Vsyncstart, 9, 0x01, 7); + hw->crtc[9] = BIT(0, 0, 0x1f, 0) | + BIT(Vblankstart,9, 0x01, 5) | + BIT(1, 0, 0x01, 6); + hw->crtc[10] = Vsyncstart; + hw->crtc[11] = BIT(Vsyncend, 0, 0x0f, 0) | + BIT(1, 0, 0x01, 7); + hw->crtc[12] = Vdispend; + hw->crtc[15] = Vblankstart; + hw->crtc[16] = Vblankend; + hw->crtc[18] = 0xff; + + /* overflow - graphics reg 0x11 */ +/* 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10 4=LINECOMP:10 5-IVIDEO 6=FIXCNT */ + hw->crtc_ofl = + BIT(Vtotal, 10, 0x01, 0) | + BIT(Vdispend, 10, 0x01, 1) | + BIT(Vsyncstart, 10, 0x01, 2) | + BIT(Vblankstart,10, 0x01, 3) | + 1 << 4; + + return 0; +} + +/* + * The following was discovered by a good monitor, + * bit twiddling, theorising and but mostly luck. + * Strangely, it looks like everyone elses' PLL! + * + * Clock registers: + * fclock = fpll / div2 + * fpll = fref * mult / div1 + * where: + * fref = 14.318MHz (69842ps) + * mult = reg0xb0.7:0 + * div1 = (reg0xb1.5:0 + 1) + * div2 = 2^(reg0xb1.7:6) + * fpll should be between 150 and 220 MHz + * (6667ps and 4545ps) + */ static int -cyber2000fb_decode_var(struct fb_var_screeninfo *var, int con, int *visual) +cyber2000fb_decode_clock(struct par_info *hw, struct fb_var_screeninfo *var) { + unsigned long pll_ps = var->pixclock; + unsigned long ref_ps = 69842; + int div2, div1, mult; + + /* + * Step 1: + * find div2 such that 150MHz < fpll < 220MHz + * and 0 <= div2 < 4 + */ + for (div2 = 0; div2 < 4; div2++, pll_ps >>= 1) + if (6667 > pll_ps && pll_ps > 4545) + break; + + if (div2 == 4) + return -EINVAL; + +#if 0 + /* + * Step 2: + * Find fpll + * fpll = fref * mult / div1 + * + * Note! This just picks any old values at the moment, + * and as such I don't trust it. It certainly doesn't + * come out with the values below, so the PLL may become + * unstable under some circumstances (you don't want an + * FM dot clock) + */ + for (div1 = 32; div1 > 1; div1 -= 1) { + mult = (ref_ps * div1 + pll_ps / 2) / pll_ps; + if (mult < 256) + break; + } +#else + if (pll_ps == 4630) { /* 216.0, 108.0, 54.00, 27.000 */ + mult = 181; /* 4630 9260 18520 37040 */ + div1 = 12; + } else if (pll_ps == 4965) { /* 201.0, 100.5, 50.25, 25.125 */ + mult = 211; /* 4965 9930 19860 39720 */ + div1 = 15; + } else if (pll_ps == 5050) { /* 198.0, 99.0, 49.50, 24.750 */ + mult = 83; /* 5050 10100 20200 40400 */ + div1 = 6; + } else if (pll_ps == 6349) { /* 158.0, 79.0, 39.50, 19.750 */ + mult = 209; /* 6349 12698 25396 50792 */ + div1 = 19; + } else if (pll_ps == 6422) { /* 156.0, 78.0, 39.00, 19.500 */ + mult = 190; /* 6422 12844 25688 51376 */ + div1 = 17; + } else + return -EINVAL; +#endif + /* + * Step 3: + * combine values + */ + hw->clock_mult = mult - 1; + hw->clock_div = div2 << 6 | (div1 - 1); + + return 0; +} + +/* + * Decode the info required for the hardware. + * This involves the PLL parameters for the dot clock, + * CRTC registers, and accelerator settings. + */ +static int +cyber2000fb_decode_var(struct fb_var_screeninfo *var, int con, struct par_info *hw) +{ + int err; + + hw->width = var->xres_virtual; switch (var->bits_per_pixel) { #ifdef FBCON_HAS_CFB8 - case 8: - *visual = FB_VISUAL_PSEUDOCOLOR; + case 8: /* PSEUDOCOLOUR, 256 */ + hw->visual = FB_VISUAL_PSEUDOCOLOR; + hw->pixformat = PIXFORMAT_8BPP; + hw->visualid = VISUALID_256; + hw->pitch = hw->width >> 3; break; #endif #ifdef FBCON_HAS_CFB16 - case 15: - case 16: - *visual = FB_VISUAL_DIRECTCOLOR; + case 15:/* DIRECTCOLOUR, 32k */ + hw->visual = FB_VISUAL_DIRECTCOLOR; + hw->pixformat = PIXFORMAT_16BPP; + hw->visualid = VISUALID_32K; + hw->pitch = hw->width >> 2; + break; + + case 16:/* DIRECTCOLOUR, 64k */ + hw->visual = FB_VISUAL_DIRECTCOLOR; + hw->pixformat = PIXFORMAT_16BPP; + hw->visualid = VISUALID_64K; + hw->pitch = hw->width >> 2; break; #endif #ifdef FBCON_HAS_CFB24 - case 24: - *visual = FB_VISUAL_TRUECOLOR; + case 24:/* TRUECOLOUR, 16m */ + hw->visual = FB_VISUAL_TRUECOLOR; + hw->pixformat = PIXFORMAT_24BPP; + hw->visualid = VISUALID_16M; + hw->width *= 3; + hw->pitch = hw->width >> 3; break; #endif default: return -EINVAL; } + err = cyber2000fb_decode_clock(hw, var); + if (err) + return err; + + err = cyber2000fb_decode_crtc(hw, var); + if (err) + return err; + + debug_printf("Clock: %02X %02X\n", + hw->clock_mult, hw->clock_div); + { + int i; + + for (i = 0; i < 19; i++) + debug_printf("%2d ", i); + debug_printf("\n"); + for (i = 0; i < 18; i++) + debug_printf("%02X ", hw->crtc[i]); + debug_printf("%02X\n", hw->crtc_ofl); + } + hw->width -= 1; + return 0; } @@ -760,7 +766,7 @@ cyber2000fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct display *display; memset(fix, 0, sizeof(struct fb_fix_screeninfo)); - strcpy(fix->id, "Cyber2000"); + strcpy(fix->id, current_par.dev_name); if (con >= 0) display = fb_display + con; @@ -770,7 +776,7 @@ cyber2000fb_get_fix(struct fb_fix_screeninfo *fix, int con, fix->smem_start = current_par.screen_base_p; fix->smem_len = current_par.screen_size; fix->mmio_start = current_par.regs_base_p; - fix->mmio_len = 0x000c0000; + fix->mmio_len = MMIO_SIZE; fix->type = display->type; fix->type_aux = display->type_aux; fix->xpanstep = 0; @@ -806,14 +812,15 @@ static int cyber2000fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info) { struct display *display; - int err, chgvar = 0, visual; + struct par_info hw; + int err, chgvar = 0; if (con >= 0) display = fb_display + con; else display = &global_disp; - err = cyber2000fb_decode_var(var, con, &visual); + err = cyber2000fb_decode_var(var, con, &hw); if (err) return err; @@ -854,11 +861,11 @@ cyber2000fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info if (var->activate & FB_ACTIVATE_ALL) global_disp.var = display->var; - display->screen_base = (char *)current_par.screen_base; - display->visual = visual; + display->screen_base = current_par.screen_base; + display->visual = hw.visual; display->type = FB_TYPE_PACKED_PIXELS; display->type_aux = 0; - display->ypanstep = 0; + display->ypanstep = 1; display->ywrapstep = 0; display->can_soft_blank = 1; display->inverse = 0; @@ -887,8 +894,8 @@ cyber2000fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info break; #endif default: - printk(KERN_WARNING "cyber2000: no support for %dbpp\n", - display->var.bits_per_pixel); + printk(KERN_WARNING "%s: no support for %dbpp\n", + current_par.dev_name, display->var.bits_per_pixel); dispsw = &fbcon_dummy; break; } @@ -908,7 +915,7 @@ cyber2000fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info struct fb_cmap *cmap; cyber2000fb_update_start(var); - cyber2000fb_set_timing(var); + cyber2000fb_set_timing(&hw); if (display->cmap.len) cmap = &display->cmap; @@ -938,10 +945,9 @@ static int cyber2000fb_pan_display(struct fb_var_screeninfo *var, int con, return -EINVAL; if (y_bottom > fb_display[con].var.yres_virtual) return -EINVAL; -/*disabled until we can update the start address properly */ -return -EINVAL; - cyber2000fb_update_start(var); + if (cyber2000fb_update_start(var)) + return -EINVAL; fb_display[con].var.xoffset = var->xoffset; fb_display[con].var.yoffset = var->yoffset; @@ -970,9 +976,12 @@ static int cyber2000fb_ioctl(struct inode *inode, struct file *file, static int cyber2000fb_updatevar(int con, struct fb_info *info) { + int ret = 0; + if (con == current_par.currcon) - cyber2000fb_update_start(&fb_display[con].var); - return 0; + ret = cyber2000fb_update_start(&fb_display[con].var); + + return ret; } static int @@ -1020,11 +1029,6 @@ static void cyber2000fb_blank(int blank, struct fb_info *fb_info) } } -int __init cyber2000fb_setup(char *options) -{ - return 0; -} - static struct fb_ops cyber2000fb_ops = { cyber2000fb_open, @@ -1038,6 +1042,27 @@ static struct fb_ops cyber2000fb_ops = cyber2000fb_ioctl }; +/* + * These parameters give + * 640x480, hsync 31.5kHz, vsync 60Hz + */ +static struct fb_videomode __initdata +cyber2000fb_default_mode = { + name: NULL, + refresh: 60, + xres: 640, + yres: 480, + pixclock: 39722, + left_margin: 56, + right_margin: 16, + upper_margin: 34, + lower_margin: 9, + hsync_len: 88, + vsync_len: 2, + sync: FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + vmode: FB_VMODE_NONINTERLACED +}; + static void __init cyber2000fb_init_fbinfo(void) { @@ -1063,23 +1088,6 @@ cyber2000fb_init_fbinfo(void) * setup initial parameters */ memset(&init_var, 0, sizeof(init_var)); - init_var.xres_virtual = - init_var.xres = DEFAULT_XRES; - init_var.yres_virtual = - init_var.yres = DEFAULT_YRES; - init_var.bits_per_pixel = DEFAULT_BPP; - - /* - * These parameters give - * 640x480, hsync 31.5kHz, vsync 60Hz - */ - init_var.left_margin = 56; - init_var.right_margin = 16; - init_var.upper_margin = 34; - init_var.lower_margin = 9; - init_var.hsync_len = 88; - init_var.vsync_len = 2; - init_var.pixclock = 39722; init_var.red.msb_right = 0; init_var.green.msb_right = 0; @@ -1134,8 +1142,81 @@ cyber2000fb_init_fbinfo(void) init_var.height = -1; init_var.width = -1; init_var.accel_flags = FB_ACCELF_TEXT; - init_var.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT; - init_var.vmode = FB_VMODE_NONINTERLACED; +} + +/* + * Cyber2000 options: + * + * font:fontname + * Set the fontname + * + * res:XxY + * Set the default display resolution + */ +static void __init +cyber2000fb_parse_font(char *opt) +{ + strcpy(fb_info.fontname, opt); +} + +static struct options { + char *name; + void (*parse)(char *opt); +} opt_table[] __initdata = { + { "font", cyber2000fb_parse_font }, + { NULL, NULL } +}; + +int __init +cyber2000fb_setup(char *options) +{ + struct options *optp; + char *opt; + + if (!options || !*options) + return 0; + + cyber2000fb_init_fbinfo(); + + for (opt = strtok(options, ","); opt; opt = strtok(NULL, ",")) { + if (!*opt) + continue; + + for (optp = opt_table; optp->name; optp++) { + int optlen; + + optlen = strlen(optp->name); + + if (strncmp(opt, optp->name, optlen) == 0 && + opt[optlen] == ':') { + optp->parse(opt + optlen + 1); + break; + } + } + + if (!optp->name) + printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", + opt); + } + return 0; +} + +static char igs_regs[] __initdata = { + 0x10, 0x10, 0x12, 0x00, 0x13, 0x00, +/* 0x30, 0x21,*/ 0x31, 0x00, 0x32, 0x00, 0x33, 0x01, + 0x50, 0x00, 0x51, 0x00, 0x52, 0x00, 0x53, 0x00, + 0x54, 0x00, 0x55, 0x00, 0x56, 0x00, 0x57, 0x01, + 0x58, 0x00, 0x59, 0x00, 0x5a, 0x00, + 0x70, 0x0b,/* 0x71, 0x10, 0x72, 0x45,*/ 0x73, 0x30, + 0x74, 0x1b, 0x75, 0x1e, 0x76, 0x00, 0x7a, 0xc8 +}; + +static void __init cyber2000fb_hw_init(void) +{ + int i; + + for (i = 0; i < sizeof(igs_regs); i += 2) + cyber2000_grphw(igs_regs[i], igs_regs[i+1]); } /* @@ -1145,37 +1226,96 @@ int __init cyber2000fb_init(void) { struct pci_dev *dev; u_int h_sync, v_sync; - u_long base_p, base_v; + u_long mmio_base, smem_base, smem_size; + int err = 0; + + dev = pci_find_device(PCI_VENDOR_ID_INTERG, + PCI_DEVICE_ID_INTERG_2000, NULL); + + if (!dev) + dev = pci_find_device(PCI_VENDOR_ID_INTERG, + PCI_DEVICE_ID_INTERG_2010, NULL); - dev = pci_find_device(PCI_VENDOR_ID_INTERG, 0x2000, NULL); if (!dev) return -ENXIO; - /* this should be done by PCI generic code */ - base_p = 0x80000000 + dev->resource[0].start; + sprintf(current_par.dev_name, "CyberPro%4X", dev->device); + + smem_base = dev->resource[0].start; + mmio_base = dev->resource[0].start + 0x00800000; /* - * This should be ioremap'd, thus: - * - * base_v = ioremap(dev->resource[0].start, dev->resource[0].end - dev->resource[0].start + 1); + * Map in the registers */ - base_v = (u_long)bus_to_virt(dev->resource[0].start); + if (!request_mem_region(mmio_base, MMIO_SIZE, "memory mapped I/O")) { + printk("%s: memory mapped IO in use\n", + current_par.dev_name); + return -EBUSY; + } - /*FIXME*/ - CyberRegs = base_v + 0x00800000; + CyberRegs = ioremap(mmio_base, MMIO_SIZE); + if (!CyberRegs) { + printk("%s: unable to map memory mapped IO\n", + current_par.dev_name); + err = -ENOMEM; + goto release_mmio_resource; + } cyber2000_outb(0x18, 0x46e8); cyber2000_outb(0x01, 0x102); cyber2000_outb(0x08, 0x46e8); + /* + * get the video RAM size from the VGA register. + * This should have been already initialised by the BIOS, + * but if it's garbage, claim default 1MB VRAM (woody) + */ + cyber2000_outb(0x72, 0x3ce); + switch (cyber2000_inb(0x3cf) & 3) { + case 2: smem_size = 0x00400000; break; + case 1: smem_size = 0x00200000; break; + default: smem_size = 0x00100000; break; + } + + /* + * Map in screen memory + */ + if (!request_mem_region(smem_base, smem_size, "frame buffer")) { + printk("%s: frame buffer in use\n", + current_par.dev_name); + err = -EBUSY; + goto release_mmio; + } + + current_par.screen_base = ioremap(smem_base, smem_size); + if (!current_par.screen_base) { + printk("%s: unable to map screen memory\n", + current_par.dev_name); + err = -ENOMEM; + goto release_smem_resource; + } +current_par.screen_base += IO_FUDGE_FACTOR; + current_par.screen_size = smem_size; + current_par.screen_base_p = smem_base + 0x80000000; + current_par.regs_base_p = mmio_base + 0x80000000; + current_par.currcon = -1; + cyber2000fb_init_fbinfo(); - current_par.currcon = -1; - current_par.screen_base_p = base_p; - current_par.screen_base = base_v; - current_par.screen_size = 0x00200000; - current_par.regs_base_p = base_p + 0x00800000; + if (!fb_find_mode(&init_var, &fb_info, NULL, + NULL, 0, &cyber2000fb_default_mode, 8)) { + printk("%s: no valid mode found\n", + current_par.dev_name); + goto release_smem_resource; + } + + init_var.yres_virtual = smem_size * 8 / + (init_var.bits_per_pixel * init_var.xres_virtual); + if (init_var.yres_virtual < init_var.yres) + init_var.yres_virtual = init_var.yres; + + cyber2000fb_hw_init(); cyber2000fb_set_var(&init_var, -1, &fb_info); h_sync = 1953125000 / init_var.pixclock; @@ -1184,24 +1324,44 @@ int __init cyber2000fb_init(void) v_sync = h_sync / (init_var.yres + init_var.upper_margin + init_var.lower_margin + init_var.vsync_len); - printk("Cyber2000: %ldkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", + printk("%s: %ldkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", + current_par.dev_name, current_par.screen_size >> 10, init_var.xres, init_var.yres, h_sync / 1000, h_sync % 1000, v_sync); - if (register_framebuffer(&fb_info) < 0) - return -EINVAL; + if (register_framebuffer(&fb_info) < 0) { + err = -EINVAL; + goto release_smem; + } + + current_par.initialised = 1; MOD_INC_USE_COUNT; /* TODO: This driver cannot be unloaded yet */ return 0; -} +release_smem: + iounmap(current_par.screen_base); +release_smem_resource: + release_mem_region(smem_base, smem_size); +release_mmio: + iounmap(CyberRegs); +release_mmio_resource: + release_mem_region(mmio_base, MMIO_SIZE); + return err; +} #ifdef MODULE int __init init_module(void) { - return cyber2000fb_init(); + int ret; + + ret = cyber2000fb_init(); + if (ret) + return ret; + + return 0; } void cleanup_module(void) @@ -1210,6 +1370,12 @@ void cleanup_module(void) decremented to zero */ unregister_framebuffer(&fb_info); /* TODO: clean up ... */ + + iounmap(current_par.screen_base); + iounmap(CyberRegs); + + release_mem_region(smem_base, current_par.screen_size); + release_mem_region(mmio_base, MMIO_SIZE); } #endif /* MODULE */ diff --git a/drivers/video/cyber2000fb.h b/drivers/video/cyber2000fb.h index bbbd1edbb..0fb1f596c 100644 --- a/drivers/video/cyber2000fb.h +++ b/drivers/video/cyber2000fb.h @@ -5,13 +5,14 @@ */ #define arraysize(x) (sizeof(x)/sizeof(*(x))) -#define cyber2000_outb(dat,reg) (CyberRegs[reg] = dat) -#define cyber2000_outw(dat,reg) (*(unsigned short *)&CyberRegs[reg] = dat) -#define cyber2000_outl(dat,reg) (*(unsigned long *)&CyberRegs[reg] = dat) -#define cyber2000_inb(reg) (CyberRegs[reg]) -#define cyber2000_inw(reg) (*(unsigned short *)&CyberRegs[reg]) -#define cyber2000_inl(reg) (*(unsigned long *)&CyberRegs[reg]) +#define cyber2000_outb(dat,reg) writeb(dat, CyberRegs + reg) +#define cyber2000_outw(dat,reg) writew(dat, CyberRegs + reg) +#define cyber2000_outl(dat,reg) writel(dat, CyberRegs + reg) + +#define cyber2000_inb(reg) readb(CyberRegs + reg) +#define cyber2000_inw(reg) readw(CyberRegs + reg) +#define cyber2000_inl(reg) readl(CyberRegs + reg) static inline void cyber2000_crtcw(int reg, int val) { @@ -40,7 +41,7 @@ static inline void cyber2000_seqw(int reg, int val) } struct cyber2000fb_par { - unsigned long screen_base; + char * screen_base; unsigned long screen_base_p; unsigned long regs_base; unsigned long regs_base_p; @@ -48,6 +49,9 @@ struct cyber2000fb_par { unsigned long screen_size; unsigned int palette_size; signed int currcon; + char dev_name[32]; + unsigned int initialised; + /* * palette */ @@ -69,10 +73,32 @@ struct cyber2000fb_par { } c_table; }; -struct res { - int xres; - int yres; - unsigned char crtc_regs[18]; - unsigned char crtc_ofl; - unsigned char clk_regs[4]; -}; +#define PIXFORMAT_8BPP 0 +#define PIXFORMAT_16BPP 1 +#define PIXFORMAT_24BPP 2 + +#define VISUALID_256 1 +#define VISUALID_64K 2 +#define VISUALID_16M 4 +#define VISUALID_32K 6 + +#define CO_CMD_L_PATTERN_FGCOL 0x8000 +#define CO_CMD_L_INC_LEFT 0x0004 +#define CO_CMD_L_INC_UP 0x0002 + +#define CO_CMD_H_SRC_PIXMAP 0x2000 +#define CO_CMD_H_BLITTER 0x0800 + +#define CO_REG_CONTROL 0xbf011 +#define CO_REG_SRC_WIDTH 0xbf018 +#define CO_REG_PIX_FORMAT 0xbf01c +#define CO_REG_FORE_MIX 0xbf048 +#define CO_REG_FOREGROUND 0xbf058 +#define CO_REG_WIDTH 0xbf060 +#define CO_REG_HEIGHT 0xbf062 +#define CO_REG_X_PHASE 0xbf078 +#define CO_REG_CMD_L 0xbf07c +#define CO_REG_CMD_H 0xbf07e +#define CO_REG_SRC_PTR 0xbf170 +#define CO_REG_DEST_PTR 0xbf178 +#define CO_REG_DEST_WIDTH 0xbf218 diff --git a/drivers/video/fbcon-mac.c b/drivers/video/fbcon-mac.c index 58deaff54..77adb6395 100644 --- a/drivers/video/fbcon-mac.c +++ b/drivers/video/fbcon-mac.c @@ -455,7 +455,7 @@ static int get_pixel_mac(struct display *p, int pixel_x, int pixel_y) u8 *dest, bit; u16 *dest16; u32 *dest32; - u8 pixel; + u8 pixel=0; switch (p->var.bits_per_pixel) { case 1: diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 9bcb6920e..4bd6e8f7b 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -102,6 +102,8 @@ extern int fm2fb_setup(char*); extern int q40fb_init(void); extern int sgivwfb_init(void); extern int sgivwfb_setup(char*); +extern int rivafb_init(void); +extern int rivafb_setup(char*); extern int tdfxfb_init(void); extern int tdfxfb_setup(char*); @@ -176,6 +178,9 @@ static struct { #ifdef CONFIG_FB_VIRGE { "virge", virgefb_init, virgefb_setup }, #endif +#ifdef CONFIG_FB_RIVA + { "riva", rivafb_init, rivafb_setup }, +#endif #ifdef CONFIG_FB_VESA { "vesa", vesafb_init, vesafb_setup }, #endif @@ -483,9 +488,12 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) struct fb_ops *fb = info->fbops; struct fb_fix_screeninfo fix; struct fb_var_screeninfo var; - unsigned long start; + unsigned long start, off; u32 len; + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) + return -EINVAL; + off = vma->vm_pgoff << PAGE_SHIFT; if (!fb) return -ENODEV; if (fb->fb_mmap) @@ -504,10 +512,10 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) start = fix.smem_start; len = (start & ~PAGE_MASK)+fix.smem_len; start &= PAGE_MASK; - len = (len+~PAGE_MASK) & PAGE_MASK; - if (vma->vm_offset >= len) { + len = (len+~PAGE_MASK) & PAGE_MASK; /* someone's on crack. */ + if (off >= len) { /* memory mapped io */ - vma->vm_offset -= len; + off -= len; fb->fb_get_var(&var, PROC_CONSOLE(info), info); if (var.accel_flags) return -EINVAL; @@ -516,11 +524,10 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) start &= PAGE_MASK; len = (len+~PAGE_MASK) & PAGE_MASK; } - if ((vma->vm_end - vma->vm_start + vma->vm_offset) > len) + if ((vma->vm_end - vma->vm_start + off) > len) return -EINVAL; - vma->vm_offset += start; - if (vma->vm_offset & ~PAGE_MASK) - return -ENXIO; + off += start; + vma->vm_pgoff = off >> PAGE_SHIFT; #if defined(__mc68000__) if (CPU_IS_020_OR_030) pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030; @@ -549,7 +556,7 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) #else #warning What do we have to do here?? #endif - if (io_remap_page_range(vma->vm_start, vma->vm_offset, + if (io_remap_page_range(vma->vm_start, off, vma->vm_end - vma->vm_start, vma->vm_page_prot)) return -EAGAIN; return 0; @@ -646,16 +653,12 @@ unregister_framebuffer(const struct fb_info *fb_info) return 0; } -static struct proc_dir_entry *proc_fbmem; - void __init fbmem_init(void) { int i; - proc_fbmem = create_proc_entry("fb", 0, 0); - if (proc_fbmem) - proc_fbmem->read_proc = fbmem_read_proc; + create_proc_read_entry("fb", 0, 0, fbmem_read_proc, NULL); if (register_chrdev(FB_MAJOR,"fb",&fb_fops)) printk("unable to get major %d for fb devs\n", FB_MAJOR); diff --git a/drivers/video/igafb.c b/drivers/video/igafb.c index 5ed528af2..43e9eeadc 100644 --- a/drivers/video/igafb.c +++ b/drivers/video/igafb.c @@ -261,8 +261,6 @@ static int igafb_mmap(struct fb_info *info, struct file *file, return -ENXIO; size = vma->vm_end - vma->vm_start; - if (vma->vm_offset & ~PAGE_MASK) - return -ENXIO; /* To stop the swapper from even considering these pages. */ vma->vm_flags |= (VM_SHM | VM_LOCKED); @@ -271,17 +269,17 @@ static int igafb_mmap(struct fb_info *info, struct file *file, for (page = 0; page < size; ) { map_size = 0; for (i = 0; fb->mmap_map[i].size; i++) { - unsigned long start = fb->mmap_map[i].voff; - unsigned long end = start + fb->mmap_map[i].size; - unsigned long offset = vma->vm_offset + page; + unsigned long start = (fb->mmap_map[i].voff) >> PAGE_SHIFT; + unsigned long end = start + (fb->mmap_map[i].size) >> PAGE_SHIFT; + unsigned long offset = vma->vm_pgoff + (page >> PAGE_SHIFT); if (start > offset) continue; if (offset >= end) continue; - map_size = fb->mmap_map[i].size - (offset - start); - map_offset = fb->mmap_map[i].poff + (offset - start); + map_size = fb->mmap_map[i].size - ((offset - start) << PAGE_SHIFT); + map_offset = fb->mmap_map[i].poff + ((offset - start) << PAGE_SHIFT); break; } if (!map_size) { diff --git a/drivers/video/nv4ref.h b/drivers/video/nv4ref.h new file mode 100644 index 000000000..ffcb4445d --- /dev/null +++ b/drivers/video/nv4ref.h @@ -0,0 +1,2445 @@ + /***************************************************************************\ +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NOTICE TO USER: The source code is copyrighted under U.S. and *| +|* international laws. Users and possessors of this source code are *| +|* hereby granted a nonexclusive, royalty-free copyright license to *| +|* use this code in individual and commercial software. *| +|* *| +|* Any use of this source code must include, in the user documenta- *| +|* tion and internal comments to the code, notices to the end user *| +|* as follows: *| +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| +|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| +|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| +|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| +|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| +|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| +|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| +|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| +|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| +|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| +|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| +|* *| +|* U.S. Government End Users. This source code is a "commercial *| +|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| +|* consisting of "commercial computer software" and "commercial *| +|* computer software documentation," as such terms are used in *| +|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| +|* ment only as a commercial end item. Consistent with 48 C.F.R. *| +|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| +|* all U.S. Government End Users acquire the source code with only *| +|* those rights set forth herein. *| +|* *| + \***************************************************************************/ + +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of + * the documentation restriction above, to merely say that this nVidia's + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + */ + + /***************************************************************************\ +|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *| + \***************************************************************************/ + + +#ifndef __NV4REF_H__ +#define __NV4REF_H__ + +/* Magic values to lock/unlock extended regs */ +#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */ +#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */ +#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */ +#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */ + +#define UNLOCK_EXT_MAGIC 0x57 +#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ + +#define LOCK_EXT_INDEX 0x6 + +#define NV_PCRTC_HORIZ_TOTAL 0x00 +#define NV_PCRTC_HORIZ_DISPLAY_END 0x01 +#define NV_PCRTC_HORIZ_BLANK_START 0x02 + +#define NV_PCRTC_HORIZ_BLANK_END 0x03 +#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7 +#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5 +#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0 + +#define NV_PCRTC_HORIZ_RETRACE_START 0x04 + +#define NV_PCRTC_HORIZ_RETRACE_END 0x05 +#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7 +#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5 +#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0 + +#define NV_PCRTC_VERT_TOTAL 0x06 + +#define NV_PCRTC_OVERFLOW 0x07 +#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7 +#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6 +#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5 +#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4 +#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3 +#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2 +#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1 +#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0 + +#define NV_PCRTC_PRESET_ROW_SCAN 0x08 + +#define NV_PCRTC_MAX_SCAN_LINE 0x09 +#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7 +#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6 +#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5 +#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0 + +#define NV_PCRTC_CURSOR_START 0x0A +#define NV_PCRTC_CURSOR_END 0x0B +#define NV_PCRTC_START_ADDR_HIGH 0x0C +#define NV_PCRTC_START_ADDR_LOW 0x0D +#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E +#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F + +#define NV_PCRTC_VERT_RETRACE_START 0x10 +#define NV_PCRTC_VERT_RETRACE_END 0x11 +#define NV_PCRTC_VERT_DISPLAY_END 0x12 +#define NV_PCRTC_OFFSET 0x13 +#define NV_PCRTC_UNDERLINE_LOCATION 0x14 +#define NV_PCRTC_VERT_BLANK_START 0x15 +#define NV_PCRTC_VERT_BLANK_END 0x16 +#define NV_PCRTC_MODE_CONTROL 0x17 +#define NV_PCRTC_LINE_COMPARE 0x18 + +/* Extended offset and start address */ +#define NV_PCRTC_REPAINT0 0x19 +#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 +#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 + +/* Horizonal extended bits */ +#define NV_PCRTC_HORIZ_EXTRA 0x2d +#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 +#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 +#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 +#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 +#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 + +/* Assorted extra bits */ +#define NV_PCRTC_EXTRA 0x25 +#define NV_PCRTC_EXTRA_OFFSET_11 5:5 +#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 +#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 +#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 +#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 +#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 + +/* Controls how much data the refresh fifo requests */ +#define NV_PCRTC_FIFO_CONTROL 0x1b +#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 +#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 +#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 +#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 +#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 +#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 +#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 + +/* When the fifo occupancy falls below *twice* the watermark, + * the refresh fifo will start to be refilled. If this value is + * too low, you will get junk on the screen. Too high, and performance + * will suffer. Watermark in units of 8 bytes + */ +#define NV_PCRTC_FIFO 0x20 +#define NV_PCRTC_FIFO_RESET 7:7 +#define NV_PCRTC_FIFO_WATERMARK 5:0 + +/* Various flags */ +#define NV_PCRTC_REPAINT1 0x1a +#define NV_PCRTC_REPAINT1_HSYNC 7:7 +#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 +#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 +#define NV_PCRTC_REPAINT1_VSYNC 6:6 +#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 +#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 +#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 +#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 +#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 +#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 +#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 +#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ +#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 +#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 +#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 + +#define NV_PCRTC_GRCURSOR0 0x30 +#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 + +#define NV_PCRTC_GRCURSOR1 0x31 +#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 +#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 +#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 +#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 +#define NV_PCRTC_GRCURSOR1_CURSOR 0:0 +#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 +#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 + +/* Controls what the format of the framebuffer is */ +#define NV_PCRTC_PIXEL 0x28 +#define NV_PCRTC_PIXEL_MODE 7:7 +#define NV_PCRTC_PIXEL_MODE_TV 0x01 +#define NV_PCRTC_PIXEL_MODE_VGA 0x00 +#define NV_PCRTC_PIXEL_TV_MODE 6:6 +#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 +#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 +#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 +#define NV_PCRTC_PIXEL_FORMAT 1:0 +#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 +#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 +#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 +#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 + +/* RAMDAC registers and fields */ +#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ +#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ +#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ +#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ +#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */ +#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */ +#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */ +#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */ +#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */ +#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */ +#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */ +#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */ +#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ +#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ +#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ +#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ +#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ +#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ +#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ +#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ + +/* Master Control */ +#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ +#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */ +#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */ +#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */ +#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */ +#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */ +#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */ +#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */ +#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */ +#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */ +#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */ +#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */ +#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */ +#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */ +#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */ +#define NV_PMC_INTR_0 0x00000100 /* RW-4R */ +#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ +#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ +#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ +#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ +#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ +#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */ +#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ +#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ +#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ +#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ +#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ +#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ +#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ +#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */ +#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */ +#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */ +#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */ +#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */ +#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */ +#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */ +#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */ + +/* dev_timer.ref */ +#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */ +#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ +#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ +#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ +#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */ +#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ +#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ +#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ +#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ +#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */ +#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */ +#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */ +#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */ +#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */ +#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */ +#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */ +#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */ +#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ +#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */ + +/* dev_fifo.ref */ +#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ +#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */ +#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */ +#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */ +#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */ +#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ +#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ +#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ +#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ +#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ +#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */ +#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */ +#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ +#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ +#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ +#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ +#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ +#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ +#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */ +#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */ +#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */ +#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */ +#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */ +#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */ +#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */ +#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */ +#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */ +#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */ +#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */ +#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ +#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ +#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ +#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ +#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ +#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ +#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ +#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ +#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ +#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */ +#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */ +#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ +#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ +#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */ +#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */ +#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */ +#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ +#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ +#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ +#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ +#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */ +#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */ +#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */ +#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */ +#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */ +#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ +#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */ +#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */ +#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ +#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */ +#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */ +#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */ +#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */ +#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ +#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ +#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ +#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */ +#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */ +#define NV_PFIFO_MODE 0x00002504 /* RW-4R */ +#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */ +#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA 0x00002508 /* RW-4R */ +#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */ +#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */ +#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */ +#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */ +#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ +#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ +#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ +#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ +#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ +#define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */ +#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ +#define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */ +#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */ +#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */ +#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */ +#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */ +#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */ +#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */ +#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */ +#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */ +#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */ +#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */ +#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ +#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */ +#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ +#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */ +#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */ +#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */ +#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */ +#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ +#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */ +#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */ +#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */ +#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */ +#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */ +#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */ +#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */ +#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */ +#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */ +#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */ +#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */ +#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */ +#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */ +#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */ +#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */ +#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */ +#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */ +#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */ +#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */ +#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */ +#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */ +#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */ +#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */ +#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ +#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */ +#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */ +#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ +#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */ +#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */ +#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */ +#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */ +#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ +#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */ +#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */ +#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */ +#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */ +#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */ +#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */ +#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */ +#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */ +#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */ +#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */ +#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */ +#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */ +#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */ +#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */ +#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */ +#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */ +#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */ +#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */ +#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */ +#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */ +#define NV_PFIFO_DEVICE__SIZE_1 128 /* */ +#define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */ +#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */ +#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ +#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */ +#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ +#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */ +#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */ +#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */ +#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ +#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ +#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */ +#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ +#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ +#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ +#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */ +#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */ +#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */ +#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ +#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */ +/* dev_graphics.ref */ +#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ +#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ +#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ +#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ +#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ +#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */ +#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */ +#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */ +#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */ +#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */ +#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */ +#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */ +#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */ +#define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */ +#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */ +#define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */ +#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */ +#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */ +#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */ +#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */ +#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */ +#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */ +#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */ +#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */ +#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */ +#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */ +#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */ +#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */ +#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */ +#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */ +#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */ +#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */ +#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */ +#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */ +#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */ +#define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */ +#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */ +#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */ +#define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */ +#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */ +#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */ +#define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */ +#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */ +#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */ +#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */ +#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */ +#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */ +#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */ +#define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */ +#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */ +#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */ +#define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */ +#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ +#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ +#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ +#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ +#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ +#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ +#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */ +#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */ +#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */ +#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ +#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ +#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ +#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ +#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ +#define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */ +#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */ +#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */ +#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */ +#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ +#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ +#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */ +#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */ +#define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */ +#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */ +#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */ +#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */ +#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */ +#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */ +#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */ +#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */ +#define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */ +#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */ +#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */ +#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ +#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */ +#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */ +#define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */ +#define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */ +#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */ +#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */ +#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */ +#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */ +#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */ +#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */ +#define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */ +#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */ +#define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */ +#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */ +#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */ +#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */ +#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */ +#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */ +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */ +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */ +#define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */ +#define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */ +#define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */ +#define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */ +#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */ +#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */ +#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */ +#define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */ +#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */ +#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */ +#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */ +#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ +#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */ +#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */ +#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */ +#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ +#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ +#define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */ +#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */ +#define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */ +#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */ +#define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */ +#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */ +#define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */ +#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */ +#define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */ +#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */ +#define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */ +#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */ +#define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */ +#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */ +#define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */ +#define NV_PGRAPH_BBASE__SIZE_1 6 /* */ +#define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */ +#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */ +#define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */ +#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */ +#define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */ +#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */ +#define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */ +#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */ +#define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */ +#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */ +#define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */ +#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */ +#define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */ +#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */ +#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */ +#define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */ +#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */ +#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */ +#define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */ +#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */ +#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */ +#define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */ +#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */ +#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */ +#define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */ +#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */ +#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */ +#define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */ +#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */ +#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */ +#define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */ +#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */ +#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */ +#define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */ +#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */ +#define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */ +#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */ +#define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */ +#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */ +#define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */ +#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */ +#define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */ +#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */ +#define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */ +#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */ +#define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */ +#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */ +#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */ +#define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */ +#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */ +#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */ +#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */ +#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */ +#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */ +#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */ +#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */ +#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */ +#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */ +#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */ +#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */ +#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */ +#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */ +#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */ +#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */ +#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */ +#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE 0x00400710 /* RW-4R */ +#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */ +#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */ +#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */ +#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */ +#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */ +#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */ +#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */ +#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */ +#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */ +#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */ +#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */ +#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */ +#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */ +#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */ +#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */ +#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */ +#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */ +#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */ +#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */ +#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */ +#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */ +#define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */ +#define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */ +#define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */ +#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */ +#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */ +#define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */ +#define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */ +#define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */ +#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */ +#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */ +#define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */ +#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */ +#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */ +#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ +#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ +#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */ +#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */ +#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */ +#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */ +#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */ +#define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */ +#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */ +#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */ +#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */ +#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */ +#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */ +#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */ +#define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */ +#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */ +#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */ +#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */ +#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */ +#define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */ +#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */ +#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */ +#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */ +#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ +#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */ +#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */ +#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */ +#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */ +#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */ +#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */ +#define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */ +#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */ +#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */ +#define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */ +#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */ +#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */ +#define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */ +#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */ +#define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */ +#define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */ +#define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */ +#define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */ +#define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */ +#define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */ +#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */ +#define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */ +#define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */ +#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ +#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */ +#define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */ +#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */ +#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */ +#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */ +#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */ +#define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */ +#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */ +#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */ +#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */ +#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */ +#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */ +#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */ +#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */ +#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */ +#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */ +#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ +#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ +#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */ +#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */ +#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */ +#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ +#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ +#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */ +#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */ +#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */ +#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ +#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */ +#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */ +#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */ +#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */ +#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */ +#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ +#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */ +#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ +#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ +#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */ +#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */ +#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */ +#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */ +#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ +#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */ +#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */ +#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */ +#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */ +#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */ +#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */ +#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */ +#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */ +#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ +#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ +#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ +#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ +#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ +#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */ +#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ +#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ +#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ +#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ +#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */ +#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ +#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */ +#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ +#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */ +#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */ +#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */ +#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */ +#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */ +#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */ +#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */ +#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */ +#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */ +#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */ +#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */ +#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */ +#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */ +#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */ +#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */ +#define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */ +#define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */ +#define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */ +#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ +#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */ +#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ +#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */ +#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ +#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ +#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */ +#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */ +#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */ +#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */ +#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */ +#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */ +#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */ +#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */ +#define NV_PGRAPH_U_RAM__SIZE_1 16 /* */ +#define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */ +#define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */ +#define NV_PGRAPH_V_RAM__SIZE_1 16 /* */ +#define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */ +#define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */ +#define NV_PGRAPH_M_RAM__SIZE_1 16 /* */ +#define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */ +#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */ +#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */ +#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */ +#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */ +#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */ +#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */ +#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */ +#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */ +#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */ +#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */ +#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */ +#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */ +#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */ +#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */ +#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */ +#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */ +#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */ +#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */ +#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */ +#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */ +#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */ +#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ +#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ +#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ +#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ +#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ +#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ +#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */ +#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ +#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ +#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ +#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */ +#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */ +#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */ +#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */ +#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ +#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ +#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ +#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */ +#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */ +#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */ +#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */ +#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */ +#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */ +#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */ +#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */ +#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */ +#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */ +#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */ +#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ +#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ +#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ +#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ +#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ +#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ +#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */ +#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ +#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ +#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ +#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */ +#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */ +#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */ +#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */ +#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ +#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ +#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ +#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */ +#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */ +#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */ +#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */ +#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */ +#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */ +#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */ +#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */ +#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */ + +/* Framebuffer registers */ +#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ +#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ +#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */ +#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */ +#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */ +#define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */ +#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */ +#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ +#define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */ +#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */ +#define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */ +#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */ +#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */ +#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */ +#define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */ +#define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */ +#define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */ +#define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */ +#define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */ +#define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */ +#define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */ +#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */ +#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */ +#define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */ +#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */ +#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */ +#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */ +#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */ +#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */ +#define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */ +#define NV_PFB_RTL 0x00100300 /* RW-4R */ +#define NV_PFB_RTL_H 0:0 /* RWIUF */ +#define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PFB_RTL_MC 1:1 /* RWIUF */ +#define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PFB_RTL_V 2:2 /* RWIUF */ +#define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PFB_RTL_G 3:3 /* RWIUF */ +#define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PFB_RTL_GB 4:4 /* RWIUF */ +#define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ +#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ +#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ +#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ +#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ +#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ +#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ +#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ +#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ +#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */ +#define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */ +#define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */ +#define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */ +#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */ +#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */ + +#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */ +#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */ +#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */ +#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */ +#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */ +#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */ + +/* Extras */ +#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */ +/*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/ +#define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */ +/*#define NV_PNVM 0x00BFFFFF:0x00800000*/ +#define NV_CHAN0 0x0080ffff:0x00800000 + +/* FIFO subchannels */ +#define NV_UROP 0x43 +#define NV_UCHROMA 0x57 +#define NV_UCLIP 0x19 +#define NV_UPATT 0x18 +#define NV_ULIN 0x5C +#define NV_UTRI 0x5D +#define NV_URECT 0x5E +#define NV_UBLIT 0x5F +#define NV_UGLYPH 0x4B + +#endif /*__NV4REF_H__*/ + diff --git a/drivers/video/nvreg.h b/drivers/video/nvreg.h new file mode 100644 index 000000000..abfc167ae --- /dev/null +++ b/drivers/video/nvreg.h @@ -0,0 +1,188 @@ +/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ +/* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */ + +#ifndef __NVREG_H_ +#define __NVREG_H_ + +/* Little macro to construct bitmask for contiguous ranges of bits */ +#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) +#define MASKEXPAND(mask) BITMASK(1?mask,0?mask) + +/* Macro to set specific bitfields (mask has to be a macro x:y) ! */ +#define SetBF(mask,value) ((value) << (0?mask)) +#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) + +#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ + | SetBF(mask,value))) + +#define DEVICE_BASE(device) (0?NV##_##device) +#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1) + +/* This is where we will have to have conditional compilation */ +#define DEVICE_ACCESS(device,reg) \ + nvCONTROL[(NV_##device##_##reg)/4] + +#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) +#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) +#define DEVICE_PRINT(device,reg) \ + ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) +#define DEVICE_DEF(device,mask,value) \ + SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) +#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) +#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) + +#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) +#define PDAC_Read(reg) DEVICE_READ(PDAC,reg) +#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) +#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) +#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) +#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) + +#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) +#define PFB_Read(reg) DEVICE_READ(PFB,reg) +#define PFB_Print(reg) DEVICE_PRINT(PFB,reg) +#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) +#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) +#define PFB_Mask(mask) DEVICE_MASK(PFB,mask) + +#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) +#define PRM_Read(reg) DEVICE_READ(PRM,reg) +#define PRM_Print(reg) DEVICE_PRINT(PRM,reg) +#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) +#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) +#define PRM_Mask(mask) DEVICE_MASK(PRM,mask) + +#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) +#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) +#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) +#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) +#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) +#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) + +#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) +#define PDMA_Read(reg) DEVICE_READ(PDMA,reg) +#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) +#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) +#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) +#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) + +#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value) +#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg) +#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg) +#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value) +#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value) +#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask) + +#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) +#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) +#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) +#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) +#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) +#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask) + +#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) +#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) +#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) +#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) +#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) +#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) + +#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) +#define PRAM_Read(reg) DEVICE_READ(PRAM,reg) +#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) +#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) +#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) +#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) + +#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) +#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) +#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) +#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) +#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) +#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) + +#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) +#define PMC_Read(reg) DEVICE_READ(PMC,reg) +#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) +#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) +#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) +#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) + +#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) +#define PMC_Read(reg) DEVICE_READ(PMC,reg) +#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) +#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) +#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) +#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) + + +#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) +#define PBUS_Read(reg) DEVICE_READ(PBUS,reg) +#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) +#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) +#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) +#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) + + +#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) +#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) +#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) +#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) +#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) +#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) + + +#define PDAC_ReadExt(reg) \ + ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ + (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ + (PDAC_Read(INDEX_DATA))) + +#define PDAC_WriteExt(reg,value)\ + ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ + (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ + (PDAC_Write(INDEX_DATA,(value)))) + +#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5) +#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5)) + +#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) +#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) + +#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) +#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) +#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) + +#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) +#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) + +extern volatile unsigned *nvCONTROL; + +typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType; + +NVChipType GetChipType(void); + +#endif + + diff --git a/drivers/video/riva_hw.c b/drivers/video/riva_hw.c new file mode 100644 index 000000000..2e0f1b27e --- /dev/null +++ b/drivers/video/riva_hw.c @@ -0,0 +1,1429 @@ + /***************************************************************************\ +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NOTICE TO USER: The source code is copyrighted under U.S. and *| +|* international laws. Users and possessors of this source code are *| +|* hereby granted a nonexclusive, royalty-free copyright license to *| +|* use this code in individual and commercial software. *| +|* *| +|* Any use of this source code must include, in the user documenta- *| +|* tion and internal comments to the code, notices to the end user *| +|* as follows: *| +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| +|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| +|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| +|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| +|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| +|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| +|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| +|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| +|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| +|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| +|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| +|* *| +|* U.S. Government End Users. This source code is a "commercial *| +|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| +|* consisting of "commercial computer software" and "commercial *| +|* computer software documentation," as such terms are used in *| +|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| +|* ment only as a commercial end item. Consistent with 48 C.F.R. *| +|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| +|* all U.S. Government End Users acquire the source code with only *| +|* those rights set forth herein. *| +|* *| + \***************************************************************************/ +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of + * the documentation restriction above, to merely say that this nVidia's + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.c,v 1.1.2.3 1998/12/26 00:12:39 dawes Exp $ */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <asm/io.h> +#include "riva_hw.h" +#include "riva_tbl.h" + + +/* + * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT + * operate identically (except TNT has more memory and better 3D quality. + */ + +static int nv3Busy +( + RIVA_HW_INST *chip +) +{ + return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x000006B0/4] & 0x01)); +} +static int nv4Busy +( + RIVA_HW_INST *chip +) +{ + return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x00000700/4] & 0x01)); +} +static int ShowHideCursor +( + RIVA_HW_INST *chip, + int ShowHide +) +{ + int xcurrent; + xcurrent = chip->CurrentState->cursor1; + chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | (ShowHide & 0x01); + outb(0x31, 0x3D4); + outb(chip->CurrentState->cursor1, 0x3D5); + return (xcurrent & 0x01); +} + +/****************************************************************************\ +* * +* The video arbitration routines calculate some "magic" numbers. Fixes * +* the snow seen when accessing the framebuffer without it. * +* It just works (I hope). * +* * +\****************************************************************************/ + +#define DEFAULT_GR_LWM 100 +#define DEFAULT_VID_LWM 100 +#define DEFAULT_GR_BURST_SIZE 256 +#define DEFAULT_VID_BURST_SIZE 128 +#define VIDEO 0 +#define GRAPHICS 1 +#define MPORT 2 +#define ENGINE 3 +#define GFIFO_SIZE 320 +#define GFIFO_SIZE_128 256 +#define MFIFO_SIZE 120 +#define VFIFO_SIZE 256 +#define ABS(a) (a>0?a:-a) +typedef struct { + int gdrain_rate; + int vdrain_rate; + int mdrain_rate; + int gburst_size; + int vburst_size; + char vid_en; + char gr_en; + int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; + int by_gfacc; + char vid_only_once; + char gr_only_once; + char first_vacc; + char first_gacc; + char first_macc; + int vocc; + int gocc; + int mocc; + char cur; + char engine_en; + char converged; + int priority; +} nv3_arb_info; +typedef struct { + int graphics_lwm; + int video_lwm; + int graphics_burst_size; + int video_burst_size; + int graphics_hi_priority; + int media_hi_priority; + int rtl_values; + int valid; +} nv3_fifo_info; +typedef struct { + char pix_bpp; + char enable_video; + char gr_during_vid; + char enable_mp; + int memory_width; + int video_scale; + int pclk_khz; + int mclk_khz; + int mem_page_miss; + int mem_latency; + char mem_aligned; +} nv3_sim_state; +typedef struct { + int graphics_lwm; + int video_lwm; + int graphics_burst_size; + int video_burst_size; + int valid; +} nv4_fifo_info; +typedef struct { + int pclk_khz; + int mclk_khz; + int nvclk_khz; + char mem_page_miss; + char mem_latency; + int memory_width; + char enable_video; + char gr_during_vid; + char pix_bpp; + char mem_aligned; + char enable_mp; +} nv4_sim_state; +static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) +{ + int iter = 0; + int tmp, t; + int vfsize, mfsize, gfsize; + int mburst_size = 32; + int mmisses, gmisses, vmisses; + int misses; + int vlwm, glwm, mlwm; + int last, next, cur; + int max_gfsize ; + long ns; + + vlwm = 0; + glwm = 0; + mlwm = 0; + vfsize = 0; + gfsize = 0; + cur = ainfo->cur; + mmisses = 2; + gmisses = 2; + vmisses = 2; + if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; + else max_gfsize = GFIFO_SIZE; + max_gfsize = GFIFO_SIZE; + while (1) + { + if (ainfo->vid_en) + { + if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; + if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; + ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; + vfsize = ns * ainfo->vdrain_rate / 1000000; + vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; + } + if (state->enable_mp) + { + if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; + } + if (ainfo->gr_en) + { + if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; + if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; + ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; + gfsize = ns *ainfo->gdrain_rate/1000000; + gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; + } + mfsize = 0; + if (!state->gr_during_vid && ainfo->vid_en) + if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) + next = VIDEO; + else if (ainfo->mocc < 0) + next = MPORT; + else if (ainfo->gocc< ainfo->by_gfacc) + next = GRAPHICS; + else return (0); + else switch (ainfo->priority) + { + case VIDEO: + if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) + next = VIDEO; + else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) + next = GRAPHICS; + else if (ainfo->mocc<0) + next = MPORT; + else return (0); + break; + case GRAPHICS: + if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) + next = GRAPHICS; + else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) + next = VIDEO; + else if (ainfo->mocc<0) + next = MPORT; + else return (0); + break; + default: + if (ainfo->mocc<0) + next = MPORT; + else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) + next = GRAPHICS; + else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) + next = VIDEO; + else return (0); + break; + } + last = cur; + cur = next; + iter++; + switch (cur) + { + case VIDEO: + if (last==cur) misses = 0; + else if (ainfo->first_vacc) misses = vmisses; + else misses = 1; + ainfo->first_vacc = 0; + if (last!=cur) + { + ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; + vlwm = ns * ainfo->vdrain_rate/ 1000000; + vlwm = ainfo->vocc - vlwm; + } + ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; + ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; + ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; + ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; + break; + case GRAPHICS: + if (last==cur) misses = 0; + else if (ainfo->first_gacc) misses = gmisses; + else misses = 1; + ainfo->first_gacc = 0; + if (last!=cur) + { + ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; + glwm = ns * ainfo->gdrain_rate/1000000; + glwm = ainfo->gocc - glwm; + } + ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; + ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; + ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; + ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; + break; + default: + if (last==cur) misses = 0; + else if (ainfo->first_macc) misses = mmisses; + else misses = 1; + ainfo->first_macc = 0; + ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; + ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; + ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; + ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; + break; + } + if (iter>100) + { + ainfo->converged = 0; + return (1); + } + ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; + tmp = ns * ainfo->gdrain_rate/1000000; + if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) + { + ainfo->converged = 0; + return (1); + } + ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; + tmp = ns * ainfo->vdrain_rate/1000000; + if (ABS(ainfo->vburst_size) + (ABS(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) + { + ainfo->converged = 0; + return (1); + } + if (ABS(ainfo->gocc) > max_gfsize) + { + ainfo->converged = 0; + return (1); + } + if (ABS(ainfo->vocc) > VFIFO_SIZE) + { + ainfo->converged = 0; + return (1); + } + if (ABS(ainfo->mocc) > MFIFO_SIZE) + { + ainfo->converged = 0; + return (1); + } + if (ABS(vfsize) > VFIFO_SIZE) + { + ainfo->converged = 0; + return (1); + } + if (ABS(gfsize) > max_gfsize) + { + ainfo->converged = 0; + return (1); + } + if (ABS(mfsize) > MFIFO_SIZE) + { + ainfo->converged = 0; + return (1); + } + } +} +static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) +{ + int g, v, not_done; + long ens, vns, mns, gns; + int mmisses, gmisses, vmisses, eburst_size, mburst_size; + int refresh_cycle; + + refresh_cycle = 0; + refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; + mmisses = 2; + if (state->mem_aligned) gmisses = 2; + else gmisses = 3; + vmisses = 2; + eburst_size = state->memory_width * 1; + mburst_size = 32; + gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; + ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; + ainfo->wcmocc = 0; + ainfo->wcgocc = 0; + ainfo->wcvocc = 0; + ainfo->wcvlwm = 0; + ainfo->wcglwm = 0; + ainfo->engine_en = 1; + ainfo->converged = 1; + if (ainfo->engine_en) + { + ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; + ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; + ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; + ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; + ainfo->cur = ENGINE; + ainfo->first_vacc = 1; + ainfo->first_gacc = 1; + ainfo->first_macc = 1; + nv3_iterate(res_info, state,ainfo); + } + if (state->enable_mp) + { + mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; + ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; + ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; + ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; + ainfo->cur = MPORT; + ainfo->first_vacc = 1; + ainfo->first_gacc = 1; + ainfo->first_macc = 0; + nv3_iterate(res_info, state,ainfo); + } + if (ainfo->gr_en) + { + ainfo->first_vacc = 1; + ainfo->first_gacc = 0; + ainfo->first_macc = 1; + gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; + ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; + ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; + ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; + ainfo->cur = GRAPHICS; + nv3_iterate(res_info, state,ainfo); + } + if (ainfo->vid_en) + { + ainfo->first_vacc = 0; + ainfo->first_gacc = 1; + ainfo->first_macc = 1; + vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; + ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; + ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; + ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; + ainfo->cur = VIDEO; + nv3_iterate(res_info, state, ainfo); + } + if (ainfo->converged) + { + res_info->graphics_lwm = (int)ABS(ainfo->wcglwm) + 16; + res_info->video_lwm = (int)ABS(ainfo->wcvlwm) + 32; + res_info->graphics_burst_size = ainfo->gburst_size; + res_info->video_burst_size = ainfo->vburst_size; + res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); + res_info->media_hi_priority = (ainfo->priority == MPORT); + if (res_info->video_lwm > 160) + { + res_info->graphics_lwm = 256; + res_info->video_lwm = 128; + res_info->graphics_burst_size = 64; + res_info->video_burst_size = 64; + res_info->graphics_hi_priority = 0; + res_info->media_hi_priority = 0; + ainfo->converged = 0; + return (0); + } + if (res_info->video_lwm > 128) + { + res_info->video_lwm = 128; + } + return (1); + } + else + { + res_info->graphics_lwm = 256; + res_info->video_lwm = 128; + res_info->graphics_burst_size = 64; + res_info->video_burst_size = 64; + res_info->graphics_hi_priority = 0; + res_info->media_hi_priority = 0; + return (0); + } +} +static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) +{ + int done, g,v, p; + int priority, gburst_size, vburst_size, iter; + + done = 0; + if (state->gr_during_vid && ainfo->vid_en) + ainfo->priority = MPORT; + else + ainfo->priority = ainfo->gdrain_rate < ainfo->vdrain_rate ? VIDEO: GRAPHICS; + for (p=0; p < 2 && done != 1; p++) + { + for (g=128 ; (g > 32) && (done != 1); g= g>> 1) + { + for (v=128; (v >=32) && (done !=1); v = v>> 1) + { + ainfo->priority = p; + ainfo->gburst_size = g; + ainfo->vburst_size = v; + done = nv3_arb(res_info, state,ainfo); + if (g==128) + { + if ((res_info->graphics_lwm + g) > 256) + done = 0; + } + } + } + } + if (!done) + return (0); + else + return (1); +} +static void nv3CalcArbitration +( + nv3_fifo_info * res_info, + nv3_sim_state * state +) +{ + nv3_fifo_info save_info; + nv3_arb_info ainfo; + char res_gr, res_vid; + + ainfo.gr_en = 1; + ainfo.vid_en = state->enable_video; + ainfo.vid_only_once = 0; + ainfo.gr_only_once = 0; + ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8; + ainfo.vdrain_rate = (int) state->pclk_khz * 2; + if (state->video_scale != 0) + ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; + ainfo.mdrain_rate = 33000; + res_info->rtl_values = 0; + if (!state->gr_during_vid && state->enable_video) + { + ainfo.gr_only_once = 1; + ainfo.gr_en = 1; + ainfo.gdrain_rate = 0; + res_vid = nv3_get_param(res_info, state, &ainfo); + res_vid = ainfo.converged; + save_info.video_lwm = res_info->video_lwm; + save_info.video_burst_size = res_info->video_burst_size; + ainfo.vid_en = 1; + ainfo.vid_only_once = 1; + ainfo.gr_en = 1; + ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8; + ainfo.vdrain_rate = 0; + res_gr = nv3_get_param(res_info, state, &ainfo); + res_gr = ainfo.converged; + res_info->video_lwm = save_info.video_lwm; + res_info->video_burst_size = save_info.video_burst_size; + res_info->valid = res_gr & res_vid; + } + else + { + if (!ainfo.gr_en) ainfo.gdrain_rate = 0; + if (!ainfo.vid_en) ainfo.vdrain_rate = 0; + res_gr = nv3_get_param(res_info, state, &ainfo); + res_info->valid = ainfo.converged; + } +} +void nv3UpdateArbitrationSettings +( + unsigned VClk, + unsigned pixelDepth, + unsigned *burst, + unsigned *lwm, + RIVA_HW_INST *chip +) +{ + nv3_fifo_info fifo_data; + nv3_sim_state sim_data; + unsigned int M, N, P, pll, MClk; + + pll = chip->PRAMDAC[0x00000504/4]; + M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; + MClk = (N * chip->CrystalFreqKHz / M) >> P; + sim_data.pix_bpp = (char)pixelDepth; + sim_data.enable_video = 0; + sim_data.enable_mp = 0; + sim_data.video_scale = 1; + sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64; + sim_data.memory_width = 128; + sim_data.mem_latency = 11; + sim_data.mem_aligned = 1; + sim_data.mem_page_miss = 9; + sim_data.gr_during_vid = 0; + sim_data.pclk_khz = VClk; + sim_data.mclk_khz = MClk; + nv3CalcArbitration(&fifo_data, &sim_data); + if (fifo_data.valid) + { + int b = fifo_data.graphics_burst_size >> 4; + *burst = 0; + while (b >>= 1) (*burst)++; + *lwm = fifo_data.graphics_lwm >> 3; + } + else + { + *lwm = 0x24; + *burst = 0x02; + } +} +static void nv4CalcArbitration +( + nv4_fifo_info *fifo, + nv4_sim_state *arb +) +{ + int data, m,n,p, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; + int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; + int found, mclk_extra, mclk_loop, cbs, m1, p1; + int xtal_freq, mclk_freq, pclk_freq, nvclk_freq, mp_enable; + int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; + int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; + int craw, vraw; + + fifo->valid = 1; + pclk_freq = arb->pclk_khz; + mclk_freq = arb->mclk_khz; + nvclk_freq = arb->nvclk_khz; + pagemiss = arb->mem_page_miss; + cas = arb->mem_latency; + width = arb->memory_width >> 6; + video_enable = arb->enable_video; + color_key_enable = arb->gr_during_vid; + bpp = arb->pix_bpp; + align = arb->mem_aligned; + mp_enable = arb->enable_mp; + clwm = 0; + vlwm = 0; + cbs = 128; + pclks = 2; + nvclks = 2; + nvclks += 2; + nvclks += 1; + mclks = 5; + mclks += 3; + mclks += 1; + mclks += cas; + mclks += 1; + mclks += 1; + mclks += 1; + mclks += 1; + mclk_extra = 3; + nvclks += 2; + nvclks += 1; + nvclks += 1; + nvclks += 1; + if (mp_enable) + mclks+=4; + nvclks += 0; + pclks += 0; + found = 0; + while (found != 1) + { + fifo->valid = 1; + found = 1; + mclk_loop = mclks+mclk_extra; + us_m = mclk_loop *1000*1000 / mclk_freq; + us_n = nvclks*1000*1000 / nvclk_freq; + us_p = nvclks*1000*1000 / pclk_freq; + if (video_enable) + { + video_drain_rate = pclk_freq * 2; + crtc_drain_rate = pclk_freq * bpp/8; + vpagemiss = 2; + vpagemiss += 1; + crtpagemiss = 2; + vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; + if (nvclk_freq * 2 > mclk_freq * width) + video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; + else + video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; + us_video = vpm_us + us_m + us_n + us_p + video_fill_us; + vlwm = us_video * video_drain_rate/(1000*1000); + vlwm++; + vbs = 128; + if (vlwm > 128) vbs = 64; + if (vlwm > (256-64)) vbs = 32; + if (nvclk_freq * 2 > mclk_freq * width) + video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; + else + video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; + cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; + us_crt = + us_video + +video_fill_us + +cpm_us + +us_m + us_n +us_p + ; + clwm = us_crt * crtc_drain_rate/(1000*1000); + clwm++; + } + else + { + crtc_drain_rate = pclk_freq * bpp/8; + crtpagemiss = 2; + crtpagemiss += 1; + cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; + us_crt = cpm_us + us_m + us_n + us_p ; + clwm = us_crt * crtc_drain_rate/(1000*1000); + clwm++; + } + m1 = clwm + cbs - 512; + p1 = m1 * pclk_freq / mclk_freq; + p1 = p1 * bpp / 8; + if ((p1 < m1) && (m1 > 0)) + { + fifo->valid = 0; + found = 0; + if (mclk_extra ==0) found = 1; + mclk_extra--; + } + else if (video_enable) + { + if ((clwm > 511) || (vlwm > 255)) + { + fifo->valid = 0; + found = 0; + if (mclk_extra ==0) found = 1; + mclk_extra--; + } + } + else + { + if (clwm > 519) + { + fifo->valid = 0; + found = 0; + if (mclk_extra ==0) found = 1; + mclk_extra--; + } + } + craw = clwm; + vraw = vlwm; + if (clwm < 384) clwm = 384; + if (vlwm < 128) vlwm = 128; + data = (int)(clwm); + fifo->graphics_lwm = data; + fifo->graphics_burst_size = 128; + data = (int)((vlwm+15)); + fifo->video_lwm = data; + fifo->video_burst_size = vbs; + } +} +static void nv4UpdateArbitrationSettings +( + unsigned VClk, + unsigned pixelDepth, + unsigned *burst, + unsigned *lwm, + RIVA_HW_INST *chip +) +{ + nv4_fifo_info fifo_data; + nv4_sim_state sim_data; + unsigned int M, N, P, pll, MClk, NVClk, cfg1; + + pll = chip->PRAMDAC[0x00000504/4]; + M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; + MClk = (N * chip->CrystalFreqKHz / M) >> P; + pll = chip->PRAMDAC[0x00000500/4]; + M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; + NVClk = (N * chip->CrystalFreqKHz / M) >> P; + cfg1 = chip->PFB[0x00000204/4]; + sim_data.pix_bpp = (char)pixelDepth; + sim_data.enable_video = 0; + sim_data.enable_mp = 0; + sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64; + sim_data.mem_latency = (char)cfg1 & 0x0F; + sim_data.mem_aligned = 1; + sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); + sim_data.gr_during_vid = 0; + sim_data.pclk_khz = VClk; + sim_data.mclk_khz = MClk; + sim_data.nvclk_khz = NVClk; + nv4CalcArbitration(&fifo_data, &sim_data); + if (fifo_data.valid) + { + int b = fifo_data.graphics_burst_size >> 4; + *burst = 0; + while (b >>= 1) (*burst)++; + *lwm = fifo_data.graphics_lwm >> 3; + } +} + +/****************************************************************************\ +* * +* RIVA Mode State Routines * +* * +\****************************************************************************/ + +/* + * Calculate the Video Clock parameters for the PLL. + */ +static int CalcVClock +( + int clockIn, + int *clockOut, + int *mOut, + int *nOut, + int *pOut, + RIVA_HW_INST *chip +) +{ + unsigned lowM, highM, highP; + unsigned DeltaNew, DeltaOld; + unsigned VClk, Freq; + unsigned M, N, O, P; + + DeltaOld = 0xFFFFFFFF; + VClk = (unsigned)clockIn; + if (chip->CrystalFreqKHz == 14318) + { + lowM = 8; + highM = 14 - (chip->Architecture == 3); + } + else + { + lowM = 7; + highM = 13 - (chip->Architecture == 3); + } + highP = 4 - (chip->Architecture == 3); + for (P = 0; P <= highP; P ++) + { + Freq = VClk << P; + if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) + { + for (M = lowM; M <= highM; M++) + { + N = (VClk * M / chip->CrystalFreqKHz) << P; + Freq = (chip->CrystalFreqKHz * N / M) >> P; + if (Freq > VClk) + DeltaNew = Freq - VClk; + else + DeltaNew = VClk - Freq; + if (DeltaNew < DeltaOld) + { + *mOut = M; + *nOut = N; + *pOut = P; + *clockOut = Freq; + DeltaOld = DeltaNew; + } + } + } + } + return (DeltaOld != 0xFFFFFFFF); +} +/* + * Calculate extended mode parameters (SVGA) and save in a + * mode state structure. + */ +static void CalcStateExt +( + RIVA_HW_INST *chip, + RIVA_HW_STATE *state, + int bpp, + int width, + int hDisplaySize, + int hDisplay, + int hStart, + int hEnd, + int hTotal, + int height, + int vDisplay, + int vStart, + int vEnd, + int vTotal, + int dotClock +) +{ + int pixelDepth, VClk, m, n, p; + /* + * Save mode parameters. + */ + state->bpp = bpp; + state->width = width; + state->height = height; + /* + * Extended RIVA registers. + */ + pixelDepth = (bpp + 1)/8; + CalcVClock(dotClock, &VClk, &m, &n, &p, chip); + switch (chip->Architecture) + { + case 3: + nv3UpdateArbitrationSettings(VClk, + pixelDepth * 8, + &(state->arbitration0), + &(state->arbitration1), + chip); + state->cursor0 = 0x00; + state->cursor1 = 0x78; + state->cursor2 = 0x00000000; + state->pllsel = 0x10010100; + state->config = ((width + 31)/32) + | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) + | 0x1000; + state->general = 0x00000100; + state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; + break; + case 4: + case 5: + nv4UpdateArbitrationSettings(VClk, + pixelDepth * 8, + &(state->arbitration0), + &(state->arbitration1), + chip); + state->cursor0 = 0x00; + state->cursor1 = 0xFC; + state->cursor2 = 0x00000000; + state->pllsel = 0x10000700; + state->config = 0x00001114; + state->general = bpp == 16 ? 0x00101100 : 0x00100100; + state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; + break; + } + state->vpll = (p << 16) | (n << 8) | m; + state->screen = ((hTotal & 0x040) >> 2) + | ((vDisplay & 0x400) >> 7) + | ((vStart & 0x400) >> 8) + | ((vDisplay & 0x400) >> 9) + | ((vTotal & 0x400) >> 10); + state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; + state->horiz = hTotal < 260 ? 0x00 : 0x01; + state->pixel = (pixelDepth > 2 ? 3 : pixelDepth) | 0x40; + state->offset0 = + state->offset1 = + state->offset2 = + state->offset3 = 0; + state->pitch0 = + state->pitch1 = + state->pitch2 = + state->pitch3 = pixelDepth * width; +} +/* + * Load fixed function state and pre-calculated/stored state. + */ +#define LOAD_FIXED_STATE(tbl,dev) \ + for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ + chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1] +#define LOAD_FIXED_STATE_8BPP(tbl,dev) \ + for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ + chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1] +#define LOAD_FIXED_STATE_15BPP(tbl,dev) \ + for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ + chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1] +#define LOAD_FIXED_STATE_16BPP(tbl,dev) \ + for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ + chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1] +#define LOAD_FIXED_STATE_32BPP(tbl,dev) \ + for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ + chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1] +static void LoadStateExt +( + RIVA_HW_INST *chip, + RIVA_HW_STATE *state +) +{ + int i; + /* + * Load HW fixed function state. + */ + LOAD_FIXED_STATE(Riva,PMC); + LOAD_FIXED_STATE(Riva,PTIMER); + /* + * Make sure frame buffer config gets set before loading PRAMIN. + */ + chip->PFB[0x00000200/4] = state->config; + switch (chip->Architecture) + { + case 3: + LOAD_FIXED_STATE(nv3,PFIFO); + LOAD_FIXED_STATE(nv3,PRAMIN); + LOAD_FIXED_STATE(nv3,PGRAPH); + switch (state->bpp) + { + case 15: + case 16: + LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); + LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); + chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); + break; + case 24: + case 32: + LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); + LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); + chip->Tri03 = 0L; + break; + case 8: + default: + LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); + LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); + chip->Tri03 = 0L; + break; + } + for (i = 0x00000; i < 0x00800; i++) + chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03; + chip->PGRAPH[0x00000630/4] = state->offset0; + chip->PGRAPH[0x00000634/4] = state->offset1; + chip->PGRAPH[0x00000638/4] = state->offset2; + chip->PGRAPH[0x0000063C/4] = state->offset3; + chip->PGRAPH[0x00000650/4] = state->pitch0; + chip->PGRAPH[0x00000654/4] = state->pitch1; + chip->PGRAPH[0x00000658/4] = state->pitch2; + chip->PGRAPH[0x0000065C/4] = state->pitch3; + break; + case 4: + case 5: + LOAD_FIXED_STATE(nv4,PFIFO); + LOAD_FIXED_STATE(nv4,PRAMIN); + LOAD_FIXED_STATE(nv4,PGRAPH); + switch (state->bpp) + { + case 15: + LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); + LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); + chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); + break; + case 16: + LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); + LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); + chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); + break; + case 24: + case 32: + LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); + LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); + chip->Tri03 = 0L; + break; + case 8: + default: + LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); + LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); + chip->Tri03 = 0L; + break; + } + chip->PGRAPH[0x00000640/4] = state->offset0; + chip->PGRAPH[0x00000644/4] = state->offset1; + chip->PGRAPH[0x00000648/4] = state->offset2; + chip->PGRAPH[0x0000064C/4] = state->offset3; + chip->PGRAPH[0x00000670/4] = state->pitch0; + chip->PGRAPH[0x00000674/4] = state->pitch1; + chip->PGRAPH[0x00000678/4] = state->pitch2; + chip->PGRAPH[0x0000067C/4] = state->pitch3; + break; + } +//NOTICE("8"); +// LOAD_FIXED_STATE(Riva,FIFO); /* FIX ME*/ +//NOTICE("9"); + /* + * Load HW mode state. + */ + outb(0x19, 0x3D4); outb(state->repaint0, 0x3D5); + outb(0x1A, 0x3D4); outb(state->repaint1, 0x3D5); + outb(0x25, 0x3D4); outb(state->screen, 0x3D5); + outb(0x28, 0x3D4); outb(state->pixel, 0x3D5); + outb(0x2D, 0x3D4); outb(state->horiz, 0x3D5); + outb(0x1B, 0x3D4); outb(state->arbitration0, 0x3D5); + outb(0x20, 0x3D4); outb(state->arbitration1, 0x3D5); + outb(0x30, 0x3D4); outb(state->cursor0, 0x3D5); + outb(0x31, 0x3D4); outb(state->cursor1, 0x3D5); + chip->PRAMDAC[0x00000300/4] = state->cursor2; + chip->PRAMDAC[0x00000508/4] = state->vpll; + chip->PRAMDAC[0x0000050C/4] = state->pllsel; + chip->PRAMDAC[0x00000600/4] = state->general; + /* + * Turn off VBlank enable and reset. + */ +// *(chip->VBLANKENABLE) = 0; /* FIXME*/ +// *(chip->VBLANK) = chip->VBlankBit; /*FIXME*/ + /* + * Set interrupt enable. + */ + chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; + /* + * Set current state pointer. + */ + chip->CurrentState = state; + /* + * Reset FIFO free count. + */ + chip->FifoFreeCount = 0; +} +static void UnloadStateExt +( + RIVA_HW_INST *chip, + RIVA_HW_STATE *state +) +{ + /* + * Save current HW state. + */ + outb(0x19, 0x3D4); state->repaint0 = inb(0x3D5); + outb(0x1A, 0x3D4); state->repaint1 = inb(0x3D5); + outb(0x25, 0x3D4); state->screen = inb(0x3D5); + outb(0x28, 0x3D4); state->pixel = inb(0x3D5); + outb(0x2D, 0x3D4); state->horiz = inb(0x3D5); + outb(0x1B, 0x3D4); state->arbitration0 = inb(0x3D5); + outb(0x20, 0x3D4); state->arbitration1 = inb(0x3D5); + outb(0x30, 0x3D4); state->cursor0 = inb(0x3D5); + outb(0x31, 0x3D4); state->cursor1 = inb(0x3D5); + state->cursor2 = chip->PRAMDAC[0x00000300/4]; + state->vpll = chip->PRAMDAC[0x00000508/4]; + state->pllsel = chip->PRAMDAC[0x0000050C/4]; + state->general = chip->PRAMDAC[0x00000600/4]; + state->config = chip->PFB[0x00000200/4]; + switch (chip->Architecture) + { + case 3: + state->offset0 = chip->PGRAPH[0x00000630/4]; + state->offset1 = chip->PGRAPH[0x00000634/4]; + state->offset2 = chip->PGRAPH[0x00000638/4]; + state->offset3 = chip->PGRAPH[0x0000063C/4]; + state->pitch0 = chip->PGRAPH[0x00000650/4]; + state->pitch1 = chip->PGRAPH[0x00000654/4]; + state->pitch2 = chip->PGRAPH[0x00000658/4]; + state->pitch3 = chip->PGRAPH[0x0000065C/4]; + break; + case 4: + case 5: + state->offset0 = chip->PGRAPH[0x00000640/4]; + state->offset1 = chip->PGRAPH[0x00000644/4]; + state->offset2 = chip->PGRAPH[0x00000648/4]; + state->offset3 = chip->PGRAPH[0x0000064C/4]; + state->pitch0 = chip->PGRAPH[0x00000670/4]; + state->pitch1 = chip->PGRAPH[0x00000674/4]; + state->pitch2 = chip->PGRAPH[0x00000678/4]; + state->pitch3 = chip->PGRAPH[0x0000067C/4]; + break; + } +} +static void SetStartAddress +( + RIVA_HW_INST *chip, + unsigned start +) +{ + int offset = start >> 2; + int pan = (start & 3) << 1; + unsigned char tmp; + + /* + * Unlock extended registers. + */ + outb(chip->LockUnlockIndex, chip->LockUnlockIO); + outb(0x57, chip->LockUnlockIO + 1); + /* + * Set start address. + */ + outb(0x0D, 0x3D4); + outb(offset, 0x3D5); + outb(0x0C, 0x3D4); + outb(offset >> 8, 0x3D5); + outb(0x19, 0x3D4); + tmp = inb(0x3D5); + outb(((offset >> 16) & 0x0F) | (tmp & 0xF0), 0x3D5); + /* + * 4 pixel pan register. + */ + offset = inb(chip->IO + 0x0A); + outb(0x13, 0x3C0); + outb(pan, 0x3C0); +} +static void nv3SetSurfaces2D +( + RIVA_HW_INST *chip, + unsigned surf0, + unsigned surf1 +) +{ + while (nv3Busy(chip)); + chip->PGRAPH[0x00000630/4] = surf0; + chip->PGRAPH[0x00000634/4] = surf1; +} +static void nv4SetSurfaces2D +( + RIVA_HW_INST *chip, + unsigned surf0, + unsigned surf1 +) +{ + while (nv4Busy(chip)); + chip->PGRAPH[0x00000640/4] = surf0; + chip->PGRAPH[0x00000644/4] = surf1; +} +static void nv3SetSurfaces3D +( + RIVA_HW_INST *chip, + unsigned surf0, + unsigned surf1 +) +{ + while (nv3Busy(chip)); + chip->PGRAPH[0x00000638/4] = surf0; + chip->PGRAPH[0x0000063C/4] = surf1; +} +static void nv4SetSurfaces3D +( + RIVA_HW_INST *chip, + unsigned surf0, + unsigned surf1 +) +{ + while (nv4Busy(chip)); + chip->PGRAPH[0x00000648/4] = surf0; + chip->PGRAPH[0x0000064C/4] = surf1; +} + +/****************************************************************************\ +* * +* Probe RIVA Chip Configuration * +* * +\****************************************************************************/ + +void nv3GetConfig +( + RIVA_HW_INST *chip +) +{ + /* + * Fill in chip configuration. + */ + if (chip->PFB[0x00000000/4] & 0x00000020) + { + if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20) + && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02)) + { + /* + * SDRAM 128 ZX. + */ + chip->RamBandwidthKBytesPerSec = 800000; + switch (chip->PFB[0x00000000/4] & 0x03) + { + case 2: + chip->RamAmountKBytes = 1024 * 4 - 32; + break; + case 1: + chip->RamAmountKBytes = 1024 * 2 - 32; + break; + default: + chip->RamAmountKBytes = 1024 * 8 - 32; + break; + } + } + else + { + chip->RamBandwidthKBytesPerSec = 1000000; + chip->RamAmountKBytes = 1024 * 8 - 32; + } + } + else + { + /* + * SGRAM 128. + */ + chip->RamBandwidthKBytesPerSec = 1000000; + switch (chip->PFB[0x00000000/4] & 0x00000003) + { + case 0: + chip->RamAmountKBytes = 1024 * 8 - 32; + break; + case 2: + chip->RamAmountKBytes = 1024 * 4 - 32; + break; + default: + chip->RamAmountKBytes = 1024 * 2 - 32; + break; + } + } + chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000020) ? 14318 : 13500; + chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); + chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); + chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]); + chip->VBLANK = &(chip->PGRAPH[0x0100/4]); + chip->VBlankBit = 0x00000100; + chip->MaxVClockFreqKHz = 230000; + chip->LockUnlockIO = 0x3C4; + chip->LockUnlockIndex = 0x06; + /* + * Set chip functions. + */ + chip->Busy = nv3Busy; + chip->ShowHideCursor = ShowHideCursor; + chip->CalcStateExt = CalcStateExt; + chip->LoadStateExt = LoadStateExt; + chip->UnloadStateExt = UnloadStateExt; + chip->SetStartAddress = SetStartAddress; + chip->SetSurfaces2D = nv3SetSurfaces2D; + chip->SetSurfaces3D = nv3SetSurfaces3D; +} + +void nv4GetConfig +( + RIVA_HW_INST *chip +) +{ + /* + * Fill in chip configuration. + */ + switch (chip->PFB[0x00000000/4] & 0x00000003) + { + case 0: + chip->RamAmountKBytes = 1024 * 32 - 128; + break; + case 1: + chip->RamAmountKBytes = 1024 * 4 - 128; + break; + case 2: + chip->RamAmountKBytes = 1024 * 8 - 128; + break; + case 3: + default: + chip->RamAmountKBytes = 1024 * 16 - 128; + break; + } + switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) + { + case 3: + chip->RamBandwidthKBytesPerSec = 800000; + break; + default: + chip->RamBandwidthKBytesPerSec = 1000000; + break; + } + chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500; + chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); + chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); + chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); + chip->VBLANK = &(chip->PCRTC[0x0100/4]); + chip->VBlankBit = 0x00000001; + chip->MaxVClockFreqKHz = 250000; + chip->LockUnlockIO = 0x3D4; + chip->LockUnlockIndex = 0x1F; + /* + * Set chip functions. + */ + chip->Busy = nv4Busy; + chip->ShowHideCursor = ShowHideCursor; + chip->CalcStateExt = CalcStateExt; + chip->LoadStateExt = LoadStateExt; + chip->UnloadStateExt = UnloadStateExt; + chip->SetStartAddress = SetStartAddress; + chip->SetSurfaces2D = nv4SetSurfaces2D; + chip->SetSurfaces3D = nv4SetSurfaces3D; +} + +void nv5GetConfig +( + RIVA_HW_INST *chip +) +{ + /* + * Fill in chip configuration. + */ + switch (chip->PFB[0x00000000/4] & 0x00000003) + { + case 0: + chip->RamAmountKBytes = 1024 * 32 - 128; + break; + case 1: + chip->RamAmountKBytes = 1024 * 4 - 128; + break; + case 2: + chip->RamAmountKBytes = 1024 * 8 - 128; + break; + case 3: + default: + chip->RamAmountKBytes = 1024 * 16 - 128; + break; + } + switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) + { + case 3: + chip->RamBandwidthKBytesPerSec = 800000; + break; + default: + chip->RamBandwidthKBytesPerSec = 1000000; + break; + } + chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500; + chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); + chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); + chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); + chip->VBLANK = &(chip->PCRTC[0x0100/4]); + chip->VBlankBit = 0x00000001; + chip->MaxVClockFreqKHz = 250000; + chip->LockUnlockIO = 0x3D4; + chip->LockUnlockIndex = 0x1F; + /* + * Set chip functions. + */ + chip->Busy = nv4Busy; + chip->ShowHideCursor = ShowHideCursor; + chip->CalcStateExt = CalcStateExt; + chip->LoadStateExt = LoadStateExt; + chip->UnloadStateExt = UnloadStateExt; + chip->SetStartAddress = SetStartAddress; + chip->SetSurfaces2D = nv4SetSurfaces2D; + chip->SetSurfaces3D = nv4SetSurfaces3D; +} + +int RivaGetConfig +( + RIVA_HW_INST *chip +) +{ + /* + * Save this so future SW know whats it's dealing with. + */ + chip->Version = RIVA_SW_VERSION; + /* + * Chip specific configuration. + */ + switch (chip->Architecture) + { + case 3: + nv3GetConfig(chip); + break; + case 4: + nv4GetConfig(chip); + break; + case 5: + nv5GetConfig(chip); + default: + return (-1); + } + /* + * Fill in FIFO pointers. + */ + chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]); + chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]); + chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]); + chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]); + chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]); + chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]); + chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); + return (0); +} + diff --git a/drivers/video/riva_hw.h b/drivers/video/riva_hw.h new file mode 100644 index 000000000..6ab8395e5 --- /dev/null +++ b/drivers/video/riva_hw.h @@ -0,0 +1,343 @@ +/***************************************************************************\ +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NOTICE TO USER: The source code is copyrighted under U.S. and *| +|* international laws. Users and possessors of this source code are *| +|* hereby granted a nonexclusive, royalty-free copyright license to *| +|* use this code in individual and commercial software. *| +|* *| +|* Any use of this source code must include, in the user documenta- *| +|* tion and internal comments to the code, notices to the end user *| +|* as follows: *| +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| +|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| +|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| +|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| +|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| +|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| +|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| +|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| +|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| +|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| +|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| +|* *| +|* U.S. Government End Users. This source code is a "commercial *| +|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| +|* consisting of "commercial computer software" and "commercial *| +|* computer software documentation," as such terms are used in *| +|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| +|* ment only as a commercial end item. Consistent with 48 C.F.R. *| +|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| +|* all U.S. Government End Users acquire the source code with only *| +|* those rights set forth herein. *| +|* *| +\***************************************************************************/ +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of + * the documentation restriction above, to merely say that this nVidia's + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.h,v 1.1.2.2 1998/12/22 16:33:19 hohndel Exp $ */ +#ifndef __RIVA_HW_H__ +#define __RIVA_HW_H__ +#define RIVA_SW_VERSION 0x00010000 + +/***************************************************************************\ +* * +* FIFO registers. * +* * +\***************************************************************************/ + +/* + * Raster OPeration. Windows style ROP3. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop; + unsigned reserved01[0x0BB]; + unsigned Rop3; +} RivaRop; +/* + * 8X8 Monochrome pattern. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop; + unsigned reserved01[0x0BD]; + unsigned Shape; + unsigned reserved03[0x001]; + unsigned Color0; + unsigned Color1; + unsigned Monochrome[2]; +} RivaPattern; +/* + * Scissor clip rectangle. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop; + unsigned reserved01[0x0BB]; + unsigned TopLeft; + unsigned WidthHeight; +} RivaClip; +/* + * 2D filled rectangle. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop[1]; + unsigned reserved01[0x0BC]; + unsigned Color; + unsigned reserved03[0x03E]; + unsigned TopLeft; + unsigned WidthHeight; +} RivaRectangle; +/* + * 2D screen-screen BLT. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop; + unsigned reserved01[0x0BB]; + unsigned TopLeftSrc; + unsigned TopLeftDst; + unsigned WidthHeight; +} RivaScreenBlt; +/* + * 2D pixel BLT. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop[1]; + unsigned reserved01[0x0BC]; + unsigned TopLeft; + unsigned WidthHeight; + unsigned WidthHeightIn; + unsigned reserved02[0x03C]; + unsigned Pixels; +} RivaPixmap; +/* + * Filled rectangle combined with monochrome expand. Useful for glyphs. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop; + unsigned reserved01[0x0BB]; + unsigned reserved03[(0x040)-1]; + unsigned Color1A; + struct + { + unsigned TopLeft; + unsigned WidthHeight; + } UnclippedRectangle[64]; + unsigned reserved04[(0x080)-3]; + struct + { + unsigned TopLeft; + unsigned BottomRight; + } ClipB; + unsigned Color1B; + struct + { + unsigned TopLeft; + unsigned BottomRight; + } ClippedRectangle[64]; + unsigned reserved05[(0x080)-5]; + struct + { + unsigned TopLeft; + unsigned BottomRight; + } ClipC; + unsigned Color1C; + unsigned WidthHeightC; + unsigned PointC; + unsigned MonochromeData1C; + unsigned reserved06[(0x080)+121]; + struct + { + unsigned TopLeft; + unsigned BottomRight; + } ClipD; + unsigned Color1D; + unsigned WidthHeightInD; + unsigned WidthHeightOutD; + unsigned PointD; + unsigned MonochromeData1D; + unsigned reserved07[(0x080)+120]; + struct + { + unsigned TopLeft; + unsigned BottomRight; + } ClipE; + unsigned Color0E; + unsigned Color1E; + unsigned WidthHeightInE; + unsigned WidthHeightOutE; + unsigned PointE; + unsigned MonochromeData01E; +} RivaBitmap; +/* + * 3D textured, Z buffered triangle. + */ +typedef volatile struct +{ + unsigned reserved00[4]; + unsigned short FifoFree; + unsigned short Nop; + unsigned reserved01[0x0BC]; + unsigned TextureOffset; + unsigned TextureFormat; + unsigned TextureFilter; + unsigned FogColor; + unsigned Control; + unsigned AlphaTest; + unsigned reserved02[0x339]; + unsigned FogAndIndex; + unsigned Color; + float ScreenX; + float ScreenY; + float ScreenZ; + float EyeM; + float TextureS; + float TextureT; +} RivaTexturedTriangle03; + +/***************************************************************************\ +* * +* Virtualized RIVA H/W interface. * +* * +\***************************************************************************/ + +struct _riva_hw_inst; +struct _riva_hw_state; +/* + * Virtialized chip interface. Makes RIVA 128 and TNT look alike. + */ +typedef struct _riva_hw_inst +{ + /* + * Chip specific settings. + */ + unsigned Architecture; + unsigned Version; + unsigned CrystalFreqKHz; + unsigned RamAmountKBytes; + unsigned MaxVClockFreqKHz; + unsigned RamBandwidthKBytesPerSec; + unsigned EnableIRQ; + unsigned IO; + unsigned LockUnlockIO; + unsigned LockUnlockIndex; + unsigned VBlankBit; + unsigned FifoFreeCount; + /* + * Non-FIFO registers. + */ + volatile unsigned *PCRTC; + volatile unsigned *PRAMDAC; + volatile unsigned *PFB; + volatile unsigned *PFIFO; + volatile unsigned *PGRAPH; + volatile unsigned *PEXTDEV; + volatile unsigned *PTIMER; + volatile unsigned *PMC; + volatile unsigned *PRAMIN; + volatile unsigned *FIFO; + volatile unsigned *CURSOR; + volatile unsigned *CURSORPOS; + volatile unsigned *VBLANKENABLE; + volatile unsigned *VBLANK; + /* + * Common chip functions. + */ + int (*Busy)(struct _riva_hw_inst *); + void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int); + void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); + void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); + void (*SetStartAddress)(struct _riva_hw_inst *,unsigned); + void (*SetSurfaces2D)(struct _riva_hw_inst *,unsigned,unsigned); + void (*SetSurfaces3D)(struct _riva_hw_inst *,unsigned,unsigned); + int (*ShowHideCursor)(struct _riva_hw_inst *,int); + /* + * Current extended mode settings. + */ + struct _riva_hw_state *CurrentState; + /* + * FIFO registers. + */ + RivaRop *Rop; + RivaPattern *Patt; + RivaClip *Clip; + RivaPixmap *Pixmap; + RivaScreenBlt *Blt; + RivaBitmap *Bitmap; + RivaTexturedTriangle03 *Tri03; +} RIVA_HW_INST; +/* + * Extended mode state information. + */ +typedef struct _riva_hw_state +{ + unsigned bpp; + unsigned width; + unsigned height; + unsigned repaint0; + unsigned repaint1; + unsigned screen; + unsigned pixel; + unsigned horiz; + unsigned arbitration0; + unsigned arbitration1; + unsigned vpll; + unsigned pllsel; + unsigned general; + unsigned config; + unsigned cursor0; + unsigned cursor1; + unsigned cursor2; + unsigned offset0; + unsigned offset1; + unsigned offset2; + unsigned offset3; + unsigned pitch0; + unsigned pitch1; + unsigned pitch2; + unsigned pitch3; +} RIVA_HW_STATE; +/* + * External routines. + */ +int RivaGetConfig(RIVA_HW_INST *); +/* + * FIFO Free Count. Should attempt to yield processor if RIVA is busy. + */ +#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ +{ \ +while ((hwinst).FifoFreeCount < (cnt)) \ +{ \ + (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \ +} \ +(hwinst).FifoFreeCount -= (cnt); \ +} +#endif /* __RIVA_HW_H__ */ + diff --git a/drivers/video/riva_tbl.h b/drivers/video/riva_tbl.h new file mode 100644 index 000000000..8188c0fd8 --- /dev/null +++ b/drivers/video/riva_tbl.h @@ -0,0 +1,402 @@ + /***************************************************************************\ +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NOTICE TO USER: The source code is copyrighted under U.S. and *| +|* international laws. Users and possessors of this source code are *| +|* hereby granted a nonexclusive, royalty-free copyright license to *| +|* use this code in individual and commercial software. *| +|* *| +|* Any use of this source code must include, in the user documenta- *| +|* tion and internal comments to the code, notices to the end user *| +|* as follows: *| +|* *| +|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* *| +|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| +|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| +|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| +|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| +|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| +|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| +|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| +|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| +|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| +|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| +|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| +|* *| +|* U.S. Government End Users. This source code is a "commercial *| +|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| +|* consisting of "commercial computer software" and "commercial *| +|* computer software documentation," as such terms are used in *| +|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| +|* ment only as a commercial end item. Consistent with 48 C.F.R. *| +|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| +|* all U.S. Government End Users acquire the source code with only *| +|* those rights set forth herein. *| +|* *| + \***************************************************************************/ +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of + * the documentation restriction above, to merely say that this nVidia's + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_tbl.h,v 1.1.2.2 1998/12/22 16:33:20 hohndel Exp $ */ +/* + * RIVA Fixed Functionality Init Tables. + */ +static unsigned RivaTablePMC[][2] = +{ + {0x00000050, 0x00000000}, + {0x00000080, 0xFFFF00FF}, + {0x00000080, 0xFFFFFFFF} +}; +static unsigned RivaTablePTIMER[][2] = +{ + {0x00000080, 0x00000008}, + {0x00000084, 0x00000003}, + {0x00000050, 0x00000000}, + {0x00000040, 0xFFFFFFFF} +}; +static unsigned RivaTableFIFO[][2] = +{ + {0x00000000, 0x80000000}, + {0x00000800, 0x80000001}, + {0x00001000, 0x80000002}, + {0x00001800, 0x80000010}, + {0x00002000, 0x80000011}, + {0x00002800, 0x80000012}, + {0x00003800, 0x80000013} +}; +static unsigned nv3TablePFIFO[][2] = +{ + {0x00000140, 0x00000000}, + {0x00000480, 0x00000000}, + {0x00000490, 0x00000000}, + {0x00000494, 0x00000000}, + {0x00000481, 0x00000000}, + {0x00000084, 0x00000000}, + {0x00000086, 0x00002000}, + {0x00000085, 0x00002200}, + {0x00000484, 0x00000000}, + {0x0000049C, 0x00000000}, + {0x00000104, 0x00000000}, + {0x00000108, 0x00000000}, + {0x00000100, 0x00000000}, + {0x000004A0, 0x00000000}, + {0x000004A4, 0x00000000}, + {0x000004A8, 0x00000000}, + {0x000004AC, 0x00000000}, + {0x000004B0, 0x00000000}, + {0x000004B4, 0x00000000}, + {0x000004B8, 0x00000000}, + {0x000004BC, 0x00000000}, + {0x00000050, 0x00000000}, + {0x00000040, 0xFFFFFFFF}, + {0x00000480, 0x00000001}, + {0x00000490, 0x00000001}, + {0x00000140, 0x00000001} +}; +static unsigned nv3TablePGRAPH[][2] = +{ + {0x00000020, 0x1230001F}, + {0x00000021, 0x10113000}, + {0x00000022, 0x1131F101}, + {0x00000023, 0x0100F531}, + {0x00000060, 0x00000000}, + {0x00000065, 0x00000000}, + {0x00000068, 0x00000000}, + {0x00000069, 0x00000000}, + {0x0000006A, 0x00000000}, + {0x0000006B, 0x00000000}, + {0x0000006C, 0x00000000}, + {0x0000006D, 0x00000000}, + {0x0000006E, 0x00000000}, + {0x0000006F, 0x00000000}, + {0x000001A8, 0x00000000}, + {0x00000440, 0xFFFFFFFF}, + {0x00000480, 0x00000001}, + {0x000001A0, 0x00000000}, + {0x000001A2, 0x00000000}, + {0x0000018A, 0xFFFFFFFF}, + {0x00000190, 0x00000000}, + {0x00000142, 0x00000000}, + {0x00000154, 0x00000000}, + {0x00000155, 0xFFFFFFFF}, + {0x00000156, 0x00000000}, + {0x00000157, 0xFFFFFFFF}, + {0x00000064, 0x10010002}, + {0x00000050, 0x00000000}, + {0x00000051, 0x00000000}, + {0x00000040, 0xFFFFFFFF}, + {0x00000041, 0xFFFFFFFF}, + {0x00000440, 0xFFFFFFFF}, + {0x000001A9, 0x00000001} +}; +static unsigned nv3TablePGRAPH_8BPP[][2] = +{ + {0x000001AA, 0x00001111} +}; +static unsigned nv3TablePGRAPH_15BPP[][2] = +{ + {0x000001AA, 0x00002222} +}; +static unsigned nv3TablePGRAPH_32BPP[][2] = +{ + {0x000001AA, 0x00003333} +}; +static unsigned nv3TablePRAMIN[][2] = +{ + {0x00000500, 0x00010000}, + {0x00000501, 0x007FFFFF}, + {0x00000200, 0x80000000}, + {0x00000201, 0x00C20341}, + {0x00000204, 0x80000001}, + {0x00000205, 0x00C50342}, + {0x00000208, 0x80000002}, + {0x00000209, 0x00C60343}, + {0x00000240, 0x80000010}, + {0x00000241, 0x00D10344}, + {0x00000244, 0x80000011}, + {0x00000245, 0x00D00345}, + {0x00000248, 0x80000012}, + {0x00000249, 0x00CC0346}, + {0x0000024C, 0x80000013}, + {0x0000024D, 0x00D70347}, + {0x00000D05, 0x00000000}, + {0x00000D06, 0x00000000}, + {0x00000D07, 0x00000000}, + {0x00000D09, 0x00000000}, + {0x00000D0A, 0x00000000}, + {0x00000D0B, 0x00000000}, + {0x00000D0D, 0x00000000}, + {0x00000D0E, 0x00000000}, + {0x00000D0F, 0x00000000}, + {0x00000D11, 0x00000000}, + {0x00000D12, 0x00000000}, + {0x00000D13, 0x00000000}, + {0x00000D15, 0x00000000}, + {0x00000D16, 0x00000000}, + {0x00000D17, 0x00000000}, + {0x00000D19, 0x00000000}, + {0x00000D1A, 0x00000000}, + {0x00000D1B, 0x00000000}, + {0x00000D1D, 0x00000140}, + {0x00000D1E, 0x00000000}, + {0x00000D1F, 0x00000000} +}; +static unsigned nv3TablePRAMIN_8BPP[][2] = +{ + {0x00000D04, 0x10110203}, + {0x00000D08, 0x10110203}, + {0x00000D0C, 0x10110203}, + {0x00000D10, 0x10118203}, + {0x00000D14, 0x10110203}, + {0x00000D18, 0x10110203}, + {0x00000D1C, 0x10419208} +}; +static unsigned nv3TablePRAMIN_15BPP[][2] = +{ + {0x00000D04, 0x10110200}, + {0x00000D08, 0x10110200}, + {0x00000D0C, 0x10110200}, + {0x00000D10, 0x10118200}, + {0x00000D14, 0x10110200}, + {0x00000D18, 0x10110200}, + {0x00000D1C, 0x10419208} +}; +static unsigned nv3TablePRAMIN_32BPP[][2] = +{ + {0x00000D04, 0x10110201}, + {0x00000D08, 0x10110201}, + {0x00000D0C, 0x10110201}, + {0x00000D10, 0x10118201}, + {0x00000D14, 0x10110201}, + {0x00000D18, 0x10110201}, + {0x00000D1C, 0x10419208} +}; +static unsigned nv4TablePFIFO[][2] = +{ + {0x00000140, 0x00000000}, + {0x00000480, 0x00000000}, + {0x00000494, 0x00000000}, + {0x00000400, 0x00000000}, + {0x00000414, 0x00000000}, + {0x00000084, 0x03000100}, + {0x00000085, 0x00000110}, + {0x00000086, 0x00000112}, + {0x00000143, 0x0000FFFF}, + {0x00000496, 0x0000FFFF}, + {0x00000050, 0x00000000}, + {0x00000040, 0xFFFFFFFF}, + {0x00000415, 0x00000001}, + {0x00000480, 0x00000001}, + {0x00000494, 0x00000001}, + {0x00000495, 0x00000001}, + {0x00000140, 0x00000001} +}; +static unsigned nv4TablePGRAPH[][2] = +{ + {0x00000020, 0x1231C001}, + {0x00000021, 0x72111101}, + {0x00000022, 0x11D5F071}, + {0x00000023, 0x10D4FF31}, + {0x00000060, 0x00000000}, + {0x00000068, 0x00000000}, + {0x00000070, 0x00000000}, + {0x00000078, 0x00000000}, + {0x00000061, 0x00000000}, + {0x00000069, 0x00000000}, + {0x00000071, 0x00000000}, + {0x00000079, 0x00000000}, + {0x00000062, 0x00000000}, + {0x0000006A, 0x00000000}, + {0x00000072, 0x00000000}, + {0x0000007A, 0x00000000}, + {0x00000063, 0x00000000}, + {0x0000006B, 0x00000000}, + {0x00000073, 0x00000000}, + {0x0000007B, 0x00000000}, + {0x00000064, 0x00000000}, + {0x0000006C, 0x00000000}, + {0x00000074, 0x00000000}, + {0x0000007C, 0x00000000}, + {0x00000065, 0x00000000}, + {0x0000006D, 0x00000000}, + {0x00000075, 0x00000000}, + {0x0000007D, 0x00000000}, + {0x00000066, 0x00000000}, + {0x0000006E, 0x00000000}, + {0x00000076, 0x00000000}, + {0x0000007E, 0x00000000}, + {0x00000067, 0x00000000}, + {0x0000006F, 0x00000000}, + {0x00000077, 0x00000000}, + {0x0000007F, 0x00000000}, + {0x00000058, 0x00000000}, + {0x00000059, 0x00000000}, + {0x0000005A, 0x00000000}, + {0x0000005B, 0x00000000}, + {0x00000196, 0x00000000}, + {0x000001A1, 0x00FFFFFF}, + {0x00000197, 0x00000000}, + {0x000001A2, 0x00FFFFFF}, + {0x00000198, 0x00000000}, + {0x000001A3, 0x00FFFFFF}, + {0x00000199, 0x00000000}, + {0x000001A4, 0x00FFFFFF}, + {0x00000050, 0x00000000}, + {0x00000040, 0xFFFFFFFF}, + {0x0000005C, 0x10010100}, + {0x000001C8, 0x00000001} +}; +static unsigned nv4TablePGRAPH_8BPP[][2] = +{ + {0x000001C4, 0xFFFFFFFF}, + {0x000001C9, 0x00111111}, + {0x00000186, 0x00001010}, + {0x0000020C, 0x01010101} +}; +static unsigned nv4TablePGRAPH_15BPP[][2] = +{ + {0x000001C4, 0xFFFFFFFF}, + {0x000001C9, 0x00226222}, + {0x00000186, 0x00002071}, + {0x0000020C, 0x09090909} +}; +static unsigned nv4TablePGRAPH_16BPP[][2] = +{ + {0x000001C4, 0xFFFFFFFF}, + {0x000001C9, 0x00556555}, + {0x00000186, 0x000050C2}, + {0x0000020C, 0x0C0C0C0C} +}; +static unsigned nv4TablePGRAPH_32BPP[][2] = +{ + {0x000001C4, 0xFFFFFFFF}, + {0x000001C9, 0x0077D777}, + {0x00000186, 0x000070E5}, + {0x0000020C, 0x07070707} +}; +static unsigned nv4TablePRAMIN[][2] = +{ + {0x00000000, 0x80000010}, + {0x00000001, 0x80011145}, + {0x00000002, 0x80000011}, + {0x00000003, 0x80011146}, + {0x00000004, 0x80000012}, + {0x00000005, 0x80011147}, + {0x00000006, 0x80000013}, + {0x00000007, 0x80011148}, + {0x00000020, 0x80000000}, + {0x00000021, 0x80011142}, + {0x00000022, 0x80000001}, + {0x00000023, 0x80011143}, + {0x00000024, 0x80000002}, + {0x00000025, 0x80011144}, + {0x00000500, 0x00003000}, + {0x00000501, 0x02FFFFFF}, + {0x00000502, 0x00000002}, + {0x00000503, 0x00000002}, + {0x00000508, 0x01008043}, + {0x0000050A, 0x00000000}, + {0x0000050B, 0x00000000}, + {0x0000050C, 0x01008019}, + {0x0000050E, 0x00000000}, + {0x0000050F, 0x00000000}, + {0x00000510, 0x01008018}, + {0x00000512, 0x00000000}, + {0x00000513, 0x00000000}, + {0x00000514, 0x0100A033}, + {0x00000516, 0x00000000}, + {0x00000517, 0x00000000}, + {0x00000518, 0x0100805F}, + {0x0000051A, 0x00000000}, + {0x0000051B, 0x00000000}, + {0x0000051C, 0x0100804B}, + {0x0000051E, 0x00000000}, + {0x0000051F, 0x00000000}, + {0x00000520, 0x0100A048}, + {0x00000521, 0x00000D01}, + {0x00000522, 0x11401140}, + {0x00000523, 0x00000000} +}; +static unsigned nv4TablePRAMIN_8BPP[][2] = +{ + {0x00000509, 0x00000301}, + {0x0000050D, 0x00000301}, + {0x00000511, 0x00000301}, + {0x00000515, 0x00000301}, + {0x00000519, 0x00000301}, + {0x0000051D, 0x00000301} +}; +static unsigned nv4TablePRAMIN_15BPP[][2] = +{ + {0x00000509, 0x00000901}, + {0x0000050D, 0x00000901}, + {0x00000511, 0x00000901}, + {0x00000515, 0x00000901}, + {0x00000519, 0x00000901}, + {0x0000051D, 0x00000901} +}; +static unsigned nv4TablePRAMIN_16BPP[][2] = +{ + {0x00000509, 0x00000C01}, + {0x0000050D, 0x00000C01}, + {0x00000511, 0x00000C01}, + {0x00000515, 0x00000C01}, + {0x00000519, 0x00000C01}, + {0x0000051D, 0x00000C01} +}; +static unsigned nv4TablePRAMIN_32BPP[][2] = +{ + {0x00000509, 0x00000E01}, + {0x0000050D, 0x00000E01}, + {0x00000511, 0x00000E01}, + {0x00000515, 0x00000E01}, + {0x00000519, 0x00000E01}, + {0x0000051D, 0x00000E01} +}; + diff --git a/drivers/video/rivafb.c b/drivers/video/rivafb.c new file mode 100644 index 000000000..134d85d17 --- /dev/null +++ b/drivers/video/rivafb.c @@ -0,0 +1,1890 @@ +/* + * linux/drivers/video/rivafb.c - nVidia RIVA 128/TNT/TNT2 fb driver + * + * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> + * + * Contributors: + * + * ani joshi: Lots of debugging and cleanup work, really helped + * get the driver going + * + * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven + * Includes riva_hw.c from nVidia, see copyright below. + * KGI code provided the basis for state storage, init, and mode switching. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file README.legal in the main directory of this archive + * for more details. + */ + +/* version number of this driver */ +#define RIVAFB_VERSION "0.6.5" + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <linux/selection.h> +#include <linux/tty.h> +#include <linux/malloc.h> +#include <linux/delay.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/pci.h> + +#include <video/fbcon.h> + +#include "riva_hw.h" +#include "nv4ref.h" +#include "nvreg.h" +#include "vga.h" +#include <video/fbcon-cfb4.h> +#include <video/fbcon-cfb8.h> +#include <video/fbcon-cfb16.h> +#include <video/fbcon-cfb32.h> + +#ifndef CONFIG_PCI /* sanity check */ +#error This driver requires PCI support. +#endif + +/***************************************************************** + * + * various helpful macros and constants + * + */ + +/* #define RIVAFBDEBUG */ +#ifdef RIVAFBDEBUG +#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args) +#else +#define DPRINTK(fmt, args...) +#endif + +#ifndef RIVA_NDEBUG +#define assert(expr) \ + if(!(expr)) { \ + printk( "Assertion failed! %s,%s,%s,line=%d\n",\ + #expr,__FILE__,__FUNCTION__,__LINE__); \ + *(int*)0 = 0; \ + } +#else +#define assert(expr) +#endif + +/* GGI compatibility macros */ +#define io_out8 outb +#define io_in8 inb +#define FatalError panic +#define NUM_SEQ_REGS 0x05 +#define NUM_CRT_REGS 0x41 +#define NUM_GRC_REGS 0x09 +#define NUM_ATC_REGS 0x15 + +/* max number of VGA controllers we scan for */ +#define RIVA_MAX_VGA_CONTROLLERS 8 + +#define PFX "rivafb: " + +#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) + +/* macro that allows you to set overflow bits */ +#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) +#define SetBit(n) (1<<(n)) +#define Set8Bits(value) ((value)&0xff) + +struct riva_chip_info { + const char *name; + unsigned arch_rev; + unsigned short vendor; + unsigned short device; +}; + + +static const struct riva_chip_info riva_pci_probe_list[] = +{ + {"RIVA-128", 3, PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128}, + {"RIVA-TNT", 4, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT}, + {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2}, + {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2}, + {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2}, + {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2}, + {NULL, 0, 0, 0} +}; + + +/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. + * From KGI originally. */ +struct riva_regs { + u8 attr[0x15]; + u8 crtc[0x41]; + u8 gra[0x09]; + u8 seq[0x05]; + u8 misc_output; + RIVA_HW_STATE ext; +}; + + +/* + * describes the state of a Riva board + */ +struct rivafb_par { + struct riva_regs state; /* state of hw board */ + __u32 visual; /* FB_VISUAL_xxx */ + unsigned depth; /* bpp of current mode */ +}; + +typedef struct { + unsigned char red, green, blue, transp; +} riva_cfb8_cmap_t; + + + +struct rivafb_info; +struct rivafb_info { + struct fb_info info; /* kernel framebuffer info */ + + RIVA_HW_INST riva; /* interface to riva_hw.c */ + + const char *drvr_name; /* Riva hardware board type */ + + unsigned long ctrl_base_phys; /* physical control register base addr */ + unsigned long fb_base_phys; /* physical framebuffer base addr */ + + caddr_t ctrl_base; /* virtual control register base addr */ + caddr_t fb_base; /* virtual framebuffer base addr */ + + unsigned ram_amount; /* amount of RAM on card, in megabytes */ + unsigned dclk_max; /* max DCLK */ + + struct riva_regs initial_state; /* initial startup video mode */ + + struct display disp; + int currcon; + struct display *currcon_display; + + struct rivafb_info *next; + + struct pci_dev *pd; /* pointer to board's pci info */ + unsigned base0_region_size; /* size of control register region */ + unsigned base1_region_size; /* size of framebuffer region */ + +#ifdef FBCON_HAS_CFB8 + riva_cfb8_cmap_t palette[256]; /* VGA DAC palette cache */ +#endif + +#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) + union { +#ifdef FBCON_HAS_CFB16 + u_int16_t cfb16[16]; +#endif +#ifdef FBCON_HAS_CFB32 + u_int32_t cfb32[16]; +#endif + } con_cmap; +#endif /* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */ +}; + +/* ------------------- global variables ------------------------ */ + + +static struct rivafb_info *riva_boards = NULL; + +/* command line data, set in rivafb_setup() */ +static char fontname[40] __initdata = { 0 }; +static char noaccel __initdata = 0; /* unused */ +#ifndef MODULE +static const char *mode_option __initdata = NULL; +#endif + + +/* ------------------- prototypes ------------------------------ */ + +int rivafb_open (struct fb_info *info, int user); +int rivafb_release (struct fb_info *info, int user); +int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, + struct fb_info *info); +int rivafb_get_var (struct fb_var_screeninfo *var, int con, + struct fb_info *info); +int rivafb_set_var (struct fb_var_screeninfo *var, int con, + struct fb_info *info); +int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con, + struct fb_info *info); +int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, + struct fb_info *info); +int rivafb_pan_display (struct fb_var_screeninfo *var, int con, + struct fb_info *info); +int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, + unsigned long arg, int con, struct fb_info *info); +int rivafb_switch(int con, struct fb_info *info); +void rivafb_blank (int blank, struct fb_info *info); + +static void riva_load_video_mode (struct rivafb_info *rivainfo, + struct fb_var_screeninfo *video_mode); +static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green, + unsigned *blue, unsigned *transp, + struct fb_info *info); +static int riva_setcolreg (unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info); +static int riva_get_cmap_len(const struct fb_var_screeninfo *var); + +static u32 riva_pci_region_size (struct pci_dev *pd, unsigned baseaddr); + +static void riva_pci_iounmap (struct rivafb_info *rinfo); +static int riva_pci_register (struct pci_dev *pd, const struct riva_chip_info *rci); +static int riva_pci_register_devices (void); +static int riva_set_fbinfo (struct rivafb_info *rinfo); + +static +void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs); +static +void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs); +static +struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list, + struct rivafb_info *new_node); + +#if 0 +static void riva_pci_region_init (struct pci_dev *pd, struct rivafb_info *rinfo); +#endif + +static void riva_wclut (unsigned char regnum, unsigned char red, + unsigned char green, unsigned char blue); + + + + +/* kernel interface */ +static struct fb_ops riva_fb_ops = +{ + rivafb_open, + rivafb_release, + rivafb_get_fix, + rivafb_get_var, + rivafb_set_var, + rivafb_get_cmap, + rivafb_set_cmap, + rivafb_pan_display, + rivafb_ioctl +}; + + + + +/* from GGI */ +static const struct riva_regs reg_template = +{ + { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x41, 0x01, 0x0F, 0x13, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ + 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, /* 0x40 */ + }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ + 0xFF }, + { 0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ + 0xEB /* MISC */ +}; + + + +/* ------------------- general utility functions -------------------------- */ + +/** + * riva_set_dispsw + * @rivainfo: pointer to internal driver struct for a given Riva card + * + * DESCRIPTION: + * Sets up console Low level operations depending on the current? color depth + * of the display + */ + +void riva_set_dispsw (struct rivafb_info *rinfo) +{ + struct display *disp = &rinfo->disp; + + DPRINTK ("ENTER\n"); + + assert (rinfo != NULL); + + disp->dispsw_data = NULL; + + switch (disp->var.bits_per_pixel) { +#ifdef FBCON_HAS_MFB + case 1: + disp->dispsw = &fbcon_mfb; + break; +#endif +#ifdef FBCON_HAS_CFB4 + case 4: + disp->dispsw = &fbcon_cfb4; + break; +#endif +#ifdef FBCON_HAS_CFB8 + case 8: + disp->dispsw = &fbcon_cfb8; + break; +#endif +#ifdef FBCON_HAS_CFB16 + case 15: + case 16: + disp->dispsw = &fbcon_cfb16; + disp->dispsw_data = &rinfo->con_cmap.cfb16; + break; +#endif +#ifdef FBCON_HAS_CFB24 + case 24: + disp->dispsw = &fbcon_cfb24; + disp->dispsw_data = rinfo->con_cmap.cfb24; + break; +#endif +#ifdef FBCON_HAS_CFB32 + case 32: + disp->dispsw = &fbcon_cfb32; + disp->dispsw_data = rinfo->con_cmap.cfb32; + break; +#endif + default: + DPRINTK ("Setting fbcon_dummy renderer\n"); + disp->dispsw = &fbcon_dummy; + } + + DPRINTK ("EXIT\n"); +} + + + + +static int riva_init_disp_var (struct rivafb_info *rinfo) +{ + if (mode_option) + fb_find_mode(&rinfo->disp.var, &rinfo->info, mode_option, + NULL, 0, NULL, 8); + else + fb_find_mode(&rinfo->disp.var, &rinfo->info, + "640x480-8@60", NULL, 0, NULL, 8); + return 0; +} + + + + +static int __init riva_init_disp (struct rivafb_info *rinfo) +{ + struct fb_info *info; + struct display *disp; + + DPRINTK("ENTER\n"); + + assert (rinfo != NULL); + + info = &rinfo->info; + disp = &rinfo->disp; + + info->disp = disp; + +#warning FIXME: assure that disp->cmap is completely filled out + + disp->screen_base = rinfo->fb_base; + disp->visual = FB_VISUAL_PSEUDOCOLOR; + disp->type = FB_TYPE_PACKED_PIXELS; + disp->type_aux = 0; + disp->ypanstep = 1; + disp->ywrapstep = 0; + disp->next_line = disp->line_length = + (disp->var.xres_virtual * disp->var.bits_per_pixel) >> 3; + disp->can_soft_blank = 1; + disp->inverse = 0; + + riva_set_dispsw(rinfo); + + rinfo->currcon_display = disp; + + if ((riva_init_disp_var (rinfo)) < 0) { /* must be done last */ + DPRINTK("EXIT, returning -1\n"); + return -1; + } + + DPRINTK("EXIT, returning 0\n"); + return 0; + +} + + + +static int __init riva_set_fbinfo (struct rivafb_info *rinfo) +{ + struct fb_info *info; + + assert (rinfo != NULL); + + info = &rinfo->info; + + strcpy (info->modename, rinfo->drvr_name); + info->node = -1; + info->flags = FBINFO_FLAG_DEFAULT; + info->fbops = &riva_fb_ops; + +#warning FIXME: set monspecs to what??? + + info->display_fg = NULL; /* FIXME: correct? */ + strncpy (info->fontname, fontname, sizeof (info->fontname)); + info->fontname[sizeof (info->fontname) - 1] = 0; + + info->changevar = NULL; /* FIXME: needed? */ + info->switch_con = rivafb_switch; + info->updatevar = NULL; /* FIXME? */ + info->blank = rivafb_blank; + + if (riva_init_disp (rinfo) < 0) /* must be done last */ + return -1; + + return 0; +} + + + + +/* ----------------------------- PCI bus ----------------------------- */ + + + + +/** + * riva_pci_region_size + * @pd: pointer to PCI device to be configured + * + * DESCRIPTION: + * Obtains from the PCI bus the size of the address space allocated to + * the given card's base address zero region. + */ + +static +u32 riva_pci_region_size (struct pci_dev *pd, unsigned baseaddr) +{ + return pd->resource[baseaddr].end - pd->resource[baseaddr].start + 1; +} + + + + +#if 0 + +/** + * riva_pci_iomap + * @nv: + * + * DESCRIPTION: + */ + +static +void riva_pci_region_init (struct pci_dev *pd, struct rivafb_info *rinfo) +{ + unsigned long addr; + + assert (rinfo != NULL); + assert (pd != NULL); + + rinfo->pd = pd; + rinfo->base0_region_size = riva_pci_region_size (pd, PCI_BASE_ADDRESS_0); + assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */ + rinfo->base1_region_size = riva_pci_region_size (pd, PCI_BASE_ADDRESS_1); + assert(rinfo->base0_region_size >= 0x01000000); /* from GGI */ + + /* Get the base addresses */ + pcibios_read_config_dword(0, rinfo->pd->devfn, PCI_BASE_ADDRESS_0, + (unsigned int*)&addr); +#ifdef SHOULDUSETHAT + /* This function should return an int. */ + if (!addr) + return -ENXIO; +#endif + + rinfo->ctrl_base_phys = addr & PCI_BASE_ADDRESS_MEM_MASK; + + pcibios_read_config_dword(0, rinfo->pd->devfn, PCI_BASE_ADDRESS_1, + (unsigned int*)&addr); + + rinfo->fb_base_phys = addr & PCI_BASE_ADDRESS_MEM_MASK; + + rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys, rinfo->base0_region_size); + assert (rinfo->ctrl_base != NULL); + rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->base1_region_size); + assert (rinfo->fb_base != NULL); + + rinfo->riva.EnableIRQ = 0; + rinfo->riva.IO = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; + rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base+0x00680000); + rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base+0x00100000); + rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base+0x00002000); + rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base+0x00400000); + rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base+0x00101000); + rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base+0x00009000); + rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base+0x00000000); + rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base+0x00800000); + + switch (rinfo->riva.Architecture) + { + case 3: + rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00C00000); + break; + case 4: + case 5: + rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base+0x00600000); + rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00710000); + break; + } +} + +#endif /* 0 */ + + + +/** + * riva_pci_iounmap + * @rinfo: + * + * DESCRIPTION: + */ + +static +void riva_pci_iounmap (struct rivafb_info *rinfo) +{ + assert (rinfo != NULL); + assert (rinfo->ctrl_base_phys != 0x00000000); + assert (rinfo->ctrl_base != NULL); + assert (rinfo->fb_base_phys != 0x00000000); + assert (rinfo->fb_base != NULL); + + iounmap (rinfo->ctrl_base); + iounmap (rinfo->fb_base); +} + + + + + +static void __init riva_init_clut (struct rivafb_info *fb_info) +{ + int j, k; + + for (j = 0; j < 256; j++) { + if (j < 16) { + k = color_table[j]; + fb_info->palette[j].red = default_red[k]; + fb_info->palette[j].green = default_grn[k]; + fb_info->palette[j].blue = default_blu[k]; + } else { + fb_info->palette[j].red = + fb_info->palette[j].green = + fb_info->palette[j].blue = j; + } + + riva_wclut (j, + fb_info->palette[j].red, + fb_info->palette[j].green, + fb_info->palette[j].blue); + } +} + + + +static int __init riva_pci_register (struct pci_dev *pd, + const struct riva_chip_info *rci) +{ + struct rivafb_info *rinfo; + + assert (pd != NULL); + assert (rci != NULL); + + rinfo = kmalloc (sizeof (struct rivafb_info), GFP_KERNEL); + assert (rinfo != NULL); + memset (rinfo, 0, sizeof (struct rivafb_info)); + + rinfo->drvr_name = rci->name; + rinfo->riva.Architecture = rci->arch_rev; + + rinfo->pd = pd; + rinfo->base0_region_size = riva_pci_region_size (pd, 0); + rinfo->base1_region_size = riva_pci_region_size (pd, 1); + + assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */ + assert(rinfo->base0_region_size >= 0x01000000); /* from GGI */ + + rinfo->ctrl_base_phys = rinfo->pd->resource[0].start; + rinfo->fb_base_phys = rinfo->pd->resource[1].start; + + __request_region(&ioport_resource, 0x3C0, 32, "rivafb"); + + if (!__request_region (&iomem_resource, rinfo->ctrl_base_phys, + rinfo->base0_region_size, "rivafb") || + !__request_region (&iomem_resource, rinfo->fb_base_phys, + rinfo->base1_region_size, "rivafb")) { + printk (KERN_ERR PFX "cannot reserve MMIO region\n"); + return -ENXIO; + } + + rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys, + rinfo->base0_region_size); + assert (rinfo->ctrl_base != NULL); + + rinfo->fb_base = ioremap (rinfo->fb_base_phys, + rinfo->base1_region_size); + assert (rinfo->fb_base != NULL); + + rinfo->riva.EnableIRQ = 0; + rinfo->riva.IO = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; + rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base+0x00680000); + rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base+0x00100000); + rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base+0x00002000); + rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base+0x00400000); + rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base+0x00101000); + rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base+0x00009000); + rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base+0x00000000); + rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base+0x00800000); + + switch (rinfo->riva.Architecture) + { + case 3: + rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00C00000); + break; + case 4: + case 5: + rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base+0x00600000); + rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00710000); + break; + } + + RivaGetConfig(&rinfo->riva); + + /* back to normal */ + + assert (rinfo->pd != NULL); + + /* unlock io */ + vga_io_wcrt (0x11, 0xFF); /* vgaHWunlock() + riva unlock (0x7F) */ + outb(rinfo->riva.LockUnlockIO, rinfo->riva.LockUnlockIndex); + outb(rinfo->riva.LockUnlockIO + 1, 0x57); + + memcpy (&rinfo->initial_state, ®_template, sizeof (reg_template)); + riva_save_state (rinfo, &rinfo->initial_state); + + rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024; + rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000; + + riva_set_fbinfo (rinfo); + + riva_init_clut (rinfo); + + riva_load_video_mode (rinfo, &rinfo->disp.var); + + if (register_framebuffer ((struct fb_info *) rinfo) < 0) { + printk(KERN_ERR PFX "error registering riva framebuffer\n"); + kfree (rinfo); + return -1; + } + + riva_boards = riva_board_list_add (riva_boards, rinfo); + + printk("PCI Riva NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n", + rinfo->riva.Architecture, + RIVAFB_VERSION, + rinfo->drvr_name, + rinfo->ram_amount / (1024 * 1024), + rinfo->fb_base_phys); + + return 0; +} + + + + +static int __init riva_pci_register_devices (void) +{ + struct pci_dev *pd; + const struct riva_chip_info *nci = &riva_pci_probe_list[0]; + + assert (nci != NULL); + while (nci->name != NULL) { + pd = pci_find_device (nci->vendor, nci->device, NULL); + while (pd != NULL) { + if (riva_pci_register (pd, nci) < 0) + return -1; + + pd = pci_find_device (nci->vendor, nci->device, pd); + } + + nci++; + } + + return 0; +} + + + +/*** riva_wclut - set CLUT entry ***/ +static void riva_wclut (unsigned char regnum, unsigned char red, + unsigned char green, unsigned char blue) +{ + unsigned int data = VGA_PEL_D; + + /* address write mode register is not translated.. */ + vga_io_w (VGA_PEL_IW, regnum); + + vga_io_w (data, red); + vga_io_w (data, green); + vga_io_w (data, blue); +} + + + +/* ------------ Hardware Independent Functions ------------ */ + +int __init rivafb_setup(char *options) +{ + char *this_opt; + + if (!options || !*options) + return 0; + + for (this_opt = strtok(options, ","); this_opt; + this_opt = strtok(NULL, ",")) { + if (!strncmp(this_opt, "font:", 5)) { + char *p; + int i; + + p = this_opt + 5; + for (i = 0; i < sizeof(fontname) - 1; i++) + if (!*p || *p == ' ' || *p == ',') + break; + memcpy(fontname, this_opt + 5, i); + fontname[i] = 0; + } + + else if (!strncmp(this_opt, "noaccel", 7)) { + noaccel = 1; + } + + else + mode_option = this_opt; + } + return 0; +} + + /* + * Initialization + */ + +int __init rivafb_init (void) +{ + if (riva_pci_register_devices () < 0) + return -ENXIO; + + if (riva_boards == NULL) + return -ENODEV; + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + /* + * Cleanup + */ + +void __exit rivafb_cleanup (struct fb_info *info) +{ +#warning FIXME: is this all we need to do? + + struct rivafb_info *tmp, *board = riva_boards; + + while (board != NULL) { + riva_load_state (board, &board->initial_state); + riva_pci_iounmap (board); + + unregister_framebuffer ((struct fb_info *) board); + + tmp = board; + board = board->next; + + kfree_s (tmp, sizeof (struct rivafb_info)); + } + + (void) info; /* unused function arg */ +} + + + + + /* + * Frame buffer operations + */ + +int rivafb_open(struct fb_info *info, int user) +{ + /* Nothing, only a usage count for the moment */ + MOD_INC_USE_COUNT; + return 0; +} + +int rivafb_release(struct fb_info *info, int user) +{ + MOD_DEC_USE_COUNT; + return 0; +} + + +/** + * rivafb_get_fix + * @fix: + * @con: + * @info: + * + * DESCRIPTION: + */ + +int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct display *p; + + DPRINTK ("ENTER\n"); + + assert (fix != NULL); + assert (info != NULL); + assert (rivainfo->drvr_name && rivainfo->drvr_name[0]); + assert (rivainfo->fb_base_phys > 0); + assert (rivainfo->ram_amount > 0); + + p = (con < 0) ? rivainfo->info.disp : &fb_display[con]; + + memset (fix, 0, sizeof (struct fb_fix_screeninfo)); + sprintf (fix->id, "Riva %s", rivainfo->drvr_name); + + fix->smem_start = rivainfo->fb_base_phys; + fix->smem_len = rivainfo->ram_amount; + + fix->type = p->type; + fix->type_aux = p->type_aux; + fix->visual = p->visual; + + fix->xpanstep = 1; + fix->ypanstep = 1; + fix->ywrapstep = 0; /* FIXME: no ywrap for now */ + + fix->line_length = p->line_length; + +#warning FIXME: set up MMIO region + fix->mmio_start = 0; + fix->mmio_len = 0; + +#warning FIXME: reference riva acceleration fb.h constant here + fix->accel = FB_ACCEL_NONE; + + DPRINTK ("EXIT, returning 0\n"); + + return 0; +} + + + +/** + * rivafb_get_var + * @var: + * @con: + * @info: + * + * DESCRIPTION: + */ + +int rivafb_get_var (struct fb_var_screeninfo *var, int con, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + + DPRINTK ("ENTER\n"); + + assert (info != NULL); + assert (var != NULL); + + *var = (con < 0) ? rivainfo->disp.var : fb_display[con].var; + + DPRINTK ("EXIT, returning 0\n"); + + return 0; +} + + + +/** + * rivafb_set_var + * @var: + * @con: + * @info: + * + * DESCRIPTION: + */ + +int rivafb_set_var (struct fb_var_screeninfo *var, int con, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct display *dsp; + struct fb_var_screeninfo v; + int nom, den; /* translating from pixels->bytes */ + int i; + unsigned chgvar = 0; + static struct { + int xres, yres; + } modes[] = { + { 1600, 1280 }, + { 1280, 1024 }, + { 1024, 768 }, + { 800, 600 }, + { 640, 480 }, + { -1, -1 } + }; + + DPRINTK ("ENTER\n"); + + assert (info != NULL); + assert (var != NULL); + + DPRINTK ("Requested: %dx%dx%d\n", var->xres, var->yres, var->bits_per_pixel); + DPRINTK (" virtual: %dx%d\n", var->xres_virtual, var->yres_virtual); + DPRINTK (" offset: (%d,%d)\n", var->xoffset, var->yoffset); + DPRINTK ("grayscale: %d\n", var->grayscale); + + dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; + assert (dsp != NULL); + + /* if var has changed, we should call changevar() later */ + if (con >= 0) { + chgvar = ((dsp->var.xres != var->xres) || + (dsp->var.yres != var->yres) || + (dsp->var.xres_virtual != var->xres_virtual) || + (dsp->var.yres_virtual != var->yres_virtual) || + (dsp->var.bits_per_pixel != var->bits_per_pixel) || + memcmp(&dsp->var.red, &var->red, sizeof(var->red)) || + memcmp(&dsp->var.green, &var->green, sizeof(var->green)) || + memcmp(&dsp->var.blue, &var->blue, sizeof(var->blue))); + } + + memcpy (&v, var, sizeof (v)); + + switch (v.bits_per_pixel) { +#ifdef FBCON_HAS_MFB + case 1: + dsp->dispsw = &fbcon_mfb; + dsp->line_length = v.xres_virtual / 8; + dsp->visual = FB_VISUAL_MONO10; + nom = 4; + den = 8; + break; +#endif + +#ifdef FBCON_HAS_CFB8 + case 2 ... 8: + v.bits_per_pixel = 8; + dsp->dispsw = &fbcon_cfb8; + nom = 1; + den = 1; + dsp->line_length = v.xres_virtual; + dsp->visual = FB_VISUAL_PSEUDOCOLOR; + v.red.offset = 0; + v.red.length = 6; + v.green.offset = 0; + v.green.length = 6; + v.blue.offset = 0; + v.blue.length = 6; + break; +#endif + +#ifdef FBCON_HAS_CFB16 + case 9 ... 16: + v.bits_per_pixel = 16; + dsp->dispsw = &fbcon_cfb16; + dsp->dispsw_data = &rivainfo->con_cmap.cfb16; + nom = 2; + den = 1; + dsp->line_length = v.xres_virtual * 2; + dsp->visual = FB_VISUAL_DIRECTCOLOR; +#ifdef CONFIG_PREP + v.red.offset = 2; + v.green.offset = -3; + v.blue.offset = 8; +#else + v.red.offset = 10; + v.green.offset = 5; + v.blue.offset = 0; +#endif + v.red.length = 5; + v.green.length = 5; + v.blue.length = 5; + break; +#endif + +#ifdef FBCON_HAS_CFB32 + case 17 ... 32: + v.bits_per_pixel = 32; + dsp->dispsw = &fbcon_cfb32; + dsp->dispsw_data = rivainfo->con_cmap.cfb32; + nom = 4; + den = 1; + dsp->line_length = v.xres_virtual * 4; + dsp->visual = FB_VISUAL_DIRECTCOLOR; +#ifdef CONFIG_PREP + v.red.offset = 8; + v.green.offset = 16; + v.blue.offset = 24; +#else + v.red.offset = 16; + v.green.offset = 8; + v.blue.offset = 0; +#endif + v.red.length = 8; + v.green.length = 8; + v.blue.length = 8; + break; +#endif + + default: + printk (KERN_ERR PFX "mode %dx%dx%d rejected...color depth not supported.\n", + var->xres, var->yres, var->bits_per_pixel); + DPRINTK ("EXIT, returning -EINVAL\n"); + return -EINVAL; + } + + if (v.xres * nom / den * v.yres > rivainfo->ram_amount) { + printk (KERN_ERR PFX "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", + var->xres, var->yres, var->bits_per_pixel); + DPRINTK ("EXIT - EINVAL error\n"); + return -EINVAL; + } + + /* use highest possible virtual resolution */ + if (v.xres_virtual == -1 && + v.yres_virtual == -1) { + printk (KERN_WARNING PFX "using maximum available virtual resolution\n"); + for (i = 0; modes[i].xres != -1; i++) { + if (modes[i].xres * nom / den * modes[i].yres < rivainfo->ram_amount / 2) + break; + } + if (modes[i].xres == -1) { + printk (KERN_ERR PFX "could not find a virtual resolution that fits into video memory!!\n"); + DPRINTK ("EXIT - EINVAL error\n"); + return -EINVAL; + } + v.xres_virtual = modes[i].xres; + v.yres_virtual = modes[i].yres; + + printk (KERN_INFO PFX "virtual resolution set to maximum of %dx%d\n", + v.xres_virtual, v.yres_virtual); + } else if (v.xres_virtual == -1) { + /* FIXME: maximize X virtual resolution only */ + } else if (v.yres_virtual == -1) { + /* FIXME: maximize Y virtual resolution only */ + } + + if (v.xoffset < 0) + v.xoffset = 0; + if (v.yoffset < 0) + v.yoffset = 0; + + /* truncate xoffset and yoffset to maximum if too high */ + if (v.xoffset > v.xres_virtual - v.xres) + v.xoffset = v.xres_virtual - v.xres - 1; + + if (v.yoffset > v.yres_virtual - v.yres) + v.yoffset = v.yres_virtual - v.yres - 1; + + v.red.msb_right = + v.green.msb_right = + v.blue.msb_right = + v.transp.offset = + v.transp.length = + v.transp.msb_right = 0; + + switch (v.activate & FB_ACTIVATE_MASK) { + case FB_ACTIVATE_TEST: + DPRINTK ("EXIT - FB_ACTIVATE_TEST\n"); + return 0; + case FB_ACTIVATE_NXTOPEN: /* ?? */ + case FB_ACTIVATE_NOW: + break; /* continue */ + default: + DPRINTK ("EXIT - unknown activation type\n"); + return -EINVAL; /* unknown */ + } + + dsp->type = FB_TYPE_PACKED_PIXELS; + +#warning FIXME: verify that the above code sets dsp->* fields correctly + + memcpy (&dsp->var, &v, sizeof (v)); + + riva_load_video_mode (rivainfo, &v); + + if (chgvar && info && info->changevar) + info->changevar (con); + + DPRINTK ("EXIT, returning 0\n"); + return 0; +} + + + +/** + * rivafb_get_cmap + * @cmap: + * @kspc: + * @con: + * @info: + * + * DESCRIPTION: + * + * NOTES: + * Copied from matroxfb::matroxfb_get_cmap() + */ + +int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct display *dsp; + + DPRINTK ("ENTER\n"); + + assert (rivainfo != NULL); + assert (cmap != NULL); + + dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; + + if (con == rivainfo->currcon) { /* current console? */ + int rc = fb_get_cmap (cmap, kspc, riva_getcolreg, info); + DPRINTK ("EXIT - returning %d\n", rc); + return rc; + } else if (dsp->cmap.len) /* non default colormap? */ + fb_copy_cmap (&dsp->cmap, cmap, kspc ? 0 : 2); + else + fb_copy_cmap (fb_default_cmap (riva_get_cmap_len (&dsp->var)), + cmap, kspc ? 0 : 2); + + DPRINTK ("EXIT, returning 0\n"); + + return 0; +} + + +/** + * rivafb_set_cmap + * @cmap: + * @kspc: + * @con: + * @info: + * + * DESCRIPTION: + * + * NOTES: + * Copied from matroxfb::matroxfb_set_cmap() + */ + +int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct display *dsp; + unsigned int cmap_len; + + DPRINTK ("ENTER\n"); + + assert (rivainfo != NULL); + assert (cmap != NULL); + + dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; + + cmap_len = riva_get_cmap_len (&dsp->var); + if (dsp->cmap.len != cmap_len) { + int err = fb_alloc_cmap (&dsp->cmap, cmap_len, 0); + if (err) { + DPRINTK ("EXIT - returning %d\n", err); + return err; + } + } + if (con == rivainfo->currcon) { /* current console? */ + int rc = fb_set_cmap (cmap, kspc, riva_setcolreg, info); + DPRINTK ("EXIT - returning %d\n", rc); + return rc; + } else + fb_copy_cmap (cmap, &dsp->cmap, kspc ? 0 : 1); + + DPRINTK ("EXIT, returning 0\n"); + + return 0; +} + + + +/** + * rivafb_pan_display + * @var: standard kernel fb changeable data + * @par: riva-specific hardware info about current video mode + * @info: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Pan (or wrap, depending on the `vmode' field) the display using the + * `xoffset' and `yoffset' fields of the `var' structure. + * If the values don't fit, return -EINVAL. + * + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag + */ + +int rivafb_pan_display (struct fb_var_screeninfo *var, int con, + struct fb_info *info) +{ + unsigned int base; + struct display *dsp; + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + + DPRINTK ("ENTER\n"); + + assert (rivainfo != NULL); + + if (var->xoffset > (var->xres_virtual - var->xres)) + return -EINVAL; + if (var->yoffset > (var->yres_virtual - var->yres)) + return -EINVAL; + + dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; + + if (var->vmode & FB_VMODE_YWRAP) { + if (var->yoffset < 0 || var->yoffset >= dsp->var.yres_virtual || var->xoffset) + return -EINVAL; + } else { + if (var->xoffset+dsp->var.xres > dsp->var.xres_virtual || + var->yoffset+dsp->var.yres > dsp->var.yres_virtual) + return -EINVAL; + } + + base = var->yoffset * dsp->line_length + var->xoffset; + + if (con == rivainfo->currcon) { + /* FIXME: do the dirty deed */ + } + + dsp->var.xoffset = var->xoffset; + dsp->var.yoffset = var->yoffset; + + if (var->vmode & FB_VMODE_YWRAP) + dsp->var.vmode |= FB_VMODE_YWRAP; + else + dsp->var.vmode &= ~FB_VMODE_YWRAP; + + DPRINTK ("EXIT, returning 0\n"); + + return 0; +} + + + +/** + * rivafb_ioctl + * @inode: + * @file: + * @cmd: + * @arg: + * @con: + * @info: + * + * DESCRIPTION: + */ + +int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, + unsigned long arg, int con, struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + + DPRINTK ("ENTER\n"); + + assert (rivainfo != NULL); + + /* no rivafb-specific ioctls */ + + DPRINTK ("EXIT, returning -EINVAL\n"); + + return -EINVAL; +} + + + + +/** + * rivafb_switch + * @con: + * @info: + * + * DESCRIPTION: + */ + +int rivafb_switch(int con, struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct fb_cmap* cmap; + struct display *dsp; + + DPRINTK("ENTER\n"); + + assert (rivainfo != NULL); + + dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; + + if (rivainfo->currcon >= 0) { + /* Do we have to save the colormap? */ + cmap = &(rivainfo->currcon_display->cmap); + DPRINTK("switch1: con = %d, cmap.len = %d\n", rivainfo->currcon, cmap->len); + + if (cmap->len) { + DPRINTK("switch1a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); + fb_get_cmap(cmap, 1, riva_getcolreg, info); +#ifdef DEBUG + if (cmap->red) { + DPRINTK("switch1r: %X\n", cmap->red[0]); + } +#endif + } + } + rivainfo->currcon = con; + rivainfo->currcon_display = dsp; + dsp->var.activate = FB_ACTIVATE_NOW; + +#ifdef riva_DEBUG + cmap = &dsp->cmap; + DPRINTK("switch2: con = %d, cmap.len = %d\n", con, cmap->len); + DPRINTK("switch2a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); + if (dsp->cmap.red) { + DPRINTK("switch2r: %X\n", cmap->red[0]); + } +#endif + + rivafb_set_var(&dsp->var, con, info); + +#ifdef riva_DEBUG + DPRINTK("switch3: con = %d, cmap.len = %d\n", con, cmap->len); + DPRINTK("switch3a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); + if (dsp->cmap.red) { + DPRINTK("switch3r: %X\n", cmap->red[0]); + } +#endif + + DPRINTK("EXIT, returning 0\n"); + + return 0; +} + + + +void rivafb_blank (int blank, struct fb_info *info) +{ + unsigned char tmp; + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + + DPRINTK ("ENTER\n"); + + assert (rivainfo != NULL); + + tmp = vga_io_rseq (VGA_SEQ_CLOCK_MODE) & ~VGA_SR01_SCREEN_OFF; + + if (blank) + tmp |= VGA_SR01_SCREEN_OFF; + + vga_io_wseq (VGA_SEQ_CLOCK_MODE, tmp); + + DPRINTK("EXIT\n"); +} + + +/* ------------------------------------------------------------------------- + * + * internal fb_ops helper functions + * + * ------------------------------------------------------------------------- + */ + + +/** + * riva_get_cmap_len + * @var: + * + * DESCRIPTION: + */ + +static int riva_get_cmap_len(const struct fb_var_screeninfo *var) +{ + int rc = 16; /* reasonable default */ + + assert (var != NULL); + + switch (var->bits_per_pixel) { +#ifdef FBCON_HAS_CFB4 + case 4: + rc = 16; /* pseudocolor... 16 entries HW palette */ + break; +#endif +#ifdef FBCON_HAS_CFB8 + case 8: + rc = 256; /* pseudocolor... 256 entries HW palette */ + break; +#endif +#ifdef FBCON_HAS_CFB16 + case 16: + rc = 16; /* directcolor... 16 entries SW palette */ + break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ +#endif +#ifdef FBCON_HAS_CFB32 + case 32: + rc = 16; /* directcolor... 16 entries SW palette */ + break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ +#endif + default: + assert (0); + /* should not occur */ + break; + } + + return rc; +} + + +/** + * riva_getcolreg + * @regno: + * @red: + * @green: + * @blue: + * @transp: + * @info: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Read a single color register and split it into colors/transparent. + * The return values must have a 16 bit magnitude. + * Return != 0 for invalid regno. + * + * CALLED FROM: + * fbcmap.c:fb_get_cmap() + * fbgen.c:fbgen_get_cmap() + * fbgen.c:fbgen_switch() + */ + +static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green, + unsigned *blue, unsigned *transp, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + + if (regno > 255) + return 1; + *red = rivainfo->palette[regno].red; + *green = rivainfo->palette[regno].green; + *blue = rivainfo->palette[regno].blue; + *transp = 0; + return 0; +} + + +/** + * riva_setcolreg + * @regno: + * @red: + * @green: + * @blue: + * @transp: + * @info: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Set a single color register. The values supplied have a 16 bit + * magnitude. + * Return != 0 for invalid regno. + * + * CALLED FROM: + * fbcmap.c:fb_set_cmap() + * fbgen.c:fbgen_get_cmap() + * fbgen.c:fbgen_install_cmap() + * fbgen.c:fbgen_set_var() + * fbgen.c:fbgen_switch() + * fbgen.c:fbgen_blank() + * fbgen.c:fbgen_blank() + */ + +static int riva_setcolreg (unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct display *p; + + DPRINTK("ENTER\n"); + + assert (rivainfo != NULL); + assert (rivainfo->currcon_display != NULL); + + if (regno > 255) + return -EINVAL; + + p = rivainfo->currcon_display; + if (p->var.grayscale) { + /* gray = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; + } + +#ifdef FBCON_HAS_CFB8 + switch (p->var.bits_per_pixel) { + case 8: + /* "transparent" stuff is completely ignored. */ + riva_wclut (regno, red >> 10, green >> 10, blue >> 10); + break; + default: + /* do nothing */ + break; + } +#endif /* FBCON_HAS_CFB8 */ + + rivainfo->palette[regno].red = red; + rivainfo->palette[regno].green = green; + rivainfo->palette[regno].blue = blue; + + if (regno >= 16) + return 0; + + switch (p->var.bits_per_pixel) { + +#ifdef FBCON_HAS_CFB16 + case 16: + assert (regno < 16); +#ifdef CONFIG_PREP + rivainfo->con_cmap.cfb16[regno] = + ((red & 0xf800) >> 9) | + ((green & 0xf800) >> 14) | + ((green & 0xf800) << 2) | + ((blue & 0xf800) >> 3); +#else + rivainfo->con_cmap.cfb16[regno] = + ((red & 0xf800) >> 1) | + ((green & 0xf800) >> 6) | + ((blue & 0xf800) >> 11); +#endif + break; +#endif /* FBCON_HAS_CFB16 */ + +#ifdef FBCON_HAS_CFB32 + case 32: + assert (regno < 16); +#ifdef CONFIG_PREP + rivainfo->con_cmap.cfb32[regno] = + ((red & 0xff00)) | + ((green & 0xff00) << 8) | + ((blue & 0xff00) << 16); +#else + rivainfo->con_cmap.cfb32[regno] = + ((red & 0xff00) << 8) | + ((green & 0xff00)) | + ((blue & 0xff00) >> 8); +#endif + break; +#endif /* FBCON_HAS_CFB32 */ + + default: + /* do nothing */ + break; + } + + return 0; +} + + + +/* + * riva_load_video_mode() + * + * calculate some timings and then send em off to riva_load_state() + */ + +static void riva_load_video_mode (struct rivafb_info *rinfo, + struct fb_var_screeninfo *video_mode) +{ + struct riva_regs newmode; + int bpp, width, hDisplaySize, hDisplay, hStart, + hEnd, hTotal, height, vDisplay, vStart, + vEnd, vTotal, dotClock; + + /* time to calculate */ + + bpp = video_mode->bits_per_pixel; + width = hDisplaySize = video_mode->xres; + hDisplay = (hDisplaySize/8) - 1; + hStart = (hDisplaySize + video_mode->right_margin)/8 + 2; + hEnd = (hDisplaySize + video_mode->right_margin + + video_mode->hsync_len)/8 - 1; + hTotal = (hDisplaySize + video_mode->right_margin + + video_mode->hsync_len + video_mode->left_margin)/8 - 1; + height = video_mode->yres; + vDisplay = video_mode->yres - 1; + vStart = video_mode->yres + video_mode->lower_margin - 1; + vEnd = video_mode->yres + video_mode->lower_margin + + video_mode->vsync_len - 1; + vTotal = video_mode->yres + video_mode->lower_margin + + video_mode->vsync_len + video_mode->upper_margin + 2; + dotClock = 1000000000 / video_mode->pixclock; + + memcpy(&newmode, ®_template, sizeof(struct riva_regs)); + + newmode.crtc[0x0] = Set8Bits(hTotal - 4); + newmode.crtc[0x1] = Set8Bits(hDisplay); + newmode.crtc[0x2] = Set8Bits(hDisplay); + newmode.crtc[0x3] = SetBitField(hTotal,4:0,4:0) | SetBit(7); + newmode.crtc[0x4] = Set8Bits(hStart); + newmode.crtc[0x5] = SetBitField(hTotal,5:5,7:7) + | SetBitField(hEnd,4:0,4:0); + newmode.crtc[0x6] = SetBitField(vTotal,7:0,7:0); + newmode.crtc[0x7] = SetBitField(vTotal,8:8,0:0) + | SetBitField(vDisplay,8:8,1:1) + | SetBitField(vStart,8:8,2:2) + | SetBitField(vDisplay,8:8,3:3) + | SetBit(4) + | SetBitField(vTotal,9:9,5:5) + | SetBitField(vDisplay,9:9,6:6) + | SetBitField(vStart,9:9,7:7); + newmode.crtc[0x9] = SetBitField(vDisplay,9:9,5:5) + | SetBit(6); + newmode.crtc[0x10] = Set8Bits(vStart); + newmode.crtc[0x11] = SetBitField(vEnd,3:0,3:0) + | SetBit(5); + newmode.crtc[0x12] = Set8Bits(vDisplay); + newmode.crtc[0x13] = ((width/8)*(bpp/8)) & 0xFF; + newmode.crtc[0x15] = Set8Bits(vDisplay); + newmode.crtc[0x16] = Set8Bits(vTotal + 1); + + newmode.ext.bpp = bpp; + newmode.ext.width = width; + newmode.ext.height = height; + + rinfo->riva.CalcStateExt(&rinfo->riva,&newmode.ext,bpp,width, + hDisplaySize,hDisplay,hStart,hEnd,hTotal, + height,vDisplay,vStart,vEnd,vTotal,dotClock); + + rinfo->initial_state = newmode; + riva_load_state(rinfo,&newmode); +} + + + + + +/* ------------------------------------------------------------------------- */ + + + /* + * Modularization + */ + +#ifdef MODULE +int __init init_module(void) +{ + return rivafb_init(); +} + +void __exit cleanup_module(void) +{ + struct rivafb_info *tmp, *board = riva_boards; + + while (board != NULL) { + riva_load_state (board, &board->initial_state); + + unregister_framebuffer ((struct fb_info *) board); + + tmp = board; + iounmap (tmp->ctrl_base); + iounmap (tmp->fb_base); + board = board->next; + + kfree (tmp); + } +} +#endif /* MODULE */ + + + + + +/* from GGI */ +static +void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs) +{ + int i; + + io_out8(NV_CIO_SR_LOCK_INDEX, 0x3D4); + io_out8(NV_CIO_SR_UNLOCK_RW_VALUE, 0x3D5); + + rinfo->riva.UnloadStateExt(&rinfo->riva, ®s->ext); + + regs->misc_output = io_in8(0x3CC); + + for (i = 0; i < NUM_CRT_REGS; i++) + { + io_out8(i, 0x3D4); + regs->crtc[i] = io_in8(0x3D5); + } + + for (i = 0; i < NUM_ATC_REGS; i++) + { + io_out8(i, 0x3C0); + regs->attr[i] = io_in8(0x3C1); + } + + for (i = 0; i < NUM_GRC_REGS; i++) + { + io_out8(i, 0x3CE); + regs->gra[i] = io_in8(0x3CF); + } + + + for (i = 0; i < NUM_SEQ_REGS; i++) + { + io_out8(i, 0x3C4); + regs->seq[i] = io_in8(0x3C5); + } +} + + +/* from GGI */ +static +void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs) +{ + int i; + RIVA_HW_STATE *state = ®s->ext; + + io_out8(0x11, 0x3D4); + io_out8(0x00, 0x3D5); + + io_out8(NV_CIO_SR_LOCK_INDEX, 0x3D4); + io_out8(NV_CIO_SR_UNLOCK_RW_VALUE, 0x3D5); + + rinfo->riva.LoadStateExt(&rinfo->riva,state); + + io_out8(regs->misc_output, 0x3C2); + + for (i = 0; i < NUM_CRT_REGS; i++) + { + if (i < 0x19) + { + io_out8(i, 0x3D4); + io_out8(regs->crtc[i], 0x3D5); + } + else + { + switch (i) + { + case 0x19: + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: +#if 0 + case 0x28: +#endif + case 0x29: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x36: + case 0x37: + case 0x38: + case 0x39: + case 0x3a: + case 0x3b: + case 0x3c: + case 0x3d: + case 0x3e: + case 0x3f: +#if 0 + case 0x40: +#endif + break; + default: + io_out8(i, 0x3D4); + io_out8(regs->crtc[i], 0x3D5); + } + } + } + + for (i = 0; i < NUM_ATC_REGS; i++) + { + io_out8(i, 0x3C0); + io_out8(regs->attr[i], 0x3C1); + } + + for (i = 0; i < NUM_GRC_REGS; i++) + { + io_out8(i, 0x3CE); + io_out8(regs->gra[i], 0x3CF); + } + + for (i = 0; i < NUM_SEQ_REGS; i++) + { + io_out8(i, 0x3C4); + io_out8(regs->seq[i], 0x3C5); + } +} + + + + +/** + * riva_board_list_add + * @board_list: Root node of list of boards + * @new_node: New node to be added + * + * DESCRIPTION: + * Adds @new_node to the list referenced by @board_list + * + * RETURNS: + * New root node + */ +static +struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list, + struct rivafb_info *new_node) +{ + struct rivafb_info *i_p = board_list; + + new_node->next = NULL; + + if (board_list == NULL) + return new_node; + + while (i_p->next != NULL) + i_p = i_p->next; + i_p->next = new_node; + + return board_list; +} + diff --git a/drivers/video/sbusfb.c b/drivers/video/sbusfb.c index 1a3b02e64..f51bd0e1c 100644 --- a/drivers/video/sbusfb.c +++ b/drivers/video/sbusfb.c @@ -175,12 +175,15 @@ static int sbusfb_mmap(struct fb_info *info, struct file *file, struct fb_info_sbusfb *fb = sbusfbinfo(info); unsigned int size, page, r, map_size; unsigned long map_offset = 0; + unsigned long off; int i; size = vma->vm_end - vma->vm_start; - if (vma->vm_offset & ~PAGE_MASK) - return -ENXIO; - + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) + return -EINVAL; + + off = vma->vm_pgoff << PAGE_SHIFT; + /* To stop the swapper from even considering these pages */ vma->vm_flags |= (VM_SHM| VM_LOCKED); @@ -190,9 +193,9 @@ static int sbusfb_mmap(struct fb_info *info, struct file *file, unsigned long j, alignment, s = 0; int max = -1; - map_offset = vma->vm_offset+size; + map_offset = (vma->vm_pgoff << PAGE_SHIFT) + size; for (i = 0; fb->mmap_map[i].size; i++) { - if (fb->mmap_map[i].voff < vma->vm_offset) + if (fb->mmap_map[i].voff < off) continue; if (fb->mmap_map[i].voff >= map_offset) break; @@ -210,7 +213,7 @@ static int sbusfb_mmap(struct fb_info *info, struct file *file, break; if (alignment > PAGE_SIZE) { j = alignment; - alignment = j - ((vma->vm_start + fb->mmap_map[max].voff - vma->vm_offset) & (j - 1)); + alignment = j - ((vma->vm_start + fb->mmap_map[max].voff - off) & (j - 1)); if (alignment != j) { struct vm_area_struct *vmm = find_vma(current->mm, vma->vm_start); if (!vmm || vmm->vm_start >= vma->vm_end + alignment) { @@ -227,7 +230,7 @@ static int sbusfb_mmap(struct fb_info *info, struct file *file, for (page = 0; page < size; ){ map_size = 0; for (i = 0; fb->mmap_map[i].size; i++) - if (fb->mmap_map[i].voff == vma->vm_offset+page) { + if (fb->mmap_map[i].voff == off+page) { map_size = sbusfb_mmapsize(fb,fb->mmap_map[i].size); #ifdef __sparc_v9__ #define POFF_MASK (PAGE_MASK|0x1UL) diff --git a/drivers/video/sgivwfb.c b/drivers/video/sgivwfb.c index ce02149cf..2031eba68 100644 --- a/drivers/video/sgivwfb.c +++ b/drivers/video/sgivwfb.c @@ -907,9 +907,12 @@ static int sgivwfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma) { unsigned long size = vma->vm_end - vma->vm_start; - unsigned long offset = sgivwfb_mem_phys + vma->vm_offset; - if (vma->vm_offset+size > sgivwfb_mem_size) + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) + return -EINVAL; + if (offset+size > sgivwfb_mem_size) return -EINVAL; + offset += sgivwfb_mem_phys; pgprot_val(vma->vm_page_prot) = pgprot_val(vma->vm_page_prot) | _PAGE_PCD; vma->vm_flags |= VM_IO; if (remap_page_range(vma->vm_start, offset, size, vma->vm_page_prot)) diff --git a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c index 30f9111ed..cd543762f 100644 --- a/drivers/video/tdfxfb.c +++ b/drivers/video/tdfxfb.c @@ -8,15 +8,17 @@ * All rights reserved * * Created : Thu Sep 23 18:17:43 1999, hmallat - * Last modified: Thu Oct 7 18:39:04 1999, hmallat + * Last modified: Tue Nov 2 21:19:47 1999, hmallat * * Lots of the information here comes from the Daryll Strauss' Banshee * patches to the XF86 server, and the rest comes from the 3dfx * Banshee specification. I'm very much indebted to Daryll for his * work on the X server. * - * Voodoo3 support was contributed Harold Oga. Thanks! - * + * Voodoo3 support was contributed Harold Oga. Lots of additions + * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila + * Kesmarki. Thanks guys! + * * While I _am_ grateful to 3Dfx for releasing the specs for Banshee, * I do wish the next version is a bit more complete. Without the XF86 * patches I couldn't have gotten even this far... for instance, the @@ -29,21 +31,24 @@ * * TODO: * - support for 16/32 bpp needs fixing (funky bootup penguin) - * - multihead support (it's all hosed now with pokes to VGA standard - * register locations, but shouldn't be that hard to change, some - * other code needs to be changed too where the fb_info (which should - * be an array of head-specific information) is referred to directly. - * are referred to ) - * - hw cursor - * - better acceleration support (e.g., font blitting from fb memory?) + * - multihead support (basically need to support an array of fb_infos) * - banshee and voodoo3 now supported -- any others? afaik, the original * voodoo was a 3d-only card, so we won't consider that. what about * voodoo2? - * - 24bpp - * - panning (doesn't seem to work properly yet) + * - support other architectures (PPC, Alpha); does the fact that the VGA + * core can be accessed only thru I/O (not memory mapped) complicate + * things? * * Version history: * + * 0.1.3 (released 1999-11-02) added Attila's panning support, code + * reorg, hwcursor address page size alignment + * (for mmaping both frame buffer and regs), + * and my changes to get rid of hardcoded + * VGA i/o register locations (uses PCI + * configuration info now) + * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and + * improvements * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga. * 0.1.0 (released 1999-10-06) initial version * @@ -69,10 +74,16 @@ #include <linux/kd.h> #include <linux/vt_kern.h> #include <asm/io.h> +#include <linux/timer.h> + +#ifdef CONFIG_MTRR +#include <asm/mtrr.h> +#endif #include <video/fbcon.h> #include <video/fbcon-cfb8.h> #include <video/fbcon-cfb16.h> +#include <video/fbcon-cfb24.h> #include <video/fbcon-cfb32.h> #ifndef LINUX_VERSION_CODE @@ -87,6 +98,12 @@ #define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 #endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) +/* nothing? */ +#else +#include <linux/spinlock.h> +#endif + /* membase0 register offsets */ #define STATUS 0x00 #define PCIINIT0 0x04 @@ -167,24 +184,26 @@ #define BIT(x) (1UL << (x)) -#define ROP_COPY 0xcc +/* COMMAND_2D reg. values */ +#define ROP_COPY 0xcc // src +#define ROP_INVERT 0x55 // NOT dst +#define ROP_XOR 0x66 // src XOR dst +#define AUTOINC_DSTX BIT(10) +#define AUTOINC_DSTY BIT(11) #define COMMAND_2D_FILLRECT 0x05 -#define COMMAND_2D_BITBLT 0x01 +#define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen +#define COMMAND_2D_H2S_BITBLT 0x03 // host to screen -#define COMMAND_3D_NOP 0x00 +#define COMMAND_3D_NOP 0x00 #define STATUS_RETRACE BIT(6) #define STATUS_BUSY BIT(9) - #define MISCINIT1_CLUT_INV BIT(0) #define MISCINIT1_2DBLOCK_DIS BIT(15) - #define DRAMINIT0_SGRAM_NUM BIT(26) #define DRAMINIT0_SGRAM_TYPE BIT(27) - #define DRAMINIT1_MEM_SDRAM BIT(30) - #define VGAINIT0_VGA_DISABLE BIT(0) #define VGAINIT0_EXT_TIMING BIT(1) #define VGAINIT0_8BIT_DAC BIT(2) @@ -196,17 +215,15 @@ #define VGAINIT0_EXTSHIFTOUT BIT(12) #define VGAINIT0_DECODE_3C6 BIT(13) #define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22) - #define VGAINIT1_MASK 0x1fffff - #define VIDCFG_VIDPROC_ENABLE BIT(0) #define VIDCFG_CURS_X11 BIT(1) #define VIDCFG_HALF_MODE BIT(4) #define VIDCFG_DESK_ENABLE BIT(7) #define VIDCFG_CLUT_BYPASS BIT(10) #define VIDCFG_2X BIT(26) +#define VIDCFG_HWCURSOR_ENABLE BIT(27) #define VIDCFG_PIXFMT_SHIFT 18 - #define DACMODE_2X BIT(0) /* VGA rubbish, need to change this for multihead support */ @@ -220,9 +237,6 @@ #define IS1_R 0x3da #define GRA_I 0x3ce #define GRA_D 0x3cf -#define DAC_IR 0x3c7 -#define DAC_IW 0x3c8 -#define DAC_D 0x3c9 #ifndef FB_ACCEL_3DFX_BANSHEE #define FB_ACCEL_3DFX_BANSHEE 31 @@ -238,9 +252,9 @@ #define TDFXF_HSYNC_MASK 0x03 #define TDFXF_VSYNC_MASK 0x0c -/* #define TDFXFB_DEBUG */ +//#define TDFXFB_DEBUG #ifdef TDFXFB_DEBUG -#define DPRINTK(a,b...) printk("fb: %s: " a, __FUNCTION__ , ## b) +#define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b) #else #define DPRINTK(a,b...) #endif @@ -271,6 +285,9 @@ struct banshee_reg { unsigned long screensize; unsigned long stride; unsigned long cursloc; + unsigned long curspataddr; + unsigned long cursc0; + unsigned long cursc1; unsigned long startaddr; unsigned long clip0min; unsigned long clip0max; @@ -305,6 +322,7 @@ struct tdfxfb_par { u32 video; u32 accel_flags; + u32 cmap_len; }; struct fb_info_tdfx { @@ -319,21 +337,37 @@ struct fb_info_tdfx { unsigned long bufbase_phys; unsigned long bufbase_virt; unsigned long bufbase_size; + unsigned long iobase; - struct { u8 red, green, blue, pad; } palette[256]; + struct { unsigned red, green, blue, pad; } palette[256]; struct tdfxfb_par default_par; struct tdfxfb_par current_par; struct display disp; struct display_switch dispsw; - +#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB24) || defined(FBCON_HAS_CFB32) union { #ifdef FBCON_HAS_CFB16 u16 cfb16[16]; #endif +#ifdef FBCON_HAS_CFB24 + u32 cfb24[16]; +#endif #ifdef FBCON_HAS_CFB32 u32 cfb32[16]; #endif } fbcon_cmap; +#endif + struct { + int type; + int state; + int w,u,d; + int x,y,redraw; + unsigned long enable,disable; + unsigned long cursorimage; + struct timer_list timer; + } cursor; + + spinlock_t DAClock; }; /* @@ -411,9 +445,30 @@ static int tdfxfb_setcolreg(u_int regno, u_int blue, u_int transp, struct fb_info* fb); -static void tdfxfb_install_cmap(int con, +static void tdfxfb_install_cmap(struct display *d, struct fb_info *info); +static void tdfxfb_hwcursor_init(void); +static void tdfxfb_createcursorshape(struct display* p); +static void tdfxfb_createcursor(struct display * p); + +/* + * do_xxx: Hardware-specific functions + */ +static void do_pan_var(struct fb_var_screeninfo* var, struct fb_info_tdfx *i); +static void do_flashcursor(unsigned long ptr); +static void do_bitblt(u32 curx, u32 cury, u32 dstx,u32 dsty, + u32 width, u32 height,u32 stride,u32 bpp); +static void do_fillrect(u32 x, u32 y, u32 w,u32 h, + u32 color,u32 stride,u32 bpp,u32 rop); +static void do_putc(u32 fgx, u32 bgx,struct display *p, + int c, int yy,int xx); +static void do_putcs(u32 fgx, u32 bgx,struct display *p, + const unsigned short *s,int count, int yy,int xx); +static u32 do_calc_pll(int freq, int* freq_out); +static void do_write_regs(struct banshee_reg* reg); +static unsigned long do_lfb_size(void); + /* * Interface used by the world */ @@ -437,7 +492,8 @@ static struct fb_ops tdfxfb_ops = { tdfxfb_set_cmap, tdfxfb_pan_display, tdfxfb_ioctl, - NULL + NULL, // fb_mmap + NULL // fb_rasterimg }; struct mode { @@ -449,7 +505,7 @@ struct mode { struct mode default_mode[] = { { "640x480-8@60", /* @ 60 Hz */ { - 640, 480, 640, 480, 0, 0, 8, 0, + 640, 480, 640, 1024, 0, 0, 8, 0, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_ACTIVATE_NOW, -1, -1, FB_ACCELF_TEXT, 39722, 40, 24, 32, 11, 96, 2, @@ -493,7 +549,26 @@ struct mode default_mode[] = { 15385, 168, 8, 29, 3, 144, 6, 0, FB_VMODE_NONINTERLACED } - } + }, + { "1024x768-24@60", /* @ 60 Hz */ + { + 1024, 768, 1024, 768, 0, 0, 24, 0, + {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, + 0, FB_ACTIVATE_NOW, -1, -1, FB_ACCELF_TEXT, + 15385, 168, 8, 29, 3, 144, 6, + 0, FB_VMODE_NONINTERLACED + } + }, + { "1024x768-32@60", /* @ 60 Hz */ + { + 1024, 768, 1024, 768, 0, 0, 32, 0, + {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, + 0, FB_ACTIVATE_NOW, -1, -1, FB_ACCELF_TEXT, + 15385, 168, 8, 29, 3, 144, 6, + 0, FB_VMODE_NONINTERLACED + } + } + #endif }; @@ -504,55 +579,81 @@ static int default_mode_index = 0; static struct fb_info_tdfx fb_info; -static int __initdata noaccel = 0; -static int __initdata nopan = 0; -static int __initdata nowrap = 0; -static int __initdata inverse = 0; +static int noaccel = 0; +static int nopan = 0; +static int nowrap = 1; // not implemented (yet) +static int inverse = 0; +static int nomtrr = 0; +static int nohwcursor = 0; static char __initdata fontname[40] = { 0 }; static const char *mode_option __initdata = NULL; -/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- + * Hardware-specific funcions + * ------------------------------------------------------------------------- */ -static inline __u8 vga_inb(__u32 reg) { return inb(reg); } -static inline __u16 vga_inw(__u32 reg) { return inw(reg); } -static inline __u16 vga_inl(__u32 reg) { return inl(reg); } +#ifdef VGA_REG_IO +static inline u8 vga_inb(u32 reg) { return inb(reg); } +static inline u16 vga_inw(u32 reg) { return inw(reg); } +static inline u16 vga_inl(u32 reg) { return inl(reg); } -static inline void vga_outb(__u32 reg, __u8 val) { outb(val, reg); } -static inline void vga_outw(__u32 reg, __u16 val) { outw(val, reg); } -static inline void vga_outl(__u32 reg, __u32 val) { outl(val, reg); } +static inline void vga_outb(u32 reg, u8 val) { outb(val, reg); } +static inline void vga_outw(u32 reg, u16 val) { outw(val, reg); } +static inline void vga_outl(u32 reg, u32 val) { outl(val, reg); } +#else +static inline u8 vga_inb(u32 reg) { + return inb(fb_info.iobase + reg - 0x300); +} +static inline u16 vga_inw(u32 reg) { + return inw(fb_info.iobase + reg - 0x300); +} +static inline u16 vga_inl(u32 reg) { + return inl(fb_info.iobase + reg - 0x300); +} -static inline void gra_outb(__u32 idx, __u8 val) { +static inline void vga_outb(u32 reg, u8 val) { + outb(val, fb_info.iobase + reg - 0x300); +} +static inline void vga_outw(u32 reg, u16 val) { + outw(val, fb_info.iobase + reg - 0x300); +} +static inline void vga_outl(u32 reg, u32 val) { + outl(val, fb_info.iobase + reg - 0x300); +} +#endif + +static inline void gra_outb(u32 idx, u8 val) { vga_outb(GRA_I, idx); vga_outb(GRA_D, val); } -static inline __u8 gra_inb(__u32 idx) { +static inline u8 gra_inb(u32 idx) { vga_outb(GRA_I, idx); return vga_inb(GRA_D); } -static inline void seq_outb(__u32 idx, __u8 val) { +static inline void seq_outb(u32 idx, u8 val) { vga_outb(SEQ_I, idx); vga_outb(SEQ_D, val); } -static inline __u8 seq_inb(__u32 idx) { +static inline u8 seq_inb(u32 idx) { vga_outb(SEQ_I, idx); return vga_inb(SEQ_D); } -static inline void crt_outb(__u32 idx, __u8 val) { +static inline void crt_outb(u32 idx, u8 val) { vga_outb(CRT_I, idx); vga_outb(CRT_D, val); } -static inline __u8 crt_inb(__u32 idx) { +static inline u8 crt_inb(u32 idx) { vga_outb(CRT_I, idx); return vga_inb(CRT_D); } -static inline void att_outb(__u32 idx, __u8 val) { +static inline void att_outb(u32 idx, u8 val) { unsigned char tmp; tmp = vga_inb(IS1_R); vga_outb(ATT_IW, idx); vga_outb(ATT_IW, val); } -static inline __u8 att_inb(__u32 idx) { +static inline u8 att_inb(u32 idx) { unsigned char tmp; tmp = vga_inb(IS1_R); vga_outb(ATT_IW, idx); @@ -585,11 +686,11 @@ static inline void vga_enable_palette(void) { vga_outb(ATT_IW, 0x20); } -static inline __u32 tdfx_inl(unsigned int reg) { +static inline u32 tdfx_inl(unsigned int reg) { return readl(fb_info.regbase_virt + reg); } -static inline void tdfx_outl(unsigned int reg, __u32 val) { +static inline void tdfx_outl(unsigned int reg, u32 val) { writel(val, fb_info.regbase_virt + reg); } @@ -608,81 +709,226 @@ static inline void banshee_wait_idle(void) { if(i == 3) break; } } +/* + * Set the color of a palette entry in 8bpp mode + */ +static inline void do_setpalentry(unsigned regno, u32 c) { + banshee_make_room(2); tdfx_outl(DACADDR, regno); tdfx_outl(DACDATA, c); } -static void banshee_fillrect(__u32 x, - __u32 y, - __u32 w, - __u32 h, - __u32 color, - __u32 stride, - __u32 bpp) { - banshee_make_room(2); - tdfx_outl(DSTFORMAT, - (stride & 0x3fff) | - (bpp == 8 ? 0x10000 : - bpp == 16 ? 0x30000 : 0x50000)); - tdfx_outl(COLORFORE, color); - - banshee_make_room(3); - tdfx_outl(COMMAND_2D, COMMAND_2D_FILLRECT | (ROP_COPY << 24)); - tdfx_outl(DSTSIZE, (w & 0x1fff) | ((h & 0x1fff) << 16)); - tdfx_outl(LAUNCH_2D, (x & 0x1fff) | ((y & 0x1fff) << 16)); -} - -static void banshee_bitblt(__u32 curx, - __u32 cury, - __u32 dstx, - __u32 dsty, - __u32 width, - __u32 height, - __u32 stride, - __u32 bpp) { - int xdir, ydir; - - xdir = dstx < curx ? 1 : -1; - ydir = dsty < cury ? 1 : -1; - - banshee_make_room(4); - tdfx_outl(SRCFORMAT, - (stride & 0x3fff) | - (bpp == 8 ? 0x10000 : - bpp == 16 ? 0x30000 : 0x50000)); - tdfx_outl(DSTFORMAT, - (stride & 0x3fff) | - (bpp == 8 ? 0x10000 : - bpp == 16 ? 0x30000 : 0x50000)); - tdfx_outl(COMMAND_2D, - COMMAND_2D_BITBLT | - (xdir == -1 ? BIT(14) : 0) | - (ydir == -1 ? BIT(15) : 0)); - tdfx_outl(COMMANDEXTRA_2D, 0); /* no color keying */ - - if(xdir == -1) { - curx += width - 1; - dstx += width - 1; - } - if(ydir == -1) { - cury += height - 1; - dsty += height - 1; - } - - /* Consecutive overlapping regions can hang the board -- - since we allow mmap'ing of control registers, we cannot - __safely__ assume anything, like XF86 does... */ - banshee_make_room(1); - tdfx_outl(COMMAND_3D, COMMAND_3D_NOP); +/* + * Set the starting position of the visible screen to var->yoffset + */ +static void do_pan_var(struct fb_var_screeninfo* var, struct fb_info_tdfx *i) +{ + u32 addr; + addr = var->yoffset*i->current_par.lpitch; + banshee_make_room(1); + tdfx_outl(VIDDESKSTART, addr); +} + +/* + * Invert the hardware cursor image (timerfunc) + */ +static void do_flashcursor(unsigned long ptr) +{ + struct fb_info_tdfx* i=(struct fb_info_tdfx *)ptr; + spin_lock(&i->DAClock); + banshee_make_room(1); + tdfx_outl( VIDPROCCFG, tdfx_inl(VIDPROCCFG) ^ VIDCFG_HWCURSOR_ENABLE ); + i->cursor.timer.expires=jiffies+HZ/2; + add_timer(&i->cursor.timer); + spin_unlock(&i->DAClock); +} - banshee_make_room(3); - tdfx_outl(DSTSIZE, (width & 0x1fff) | ((height & 0x1fff) << 16)); - tdfx_outl(DSTXY, (dstx & 0x1fff) | ((dsty & 0x1fff) << 16)); - tdfx_outl(LAUNCH_2D, (curx & 0x1fff) | ((cury & 0x1fff) << 16)); +/* + * FillRect 2D command (solidfill or invert (via ROP_XOR)) + */ +static void do_fillrect(u32 x, u32 y, u32 w, u32 h, + u32 color, u32 stride, u32 bpp, u32 rop) { + + u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13); + + banshee_make_room(5); + tdfx_outl(DSTFORMAT, fmt); + tdfx_outl(COLORFORE, color); + tdfx_outl(COMMAND_2D, COMMAND_2D_FILLRECT | (rop << 24)); + tdfx_outl(DSTSIZE, w | (h << 16)); + tdfx_outl(LAUNCH_2D, x | (y << 16)); + banshee_wait_idle(); } -static __u32 banshee_calc_pll(int freq, int* freq_out) { +/* + * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) + */ + +static void do_bitblt(u32 curx, + u32 cury, + u32 dstx, + u32 dsty, + u32 width, + u32 height, + u32 stride, + u32 bpp) { + + u32 blitcmd = COMMAND_2D_S2S_BITBLT | (ROP_COPY << 24); + u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13); + + if (curx <= dstx) { + //-X + blitcmd |= BIT(14); + curx += width-1; + dstx += width-1; + } + if (cury <= dsty) { + //-Y + blitcmd |= BIT(15); + cury += height-1; + dsty += height-1; + } + + banshee_make_room(6); + + tdfx_outl(SRCFORMAT, fmt); + tdfx_outl(DSTFORMAT, fmt); + tdfx_outl(COMMAND_2D, blitcmd); + tdfx_outl(DSTSIZE, width | (height << 16)); + tdfx_outl(DSTXY, dstx | (dsty << 16)); + tdfx_outl(LAUNCH_2D, curx | (cury << 16)); + banshee_wait_idle(); +} + +static void do_putc(u32 fgx, u32 bgx, + struct display *p, + int c, int yy,int xx) +{ + int i; + int stride=fb_info.current_par.lpitch; + u32 bpp=fb_info.current_par.bpp; + int fw=(fontwidth(p)+7)>>3; + u8 *chardata=p->fontdata+(c&p->charmask)*fontheight(p)*fw; + u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13); + + xx *= fontwidth(p); + yy *= fontheight(p); + + banshee_make_room(8+((fontheight(p)*fw+3)>>2) ); + tdfx_outl(COLORFORE, fgx); + tdfx_outl(COLORBACK, bgx); + tdfx_outl(SRCXY, 0); + tdfx_outl(DSTXY, xx | (yy << 16)); + tdfx_outl(COMMAND_2D, COMMAND_2D_H2S_BITBLT | (ROP_COPY << 24)); + tdfx_outl(SRCFORMAT, 0x400000); + tdfx_outl(DSTFORMAT, fmt); + tdfx_outl(DSTSIZE, fontwidth(p) | (fontheight(p) << 16)); + i=fontheight(p); + switch (fw) { + case 1: + while (i>=4) { + tdfx_outl(LAUNCH_2D,*(u32*)chardata); + chardata+=4; + i-=4; + } + switch (i) { + case 0: break; + case 1: tdfx_outl(LAUNCH_2D,*chardata); break; + case 2: tdfx_outl(LAUNCH_2D,*(u16*)chardata); break; + case 3: tdfx_outl(LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break; + } + break; + case 2: + while (i>=2) { + tdfx_outl(LAUNCH_2D,*(u32*)chardata); + chardata+=4; + i-=2; + } + if (i) tdfx_outl(LAUNCH_2D,*(u16*)chardata); + break; + default: + // Is there a font with width more that 16 pixels ? + for (i=fontheight(p);i>0;i--) { + tdfx_outl(LAUNCH_2D,*(u32*)chardata); + chardata+=4; + } + break; + } + banshee_wait_idle(); +} + +static void do_putcs(u32 fgx, u32 bgx, + struct display *p, + const unsigned short *s, + int count, int yy,int xx) +{ + int i; + int stride=fb_info.current_par.lpitch; + u32 bpp=fb_info.current_par.bpp; + int fw=(fontwidth(p)+7)>>3; + int w=fontwidth(p); + int h=fontheight(p); + int regsneed=1+((h*fw+3)>>2); + u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13); + + xx *= w; + yy = (yy*h) << 16; + banshee_make_room(8); + + tdfx_outl(COMMAND_3D, COMMAND_3D_NOP); + tdfx_outl(COLORFORE, fgx); + tdfx_outl(COLORBACK, bgx); + tdfx_outl(SRCFORMAT, 0x400000); + tdfx_outl(DSTFORMAT, fmt); + tdfx_outl(DSTSIZE, w | (h << 16)); + tdfx_outl(SRCXY, 0); + tdfx_outl(COMMAND_2D, COMMAND_2D_H2S_BITBLT | (ROP_COPY << 24)); + + while (count--) { + u8 *chardata=p->fontdata+(scr_readw(s++) & p->charmask)*h*fw; + + banshee_make_room(regsneed); + tdfx_outl(DSTXY, xx | yy); + xx+=w; + + i=h; + switch (fw) { + case 1: + while (i>=4) { + tdfx_outl(LAUNCH_2D,*(u32*)chardata); + chardata+=4; + i-=4; + } + switch (i) { + case 0: break; + case 1: tdfx_outl(LAUNCH_2D,*chardata); break; + case 2: tdfx_outl(LAUNCH_2D,*(u16*)chardata); break; + case 3: tdfx_outl(LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break; + } + break; + case 2: + while (i>=2) { + tdfx_outl(LAUNCH_2D,*(u32*)chardata); + chardata+=4; + i-=2; + } + if (i) tdfx_outl(LAUNCH_2D,*(u16*)chardata); + break; + default: + // Is there a font with width more that 16 pixels ? + for (;i>0;i--) { + tdfx_outl(LAUNCH_2D,*(u32*)chardata); + chardata+=4; + } + break; + } + } + banshee_wait_idle(); +} + +static u32 do_calc_pll(int freq, int* freq_out) { int m, n, k, best_m, best_n, best_k, f_cur, best_error; int fref = 14318; - /* this really could be done with more intelligence */ + /* this really could be done with more intelligence -- + 255*63*4 = 64260 iterations is silly */ best_error = freq; best_n = best_m = best_k = 0; for(n = 1; n < 256; n++) { @@ -703,13 +949,10 @@ static __u32 banshee_calc_pll(int freq, int* freq_out) { k = best_k; *freq_out = fref*(n + 2)/(m + 2)/(1 << k); - DPRINTK("freq = %d kHz, freq_out = %d kHz\n", freq, *freq_out); - DPRINTK("N = %d, M = %d, K = %d\n", n, m, k); - return (n << 8) | (m << 2) | k; } -static void banshee_write_regs(struct banshee_reg* reg) { +static void do_write_regs(struct banshee_reg* reg) { int i; banshee_wait_idle(); @@ -747,17 +990,25 @@ static void banshee_write_regs(struct banshee_reg* reg) { vga_enable_palette(); vga_enable_video(); - banshee_make_room(9); + banshee_make_room(11); tdfx_outl(VGAINIT0, reg->vgainit0); tdfx_outl(DACMODE, reg->dacmode); tdfx_outl(VIDDESKSTRIDE, reg->stride); - tdfx_outl(HWCURPATADDR, reg->cursloc); + if (nohwcursor) { + tdfx_outl(HWCURPATADDR, 0); + } else { + tdfx_outl(HWCURPATADDR, reg->curspataddr); + tdfx_outl(HWCURC0, reg->cursc0); + tdfx_outl(HWCURC1, reg->cursc1); + tdfx_outl(HWCURLOC, reg->cursloc); + } + tdfx_outl(VIDSCREENSIZE, reg->screensize); tdfx_outl(VIDDESKSTART, reg->startaddr); tdfx_outl(VIDPROCCFG, reg->vidcfg); tdfx_outl(VGAINIT1, reg->vgainit1); - banshee_make_room(7); + banshee_make_room(8); tdfx_outl(SRCBASE, reg->srcbase); tdfx_outl(DSTBASE, reg->dstbase); tdfx_outl(COMMANDEXTRA_2D, 0); @@ -765,15 +1016,16 @@ static void banshee_write_regs(struct banshee_reg* reg) { tdfx_outl(CLIP0MAX, 0x0fff0fff); tdfx_outl(CLIP1MIN, 0); tdfx_outl(CLIP1MAX, 0x0fff0fff); + tdfx_outl(SRCXY, 0); banshee_wait_idle(); } -static unsigned long tdfx_lfb_size(void) { - __u32 draminit0 = 0; - __u32 draminit1 = 0; - __u32 miscinit1 = 0; - __u32 lfbsize = 0; +static unsigned long do_lfb_size(void) { + u32 draminit0 = 0; + u32 draminit1 = 0; + u32 miscinit1 = 0; + u32 lfbsize = 0; int sgram_p = 0; if(!((fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) || @@ -782,7 +1034,7 @@ static unsigned long tdfx_lfb_size(void) { draminit0 = tdfx_inl(DRAMINIT0); draminit1 = tdfx_inl(DRAMINIT1); - + sgram_p = (draminit1 & DRAMINIT1_MEM_SDRAM) ? 0 : 1; lfbsize = sgram_p ? @@ -794,19 +1046,53 @@ static unsigned long tdfx_lfb_size(void) { miscinit1 = tdfx_inl(MISCINIT1); miscinit1 |= sgram_p ? 0 : MISCINIT1_2DBLOCK_DIS; miscinit1 |= MISCINIT1_CLUT_INV; + + banshee_make_room(1); tdfx_outl(MISCINIT1, miscinit1); return lfbsize; } -static void fbcon_banshee_bmove(struct display* p, +/* ------------------------------------------------------------------------- + * Hardware independent part, interface to the world + * ------------------------------------------------------------------------- */ + +#define tdfx_cfb24_putc tdfx_cfb32_putc +#define tdfx_cfb24_putcs tdfx_cfb32_putcs +#define tdfx_cfb24_clear tdfx_cfb32_clear + +static void tdfx_cfbX_clear_margins(struct vc_data* conp, struct display* p, + int bottom_only) +{ + unsigned int cw=fontwidth(p); + unsigned int ch=fontheight(p); + unsigned int rw=p->var.xres % cw; // it be in a non-standard mode or not? + unsigned int bh=p->var.yres % ch; + unsigned int rs=p->var.xres - rw; + unsigned int bs=p->var.yres - bh; + + if (!bottom_only && rw) { + do_fillrect( p->var.xoffset+rs, 0, + rw, p->var.yres_virtual, 0, + fb_info.current_par.lpitch, + fb_info.current_par.bpp, ROP_COPY); + } + + if (bh) { + do_fillrect( p->var.xoffset, p->var.yoffset+bs, + rs, bh, 0, + fb_info.current_par.lpitch, + fb_info.current_par.bpp, ROP_COPY); + } +} +static void tdfx_cfbX_bmove(struct display* p, int sy, int sx, int dy, int dx, int height, int width) { - banshee_bitblt(fontwidth(p)*sx, + do_bitblt(fontwidth(p)*sx, fontheight(p)*sy, fontwidth(p)*dx, fontheight(p)*dy, @@ -815,64 +1101,221 @@ static void fbcon_banshee_bmove(struct display* p, fb_info.current_par.lpitch, fb_info.current_par.bpp); } +static void tdfx_cfb8_putc(struct vc_data* conp, + struct display* p, + int c, int yy,int xx) +{ + u32 fgx,bgx; + fgx=attr_fgcol(p, c); + bgx=attr_bgcol(p, c); + do_putc( fgx,bgx,p,c,yy,xx ); +} + +static void tdfx_cfb16_putc(struct vc_data* conp, + struct display* p, + int c, int yy,int xx) +{ + u32 fgx,bgx; + fgx=((u16*)p->dispsw_data)[attr_fgcol(p,c)]; + bgx=((u16*)p->dispsw_data)[attr_bgcol(p,c)]; + do_putc( fgx,bgx,p,c,yy,xx ); +} + +static void tdfx_cfb32_putc(struct vc_data* conp, + struct display* p, + int c, int yy,int xx) +{ + u32 fgx,bgx; + fgx=((u32*)p->dispsw_data)[attr_fgcol(p,c)]; + bgx=((u32*)p->dispsw_data)[attr_bgcol(p,c)]; + do_putc( fgx,bgx,p,c,yy,xx ); +} +static void tdfx_cfb8_putcs(struct vc_data* conp, + struct display* p, + const unsigned short *s,int count,int yy,int xx) +{ + u32 fgx,bgx; + fgx=attr_fgcol(p, *s); + bgx=attr_bgcol(p, *s); + do_putcs( fgx,bgx,p,s,count,yy,xx ); +} +static void tdfx_cfb16_putcs(struct vc_data* conp, + struct display* p, + const unsigned short *s,int count,int yy,int xx) +{ + u32 fgx,bgx; + fgx=((u16*)p->dispsw_data)[attr_fgcol(p,*s)]; + bgx=((u16*)p->dispsw_data)[attr_bgcol(p,*s)]; + do_putcs( fgx,bgx,p,s,count,yy,xx ); +} +static void tdfx_cfb32_putcs(struct vc_data* conp, + struct display* p, + const unsigned short *s,int count,int yy,int xx) +{ + u32 fgx,bgx; + fgx=((u32*)p->dispsw_data)[attr_fgcol(p,*s)]; + bgx=((u32*)p->dispsw_data)[attr_bgcol(p,*s)]; + do_putcs( fgx,bgx,p,s,count,yy,xx ); +} -static void fbcon_banshee_clear(struct vc_data* conp, +static void tdfx_cfb8_clear(struct vc_data* conp, struct display* p, int sy, int sx, int height, int width) { - unsigned int bg; + u32 bg; bg = attr_bgcol_ec(p,conp); - banshee_fillrect(fontwidth(p)*sx, + do_fillrect(fontwidth(p)*sx, fontheight(p)*sy, fontwidth(p)*width, fontheight(p)*height, bg, fb_info.current_par.lpitch, - fb_info.current_par.bpp); + fb_info.current_par.bpp,ROP_COPY); } +static void tdfx_cfb16_clear(struct vc_data* conp, + struct display* p, + int sy, + int sx, + int height, + int width) { + u32 bg; + + bg = ((u16*)p->dispsw_data)[attr_bgcol_ec(p,conp)]; + do_fillrect(fontwidth(p)*sx, + fontheight(p)*sy, + fontwidth(p)*width, + fontheight(p)*height, + bg, + fb_info.current_par.lpitch, + fb_info.current_par.bpp,ROP_COPY); +} + +static void tdfx_cfb32_clear(struct vc_data* conp, + struct display* p, + int sy, + int sx, + int height, + int width) { + u32 bg; + + bg = ((u32*)p->dispsw_data)[attr_bgcol_ec(p,conp)]; + do_fillrect(fontwidth(p)*sx, + fontheight(p)*sy, + fontwidth(p)*width, + fontheight(p)*height, + bg, + fb_info.current_par.lpitch, + fb_info.current_par.bpp,ROP_COPY); +} +static void tdfx_cfbX_revc(struct display *p, int xx, int yy) +{ + int bpp=fb_info.current_par.bpp; + + do_fillrect( xx * fontwidth(p), yy * fontheight(p), + fontwidth(p), fontheight(p), + (bpp==8) ? 0x0f : 0xffffffff, + fb_info.current_par.lpitch, bpp, ROP_XOR); + +} +static void tdfx_cfbX_cursor(struct display *p, int mode, int x, int y) +{ + unsigned long flags; + int tip; + struct fb_info_tdfx *info=(struct fb_info_tdfx *)p->fb_info; + + tip=p->conp->vc_cursor_type & CUR_HWMASK; + if (mode==CM_ERASE) { + if (info->cursor.state != CM_ERASE) { + spin_lock_irqsave(&info->DAClock,flags); + info->cursor.state=CM_ERASE; + del_timer(&(info->cursor.timer)); + tdfx_outl(VIDPROCCFG,info->cursor.disable); + spin_unlock_irqrestore(&info->DAClock,flags); + } + return; + } + if ((p->conp->vc_cursor_type & CUR_HWMASK) != info->cursor.type) + tdfxfb_createcursor(p); + x *= fontwidth(p); + y *= fontheight(p); + y -= p->var.yoffset; + spin_lock_irqsave(&info->DAClock,flags); + if ((x!=info->cursor.x) || + (y!=info->cursor.y) || + (info->cursor.redraw)) { + info->cursor.x=x; + info->cursor.y=y; + info->cursor.redraw=0; + x += 63; + y += 63; + banshee_make_room(2); + tdfx_outl(VIDPROCCFG, info->cursor.disable); + tdfx_outl(HWCURLOC, (y << 16) + x); + } + info->cursor.state = CM_DRAW; + mod_timer(&info->cursor.timer,jiffies+HZ/2); + banshee_make_room(1); + tdfx_outl(VIDPROCCFG, info->cursor.enable); + spin_unlock_irqrestore(&info->DAClock,flags); + return; +} #ifdef FBCON_HAS_CFB8 static struct display_switch fbcon_banshee8 = { fbcon_cfb8_setup, - fbcon_banshee_bmove, - fbcon_banshee_clear, - fbcon_cfb8_putc, - fbcon_cfb8_putcs, - fbcon_cfb8_revc, - NULL, + tdfx_cfbX_bmove, + tdfx_cfb8_clear, + tdfx_cfb8_putc, + tdfx_cfb8_putcs, + tdfx_cfbX_revc, + tdfx_cfbX_cursor, NULL, - fbcon_cfb8_clear_margins, + tdfx_cfbX_clear_margins, FONTWIDTH(8) }; #endif #ifdef FBCON_HAS_CFB16 static struct display_switch fbcon_banshee16 = { fbcon_cfb16_setup, - fbcon_banshee_bmove, - fbcon_banshee_clear, - fbcon_cfb16_putc, - fbcon_cfb16_putcs, - fbcon_cfb16_revc, + tdfx_cfbX_bmove, + tdfx_cfb16_clear, + tdfx_cfb16_putc, + tdfx_cfb16_putcs, + tdfx_cfbX_revc, + tdfx_cfbX_cursor, NULL, + tdfx_cfbX_clear_margins, + FONTWIDTH(8) +}; +#endif +#ifdef FBCON_HAS_CFB24 +static struct display_switch fbcon_banshee24 = { + fbcon_cfb24_setup, + tdfx_cfbX_bmove, + tdfx_cfb24_clear, + tdfx_cfb24_putc, + tdfx_cfb24_putcs, + tdfx_cfbX_revc, + tdfx_cfbX_cursor, NULL, - fbcon_cfb16_clear_margins, + tdfx_cfbX_clear_margins, FONTWIDTH(8) }; #endif #ifdef FBCON_HAS_CFB32 static struct display_switch fbcon_banshee32 = { fbcon_cfb32_setup, - fbcon_banshee_bmove, - fbcon_banshee_clear, - fbcon_cfb32_putc, - fbcon_cfb32_putcs, - fbcon_cfb32_revc, - NULL, + tdfx_cfbX_bmove, + tdfx_cfb32_clear, + tdfx_cfb32_putc, + tdfx_cfb32_putcs, + tdfx_cfbX_revc, + tdfx_cfbX_cursor, NULL, - fbcon_cfb32_clear_margins, + tdfx_cfbX_clear_margins, FONTWIDTH(8) }; #endif @@ -883,13 +1326,13 @@ static void tdfxfb_set_par(const struct tdfxfb_par* par, struct fb_info_tdfx* info) { struct fb_info_tdfx* i = (struct fb_info_tdfx*)info; struct banshee_reg reg; - __u32 cpp; - __u32 hd, hs, he, ht, hbs, hbe; - __u32 vd, vs, ve, vt, vbs, vbe; - __u32 wd; + u32 cpp; + u32 hd, hs, he, ht, hbs, hbe; + u32 vd, vs, ve, vt, vbs, vbe; + u32 wd; int fout; int freq; - + memset(®, 0, sizeof(reg)); cpp = (par->bpp + 7)/8; @@ -1018,11 +1461,21 @@ static void tdfxfb_set_par(const struct tdfxfb_par* par, reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | + VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0); + + fb_info.cursor.enable=reg.vidcfg | VIDCFG_HWCURSOR_ENABLE; + fb_info.cursor.disable=reg.vidcfg; + reg.stride = par->width*cpp; reg.cursloc = 0; - + + reg.cursc0 = 0; + reg.cursc1 = 0xffffff; + + reg.curspataddr = fb_info.cursor.cursorimage; + reg.startaddr = par->baseline*reg.stride; reg.srcbase = reg.startaddr; reg.dstbase = reg.startaddr; @@ -1037,18 +1490,19 @@ static void tdfxfb_set_par(const struct tdfxfb_par* par, reg.dacmode |= DACMODE_2X; reg.vidcfg |= VIDCFG_2X; } - reg.vidpll = banshee_calc_pll(freq, &fout); + reg.vidpll = do_calc_pll(freq, &fout); #if 0 - reg.mempll = banshee_calc_pll(..., &fout); - reg.gfxpll = banshee_calc_pll(..., &fout); + reg.mempll = do_calc_pll(..., &fout); + reg.gfxpll = do_calc_pll(..., &fout); #endif reg.screensize = par->width | (par->height << 12); reg.vidcfg &= ~VIDCFG_HALF_MODE; - banshee_write_regs(®); + do_write_regs(®); i->current_par = *par; + } static int tdfxfb_decode_var(const struct fb_var_screeninfo* var, @@ -1058,6 +1512,7 @@ static int tdfxfb_decode_var(const struct fb_var_screeninfo* var, if(var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && + var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { DPRINTK("depth not supported: %u\n", var->bits_per_pixel); return -EINVAL; @@ -1078,18 +1533,12 @@ static int tdfxfb_decode_var(const struct fb_var_screeninfo* var, return -EINVAL; } - if(nopan && nowrap) { - if(var->yres != var->yres_virtual) { - DPRINTK("virtual y resolution != physical y resolution not supported\n"); - return -EINVAL; - } - } else { - if(var->yres > var->yres_virtual) { - DPRINTK("virtual y resolution < physical y resolution not possible\n"); - return -EINVAL; - } + if(var->yres > var->yres_virtual) { + DPRINTK("virtual y resolution < physical y resolution not possible\n"); + return -EINVAL; } + /* fixme: does Voodoo3 support interlace? Banshee doesn't */ if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { DPRINTK("interlace not supported\n"); return -EINVAL; @@ -1106,8 +1555,9 @@ static int tdfxfb_decode_var(const struct fb_var_screeninfo* var, par->height_virt = var->yres_virtual; par->bpp = var->bits_per_pixel; par->ppitch = var->bits_per_pixel; - par->lpitch = par->width*par->ppitch/8; - + par->lpitch = par->width* ((par->ppitch+7)>>3); + par->cmap_len = (par->bpp == 8) ? 256 : 16; + par->baseline = 0; if(par->width < 320 || par->width > 2048) { @@ -1190,6 +1640,11 @@ static int tdfxfb_encode_var(struct fb_var_screeninfo* var, v.blue.offset = 0; v.blue.length = 5; break; + case 24: + v.red.offset=16; + v.green.offset=8; + v.blue.offset=0; + v.red.length = v.green.length = v.blue.length = 8; case 32: v.red.offset = 16; v.green.offset = 8; @@ -1230,10 +1685,10 @@ static int tdfxfb_encode_fix(struct fb_fix_screeninfo* fix, switch(info->dev) { case PCI_DEVICE_ID_3DFX_BANSHEE: case PCI_DEVICE_ID_3DFX_VOODOO3: - if (info->dev == PCI_DEVICE_ID_3DFX_BANSHEE) - strcpy(fix->id, "3Dfx Banshee"); - else - strcpy(fix->id, "3Dfx Voodoo3"); + strcpy(fix->id, + info->dev == PCI_DEVICE_ID_3DFX_BANSHEE + ? "3Dfx Banshee" + : "3Dfx Voodoo3"); #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) fix->smem_start = (char*)info->bufbase_phys; fix->smem_len = info->bufbase_size; @@ -1249,12 +1704,12 @@ static int tdfxfb_encode_fix(struct fb_fix_screeninfo* fix, fix->type = FB_TYPE_PACKED_PIXELS; fix->type_aux = 0; fix->line_length = par->lpitch; - fix->visual = par->bpp == 8 - ? FB_VISUAL_PSEUDOCOLOR - : FB_VISUAL_DIRECTCOLOR; + fix->visual = (par->bpp == 8) + ? FB_VISUAL_PSEUDOCOLOR + : FB_VISUAL_DIRECTCOLOR; fix->xpanstep = 0; - fix->ypanstep = (nowrap && nopan) ? 0 : 1; + fix->ypanstep = nopan ? 0 : 1; fix->ywrapstep = nowrap ? 0 : 1; break; @@ -1290,19 +1745,20 @@ static int tdfxfb_get_var(struct fb_var_screeninfo *var, *var = fb_display[con].var; return 0; } - + static void tdfxfb_set_disp(struct display *disp, struct fb_info_tdfx *info, int bpp, int accel) { - DPRINTK("actually, %s using acceleration!\n", - noaccel ? "NOT" : ""); + if (disp->dispsw && disp->conp) + fb_con.con_cursor(disp->conp, CM_ERASE); switch(bpp) { #ifdef FBCON_HAS_CFB8 case 8: info->dispsw = noaccel ? fbcon_cfb8 : fbcon_banshee8; disp->dispsw = &info->dispsw; + if (nohwcursor) fbcon_banshee8.cursor = NULL; break; #endif #ifdef FBCON_HAS_CFB16 @@ -1310,6 +1766,15 @@ static void tdfxfb_set_disp(struct display *disp, info->dispsw = noaccel ? fbcon_cfb16 : fbcon_banshee16; disp->dispsw = &info->dispsw; disp->dispsw_data = info->fbcon_cmap.cfb16; + if (nohwcursor) fbcon_banshee16.cursor = NULL; + break; +#endif +#ifdef FBCON_HAS_CFB24 + case 24: + info->dispsw = noaccel ? fbcon_cfb24 : fbcon_banshee24; + disp->dispsw = &info->dispsw; + disp->dispsw_data = info->fbcon_cmap.cfb24; + if (nohwcursor) fbcon_banshee24.cursor = NULL; break; #endif #ifdef FBCON_HAS_CFB32 @@ -1317,161 +1782,159 @@ static void tdfxfb_set_disp(struct display *disp, info->dispsw = noaccel ? fbcon_cfb32 : fbcon_banshee32; disp->dispsw = &info->dispsw; disp->dispsw_data = info->fbcon_cmap.cfb32; + if (nohwcursor) fbcon_banshee32.cursor = NULL; break; #endif default: info->dispsw = fbcon_dummy; disp->dispsw = &info->dispsw; } + } static int tdfxfb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb) { - struct fb_info_tdfx *info = (struct fb_info_tdfx*)fb; - struct tdfxfb_par par; - struct display *display; - int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel, err; - int activate = var->activate; - - if(con >= 0) - display = &fb_display[con]; - else - display = fb->disp; /* used during initialization */ - - if((err = tdfxfb_decode_var(var, &par, info))) - return err; - - tdfxfb_encode_var(var, &par, info); - - if((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) { - oldxres = display->var.xres; - oldyres = display->var.yres; - oldvxres = display->var.xres_virtual; - oldvyres = display->var.yres_virtual; - oldbpp = display->var.bits_per_pixel; - oldaccel = display->var.accel_flags; - display->var = *var; - if(con < 0 || - oldxres != var->xres || - oldyres != var->yres || - oldvxres != var->xres_virtual || - oldvyres != var->yres_virtual || - oldbpp != var->bits_per_pixel || - oldaccel != var->accel_flags) { - struct fb_fix_screeninfo fix; - - tdfxfb_encode_fix(&fix, &par, info); - display->screen_base = (char *)info->bufbase_virt; - display->visual = fix.visual; - display->type = fix.type; - display->type_aux = fix.type_aux; - display->ypanstep = fix.ypanstep; - display->ywrapstep = fix.ywrapstep; - display->line_length = fix.line_length; - display->next_line = fix.line_length; - display->can_soft_blank = 1; - display->inverse = inverse; - accel = var->accel_flags & FB_ACCELF_TEXT; - tdfxfb_set_disp(display, info, par.bpp, accel); - - if(nopan && nowrap) { - display->scrollmode = SCROLL_YREDRAW; -#ifdef FBCON_HAS_CFB8 - fbcon_banshee8.bmove = fbcon_redraw_bmove; -#endif -#ifdef FBCON_HAS_CFB16 - fbcon_banshee16.bmove = fbcon_redraw_bmove; -#endif -#ifdef FBCON_HAS_CFB32 - fbcon_banshee32.bmove = fbcon_redraw_bmove; -#endif + struct fb_info_tdfx *info = (struct fb_info_tdfx*)fb; + struct tdfxfb_par par; + struct display *display; + int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel, err; + int activate = var->activate; + int j,k; + + if(con >= 0) + display = &fb_display[con]; + else + display = fb->disp; /* used during initialization */ + + if((err = tdfxfb_decode_var(var, &par, info))) + return err; + + tdfxfb_encode_var(var, &par, info); + + if((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) { + oldxres = display->var.xres; + oldyres = display->var.yres; + oldvxres = display->var.xres_virtual; + oldvyres = display->var.yres_virtual; + oldbpp = display->var.bits_per_pixel; + oldaccel = display->var.accel_flags; + display->var = *var; + if(con < 0 || + oldxres != var->xres || + oldyres != var->yres || + oldvxres != var->xres_virtual || + oldvyres != var->yres_virtual || + oldbpp != var->bits_per_pixel || + oldaccel != var->accel_flags) { + struct fb_fix_screeninfo fix; + + tdfxfb_encode_fix(&fix, &par, info); + display->screen_base = (char *)info->bufbase_virt; + display->visual = fix.visual; + display->type = fix.type; + display->type_aux = fix.type_aux; + display->ypanstep = fix.ypanstep; + display->ywrapstep = fix.ywrapstep; + display->line_length = fix.line_length; + display->next_line = fix.line_length; + display->can_soft_blank = 1; + display->inverse = inverse; + accel = var->accel_flags & FB_ACCELF_TEXT; + tdfxfb_set_disp(display, info, par.bpp, accel); + + if(nopan) display->scrollmode = SCROLL_YREDRAW; + + if (info->fb_info.changevar) + (*info->fb_info.changevar)(con); } - if (info->fb_info.changevar) - (*info->fb_info.changevar)(con); - } - if(!info->fb_info.display_fg || - info->fb_info.display_fg->vc_num == con || - con < 0) - tdfxfb_set_par(&par, info); - if(oldbpp != var->bits_per_pixel || con < 0) { - if((err = fb_alloc_cmap(&display->cmap, 0, 0))) - return err; - tdfxfb_install_cmap(con, &info->fb_info); - } - } + if (var->bits_per_pixel==8) + for(j = 0; j < 16; j++) { + k = color_table[j]; + fb_info.palette[j].red = default_red[k]; + fb_info.palette[j].green = default_grn[k]; + fb_info.palette[j].blue = default_blu[k]; + } + + del_timer(&(info->cursor.timer)); + fb_info.cursor.state=CM_ERASE; + if(!info->fb_info.display_fg || + info->fb_info.display_fg->vc_num == con || + con < 0) + tdfxfb_set_par(&par, info); + if (!nohwcursor) + if (display && display->conp) + tdfxfb_createcursor( display ); + info->cursor.redraw=1; + if(oldbpp != var->bits_per_pixel || con < 0) { + if((err = fb_alloc_cmap(&display->cmap, 0, 0))) + return err; + tdfxfb_install_cmap(display, &(info->fb_info)); + } + } - return 0; + return 0; } static int tdfxfb_pan_display(struct fb_var_screeninfo* var, int con, struct fb_info* fb) { struct fb_info_tdfx* i = (struct fb_info_tdfx*)fb; - __u32 addr; - if(nowrap && nopan) { - return -EINVAL; - } else { - if(var->xoffset) - return -EINVAL; - if(var->yoffset < 0) - return -EINVAL; - if(nopan && var->yoffset > var->yres_virtual) - return -EINVAL; - if(nowrap && var->yoffset + var->yres > var->yres_virtual) - return -EINVAL; - - i->current_par.baseline = var->yoffset; - - addr = var->yoffset*i->current_par.lpitch; - tdfx_outl(VIDDESKSTART, addr); - tdfx_outl(SRCBASE, addr); - tdfx_outl(DSTBASE, addr); - return 0; - } + if(nopan) return -EINVAL; + if(var->xoffset) return -EINVAL; + if(var->yoffset > var->yres_virtual) return -EINVAL; + if(nowrap && + (var->yoffset + var->yres > var->yres_virtual)) return -EINVAL; + + if (con==currcon) + do_pan_var(var,i); + + fb_display[con].var.xoffset=var->xoffset; + fb_display[con].var.yoffset=var->yoffset; + return 0; } static int tdfxfb_get_cmap(struct fb_cmap *cmap, int kspc, int con, struct fb_info *fb) { - if(!fb->display_fg || con == fb->display_fg->vc_num) { - /* current console? */ - return fb_get_cmap(cmap, kspc, tdfxfb_getcolreg, fb); - } else if(fb_display[con].cmap.len) { - /* non default colormap? */ - fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2); - } else { - int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256; - fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2); - } - return 0; + + struct fb_info_tdfx* i = (struct fb_info_tdfx*)fb; + struct display *d=(con<0) ? fb->disp : fb_display + con; + + if(con == currcon) { + /* current console? */ + return fb_get_cmap(cmap, kspc, tdfxfb_getcolreg, fb); + } else if(d->cmap.len) { + /* non default colormap? */ + fb_copy_cmap(&d->cmap, cmap, kspc ? 0 : 2); + } else { + fb_copy_cmap(fb_default_cmap(i->current_par.cmap_len), cmap, kspc ? 0 : 2); + } + return 0; } static int tdfxfb_set_cmap(struct fb_cmap *cmap, int kspc, int con, struct fb_info *fb) { - int err; - struct display *disp; + struct display *d=(con<0) ? fb->disp : fb_display + con; + struct fb_info_tdfx *i = (struct fb_info_tdfx*)fb; - if(con >= 0) - disp = &fb_display[con]; - else - disp = fb->disp; - if(!disp->cmap.len) { /* no colormap allocated? */ - int size = disp->var.bits_per_pixel == 16 ? 32 : 256; - if((err = fb_alloc_cmap(&disp->cmap, size, 0))) - return err; - } - if(!fb->display_fg || con == fb->display_fg->vc_num) { - /* current console? */ - return fb_set_cmap(cmap, kspc, tdfxfb_setcolreg, fb); - } else { - fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1); - } - return 0; + int cmap_len= (i->current_par.bpp == 8) ? 256 : 16; + if (d->cmap.len!=cmap_len) { + int err; + if((err = fb_alloc_cmap(&d->cmap, cmap_len, 0))) + return err; + } + if(con == currcon) { + /* current console? */ + return fb_set_cmap(cmap, kspc, tdfxfb_setcolreg, fb); + } else { + fb_copy_cmap(cmap, &d->cmap, kspc ? 0 : 1); + } + return 0; } static int tdfxfb_ioctl(struct inode *inode, @@ -1480,7 +1943,16 @@ static int tdfxfb_ioctl(struct inode *inode, u_long arg, int con, struct fb_info *fb) { - return -EINVAL; +/* These IOCTLs ar just for testing only... + switch (cmd) { + case 0x4680: + nowrap=nopan=0; + return 0; + case 0x4681: + nowrap=nopan=1; + return 0; + }*/ + return -EINVAL; } #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) @@ -1490,8 +1962,7 @@ int __init tdfxfb_init(void) { #endif struct pci_dev *pdev = NULL; struct fb_var_screeninfo var; - int j, k; - + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) if(!pcibios_present()) return; #else @@ -1503,7 +1974,10 @@ int __init tdfxfb_init(void) { (pdev->vendor == PCI_VENDOR_ID_3DFX) && ((pdev->device == PCI_DEVICE_ID_3DFX_BANSHEE) || (pdev->device == PCI_DEVICE_ID_3DFX_VOODOO3))) { - + char* name = pdev->device == PCI_DEVICE_ID_3DFX_BANSHEE + ? "Banshee" + : "Voodoo3"; + fb_info.dev = pdev->device; fb_info.max_pixclock = pdev->device == PCI_DEVICE_ID_3DFX_BANSHEE @@ -1512,82 +1986,79 @@ int __init tdfxfb_init(void) { #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) fb_info.regbase_phys = pdev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; - fb_info.regbase_size = 1 << 25; + fb_info.regbase_size = 1 << 24; fb_info.regbase_virt = - (__u32)ioremap_nocache(fb_info.regbase_phys, 1 << 25); + (u32)ioremap_nocache(fb_info.regbase_phys, 1 << 24); if(!fb_info.regbase_virt) { - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Can't remap Banshee register area.\n"); - else - printk("fb: Can't remap Voodoo3 register area.\n"); + printk("fb: Can't remap %s register area.\n", name); return; } fb_info.bufbase_phys = pdev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK; - if(!(fb_info.bufbase_size = tdfx_lfb_size())) { - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Can't count Banshee memory.\n"); - else - printk("fb: Can't count Voodoo3 memory.\n"); + if(!(fb_info.bufbase_size = do_lfb_size())) { + printk("fb: Can't count %s memory.\n", name); iounmap((void*)fb_info.regbase_virt); return; } fb_info.bufbase_virt = - (__u32)ioremap_nocache(fb_info.bufbase_phys, 1 << 25); + (u32)ioremap_nocache(fb_info.bufbase_phys, fb_info.bufbase_size); if(!fb_info.regbase_virt) { - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Can't remap Banshee framebuffer.\n"); - else - printk("fb: Can't remap Voodoo3 framebuffer.\n"); + printk("fb: Can't remap %s framebuffer.\n", name); iounmap((void*)fb_info.regbase_virt); return; } + + fb_info.iobase = pdev->base_address[2] & PCI_BASE_ADDRESS_IO_MASK; #else fb_info.regbase_phys = pdev->resource[0].start; - fb_info.regbase_size = 1 << 25; + fb_info.regbase_size = 1 << 24; fb_info.regbase_virt = - (__u32)ioremap_nocache(fb_info.regbase_phys, 1 << 25); + (u32)ioremap_nocache(fb_info.regbase_phys, 1 << 24); if(!fb_info.regbase_virt) { - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Can't remap Banshee register area.\n"); - else - printk("fb: Can't remap Voodoo3 register area.\n"); + printk("fb: Can't remap %s register area.\n", name); return -ENXIO; } fb_info.bufbase_phys = pdev->resource[1].start; - if(!(fb_info.bufbase_size = tdfx_lfb_size())) { + if(!(fb_info.bufbase_size = do_lfb_size())) { iounmap((void*)fb_info.regbase_virt); - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Can't count Banshee memory.\n"); - else - printk("fb: Can't count Voodoo3 memory.\n"); + printk("fb: Can't count %s memory.\n", name); return -ENXIO; } fb_info.bufbase_virt = - (__u32)ioremap_nocache(fb_info.bufbase_phys, 1 << 25); + (u32)ioremap_nocache(fb_info.bufbase_phys, fb_info.bufbase_size); if(!fb_info.regbase_virt) { - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Can't remap Banshee framebuffer.\n"); - else - printk("fb: Can't remap Voodoo3 framebuffer.\n"); + printk("fb: Can't remap %s framebuffer.\n", name); iounmap((void*)fb_info.regbase_virt); return -ENXIO; } + + fb_info.iobase = pdev->resource[2].start; #endif - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - printk("fb: Banshee memory = %ldK\n", fb_info.bufbase_size >> 10); - else - printk("fb: Voodoo3 memory = %ldK\n", fb_info.bufbase_size >> 10); - + printk("fb: %s memory = %ldK\n", name, fb_info.bufbase_size >> 10); + +#ifdef CONFIG_MTRR + if (!nomtrr) { + if (mtrr_add(fb_info.bufbase_phys, fb_info.bufbase_size, + MTRR_TYPE_WRCOMB, 1)>=0) + printk("fb: MTRR's turned on\n"); + } +#endif + /* clear framebuffer memory */ memset_io(fb_info.bufbase_virt, 0, fb_info.bufbase_size); - - if (fb_info.dev == PCI_DEVICE_ID_3DFX_BANSHEE) - strcpy(fb_info.fb_info.modename, "3Dfx Banshee"); - else - strcpy(fb_info.fb_info.modename, "3Dfx Voodoo3"); + currcon = -1; + if (!nohwcursor) tdfxfb_hwcursor_init(); + + fb_info.cursor.timer.function = do_flashcursor; + fb_info.cursor.state = CM_ERASE; + fb_info.cursor.timer.prev = fb_info.cursor.timer.next=NULL; + fb_info.cursor.timer.data = (unsigned long)(&fb_info); + spin_lock_init(&fb_info.DAClock); + + strcpy(fb_info.fb_info.modename, "3Dfx "); + strcat(fb_info.fb_info.modename, name); fb_info.fb_info.changevar = NULL; fb_info.fb_info.node = -1; fb_info.fb_info.fbops = &tdfxfb_ops; @@ -1624,6 +2095,7 @@ int __init tdfxfb_init(void) { else var.accel_flags |= FB_ACCELF_TEXT; if(tdfxfb_decode_var(&var, &fb_info.default_par, &fb_info)) { + /* this is getting really bad!... */ printk("tdfxfb: can't decode default video mode\n"); #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) return; @@ -1634,33 +2106,7 @@ int __init tdfxfb_init(void) { } fb_info.disp.screen_base = (void*)fb_info.bufbase_virt; - fb_info.disp.visual = - var.bits_per_pixel == 8 - ? FB_VISUAL_PSEUDOCOLOR - : FB_VISUAL_DIRECTCOLOR; - fb_info.disp.type = FB_TYPE_PACKED_PIXELS; - fb_info.disp.type_aux = 0; - - fb_info.disp.ypanstep = (nowrap && nopan) ? 0 : 1; - fb_info.disp.ywrapstep = nowrap ? 0 : 1; - - fb_info.disp.line_length = - fb_info.disp.next_line = - var.xres*(var.bits_per_pixel + 7)/8; - fb_info.disp.can_soft_blank = 1; - fb_info.disp.inverse = inverse; - fb_info.disp.scrollmode = SCROLL_YREDRAW; fb_info.disp.var = var; - tdfxfb_set_disp(&fb_info.disp, &fb_info, - var.bits_per_pixel, - 0); - - for(j = 0; j < 16; j++) { - k = color_table[j]; - fb_info.palette[j].red = default_red[k]; - fb_info.palette[j].green = default_grn[k]; - fb_info.palette[j].blue = default_blu[k]; - } if(tdfxfb_set_var(&var, -1, &fb_info.fb_info)) { printk("tdfxfb: can't set default video mode\n"); @@ -1694,6 +2140,7 @@ int __init tdfxfb_init(void) { } } + /* hmm, no frame suitable buffer found ... */ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,1) return; #else @@ -1715,11 +2162,17 @@ void tdfxfb_setup(char *options, inverse = 1; fb_invert_cmaps(); } else if(!strcmp(this_opt, "noaccel")) { - noaccel = 1; + noaccel = nopan = nowrap = nohwcursor = 1; } else if(!strcmp(this_opt, "nopan")) { nopan = 1; } else if(!strcmp(this_opt, "nowrap")) { nowrap = 1; + } else if (!strcmp(this_opt, "nohwcursor")) { + nohwcursor = 1; +#ifdef CONFIG_MTRR + } else if (!strcmp(this_opt, "nomtrr")) { + nomtrr = 1; +#endif } else if (!strncmp(this_opt, "font:", 5)) { strncpy(fontname, this_opt + 5, 40); } else { @@ -1739,26 +2192,39 @@ void tdfxfb_setup(char *options, static int tdfxfb_switch_con(int con, struct fb_info *fb) { - struct fb_info_tdfx *info = (struct fb_info_tdfx*)fb; - struct tdfxfb_par par; - - /* Do we have to save the colormap? */ - if(fb_display[currcon].cmap.len) - fb_get_cmap(&fb_display[currcon].cmap, 1, tdfxfb_getcolreg, fb); - - currcon = con; - - tdfxfb_decode_var(&fb_display[con].var, &par, info); - tdfxfb_set_par(&par, info); - tdfxfb_set_disp(&fb_display[con], - info, - par.bpp, - par.accel_flags & FB_ACCELF_TEXT); - - tdfxfb_install_cmap(con, fb); - tdfxfb_updatevar(con, fb); - - return 1; + struct fb_info_tdfx *info = (struct fb_info_tdfx*)fb; + struct tdfxfb_par par; + + /* Do we have to save the colormap? */ + if (currcon>=0) + if(fb_display[currcon].cmap.len) + fb_get_cmap(&fb_display[currcon].cmap, 1, tdfxfb_getcolreg, fb); + + currcon = con; + fb_display[currcon].var.activate = FB_ACTIVATE_NOW; + tdfxfb_decode_var(&fb_display[con].var, &par, info); + tdfxfb_set_par(&par, info); + if (fb_display[con].dispsw && fb_display[con].conp) + fb_con.con_cursor(fb_display[con].conp, CM_ERASE); + + del_timer(&(info->cursor.timer)); + fb_info.cursor.state=CM_ERASE; + + if (!nohwcursor) + if (fb_display[con].conp) + tdfxfb_createcursor( &fb_display[con] ); + + info->cursor.redraw=1; + + tdfxfb_set_disp(&fb_display[con], + info, + par.bpp, + par.accel_flags & FB_ACCELF_TEXT); + + tdfxfb_install_cmap(&fb_display[con], fb); + tdfxfb_updatevar(con, fb); + + return 1; } /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */ @@ -1793,6 +2259,7 @@ static void tdfxfb_blank(int blank, dacmode &= ~(BIT(1) | BIT(3)); dacmode |= state; + banshee_make_room(1); tdfx_outl(DACMODE, dacmode); if(vgablank) vga_disable_video(); @@ -1804,12 +2271,11 @@ static void tdfxfb_blank(int blank, static int tdfxfb_updatevar(int con, struct fb_info* fb) { - if(con != currcon || (nowrap && nopan)) { - return 0; - } else { - struct fb_var_screeninfo* var = &fb_display[currcon].var; - return tdfxfb_pan_display(var, con, fb); - } + + struct fb_info_tdfx* i = (struct fb_info_tdfx*)fb; + if ((con==currcon) && (!nopan)) + do_pan_var(&fb_display[con].var,i); + return 0; } static int tdfxfb_getcolreg(unsigned regno, @@ -1818,15 +2284,16 @@ static int tdfxfb_getcolreg(unsigned regno, unsigned* blue, unsigned* transp, struct fb_info* fb) { - struct fb_info_tdfx* i = (struct fb_info_tdfx*)fb; - - if(regno < 256) { - *red = i->palette[regno].red << 8 | i->palette[regno].red; - *green = i->palette[regno].green << 8 | i->palette[regno].green; - *blue = i->palette[regno].blue << 8 | i->palette[regno].blue; - *transp = 0; - } - return regno > 255; + struct fb_info_tdfx* i = (struct fb_info_tdfx*)fb; + + if (regno > i->current_par.cmap_len) return 1; + + *red = i->palette[regno].red; + *green = i->palette[regno].green; + *blue = i->palette[regno].blue; + *transp = 0; + + return 0; } static int tdfxfb_setcolreg(unsigned regno, @@ -1835,12 +2302,21 @@ static int tdfxfb_setcolreg(unsigned regno, unsigned blue, unsigned transp, struct fb_info* info) { - struct fb_info_tdfx* i = (struct fb_info_tdfx*)info; - - if(regno < 16) { - switch(i->current_par.bpp) { + struct fb_info_tdfx* i = (struct fb_info_tdfx*)info; + u32 rgbcol; + if (regno >= i->current_par.cmap_len) return 1; + + i->palette[regno].red = red; + i->palette[regno].green = green; + i->palette[regno].blue = blue; + + switch(i->current_par.bpp) { #ifdef FBCON_HAS_CFB8 case 8: + rgbcol=(((u32)red & 0xff00) << 8) | + (((u32)green & 0xff00) << 0) | + (((u32)blue & 0xff00) >> 8); + do_setpalentry(regno,rgbcol); break; #endif #ifdef FBCON_HAS_CFB16 @@ -1849,6 +2325,14 @@ static int tdfxfb_setcolreg(unsigned regno, (((u32)red & 0xf800) >> 0) | (((u32)green & 0xfc00) >> 5) | (((u32)blue & 0xf800) >> 11); + break; +#endif +#ifdef FBCON_HAS_CFB24 + case 24: + i->fbcon_cmap.cfb24[regno] = + (((u32)red & 0xff00) << 8) | + (((u32)green & 0xff00) << 0) | + (((u32)blue & 0xff00) >> 8); break; #endif #ifdef FBCON_HAS_CFB32 @@ -1862,30 +2346,105 @@ static int tdfxfb_setcolreg(unsigned regno, default: DPRINTK("bad depth %u\n", i->current_par.bpp); break; - } - } - if(regno < 256) { - i->palette[regno].red = red >> 8; - i->palette[regno].green = green >> 8; - i->palette[regno].blue = blue >> 8; - if(i->current_par.bpp == 8) { - vga_outb(DAC_IW, (unsigned char)regno); - vga_outb(DAC_D, (unsigned char)(red >> 8)); - vga_outb(DAC_D, (unsigned char)(green >> 8)); - vga_outb(DAC_D, (unsigned char)(blue >> 8)); - } - } - return regno > 255; + } + return 0; } -static void tdfxfb_install_cmap(int con, - struct fb_info* info) { - if(con != currcon) return; - if(fb_display[con].cmap.len) { - fb_set_cmap(&fb_display[con].cmap, 1, tdfxfb_setcolreg, info); - } else { - int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256; - fb_set_cmap(fb_default_cmap(size), 1, tdfxfb_setcolreg, info); - } +static void tdfxfb_install_cmap(struct display *d,struct fb_info *info) +{ + struct fb_info_tdfx* i = (struct fb_info_tdfx*)info; + + if(d->cmap.len) { + fb_set_cmap(&(d->cmap), 1, tdfxfb_setcolreg, info); + } else { + fb_set_cmap(fb_default_cmap(i->current_par.cmap_len), 1, + tdfxfb_setcolreg, info); + } } +static void tdfxfb_createcursorshape(struct display* p) +{ + unsigned int h,cu,cd; + + h=fontheight(p); + cd=h; + if (cd >= 10) cd --; + fb_info.cursor.type=p->conp->vc_cursor_type & CUR_HWMASK; + switch (fb_info.cursor.type) { + case CUR_NONE: + cu=cd; + break; + case CUR_UNDERLINE: + cu=cd - 2; + break; + case CUR_LOWER_THIRD: + cu=(h * 2) / 3; + break; + case CUR_LOWER_HALF: + cu=h / 2; + break; + case CUR_TWO_THIRDS: + cu=h / 3; + break; + case CUR_BLOCK: + default: + cu=0; + cd = h; + break; + } + fb_info.cursor.w=fontwidth(p); + fb_info.cursor.u=cu; + fb_info.cursor.d=cd; +} + +static void tdfxfb_createcursor(struct display *p) +{ + u8 *cursorbase; + u32 xline; + unsigned int i; + unsigned int h,to; + + tdfxfb_createcursorshape(p); + xline = (1 << fb_info.cursor.w)-1; + cursorbase=(u8*)fb_info.bufbase_virt; + h=fb_info.cursor.cursorimage; + + to=fb_info.cursor.u; + for (i = 0; i < to; i++) { + writel(0, cursorbase+h); + writel(0, cursorbase+h+4); + writel(~0, cursorbase+h+8); + writel(~0, cursorbase+h+12); + h += 16; + } + + to = fb_info.cursor.d; + + for (; i < to; i++) { + writel(xline, cursorbase+h); + writel(0, cursorbase+h+4); + writel(~0, cursorbase+h+8); + writel(~0, cursorbase+h+12); + h += 16; + } + + for (; i < 64; i++) { + writel(0, cursorbase+h); + writel(0, cursorbase+h+4); + writel(~0, cursorbase+h+8); + writel(~0, cursorbase+h+12); + h += 16; + } +} + +static void tdfxfb_hwcursor_init(void) +{ + unsigned int start; + start = (fb_info.bufbase_size-1024) & PAGE_MASK; + fb_info.bufbase_size=start; + fb_info.cursor.cursorimage=fb_info.bufbase_size; + printk("tdfxfb: reserving 1024 bytes for the hwcursor at 0x%08lx\n", + fb_info.regbase_virt+fb_info.cursor.cursorimage); +} + + |