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authorRalf Baechle <ralf@linux-mips.org>1999-02-15 02:15:32 +0000
committerRalf Baechle <ralf@linux-mips.org>1999-02-15 02:15:32 +0000
commit86464aed71025541805e7b1515541aee89879e33 (patch)
treee01a457a4912a8553bc65524aa3125d51f29f810 /include/asm-arm/arch-ebsa285/hardware.h
parent88f99939ecc6a95a79614574cb7d95ffccfc3466 (diff)
Merge with Linux 2.2.1.
Diffstat (limited to 'include/asm-arm/arch-ebsa285/hardware.h')
-rw-r--r--include/asm-arm/arch-ebsa285/hardware.h70
1 files changed, 5 insertions, 65 deletions
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index a9bc6f0a4..e08c5b823 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -19,12 +19,12 @@
* 0xf8000000 0x7b010000 PCI Config type 0
*
*/
+
+#include <asm/dec21285.h>
-#define IO_END 0xffffffff
#define IO_BASE 0xe0000000
-#define IO_SIZE (IO_END - IO_BASE)
-
-#define HAS_PCIO
+#define PCIO_BASE 0xffe00000
+#define PCI_IACK 0xfc000000
#define XBUS_LEDS ((volatile unsigned char *)0xfff12000)
#define XBUS_LED_AMBER (1 << 0)
@@ -38,70 +38,10 @@
#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
-#define PCIO_BASE 0xffe00000
-
-#define CSR_SA110_CNTL ((volatile unsigned long *)0xfe00013c)
-#define CSR_PCIADDR_EXTN ((volatile unsigned long *)0xfe000140)
-#define CSR_PREFETCHMEMRANGE ((volatile unsigned long *)0xfe000144)
-#define CSR_XBUS_CYCLE ((volatile unsigned long *)0xfe000148)
-#define CSR_XBUS_IOSTROBE ((volatile unsigned long *)0xfe00014c)
-#define CSR_DOORBELL_PCI ((volatile unsigned long *)0xfe000150)
-#define CSR_DOORBELL_SA110 ((volatile unsigned long *)0xfe000154)
-
-
-#define CSR_UARTDR ((volatile unsigned long *)0xfe000160)
-#define CSR_RXSTAT ((volatile unsigned long *)0xfe000164)
-#define CSR_H_UBRLCR ((volatile unsigned long *)0xfe000168)
-#define CSR_M_UBRLCR ((volatile unsigned long *)0xfe00016c)
-#define CSR_L_UBRLCR ((volatile unsigned long *)0xfe000170)
-#define CSR_UARTCON ((volatile unsigned long *)0xfe000174)
-#define CSR_UARTFLG ((volatile unsigned long *)0xfe000178)
-
-#define CSR_IRQ_STATUS ((volatile unsigned long *)0xfe000180)
-#define CSR_IRQ_RAWSTATUS ((volatile unsigned long *)0xfe000184)
-#define CSR_IRQ_ENABLE ((volatile unsigned long *)0xfe000188)
-#define CSR_IRQ_DISABLE ((volatile unsigned long *)0xfe00018c)
-#define CSR_IRQ_SOFT ((volatile unsigned long *)0xfe000190)
-
-#define CSR_FIQ_STATUS ((volatile unsigned long *)0xfe000280)
-#define CSR_FIQ_RAWSTATUS ((volatile unsigned long *)0xfe000284)
-#define CSR_FIQ_ENABLE ((volatile unsigned long *)0xfe000288)
-#define CSR_FIQ_DISABLE ((volatile unsigned long *)0xfe00028c)
-#define CSR_FIQ_SOFT ((volatile unsigned long *)0xfe000290)
-
-#define CSR_TIMER1_LOAD ((volatile unsigned long *)0xfe000300)
-#define CSR_TIMER1_VALUE ((volatile unsigned long *)0xfe000304)
-#define CSR_TIMER1_CNTL ((volatile unsigned long *)0xfe000308)
-#define CSR_TIMER1_CLR ((volatile unsigned long *)0xfe00030c)
-
-#define CSR_TIMER2_LOAD ((volatile unsigned long *)0xfe000320)
-#define CSR_TIMER2_VALUE ((volatile unsigned long *)0xfe000324)
-#define CSR_TIMER2_CNTL ((volatile unsigned long *)0xfe000328)
-#define CSR_TIMER2_CLR ((volatile unsigned long *)0xfe00032c)
-
-#define CSR_TIMER3_LOAD ((volatile unsigned long *)0xfe000340)
-#define CSR_TIMER3_VALUE ((volatile unsigned long *)0xfe000344)
-#define CSR_TIMER3_CNTL ((volatile unsigned long *)0xfe000348)
-#define CSR_TIMER3_CLR ((volatile unsigned long *)0xfe00034c)
-
-#define CSR_TIMER4_LOAD ((volatile unsigned long *)0xfe000360)
-#define CSR_TIMER4_VALUE ((volatile unsigned long *)0xfe000364)
-#define CSR_TIMER4_CNTL ((volatile unsigned long *)0xfe000368)
-#define CSR_TIMER4_CLR ((volatile unsigned long *)0xfe00036c)
-
-
-#define TIMER_CNTL_ENABLE (1 << 7)
-#define TIMER_CNTL_AUTORELOAD (1 << 6)
-#define TIMER_CNTL_DIV1 (0)
-#define TIMER_CNTL_DIV16 (1 << 2)
-#define TIMER_CNTL_DIV256 (2 << 2)
-#define TIMER_CNTL_CNTEXT (3 << 2)
-
-
#define KERNTOPHYS(a) ((unsigned long)(&a))
#define PARAMS_OFFSET 0x0100
#define PARAMS_BASE (PAGE_OFFSET + PARAMS_OFFSET)
-#define SAFE_ADDR 0x50000000
+#define FLUSH_BASE_PHYS 0x50000000