diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-07-21 22:00:56 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-07-21 22:00:56 +0000 |
| commit | 168660f24dfc46c2702acbe4701a446f42a59578 (patch) | |
| tree | f431368afbf6b1b71809cf3fd904d800ea126f4d /include/asm-arm | |
| parent | 6420f767924fa73b0ea267864d96820815f4ba5a (diff) | |
Merge with Linux 2.4.0-test5-pre3.
Diffstat (limited to 'include/asm-arm')
35 files changed, 4435 insertions, 177 deletions
diff --git a/include/asm-arm/arch-arc/dma.h b/include/asm-arm/arch-arc/dma.h index 49e184769..77d1dfddf 100644 --- a/include/asm-arm/arch-arc/dma.h +++ b/include/asm-arm/arch-arc/dma.h @@ -12,24 +12,15 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H -#include <linux/config.h> - #define MAX_DMA_ADDRESS 0x03000000 - -#ifdef CONFIG_ARCH_ARC #define MAX_DMA_CHANNELS 3 +/* ARC */ #define DMA_VIRTUAL_FLOPPY0 0 #define DMA_VIRTUAL_FLOPPY1 1 #define DMA_VIRTUAL_SOUND 2 -#endif - -#ifdef CONFIG_ARCH_A5K -#define MAX_DMA_CHANNELS 2 -#define DMA_VIRTUAL_FLOPPY 0 -#define DMA_VIRTUAL_SOUND 1 -#define DMA_FLOPPY DMA_VIRTUAL_FLOPPY -#endif +/* A5K */ +#define DMA_FLOPPY DMA_VIRTUAL_FLOPPY0 #endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-arc/hardware.h b/include/asm-arm/arch-arc/hardware.h index 294c18b57..8d734d2bb 100644 --- a/include/asm-arm/arch-arc/hardware.h +++ b/include/asm-arm/arch-arc/hardware.h @@ -54,10 +54,8 @@ #define IOEB_PSCLR 0x800d4016 #define IOEB_MONTYPE 0x800d401c #endif -#ifdef CONFIG_ARCH_ARC #define LATCHAADDR 0x80094010 #define LATCHBADDR 0x80094006 -#endif #define IOC_BASE 0x80080000 #define IO_EC_IOC4_BASE 0x8009c000 diff --git a/include/asm-arm/arch-arc/ide.h b/include/asm-arm/arch-arc/ide.h index 39f91b60b..c24213b20 100644 --- a/include/asm-arm/arch-arc/ide.h +++ b/include/asm-arm/arch-arc/ide.h @@ -11,8 +11,6 @@ * 01-07-1998 RMK Added new ide_ioregspec_t * 29-07-1998 RMK Major re-work of IDE architecture specific code */ - -#include <linux/config.h> #include <asm/irq.h> /* @@ -40,13 +38,13 @@ ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq) */ static __inline__ void ide_init_default_hwifs(void) { -#ifdef CONFIG_ARCH_A5K - hw_regs_t hw; + if (machine_is_a5k()) { + hw_regs_t hw; - memset(&hw, 0, sizeof(hw)); + memset(&hw, 0, sizeof(hw)); - ide_init_hwif_ports(&hw, 0x1f0, 0x3f6, NULL); - hw.irq = IRQ_HARDDISK; - ide_register_hw(&hw, NULL); -#endif + ide_init_hwif_ports(&hw, 0x1f0, 0x3f6, NULL); + hw.irq = IRQ_HARDDISK; + ide_register_hw(&hw, NULL); + } } diff --git a/include/asm-arm/arch-arc/oldlatches.h b/include/asm-arm/arch-arc/oldlatches.h index 42f4c22f4..847d3a0ba 100644 --- a/include/asm-arm/arch-arc/oldlatches.h +++ b/include/asm-arm/arch-arc/oldlatches.h @@ -11,9 +11,6 @@ #ifndef _ASM_ARCH_OLDLATCH_H #define _ASM_ARCH_OLDLATCH_H -#include <linux/config.h> - -#if defined(CONFIG_ARCH_ARC) #define LATCHA_FDSEL0 (1<<0) #define LATCHA_FDSEL1 (1<<1) #define LATCHA_FDSEL2 (1<<2) @@ -34,14 +31,5 @@ void oldlatch_bupdate(unsigned char mask,unsigned char newdata); /* newval=(oldval & mask)|newdata */ void oldlatch_aupdate(unsigned char mask,unsigned char newdata); -void oldlatch_init(void); - -#elif defined(CONFIG_ARCH_A5K) - -#ifdef __need_oldlatches -#error "Old latches not present in this (a5k) machine" -#endif - -#endif #endif diff --git a/include/asm-arm/arch-arc/system.h b/include/asm-arm/arch-arc/system.h index 31db5f390..578f6f70b 100644 --- a/include/asm-arm/arch-arc/system.h +++ b/include/asm-arm/arch-arc/system.h @@ -20,13 +20,11 @@ #endif -extern __inline__ void arch_idle(void) +static void arch_idle(void) { while (!current->need_resched && !hlt_counter); } -#define arch_power_off() do { } while (0) - extern __inline__ void arch_reset(char mode) { extern void ecard_reset(int card); diff --git a/include/asm-arm/arch-cl7500/dma.h b/include/asm-arm/arch-cl7500/dma.h index fb31f5db9..7bab998b9 100644 --- a/include/asm-arm/arch-cl7500/dma.h +++ b/include/asm-arm/arch-cl7500/dma.h @@ -13,7 +13,6 @@ * bytes of RAM. */ #define MAX_DMA_ADDRESS 0xd0000000 - #define MAX_DMA_CHANNELS 1 #define DMA_S0 0 diff --git a/include/asm-arm/arch-cl7500/system.h b/include/asm-arm/arch-cl7500/system.h index a44cc9373..1962f75e0 100644 --- a/include/asm-arm/arch-cl7500/system.h +++ b/include/asm-arm/arch-cl7500/system.h @@ -8,7 +8,7 @@ #include <asm/iomd.h> -extern __inline__ void arch_idle(void) +static void arch_idle(void) { while (!current->need_resched && !hlt_counter) outb(0, IOMD_SUSMODE); @@ -20,6 +20,4 @@ extern __inline__ void arch_idle(void) cpu_reset(0); \ } while (0); -#define arch_power_off() do { } while (0) - #endif diff --git a/include/asm-arm/arch-ebsa110/dma.h b/include/asm-arm/arch-ebsa110/dma.h index 971369789..ae841827a 100644 --- a/include/asm-arm/arch-ebsa110/dma.h +++ b/include/asm-arm/arch-ebsa110/dma.h @@ -3,18 +3,13 @@ * * Architecture DMA routes * - * Copyright (C) 1997.1998 Russell King + * Copyright (C) 1997,1998 Russell King */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H -/* - * This is the maximum DMA address that can be DMAd to. - * There should not be more than (0xd0000000 - 0xc0000000) - * bytes of RAM. - */ -#define MAX_DMA_ADDRESS 0xd0000000 -#define MAX_DMA_CHANNELS 8 +#define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 #endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-ebsa110/system.h b/include/asm-arm/arch-ebsa110/system.h index 767623096..76bd8c2e3 100644 --- a/include/asm-arm/arch-ebsa110/system.h +++ b/include/asm-arm/arch-ebsa110/system.h @@ -10,7 +10,7 @@ * This machine must never stop it MCLK. However, if we are * idle for a long time, slow the processor clock to MCLK. */ -extern __inline__ void arch_idle(void) +static void arch_idle(void) { unsigned long start_idle; @@ -31,7 +31,6 @@ extern __inline__ void arch_idle(void) slow_out: } -#define arch_power_off() do { } while (0) #define arch_reset(mode) cpu_reset(0x80000000) #endif diff --git a/include/asm-arm/arch-ebsa285/system.h b/include/asm-arm/arch-ebsa285/system.h index 0e37477b2..4704e3de3 100644 --- a/include/asm-arm/arch-ebsa285/system.h +++ b/include/asm-arm/arch-ebsa285/system.h @@ -8,7 +8,7 @@ #include <asm/hardware.h> #include <asm/leds.h> -extern __inline__ void arch_idle(void) +static void arch_idle(void) { unsigned long start_idle; @@ -30,8 +30,6 @@ extern __inline__ void arch_idle(void) slow_out: } -#define arch_power_off() do { } while (0) - extern __inline__ void arch_reset(char mode) { if (mode == 's') { diff --git a/include/asm-arm/arch-l7200/dma.h b/include/asm-arm/arch-l7200/dma.h index be68279f7..f7cb3cc52 100644 --- a/include/asm-arm/arch-l7200/dma.h +++ b/include/asm-arm/arch-l7200/dma.h @@ -1,3 +1,6 @@ +/* + * linux/include/asm-arm/arch-l7200/dma.h + */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H diff --git a/include/asm-arm/arch-l7200/system.h b/include/asm-arm/arch-l7200/system.h index c3bbe3773..c299629dd 100644 --- a/include/asm-arm/arch-l7200/system.h +++ b/include/asm-arm/arch-l7200/system.h @@ -11,15 +11,13 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -extern __inline__ void arch_idle(void) +static void arch_idle(void) { while (!current->need_resched && !hlt_counter) { }; /* outb(0, IOMD_SUSMODE);*/ } -#define arch_power_off() do { } while (0) - extern inline void arch_reset(char mode) { if (mode == 's') { diff --git a/include/asm-arm/arch-nexuspci/dma.h b/include/asm-arm/arch-nexuspci/dma.h index d8f89e3c4..585fbe53b 100644 --- a/include/asm-arm/arch-nexuspci/dma.h +++ b/include/asm-arm/arch-nexuspci/dma.h @@ -10,3 +10,4 @@ * This is the maximum DMA address that can be DMAd to. */ #define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 diff --git a/include/asm-arm/arch-nexuspci/system.h b/include/asm-arm/arch-nexuspci/system.h index 0726698e7..cf083f496 100644 --- a/include/asm-arm/arch-nexuspci/system.h +++ b/include/asm-arm/arch-nexuspci/system.h @@ -6,13 +6,12 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -extern __inline__ void arch_idle(void) +static void arch_idle(void) { while (!current->need_resched && !hlt_counter) cpu_do_idle(IDLE_WAIT_SLOW); } #define arch_reset(mode) do { } while (0) -#define arch_power_off() do { } while (0) #endif diff --git a/include/asm-arm/arch-rpc/dma.h b/include/asm-arm/arch-rpc/dma.h index c6b6679af..b52f5b110 100644 --- a/include/asm-arm/arch-rpc/dma.h +++ b/include/asm-arm/arch-rpc/dma.h @@ -1,3 +1,6 @@ +/* + * linux/include/asm-arm/arch-rpc/dma.h + */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H diff --git a/include/asm-arm/arch-rpc/system.h b/include/asm-arm/arch-rpc/system.h index 135f3892d..885e43de3 100644 --- a/include/asm-arm/arch-rpc/system.h +++ b/include/asm-arm/arch-rpc/system.h @@ -7,7 +7,7 @@ #include <asm/iomd.h> #include <asm/io.h> -extern __inline__ void arch_idle(void) +static void arch_idle(void) { unsigned long start_idle; @@ -29,8 +29,6 @@ extern __inline__ void arch_idle(void) slow_out: } -#define arch_power_off() do { } while (0) - extern __inline__ void arch_reset(char mode) { extern void ecard_reset(int card); diff --git a/include/asm-arm/arch-sa1100/SA-1100.h b/include/asm-arm/arch-sa1100/SA-1100.h new file mode 100644 index 000000000..d528c3d2e --- /dev/null +++ b/include/asm-arm/arch-sa1100/SA-1100.h @@ -0,0 +1,2772 @@ +/* + * FILE SA-1100.h + * + * Version 1.2 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date January 1998 (April 1997) + * System StrongARM SA-1100 + * Language C or ARM Assembly + * Purpose Definition of constants related to the StrongARM + * SA-1100 microprocessor (Advanced RISC Machine (ARM) + * architecture version 4). This file is based on the + * StrongARM SA-1100 data sheet version 2.2. + * + * Language-specific definitions are selected by the + * macro "LANGUAGE", which should be defined as either + * "C" (default) or "Assembly". + */ + + +/* Be sure that virtual mapping is defined right */ +#ifndef __ASM_ARCH_HARDWARE_H +#error You must include hardware.h not SA-1100.h +#endif + + +#ifndef LANGUAGE +# ifdef __ASSEMBLY__ +# define LANGUAGE Assembly +# else +# define LANGUAGE C +# endif +#endif + +#ifndef io_p2v +#define io_p2v(PhAdd) (PhAdd) +#endif + +#include <asm/arch/bitfield.h> + +#define C 0 +#define Assembly 1 + + +#if LANGUAGE == C +typedef unsigned short Word16 ; +typedef unsigned int Word32 ; +typedef Word32 Word ; +typedef Word Quad [4] ; +typedef void *Address ; +typedef void (*ExcpHndlr) (void) ; +#endif /* LANGUAGE == C */ + + +/* + * Memory + */ + +#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ + +#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ +#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ + /* [byte] */ +#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ + /* [byte] */ +#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ + /* [byte] */ +#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ + /* [byte] */ + +#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ +#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ +#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ +#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ +#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ + +#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ + +#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ + (0x00000000 + (Nb)*StMemBnkSp) +#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ +#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ +#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ +#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ + +#if LANGUAGE == C +typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; +#define StMemBnk /* Static Memory Bank [0..3] */ \ + ((StMemBnkType *) io_p2v (_StMemBnk (0))) +#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ +#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ +#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ +#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ +#endif /* LANGUAGE == C */ + +#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ + (0xC0000000 + (Nb)*DRAMBnkSp) +#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ +#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ +#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ +#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ + +#if LANGUAGE == C +typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; +#define DRAMBnk /* DRAM Bank [0..3] */ \ + ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) +#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ +#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ +#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ +#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ +#endif /* LANGUAGE == C */ + +#define _ZeroMem 0xE0000000 /* Zero Memory bank */ + +#if LANGUAGE == C +typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; +#define ZeroMem /* Zero Memory bank */ \ + (*((ZeroMemType *) io_p2v (_ZeroMem))) +#endif /* LANGUAGE == C */ + + +/* + * Personal Computer Memory Card International Association (PCMCIA) sockets + */ + +#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ +#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (0x20000000 + (Nb)*PCMCIASp) +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ + +#if LANGUAGE == C + +typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; +typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; + +#define PCMCIA0 /* PCMCIA 0 */ \ + (*((PCMCIAType *) io_p2v (_PCMCIA0))) +#define PCMCIA0IO /* PCMCIA 0 I/O */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) +#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) +#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) + +#define PCMCIA1 /* PCMCIA 1 */ \ + (*((PCMCIAType *) io_p2v (_PCMCIA1))) +#define PCMCIA1IO /* PCMCIA 1 I/O */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) +#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) +#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) + +#endif /* LANGUAGE == C */ + + +/* + * Universal Serial Bus (USB) Device Controller (UDC) control registers + * + * Registers + * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control Register (read/write). + * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Address Register (read/write). + * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Output Maximum Packet size register + * (read/write). + * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Input Maximum Packet size register + * (read/write). + * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 0 + * (read/write). + * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 1 + * (output, read/write). + * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 2 + * (input, read/write). + * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data register end-point 0 + * (read/write). + * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Write Count register end-point 0 + * (read). + * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data Register (read/write). + * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Status Register (read/write). + */ + +#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ +#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ +#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ + /* Packet size reg. */ +#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ + /* Packet size reg. */ +#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 0 */ +#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 1 (output) */ +#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 2 (input) */ +#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ + /* end-point 0 */ +#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ + /* reg. end-point 0 */ +#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ +#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ + +#if LANGUAGE == C +#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCR))) +#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCAR))) +#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCOMP))) +#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCIMP))) +#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS0))) +#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 1 (output) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS1))) +#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 2 (input) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS2))) +#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ + /* end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCD0))) +#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCWC))) +#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCDR))) +#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCSR))) +#endif /* LANGUAGE == C */ + +#define UDCCR_UDD 0x00000001 /* UDC Disable */ +#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ +#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ + /* (disable) */ +#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ + /* (disable) */ +#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ + /* (disable) */ +#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ + /* (disable) */ +#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ + +#define UDCAR_ADD Fld (7, 0) /* function ADDress */ + +#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) + +#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCIMP_INMAXP)) + +#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ +#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ +#define UDCCS0_SST 0x00000004 /* Sent STall */ +#define UDCCS0_FST 0x00000008 /* Force STall */ +#define UDCCS0_DE 0x00000010 /* Data End */ +#define UDCCS0_SE 0x00000020 /* Setup End (read) */ +#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ + /* (write) */ +#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ + +#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ + /* Service request (read) */ +#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ +#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ +#define UDCCS1_SST 0x00000008 /* Sent STall */ +#define UDCCS1_FST 0x00000010 /* Force STall */ +#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ + +#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ + /* Service request (read) */ +#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ +#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ +#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ +#define UDCCS2_SST 0x00000010 /* Sent STall */ +#define UDCCS2_FST 0x00000020 /* Force STall */ + +#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCWC_WC Fld (4, 0) /* Write Count */ + +#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ +#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ +#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ +#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ +#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ +#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ + + +/* + * Universal Asynchronous Receiver/Transmitter (UART) control registers + * + * Registers + * Ser1UTCR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser1UTCR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser1UTCR2 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser1UTCR3 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser1UTDR Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser1UTSR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser1UTSR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Ser2UTCR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser2UTCR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser2UTCR2 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser2UTCR3 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser2UTCR4 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 4 + * (read/write). + * Ser2UTDR Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser2UTSR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser2UTSR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Ser3UTCR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser3UTCR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser3UTCR2 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser3UTCR3 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser3UTDR Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser3UTSR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser3UTSR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fua, Tua Frequency, period of the UART communication. + */ + +#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ + (0x80010000 + ((Nb) - 1)*0x00020000) +#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ + (0x80010004 + ((Nb) - 1)*0x00020000) +#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ + (0x80010008 + ((Nb) - 1)*0x00020000) +#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ + (0x8001000C + ((Nb) - 1)*0x00020000) +#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ + (0x80010010 + ((Nb) - 1)*0x00020000) +#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ + (0x80010014 + ((Nb) - 1)*0x00020000) +#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ + (0x8001001C + ((Nb) - 1)*0x00020000) +#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ + (0x80010020 + ((Nb) - 1)*0x00020000) + +#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ +#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ +#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ +#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ +#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ +#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ +#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ + +#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ +#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ +#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ +#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ +#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ +#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ +#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ +#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ + +#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ +#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ +#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ +#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ +#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ +#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ +#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ + +#if LANGUAGE == C + +#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR0))) +#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR1))) +#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR2))) +#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR3))) +#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser1UTDR))) +#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1UTSR0))) +#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1UTSR1))) + +#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR0))) +#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR1))) +#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR2))) +#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR3))) +#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR4))) +#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser2UTDR))) +#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2UTSR0))) +#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2UTSR1))) + +#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR0))) +#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR1))) +#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR2))) +#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR3))) +#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser3UTDR))) +#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser3UTSR0))) +#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser3UTSR1))) + +#endif /* LANGUAGE == C */ + +#define UTCR0_PE 0x00000001 /* Parity Enable */ +#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ +#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ +#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ +#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ +#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ +#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ +#define UTCR0_DSS 0x00000008 /* Data Size Select */ +#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ +#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ +#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ + /* (ser. port 1: GPIO [18], */ + /* ser. port 3: GPIO [20]) */ +#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ +#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ +#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ +#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ +#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ +#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ + (UTCR0_1StpBit + UTCR0_8BitData) + +#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ +#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ + /* fua = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tua = 16*(BRD [11:0] + 1)*Txtl */ +#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) +#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Floor (Div/16)) */ + /* Tua = 16*Floor (Div/16)*Txtl */ +#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) +#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Ceil (Div/16)) */ + /* Tua = 16*Ceil (Div/16)*Txtl */ + +#define UTCR3_RXE 0x00000001 /* Receive Enable */ +#define UTCR3_TXE 0x00000002 /* Transmit Enable */ +#define UTCR3_BRK 0x00000004 /* BReaK mode */ +#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Interrupt Enable */ +#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ +#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ + /* TIE, LBM can be set or cleared) */ \ + (UTCR3_RXE + UTCR3_TXE) + +#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ + /* (HP-SIR) modulation Enable */ +#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ +#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ +#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ +#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ +#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ + +#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ +#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ +#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Service request (read) */ +#define UTSR0_RID 0x00000004 /* Receiver IDle */ +#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ +#define UTSR0_REB 0x00000010 /* Receive End of Break */ +#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ + +#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ +#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ +#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ +#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ +#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ +#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ + + +/* + * Synchronous Data Link Controller (SDLC) control registers + * + * Registers + * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 0 (read/write). + * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 1 (read/write). + * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 2 (read/write). + * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 3 (read/write). + * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 4 (read/write). + * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) + * Data Register (read/write). + * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 0 (read/write). + * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 1 (read/write). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fsd, Tsd Frequency, period of the SDLC communication. + */ + +#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ +#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */ +#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ +#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ +#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ +#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ +#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ +#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ + +#if LANGUAGE == C +#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR0))) +#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR1))) +#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR2))) +#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR3))) +#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR4))) +#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser1SDDR))) +#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1SDSR0))) +#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1SDSR1))) +#endif /* LANGUAGE == C */ + +#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ +#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ +#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ +#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ +#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ +#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ +#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ +#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ +#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ +#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ +#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ +#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ + /* (GPIO [16]) */ +#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ +#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ +#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ +#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ +#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ +#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ +#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ + +#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ + /* (GPIO [17]) */ +#define SDCR1_TXE 0x00000002 /* Transmit Enable */ +#define SDCR1_RXE 0x00000004 /* Receive Enable */ +#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Interrupt Enable */ +#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define SDCR1_AME 0x00000020 /* Address Match Enable */ +#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ +#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ +#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ +#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ + +#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ + +#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ +#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ + /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ +#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) +#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Floor (Div/16)) */ + /* Tsd = 16*Floor (Div/16)*Txtl */ +#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) +#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Ceil (Div/16)) */ + /* Tsd = 16*Ceil (Div/16)*Txtl */ + +#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ +#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define SDSR0_RAB 0x00000004 /* Receive ABort */ +#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Service request (read) */ + +#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ +#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ +#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ +#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ +#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ +#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ + + +/* + * High-Speed Serial to Parallel controller (HSSP) control registers + * + * Registers + * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 0 (read/write). + * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 1 (read/write). + * Ser2HSDR Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Data Register (read/write). + * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 0 (read/write). + * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 1 (read). + * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 2 (read/write). + * [The HSCR2 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + */ + +#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ +#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ +#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ +#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ +#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ +#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ + +#if LANGUAGE == C +#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR0))) +#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR1))) +#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser2HSDR))) +#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2HSSR0))) +#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2HSSR1))) +#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR2))) +#endif /* LANGUAGE == C */ + +#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ +#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ +#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ +#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ +#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ +#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ +#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ +#define HSCR0_TXE 0x00000008 /* Transmit Enable */ +#define HSCR0_RXE 0x00000010 /* Receive Enable */ +#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ + /* more Interrupt Enable */ +#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define HSCR0_AME 0x00000080 /* Address Match Enable */ + +#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ + +#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ +#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define HSSR0_RAB 0x00000004 /* Receive ABort */ +#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ + /* more Service request (read) */ +#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ + +#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ +#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ +#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ +#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ +#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ + +#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ +#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ + /* (inverted) */ +#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ + /* (non-inverted) */ +#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ +#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ + /* (inverted) */ +#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ + /* (non-inverted) */ + + +/* + * Multi-media Communications Port (MCP) control registers + * + * Registers + * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 0 (read/write). + * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 0 (audio, read/write). + * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 1 (telecom, read/write). + * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 2 (CODEC registers, read/write). + * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) + * Status Register (read/write). + * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 1 (read/write). + * [The MCCR1 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * + * Clocks + * fmc, Tmc Frequency, period of the MCP communication (10 MHz, + * 12 MHz, or GPIO [21]). + * faud, Taud Frequency, period of the audio sampling. + * ftcm, Ttcm Frequency, period of the telecom sampling. + */ + +#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ +#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ + /* (audio) */ +#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ + /* (telecom) */ +#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ + /* (CODEC reg.) */ +#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ +#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ + +#if LANGUAGE == C +#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser4MCCR0))) +#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ + /* (audio) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR0))) +#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ + /* (telecom) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR1))) +#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ + /* (CODEC reg.) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR2))) +#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4MCSR))) +#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser4MCCR1))) +#endif /* LANGUAGE == C */ + +#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ + /* [6..127] */ + /* faud = fmc/(32*ASD) */ + /* Taud = 32*ASD*Tmc */ +#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ + /* [192..4064] */ \ + ((Div)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Floor (Div/32)) */ + /* Taud = 32*Floor (Div/32)*Tmc */ +#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ + (((Div) + 31)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Ceil (Div/32)) */ + /* Taud = 32*Ceil (Div/32)*Tmc */ +#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ + /* Divisor/32 [16..127] */ + /* ftcm = fmc/(32*TSD) */ + /* Ttcm = 32*TSD*Tmc */ +#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ + /* [512..4064] */ \ + ((Div)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Floor (Div/32)) */ + /* Ttcm = 32*Floor (Div/32)*Tmc */ +#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ + (((Div) + 31)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Ceil (Div/32)) */ + /* Ttcm = 32*Ceil (Div/32)*Tmc */ +#define MCCR0_MCE 0x00010000 /* MCP Enable */ +#define MCCR0_ECS 0x00020000 /* External Clock Select */ +#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ +#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ +#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ + /* sampling/storing Mode */ +#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ +#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ +#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ + /* or less interrupt Enable */ +#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ + /* or more interrupt Enable */ +#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ + /* or less interrupt Enable */ +#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ + /* more interrupt Enable */ +#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ +#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ +#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ + (((Div) - 1) << FShft (MCCR0_ECP)) + +#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ + /* FIFOs */ + +#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ + /* FIFOs */ + + /* receive/transmit CODEC reg. */ + /* FIFOs: */ +#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ +#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ +#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ +#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ +#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ + +#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ + /* or less Service request (read) */ +#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ + /* more Service request (read) */ +#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ + /* or less Service request (read) */ +#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ + /* or more Service request (read) */ +#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ +#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ +#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ +#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ +#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ + /* (read) */ +#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ + /* (read) */ +#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ + /* (read) */ +#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ + /* (read) */ +#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ + /* (read) */ +#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ + /* (read) */ +#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ +#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ + +#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ +#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ + /* (11.981 MHz) */ +#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ + /* (9.585 MHz) */ + + +/* + * Synchronous Serial Port (SSP) control registers + * + * Registers + * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 0 (read/write). + * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 1 (read/write). + * [Bits SPO and SP are only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data + * Register (read/write). + * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status + * Register (read/write). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fss, Tss Frequency, period of the SSP communication. + */ + +#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ +#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ +#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ +#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ + +#if LANGUAGE == C +#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser4SSCR0))) +#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser4SSCR1))) +#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4SSDR))) +#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4SSSR))) +#endif /* LANGUAGE == C */ + +#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ +#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ + (((Size) - 1) << FShft (SSCR0_DSS)) +#define SSCR0_FRF Fld (2, 4) /* FRame Format */ +#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ + /* Interface (SPI) format */ \ + (0 << FShft (SSCR0_FRF)) +#define SSCR0_TI /* Texas Instruments Synchronous */ \ + /* Serial format */ \ + (1 << FShft (SSCR0_FRF)) +#define SSCR0_National /* National Microwire format */ \ + (2 << FShft (SSCR0_FRF)) +#define SSCR0_SSE 0x00000080 /* SSP Enable */ +#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ + /* fss = fxtl/(2*(SCR + 1)) */ + /* Tss = 2*(SCR + 1)*Txtl */ +#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ + (((Div) - 2)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Floor (Div/2)) */ + /* Tss = 2*Floor (Div/2)*Txtl */ +#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ + (((Div) - 1)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Ceil (Div/2)) */ + /* Tss = 2*Ceil (Div/2)*Txtl */ + +#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ + /* Interrupt Enable */ +#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ +#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ +#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ +#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ +#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ +#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ + /* after frame (SFRM, 1st edge) */ +#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ + /* after frame (SFRM, 1st edge) */ +#define SSCR1_ECS 0x00000020 /* External Clock Select */ +#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ +#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ + +#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ + +#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ +#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ +#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ + /* Service request (read) */ +#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ + + +/* + * Operating System (OS) timer control registers + * + * Registers + * OSMR0 Operating System (OS) timer Match Register 0 + * (read/write). + * OSMR1 Operating System (OS) timer Match Register 1 + * (read/write). + * OSMR2 Operating System (OS) timer Match Register 2 + * (read/write). + * OSMR3 Operating System (OS) timer Match Register 3 + * (read/write). + * OSCR Operating System (OS) timer Counter Register + * (read/write). + * OSSR Operating System (OS) timer Status Register + * (read/write). + * OWER Operating System (OS) timer Watch-dog Enable Register + * (read/write). + * OIER Operating System (OS) timer Interrupt Enable Register + * (read/write). + */ + +#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ + (0x90000000 + (Nb)*4) +#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ +#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ +#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ +#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ +#define _OSCR 0x90000010 /* OS timer Counter Reg. */ +#define _OSSR 0x90000014 /* OS timer Status Reg. */ +#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ +#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ + +#if LANGUAGE == C +#define OSMR /* OS timer Match Reg. [0..3] */ \ + ((volatile Word *) io_p2v (_OSMR (0))) +#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ +#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ +#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ +#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ +#define OSCR /* OS timer Counter Reg. */ \ + (*((volatile Word *) io_p2v (_OSCR))) +#define OSSR /* OS timer Status Reg. */ \ + (*((volatile Word *) io_p2v (_OSSR))) +#define OWER /* OS timer Watch-dog Enable Reg. */ \ + (*((volatile Word *) io_p2v (_OWER))) +#define OIER /* OS timer Interrupt Enable Reg. */ \ + (*((volatile Word *) io_p2v (_OIER))) +#endif /* LANGUAGE == C */ + +#define OSSR_M(Nb) /* Match detected [0..3] */ \ + (0x00000001 << (Nb)) +#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ +#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ +#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ +#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ + +#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ + /* (set only) */ + +#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ + (0x00000001 << (Nb)) +#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ +#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ +#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ +#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ + + +/* + * Real-Time Clock (RTC) control registers + * + * Registers + * RTAR Real-Time Clock (RTC) Alarm Register (read/write). + * RCNR Real-Time Clock (RTC) CouNt Register (read/write). + * RTTR Real-Time Clock (RTC) Trim Register (read/write). + * RTSR Real-Time Clock (RTC) Status Register (read/write). + * + * Clocks + * frtx, Trtx Frequency, period of the real-time clock crystal + * (32.768 kHz nominal). + * frtc, Trtc Frequency, period of the real-time clock counter + * (1 Hz nominal). + */ + +#define _RTAR 0x90010000 /* RTC Alarm Reg. */ +#define _RCNR 0x90010004 /* RTC CouNt Reg. */ +#define _RTTR 0x90010008 /* RTC Trim Reg. */ +#define _RTSR 0x90010010 /* RTC Status Reg. */ + +#if LANGUAGE == C +#define RTAR /* RTC Alarm Reg. */ \ + (*((volatile Word *) io_p2v (_RTAR))) +#define RCNR /* RTC CouNt Reg. */ \ + (*((volatile Word *) io_p2v (_RCNR))) +#define RTTR /* RTC Trim Reg. */ \ + (*((volatile Word *) io_p2v (_RTTR))) +#define RTSR /* RTC Status Reg. */ \ + (*((volatile Word *) io_p2v (_RTSR))) +#endif /* LANGUAGE == C */ + +#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ +#define RTTR_D Fld (10, 16) /* trim Delete count */ + /* frtc = (1023*(C + 1) - D)*frtx/ */ + /* (1023*(C + 1)^2) */ + /* Trtc = (1023*(C + 1)^2)*Trtx/ */ + /* (1023*(C + 1) - D) */ + +#define RTSR_AL 0x00000001 /* ALarm detected */ +#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ +#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ +#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ + + +/* + * Power Manager (PM) control registers + * + * Registers + * PMCR Power Manager (PM) Control Register (read/write). + * PSSR Power Manager (PM) Sleep Status Register (read/write). + * PSPR Power Manager (PM) Scratch-Pad Register (read/write). + * PWER Power Manager (PM) Wake-up Enable Register + * (read/write). + * PCFR Power Manager (PM) general ConFiguration Register + * (read/write). + * PPCR Power Manager (PM) Phase-Locked Loop (PLL) + * Configuration Register (read/write). + * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) + * Sleep state Register (read/write, see GPIO pins). + * POSR Power Manager (PM) Oscillator Status Register (read). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + */ + +#define _PMCR 0x90020000 /* PM Control Reg. */ +#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ +#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ +#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ +#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ +#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ +#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ +#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ + +#if LANGUAGE == C +#define PMCR /* PM Control Reg. */ \ + (*((volatile Word *) io_p2v (_PMCR))) +#define PSSR /* PM Sleep Status Reg. */ \ + (*((volatile Word *) io_p2v (_PSSR))) +#define PSPR /* PM Scratch-Pad Reg. */ \ + (*((volatile Word *) io_p2v (_PSPR))) +#define PWER /* PM Wake-up Enable Reg. */ \ + (*((volatile Word *) io_p2v (_PWER))) +#define PCFR /* PM general ConFiguration Reg. */ \ + (*((volatile Word *) io_p2v (_PCFR))) +#define PPCR /* PM PLL Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_PPCR))) +#define PGSR /* PM GPIO Sleep state Reg. */ \ + (*((volatile Word *) io_p2v (_PGSR))) +#define POSR /* PM Oscillator Status Reg. */ \ + (*((volatile Word *) io_p2v (_POSR))) +#endif /* LANGUAGE == C */ + +#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ + +#define PSSR_SS 0x00000001 /* Software Sleep */ +#define PSSR_BFS 0x00000002 /* Battery Fault Status */ + /* (BATT_FAULT) */ +#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ +#define PSSR_DH 0x00000008 /* DRAM control Hold */ +#define PSSR_PH 0x00000010 /* Peripheral control Hold */ + +#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ +#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ +#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ +#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ +#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ +#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ +#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ +#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ +#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ +#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ +#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ +#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ + +#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ +#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ +#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ +#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ +#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ +#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ +#define PCFR_FS 0x00000004 /* Float Static memory pins */ +#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ +#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ +#define PCFR_FO 0x00000008 /* Force RTC oscillator */ + /* (32.768 kHz) enable On */ + +#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ +#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ + (0x00 << FShft (PPCR_CCF)) +#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ + (0x01 << FShft (PPCR_CCF)) +#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ + (0x02 << FShft (PPCR_CCF)) +#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ + (0x03 << FShft (PPCR_CCF)) +#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ + (0x04 << FShft (PPCR_CCF)) +#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ + (0x05 << FShft (PPCR_CCF)) +#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ + (0x06 << FShft (PPCR_CCF)) +#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ + (0x07 << FShft (PPCR_CCF)) +#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ + (0x08 << FShft (PPCR_CCF)) +#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ + (0x09 << FShft (PPCR_CCF)) +#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ + (0x0A << FShft (PPCR_CCF)) +#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ + (0x0B << FShft (PPCR_CCF)) +#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ + (0x0C << FShft (PPCR_CCF)) +#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ + (0x0D << FShft (PPCR_CCF)) +#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ + (0x0E << FShft (PPCR_CCF)) +#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ + (0x0F << FShft (PPCR_CCF)) + /* 3.6864 MHz crystal (fxtl): */ +#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ +#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ +#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ +#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ +#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ +#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ +#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ +#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ +#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ +#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ +#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ +#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ +#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ +#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ +#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ +#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ + /* 3.5795 MHz crystal (fxtl): */ +#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ +#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ +#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ +#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ +#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ +#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ +#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ +#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ +#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ +#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ +#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ +#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ +#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ +#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ +#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ +#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ + +#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ + + +/* + * Reset Controller (RC) control registers + * + * Registers + * RSRR Reset Controller (RC) Software Reset Register + * (read/write). + * RCSR Reset Controller (RC) Status Register (read/write). + */ + +#define _RSRR 0x90030000 /* RC Software Reset Reg. */ +#define _RCSR 0x90030004 /* RC Status Reg. */ + +#if LANGUAGE == C +#define RSRR /* RC Software Reset Reg. */ \ + (*((volatile Word *) io_p2v (_RSRR))) +#define RCSR /* RC Status Reg. */ \ + (*((volatile Word *) io_p2v (_RCSR))) +#endif /* LANGUAGE == C */ + +#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ + +#define RCSR_HWR 0x00000001 /* HardWare Reset */ +#define RCSR_SWR 0x00000002 /* SoftWare Reset */ +#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ +#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ + + +/* + * Test unit control registers + * + * Registers + * TUCR Test Unit Control Register (read/write). + */ + +#define _TUCR 0x90030008 /* Test Unit Control Reg. */ + +#if LANGUAGE == C +#define TUCR /* Test Unit Control Reg. */ \ + (*((volatile Word *) io_p2v (_TUCR))) +#endif /* LANGUAGE == C */ + +#define TUCR_TIC 0x00000040 /* TIC mode */ +#define TUCR_TTST 0x00000080 /* Trim TeST mode */ +#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ + /* Check */ +#define TUCR_PMD 0x00000200 /* Power Management Disable */ +#define TUCR_MR 0x00000400 /* Memory Request mode */ +#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ +#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ + /* grant (MBGNT) on GPIO [22:21] */ +#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ +#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ +#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ +#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ +#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ +#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ +#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ + (0 << FShft (TUCR_TSEL)) +#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ + (1 << FShft (TUCR_TSEL)) +#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ + (2 << FShft (TUCR_TSEL)) +#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ + (3 << FShft (TUCR_TSEL)) +#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ + /* Clocks on GPIO [26:27] */ \ + (4 << FShft (TUCR_TSEL)) +#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ + /* (Alternative) */ \ + (5 << FShft (TUCR_TSEL)) +#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ + (6 << FShft (TUCR_TSEL)) +#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ + (7 << FShft (TUCR_TSEL)) + + +/* + * General-Purpose Input/Output (GPIO) control registers + * + * Registers + * GPLR General-Purpose Input/Output (GPIO) Pin Level + * Register (read). + * GPDR General-Purpose Input/Output (GPIO) Pin Direction + * Register (read/write). + * GPSR General-Purpose Input/Output (GPIO) Pin output Set + * Register (write). + * GPCR General-Purpose Input/Output (GPIO) Pin output Clear + * Register (write). + * GRER General-Purpose Input/Output (GPIO) Rising-Edge + * detect Register (read/write). + * GFER General-Purpose Input/Output (GPIO) Falling-Edge + * detect Register (read/write). + * GEDR General-Purpose Input/Output (GPIO) Edge Detect + * status Register (read/write). + * GAFR General-Purpose Input/Output (GPIO) Alternate + * Function Register (read/write). + * + * Clock + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + */ + +#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ +#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ +#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ +#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ +#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ +#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ +#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ +#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ + +#if LANGUAGE == C +#define GPLR /* GPIO Pin Level Reg. */ \ + (*((volatile Word *) io_p2v (_GPLR))) +#define GPDR /* GPIO Pin Direction Reg. */ \ + (*((volatile Word *) io_p2v (_GPDR))) +#define GPSR /* GPIO Pin output Set Reg. */ \ + (*((volatile Word *) io_p2v (_GPSR))) +#define GPCR /* GPIO Pin output Clear Reg. */ \ + (*((volatile Word *) io_p2v (_GPCR))) +#define GRER /* GPIO Rising-Edge detect Reg. */ \ + (*((volatile Word *) io_p2v (_GRER))) +#define GFER /* GPIO Falling-Edge detect Reg. */ \ + (*((volatile Word *) io_p2v (_GFER))) +#define GEDR /* GPIO Edge Detect status Reg. */ \ + (*((volatile Word *) io_p2v (_GEDR))) +#define GAFR /* GPIO Alternate Function Reg. */ \ + (*((volatile Word *) io_p2v (_GAFR))) +#endif /* LANGUAGE == C */ + +#define GPIO_MIN (0) +#define GPIO_MAX (27) + +#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ + (0x00000001 << (Nb)) +#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ +#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ +#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ +#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ +#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ +#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ +#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ +#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ +#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ +#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ +#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ +#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ +#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ +#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ +#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ +#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ +#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ +#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ +#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ +#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ +#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ +#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ +#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ +#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ +#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ +#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ +#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ +#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ + +#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ + GPIO_GPIO ((Nb) - 6) +#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ +#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ +#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ +#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ +#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ +#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ +#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ +#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ + /* ser. port 4: */ +#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ +#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ +#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ +#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ + /* ser. port 1: */ +#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ +#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ +#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ +#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ +#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ + /* ser. port 4: */ +#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ + /* ser. port 3: */ +#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ + /* ser. port 4: */ +#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ + /* test controller: */ +#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ +#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ +#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ +#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ +#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ +#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ +#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ +#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ + +#define GPDR_In 0 /* Input */ +#define GPDR_Out 1 /* Output */ + + +/* + * Interrupt Controller (IC) control registers + * + * Registers + * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) + * Pending register (read). + * ICMR Interrupt Controller (IC) Mask Register (read/write). + * ICLR Interrupt Controller (IC) Level Register (read/write). + * ICCR Interrupt Controller (IC) Control Register + * (read/write). + * [The ICCR register is only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * ICFP Interrupt Controller (IC) Fast Interrupt reQuest + * (FIQ) Pending register (read). + * ICPR Interrupt Controller (IC) Pending Register (read). + * [The ICPR register is active low (inverted) in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it is active high (non-inverted) in + * versions 2.0 (rev. = 8) and higher.] + */ + +#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ +#define _ICMR 0x90050004 /* IC Mask Reg. */ +#define _ICLR 0x90050008 /* IC Level Reg. */ +#define _ICCR 0x9005000C /* IC Control Reg. */ +#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ +#define _ICPR 0x90050020 /* IC Pending Reg. */ + +#if LANGUAGE == C +#define ICIP /* IC IRQ Pending reg. */ \ + (*((volatile Word *) io_p2v (_ICIP))) +#define ICMR /* IC Mask Reg. */ \ + (*((volatile Word *) io_p2v (_ICMR))) +#define ICLR /* IC Level Reg. */ \ + (*((volatile Word *) io_p2v (_ICLR))) +#define ICCR /* IC Control Reg. */ \ + (*((volatile Word *) io_p2v (_ICCR))) +#define ICFP /* IC FIQ Pending reg. */ \ + (*((volatile Word *) io_p2v (_ICFP))) +#define ICPR /* IC Pending Reg. */ \ + (*((volatile Word *) io_p2v (_ICPR))) +#endif /* LANGUAGE == C */ + +#define IC_GPIO(Nb) /* GPIO [0..10] */ \ + (0x00000001 << (Nb)) +#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ +#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ +#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ +#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ +#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ +#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ +#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ +#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ +#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ +#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ +#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ +#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ +#define IC_LCD 0x00001000 /* LCD controller */ +#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ +#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ +#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ +#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ +#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ +#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ +#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ +#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ + (0x00100000 << (Nb)) +#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ +#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ +#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ +#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ +#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ +#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ +#define IC_OST(Nb) /* OS Timer match [0..3] */ \ + (0x04000000 << (Nb)) +#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ +#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ +#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ +#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ +#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ +#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ + +#define ICLR_IRQ 0 /* Interrupt ReQuest */ +#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ + +#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ + /* Mask */ +#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ + /* (ICMR ignored) */ +#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ + /* enable (ICMR used) */ + + +/* + * Peripheral Pin Controller (PPC) control registers + * + * Registers + * PPDR Peripheral Pin Controller (PPC) Pin Direction + * Register (read/write). + * PPSR Peripheral Pin Controller (PPC) Pin State Register + * (read/write). + * PPAR Peripheral Pin Controller (PPC) Pin Assignment + * Register (read/write). + * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin + * Direction Register (read/write). + * PPFR Peripheral Pin Controller (PPC) Pin Flag Register + * (read). + */ + +#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ +#define _PPSR 0x90060004 /* PPC Pin State Reg. */ +#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ +#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ + /* Reg. */ +#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ + +#if LANGUAGE == C +#define PPDR /* PPC Pin Direction Reg. */ \ + (*((volatile Word *) io_p2v (_PPDR))) +#define PPSR /* PPC Pin State Reg. */ \ + (*((volatile Word *) io_p2v (_PPSR))) +#define PPAR /* PPC Pin Assignment Reg. */ \ + (*((volatile Word *) io_p2v (_PPAR))) +#define PSDR /* PPC Sleep-mode pin Direction */ \ + /* Reg. */ \ + (*((volatile Word *) io_p2v (_PSDR))) +#define PPFR /* PPC Pin Flag Reg. */ \ + (*((volatile Word *) io_p2v (_PPFR))) +#endif /* LANGUAGE == C */ + +#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ + (0x00000001 << (Nb)) +#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ +#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ +#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ +#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ +#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ +#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ +#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ +#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ +#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ +#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ +#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ +#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ + /* ser. port 1: */ +#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ +#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ + /* ser. port 2: */ +#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ +#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ + /* ser. port 3: */ +#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ +#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ + /* ser. port 4: */ +#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ +#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ +#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ +#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ + +#define PPDR_In 0 /* Input */ +#define PPDR_Out 1 /* Output */ + + /* ser. port 1: */ +#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ +#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ +#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ + /* ser. port 4: */ +#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ +#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ + /* & SFRM_C */ +#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ + +#define PSDR_OutL 0 /* Output Low in sleep mode */ +#define PSDR_Flt 1 /* Floating (input) in sleep mode */ + +#define PPFR_LCD 0x00000001 /* LCD controller */ +#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ +#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ +#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ +#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ +#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ +#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ +#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ +#define PPFR_PerEn 0 /* Peripheral Enabled */ +#define PPFR_PPCEn 1 /* PPC Enabled */ + + +/* + * Dynamic Random-Access Memory (DRAM) control registers + * + * Registers + * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) + * CoNFiGuration register (read/write). + * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 0 + * (read/write). + * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 1 + * (read/write). + * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 2 + * (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fcas, Tcas Frequency, period of the DRAM CAS shift registers. + */ + + /* Memory system: */ +#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ +#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ + (0xA0000004 + (Nb)*4) +#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ +#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ +#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ + +#if LANGUAGE == C + /* Memory system: */ +#define MDCNFG /* DRAM CoNFiGuration reg. */ \ + (*((volatile Word *) io_p2v (_MDCNFG))) +#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ + ((volatile Word *) io_p2v (_MDCAS (0))) +#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ +#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ +#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ +#endif /* LANGUAGE == C */ + +/* SA1100 MDCNFG values */ +#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ + (0x00000001 << (Nb)) +#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ +#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ +#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ +#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ +#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ +#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ + (((Add) - 9) << FShft (MDCNFG_DRAC)) +#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ + /* (fcas = fcpu/2) */ +#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ +#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) +#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) +#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ +#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) +#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) +#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ +#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ + ((Tcpu) << FShft (MDCNFG_TDL)) +#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ + /* [Tmem] */ +#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ + /* [0..262136 Tcpu] */ \ + ((Tcpu)/8 << FShft (MDCNFG_DRI)) + +/* SA1110 MDCNFG values */ +#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ +#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ + /* bank 0/1 */ +#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ +#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ + /* deassertion 0/1 */ +#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ +#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ +#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ + /* bank 0/1 */ +#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ +#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ + /* deassertion 0/1 */ +#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ + + +/* + * Static memory control registers + * + * Registers + * MSC0 Memory system: Static memory Control register 0 + * (read/write). + * MSC1 Memory system: Static memory Control register 1 + * (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + */ + + /* Memory system: */ +#define _MSC(Nb) /* Static memory Control reg. */ \ + /* [0..1] */ \ + (0xA0000010 + (Nb)*4) +#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ +#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ + +#if LANGUAGE == C + /* Memory system: */ +#define MSC /* Static memory Control reg. */ \ + /* [0..1] */ \ + ((volatile Word *) io_p2v (_MSC (0))) +#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ +#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ +#endif /* LANGUAGE == C */ + +#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ + Fld (16, ((Nb) Modulo 2)*16) +#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ +#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ +#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ +#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ + +#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ +#define MSC_NonBrst /* Non-Burst static memory */ \ + (0 << FShft (MSC_RT)) +#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ + (1 << FShft (MSC_RT)) +#define MSC_Brst4 /* Burst-of-4 static memory */ \ + (2 << FShft (MSC_RT)) +#define MSC_Brst8 /* Burst-of-8 static memory */ \ + (3 << FShft (MSC_RT)) +#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ +#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ +#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ +#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ + /* First access - 1(.5) [Tmem] */ +#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ + /* static memory) [3..65 Tcpu] */ \ + (((Tcpu) - 3)/2 << FShft (MSC_RDF)) +#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MSC_RDF)) +#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ + /* static memory) [2..64 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MSC_RDF)) +#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MSC_RDF)) +#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ + /* Next access - 1 [Tmem] */ +#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ + /* static memory) [2..64 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MSC_RDN)) +#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MSC_RDN)) +#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ + /* static memory) [2..64 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MSC_RDN)) +#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MSC_RDN)) +#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ + /* time/2 [Tmem] */ +#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ + ((Tcpu)/4 << FShft (MSC_RRR)) +#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ + (((Tcpu) + 3)/4 << FShft (MSC_RRR)) + + +/* + * Personal Computer Memory Card International Association (PCMCIA) control + * register + * + * Register + * MECR Memory system: Expansion memory bus (PCMCIA) + * Configuration Register (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). + */ + + /* Memory system: */ +#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ + /* Configuration Reg. */ + +#if LANGUAGE == C + /* Memory system: */ +#define MECR /* Expansion memory bus (PCMCIA) */ \ + /* Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_MECR))) +#endif /* LANGUAGE == C */ + +#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ + Fld (15, (Nb)*16) +#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ +#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ + +#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ +#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MECR_BSIO)) +#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MECR_BSIO)) +#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ + /* [Tmem] */ +#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MECR_BSA)) +#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MECR_BSA)) +#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ +#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MECR_BSM)) +#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MECR_BSM)) + +/* + * On SA1110 only + */ + +#define _MDREFR 0xA000001C + +#if LANGUAGE == C + /* Memory system: */ +#define MDREFR \ + (*((volatile Word *) io_p2v (_MDREFR))) + +#endif /* LANGUAGE == C */ + +#define MDREFR_TRASR Fld (4, 0) +#define MDREFR_DRI Fld (12, 4) +#define MDREFR_E0PIN (1 << 16) +#define MDREFR_K0RUN (1 << 17) +#define MDREFR_K0DB2 (1 << 18) +#define MDREFR_E1PIN (1 << 20) +#define MDREFR_K1RUN (1 << 21) +#define MDREFR_K1DB2 (1 << 22) +#define MDREFR_K2RUN (1 << 25) +#define MDREFR_K2DB2 (1 << 26) +#define MDREFR_EAPD (1 << 28) +#define MDREFR_KAPD (1 << 29) +#define MDREFR_SLFRSH (1 << 31) + + +/* + * Direct Memory Access (DMA) control registers + * + * Registers + * DDAR0 Direct Memory Access (DMA) Device Address Register + * channel 0 (read/write). + * DCSR0 Direct Memory Access (DMA) Control and Status + * Register channel 0 (read/write). + * DBSA0 Direct Memory Access (DMA) Buffer Start address + * register A channel 0 (read/write). + * DBTA0 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 0 (read/write). + * DBSB0 Direct Memory Access (DMA) Buffer Start address + * register B channel 0 (read/write). + * DBTB0 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 0 (read/write). + * + * DDAR1 Direct Memory Access (DMA) Device Address Register + * channel 1 (read/write). + * DCSR1 Direct Memory Access (DMA) Control and Status + * Register channel 1 (read/write). + * DBSA1 Direct Memory Access (DMA) Buffer Start address + * register A channel 1 (read/write). + * DBTA1 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 1 (read/write). + * DBSB1 Direct Memory Access (DMA) Buffer Start address + * register B channel 1 (read/write). + * DBTB1 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 1 (read/write). + * + * DDAR2 Direct Memory Access (DMA) Device Address Register + * channel 2 (read/write). + * DCSR2 Direct Memory Access (DMA) Control and Status + * Register channel 2 (read/write). + * DBSA2 Direct Memory Access (DMA) Buffer Start address + * register A channel 2 (read/write). + * DBTA2 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 2 (read/write). + * DBSB2 Direct Memory Access (DMA) Buffer Start address + * register B channel 2 (read/write). + * DBTB2 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 2 (read/write). + * + * DDAR3 Direct Memory Access (DMA) Device Address Register + * channel 3 (read/write). + * DCSR3 Direct Memory Access (DMA) Control and Status + * Register channel 3 (read/write). + * DBSA3 Direct Memory Access (DMA) Buffer Start address + * register A channel 3 (read/write). + * DBTA3 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 3 (read/write). + * DBSB3 Direct Memory Access (DMA) Buffer Start address + * register B channel 3 (read/write). + * DBTB3 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 3 (read/write). + * + * DDAR4 Direct Memory Access (DMA) Device Address Register + * channel 4 (read/write). + * DCSR4 Direct Memory Access (DMA) Control and Status + * Register channel 4 (read/write). + * DBSA4 Direct Memory Access (DMA) Buffer Start address + * register A channel 4 (read/write). + * DBTA4 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 4 (read/write). + * DBSB4 Direct Memory Access (DMA) Buffer Start address + * register B channel 4 (read/write). + * DBTB4 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 4 (read/write). + * + * DDAR5 Direct Memory Access (DMA) Device Address Register + * channel 5 (read/write). + * DCSR5 Direct Memory Access (DMA) Control and Status + * Register channel 5 (read/write). + * DBSA5 Direct Memory Access (DMA) Buffer Start address + * register A channel 5 (read/write). + * DBTA5 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 5 (read/write). + * DBSB5 Direct Memory Access (DMA) Buffer Start address + * register B channel 5 (read/write). + * DBTB5 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 5 (read/write). + */ + +#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ + +#define _DDAR(Nb) /* DMA Device Address Reg. */ \ + /* channel [0..5] */ \ + (0xB0000000 + (Nb)*DMASp) +#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ + (0xB0000004 + (Nb)*DMASp) +#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ + (0xB0000008 + (Nb)*DMASp) +#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ + /* channel [0..5] (read) */ \ + (0xB000000C + (Nb)*DMASp) +#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ + /* channel [0..5] */ \ + (0xB0000010 + (Nb)*DMASp) +#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ + /* reg. A channel [0..5] */ \ + (0xB0000014 + (Nb)*DMASp) +#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ + /* channel [0..5] */ \ + (0xB0000018 + (Nb)*DMASp) +#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ + /* reg. B channel [0..5] */ \ + (0xB000001C + (Nb)*DMASp) + +#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ + /* channel 0 */ +#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ + /* channel 0 (write) */ +#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ + /* channel 0 (write) */ +#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ + /* channel 0 (read) */ +#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ + /* channel 0 */ +#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ + /* reg. A channel 0 */ +#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ + /* channel 0 */ +#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ + /* reg. B channel 0 */ + +#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ + /* channel 1 */ +#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ + /* channel 1 (write) */ +#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ + /* channel 1 (write) */ +#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ + /* channel 1 (read) */ +#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ + /* channel 1 */ +#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ + /* reg. A channel 1 */ +#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ + /* channel 1 */ +#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ + /* reg. B channel 1 */ + +#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ + /* channel 2 */ +#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ + /* channel 2 (write) */ +#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ + /* channel 2 (write) */ +#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ + /* channel 2 (read) */ +#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ + /* channel 2 */ +#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ + /* reg. A channel 2 */ +#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ + /* channel 2 */ +#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ + /* reg. B channel 2 */ + +#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ + /* channel 3 */ +#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ + /* channel 3 (write) */ +#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ + /* channel 3 (write) */ +#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ + /* channel 3 (read) */ +#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ + /* channel 3 */ +#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ + /* reg. A channel 3 */ +#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ + /* channel 3 */ +#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ + /* reg. B channel 3 */ + +#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ + /* channel 4 */ +#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ + /* channel 4 (write) */ +#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ + /* channel 4 (write) */ +#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ + /* channel 4 (read) */ +#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ + /* channel 4 */ +#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ + /* reg. A channel 4 */ +#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ + /* channel 4 */ +#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ + /* reg. B channel 4 */ + +#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ + /* channel 5 */ +#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ + /* channel 5 (write) */ +#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ + /* channel 5 (write) */ +#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ + /* channel 5 (read) */ +#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ + /* channel 5 */ +#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ + /* reg. A channel 5 */ +#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ + /* channel 5 */ +#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ + /* reg. B channel 5 */ + +#if LANGUAGE == C + +#define DDAR0 /* DMA Device Address Reg. */ \ + /* channel 0 */ \ + (*((volatile Word *) io_p2v (_DDAR0))) +#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR0))) +#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR0))) +#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ + /* channel 0 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR0))) +#define DBSA0 /* DMA Buffer Start address reg. A */ \ + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSA0))) +#define DBTA0 /* DMA Buffer Transfer count */ \ + /* reg. A channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTA0))) +#define DBSB0 /* DMA Buffer Start address reg. B */ \ + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSB0))) +#define DBTB0 /* DMA Buffer Transfer count */ \ + /* reg. B channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTB0))) + +#define DDAR1 /* DMA Device Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Word *) io_p2v (_DDAR1))) +#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR1))) +#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR1))) +#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ + /* channel 1 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR1))) +#define DBSA1 /* DMA Buffer Start address reg. A */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSA1))) +#define DBTA1 /* DMA Buffer Transfer count */ \ + /* reg. A channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTA1))) +#define DBSB1 /* DMA Buffer Start address reg. B */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSB1))) +#define DBTB1 /* DMA Buffer Transfer count */ \ + /* reg. B channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTB1))) + +#define DDAR2 /* DMA Device Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Word *) io_p2v (_DDAR2))) +#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR2))) +#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR2))) +#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ + /* channel 2 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR2))) +#define DBSA2 /* DMA Buffer Start address reg. A */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSA2))) +#define DBTA2 /* DMA Buffer Transfer count */ \ + /* reg. A channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTA2))) +#define DBSB2 /* DMA Buffer Start address reg. B */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSB2))) +#define DBTB2 /* DMA Buffer Transfer count */ \ + /* reg. B channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTB2))) + +#define DDAR3 /* DMA Device Address Reg. */ \ + /* channel 3 */ \ + (*((volatile Word *) io_p2v (_DDAR3))) +#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR3))) +#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR3))) +#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ + /* channel 3 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR3))) +#define DBSA3 /* DMA Buffer Start address reg. A */ \ + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSA3))) +#define DBTA3 /* DMA Buffer Transfer count */ \ + /* reg. A channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTA3))) +#define DBSB3 /* DMA Buffer Start address reg. B */ \ + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSB3))) +#define DBTB3 /* DMA Buffer Transfer count */ \ + /* reg. B channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTB3))) + +#define DDAR4 /* DMA Device Address Reg. */ \ + /* channel 4 */ \ + (*((volatile Word *) io_p2v (_DDAR4))) +#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR4))) +#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR4))) +#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ + /* channel 4 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR4))) +#define DBSA4 /* DMA Buffer Start address reg. A */ \ + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSA4))) +#define DBTA4 /* DMA Buffer Transfer count */ \ + /* reg. A channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTA4))) +#define DBSB4 /* DMA Buffer Start address reg. B */ \ + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSB4))) +#define DBTB4 /* DMA Buffer Transfer count */ \ + /* reg. B channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTB4))) + +#define DDAR5 /* DMA Device Address Reg. */ \ + /* channel 5 */ \ + (*((volatile Word *) io_p2v (_DDAR5))) +#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR5))) +#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR5))) +#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ + /* channel 5 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR5))) +#define DBSA5 /* DMA Buffer Start address reg. A */ \ + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSA5))) +#define DBTA5 /* DMA Buffer Transfer count */ \ + /* reg. A channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTA5))) +#define DBSB5 /* DMA Buffer Start address reg. B */ \ + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSB5))) +#define DBTB5 /* DMA Buffer Transfer count */ \ + /* reg. B channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTB5))) + +#endif /* LANGUAGE == C */ + +#define DDAR_RW 0x00000001 /* device data Read/Write */ +#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ + /* (memory -> device) */ +#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ + /* (device -> memory) */ +#define DDAR_E 0x00000002 /* big/little Endian device */ +#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ +#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ +#define DDAR_BS 0x00000004 /* device Burst Size */ +#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ +#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ +#define DDAR_DW 0x00000008 /* device Data Width */ +#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ +#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ +#define DDAR_DS Fld (4, 4) /* Device Select */ +#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ + (0x0 << FShft (DDAR_DS)) +#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ + (0x1 << FShft (DDAR_DS)) +#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ + (0x2 << FShft (DDAR_DS)) +#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ + (0x3 << FShft (DDAR_DS)) +#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ + (0x4 << FShft (DDAR_DS)) +#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ + (0x5 << FShft (DDAR_DS)) +#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ + (0x6 << FShft (DDAR_DS)) +#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ + (0x7 << FShft (DDAR_DS)) +#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ + (0x8 << FShft (DDAR_DS)) +#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ + (0x9 << FShft (DDAR_DS)) +#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ + /* (audio) */ \ + (0xA << FShft (DDAR_DS)) +#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ + /* (audio) */ \ + (0xB << FShft (DDAR_DS)) +#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ + /* (telecom) */ \ + (0xC << FShft (DDAR_DS)) +#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ + /* (telecom) */ \ + (0xD << FShft (DDAR_DS)) +#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ + (0xE << FShft (DDAR_DS)) +#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ + (0xF << FShft (DDAR_DS)) +#define DDAR_DA Fld (24, 8) /* Device Address */ +#define DDAR_DevAdd(Add) /* Device Address */ \ + ((Add) & 0xF0000000 | \ + ((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)) +#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) +#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) +#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) +#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) +#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) +#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) +#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) +#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) +#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) +#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) +#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) +#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) +#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) +#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) +#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ + /* (telecom) */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) +#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ + /* (telecom) */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) +#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) +#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) + +#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ +#define DCSR_ERROR 0x00000004 /* DMA ERROR */ +#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ +#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ +#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ +#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ +#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ +#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ +#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ + +#define DBT_TC Fld (13, 0) /* Transfer Count */ +#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ +#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ + + +/* + * Liquid Crystal Display (LCD) control registers + * + * Registers + * LCCR0 Liquid Crystal Display (LCD) Control Register 0 + * (read/write). + * [Bits LDM, BAM, and ERM are only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * LCSR Liquid Crystal Display (LCD) Status Register + * (read/write). + * [Bit LDD can be only read in versions 1.0 (rev. = 1) + * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be + * read and written (cleared) in versions 2.0 (rev. = 8) + * and higher.] + * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 1 (read/write). + * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 1 (read). + * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 2 (read/write). + * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 2 (read). + * LCCR1 Liquid Crystal Display (LCD) Control Register 1 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR2 Liquid Crystal Display (LCD) Control Register 2 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR3 Liquid Crystal Display (LCD) Control Register 3 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher. Bit PCP is only + * implemented in versions 2.0 (rev. = 8) and higher of + * the StrongARM SA-1100.] + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fpix, Tpix Frequency, period of the pixel clock. + * fln, Tln Frequency, period of the line clock. + * fac, Tac Frequency, period of the AC bias clock. + */ + +#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ +#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ + /* [byte] */ \ + (16*LCD_PEntrySp) +#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ + /* [byte] */ \ + (256*LCD_PEntrySp) +#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ + /* dummy-Palette Space [byte] */ \ + (16*LCD_PEntrySp) + +#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ +#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ +#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ +#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ +#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ +#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ + (0 << FShft (LCD_PBS)) +#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ + (1 << FShft (LCD_PBS)) +#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ + (2 << FShft (LCD_PBS)) + +#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ +#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ +#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ +#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ +#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ +#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ +#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ +#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ +#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ +#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ +#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ +#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ +#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ +#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ +#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ +#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ + /* (Alternative) */ + +#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ +#define _LCSR 0xB0100004 /* LCD Status Reg. */ +#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ + /* channel 1 */ +#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ + /* channel 1 */ +#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ + /* channel 2 */ +#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ + /* channel 2 */ +#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ +#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ +#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ + +#if LANGUAGE == C +#define LCCR0 /* LCD Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_LCCR0))) +#define LCSR /* LCD Status Reg. */ \ + (*((volatile Word *) io_p2v (_LCSR))) +#define DBAR1 /* LCD DMA Base Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBAR1))) +#define DCAR1 /* LCD DMA Current Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DCAR1))) +#define DBAR2 /* LCD DMA Base Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBAR2))) +#define DCAR2 /* LCD DMA Current Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DCAR2))) +#define LCCR1 /* LCD Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_LCCR1))) +#define LCCR2 /* LCD Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_LCCR2))) +#define LCCR3 /* LCD Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_LCCR3))) +#endif /* LANGUAGE == C */ + +#define LCCR0_LEN 0x00000001 /* LCD ENable */ +#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ +#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ +#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ +#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ + /* Select */ +#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ +#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ +#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ + /* interrupt Mask (disable) */ +#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ + /* interrupt Mask (disable) */ +#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ + /* IUU, OOL, OUL, OOU, and OUU) */ + /* interrupt Mask (disable) */ +#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ +#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ +#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ +#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ +#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ +#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ +#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ + /* display mode) */ +#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ + /* [Tmem] */ +#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ + /* [0..510 Tcpu] */ \ + ((Tcpu)/2 << FShft (LCCR0_PDD)) + +#define LCSR_LDD 0x00000001 /* LCD Disable Done */ +#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ +#define LCSR_BER 0x00000004 /* Bus ERror */ +#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ +#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ + /* panel */ +#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ + /* panel */ +#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ + /* panel */ +#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ + /* panel */ +#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ + /* panel */ +#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ + /* panel */ +#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ + /* panel */ +#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ + /* panel */ + +#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ + (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ + /* pulse Width - 2 [Tpix] (L_LCLK) */ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [2..65 Tpix] */ \ + (((Tpix) - 2) << FShft (LCCR1_HSW)) +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) + +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ + (((Line) - 1) << FShft (LCCR2_LPP)) +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) + +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ + /* [1..255] (L_PCLK) */ + /* fpix = fcpu/(2*(PCD + 2)) */ + /* Tpix = 2*(PCD + 2)*Tcpu */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ + (((Div) - 4)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Floor (Div/2)) */ + /* Tpix = 2*Floor (Div/2)*Tcpu */ +#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ + (((Div) - 3)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Ceil (Div/2)) */ + /* Tpix = 2*Ceil (Div/2)*Tcpu */ +#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ + /* [Tln] (L_BIAS) */ +#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ + (((Div) - 2)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Floor (Div/2)) */ + /* Tac = 2*Floor (Div/2)*Tln */ +#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ + (((Div) - 1)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Ceil (Div/2)) */ + /* Tac = 2*Ceil (Div/2)*Tln */ +#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ + /* Interrupt */ +#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ + /* Off */ \ + (0 << FShft (LCCR3_API)) +#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ + /* [1..15] */ \ + ((Trans) << FShft (LCCR3_API)) +#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ + /* Polarity (L_FCLK) */ +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ + /* active High */ +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ +#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ + /* pulse Polarity (L_LCLK) */ +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + /* pulse active Low */ +#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ +#define LCCR3_PixFlEdg (LCCR3_PCP*0) /* Pixel clock Falling-Edge */ +#define LCCR3_PixRsEdg (LCCR3_PCP*1) /* Pixel clock Rising-Edge */ +#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ + /* active display mode) */ +#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ +#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ + + +#undef C +#undef Assembly + diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h new file mode 100644 index 000000000..854a6d292 --- /dev/null +++ b/include/asm-arm/arch-sa1100/SA-1101.h @@ -0,0 +1,917 @@ +/* + * SA-1101.h + * + * Copyright (c) Peter Danielsson 1999 + * + * Definition of constants related to the sa1101 + * support chip for the sa1100 + * + */ + + +/* Be sure that virtual mapping is defined right */ +#ifndef __ASM_ARCH_HARDWARE_H +#error You must include hardware.h not SA-1101.h +#endif + +#ifndef SA1101_BASE +#error You must define SA-1101 physical base address +#endif + +#ifndef LANGUAGE +# ifdef __ASSEMBLY__ +# define LANGUAGE Assembly +# else +# define LANGUAGE C +# endif +#endif + +#ifndef SA1101_p2v +#define SA1101_p2v(PhAdd) (PhAdd) +#endif + +#include <asm/arch/bitfield.h> + +#define C 0 +#define Assembly 1 + + +/* + * Memory map + */ + +#define __SHMEM_CONTROL0 0x00000000 +#define __SYSTEM_CONTROL1 0x00000400 +#define __ARBITER 0x00020000 +#define __SYSTEM_CONTROL2 0x00040000 +#define __SYSTEM_CONTROL3 0x00060000 +#define __PARALLEL_PORT 0x00080000 +#define __VIDMEM_CONTROL 0x00100000 +#define __UPDATE_FIFO 0x00120000 +#define __SHMEM_CONTROL1 0x00140000 +#define __INTERRUPT_CONTROL 0x00160000 +#define __USB_CONTROL 0x00180000 +#define __TRACK_INTERFACE 0x001a0000 +#define __MOUSE_INTERFACE 0x001b0000 +#define __KEYPAD_INTERFACE 0x001c0000 +#define __PCMCIA_INTERFACE 0x001e0000 +#define __VGA_CONTROL 0x00200000 +#define __GPIO_INTERFACE 0x00300000 + +/* + * Macro that calculates real address for registers in the SA-1101 + */ + +#define _SA1101( x ) ((x) + SA1101_BASE) + +/* + * Interface and shared memory controller registers + * + * Registers + * SKCR SA-1101 control register (read/write) + * SMCR Shared Memory Controller Register + * SNPR Snoop Register + */ + +#define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */ +#define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */ +#define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */ + +#if LANGUAGE == C +#define SKCR (*((volatile Word *) SA1101_p2v (_SKCR))) +#define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) +#define SNPR (*((volatile Word *) SA1101_p2v (_SNPR))) + +#define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */ +#define SKCR_BCLKEn 0x0002 /* Enables BCLK */ +#define SKCR_Sleep 0x0004 /* Sleep Mode */ +#define SKCR_IRefEn 0x0008 /* DAC Iref input enable */ +#define SKCR_VCOON 0x0010 /* VCO bias */ +#define SKCR_ScanTestEn 0x0020 /* Enables scan test */ +#define SKCR_ClockTestEn 0x0040 /* Enables clock test */ + +#define SMCR_DCAC Fld(2,0) /* Number of column address bits */ +#define SMCR_DRAC Fld(2,2) /* Number of row address bits */ +#define SMCR_ArbiterBias 0x0008 /* favor video or USB */ +#define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */ + +#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ + (( (x) - 8 ) << FShft (SMCR_DCAC)) +#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ + (( (x) - 9 ) << FShft (SMCR_DRAC) + +#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ +#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ +#define SNPR_WholeBank (1 << 23) /* Whole bank bit */ +#define SNPR_BankSelect Fld(2,27) /* Bank select */ +#define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */ + +#define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \ + ( (x) << FShft (SNPR_VFBsize)) +#define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \ + (( (x) + 1 ) << FShft (SNPR_BankSelect )) + +#endif /* LANGUAGE == C */ + +/* + * Video Memory Controller + * + * Registers + * VMCCR Configuration register + * VMCAR VMC address register + * VMCDR VMC data register + * + */ + +#define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */ +#define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */ +#define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */ + +#if LANGUAGE == C +#define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR))) +#define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR))) +#define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR))) + +#define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */ +#define VMCCR_Config 0x0001 /* DRAM size */ +#define VMCCR_RefPeriod Fld(2,3) /* Refresh period */ +#define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */ +#define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/ +#define VMCCR_RefTest (1<<10) /* refresh test */ +#define VMCCR_RefLow Fld(6,11) /* refresh low counter */ +#define VMCCR_RefHigh Fld(7,17) /* refresh high counter */ +#define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */ +#define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */ + +#endif LANGUAGE == C + + +/* Update FIFO + * + * Registers + * UFCR Update FIFO Control Register + * UFSR Update FIFO Status Register + * UFLVLR update FIFO level register + * UFDR update FIFO data register + */ + +#define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */ +#define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ +#define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */ +#define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */ + +#if LANGUAGE == C + +#define UFCR (*((volatile Word *) SA1101_p2v (_UFCR))) +#define UFSR (*((volatile Word *) SA1101_p2v (_UFSR))) +#define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) +#define UFDR (*((volatile Word *) SA1101_p2v (_UFDR))) + + +#define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */ + +#define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */ + +#endif /* LANGUAGE == C */ + +/* System Controller + * + * Registers + * SKPCR Power Control Register + * SKCDR Clock Divider Register + * DACDR1 DAC1 Data register + * DACDR2 DAC2 Data register + */ + +#define _SKPCR _SA1101(0x00000400) +#define _SKCDR _SA1101(0x00040000) +#define _DACDR1 _SA1101(0x00060000) +#define _DACDR2 _SA1101(0x00060400) + +#if LANGUAGE == C +#define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR))) +#define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR))) +#define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1))) +#define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2))) + +#define SKPCR_UCLKEn 0x01 /* USB Enable */ +#define SKPCR_PCLKEn 0x02 /* PS/2 Enable */ +#define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */ +#define SKPCR_VCLKEn 0x08 /* Video Controller Enable */ +#define SKPCR_PICLKEn 0x10 /* parallel port Enable */ +#define SKPCR_DCLKEn 0x20 /* DACs Enable */ +#define SKPCR_nKPADEn 0x40 /* Multiplexer */ + +#define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */ +#define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */ +#define SKDCR_BCLKEn (1<<9) /* BCLK Divider */ +#define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */ +#define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */ +#define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */ +#define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */ +#define SKDCR_ChargePump (1<<25) /* Charge pump control */ +#define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */ +#define SKDCR_ClkTestEn (1<<27) /* Test clock generator */ +#define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */ + +#define DACDR_DACCount Fld(8,0) /* Count value */ +#define DACDR1_DACCount DACDR_DACCount +#define DACDR2_DACCount DACDR_DACCount + +#endif /* LANGUAGE == C */ + +/* + * Parallel Port Interface + * + * Registers + * IEEE_Config IEEE mode selection and programmable attributes + * IEEE_Control Controls the states of IEEE port control outputs + * IEEE_Data Forward transfer data register + * IEEE_Addr Forward transfer address register + * IEEE_Status Port IO signal status register + * IEEE_IntStatus Port interrupts status register + * IEEE_FifoLevels Rx and Tx FIFO interupt generation levels + * IEEE_InitTime Forward timeout counter initial value + * IEEE_TimerStatus Forward timeout counter current value + * IEEE_FifoReset Reset forward transfer FIFO + * IEEE_ReloadValue Counter reload value + * IEEE_TestControl Control testmode + * IEEE_TestDataIn Test data register + * IEEE_TestDataInEn Enable test data + * IEEE_TestCtrlIn Test control signals + * IEEE_TestCtrlInEn Enable test control signals + * IEEE_TestDataStat Current data bus value + * + */ + +/* + * The control registers are defined as offsets from a base address + */ + +#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT ) + +#define _IEEE_Config _IEEE( 0x0000 ) +#define _IEEE_Control _IEEE( 0x0400 ) +#define _IEEE_Data _IEEE( 0x4000 ) +#define _IEEE_Addr _IEEE( 0x0800 ) +#define _IEEE_Status _IEEE( 0x0c00 ) +#define _IEEE_IntStatus _IEEE( 0x1000 ) +#define _IEEE_FifoLevels _IEEE( 0x1400 ) +#define _IEEE_InitTime _IEEE( 0x1800 ) +#define _IEEE_TimerStatus _IEEE( 0x1c00 ) +#define _IEEE_FifoReset _IEEE( 0x2000 ) +#define _IEEE_ReloadValue _IEEE( 0x3c00 ) +#define _IEEE_TestControl _IEEE( 0x2400 ) +#define _IEEE_TestDataIn _IEEE( 0x2800 ) +#define _IEEE_TestDataInEn _IEEE( 0x2c00 ) +#define _IEEE_TestCtrlIn _IEEE( 0x3000 ) +#define _IEEE_TestCtrlInEn _IEEE( 0x3400 ) +#define _IEEE_TestDataStat _IEEE( 0x3800 ) + + +#if LANGUAGE == C +#define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config))) +#define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control))) +#define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data))) +#define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr))) +#define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status))) +#define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus))) +#define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels))) +#define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime))) +#define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus))) +#define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset))) +#define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue))) +#define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl))) +#define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn))) +#define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn))) +#define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn))) +#define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn))) +#define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat))) + + +#define IEEE_Config_M Fld(3,0) /* Mode select */ +#define IEEE_Config_D 0x04 /* FIFO access enable */ +#define IEEE_Config_B 0x08 /* 9-bit word enable */ +#define IEEE_Config_T 0x10 /* Data transfer enable */ +#define IEEE_Config_A 0x20 /* Data transfer direction */ +#define IEEE_Config_E 0x40 /* Timer enable */ +#define IEEE_Control_A 0x08 /* AutoFd output */ +#define IEEE_Control_E 0x04 /* Selectin output */ +#define IEEE_Control_T 0x02 /* Strobe output */ +#define IEEE_Control_I 0x01 /* Port init output */ +#define IEEE_Data_C (1<<31) /* Byte count */ +#define IEEE_Data_Db Fld(9,16) /* Data byte 2 */ +#define IEEE_Data_Da Fld(9,0) /* Data byte 1 */ +#define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */ +#define IEEE_Status_A 0x0100 /* nAutoFd port output status */ +#define IEEE_Status_E 0x0080 /* nSelectIn port output status */ +#define IEEE_Status_T 0x0040 /* nStrobe port output status */ +#define IEEE_Status_I 0x0020 /* nInit port output status */ +#define IEEE_Status_B 0x0010 /* Busy port inout status */ +#define IEEE_Status_S 0x0008 /* Select port input status */ +#define IEEE_Status_K 0x0004 /* nAck port input status */ +#define IEEE_Status_F 0x0002 /* nFault port input status */ +#define IEEE_Status_R 0x0001 /* pError port input status */ + +#define IEEE_IntStatus_IntReqDat 0x0100 +#define IEEE_IntStatus_IntReqEmp 0x0080 +#define IEEE_IntStatus_IntReqInt 0x0040 +#define IEEE_IntStatus_IntReqRav 0x0020 +#define IEEE_IntStatus_IntReqTim 0x0010 +#define IEEE_IntStatus_RevAddrComp 0x0008 +#define IEEE_IntStatus_RevDataComp 0x0004 +#define IEEE_IntStatus_FwdAddrComp 0x0002 +#define IEEE_IntStatus_FwdDataComp 0x0001 +#define IEEE_FifoLevels_RevFifoLevel 2 +#define IEEE_FifoLevels_FwdFifoLevel 1 +#define IEEE_InitTime_TimValInit Fld(22,0) +#define IEEE_TimerStatus_TimValStat Fld(22,0) +#define IEEE_ReloadValue_Reload Fld(4,0) + +#define IEEE_TestControl_RegClk 0x04 +#define IEEE_TestControl_ClockSelect Fld(2,1) +#define IEEE_TestControl_TimerTestModeEn 0x01 +#define IEEE_TestCtrlIn_PError 0x10 +#define IEEE_TestCtrlIn_nFault 0x08 +#define IEEE_TestCtrlIn_nAck 0x04 +#define IEEE_TestCtrlIn_PSel 0x02 +#define IEEE_TestCtrlIn_Busy 0x01 + +#endif /* LANGUAGE == C */ + +/* + * VGA Controller + * + * Registers + * VideoControl Video Control Register + * VgaTiming0 VGA Timing Register 0 + * VgaTiming1 VGA Timing Register 1 + * VgaTiming2 VGA Timing Register 2 + * VgaTiming3 VGA Timing Register 3 + * VgaBorder VGA Border Color Register + * VgaDBAR VGADMA Base Address Register + * VgaDCAR VGADMA Channel Current Address Register + * VgaStatus VGA Status Register + * VgaInterruptMask VGA Interrupt Mask Register + * VgaPalette VGA Palette Registers + * DacControl DAC Control Register + * VgaTest VGA Controller Test Register + */ + +#define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL ) + +#define _VideoControl _VGA( 0x0000 ) +#define _VgaTiming0 _VGA( 0x0400 ) +#define _VgaTiming1 _VGA( 0x0800 ) +#define _VgaTiming2 _VGA( 0x0c00 ) +#define _VgaTiming3 _VGA( 0x1000 ) +#define _VgaBorder _VGA( 0x1400 ) +#define _VgaDBAR _VGA( 0x1800 ) +#define _VgaDCAR _VGA( 0x1c00 ) +#define _VgaStatus _VGA( 0x2000 ) +#define _VgaInterruptMask _VGA( 0x2400 ) +#define _VgaPalette _VGA( 0x40000 ) +#define _DacControl _VGA( 0x3000 ) +#define _VgaTest _VGA( 0x2c00 ) + +#if (LANGUAGE == C) +#define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl))) +#define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0))) +#define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1))) +#define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2))) +#define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3))) +#define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder))) +#define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR))) +#define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR))) +#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) +#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) +#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) +#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)) +#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) + +#define VideoControl_VgaEn 0x00000000 +#define VideoControl_BGR 0x00000001 +#define VideoControl_VCompVal Fld(2,2) +#define VideoControl_VgaReq Fld(4,4) +#define VideoControl_VBurstL Fld(4,8) +#define VideoControl_VMode (1<<12) +#define VideoControl_PalRead (1<<13) + +#define VgaTiming0_PPL Fld(6,2) +#define VgaTiming0_HSW Fld(8,8) +#define VgaTiming0_HFP Fld(8,16) +#define VgaTiming0_HBP Fld(8,24) + +#define VgaTiming1_LPS Fld(10,0) +#define VgaTiming1_VSW Fld(6,10) +#define VgaTiming1_VFP Fld(8,16) +#define VgaTiming1_VBP Fld(8,24) + +#define VgaTiming2_IVS 0x01 +#define VgaTiming2_IHS 0x02 +#define VgaTiming2_CVS 0x04 +#define VgaTiming2_CHS 0x08 + +#define VgaTiming3_HBS Fld(8,0) +#define VgaTiming3_HBE Fld(8,8) +#define VgaTiming3_VBS Fld(8,16) +#define VgaTiming3_VBE Fld(8,24) + +#define VgaBorder_BCOL Fld(24,0) + +#define VgaStatus_VFUF 0x01 +#define VgaStatus_VNext 0x02 +#define VgaStatus_VComp 0x04 + +#define VgaInterruptMask_VFUFMask 0x00 +#define VgaInterruptMask_VNextMask 0x01 +#define VgaInterruptMask_VCompMask 0x02 + +#define VgaPalette_R Fld(8,0) +#define VgaPalette_G Fld(8,8) +#define VgaPalette_B Fld(8,16) + +#define DacControl_DACON 0x0001 +#define DacControl_COMPON 0x0002 +#define DacControl_PEDON 0x0004 +#define DacControl_RTrim Fld(5,4) +#define DacControl_GTrim Fld(5,9) +#define DacControl_BTrim Fld(5,14) + +#define VgaTest_TDAC 0x00 +#define VgaTest_Datatest Fld(4,1) +#define VgaTest_DACTESTDAC 0x10 +#define VgaTest_DACTESTOUT Fld(3,5) + +#endif /* LANGUAGE == C */ + +/* + * USB Host Interface Controller + * + * Registers + * Revision + * Control + * CommandStatus + * InterruptStatus + * InterruptEnable + * HCCA + * PeriodCurrentED + * ControlHeadED + * BulkHeadED + * BulkCurrentED + * DoneHead + * FmInterval + * FmRemaining + * FmNumber + * PeriodicStart + * LSThreshold + * RhDescriptorA + * RhDescriptorB + * RhStatus + * RhPortStatus + * USBStatus + * USBReset + * USTAR + * USWER + * USRFR + * USNFR + * USTCSR + * USSR + * + */ + +#define _USB( x ) _SA1101( ( x ) + __USB_CONTROL ) + + +#define _Revision _USB( 0x0000 ) +#define _Control _USB( 0x0888 ) +#define _CommandStatus _USB( 0x0c00 ) +#define _InterruptStatus _USB( 0x1000 ) +#define _InterruptEnable _USB( 0x1400 ) +#define _HCCA _USB( 0x1800 ) +#define _PeriodCurrentED _USB( 0x1c00 ) +#define _ControlHeadED _USB( 0x2000 ) +#define _BulkHeadED _USB( 0x2800 ) +#define _BulkCurrentED _USB( 0x2c00 ) +#define _DoneHead _USB( 0x3000 ) +#define _FmInterval _USB( 0x3400 ) +#define _FmRemaining _USB( 0x3800 ) +#define _FmNumber _USB( 0x3c00 ) +#define _PeriodicStart _USB( 0x4000 ) +#define _LSThreshold _USB( 0x4400 ) +#define _RhDescriptorA _USB( 0x4800 ) +#define _RhDescriptorB _USB( 0x4c00 ) +#define _RhStatus _USB( 0x5000 ) +#define _RhPortStatus _USB( 0x5400 ) +#define _USBStatus _USB( 0x11800 ) +#define _USBReset _USB( 0x11c00 ) + +#define _USTAR _USB( 0x10400 ) +#define _USWER _USB( 0x10800 ) +#define _USRFR _USB( 0x10c00 ) +#define _USNFR _USB( 0x11000 ) +#define _USTCSR _USB( 0x11400 ) +#define _USSR _USB( 0x11800 ) + + +#if (LANGUAGE == C) + +#define Revision (*((volatile Word *) SA1101_p2v (_Revision))) +#define Control (*((volatile Word *) SA1101_p2v (_Control))) +#define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus))) +#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus))) +#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable))) +#define HCCA (*((volatile Word *) SA1101_p2v (_HCCA))) +#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED))) +#define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED))) +#define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED))) +#define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED))) +#define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead))) +#define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval))) +#define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining))) +#define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber))) +#define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart))) +#define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold))) +#define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA))) +#define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB))) +#define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus))) +#define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus))) +#define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus))) +#define USBReset (*((volatile Word *) SA1101_p2v (_USBReset))) +#define USTAR (*((volatile Word *) SA1101_p2v (_USTAR))) +#define USWER (*((volatile Word *) SA1101_p2v (_USWER))) +#define USRFR (*((volatile Word *) SA1101_p2v (_USRFR))) +#define USNFR (*((volatile Word *) SA1101_p2v (_USNFR))) +#define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR))) +#define USSR (*((volatile Word *) SA1101_p2v (_USSR))) + + +#define USBStatus_IrqHciRmtWkp (1<<7) +#define USBStatus_IrqHciBuffAcc (1<<8) +#define USBStatus_nIrqHciM (1<<9) +#define USBStatus_nHciMFClr (1<<10) + +#define USBReset_ForceIfReset 0x01 +#define USBReset_ForceHcReset 0x02 +#define USBReset_ClkGenReset 0x04 + +#define USTCR_RdBstCntrl Fld(3,0) +#define USTCR_ByteEnable Fld(4,3) +#define USTCR_WriteEn (1<<7) +#define USTCR_FifoCir (1<<8) +#define USTCR_TestXferSel (1<<9) +#define USTCR_FifoCirAtEnd (1<<10) +#define USTCR_nSimScaleDownClk (1<<11) + +#define USSR_nAppMDEmpty 0x01 +#define USSR_nAppMDFirst 0x02 +#define USSR_nAppMDLast 0x04 +#define USSR_nAppMDFull 0x08 +#define USSR_nAppMAFull 0x10 +#define USSR_XferReq 0x20 +#define USSR_XferEnd 0x40 + +#endif /* LANGUAGE == C */ + + +/* + * Interrupt Controller + * + * Registers + * INTTEST0 Test register 0 + * INTTEST1 Test register 1 + * INTENABLE0 Interrupt Enable register 0 + * INTENABLE1 Interrupt Enable register 1 + * INTPOL0 Interrupt Polarity selection 0 + * INTPOL1 Interrupt Polarity selection 1 + * INTTSTSEL Interrupt source selection + * INTSTATCLR0 Interrupt Status 0 + * INTSTATCLR1 Interrupt Status 1 + * INTSET0 Interrupt Set 0 + * INTSET1 Interrupt Set 1 + */ + +#define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL) + +#define _INTTEST0 _INT( 0x1000 ) +#define _INTTEST1 _INT( 0x1400 ) +#define _INTENABLE0 _INT( 0x2000 ) +#define _INTENABLE1 _INT( 0x2400 ) +#define _INTPOL0 _INT( 0x3000 ) +#define _INTPOL1 _INT( 0x3400 ) +#define _INTTSTSEL _INT( 0x5000 ) +#define _INTSTATCLR0 _INT( 0x6000 ) +#define _INTSTATCLR1 _INT( 0x6400 ) +#define _INTSET0 _INT( 0x7000 ) +#define _INTSET1 _INT( 0x7400 ) + +#if ( LANGUAGE == C ) +#define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0))) +#define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1))) +#define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0))) +#define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1))) +#define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0))) +#define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1))) +#define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL))) +#define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0))) +#define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1))) +#define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0))) +#define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1))) + +#endif /* LANGUAGE == C */ + +/* + * PS/2 Trackpad and Mouse Interfaces + * + * Registers (prefix kbd applies to trackpad interface, mse to mouse) + * KBDCR Control Register + * KBDSTAT Status Register + * KBDDATA Transmit/Receive Data register + * KBDCLKDIV Clock Division Register + * KBDPRECNT Clock Precount Register + * KBDTEST1 Test register 1 + * KBDTEST2 Test register 2 + * KBDTEST3 Test register 3 + * KBDTEST4 Test register 4 + * MSECR + * MSESTAT + * MSEDATA + * MSECLKDIV + * MSEPRECNT + * MSETEST1 + * MSETEST2 + * MSETEST3 + * MSETEST4 + * + */ + +#define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE ) +#define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE ) + +#define _KBDCR _KBD( 0x0000 ) +#define _KBDSTAT _KBD( 0x0400 ) +#define _KBDDATA _KBD( 0x0800 ) +#define _KBDCLKDIV _KBD( 0x0c00 ) +#define _KBDPRECNT _KBD( 0x1000 ) +#define _KBDTEST1 _KBD( 0x2000 ) +#define _KBDTEST2 _KBD( 0x2400 ) +#define _KBDTEST3 _KBD( 0x2800 ) +#define _KBDTEST4 _KBD( 0x2c00 ) +#define _MSECR _MSE( 0x0000 ) +#define _MSESTAT _MSE( 0x0400 ) +#define _MSEDATA _MSE( 0x0800 ) +#define _MSECLKDIV _MSE( 0x0c00 ) +#define _MSEPRECNT _MSE( 0x1000 ) +#define _MSETEST1 _MSE( 0x2000 ) +#define _MSETEST2 _MSE( 0x2400 ) +#define _MSETEST3 _MSE( 0x2800 ) +#define _MSETEST4 _MSE( 0x2c00 ) + +#if ( LANGUAGE == C ) + +#define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR))) +#define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT))) +#define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA))) +#define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV))) +#define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT))) +#define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1))) +#define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2))) +#define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3))) +#define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4))) +#define MSECR (*((volatile Word *) SA1101_p2v (_MSECR))) +#define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT))) +#define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA))) +#define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV))) +#define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT))) +#define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1))) +#define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2))) +#define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3))) +#define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4))) + + +#define KBDCR_ENA 0x08 +#define KBDCR_FKD 0x02 +#define KBDCR_FKC 0x01 + +#define KBDSTAT_TXE 0x80 +#define KBDSTAT_TXB 0x40 +#define KBDSTAT_RXF 0x20 +#define KBDSTAT_RXB 0x10 +#define KBDSTAT_ENA 0x08 +#define KBDSTAT_RXP 0x04 +#define KBDSTAT_KBD 0x02 +#define KBDSTAT_KBC 0x01 + +#define KBDCLKDIV_DivVal Fld(4,0) + +#define MSECR_ENA 0x08 +#define MSECR_FKD 0x02 +#define MSECR_FKC 0x01 + +#define MSESTAT_TXE 0x80 +#define MSESTAT_TXB 0x40 +#define MSESTAT_RXF 0x20 +#define MSESTAT_RXB 0x10 +#define MSESTAT_ENA 0x08 +#define MSESTAT_RXP 0x04 +#define MSESTAT_MSD 0x02 +#define MSESTAT_MSC 0x01 + +#define MSECLKDIV_DivVal Fld(4,0) + +#define KBDTEST1_CD 0x80 +#define KBDTEST1_RC1 0x40 +#define KBDTEST1_MC 0x20 +#define KBDTEST1_C Fld(2,3) +#define KBDTEST1_T2 0x40 +#define KBDTEST1_T1 0x20 +#define KBDTEST1_T0 0x10 +#define KBDTEST2_TICBnRES 0x08 +#define KBDTEST2_RKC 0x04 +#define KBDTEST2_RKD 0x02 +#define KBDTEST2_SEL 0x01 +#define KBDTEST3_ms_16 0x80 +#define KBDTEST3_us_64 0x40 +#define KBDTEST3_us_16 0x20 +#define KBDTEST3_DIV8 0x10 +#define KBDTEST3_DIn 0x08 +#define KBDTEST3_CIn 0x04 +#define KBDTEST3_KD 0x02 +#define KBDTEST3_KC 0x01 +#define KBDTEST4_BC12 0x80 +#define KBDTEST4_BC11 0x40 +#define KBDTEST4_TRES 0x20 +#define KBDTEST4_CLKOE 0x10 +#define KBDTEST4_CRES 0x08 +#define KBDTEST4_RXB 0x04 +#define KBDTEST4_TXB 0x02 +#define KBDTEST4_SRX 0x01 + +#define MSETEST1_CD 0x80 +#define MSETEST1_RC1 0x40 +#define MSETEST1_MC 0x20 +#define MSETEST1_C Fld(2,3) +#define MSETEST1_T2 0x40 +#define MSETEST1_T1 0x20 +#define MSETEST1_T0 0x10 +#define MSETEST2_TICBnRES 0x08 +#define MSETEST2_RKC 0x04 +#define MSETEST2_RKD 0x02 +#define MSETEST2_SEL 0x01 +#define MSETEST3_ms_16 0x80 +#define MSETEST3_us_64 0x40 +#define MSETEST3_us_16 0x20 +#define MSETEST3_DIV8 0x10 +#define MSETEST3_DIn 0x08 +#define MSETEST3_CIn 0x04 +#define MSETEST3_KD 0x02 +#define MSETEST3_KC 0x01 +#define MSETEST4_BC12 0x80 +#define MSETEST4_BC11 0x40 +#define MSETEST4_TRES 0x20 +#define MSETEST4_CLKOE 0x10 +#define MSETEST4_CRES 0x08 +#define MSETEST4_RXB 0x04 +#define MSETEST4_TXB 0x02 +#define MSETEST4_SRX 0x01 + +#endif /* LANGUAGE == C */ + + +/* + * General-Purpose I/O Interface + * + * Registers + * PADWR Port A Data Write Register + * PBDWR Port B Data Write Register + * PADRR Port A Data Read Register + * PBDRR Port B Data Read Register + * PADDR Port A Data Direction Register + * PBDDR Port B Data Direction Register + * PASSR Port A Sleep State Register + * PBSSR Port B Sleep State Register + * + */ + +#define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE ) + +#define _PADWR _PIO( 0x0000 ) +#define _PBDWR _PIO( 0x0400 ) +#define _PADRR _PIO( 0x0000 ) +#define _PBDRR _PIO( 0x0400 ) +#define _PADDR _PIO( 0x0800 ) +#define _PBDDR _PIO( 0x0c00 ) +#define _PASSR _PIO( 0x1000 ) +#define _PBSSR _PIO( 0x1400 ) + + +#if ( LANGUAGE == C ) + + +#define PADWR (*((volatile Word *) SA1101_p2v (_PADWR))) +#define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR))) +#define PADRR (*((volatile Word *) SA1101_p2v (_PADRR))) +#define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR))) +#define PADDR (*((volatile Word *) SA1101_p2v (_PADDR))) +#define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR))) +#define PASSR (*((volatile Word *) SA1101_p2v (_PASSR))) +#define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR))) + +#endif + + + +/* + * Keypad Interface + * + * Registers + * PXDWR + * PXDRR + * PYDWR + * PYDRR + * + */ + +#define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE ) + +#define _PXDWR _KEYPAD( 0x0000 ) +#define _PXDRR _KEYPAD( 0x0000 ) +#define _PYDWR _KEYPAD( 0x0400 ) +#define _PYDRR _KEYPAD( 0x0400 ) + +#if ( LANGUAGE == C ) + + +#define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR))) +#define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR))) +#define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR))) +#define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR))) + +#endif + + + +/* + * PCMCIA Interface + * + * Registers + * PCSR Status Register + * PCCR Control Register + * PCSSR Sleep State Register + * + */ + +#define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE ) + +#define _PCSR _CARD( 0x0000 ) +#define _PCCR _CARD( 0x0400 ) +#define _PCSSR _CARD( 0x0800 ) + +#if ( LANGUAGE == C ) +#define PCSR (*((volatile Word *) SA1101_p2v (_PCSR))) +#define PCCR (*((volatile Word *) SA1101_p2v (_PCCR))) +#define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR))) + +#define PCSR_S0_ready 0x0001 +#define PCSR_S1_ready 0x0002 +#define PCSR_S0_detected 0x0004 +#define PCSR_S1_detected 0x0008 +#define PCSR_S0_VS1 0x0010 +#define PCSR_S0_VS2 0x0020 +#define PCSR_S1_VS1 0x0040 +#define PCSR_S1_VS2 0x0080 +#define PCSR_S0_WP 0x0100 +#define PCSR_S1_WP 0x0200 +#define PCSR_S0_BVD1_nSTSCHG 0x0400 +#define PCSR_S0_BVD2_nSPKR 0x0800 +#define PCSR_S1_BVD1_nSTSCHG 0x1000 +#define PCSR_S1_BVD2_nSPKR 0x2000 + +#define PCCR_S0_VPP0 0x0001 +#define PCCR_S0_VPP1 0x0002 +#define PCCR_S0_VCC0 0x0004 +#define PCCR_S0_VCC1 0x0008 +#define PCCR_S1_VPP0 0x0010 +#define PCCR_S1_VPP1 0x0020 +#define PCCR_S1_VCC0 0x0040 +#define PCCR_S1_VCC1 0x0080 +#define PCCR_S0_reset 0x0100 +#define PCCR_S1_reset 0x0200 +#define PCCR_S0_float 0x0400 +#define PCCR_S1_float 0x0800 + +#define PCSSR_S0_VCC0 0x0001 +#define PCSSR_S0_VCC1 0x0002 +#define PCSSR_S0_VPP0 0x0004 +#define PCSSR_S0_VPP1 0x0008 +#define PCSSR_S0_control 0x0010 +#define PCSSR_S1_VCC0 0x0020 +#define PCSSR_S1_VCC1 0x0040 +#define PCSSR_S1_VPP0 0x0080 +#define PCSSR_S1_VPP1 0x0100 +#define PCSSR_S1_control 0x0200 + +#endif + +#undef C +#undef Assembly diff --git a/include/asm-arm/arch-sa1100/SA-1111.h b/include/asm-arm/arch-sa1100/SA-1111.h new file mode 100644 index 000000000..34c303261 --- /dev/null +++ b/include/asm-arm/arch-sa1100/SA-1111.h @@ -0,0 +1,265 @@ +/* + * linux/include/asm/arch/SA-1111.h + * + * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> + * + * This file contains definitions for the SA-1111 Companion Chip. + * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) + * + */ + +#ifndef _ASM_ARCH_SA1111 +#define _ASM_ARCH_SA1111 + +/* + * Macro that calculates real address for registers in the SA-1111 + */ + +#define _SA1111( x ) ((x) + SA1111_BASE) + +/* + * System Bus Interface (SBI) + * + * Registers + * SKCR Control Register + * SMCR Shared Memory Controller Register + * SKID ID Register + */ + +#define _SKCR _SA1111( 0x0000 ) +#define _SMCR _SA1111( 0x0004 ) +#define _SKID _SA1111( 0x0008 ) + +#if LANGUAGE == C + +#define SKCR (*((volatile Word *) SA1111_p2v (_SKCR))) +#define SMCR (*((volatile Word *) SA1111_p2v (_SMCR))) +#define SKID (*((volatile Word *) SA1111_p2v (_SKID))) + +#endif /* LANGUAGE == C */ + +#define SKCR_PLL_BYPASS (1<<0) +#define SKCR_RCLKEN (1<<1) +#define SKCR_SLEEP (1<<2) +#define SKCR_DOZE (1<<3) +#define SKCR_VCO_OFF (1<<4) +#define SKCR_SCANTSTEN (1<<5) +#define SKCR_CLKTSTEN (1<<6) +#define SKCR_RDYEN (1<<7) +#define SKCR_SELAC (1<<8) +#define SKCR_OPPC (1<<9) +#define SKCR_PLLTSTEN (1<<10) +#define SKCR_USBIOTSTEN (1<<11) +#define SKCR_OE_EN (1<<13) + +#define SMCR_DTIM (1<<0) +#define SMCR_MBGE (1<<1) +#define SMCR_DRAC_0 (1<<2) +#define SMCR_DRAC_1 (1<<3) +#define SMCR_DRAC_2 (1<<4) +#define SMCR_CLAT (1<<5) + +#define SKID_SIREV_MASK (0x000000f0) +#define SKID_MTREV_MASK (0x0000000f) +#define SKID_ID_MASK (0xffffff00) +#define SKID_SA1111_ID (0x690cc200) + +/* + * System Controller + * + * Registers + * SKPCR Power Control Register + * SKCDR Clock Divider Register + * SKAUD Audio Clock Divider Register + * SKPMC PS/2 Mouse Clock Divider Register + * SKPTC PS/2 Track Pad Clock Divider Register + * SKPEN0 PWM0 Enable Register + * SKPWM0 PWM0 Clock Register + * SKPEN1 PWM1 Enable Register + * SKPWM1 PWM1 Clock Register + */ + +#define _SKPCR _SA1111(0x0200) +#define _SKCDR _SA1111(0x0204) +#define _SKAUD _SA1111(0x0208) +#define _SKPMC _SA1111(0x020c) +#define _SKPTC _SA1111(0x0210) +#define _SKPEN0 _SA1111(0x0214) +#define _SKPWM0 _SA1111(0x0218) +#define _SKPEN1 _SA1111(0x021c) +#define _SKPWM1 _SA1111(0x0220) + +#if LANGUAGE == C + +#define SKPCR (*((volatile Word *) SA1111_p2v (_SKPCR))) +#define SKCDR (*((volatile Word *) SA1111_p2v (_SKCDR))) +#define SKAUD (*((volatile Word *) SA1111_p2v (_SKAUD))) +#define SKPMC (*((volatile Word *) SA1111_p2v (_SKPMC))) +#define SKPTC (*((volatile Word *) SA1111_p2v (_SKPTC))) +#define SKPEN0 (*((volatile Word *) SA1111_p2v (_SKPEN0))) +#define SKPWM0 (*((volatile Word *) SA1111_p2v (_SKPWM0))) +#define SKPEN1 (*((volatile Word *) SA1111_p2v (_SKPEN1))) +#define SKPWM1 (*((volatile Word *) SA1111_p2v (_SKPWM1))) + +#endif /* LANGUAGE == C */ + +/* + * General-Purpose I/O Interface + * + * Registers + * PA_DDR GPIO Block A Data Direction + * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write) + * PA_SDR GPIO Block A Sleep Direction + * PA_SSR GPIO Block A Sleep State + * PB_DDR GPIO Block B Data Direction + * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write) + * PB_SDR GPIO Block B Sleep Direction + * PB_SSR GPIO Block B Sleep State + * PC_DDR GPIO Block C Data Direction + * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write) + * PC_SDR GPIO Block C Sleep Direction + * PC_SSR GPIO Block C Sleep State + */ + +#define _PA_DDR _SA1111( 0x1000 ) +#define _PA_DRR _SA1111( 0x1004 ) +#define _PA_DWR _SA1111( 0x1004 ) +#define _PA_SDR _SA1111( 0x1008 ) +#define _PA_SSR _SA1111( 0x100c ) +#define _PB_DDR _SA1111( 0x1010 ) +#define _PB_DRR _SA1111( 0x1014 ) +#define _PB_DWR _SA1111( 0x1014 ) +#define _PB_SDR _SA1111( 0x1018 ) +#define _PB_SSR _SA1111( 0x101c ) +#define _PC_DDR _SA1111( 0x1020 ) +#define _PC_DRR _SA1111( 0x1024 ) +#define _PC_DWR _SA1111( 0x1024 ) +#define _PC_SDR _SA1111( 0x1028 ) +#define _PC_SSR _SA1111( 0x102c ) + +#if LANGUAGE == C + +#define PA_DDR (*((volatile Word *) SA1111_p2v (_PA_DDR))) +#define PA_DRR (*((volatile Word *) SA1111_p2v (_PA_DRR))) +#define PA_DWR (*((volatile Word *) SA1111_p2v (_PA_DWR))) +#define PA_SDR (*((volatile Word *) SA1111_p2v (_PA_SDR))) +#define PA_SSR (*((volatile Word *) SA1111_p2v (_PA_SSR))) +#define PB_DDR (*((volatile Word *) SA1111_p2v (_PB_DDR))) +#define PB_DRR (*((volatile Word *) SA1111_p2v (_PB_DRR))) +#define PB_DWR (*((volatile Word *) SA1111_p2v (_PB_DWR))) +#define PB_SDR (*((volatile Word *) SA1111_p2v (_PB_SDR))) +#define PB_SSR (*((volatile Word *) SA1111_p2v (_PB_SSR))) +#define PC_DDR (*((volatile Word *) SA1111_p2v (_PC_DDR))) +#define PC_DRR (*((volatile Word *) SA1111_p2v (_PC_DRR))) +#define PC_DWR (*((volatile Word *) SA1111_p2v (_PC_DWR))) +#define PC_SDR (*((volatile Word *) SA1111_p2v (_PC_SDR))) +#define PC_SSR (*((volatile Word *) SA1111_p2v (_PC_SSR))) + +#endif /* LANGUAGE == C */ + +/* + * Interrupt Controller + * + * Registers + * INTTEST0 Test register 0 + * INTTEST1 Test register 1 + * INTEN0 Interrupt Enable register 0 + * INTEN1 Interrupt Enable register 1 + * INTPOL0 Interrupt Polarity selection 0 + * INTPOL1 Interrupt Polarity selection 1 + * INTTSTSEL Interrupt source selection + * INTSTATCLR0 Interrupt Status/Clear 0 + * INTSTATCLR1 Interrupt Status/Clear 1 + * INTSET0 Interrupt source set 0 + * INTSET1 Interrupt source set 1 + * WAKE_EN0 Wake-up source enable 0 + * WAKE_EN1 Wake-up source enable 1 + * WAKE_POL0 Wake-up polarity selection 0 + * WAKE_POL1 Wake-up polarity selection 1 + */ + +#define _INTTEST0 _SA1111( 0x1600 ) +#define _INTTEST1 _SA1111( 0x1604 ) +#define _INTEN0 _SA1111( 0x1608 ) +#define _INTEN1 _SA1111( 0x160c ) +#define _INTPOL0 _SA1111( 0x1610 ) +#define _INTPOL1 _SA1111( 0x1614 ) +#define _INTTSTSEL _SA1111( 0x1618 ) +#define _INTSTATCLR0 _SA1111( 0x161c ) +#define _INTSTATCLR1 _SA1111( 0x1620 ) +#define _INTSET0 _SA1111( 0x1624 ) +#define _INTSET1 _SA1111( 0x1628 ) +#define _WAKE_EN0 _SA1111( 0x162c ) +#define _WAKE_EN1 _SA1111( 0x1630 ) +#define _WAKE_POL0 _SA1111( 0x1634 ) +#define _WAKE_POL1 _SA1111( 0x1638 ) + +#if LANGUAGE == C + +#define INTTEST0 (*((volatile Word *) SA1111_p2v (_INTTEST0))) +#define INTTEST1 (*((volatile Word *) SA1111_p2v (_INTTEST1))) +#define INTEN0 (*((volatile Word *) SA1111_p2v (_INTEN0))) +#define INTEN1 (*((volatile Word *) SA1111_p2v (_INTEN1))) +#define INTPOL0 (*((volatile Word *) SA1111_p2v (_INTPOL0))) +#define INTPOL1 (*((volatile Word *) SA1111_p2v (_INTPOL1))) +#define INTTSTSEL (*((volatile Word *) SA1111_p2v (_INTTSTSEL))) +#define INTSTATCLR0 (*((volatile Word *) SA1111_p2v (_INTSTATCLR0))) +#define INTSTATCLR1 (*((volatile Word *) SA1111_p2v (_INTSTATCLR1))) +#define INTSET0 (*((volatile Word *) SA1111_p2v (_INTSET0))) +#define INTSET1 (*((volatile Word *) SA1111_p2v (_INTSET1))) +#define WAKE_EN0 (*((volatile Word *) SA1111_p2v (_WAKE_EN0))) +#define WAKE_EN1 (*((volatile Word *) SA1111_p2v (_WAKE_EN1))) +#define WAKE_POL0 (*((volatile Word *) SA1111_p2v (_WAKE_POL0))) +#define WAKE_POL1 (*((volatile Word *) SA1111_p2v (_WAKE_POL1))) + +#endif /* LANGUAGE == C */ + +/* + * PCMCIA Interface + * + * Registers + * PCSR Status Register + * PCCR Control Register + * PCSSR Sleep State Register + */ + +#define _PCCR _SA1111( 0x1800 ) +#define _PCSSR _SA1111( 0x1804 ) +#define _PCSR _SA1111( 0x1808 ) + +#if LANGUAGE == C + +#define PCCR (*((volatile Word *) SA1111_p2v (_PCCR))) +#define PCSSR (*((volatile Word *) SA1111_p2v (_PCSSR))) +#define PCSR (*((volatile Word *) SA1111_p2v (_PCSR))) + +#endif /* LANGUAGE == C */ + +#define PCSR_S0_READY (1<<0) +#define PCSR_S1_READY (1<<1) +#define PCSR_S0_DETECT (1<<2) +#define PCSR_S1_DETECT (1<<3) +#define PCSR_S0_VS1 (1<<4) +#define PCSR_S0_VS2 (1<<5) +#define PCSR_S1_VS1 (1<<6) +#define PCSR_S1_VS2 (1<<7) +#define PCSR_S0_WP (1<<8) +#define PCSR_S1_WP (1<<9) +#define PCSR_S0_BVD1 (1<<10) +#define PCSR_S0_BVD2 (1<<11) +#define PCSR_S1_BVD1 (1<<12) +#define PCSR_S1_BVD2 (1<<13) + +#define PCCR_S0_RST (1<<0) +#define PCCR_S1_RST (1<<1) +#define PCCR_S0_FLT (1<<2) +#define PCCR_S1_FLT (1<<3) +#define PCCR_S0_PWAITEN (1<<4) +#define PCCR_S1_PWAITEN (1<<5) +#define PCCR_S0_PSE (1<<6) +#define PCCR_S1_PSE (1<<7) + +#define PCSSR_S0_SLEEP (1<<0) +#define PCSSR_S1_SLEEP (1<<1) + +#endif /* _ASM_ARCH_SA1111 */ diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h new file mode 100644 index 000000000..a7f590306 --- /dev/null +++ b/include/asm-arm/arch-sa1100/bitfield.h @@ -0,0 +1,123 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + + +#ifndef BITFIELD +#define BITFIELD + +#ifndef LANGUAGE +#define LANGUAGE C +#endif /* !defined (LANGUAGE) */ + +#define C 0 +#define Assembly 1 + +#if LANGUAGE == C +#define UData(Data) ((unsigned int) (Data)) +#elif LANGUAGE == Assembly +#define UData(Data) (Data) +#endif /* LANGUAGE == C || LANGUAGE == Assembly */ + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#undef C +#undef Assembly + +#endif /* !defined (BITFIELD) */ diff --git a/include/asm-arm/arch-sa1100/bitsy.h b/include/asm-arm/arch-sa1100/bitsy.h new file mode 100644 index 000000000..42c178f58 --- /dev/null +++ b/include/asm-arm/arch-sa1100/bitsy.h @@ -0,0 +1,45 @@ +#ifndef _INCLUDE_BITSY_H_ +#define _INCLUDE_BITSY_H_ + +#define GPIO_BITSY_PCMCIA_CD0 GPIO_GPIO (17) +#define GPIO_BITSY_PCMCIA_CD1 GPIO_GPIO (10) +#define GPIO_BITSY_PCMCIA_IRQ0 GPIO_GPIO (21) +#define GPIO_BITSY_PCMCIA_IRQ1 GPIO_GPIO (11) + +/* audio sample rate clock generator */ +#define GPIO_BITSY_CLK_SET0 GPIO_GPIO (12) +#define GPIO_BITSY_CLK_SET1 GPIO_GPIO (13) +/* UDA1341 L3 Interface */ +#define GPIO_BITSY_L3_DATA GPIO_GPIO (14) +#define GPIO_BITSY_L3_CLOCK GPIO_GPIO (16) +#define GPIO_BITSY_L3_MODE GPIO_GPIO (15) + + +#define IRQ_GPIO_BITSY_PCMCIA_CD0 IRQ_GPIO17 +#define IRQ_GPIO_BITSY_PCMCIA_CD1 IRQ_GPIO10 +#define IRQ_GPIO_BITSY_PCMCIA_IRQ0 IRQ_GPIO21 +#define IRQ_GPIO_BITSY_PCMCIA_IRQ1 IRQ_GPIO22 + +#define EGPIO_BITSY_VPP_ON (1 << 0) +#define EGPIO_BITSY_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ +#define EGPIO_BITSY_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ +#define EGPIO_BITSY_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ +#define EGPIO_BITSY_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ +#define EGPIO_BITSY_OPT_ON (1 << 5) /* full power to option pack. active high. */ +#define EGPIO_BITSY_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ +#define EGPIO_BITSY_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ +#define EGPIO_BITSY_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ +#define EGPIO_BITSY_IR_ON (1 << 9) /* apply power to IR module. active high. */ +#define EGPIO_BITSY_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ +#define EGPIO_BITSY_AUD_PWR_ON (1 << 11) /* apply poewr to reset of audio circuit. active high. */ +#define EGPIO_BITSY_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ +#define EGPIO_BITSY_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ +#define EGPIO_BITSY_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ +#define EGPIO_BITSY_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ + +#ifndef __ASSEMBLY__ +extern void clr_bitsy_egpio(unsigned long x); +extern void set_bitsy_egpio(unsigned long x); +#endif + +#endif diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h index 4aabcaf32..cd110f1fb 100644 --- a/include/asm-arm/arch-sa1100/dma.h +++ b/include/asm-arm/arch-sa1100/dma.h @@ -1,3 +1,6 @@ +/* + * linux/include/asm-arm/arch-sa1100/dma.h + */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h index 3b9ba67b5..8f9a13152 100644 --- a/include/asm-arm/arch-sa1100/hardware.h +++ b/include/asm-arm/arch-sa1100/hardware.h @@ -81,6 +81,10 @@ extern void set_GPIO_IRQ_edge( int gpio_mask, int edge_mask ); #include "empeg.h" #endif +#ifdef CONFIG_SA1100_BITSY +#include "bitsy.h" +#endif + #if defined(CONFIG_SA1100_GRAPHICSCLIENT) || defined(CONFIG_SA1100_THINCLIENT) #include "thinclient.h" #endif diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h index 3a9935c0b..63cdc6833 100644 --- a/include/asm-arm/arch-sa1100/ide.h +++ b/include/asm-arm/arch-sa1100/ide.h @@ -21,36 +21,59 @@ ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq) { ide_ioreg_t reg; int i; + int ioshift = 0; + /* The Empeg board has the first two address lines unused */ + if (machine_is_empeg()) + ioshift = 2; + memset(hw, 0, sizeof(*hw)); -#ifdef CONFIG_SA1100_EMPEG -/* The Empeg board has the first two address lines unused */ -#define IO_SHIFT 2 -#else -#define IO_SHIFT 0 -#endif - - reg = (ide_ioreg_t) (data_port << IO_SHIFT); + reg = (ide_ioreg_t) (data_port << ioshift); for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { hw->io_ports[i] = reg; - reg += (1 << IO_SHIFT); + reg += (1 << ioshift); } - hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) (ctrl_port << IO_SHIFT); + + hw->io_ports[IDE_CONTROL_OFFSET] = + (ide_ioreg_t) (ctrl_port << ioshift); + if (irq) *irq = 0; } /* + * Special case for the empeg board which has the first two + * address lines unused + */ +static __inline__ void +empeg_ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port) +{ + ide_ioreg_t reg; + int i; + + memset(hw, 0, sizeof(*hw)); + + reg = (ide_ioreg_t) (0xe0000000 + (data_port << 2)); + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += (1 << 2); + } + hw->io_ports[IDE_CONTROL_OFFSET] = + (ide_ioreg_t) (0xe0000000 + (ctrl_port << 2)); +} + +/* * This registers the standard ports for this architecture with the IDE * driver. */ static __inline__ void ide_init_default_hwifs(void) { + if( machine_is_empeg() ){ +#ifdef CONFIG_SA1100_EMPEG hw_regs_t hw; -#if defined( CONFIG_SA1100_EMPEG ) /* First, do the SA1100 setup */ /* PCMCIA IO space */ @@ -61,41 +84,40 @@ ide_init_default_hwifs(void) /* Interrupts on rising edge: lines are inverted before they get to the SA */ - GRER&=~(EMPEG_IDE1IRQ|EMPEG_IDE2IRQ); - GFER|=(EMPEG_IDE1IRQ|EMPEG_IDE2IRQ); + set_GPIO_IRQ_edge( (EMPEG_IDE1IRQ|EMPEG_IDE2IRQ), GPIO_FALLING_EDGE ); /* Take hard drives out of reset */ GPSR=(EMPEG_IDERESET); - /* Clear GEDR */ - GEDR=0xffffffff; - /* Sonja and her successors have two IDE ports. */ /* MAC 23/4/1999, swap these round so that the left hand hard disk is hda when viewed from the front. This doesn't match the silkscreen however. */ - ide_init_hwif_ports(&hw,0x10,0x1e,NULL); + empeg_ide_init_hwif_ports(&hw,0x10,0x1e); hw.irq = EMPEG_IRQ_IDE2; ide_register_hw(&hw, NULL); - ide_init_hwif_ports(&hw,0x00,0x0e,NULL); - hw.irq = EMPEG_IRQ_IDE1; + empeg_ide_init_hwif_ports(&hw,0x00,0x0e); + hw.irq = ,EMPEG_IRQ_IDE1; ide_register_hw(&hw, NULL); +#endif + } + + else if( machine_is_victor() ){ +#ifdef CONFIG_SA1100_VICTOR + hw_regs_t hw; -#elif defined( CONFIG_SA1100_VICTOR ) /* Enable appropriate GPIOs as interrupt lines */ GPDR &= ~GPIO_GPIO7; - GRER |= GPIO_GPIO7; - GFER &= ~GPIO_GPIO7; - GEDR = GPIO_GPIO7; + set_GPIO_IRQ_edge( GPIO_GPIO7, GPIO_RISING_EDGE ); + /* set the pcmcia interface timing */ MECR = 0x00060006; - ide_init_hwif_ports(&hw, 0x1f0, 0x3f6, NULL); + ide_init_hwif_ports(&hw, 0xe00001f0, 0xe00003f6, NULL); hw.irq = IRQ_GPIO7; ide_register_hw(&hw, NULL); -#else -#error Missing IDE interface definition in include/asm/arch/ide.h #endif + } } #endif diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h index d1d8aa11a..9a955de6c 100644 --- a/include/asm-arm/arch-sa1100/io.h +++ b/include/asm-arm/arch-sa1100/io.h @@ -12,7 +12,13 @@ #define IO_SPACE_LIMIT 0xffffffff +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ #define __io_pci(a) (PCIO_BASE + (a)) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) ((unsigned long)(a)) #define __ioaddr(p) __io_pci(p) @@ -49,4 +55,6 @@ extern __inline__ void __arch_putw(unsigned int value, unsigned long a) #define outw(v,p) __arch_putw(v,__io_pci(p)) #define outl(v,p) __arch_putl(v,__io_pci(p)) +#define __arch_ioremap __ioremap + #endif diff --git a/include/asm-arm/arch-sa1100/irq.h b/include/asm-arm/arch-sa1100/irq.h index 2f1e63d82..6e24e97b1 100644 --- a/include/asm-arm/arch-sa1100/irq.h +++ b/include/asm-arm/arch-sa1100/irq.h @@ -143,7 +143,9 @@ static void sa1111_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs ) int i; unsigned long stat0, stat1; - while( (stat0 = INTSTATCLR0) && (stat1 = INTSTATCLR1) ){ + for(;;) { + stat0 = INTSTATCLR0, stat1 = INTSTATCLR1; + if( !stat0 && !stat1 ) break; if( stat0 ) for( i = 0; i < 32; i++ ) if( stat0 & (1<<i) ) diff --git a/include/asm-arm/arch-sa1100/keyboard.h b/include/asm-arm/arch-sa1100/keyboard.h index da214d3ed..84dd76454 100644 --- a/include/asm-arm/arch-sa1100/keyboard.h +++ b/include/asm-arm/arch-sa1100/keyboard.h @@ -39,10 +39,10 @@ extern unsigned char Brutus_kbd_sysrq_xlate[128]; #define kbd_getkeycode(x...) (-ENOSYS) #define kbd_translate(x...) (0) #define kbd_unexpected_up(x...) (1) -#define kbd_leds(x...) (0) -#define kbd_init_hw(x...) (0) -#define kbd_enable_irq(x...) (0) -#define kbd_disable_irq(x...) (0) +#define kbd_leds(x...) do { } while (0) +#define kbd_init_hw(x...) do { } while (0) +#define kbd_enable_irq(x...) do { } while (0) +#define kbd_disable_irq(x...) do { } while (0) #endif diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h index 3b56a4220..5f0febaaa 100644 --- a/include/asm-arm/arch-sa1100/system.h +++ b/include/asm-arm/arch-sa1100/system.h @@ -5,7 +5,7 @@ */ #include <linux/config.h> -extern __inline__ void arch_idle(void) +static void arch_idle(void) { while (!current->need_resched && !hlt_counter) { cpu_do_idle(IDLE_CLOCK_SLOW); @@ -16,16 +16,8 @@ extern __inline__ void arch_idle(void) #ifdef CONFIG_SA1100_VICTOR -extern inline void arch_power_off(void) -{ - /* switch off power supply */ - mdelay(2000); - GPCR = GPIO_GPIO23; - while(1); -} - /* power off unconditionally */ -#define arch_reset(x) arch_power_off() +#define arch_reset(x) machine_power_off() #else diff --git a/include/asm-arm/arch-sa1100/thinclient.h b/include/asm-arm/arch-sa1100/thinclient.h new file mode 100644 index 000000000..4c1846779 --- /dev/null +++ b/include/asm-arm/arch-sa1100/thinclient.h @@ -0,0 +1,89 @@ +/* + * linux/include/asm-arm/arch-sa1100/thinclient.h + * + * Created 2000/06/11 by Nicolas Pitre <nico@cam.org> + * + * This file contains the hardware specific definitions for the ADS + * ThinClient/GraphicsClient boards. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#error "include <asm/hardware.h> instead" +#endif + + +#define ADS_CPLD_BASE (0x10000000) +#define ADS_p2v( x ) ((x) - ADS_CPLD_BASE + 0xdc000000) +#define ADS_v2p( x ) ((x) - 0xdc000000 + ADS_CPLD_BASE) + + +/* Parallel Port */ + +#define _ADS_PPDR 0x10020000 /* parallel port data reg */ +#define _ADS_PPSR 0x10020004 /* parallel port status reg */ + + +/* PCMCIA */ + +#define _ADS_CS_STATUS 0x10040000 /* PCMCIA status reg */ +#define ADS_CS_ST_A_READY (1 << 0) /* Socket A Card Ready */ +#define ADS_CS_ST_B_READY (1 << 1) /* Socket B Card Ready */ +#define ADS_CS_ST_A_CD (1 << 2) /* Socket A Card Detect */ +#define ADS_CS_ST_B_CD (1 << 3) /* Socket B Card Detect */ +#define ADS_CS_ST_A_BUSY (1 << 4) /* Socket A Card Busy */ +#define ADS_CS_ST_B_BUSY (1 << 5) /* Socket B Card Busy */ +#define ADS_CS_ST_A_STS (1 << 6) /* Socket A Card STS */ +#define ADS_CS_ST_B_STS (1 << 7) /* Socket B Card STS */ + +#define _ADS_CS_PR 0x10040004 /* PCMCIA Power/Reset */ +#define ADS_CS_PR_A_POWER (1 << 0) /* Socket A Enable Power */ +#define ADS_CS_PR_B_POWER (1 << 1) /* Socket B Enable Power */ +#define ADS_CS_PR_A_RESET (1 << 2) /* Socket A Reset */ +#define ADS_CS_PR_B_RESET (1 << 3) /* Socket B Reset */ + + +#define _ADS_SW_SWITCHES 0x10060000 /* Software Switches */ + + +/* Extra IRQ Controller */ + +#define _ADS_INT_ST1 0x10080000 /* IRQ Status #1 */ +#define _ADS_INT_ST2 0x10080004 /* IRQ Status #2 */ +#define _ADS_INT_EN1 0x10080008 /* IRQ Enable #1 */ +#define _ADS_INT_EN2 0x1008000c /* IRQ Enable #2 */ + + +/* On-Board Ethernet */ + +#define _ADS_ETHERNET 0x100e0000 /* Ethernet */ + + +/* Extra UARTs */ + +#define _ADS_UARTA 0x10100000 /* UART A */ +#define _ADS_UARTB 0x10120000 /* UART B */ +#define _ADS_UARTC 0x10140000 /* UART C */ +#define _ADS_UARTD 0x10160000 /* UART D */ + + +/* LEDs */ + +#define ADS_LED0 GPIO_GPIO20 /* on-board D22 */ +#define ADS_LED1 GPIO_GPIO21 /* on-board D21 */ +#define ADS_LED2 GPIO_GPIO22 /* on-board D20 */ +#define ADS_LED3 GPIO_GPIO23 /* external */ +#define ADS_LED4 GPIO_GPIO24 /* external */ +#define ADS_LED5 GPIO_GPIO25 /* external */ +#define ADS_LED6 GPIO_GPIO26 /* external */ +#define ADS_LED7 GPIO_GPIO27 /* external */ + + +/* Virtual register addresses */ + +#ifndef __ASSEMBLY__ +#define ADS_INT_ST1 (*((volatile u_char *) ADS_p2v(_ADS_INT_ST1))) +#define ADS_INT_ST2 (*((volatile u_char *) ADS_p2v(_ADS_INT_ST2))) +#define ADS_INT_EN1 (*((volatile u_char *) ADS_p2v(_ADS_INT_EN1))) +#define ADS_INT_EN2 (*((volatile u_char *) ADS_p2v(_ADS_INT_EN2))) +#define ADS_ETHERNET ((int) ADS_p2v(_ADS_ETHERNET)) +#endif diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h index 69b3140d3..7f9359782 100644 --- a/include/asm-arm/arch-sa1100/uncompress.h +++ b/include/asm-arm/arch-sa1100/uncompress.h @@ -9,6 +9,13 @@ #include "hardware.h" #include "serial_reg.h" +/* Assabet's Status Control "Register" */ +unsigned long SCR_value; + +/* sa1100_setup() will perform any special initialization for UART, etc. */ +extern void sa1100_setup( int arch_id ); +#define arch_decomp_setup() sa1100_setup(arch_id) + /* * The following code assumes the serial port has already been * initialized by the bootloader or such... @@ -18,7 +25,7 @@ static void puts( const char *s ) volatile unsigned long *serial_port; if (machine_is_assabet()) { - if (0/*SA1111 connected*/) + if( machine_has_neponset() ) serial_port = (unsigned long *)_Ser3UTCR0; else serial_port = (unsigned long *)_Ser1UTCR0; @@ -48,5 +55,4 @@ static void puts( const char *s ) /* * Nothing to do for these */ -#define arch_decomp_setup() #define arch_decomp_wdog() diff --git a/include/asm-arm/arch-shark/system.h b/include/asm-arm/arch-shark/system.h index b0d34e811..cefb21609 100644 --- a/include/asm-arm/arch-shark/system.h +++ b/include/asm-arm/arch-shark/system.h @@ -1,12 +1,12 @@ /* - * linux/include/asm-arm/arch-ebsa110/system.h + * linux/include/asm-arm/arch-shark/system.h * * Copyright (c) 1996-1998 Russell King. */ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -extern __inline__ void arch_reset(char mode) +static void arch_reset(char mode) { /* * loop endlessly @@ -14,8 +14,8 @@ extern __inline__ void arch_reset(char mode) cli(); } -#define arch_power_off() do { } while (0) -#define arch_do_idle() do {} while (0) -/*cpu_do_idle()*/ +static void arch_idle(void) +{ +} #endif diff --git a/include/asm-arm/dec21285.h b/include/asm-arm/dec21285.h index 39184ef9a..dd49f6416 100644 --- a/include/asm-arm/dec21285.h +++ b/include/asm-arm/dec21285.h @@ -94,18 +94,6 @@ #define footbridge_cfn_mode() (0) #endif -/* - * footbridge_cfn_mode() is used when we want - * to check whether we are the central function - */ -#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN) -#define footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN) -#elif defined(CONFIG_FOOTBRIDGE_HOST) -#define footbridge_cfn_mode() (1) -#else -#define footbridge_cfn_mode() (0) -#endif - #define CSR_PCIADDR_EXTN DC21285_IO(0x0140) #define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144) #define CSR_XBUS_CYCLE DC21285_IO(0x0148) diff --git a/include/asm-arm/dma.h b/include/asm-arm/dma.h index 67db9ab90..ed2d9627b 100644 --- a/include/asm-arm/dma.h +++ b/include/asm-arm/dma.h @@ -27,8 +27,6 @@ typedef struct { unsigned long length; } dmasg_t; -extern const char dma_str[]; - extern spinlock_t dma_spin_lock; extern __inline__ unsigned long claim_dma_lock(void) @@ -45,9 +43,6 @@ extern __inline__ void release_dma_lock(unsigned long flags) /* Clear the 'DMA Pointer Flip Flop'. * Write 0 for LSB/MSB, 1 for MSB/LSB access. - * - * NOTE: This is an architecture specific function, and should - * be hidden from the drivers. */ #define clear_dma_ff(channel) @@ -56,10 +51,7 @@ extern __inline__ void release_dma_lock(unsigned long flags) * NOTE: This is an architecture specific function, and should * be hidden from the drivers */ -extern __inline__ void set_dma_page(dmach_t channel, char pagenr) -{ - printk(dma_str, "set_dma_page", channel); -} +extern void set_dma_page(dmach_t channel, char pagenr); /* Request a DMA channel * diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 94073475d..c7f71bb14 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -34,9 +34,9 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_SHARK 15 #define MACH_TYPE_BRUTUS 16 #define MACH_TYPE_PERSONAL_SERVER 17 -#define MACH_TYPE_SA1100 18 /* unused/too general */ +#define MACH_TYPE_ITSY 18 #define MACH_TYPE_L7200 19 -#define MACH_TYPE_SA1110 20 /* unused/too general */ +/* 20 is free - contact rmk@arm.linux.org.uk directly if you wish to use this number */ #define MACH_TYPE_INTEGRATOR 21 #define MACH_TYPE_BITSY 22 #define MACH_TYPE_IXP1200 23 @@ -209,6 +209,18 @@ extern unsigned int __machine_arch_type; # define machine_is_personal_server() (0) #endif +#ifdef CONFIG_SA1100_ITSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITSY +# endif +# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) +#else +# define machine_is_itsy() (0) +#endif + #ifdef CONFIG_ARCH_L7200 # ifdef machine_arch_type # undef machine_arch_type @@ -310,18 +322,6 @@ extern unsigned int __machine_arch_type; /* * The following are currently unregistered */ -#ifdef CONFIG_SA1100_ITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITSY -# endif -# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) -#else -# define machine_is_itsy() (0) -#endif - #ifdef CONFIG_SA1100_EMPEG # ifdef machine_arch_type # undef machine_arch_type diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h index 3e4912a5c..2ff6723d8 100644 --- a/include/asm-arm/unaligned.h +++ b/include/asm-arm/unaligned.h @@ -3,46 +3,112 @@ #include <linux/types.h> -#define get_unaligned(ptr) \ - ((__typeof__(*(ptr)))__get_unaligned_size((ptr), sizeof(*(ptr)))) - -#define put_unaligned(val, ptr) \ - __put_unaligned_size((unsigned long)(val), (ptr), sizeof(*(ptr))) +extern int __bug_unaligned_x(void *ptr); /* - * We use a similar method to the uaccess.h badness detection. + * What is the most efficient way of loading/storing an unaligned value? + * + * That is the subject of this file. Efficiency here is defined as + * minimum code size with minimum register usage for the common cases. + * It is currently not believed that long longs are common, so we + * trade efficiency for the chars, shorts and longs against the long + * longs. + * + * Current stats with gcc 2.7.2.2 for these functions: + * + * ptrsize get: code regs put: code regs + * 1 1 1 1 2 + * 2 3 2 3 2 + * 4 7 3 7 3 + * 8 20 6 16 6 + * + * gcc 2.95.1 seems to code differently: * - * These are actually never defined anywhere, and therefore - * catch errors at compile/link time. Don't be tempted to - * provide a declaration for them; doing so will mask the - * errors. + * ptrsize get: code regs put: code regs + * 1 1 1 1 2 + * 2 3 2 3 2 + * 4 7 4 7 4 + * 8 19 8 15 6 + * + * which may or may not be more efficient (depending upon whether + * you can afford the extra registers). Hopefully the gcc 2.95 + * is inteligent enough to decide if it is better to use the + * extra register, but evidence so far seems to suggest otherwise. + * + * Unfortunately, gcc is not able to optimise the high word + * out of long long >> 32, or the low word from long long << 32 */ -extern unsigned long __get_unaligned_bad(void); -extern void __put_unaligned_bad(void); -extern __inline__ unsigned long __get_unaligned_size(const void *ptr, size_t size) +#define __get_unaligned_2(__p) \ + (__p[0] | __p[1] << 8) + +#define __get_unaligned_4(__p) \ + (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24) + +#define get_unaligned(ptr) \ + ({ \ + __typeof__(*(ptr)) __v; \ + __u8 *__p = (__u8 *)(ptr); \ + switch (sizeof(*(ptr))) { \ + case 1: __v = *(ptr); break; \ + case 2: __v = __get_unaligned_2(__p); break; \ + case 4: __v = __get_unaligned_4(__p); break; \ + case 8: { \ + unsigned int __v1, __v2; \ + __v2 = __get_unaligned_4((__p+4)); \ + __v1 = __get_unaligned_4(__p); \ + __v = ((unsigned long long)__v2 << 32 | __v1); \ + } \ + break; \ + default: __v = __bug_unaligned_x(__p); break; \ + } \ + __v; \ + }) + + +static inline void __put_unaligned_2(__u32 __v, register __u8 *__p) +{ + *__p++ = __v; + *__p++ = __v >> 8; +} + +static inline void __put_unaligned_4(__u32 __v, register __u8 *__p) { - const unsigned char *p = (const unsigned char *)ptr; - unsigned long val = 0; - - switch (size) { - case 4: val = p[2] << 16 | p[3] << 24; - case 2: val |= p[1] << 8; - case 1: val |= p[0]; break; - default: val = __get_unaligned_bad(); break; - } - return val; + __put_unaligned_2(__v >> 16, __p + 2); + __put_unaligned_2(__v, __p); } -extern __inline__ void __put_unaligned_size(unsigned long val, void *ptr, size_t size) +static inline void __put_unaligned_8(const unsigned long long __v, register __u8 *__p) { - switch (size) { - case 4: ((unsigned char *)ptr)[3] = val >> 24; - ((unsigned char *)ptr)[2] = val >> 16; - case 2: ((unsigned char *)ptr)[1] = val >> 8; - case 1: ((unsigned char *)ptr)[0] = val; break; - default: __put_unaligned_bad(); break; - } + /* + * tradeoff: 8 bytes of stack for all unaligned puts (2 + * instructions), or an extra register in the long long + * case - go for the extra register. + */ + __put_unaligned_4(__v >> 32, __p+4); + __put_unaligned_4(__v, __p); } +/* + * Try to store an unaligned value as efficiently as possible. + */ +#define put_unaligned(val,ptr) \ + ({ \ + switch (sizeof(*(ptr))) { \ + case 1: \ + *(ptr) = (val); \ + break; \ + case 2: __put_unaligned_2((val),(__u8 *)(ptr)); \ + break; \ + case 4: __put_unaligned_4((val),(__u8 *)(ptr)); \ + break; \ + case 8: __put_unaligned_8((val),(__u8 *)(ptr)); \ + break; \ + default: __bug_unaligned_x(ptr); \ + break; \ + } \ + (void) 0; \ + }) + + #endif |