Merge with 2.3.99-pre6.

31 files changed, 431 insertions, 503 deletions

diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h
index 5230bcc15..43a44f4ad 100644
--- a/include/asm-ia64/atomic.h
+++ b/include/asm-ia64/atomic.h
@@ -44,7 +44,7 @@ ia64_atomic_add (int i, atomic_t *v)
 		CMPXCHG_BUGCHECK(v);
 		old = atomic_read(v);
 		new = old + i;
-	} while (ia64_cmpxchg(v, old, old + i, sizeof(atomic_t)) != old);
+	} while (ia64_cmpxchg("acq", v, old, old + i, sizeof(atomic_t)) != old);
 	return new;
 }
 
@@ -58,7 +58,7 @@ ia64_atomic_sub (int i, atomic_t *v)
 		CMPXCHG_BUGCHECK(v);
 		old = atomic_read(v);
 		new = old - i;
-	} while (ia64_cmpxchg(v, old, new, sizeof(atomic_t)) != old);
+	} while (ia64_cmpxchg("acq", v, old, new, sizeof(atomic_t)) != old);
 	return new;
 }
 
diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h
index c10d745e7..13b9dcbdc 100644
--- a/include/asm-ia64/bitops.h
+++ b/include/asm-ia64/bitops.h
@@ -33,7 +33,7 @@ set_bit (int nr, volatile void *addr)
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old | bit;
-	} while (cmpxchg(m, old, new) != old);
+	} while (cmpxchg_acq(m, old, new) != old);
 }
 
 extern __inline__ void
@@ -49,7 +49,7 @@ clear_bit (int nr, volatile void *addr)
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old & mask;
-	} while (cmpxchg(m, old, new) != old);
+	} while (cmpxchg_acq(m, old, new) != old);
 }
 
 extern __inline__ void
@@ -65,7 +65,7 @@ change_bit (int nr, volatile void *addr)
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old ^ bit;
-	} while (cmpxchg(m, old, new) != old);
+	} while (cmpxchg_acq(m, old, new) != old);
 }
 
 extern __inline__ int
@@ -81,7 +81,7 @@ test_and_set_bit (int nr, volatile void *addr)
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old | bit;
-	} while (cmpxchg(m, old, new) != old);
+	} while (cmpxchg_acq(m, old, new) != old);
 	return (old & bit) != 0;
 }
 
@@ -98,7 +98,7 @@ test_and_clear_bit (int nr, volatile void *addr)
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old & mask;
-	} while (cmpxchg(m, old, new) != old);
+	} while (cmpxchg_acq(m, old, new) != old);
 	return (old & ~mask) != 0;
 }
 
@@ -115,7 +115,7 @@ test_and_change_bit (int nr, volatile void *addr)
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old ^ bit;
-	} while (cmpxchg(m, old, new) != old);
+	} while (cmpxchg_acq(m, old, new) != old);
 	return (old & bit) != 0;
 }
 
diff --git a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
index aa1040e13..15035374f 100644
--- a/include/asm-ia64/cache.h
+++ b/include/asm-ia64/cache.h
@@ -1,12 +1,28 @@
 #ifndef _ASM_IA64_CACHE_H
 #define _ASM_IA64_CACHE_H
 
+#include <linux/config.h>
+
 /*
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 /* Bytes per L1 (data) cache line.  */
-#define L1_CACHE_BYTES		64
+#define LOG_L1_CACHE_BYTES	6
+#define L1_CACHE_BYTES		(1 << LOG_L1_CACHE_BYTES)
+
+#ifdef CONFIG_SMP
+# define SMP_LOG_CACHE_BYTES	LOG_L1_CACHE_BYTES
+# define SMP_CACHE_BYTES	L1_CACHE_BYTES
+#else
+  /*
+   * The "aligned" directive can only _increase_ alignment, so this is
+   * safe and provides an easy way to avoid wasting space on a
+   * uni-processor:
+   */
+# define SMP_LOG_CACHE_BYTES	3
+# define SMP_CACHE_BYTES	(1 << 3)
+#endif
 
 #endif /* _ASM_IA64_CACHE_H */
diff --git a/include/asm-ia64/current.h b/include/asm-ia64/current.h
index 29aa54e6c..3d4f232f3 100644
--- a/include/asm-ia64/current.h
+++ b/include/asm-ia64/current.h
@@ -2,8 +2,8 @@
 #define _ASM_IA64_CURRENT_H
 
 /*
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 /* In kernel mode, thread pointer (r13) is used to point to the
diff --git a/include/asm-ia64/elf.h b/include/asm-ia64/elf.h
index 8176841d1..c0ae62524 100644
--- a/include/asm-ia64/elf.h
+++ b/include/asm-ia64/elf.h
@@ -82,8 +82,7 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
 #define ELF_PLATFORM	0
 
 #ifdef __KERNEL__
-# define SET_PERSONALITY(EX,IBCS2)				\
-	(current->personality = (IBCS2) ? PER_SVR4 : PER_LINUX)
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
 #endif
 
 #endif /* _ASM_IA64_ELF_H */
diff --git a/include/asm-ia64/hardirq.h b/include/asm-ia64/hardirq.h
index cd256f403..ab7dad947 100644
--- a/include/asm-ia64/hardirq.h
+++ b/include/asm-ia64/hardirq.h
@@ -54,8 +54,8 @@ extern irq_cpustat_t irq_stat[NR_CPUS];
 #include <asm/atomic.h>
 #include <asm/smp.h>
 
-extern unsigned char global_irq_holder;
-extern unsigned volatile int global_irq_lock;
+extern unsigned int global_irq_holder;
+extern volatile unsigned int global_irq_lock;
 
 static inline int irqs_running (void)
 {
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
index b897bea30..e4dd5c1ee 100644
--- a/include/asm-ia64/hw_irq.h
+++ b/include/asm-ia64/hw_irq.h
@@ -11,8 +11,7 @@
 #include <linux/types.h>
 
 #include <asm/ptrace.h>
-
-#define NR_ISA_IRQS	 16
+#include <asm/smp.h>
 
 /*
  * 0 special
@@ -42,6 +41,8 @@
 
 /* IA64 inter-cpu interrupt related definitions */
 
+#define IPI_DEFAULT_BASE_ADDR	0xfee00000
+
 /* Delivery modes for inter-cpu interrupts */
 enum {
         IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
@@ -57,20 +58,26 @@ enum {
 extern __u8 isa_irq_to_vector_map[16];
 #define isa_irq_to_vector(x)	isa_irq_to_vector_map[(x)]
 
-extern struct hw_interrupt_type irq_type_ia64_internal;	/* CPU-internal interrupt controller */
+extern unsigned long ipi_base_addr;
 
-extern void ipi_send (int cpu, int vector, int delivery_mode);
+extern struct hw_interrupt_type irq_type_ia64_sapic;	/* CPU-internal interrupt controller */
 
-#ifdef CONFIG_SMP
-extern void handle_IPI(int irq, void *dev_id, struct pt_regs *regs);
+extern void ipi_send (int cpu, int vector, int delivery_mode, int redirect);
 
 static inline void
-hw_resend_irq (struct hw_interrupt_type *h, unsigned int i)
+hw_resend_irq (struct hw_interrupt_type *h, unsigned int vector)
 {
-	send_IPI_self(i);
-}
+	int my_cpu_id;
+
+#ifdef CONFIG_SMP
+	my_cpu_id = smp_processor_id();
 #else
-# define hw_resend_irq(h,i)
+	__u64 lid;
+
+	__asm__ ("mov %0=cr.lid" : "=r"(lid));
+	my_cpu_id = (lid >> 24) & 0xff;		/* extract id (ignore eid) */
 #endif
+	ipi_send(my_cpu_id, vector, IA64_IPI_DM_INT, 0);
+}
 
 #endif /* _ASM_IA64_HW_IRQ_H */
diff --git a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h
index d76ce8b58..7870762ba 100644
--- a/include/asm-ia64/ia32.h
+++ b/include/asm-ia64/ia32.h
@@ -90,7 +90,7 @@ struct sigcontext_ia32 {
        unsigned int eflags;
        unsigned int esp_at_signal;
        unsigned short ss, __ssh;
-       struct _fpstate_ia32 * fpstate;
+       unsigned int fpstate;		/* really (struct _fpstate_ia32 *) */
        unsigned int oldmask;
        unsigned int cr2;
 };
@@ -221,8 +221,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #define ELF_PLATFORM	0
 
 #ifdef __KERNEL__
-# define SET_PERSONALITY(EX,IBCS2)				\
-	(current->personality = (IBCS2) ? PER_SVR4 : PER_LINUX)
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
 #endif
 
 #define IA32_EFLAG	0x200
@@ -288,9 +287,14 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  *  IA32 floating point control registers starting values
  */
 
-#define IA32_FSR_DEFAULT	0x555500000	/* set all tag bits */
+#define IA32_FSR_DEFAULT	0x55550000	/* set all tag bits */
 #define IA32_FCR_DEFAULT	0x33f		/* single precision, all masks */
 
+#define IA32_PTRACE_GETREGS	12
+#define IA32_PTRACE_SETREGS	13
+#define IA32_PTRACE_GETFPREGS	14
+#define IA32_PTRACE_SETFPREGS	15
+
 #define ia32_start_thread(regs,new_ip,new_sp) do {				\
 	set_fs(USER_DS);							\
 	ia64_psr(regs)->cpl = 3;	/* set user mode */			\
@@ -303,10 +307,11 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 } while (0)
 
 extern void ia32_gdt_init (void);
-extern long ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
+extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
 			       sigset_t *set, struct pt_regs *regs);
 extern void ia32_init_addr_space (struct pt_regs *regs);
 extern int ia32_setup_arg_pages (struct linux_binprm *bprm);
+extern int ia32_exception (struct pt_regs *regs, unsigned long isr);
 
 #endif /* !CONFIG_IA32_SUPPORT */
  
diff --git a/include/asm-ia64/ide.h b/include/asm-ia64/ide.h
index 023203dc3..4ea799861 100644
--- a/include/asm-ia64/ide.h
+++ b/include/asm-ia64/ide.h
@@ -15,6 +15,8 @@
 
 #include <linux/config.h>
 
+#include <linux/irq.h>
+
 #ifndef MAX_HWIFS
 # ifdef CONFIG_BLK_DEV_IDEPCI
 #define MAX_HWIFS	10
@@ -29,12 +31,12 @@ static __inline__ int
 ide_default_irq (ide_ioreg_t base)
 {
 	switch (base) {
-		case 0x1f0: return 14;
-		case 0x170: return 15;
-		case 0x1e8: return 11;
-		case 0x168: return 10;
-		case 0x1e0: return 8;
-		case 0x160: return 12;
+		case 0x1f0: return isa_irq_to_vector(14);
+		case 0x170: return isa_irq_to_vector(15);
+		case 0x1e8: return isa_irq_to_vector(11);
+		case 0x168: return isa_irq_to_vector(10);
+		case 0x1e0: return isa_irq_to_vector(8);
+		case 0x160: return isa_irq_to_vector(12);
 		default:
 			return 0;
 	}
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h
index ad532b26b..a371f1361 100644
--- a/include/asm-ia64/io.h
+++ b/include/asm-ia64/io.h
@@ -13,8 +13,8 @@
  * over and over again with slight variations and possibly making a
  * mistake somewhere.
  *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  */
@@ -253,66 +253,66 @@ __outsl (unsigned long port, void *src, unsigned long count)
 /*
  * The address passed to these functions are ioremap()ped already.
  */
-extern inline unsigned long
-__readb (unsigned long addr)
+extern inline unsigned char
+__readb (void *addr)
 {
 	return *(volatile unsigned char *)addr;
 }
 
-extern inline unsigned long
-__readw (unsigned long addr)
+extern inline unsigned short
+__readw (void *addr)
 {
 	return *(volatile unsigned short *)addr;
 }
 
-extern inline unsigned long
-__readl (unsigned long addr)
+extern inline unsigned int
+__readl (void *addr)
 {
 	return *(volatile unsigned int *) addr;
 }
 
 extern inline unsigned long
-__readq (unsigned long addr)
+__readq (void *addr)
 {
 	return *(volatile unsigned long *) addr;
 }
 
 extern inline void
-__writeb (unsigned char val, unsigned long addr)
+__writeb (unsigned char val, void *addr)
 {
 	*(volatile unsigned char *) addr = val;
 }
 
 extern inline void
-__writew (unsigned short val, unsigned long addr)
+__writew (unsigned short val, void *addr)
 {
 	*(volatile unsigned short *) addr = val;
 }
 
 extern inline void
-__writel (unsigned int val, unsigned long addr)
+__writel (unsigned int val, void *addr)
 {
 	*(volatile unsigned int *) addr = val;
 }
 
 extern inline void
-__writeq (unsigned long val, unsigned long addr)
+__writeq (unsigned long val, void *addr)
 {
 	*(volatile unsigned long *) addr = val;
 }
 
-#define readb		__readb
-#define readw		__readw
-#define readl		__readl
-#define readq		__readqq
+#define readb(a)	__readb((void *)(a))
+#define readw(a)	__readw((void *)(a))
+#define readl(a)	__readl((void *)(a))
+#define readq(a)	__readqq((void *)(a))
 #define __raw_readb	readb
 #define __raw_readw	readw
 #define __raw_readl	readl
 #define __raw_readq	readq
-#define writeb		__writeb
-#define writew		__writew
-#define writel		__writel
-#define writeq		__writeq
+#define writeb(v,a)	__writeb((v), (void *) (a))
+#define writew(v,a)	__writew((v), (void *) (a))
+#define writel(v,a)	__writel((v), (void *) (a))
+#define writeq(v,a)	__writeq((v), (void *) (a))
 #define __raw_writeb	writeb
 #define __raw_writew	writew
 #define __raw_writeq	writeq
diff --git a/include/asm-ia64/kdbsupport.h b/include/asm-ia64/kdbsupport.h
deleted file mode 100644
index beb846f79..000000000
--- a/include/asm-ia64/kdbsupport.h
+++ /dev/null
@@ -1,252 +0,0 @@
-#ifndef _ASM_IA64_KDBSUPPORT_H
-#define _ASM_IA64_KDBSUPPORT_H
-
-/*
- * Kernel Debugger Breakpoint Handler
- *
- * Copyright 1999, Silicon Graphics, Inc.
- *
- * Written March 1999 by Scott Lurndal at Silicon Graphics, Inc.
- */
-
-#include <asm/ptrace.h>
-
-	/*
-	 * This file provides definitions for functions that
-	 * are dependent upon the product into which  kdb is
-	 * linked. 
-	 *
-	 * This version is for linux.
-	 */
-typedef void (*handler_t)(struct pt_regs *);
-typedef unsigned long k_machreg_t;
-
-unsigned long show_cur_stack_frame(struct pt_regs *, int, unsigned long *) ;
-
-extern char*         kbd_getstr(char *, size_t, char *);
-extern int           kdbinstalltrap(int, handler_t, handler_t*);
-extern int           kdbinstalldbreg(kdb_bp_t *);
-extern void          kdbremovedbreg(kdb_bp_t *);
-extern void          kdb_initbptab(void);
-extern int	     kdbgetregcontents(const char *, struct pt_regs *, unsigned long *);
-extern int	     kdbsetregcontents(const char *, struct pt_regs *, unsigned long);
-extern int	     kdbdumpregs(struct pt_regs *, const char *, const char *);
-
-typedef int kdbintstate_t;
-	
-extern void	     kdb_disableint(kdbintstate_t *);
-extern void	     kdb_restoreint(kdbintstate_t *);
-
-extern k_machreg_t   kdb_getpc(struct pt_regs *);
-extern int	     kdb_setpc(struct pt_regs *, k_machreg_t);
-
-extern int	     kdb_putword(unsigned long, unsigned long);
-extern int	     kdb_getcurrentframe(struct pt_regs *);
-
-/*
- * kdb_db_trap is a processor dependent routine invoked
- * from kdb() via the #db trap handler.   It handles breakpoints involving
- * the processor debug registers and handles single step traps
- * using the processor trace flag.
- */
-
-#define KDB_DB_BPT	0	/* Straight breakpoint */
-#define KDB_DB_SS	1	/* Single Step trap */
-#define KDB_DB_SSB	2	/* Single Step, caller should continue */
-
-extern int 	     kdb_db_trap(struct pt_regs *, int);
-
-extern int	     kdb_allocdbreg(kdb_bp_t *);
-extern void          kdb_freedbreg(kdb_bp_t *);
-extern void	     kdb_initdbregs(void);
-
-extern void          kdb_setsinglestep(struct pt_regs *);
-
-	/*
-	 *  Support for ia32 architecture debug registers.
-	 */
-#define KDB_DBREGS	4	
-extern k_machreg_t dbregs[];
-
-#define DR6_BT  0x00008000
-#define DR6_BS	0x00004000
-#define DR6_BD  0x00002000
-
-#define DR6_B3  0x00000008
-#define DR6_B2	0x00000004
-#define DR6_B1  0x00000002
-#define DR6_B0	0x00000001
-
-#define DR7_RW_VAL(dr, drnum) \
-       (((dr) >> (16 + (4 * (drnum)))) & 0x3)
-
-#define DR7_RW_SET(dr, drnum, rw)                              \
-       do {                                                    \
-               (dr) &= ~(0x3 << (16 + (4 * (drnum))));         \
-               (dr) |= (((rw) & 0x3) << (16 + (4 * (drnum)))); \
-       } while (0)
-
-#define DR7_RW0(dr)       DR7_RW_VAL(dr, 0)
-#define DR7_RW0SET(dr,rw)  DR7_RW_SET(dr, 0, rw)
-#define DR7_RW1(dr)       DR7_RW_VAL(dr, 1)
-#define DR7_RW1SET(dr,rw)  DR7_RW_SET(dr, 1, rw)
-#define DR7_RW2(dr)       DR7_RW_VAL(dr, 2)
-#define DR7_RW2SET(dr,rw)  DR7_RW_SET(dr, 2, rw)
-#define DR7_RW3(dr)       DR7_RW_VAL(dr, 3)
-#define DR7_RW3SET(dr,rw)  DR7_RW_SET(dr, 3, rw)
-
-
-#define DR7_LEN_VAL(dr, drnum) \
-       (((dr) >> (18 + (4 * (drnum)))) & 0x3)
-
-#define DR7_LEN_SET(dr, drnum, rw)                             \
-       do {                                                    \
-               (dr) &= ~(0x3 << (18 + (4 * (drnum))));         \
-               (dr) |= (((rw) & 0x3) << (18 + (4 * (drnum)))); \
-       } while (0)
-
-#define DR7_LEN0(dr)        DR7_LEN_VAL(dr, 0)
-#define DR7_LEN0SET(dr,len)  DR7_LEN_SET(dr, 0, len)
-#define DR7_LEN1(dr)        DR7_LEN_VAL(dr, 1)
-#define DR7_LEN1SET(dr,len)  DR7_LEN_SET(dr, 1, len)
-#define DR7_LEN2(dr)        DR7_LEN_VAL(dr, 2)
-#define DR7_LEN2SET(dr,len)  DR7_LEN_SET(dr, 2, len)
-#define DR7_LEN3(dr)        DR7_LEN_VAL(dr, 3)
-#define DR7_LEN3SET(dr,len)  DR7_LEN_SET(dr, 3, len)
-
-#define DR7_G0(dr)    (((dr)>>1)&0x1)
-#define DR7_G0SET(dr) ((dr) |= 0x2)
-#define DR7_G0CLR(dr) ((dr) &= ~0x2)
-#define DR7_G1(dr)    (((dr)>>3)&0x1)
-#define DR7_G1SET(dr) ((dr) |= 0x8)
-#define DR7_G1CLR(dr) ((dr) &= ~0x8)
-#define DR7_G2(dr)    (((dr)>>5)&0x1)
-#define DR7_G2SET(dr) ((dr) |= 0x20)
-#define DR7_G2CLR(dr) ((dr) &= ~0x20)
-#define DR7_G3(dr)    (((dr)>>7)&0x1)
-#define DR7_G3SET(dr) ((dr) |= 0x80)
-#define DR7_G3CLR(dr) ((dr) &= ~0x80)
-
-#define DR7_L0(dr)    (((dr))&0x1)
-#define DR7_L0SET(dr) ((dr) |= 0x1)
-#define DR7_L0CLR(dr) ((dr) &= ~0x1)
-#define DR7_L1(dr)    (((dr)>>2)&0x1)
-#define DR7_L1SET(dr) ((dr) |= 0x4)
-#define DR7_L1CLR(dr) ((dr) &= ~0x4)
-#define DR7_L2(dr)    (((dr)>>4)&0x1)
-#define DR7_L2SET(dr) ((dr) |= 0x10)
-#define DR7_L2CLR(dr) ((dr) &= ~0x10)
-#define DR7_L3(dr)    (((dr)>>6)&0x1)
-#define DR7_L3SET(dr) ((dr) |= 0x40)
-#define DR7_L3CLR(dr) ((dr) &= ~0x40)
-
-#define DR7_GD		0x00002000		/* General Detect Enable */
-#define DR7_GE		0x00000200		/* Global exact */
-#define DR7_LE		0x00000100		/* Local exact */
-
-extern k_machreg_t kdb_getdr6(void);
-extern void kdb_putdr6(k_machreg_t);
-
-extern k_machreg_t kdb_getdr7(void);
-extern void kdb_putdr7(k_machreg_t);
-
-extern k_machreg_t kdb_getdr(int);
-extern void kdb_putdr(int, k_machreg_t);
-
-extern k_machreg_t kdb_getcr(int);
-
-extern void kdb_bp_install(void);
-extern void kdb_bp_remove(void);
-
-/*
- * Support for setjmp/longjmp
- */
-#define JB_BX   0
-#define JB_SI   1
-#define JB_DI   2
-#define JB_BP   3
-#define JB_SP   4
-#define JB_PC   5
-
-typedef struct __kdb_jmp_buf {
-	unsigned long   regs[6];
-} kdb_jmp_buf;
-
-extern int kdb_setjmp(kdb_jmp_buf *);
-extern void kdb_longjmp(kdb_jmp_buf *, int);
-
-extern kdb_jmp_buf  kdbjmpbuf;
-
-#define getprsregs(regs)	((struct switch_stack *)regs -1)
-
-#define BITMASK(bp,value)  (value << bp)
-
-/* bkpt support using break inst instead of IBP reg */
-
-/*
- * Define certain specific instructions
- */
-#define BREAK_INSTR             (0x00000080100L << 11)
-#define INST_SLOT0_MASK         (0x1ffffffffffL << 5)
-
-#if 0
-#define MAX_BREAKPOINTS         40
-#define PSR_SS                  40
-#endif
-
-/**
- * IA-64 instruction format structures
- */
-typedef union bundle {
-        struct {
-                long    low8;
-                long    high8;
-        } lform;
-        struct {
-                int     low_low4;
-                int     low_high4;
-                long    high8;
-        } iform;
-} bundle_t;
-
-#define BKPTMODE_DATAR	3
-#define BKPTMODE_IO   	2
-#define BKPTMODE_DATAW	1
-#define BKPTMODE_INST	0
-
-/* Some of the fault registers needed by kdb but not passed with
- * regs or switch stack.
- */
-typedef struct fault_regs {
-	unsigned long	isr ;
-	unsigned long	ifa ;
-	unsigned long	iim ;
-	unsigned long	itir ;
-} fault_regs_t ;
-
-/*
- * State of kdb
- */
-
-typedef struct kdb_state {
-        int     cmd_given ;
-        int     reason_for_entry ;
-        int     bkpt_handling_state ;
-	int	kdb_action ;
-} kdb_state_t ;
-
-#define BKPTSTATE_NOT_HANDLED 	0
-#define BKPTSTATE_HANDLED 	1
-
-#define CMDGIVEN_UNKNOWN	0	
-#define CMDGIVEN_SSTEP		1	
-#define CMDGIVEN_GO		2	
-
-#define ENTRYREASON_GO	 	0
-#define ENTRYREASON_SSTEP	1
-
-#define ACTION_UNKNOWN		0
-#define ACTION_NOBPINSTALL	1
-#define ACTION_NOPROMPT		2
-
-#endif /* _ASM_IA64_KDBSUPPORT_H */
diff --git a/include/asm-ia64/keyboard.h b/include/asm-ia64/keyboard.h
index 38dbbc7bb..9259e163c 100644
--- a/include/asm-ia64/keyboard.h
+++ b/include/asm-ia64/keyboard.h
@@ -11,7 +11,7 @@
 
 # ifdef __KERNEL__
 
-#include <linux/config.h>
+#include <linux/irq.h>
 
 #define KEYBOARD_IRQ			isa_irq_to_vector(1)
 #define DISABLE_KBD_DURING_INTERRUPTS	0
@@ -38,9 +38,6 @@ extern unsigned char pckbd_sysrq_xlate[128];
 #define INIT_KBD
 
 #define SYSRQ_KEY		0x54
-#if defined(CONFIG_KDB)
-#define E1_PAUSE  119                   /* PAUSE key */
-#endif
 
 /* resource allocation */
 #define kbd_request_region()
diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h
index 0b9df0dcd..054b999f8 100644
--- a/include/asm-ia64/mca.h
+++ b/include/asm-ia64/mca.h
@@ -6,9 +6,14 @@
  * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
  * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
  */
+
+/* XXX use this temporary define for MP systems trying to INIT */
+#define SAL_MPINIT_WORKAROUND
+
 #ifndef _ASM_IA64_MCA_H
 #define _ASM_IA64_MCA_H
 
+#if !defined(__ASSEMBLY__)
 #include <linux/types.h>
 #include <asm/param.h>
 #include <asm/sal.h>
@@ -119,7 +124,7 @@ typedef struct ia64_mca_os_to_sal_state_s {
 
 typedef int (*prfunc_t)(const char * fmt, ...);
 
-extern void mca_init(void);
+extern void ia64_mca_init(void);
 extern void ia64_os_mca_dispatch(void);
 extern void ia64_os_mca_dispatch_end(void);
 extern void ia64_mca_ucmc_handler(void);
@@ -134,10 +139,12 @@ extern void ia64_log_print(int,int,prfunc_t);
 
 #undef 	MCA_TEST
 
-#if defined(MCA_TEST)
-# define MCA_DEBUG	printk
+#define IA64_MCA_DEBUG_INFO 1
+
+#if defined(IA64_MCA_DEBUG_INFO)
+# define IA64_MCA_DEBUG	printk
 #else
-# define MCA_DEBUG
+# define IA64_MCA_DEBUG
 #endif
-
+#endif /* !__ASSEMBLY__ */
 #endif /* _ASM_IA64_MCA_H */
diff --git a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h
index 97f36e587..030c1969b 100644
--- a/include/asm-ia64/mca_asm.h
+++ b/include/asm-ia64/mca_asm.h
@@ -3,7 +3,9 @@
  *
  * Copyright (C) 1999 Silicon Graphics, Inc.
  * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
- * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
+ * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
+ * Copyright (C) 2000 Hewlett-Packard Co.
+ * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #ifndef _ASM_IA64_MCA_ASM_H
 #define _ASM_IA64_MCA_ASM_H
@@ -70,25 +72,26 @@
 	;;										\
 	dep	old_psr = 0, old_psr, 32, 32;						\
 	                                                                                \
-	mov	ar##.##rsc = r0 ;							\
+	mov	ar.rsc = r0 ;								\
 	;;										\
-	mov	temp2 = ar##.##bspstore;						\
+	mov	temp2 = ar.bspstore;							\
 	;;										\
 	DATA_VA_TO_PA(temp2);								\
 	;;										\
-	mov	temp1 = ar##.##rnat;							\
+	mov	temp1 = ar.rnat;							\
 	;;										\
-	mov	ar##.##bspstore = temp2;						\
+	mov	ar.bspstore = temp2;							\
 	;;										\
-	mov	ar##.##rnat = temp1;							\
+	mov	ar.rnat = temp1;							\
 	mov	temp1 = psr;								\
 	mov	temp2 = psr;								\
 	;;										\
 	                                                                                \
 	dep	temp2 = 0, temp2, PSR_IC, 2;						\
 	;;										\
-	mov	psr##.##l = temp2;							\
-	                                                                                \
+	mov	psr.l = temp2;								\
+	;;										\
+	srlz.d;										\
 	dep	temp1 = 0, temp1, 32, 32;						\
 	;;										\
  	dep	temp1 = 0, temp1, PSR_IT, 1;						\
@@ -100,15 +103,16 @@
 	dep	temp1 = 0, temp1, PSR_I, 1;						\
 	;;										\
 	movl	temp2 = start_addr;							\
-	mov	cr##.##ipsr = temp1;							\
+	mov	cr.ipsr = temp1;							\
 	;;										\
 	INST_VA_TO_PA(temp2);								\
-	mov	cr##.##iip = temp2;							\
-	mov	cr##.##ifs = r0;							\
+	;;										\
+	mov	cr.iip = temp2;								\
+	mov	cr.ifs = r0;								\
 	DATA_VA_TO_PA(sp)								\
 	DATA_VA_TO_PA(gp)								\
 	;;										\
-	srlz##.##i;									\
+	srlz.i;										\
 	;;										\
 	nop	1;									\
 	nop	2;									\
@@ -143,18 +147,19 @@
 	;;										\
 	dep	temp2 = 0, temp2, PSR_IC, 2;						\
 	;;										\
-	mov	psr##.##l = temp2;							\
-	mov	ar##.##rsc = r0 ;							\
+	mov	psr.l = temp2;								\
+	mov	ar.rsc = r0;								\
 	;;										\
-	mov	temp2 = ar##.##bspstore;						\
+	srlz.d;										\
+	mov	temp2 = ar.bspstore;							\
 	;;										\
 	DATA_PA_TO_VA(temp2,temp1);							\
 	;;										\
-	mov	temp1 = ar##.##rnat;							\
+	mov	temp1 = ar.rnat;							\
 	;;										\
-	mov	ar##.##bspstore = temp2;						\
+	mov	ar.bspstore = temp2;							\
 	;;										\
-	mov	ar##.##rnat = temp1;							\
+	mov	ar.rnat = temp1;							\
 	;;										\
 	mov	temp1 = old_psr;							\
 	;;										\
@@ -172,12 +177,12 @@
 	dep	temp1 = temp2, temp1, PSR_BN, 1;					\
 	;;										\
 	                                                                                \
-	mov     cr##.##ipsr = temp1;							\
+	mov     cr.ipsr = temp1;							\
 	movl	temp2 = start_addr;							\
 	;;										\
-	mov	cr##.##iip = temp2;							\
+	mov	cr.iip = temp2;								\
 	DATA_PA_TO_VA(sp, temp1);							\
-	DATA_PA_TO_VA(gp, temp1);							\
+	DATA_PA_TO_VA(gp, temp2);							\
 	;;										\
 	nop	1;									\
 	nop	2;									\
@@ -226,19 +231,19 @@
  */
 #define rse_switch_context(temp,p_stackframe,p_bspstore) 			\
         ;; 									\
-        mov     temp=ar##.##rsc;; 						\
+        mov     temp=ar.rsc;; 							\
         st8     [p_stackframe]=temp,8;; 					\
-        mov     temp=ar##.##pfs;; 						\
+        mov     temp=ar.pfs;; 							\
         st8     [p_stackframe]=temp,8; 						\
         cover ;;								\
-        mov     temp=cr##.##ifs;; 						\
+        mov     temp=cr.ifs;; 							\
         st8     [p_stackframe]=temp,8;;	 					\
-        mov     temp=ar##.##bspstore;; 						\
+        mov     temp=ar.bspstore;; 						\
         st8     [p_stackframe]=temp,8;; 					\
-        mov     temp=ar##.##rnat;; 						\
+        mov     temp=ar.rnat;; 							\
         st8     [p_stackframe]=temp,8; 						\
-        mov     ar##.##bspstore=p_bspstore;; 					\
-        mov     temp=ar##.##bsp;; 						\
+        mov     ar.bspstore=p_bspstore;; 					\
+        mov     temp=ar.bsp;; 							\
         sub     temp=temp,p_bspstore;;						\
         st8     [p_stackframe]=temp,8
 
@@ -262,23 +267,23 @@
         add     p_stackframe=rse_ndirty_offset,p_stackframe;;			\
         ld8     temp=[p_stackframe];; 						\
         shl     temp=temp,16;;							\
-        mov     ar##.##rsc=temp;; 						\
+        mov     ar.rsc=temp;; 							\
         loadrs;;								\
         add     p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
         ld8     temp=[p_stackframe];; 						\
-        mov     ar##.##bspstore=temp;; 						\
+        mov     ar.bspstore=temp;; 						\
         add     p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
         ld8     temp=[p_stackframe];; 						\
-        mov     ar##.##rnat=temp;;						\
+        mov     ar.rnat=temp;;							\
         add     p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;;	\
         ld8     temp=[p_stackframe];; 						\
-        mov     ar##.##pfs=temp;						\
+        mov     ar.pfs=temp;							\
         add     p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;;	\
         ld8     temp=[p_stackframe];; 						\
-        mov     cr##.##ifs=temp;						\
+        mov     cr.ifs=temp;							\
         add     p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;;	\
         ld8     temp=[p_stackframe];; 						\
-        mov     ar##.##rsc=temp ;						\
+        mov     ar.rsc=temp ;							\
         add     p_stackframe=-rse_rsc_offset,p_stackframe;			\
         mov     temp=cr.ipsr;;							\
         st8     [p_stackframe]=temp,8;						\
diff --git a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h
index 93e73d77b..8687682f9 100644
--- a/include/asm-ia64/mman.h
+++ b/include/asm-ia64/mman.h
@@ -2,8 +2,8 @@
 #define _ASM_IA64_MMAN_H
 
 /*
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #define PROT_READ	0x1		/* page can be read */
@@ -31,6 +31,12 @@
 #define MCL_CURRENT	1		/* lock all current mappings */
 #define MCL_FUTURE	2		/* lock all future mappings */
 
+#define MADV_NORMAL	0x0		/* default page-in behavior */
+#define MADV_RANDOM	0x1		/* page-in minimum required */
+#define MADV_SEQUENTIAL	0x2		/* read-ahead aggressively */
+#define MADV_WILLNEED	0x3		/* pre-fault pages */
+#define MADV_DONTNEED	0x4		/* discard these pages */
+
 /* compatibility flags */
 #define MAP_ANON	MAP_ANONYMOUS
 #define MAP_FILE	0
diff --git a/include/asm-ia64/offsets.h b/include/asm-ia64/offsets.h
index 72eccbc24..de309ee56 100644
--- a/include/asm-ia64/offsets.h
+++ b/include/asm-ia64/offsets.h
@@ -10,7 +10,7 @@
 
 #define PF_PTRACED_BIT			4
 
-#define IA64_TASK_SIZE			2800	/* 0xaf0 */
+#define IA64_TASK_SIZE			2816	/* 0xb00 */
 #define IA64_PT_REGS_SIZE		400	/* 0x190 */
 #define IA64_SWITCH_STACK_SIZE		560	/* 0x230 */
 #define IA64_SIGINFO_SIZE		136	/* 0x88 */
@@ -21,6 +21,7 @@
 #define IA64_TASK_PROCESSOR_OFFSET	108	/* 0x6c */
 #define IA64_TASK_THREAD_OFFSET		928	/* 0x3a0 */
 #define IA64_TASK_THREAD_KSP_OFFSET	928	/* 0x3a0 */
+#define IA64_TASK_THREAD_SIGMASK_OFFSET	2656	/* 0xa60 */
 #define IA64_TASK_PID_OFFSET		188	/* 0xbc */
 #define IA64_TASK_MM_OFFSET		88	/* 0x58 */
 #define IA64_PT_REGS_CR_IPSR_OFFSET	0	/* 0x0 */
@@ -34,5 +35,7 @@
 #define IA64_SIGCONTEXT_FLAGS_OFFSET	0	/* 0x0 */
 #define IA64_SIGCONTEXT_CFM_OFFSET	48	/* 0x30 */
 #define IA64_SIGCONTEXT_FR6_OFFSET	560	/* 0x230 */
+#define IA64_CLONE_VFORK			16384	/* 0x4000 */
+#define IA64_CLONE_VM			256	/* 0x100 */
 
 #endif /* _ASM_IA64_OFFSETS_H */
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 1289930fc..afae33050 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -15,6 +15,7 @@
  *
  * 99/10/01	davidm	Make sure we pass zero for reserved parameters.
  * 00/03/07	davidm	Updated pal_cache_flush() to be in sync with PAL v2.6.
+ * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  */
 
 /*
@@ -595,18 +596,27 @@ typedef union pal_mc_error_info_u {
 #define pmci_bus_external_error			pme_bus.eb
 #define pmci_bus_mc				pme_bus.mc
 
+/* 
+ * NOTE: this min_state_save area struct only includes the 1KB 
+ * architectural state save area.  The other 3 KB is scratch space
+ * for PAL.
+ */
 
 typedef struct pal_min_state_area_s {
-	u64	pmsa_reserved[26];
-	u64	pmsa_xfs;
-	u64	pmsa_xpsr;
-	u64	pmsa_xip;
-	u64	pmsa_rsc;
-	u64	pmsa_br0;
-	u64	pmsa_pr;
-	u64	pmsa_bank0_gr[16];
-	u64	pmsa_gr[16];
-	u64	pmsa_nat_bits;
+	u64	pmsa_nat_bits;		/* nat bits for saved GRs  */
+	u64	pmsa_gr[15];		/* GR1	- GR15		   */
+	u64	pmsa_bank0_gr[16];	/* GR16 - GR31		   */
+	u64	pmsa_bank1_gr[16];	/* GR16 - GR31		   */
+	u64	pmsa_pr;		/* predicate registers	   */
+	u64	pmsa_br0;		/* branch register 0	   */
+	u64	pmsa_rsc;		/* ar.rsc		   */
+	u64	pmsa_iip;		/* cr.iip		   */
+	u64	pmsa_ipsr;		/* cr.ipsr		   */
+	u64	pmsa_ifs;		/* cr.ifs		   */
+	u64	pmsa_xip;		/* previous iip		   */
+	u64	pmsa_xpsr;		/* previous psr		   */
+	u64	pmsa_xfs;		/* previous ifs		   */
+	u64	pmsa_reserved[71];	/* pal_min_state_area should total to 1KB */
 } pal_min_state_area_t;
 
 
diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h
index b26321422..7c35de4bc 100644
--- a/include/asm-ia64/pgalloc.h
+++ b/include/asm-ia64/pgalloc.h
@@ -139,6 +139,9 @@ free_pte_fast (pte_t *pte)
 #define pmd_free(pmd)		free_pmd_fast(pmd)
 #define pgd_free(pgd)		free_pgd_fast(pgd)
 
+extern void __handle_bad_pgd (pgd_t *pgd);
+extern void __handle_bad_pmd (pmd_t *pmd);
+
 extern __inline__ pte_t*
 pte_alloc (pmd_t *pmd, unsigned long vmaddr)
 {
@@ -242,11 +245,6 @@ extern void flush_tlb_range (struct mm_struct *mm, unsigned long start, unsigned
 
 /*
  * Page-granular tlb flush.
- *
- * do a tbisd (type = 2) normally, and a tbis (type = 3)
- * if it is an executable mapping.  We want to avoid the
- * itlb flush, because that potentially also does a
- * icache flush.
  */
 static __inline__ void
 flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index 7c3fbdd95..a7f5ceb56 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -8,16 +8,24 @@
  * This hopefully works with any (fixed) ia-64 page-size, as defined
  * in <asm/page.h> (currently 8192).
  *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
+#include <linux/config.h>
+
 #include <asm/mman.h>
 #include <asm/page.h>
 #include <asm/types.h>
 
-/* Size of physical address space: */
-#define IA64_PHYS_BITS		50		/* EAS2.5 defines 50 bits of ppn */
+/* Size of virtuaql and physical address spaces: */
+#ifdef CONFIG_ITANIUM
+# define IA64_IMPL_VA_MSB	50
+# define IA64_PHYS_BITS		44		/* Itanium PRM defines 44 bits of ppn */
+#else
+# define IA64_IMPL_VA_MSB	60		/* maximum value (bits 61-63 are region bits) */
+# define IA64_PHYS_BITS		50		/* EAS2.6 allows up to 50 bits of ppn */
+#endif
 #define IA64_PHYS_SIZE		(__IA64_UL(1) << IA64_PHYS_BITS)
 
 /* Is ADDR a valid kernel address? */
@@ -338,10 +346,6 @@ pgd_offset (struct mm_struct *mm, unsigned long address)
 	((pte_t *) pmd_page(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 
 
-extern void __handle_bad_pgd (pgd_t *pgd);
-extern void __handle_bad_pmd (pmd_t *pmd);
-
-
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 extern void paging_init (void);
 
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index d31d746fa..d702b7f0c 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -62,6 +62,8 @@
 #define IA64_PSR_TB_BIT		26
 #define IA64_PSR_RT_BIT		27
 /* The following are not affected by save_flags()/restore_flags(): */
+#define IA64_PSR_CPL0_BIT	32
+#define IA64_PSR_CPL1_BIT	33
 #define IA64_PSR_IS_BIT		34
 #define IA64_PSR_MC_BIT		35
 #define IA64_PSR_IT_BIT		36
@@ -151,6 +153,7 @@
 #define IA64_THREAD_DBG_VALID	(__IA64_UL(1) << 1)	/* debug registers valid? */
 #define IA64_THREAD_UAC_NOPRINT	(__IA64_UL(1) << 2)	/* don't log unaligned accesses */
 #define IA64_THREAD_UAC_SIGBUS	(__IA64_UL(1) << 3)	/* generate SIGBUS on unaligned acc. */
+#define IA64_THREAD_KRBS_SYNCED	(__IA64_UL(1) << 4)	/* krbs synced with process vm? */
 #define IA64_KERNEL_DEATH	(__IA64_UL(1) << 63)	/* see die_if_kernel()... */
 
 #define IA64_THREAD_UAC_SHIFT	2	
@@ -270,6 +273,8 @@ typedef struct {
 		 (int *) (addr));								\
 })
 
+struct siginfo;
+
 struct thread_struct {
 	__u64 ksp;			/* kernel stack pointer */
 	unsigned long flags;		/* various flags */
@@ -278,14 +283,19 @@ struct thread_struct {
 	__u64 ibr[IA64_NUM_DBG_REGS];
 	__u64 map_base;			/* base address for mmap() */
 #ifdef CONFIG_IA32_SUPPORT
+	__u64 eflag;			/* IA32 EFLAGS reg */
 	__u64 fsr;			/* IA32 floating pt status reg */
 	__u64 fcr;			/* IA32 floating pt control reg */
 	__u64 fir;			/* IA32 fp except. instr. reg */
 	__u64 fdr;			/* IA32 fp except. data reg */
-# define INIT_THREAD_IA32	, 0, 0, 0, 0
+	union {
+		__u64 sigmask;		/* aligned mask for sigsuspend scall */
+	} un;
+# define INIT_THREAD_IA32	, 0, 0, 0, 0, 0, {0}
 #else
 # define INIT_THREAD_IA32
 #endif /* CONFIG_IA32_SUPPORT */
+	struct siginfo *siginfo;	/* current siginfo struct for ptrace() */
 };
 
 #define INIT_MMAP {								\
@@ -300,7 +310,8 @@ struct thread_struct {
 	{0, },				/* dbr */	\
 	{0, },				/* ibr */	\
 	0x2000000000000000		/* map_base */	\
-	INIT_THREAD_IA32				\
+	INIT_THREAD_IA32,				\
+	0				/* siginfo */	\
 }
 
 #define start_thread(regs,new_ip,new_sp) do {					\
diff --git a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h
index d50ce82e7..caae43a3d 100644
--- a/include/asm-ia64/ptrace.h
+++ b/include/asm-ia64/ptrace.h
@@ -232,9 +232,11 @@ struct switch_stack {
 #endif /* !__ASSEMBLY__ */
 
 /*
- * The number chosen here is somewhat arbitrary but absolutely MUST
+ * The numbers chosen here are somewhat arbitrary but absolutely MUST
  * not overlap with any of the number assigned in <linux/ptrace.h>.
  */
 #define PTRACE_SINGLEBLOCK	12	/* resume execution until next branch */
+#define PTRACE_GETSIGINFO	13	/* get child's siginfo structure */
+#define PTRACE_SETSIGINFO	14	/* set child's siginfo structure */
 
 #endif /* _ASM_IA64_PTRACE_H */
diff --git a/include/asm-ia64/ptrace_offsets.h b/include/asm-ia64/ptrace_offsets.h
index 46e8bccb1..fbbe9bff4 100644
--- a/include/asm-ia64/ptrace_offsets.h
+++ b/include/asm-ia64/ptrace_offsets.h
@@ -13,9 +13,9 @@
  *		struct ia64_fpreg fph[96];		// f32-f127
  *		struct switch_stack sw;
  *		struct pt_regs pt;
- *		unsigned long rsvd1[358];
+ *		unsigned long rsvd1[712];
  *		unsigned long dbr[8];
- *		unsigned long rsvd2[252];
+ *		unsigned long rsvd2[504];
  *		unsigned long ibr[8];
  *	}
  */
@@ -165,7 +165,8 @@
 /* pt_regs */
 #define PT_CR_IPSR		0x0830
 #define PT_CR_IIP		0x0838
-#define PT_CR_IFS		0x0840
+#define PT_CFM			0x0840
+#define PT_CR_IFS		PT_CFM		/* Use of PT_CR_IFS is deprecated */
 #define PT_AR_UNAT		0x0848
 #define PT_AR_PFS		0x0850
 #define PT_AR_RSC		0x0858
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
index e26091a94..5fadec55f 100644
--- a/include/asm-ia64/sal.h
+++ b/include/asm-ia64/sal.h
@@ -12,6 +12,8 @@
  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  *
  * 99/09/29 davidm	Updated for SAL 2.6.
+ * 00/03/29 cfleck      Updated SAL Error Logging info for processor (SAL 2.6) 
+ *                      (plus examples of platform error info structures from smariset @ Intel)
  */
 
 #include <linux/config.h>
@@ -274,8 +276,6 @@ typedef struct sal_log_processor_info_s {
 	} slpi_bus_check_info[MAX_BUS_ERRORS];
 
 	pal_min_state_area_t		slpi_min_state_area;
-	u64				slpi_bank1_gr[16];
-	u64				slpi_bank1_nat_bits;
 	u64				slpi_br[8];
 	u64				slpi_cr[128];
 	u64				slpi_ar[128];
@@ -283,6 +283,87 @@ typedef struct sal_log_processor_info_s {
 	u64				slpi_fr[128];
 } sal_log_processor_info_t;
 
+/* platform error log structures */
+typedef struct platerr_logheader {
+	u64	nextlog;	/* next log offset if present */
+	u64	loglength;	/* log length */
+	u64	logsubtype;	/* log subtype memory/bus/component */
+	u64	eseverity;	/* error severity */
+} ehdr_t;
+
+typedef struct sysmem_errlog {
+	ehdr_t	lhdr;		/* header */
+	u64	vflag;		/* valid bits for each field in the log */
+	u64	addr;		/* memory address */
+	u64	data;		/* memory data */
+	u64	cmd;		/* command bus value if any */
+	u64	ctrl;		/* control bus value if any */
+	u64	addrsyndrome;	/* memory address ecc/parity syndrome bits */
+	u64	datasyndrome;	/* data ecc/parity syndrome */
+	u64	cacheinfo;	/* platform cache info as defined in pal spec. table 7-34 */
+} merrlog_t;
+
+typedef struct sysbus_errlog {
+	ehdr_t	lhdr;		/* linkded list header */
+	u64	vflag;		/* valid bits for each field in the log */
+	u64	busnum;		/* bus number in error */
+	u64	reqaddr;	/* requestor address */
+	u64	resaddr;	/* responder address */
+	u64	taraddr;	/* target address */
+	u64	data;		/* requester r/w data */
+	u64	cmd;		/* bus commands */
+	u64	ctrl;		/* bus controls (be# &-0) */
+	u64	addrsyndrome;	/* addr bus ecc/parity bits */
+	u64	datasyndrome;	/* data bus ecc/parity bits */
+	u64	cmdsyndrome;	/* command bus ecc/parity bits */
+	u64	ctrlsyndrome;	/* control bus ecc/parity bits */
+} berrlog_t;
+
+/* platform error log structures */
+typedef struct syserr_chdr {	/* one header per component */
+	u64	busnum;		/* bus number on which the component resides */
+	u64	devnum;		/* same as device select */
+	u64	funcid;		/* function id of the device */
+	u64	devid;		/* pci device id */
+	u64	classcode;	/* pci class code for the device */
+	u64	cmdreg;		/* pci command reg value */
+	u64	statreg;	/* pci status reg value */
+} chdr_t;
+
+typedef struct cfginfo {
+	u64	cfgaddr;
+	u64	cfgval;
+} cfginfo_t;
+
+typedef struct sys_comperr {	/* per component */
+	ehdr_t	lhdr;		/* linked list header */
+	u64	vflag;		/* valid bits for each field in the log */
+	chdr_t	scomphdr;	
+	u64	numregpair;	/* number of reg addr/value pairs */
+	cfginfo_t cfginfo;
+} cerrlog_t;
+
+typedef struct sel_records {
+	ehdr_t	lhdr;
+	u64	seldata;
+} isel_t;
+
+typedef struct plat_errlog {
+	u64	      mbcsvalid;	/* valid bits for each type of log */
+	merrlog_t     smemerrlog;	/* platform memory error logs */
+	berrlog_t     sbuserrlog;	/* platform bus error logs */
+	cerrlog_t     scomperrlog;	/* platform chipset error logs */
+	isel_t	      selrecord;	/* ipmi sel record */
+} platforminfo_t;
+
+/* over all log structure (processor+platform) */
+
+typedef union udev_specific_log {
+	sal_log_processor_info_t  proclog;
+	platforminfo_t		  platlog;
+} devicelog_t;
+
+
 #define sal_log_processor_info_psi_valid		slpi_valid.spli_psi
 #define sal_log_processor_info_cache_check_valid	slpi_valid.spli_cache_check
 #define sal_log_processor_info_tlb_check_valid		slpi_valid.spli_tlb_check
@@ -303,15 +384,14 @@ typedef struct sal_log_header_s {
 	ushort			slh_log_type;		/* Type of log (0 - cpu ,1 - platform) */
 	ushort			slh_log_sub_type;	/* SGI specific sub type */
 	sal_log_timestamp_t	slh_log_timestamp;	/* Timestamp */
-	u64			slh_log_dev_spec_info;	/* For processor log this field will
-							 * contain an area architected for all
-							 * IA-64 processors. For platform log
-							 * this field will contain information
-							 * specific to the hardware 
-							 * implementation.
-							 */
 } sal_log_header_t;
 
+/* SAL PSI log structure */
+typedef struct psilog
+{
+	sal_log_header_t   sal_elog_header;
+	devicelog_t        devlog;
+} ia64_psilog_t;
 
 /*
  * Now define a couple of inline functions for improved type checking
diff --git a/include/asm-ia64/semaphore.h b/include/asm-ia64/semaphore.h
index a50ee01e3..c42aff9ad 100644
--- a/include/asm-ia64/semaphore.h
+++ b/include/asm-ia64/semaphore.h
@@ -230,7 +230,7 @@ down_write (struct rw_semaphore *sem)
 	do {
 		old_count = sem->count;
 		new_count = old_count - RW_LOCK_BIAS;
-	} while (cmpxchg(&sem->count, old_count, new_count) != old_count);
+	} while (cmpxchg_acq(&sem->count, old_count, new_count) != old_count);
 
 	if (new_count != 0)
 		__down_write_failed(sem, new_count);
@@ -279,7 +279,7 @@ __up_write (struct rw_semaphore *sem)
 	do {
 		old_count = sem->count;
 		new_count = old_count + RW_LOCK_BIAS;
-	} while (cmpxchg(&sem->count, old_count, new_count) != old_count);
+	} while (cmpxchg_rel(&sem->count, old_count, new_count) != old_count);
 
 	/*
 	 * Note: new_count <u RW_LOCK_BIAS <=> old_count < 0 && new_count >= 0.
diff --git a/include/asm-ia64/siginfo.h b/include/asm-ia64/siginfo.h
index d3b71ccaf..9e04b129b 100644
--- a/include/asm-ia64/siginfo.h
+++ b/include/asm-ia64/siginfo.h
@@ -152,7 +152,8 @@ typedef struct siginfo {
 #define TRAP_BRKPT	1	/* process breakpoint */
 #define TRAP_TRACE	2	/* process trace trap */
 #define TRAP_BRANCH	3	/* process taken branch trap */
-#define NSIGTRAP	3
+#define TRAP_HWBKPT	4	/* hardware breakpoint or watchpoint */
+#define NSIGTRAP	4
 
 /*
  * SIGCHLD si_codes
diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
index 0fd137267..6175de538 100644
--- a/include/asm-ia64/smp.h
+++ b/include/asm-ia64/smp.h
@@ -18,10 +18,17 @@
 #include <asm/ptrace.h>
 #include <asm/io.h>
 
-#define IPI_DEFAULT_BASE_ADDR	0xfee00000
 #define XTP_OFFSET		0x1e0008
 
-#define smp_processor_id() (current->processor)
+#define SMP_IRQ_REDIRECTION     (1 << 0)
+#define SMP_IPI_REDIRECTION     (1 << 1)
+
+#define smp_processor_id()	(current->processor)
+
+struct smp_boot_data {
+	int cpu_count;
+	int cpu_map[NR_CPUS];
+};
 
 extern unsigned long cpu_present_map;
 extern unsigned long cpu_online_map;
@@ -29,52 +36,43 @@ extern unsigned long ipi_base_addr;
 extern int bootstrap_processor;
 extern volatile int __cpu_number_map[NR_CPUS];
 extern volatile int __cpu_logical_map[NR_CPUS];
+extern unsigned char smp_int_redirect;
+extern char no_int_routing;
 
 #define cpu_number_map(i)	__cpu_number_map[i]
 #define cpu_logical_map(i)	__cpu_logical_map[i]
 
-#if defined(CONFIG_KDB)
-extern volatile unsigned long smp_kdb_wait;
-#endif  /* CONFIG_KDB */
-
 extern unsigned long ap_wakeup_vector;
 
 /*
  * XTP control functions:
  *    min_xtp   :  route all interrupts to this CPU
  *    normal_xtp:  nominal XTP value
- *    raise_xtp :  Route all interrupts away from this CPU
  *    max_xtp   :  never deliver interrupts to this CPU.
  */
 
-/* 
- * This turns off XTP based interrupt routing.  There is a bug in the handling of 
- * IRQ_INPROGRESS when the same vector appears on more than one CPU. 
- */
-extern int use_xtp;
-
 extern __inline void 
 min_xtp(void)
 {
-	if (use_xtp)
-		writeb(0x80, ipi_base_addr | XTP_OFFSET); /* XTP to min */
+	if (smp_int_redirect & SMP_IRQ_REDIRECTION)
+		writeb(0x00, ipi_base_addr | XTP_OFFSET); /* XTP to min */
 }
 
 extern __inline void
 normal_xtp(void)
 {
-	if (use_xtp)
-		writeb(0x8e, ipi_base_addr | XTP_OFFSET); /* XTP normal */
+	if (smp_int_redirect & SMP_IRQ_REDIRECTION)
+		writeb(0x08, ipi_base_addr | XTP_OFFSET); /* XTP normal */
 }
 
 extern __inline void
 max_xtp(void) 
 {
-	if (use_xtp)
-		writeb(0x8f, ipi_base_addr | XTP_OFFSET); /* Set XTP to max... */
+	if (smp_int_redirect & SMP_IRQ_REDIRECTION)
+		writeb(0x0f, ipi_base_addr | XTP_OFFSET); /* Set XTP to max */
 }
 
-extern __inline unsigned int 
+extern __inline__ unsigned int 
 hard_smp_processor_id(void)
 {
 	struct {
@@ -84,18 +82,19 @@ hard_smp_processor_id(void)
 		unsigned long ignored : 32;
 	} lid;
 
-	__asm__ __volatile__ ("mov %0=cr.lid" : "=r" (lid));
+	__asm__ ("mov %0=cr.lid" : "=r" (lid));
 
-	/*
-	 * Damn.  IA64 CPU ID's are 16 bits long, Linux expect the hard id to be 
-	 * in the range 0..31.  So, return the low-order bits of the bus-local ID 
-	 * only and hope it's less than 32. This needs to be fixed...
-	 */
-	return (lid.id & 0x0f);
+#ifdef LARGE_CPU_ID_OK
+	return lid.eid << 8 | lid.id;
+#else
+	if (((lid.id << 8) | lid.eid) > NR_CPUS)
+		printk("WARNING: SMP ID %d > NR_CPUS\n", (lid.id << 8) | lid.eid);
+	return lid.id;
+#endif
 }
 
-#define NO_PROC_ID 0xffffffff
-#define PROC_CHANGE_PENALTY 20
+#define NO_PROC_ID		(-1)
+#define PROC_CHANGE_PENALTY	20
 
 extern void __init init_smp_config (void);
 extern void smp_do_timer (struct pt_regs *regs);
diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
index ec10fb794..97a9511e8 100644
--- a/include/asm-ia64/spinlock.h
+++ b/include/asm-ia64/spinlock.h
@@ -2,8 +2,8 @@
 #define _ASM_IA64_SPINLOCK_H
 
 /*
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  *
  * This file is used for SMP configurations only.
@@ -16,29 +16,58 @@
 typedef struct { 
 	volatile unsigned int lock;
 } spinlock_t;
+
 #define SPIN_LOCK_UNLOCKED			(spinlock_t) { 0 }
 #define spin_lock_init(x)			((x)->lock = 0) 
 
-/* Streamlined test_and_set_bit(0, (x)) */
+/*
+ * Streamlined test_and_set_bit(0, (x)).  We use test-and-test-and-set
+ * rather than a simple xchg to avoid writing the cache-line when
+ * there is contention.
+ */
+#if 1 /* Bad code generation? */
 #define spin_lock(x) __asm__ __volatile__ ( \
-	"mov ar.ccv = r0\n" \
-	"mov r29 = 1\n" \
-	";;\n" \
-	"1:\n" \
-	"ld4 r2 = [%0]\n" \
-	";;\n" \
-	"cmp4.eq p0,p7 = r0,r2\n" \
-	"(p7) br.cond.dptk.few 1b \n" \
-	"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n" \
-	";;\n" \
-	"cmp4.eq p0,p7 = r0, r2\n" \
-	"(p7) br.cond.dptk.few 1b\n" \
-	";;\n" \
-	:: "m" __atomic_fool_gcc((x)) : "r2", "r29")
+       "mov ar.ccv = r0\n" \
+       "mov r29 = 1\n" \
+       ";;\n" \
+       "1:\n" \
+       "ld4 r2 = %0\n" \
+       ";;\n" \
+       "cmp4.eq p0,p7 = r0,r2\n" \
+       "(p7) br.cond.spnt.few 1b \n" \
+       "cmpxchg4.acq r2 = %0, r29, ar.ccv\n" \
+       ";;\n" \
+       "cmp4.eq p0,p7 = r0, r2\n" \
+       "(p7) br.cond.spnt.few 1b\n" \
+       ";;\n" \
+       :: "m" __atomic_fool_gcc((x)) : "r2", "r29")
+ 
+#else 
+#define spin_lock(x)					\
+{							\
+	spinlock_t *__x = (x);				\
+							\
+	do {						\
+		while (__x->lock);			\
+	} while (cmpxchg_acq(&__x->lock, 0, 1));	\
+}
+#endif
 
-#define spin_unlock(x) __asm__ __volatile__ ("st4.rel [%0] = r0;;" : "=m" (__atomic_fool_gcc((x))))
+#define spin_is_locked(x)	((x)->lock != 0)
 
-#define spin_trylock(x) (!test_and_set_bit(0, (x)))
+#define spin_unlock(x)		(((spinlock_t *) x)->lock = 0)
+
+/* Streamlined !test_and_set_bit(0, (x)) */
+#define spin_trylock(x)						\
+({								\
+	spinlock_t *__x = (x);					\
+	__u32 old;						\
+								\
+	do {							\
+		old = __x->lock;				\
+	} while (cmpxchg_acq(&__x->lock, old, 1) != old);	\
+	old == 0;						\
+})
 
 #define spin_unlock_wait(x) \
 	({ do { barrier(); } while(((volatile spinlock_t *)x)->lock); })
@@ -49,47 +78,43 @@ typedef struct {
 } rwlock_t;
 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
 
-#define read_lock(rw) \
-do { \
-	int tmp = 0; \
-	__asm__ __volatile__ ("1:\tfetchadd4.acq %0 = %1, 1\n" \
-			      ";;\n" \
-			      "tbit.nz p6,p0 = %0, 31\n" \
-			      "(p6) br.cond.sptk.few 2f\n" \
-			      ".section .text.lock,\"ax\"\n" \
-			      "2:\tfetchadd4.rel %0 = %1, -1\n" \
-			      ";;\n" \
-			      "3:\tld4.acq %0 = %1\n" \
-			      ";;\n" \
-			      "tbit.nz p6,p0 = %0, 31\n" \
-			      "(p6) br.cond.sptk.few 3b\n" \
-			      "br.cond.sptk.few 1b\n" \
-			      ";;\n" \
-			      ".previous\n": "=r" (tmp), "=m" (__atomic_fool_gcc(rw))); \
+#define read_lock(rw)									\
+do {											\
+	int tmp = 0;									\
+	__asm__ __volatile__ ("1:\tfetchadd4.acq %0 = %1, 1\n"				\
+			      ";;\n"							\
+			      "tbit.nz p6,p0 = %0, 31\n"				\
+			      "(p6) br.cond.sptk.few 2f\n"				\
+			      ".section .text.lock,\"ax\"\n"				\
+			      "2:\tfetchadd4.rel %0 = %1, -1\n"				\
+			      ";;\n"							\
+			      "3:\tld4.acq %0 = %1\n"					\
+			      ";;\n"							\
+			      "tbit.nz p6,p0 = %0, 31\n"				\
+			      "(p6) br.cond.sptk.few 3b\n"				\
+			      "br.cond.sptk.few 1b\n"					\
+			      ";;\n"							\
+			      ".previous\n": "=r" (tmp), "=m" (__atomic_fool_gcc(rw)));	\
 } while(0)
 
-#define read_unlock(rw) \
-do { \
-	int tmp = 0; \
-	__asm__ __volatile__ ("fetchadd4.rel %0 = %1, -1\n" \
-			      : "=r" (tmp) : "m" (__atomic_fool_gcc(rw))); \
+#define read_unlock(rw)								\
+do {										\
+	int tmp = 0;								\
+	__asm__ __volatile__ ("fetchadd4.rel %0 = %1, -1\n"			\
+			      : "=r" (tmp) : "m" (__atomic_fool_gcc(rw)));	\
 } while(0)
 
-/*
- * These may need to be rewhacked in asm().
- * XXX FIXME SDV - This may have a race on real hardware but is sufficient for SoftSDV
- */
-#define write_lock(rw) \
-while(1) {\
-	do { \
-	} while (!test_and_set_bit(31, (rw))); \
-	if ((rw)->read_counter) { \
-		clear_bit(31, (rw)); \
-		while ((rw)->read_counter) \
-			; \
-	} else { \
-		break; \
-	} \
+#define write_lock(rw)				\
+while(1) {					\
+	do {					\
+	} while (!test_and_set_bit(31, (rw)));	\
+	if ((rw)->read_counter) {		\
+		clear_bit(31, (rw));		\
+		while ((rw)->read_counter)	\
+			;			\
+	} else {				\
+		break;				\
+	}					\
 }
 
 #define write_unlock(x)				(clear_bit(31, (x)))
diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h
index 53dc2d2e5..a7ba6daf7 100644
--- a/include/asm-ia64/system.h
+++ b/include/asm-ia64/system.h
@@ -323,7 +323,7 @@ extern long __cmpxchg_called_with_bad_pointer(void);
 struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) (*(struct __xchg_dummy *)(x))
 
-#define ia64_cmpxchg(ptr,old,new,size)					\
+#define ia64_cmpxchg(sem,ptr,old,new,size)				\
 ({									\
 	__typeof__(ptr) _p_ = (ptr);					\
 	__typeof__(new) _n_ = (new);					\
@@ -336,28 +336,28 @@ struct __xchg_dummy { unsigned long a[100]; };
 	      case 8: _o_ = (__u64) (old); break;			\
 	      default:							\
 	}								\
-	 __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "r"(_o_));		\
+	 __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(_o_));		\
 	switch (size) {							\
 	      case 1:							\
-		__asm__ __volatile__ ("cmpxchg1.rel %0=%2,%3,ar.ccv"	\
+		__asm__ __volatile__ ("cmpxchg1."sem" %0=%2,%3,ar.ccv"	\
 				      : "=r"(_r_), "=m"(__xg(_p_))	\
 				      : "m"(__xg(_p_)), "r"(_n_));	\
 		break;							\
 									\
 	      case 2:							\
-		__asm__ __volatile__ ("cmpxchg2.rel %0=%2,%3,ar.ccv"	\
+		__asm__ __volatile__ ("cmpxchg2."sem" %0=%2,%3,ar.ccv"	\
 				      : "=r"(_r_), "=m"(__xg(_p_))	\
 				      : "m"(__xg(_p_)), "r"(_n_));	\
 		break;							\
 									\
 	      case 4:							\
-		__asm__ __volatile__ ("cmpxchg4.rel %0=%2,%3,ar.ccv"	\
+		__asm__ __volatile__ ("cmpxchg4."sem" %0=%2,%3,ar.ccv"	\
 				      : "=r"(_r_), "=m"(__xg(_p_))	\
 				      : "m"(__xg(_p_)), "r"(_n_));	\
 		break;							\
 									\
 	      case 8:							\
-		__asm__ __volatile__ ("cmpxchg8.rel %0=%2,%3,ar.ccv"	\
+		__asm__ __volatile__ ("cmpxchg8."sem" %0=%2,%3,ar.ccv"	\
 				      : "=r"(_r_), "=m"(__xg(_p_))	\
 				      : "m"(__xg(_p_)), "r"(_n_));	\
 		break;							\
@@ -369,7 +369,11 @@ struct __xchg_dummy { unsigned long a[100]; };
 	(__typeof__(old)) _r_;						\
 })
 
-#define cmpxchg(ptr,o,n)     ia64_cmpxchg((ptr), (o), (n), sizeof(*(ptr)))
+#define cmpxchg_acq(ptr,o,n)	ia64_cmpxchg("acq", (ptr), (o), (n), sizeof(*(ptr)))
+#define cmpxchg_rel(ptr,o,n)	ia64_cmpxchg("rel", (ptr), (o), (n), sizeof(*(ptr)))
+
+/* for compatibility with other platforms: */
+#define cmpxchg(ptr,o,n)	cmpxchg_acq(ptr,o,n)
 
 #ifdef CONFIG_IA64_DEBUG_CMPXCHG
 # define CMPXCHG_BUGCHECK_DECL	int _cmpxchg_bugcheck_count = 128;
@@ -396,24 +400,24 @@ extern void ia64_load_debug_regs (unsigned long *save_area);
 #define prepare_to_switch()    do { } while(0)
 
 #ifdef CONFIG_IA32_SUPPORT
-# define TASK_TO_PTREGS(t)									\
-	((struct pt_regs *)(((unsigned long)(t) + IA64_STK_OFFSET - IA64_PT_REGS_SIZE)))
 # define IS_IA32_PROCESS(regs)	(ia64_psr(regs)->is != 0)
-# define IA32_FP_STATE(prev,next)						\
-	if (IS_IA32_PROCESS(TASK_TO_PTREGS(prev))) {				\
+# define IA32_STATE(prev,next)							\
+	if (IS_IA32_PROCESS(ia64_task_regs(prev))) {				\
+	    __asm__ __volatile__("mov %0=ar.eflag":"=r"((prev)->thread.eflag));	\
 	    __asm__ __volatile__("mov %0=ar.fsr":"=r"((prev)->thread.fsr));	\
 	    __asm__ __volatile__("mov %0=ar.fcr":"=r"((prev)->thread.fcr));	\
 	    __asm__ __volatile__("mov %0=ar.fir":"=r"((prev)->thread.fir));	\
 	    __asm__ __volatile__("mov %0=ar.fdr":"=r"((prev)->thread.fdr));	\
 	}									\
-	if (IS_IA32_PROCESS(TASK_TO_PTREGS(next))) {				\
+	if (IS_IA32_PROCESS(ia64_task_regs(next))) {				\
+	    __asm__ __volatile__("mov ar.eflag=%0"::"r"((next)->thread.eflag));	\
 	    __asm__ __volatile__("mov ar.fsr=%0"::"r"((next)->thread.fsr));	\
 	    __asm__ __volatile__("mov ar.fcr=%0"::"r"((next)->thread.fcr));	\
 	    __asm__ __volatile__("mov ar.fir=%0"::"r"((next)->thread.fir));	\
 	    __asm__ __volatile__("mov ar.fdr=%0"::"r"((next)->thread.fdr));	\
 	}
 #else /* !CONFIG_IA32_SUPPORT */
-# define IA32_FP_STATE(prev,next)
+# define IA32_STATE(prev,next)
 # define IS_IA32_PROCESS(regs)		0
 #endif /* CONFIG_IA32_SUPPORT */
 
@@ -436,7 +440,7 @@ extern struct task_struct *ia64_switch_to (void *next_task);
 	if ((next)->thread.flags & IA64_THREAD_DBG_VALID) {			\
 		ia64_load_debug_regs(&(next)->thread.dbr[0]);			\
 	}									\
-	IA32_FP_STATE(prev,next);						\
+	IA32_STATE(prev,next);							\
 	(last) = ia64_switch_to((next));					\
 } while (0)
 
diff --git a/include/asm-ia64/types.h b/include/asm-ia64/types.h
index d4b1732e2..aee357781 100644
--- a/include/asm-ia64/types.h
+++ b/include/asm-ia64/types.h
@@ -13,10 +13,10 @@
  */
 
 #ifdef __ASSEMBLY__
-# define __IA64_UL(x)		x
+# define __IA64_UL(x)		(x)
 # define __IA64_UL_CONST(x)	x
 #else
-# define __IA64_UL(x)		((unsigned long)x)
+# define __IA64_UL(x)		((unsigned long)(x))
 # define __IA64_UL_CONST(x)	x##UL
 #endif
 
diff --git a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h
index dffc5879f..e530e7f35 100644
--- a/include/asm-ia64/uaccess.h
+++ b/include/asm-ia64/uaccess.h
@@ -71,10 +71,6 @@ verify_area (int type, const void *addr, unsigned long size)
  * These are the main single-value transfer routines.  They automatically
  * use the right size if we just have the right pointer type.
  *
- * As the alpha uses the same address space for kernel and user
- * data, we can just do these as direct assignments.  (Of course, the
- * exception handling means that it's no longer "just"...)
- *
  * Careful to not
  * (a) re-use the arguments for side effects (sizeof/typeof is ok)
  * (b) require any knowledge of processes at this stage
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index b20e42686..5be533112 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -197,6 +197,8 @@
 #define __NR_sendmsg			1205
 #define __NR_recvmsg			1206
 #define __NR_sys_pivot_root		1207
+#define __NR_mincore			1208
+#define __NR_madvise			1209
 
 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)