diff options
author | Ralf Baechle <ralf@linux-mips.org> | 1999-01-27 23:59:02 +0000 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 1999-01-27 23:59:02 +0000 |
commit | a2566570f3d0b6c94532d5bd0b1d07a34dac15f3 (patch) | |
tree | b529f0e12a72b2966fd8bc5838bbab39616d99e1 /include/asm-mips/dec/interrupts.h | |
parent | 840d2d3dbfd336a05c8cde24fbe2b7e75684dfa7 (diff) |
More DEC and Baget stuff.
Diffstat (limited to 'include/asm-mips/dec/interrupts.h')
-rw-r--r-- | include/asm-mips/dec/interrupts.h | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h new file mode 100644 index 000000000..5f99727cc --- /dev/null +++ b/include/asm-mips/dec/interrupts.h @@ -0,0 +1,79 @@ +/* + * Miscellaneous definitions used to initialise the interrupt vector table + * with the machine-specific interrupt routines. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 by Paul M. Antoine. + * reworked 1998 by Harald Koerfgen. + */ + +#ifndef __ASM_DEC_INTERRUPTS_H +#define __ASM_DEC_INTERRUPTS_H + +/* + * DECstation Interrupts + */ + +/* + * This list reflects the priority of the Interrupts. + * Exception: on kmins we have to handle Memory Error + * Interrupts before the TC Interrupts. + */ +#define CLOCK 0 +#define SCSI_INT 1 +#define ETHER 2 +#define SERIAL 3 +#define TC0 4 +#define TC1 5 +#define TC2 6 +#define MEMORY 7 +#define FPU 8 +#define HALT 9 + +#define NR_INTS 10 + +#ifndef _LANGUAGE_ASSEMBLY +/* + * Data structure to hide the differences between the DECstation Interrupts + * + * If asic_mask == NULL, the interrupt is directly handled by the CPU. + * Otherwise this Interrupt is handled the IRQ Controller. + */ + +typedef struct +{ + unsigned int cpu_mask; /* checking and enabling interrupts in CP0 */ + unsigned int iemask; /* enabling interrupts in IRQ Controller */ +} decint_t; + +/* + * Interrupt table structure to hide differences between different + * systems such. + */ +extern void *cpu_ivec_tbl[8]; +extern long cpu_mask_tbl[8]; +extern long cpu_irq_nr[8]; +extern long asic_irq_nr[32]; +extern long asic_mask_tbl[32]; + +/* + * Common interrupt routine prototypes for all DECStations + */ +extern void dec_intr_unimplemented(void); +extern void dec_intr_fpu(void); +extern void dec_intr_rtc(void); + +extern void kn02_io_int(void); +extern void kn02ba_io_int(void); +extern void kn03_io_int(void); + +extern void intr_halt(void); + +extern void asic_intr_unimplemented(void); + +#endif +#endif + |