diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-12-29 16:35:43 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-12-29 16:35:43 +0000 |
| commit | d0ed783f34132a6456fbee80ce5d121faf55fb8c (patch) | |
| tree | ed7bb65b9ba2d86bafa9ba4631718717cd944d01 /include/asm-mips/gt64120.h | |
| parent | 041d5780d54608a859ac6fd0fac06ec0e670aa5b (diff) | |
Bunch more patches from MIPS.
Diffstat (limited to 'include/asm-mips/gt64120.h')
| -rw-r--r-- | include/asm-mips/gt64120.h | 54 |
1 files changed, 32 insertions, 22 deletions
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h index 1ef59a11d..5d78b6126 100644 --- a/include/asm-mips/gt64120.h +++ b/include/asm-mips/gt64120.h @@ -28,23 +28,6 @@ /* * Interrupt Registers */ -#define GT_INTRCAUSE_OFS 0xc18 -#define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ -#define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ -#define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ - -#define GT_PCI0_CFGADDR_OFS 0xcf8 -#define GT_PCI0_CFGDATA_OFS 0xcfc -#define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ -#define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ - -#define GT_SDRAM_BM_OFS 0x478 -#define GT_SDRAM_ADDRDECODE_OFS 0x47c -#define GT_SDRAM_B0_OFS 0x44c -#define GT_SDRAM_B2_OFS 0x454 -#define GT_SDRAM_CFG_OFS 0x448 -#define GT_SDRAM_OPMODE_OFS 0x474 - #define GT_SCS10LD_OFS 0x008 #define GT_SCS10HD_OFS 0x010 #define GT_SCS32LD_OFS 0x018 @@ -96,14 +79,27 @@ #define GT_BOOTLD_OFS 0x440 #define GT_BOOTHD_OFS 0x444 +#define GT_SDRAM_B0_OFS 0x44c +#define GT_SDRAM_CFG_OFS 0x448 +#define GT_SDRAM_B2_OFS 0x454 +#define GT_SDRAM_OPMODE_OFS 0x474 +#define GT_SDRAM_BM_OFS 0x478 +#define GT_SDRAM_ADDRDECODE_OFS 0x47c + #define GT_PCI0_CMD_OFS 0xc00 /* GT64120A only */ +#define GT_PCI0_TOR_OFS 0xc04 #define GT_PCI0_BS_SCS10_OFS 0xc08 #define GT_PCI0_BS_SCS32_OFS 0xc0c -#define GT_PCI0_BARE_OFS 0xc3c - -#define GT_PCI0_TOR_OFS 0xc04 - +#define GT_INTRCAUSE_OFS 0xc18 +#define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ #define GT_PCI0_IACK_OFS 0xc34 +#define GT_PCI0_BARE_OFS 0xc3c +#define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ +#define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ +#define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ +#define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ +#define GT_PCI0_CFGADDR_OFS 0xcf8 +#define GT_PCI0_CFGDATA_OFS 0xcfc /* @@ -167,7 +163,9 @@ /* * Register encodings */ - +#define GT_CPU_ENDIAN_SHF 12 +#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) +#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK #define GT_CPU_WR_SHF 16 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) #define GT_CPU_WR_BIT GT_CPU_WR_MSK @@ -377,6 +375,18 @@ #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK +#define GT_PCI0_CMD_MBYTESWAP_SHF 0 +#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) +#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK +#define GT_PCI0_CMD_MWORDSWAP_SHF 10 +#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) +#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK +#define GT_PCI0_CMD_SBYTESWAP_SHF 16 +#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) +#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK +#define GT_PCI0_CMD_SWORDSWAP_SHF 11 +#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) +#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK /* * Misc |