diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-06-05 23:24:07 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-06-05 23:24:07 +0000 |
| commit | 1385617929e09545f9858785ea3dc1068fedfde1 (patch) | |
| tree | 728aa64786357d033a263299df97c98b28f31f0c /include/asm-mips/gt64120 | |
| parent | e4598d1f9097360d265a55f468db81d751e29a1d (diff) | |
Support 512mb RAM configuration for Momenco Ocelot. Patch from
David Woodhouse (dwmw2@infradead.org).
Diffstat (limited to 'include/asm-mips/gt64120')
| -rw-r--r-- | include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h index 9984048f2..b87658a66 100644 --- a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h +++ b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h @@ -19,14 +19,16 @@ #include <asm/byteorder.h> /* for cpu_to_le32() */ /* - * PCI address allocatoin + * PCI address allocation */ -#define GT_PCI_MEM_BASE GT_DEF_PCI0_MEM0_BASE +#define GT_PCI_MEM_BASE (0x22000000) #define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE -#define GT_PCI_IO_BASE GT_DEF_PCI0_IO_BASE +#define GT_PCI_IO_BASE (0x20000000) #define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE -#define GT64120_BASE (KSEG1ADDR(GT_DEF_BASE)) +extern unsigned long gt64120_base; + +#define GT64120_BASE (gt64120_base) /* * Because of an error/peculiarity in the Galileo chip, we need to swap the |