diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-06-05 23:24:07 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-06-05 23:24:07 +0000 |
| commit | 1385617929e09545f9858785ea3dc1068fedfde1 (patch) | |
| tree | 728aa64786357d033a263299df97c98b28f31f0c /include/asm-mips/pgtable.h | |
| parent | e4598d1f9097360d265a55f468db81d751e29a1d (diff) | |
Support 512mb RAM configuration for Momenco Ocelot. Patch from
David Woodhouse (dwmw2@infradead.org).
Diffstat (limited to 'include/asm-mips/pgtable.h')
| -rw-r--r-- | include/asm-mips/pgtable.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 6b4ebcbc3..605d48080 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -59,6 +59,16 @@ extern void (*_flush_icache_page)(struct vm_area_struct *vma, extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask); +/* + * - add_temporary_entry() add a temporary TLB entry. We use TLB entries + * starting at the top and working down. This is for populating the + * TLB before trap_init() puts the TLB miss handler in place. It + * should be used only for entries matching the actual page tables, + * to prevent inconsistencies. + */ +extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + /* Basically we have the same two-level (which is the logical three level * Linux page table layout folded) page tables as the i386. Some day |