diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
| commit | 93f107ba6cceee2c35d207349976936da48393bc (patch) | |
| tree | c33ea3d9e7e92245d6593b694cb514c8db5ff05d /include/asm-mips/pgtable.h | |
| parent | f79c44e04169d10b07b53d4a524c8c41ea5504d5 (diff) | |
Add code to support the SB1 core, including mmu routines, processor
detection. This also tweaks cpu_probe() to use bits 15:8 of PRId as
a company ID, as per the mips32/mips64 specs, and use bits 7:0 as the
processor ID within the company. Patch from Justin with mods and some
additional bits by me.
Diffstat (limited to 'include/asm-mips/pgtable.h')
| -rw-r--r-- | include/asm-mips/pgtable.h | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 25666e99f..4018ba883 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -130,13 +130,25 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, #define _CACHE_CACHABLE_NONCOHERENT 0 #else - #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ #define _PAGE_GLOBAL (1<<6) #define _PAGE_VALID (1<<7) #define _PAGE_SILENT_READ (1<<7) /* synonym */ #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ #define _PAGE_SILENT_WRITE (1<<8) +#define _CACHE_MASK (7<<9) + +#if defined(CONFIG_CPU_SB1) + +/* No penalty for being coherent on the SB1, so just + use it for "noncoherent" spaces, too. Shouldn't hurt. */ + +#define _CACHE_UNCACHED (2<<9) +#define _CACHE_CACHABLE_COW (5<<9) +#define _CACHE_CACHABLE_NONCOHERENT (5<<9) + +#else + #define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ @@ -145,9 +157,9 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, #define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */ #define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */ #define _CACHE_CACHABLE_ACCELERATED (7<<9) /* R10000 only */ -#define _CACHE_MASK (7<<9) #endif +#endif #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) @@ -157,8 +169,12 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, #ifdef CONFIG_MIPS_UNCACHED #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED #else +#ifdef CONFIG_CPU_SB1 +#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW +#else #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT #endif +#endif #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |