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authorFlorian Lohoff <flo@rfc822.org>2001-03-25 22:37:00 +0000
committerFlorian Lohoff <flo@rfc822.org>2001-03-25 22:37:00 +0000
commit12e21056dc59022eef82e32eb40cc9f98195e021 (patch)
treecc686bcd405a94be95e13e2fa1cdbd820fdad38c /include/asm-mips
parent9faa36e19ca9b0d87e0b1a280b593ba757a997f3 (diff)
Add MACH_GROUP_TOSHIBA and TX39 names
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/bootinfo.h21
1 files changed, 18 insertions, 3 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 5d7b01020..deb919475 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -29,10 +29,11 @@
#define MACH_GROUP_PHILLIPS 14
#define MACH_GROUP_GLOBESPAN 15 /* Globespan PVR Referrence Board */
#define MACH_GROUP_SIBYTE 16 /* Sibyte Eval Boards */
+#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */
#define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN", \
"SGI", "Cobalt", "NEC DDB", "Baget", "Cosine", "Galileo", "Momentum", \
- "ITE", "Phillips", "Globepspan", "SiByte" }
+ "ITE", "Phillips", "Globepspan", "SiByte", "Toshiba" }
/*
* Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -176,6 +177,15 @@
#define GROUP_SIBYTE_NAMES {"SWARM" }
/*
+ * Valid machtypes for group Toshiba
+ */
+#define MACH_PALLAS 0
+#define MACH_TOPAS 1
+#define MACH_JMR 2
+
+#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR" }
+
+/*
* Valid cputype values
*/
#define CPU_UNKNOWN 0
@@ -213,14 +223,19 @@
#define CPU_R4310 32
#define CPU_R3912 33
#define CPU_SB1 34
-#define CPU_LAST 34
+#define CPU_TX3912 35
+#define CPU_TX3922 36
+#define CPU_TX3927 37
+
+#define CPU_LAST 37
#define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
"R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \
"R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \
"R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \
"R5000A", "R4640", "Nevada", "RM7000", "R5432", "MIPS 4Kc", \
- "MIPS 5Kc", "R4310", "R3912", "SiByte SB1" }
+ "MIPS 5Kc", "R4310", "R3912", "SiByte SB1", "TX3912", "TX3922", \
+ "TX3927" }
#define COMMAND_LINE_SIZE 256