diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1997-01-07 02:33:00 +0000 |
|---|---|---|
| committer | <ralf@linux-mips.org> | 1997-01-07 02:33:00 +0000 |
| commit | beb116954b9b7f3bb56412b2494b562f02b864b1 (patch) | |
| tree | 120e997879884e1b9d93b265221b939d2ef1ade1 /include/asm-mips | |
| parent | 908d4681a1dc3792ecafbe64265783a86c4cccb6 (diff) | |
Import of Linux/MIPS 2.1.14
Diffstat (limited to 'include/asm-mips')
75 files changed, 7718 insertions, 1727 deletions
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h new file mode 100644 index 000000000..c50f2aa24 --- /dev/null +++ b/include/asm-mips/a.out.h @@ -0,0 +1,26 @@ +#ifndef __ASM_MIPS_A_OUT_H +#define __ASM_MIPS_A_OUT_H + +struct exec +{ + unsigned long a_info; /* Use macros N_MAGIC, etc for access */ + unsigned a_text; /* length of text, in bytes */ + unsigned a_data; /* length of data, in bytes */ + unsigned a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned a_syms; /* length of symbol table data in file, in bytes */ + unsigned a_entry; /* start address */ + unsigned a_trsize; /* length of relocation info for text, in bytes */ + unsigned a_drsize; /* length of relocation info for data, in bytes */ +}; + +#define N_TRSIZE(a) ((a).a_trsize) +#define N_DRSIZE(a) ((a).a_drsize) +#define N_SYMSIZE(a) ((a).a_syms) + +#ifdef __KERNEL__ + +#define STACK_TOP TASK_SIZE + +#endif + +#endif /* __ASM_MIPS_A_OUT_H */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h new file mode 100644 index 000000000..39259486e --- /dev/null +++ b/include/asm-mips/addrspace.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + * + * Defitions for the address spaces of the MIPS CPUs. + */ +#ifndef __ASM_MIPS_ADDRSPACE_H +#define __ASM_MIPS_ADDRSPACE_H + +/* + * Memory segments (32bit kernel mode addresses) + */ +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +/* + * Returns the kernel segment base of a given address + */ +#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) + +/* + * Returns the physical address of a KSEG0/KSEG1 address + */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain kernel segment + */ +#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) +#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) +#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) +#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) + +/* + * Memory segments (64bit kernel mode addresses) + */ +#define XKUSEG 0x0000000000000000 +#define XKSSEG 0x4000000000000000 +#define XKPHYS 0x8000000000000000 +#define XKSEG 0xc000000000000000 +#define CKSEG0 0xffffffff80000000 +#define CKSEG1 0xffffffffa0000000 +#define CKSSEG 0xffffffffc0000000 +#define CKSEG3 0xffffffffe0000000 + +#endif /* __ASM_MIPS_ADDRSPACE_H */ diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index 12c9785d8..afb189d63 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -5,9 +5,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995 by Ralf Baechle + * Copyright (C) 1995, 1996 by Ralf Baechle * - * Some usefull macros for MIPS assembler code + * Some useful macros for MIPS assembler code * * Some of the routines below contain useless nops that will be optimized * away by gas in -O mode. These nops are however required to fill delay @@ -16,8 +16,7 @@ #ifndef __ASM_ASM_H #define __ASM_ASM_H -#include <linux/autoconf.h> -#include <asm/regdef.h> +#include <asm/sgidefs.h> #ifndef CAT #ifdef __STDC__ @@ -29,32 +28,14 @@ #endif /* - * Macros to handle different pointer sizes for 32/64-bit code + * Macros to handle different pointer/register sizes for 32/64-bit code + * + * 64 bit address space isn't used yet, so we may use the R3000 32 bit + * defines for now. */ -#if __mips == 3 -#define PTR .quad -#define PTRSIZE 8 -#define PTRLOG 3 -#define lp ld -#else #define PTR .word #define PTRSIZE 4 #define PTRLOG 2 -#define lp lw -#endif - -/* - * ELF specific declarations - */ -#ifdef __ELF__ -#define TYPE(symbol,_type) \ - .type symbol,@_type -#define SIZE(symbol,_size) \ - .size symbol,_size -#else -#define TYPE(symbol,type) -#define SIZE(symbol,size) -#endif /* * PIC specific declarations @@ -62,11 +43,11 @@ */ #ifdef __PIC__ #define CPRESTORE(register) \ - .cprestore register + .cprestore register #define CPADD(register) \ - .cpadd register + .cpadd register #define CPLOAD(register) \ - .cpload register + .cpload register #else #define CPRESTORE(register) #define CPADD(register) @@ -77,64 +58,67 @@ * LEAF - declare leaf routine */ #define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - TYPE(symbol,function); \ - .ent symbol,0; \ -symbol: .frame sp,0,ra + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp,0,ra /* * NESTED - declare nested routine entry point */ #define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - TYPE(symbol,function); \ - .ent symbol,0; \ -symbol: .frame sp, framesize, rpc + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp, framesize, rpc /* * END - mark end of function */ #define END(function) \ - .end function; \ - SIZE(function,.-function) + .end function; \ + .size function,.-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* * ABS - export absolute symbol */ #define ABS(symbol,value) \ - .globl symbol; \ -symbol = value + .globl symbol; \ +symbol = value #define PANIC(msg) \ - la a0,8f; \ - jal panic; \ - nop; \ -9: b 9b; \ - nop; \ - TEXT(msg) + .set push; \ + .set reorder; \ + la a0,8f; \ + jal panic; \ +9: b 9b; \ + .set pop; \ + TEXT(msg) /* * Print formated string */ #define PRINT(string) \ - la a0,8f; \ - jal printk; \ - nop; \ - TEXT(string) + .set push; \ + .set reorder; \ + la a0,8f; \ + jal printk; \ + .set pop; \ + TEXT(string) #define TEXT(msg) \ - .data; \ -8: .asciiz msg; \ - .text + .data; \ +8: .asciiz msg; \ + .text; /* * Build text tables @@ -144,60 +128,33 @@ symbol = value .word 1f; \ .data; \ 1: .asciz string; \ - .text; - -/* - * Move to kernel mode and disable interrupts - * Set cp0 enable bit as sign that we're running on the kernel stack - * Use with .set noat! - */ -#define CLI \ - mfc0 AT,CP0_STATUS; \ - li t0,ST0_CU0|0x1f; \ - or AT,t0; \ - xori AT,0x1f; \ - mtc0 AT,CP0_STATUS; \ - -/* - * Move to kernel mode and enable interrupts - * Set cp0 enable bit as sign that we're running on the kernel stack - * Use with .set noat! - */ -#define STI \ - mfc0 AT,CP0_STATUS; \ - li t0,ST0_CU0|0x1f; \ - or AT,t0; \ - xori AT,0x1e; \ - mtc0 AT,CP0_STATUS; \ - -/* - * Special nop to fill load delay slots - */ -#ifndef __R4000__ -#define NOP nop -#else -#define NOP -#endif + .text /* * Return from exception */ -#if defined (CONFIG_CPU_R3000) +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) #define ERET rfe -#elif defined (CONFIG_CPU_R4X00) || defined (CONFIG_CPU_R4600) +#endif +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) #define ERET \ - .set mips3; \ eret; \ - .set mips0 -#else -#error "Implement ERET macro!" + nop; \ + nop; \ + nop; \ + nop; \ + nop #endif /* - * R8000/R10000 (MIPS ISA IV) pref instruction. + * MIPS IV pref instruction. * Use with .set noreorder only! + * + * MIPS IV implementations are free to treat this as a nop. The R5000 + * is one of them. So we should have an option not to use this instruction. */ -#if defined (CONFIG_CPU_R8000) || defined(CONFIG_CPU_R10000) +#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) #define PREF(hint,addr) \ pref hint,addr #define PREFX(hint,addr) \ @@ -208,34 +165,226 @@ symbol = value #endif /* - * R8000/R10000 (MIPS ISA IV) movn/movz instructions and - * equivalents for old CPUs. Use with .set noreorder only! + * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ -#if defined (CONFIG_CPU_R8000) || defined (CONFIG_CPU_R10000) -#define MOVN(rd,rs,rt) \ - movn rd,rs,rt -#define MOVZ(rd,rs,rt) \ - movz rd,rs,rt -#elif defined (CONFIG_CPU_R4000) || defined (CONFIG_CPU_R6000) +#if _MIPS_ISA == _MIPS_ISA_MIPS1 #define MOVN(rd,rs,rt) \ - bnezl rt,9f \ - move rd,rs \ + .set push; \ + .set reorder; \ + beqz rt,9f; \ + move rd,rs; \ + .set pop; \ 9: #define MOVZ(rd,rs,rt) \ - beqzl rt,9f \ - movz rd,rt \ + .set push; \ + .set reorder; \ + bnez rt,9f; \ + move rd,rt; \ + .set pop; \ 9: -#else /* R2000, R3000 */ +#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) #define MOVN(rd,rs,rt) \ - beqz rt,9f \ - nop \ - move rd,rs \ + .set push; \ + .set noreorder; \ + bnezl rt,9f; \ + move rd,rs; \ + .set pop; \ 9: #define MOVZ(rd,rs,rt) \ - bneqz rt,9f \ - nop \ - movz rd,rt \ + .set push; \ + .set noreorder; \ + beqzl rt,9f; \ + movz rd,rs; \ + .set pop; \ 9: +#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define MOVN(rd,rs,rt) \ + movn rd,rs,rt +#define MOVZ(rd,rs,rt) \ + movz rd,rs,rt +#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */ + +/* + * Stack alignment + */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) +#define ALSZ 7 +#define ALMASK ~7 +#endif +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define ALSZ 15 +#define ALMASK ~15 +#endif + +/* + * Size of a register + */ +#ifdef __mips64 +#define SZREG 8 +#else +#define SZREG 4 +#endif + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) +#define REG_S sw +#define REG_L lw +#define PTR_SUBU subu +#define PTR_ADDU addu +#endif +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define REG_S sd +#define REG_L ld +/* We still live in a 32 bit address space ... */ +#define PTR_SUBU subu +#define PTR_ADDU addu +#endif + +/* + * How to add/sub/load/store/shift C int variables. + */ +#if (_MIPS_SZINT == 32) +#define INT_ADD add +#define INT_ADDI addi +#define INT_ADDU addu +#define INT_ADDIU addiu +#define INT_SUB add +#define INT_SUBI subi +#define INT_SUBU subu +#define INT_SUBIU subu +#define INT_L lw +#define INT_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav +#endif + +#if (_MIPS_SZINT == 64) +#define INT_ADD dadd +#define INT_ADDI daddi +#define INT_ADDU daddu +#define INT_ADDIU daddiu +#define INT_SUB dadd +#define INT_SUBI dsubi +#define INT_SUBU dsubu +#define INT_SUBIU dsubu +#define INT_L ld +#define INT_S sd +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav +#endif + +/* + * How to add/sub/load/store/shift C long variables. + */ +#if (_MIPS_SZLONG == 32) +#define LONG_ADD add +#define LONG_ADDI addi +#define LONG_ADDU addu +#define LONG_ADDIU addiu +#define LONG_SUB add +#define LONG_SUBI subi +#define LONG_SUBU subu +#define LONG_SUBIU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav +#endif + +#if (_MIPS_SZLONG == 64) +#define LONG_ADD dadd +#define LONG_ADDI daddi +#define LONG_ADDU daddu +#define LONG_ADDIU daddiu +#define LONG_SUB dadd +#define LONG_SUBI dsubi +#define LONG_SUBU dsubu +#define LONG_SUBIU dsubu +#define LONG_L ld +#define LONG_S sd +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav +#endif + +/* + * How to add/sub/load/store/shift pointers. + */ +#if (_MIPS_SZLONG == 32) +#define PTR_ADD add +#define PTR_ADDI addi +#define PTR_ADDU addu +#define PTR_ADDIU addiu +#define PTR_SUB add +#define PTR_SUBI subi +#define PTR_SUBU subu +#define PTR_SUBIU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav + +#define PTR_SCALESHIFT 2 +#endif + +#if (_MIPS_SZLONG == 64) +#define PTR_ADD dadd +#define PTR_ADDI daddi +#define PTR_ADDU daddu +#define PTR_ADDIU daddiu +#define PTR_SUB dadd +#define PTR_SUBI dsubi +#define PTR_SUBU dsubu +#define PTR_SUBIU dsubu +#define PTR_L ld +#define PTR_S sd +#define PTR_SLL dsll +#define PTR_SLLV dsllv +#define PTR_SRL dsrl +#define PTR_SRLV dsrlv +#define PTR_SRA dsra +#define PTR_SRAV dsrav + +#define PTR_SCALESHIFT 3 +#endif + +/* + * Some cp0 registers were extended to 64bit for MIPS III. + */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) +#define MFC0 mfc0 +#define MTC0 mtc0 +#endif +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define MFC0 dmfc0 +#define MTC0 dmtc0 #endif #endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h new file mode 100644 index 000000000..1faf804c6 --- /dev/null +++ b/include/asm-mips/atomic.h @@ -0,0 +1,176 @@ +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + * + * But use these as seldom as possible since they are much more slower + * than regular operations. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_ATOMIC_H +#define __ASM_MIPS_ATOMIC_H + +#include <asm/sgidefs.h> + +/* + * Make sure gcc doesn't try to be clever and move things around + * on us. We need to use _exactly_ the address the user gave us, + * not some alias that contains the same information. + */ +#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x) + +typedef int atomic_t; + +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) + +#include <asm/system.h> + +/* + * The MIPS I implementation is only atomic with respect to + * interrupts. R3000 based multiprocessor machines are rare anyway ... + */ +extern __inline__ void atomic_add(atomic_t i, atomic_t * v) +{ + int flags; + + save_flags(flags); + cli(); + *v += i; + restore_flags(flags); +} + +extern __inline__ void atomic_sub(atomic_t i, atomic_t * v) +{ + int flags; + + save_flags(flags); + cli(); + *v -= i; + restore_flags(flags); +} + +extern __inline__ int atomic_add_return(atomic_t i, atomic_t * v) +{ + int temp, flags; + + save_flags(flags); + cli(); + temp = *v; + temp += i; + *v = temp; + restore_flags(flags); + + return temp; +} + +extern __inline__ int atomic_sub_return(atomic_t i, atomic_t * v) +{ + int temp, flags; + + save_flags(flags); + cli(); + temp = *v; + temp -= i; + *v = temp; + restore_flags(flags); + + return temp; +} +#endif + +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) +/* + * ... while for MIPS II and better we can use ll/sc instruction. This + * implementation is SMP safe ... + */ +extern __inline__ void atomic_add(atomic_t i, atomic_t * v) +{ + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0,%1\n\t" + "addu\t%0,%2\n\t" + "sc\t%0,%1\n\t" + "beqz\t%0,1b" + :"=&r" (temp), + "=m" (__atomic_fool_gcc(v)) + :"Ir" (i), + "m" (__atomic_fool_gcc(v))); +} + +extern __inline__ void atomic_sub(atomic_t i, atomic_t * v) +{ + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0,%1\n\t" + "subu\t%0,%2\n\t" + "sc\t%0,%1\n\t" + "beqz\t%0,1b" + :"=&r" (temp), + "=m" (__atomic_fool_gcc(v)) + :"Ir" (i), + "m" (__atomic_fool_gcc(v))); +} + +/* + * Same as above, but return the result value + */ +extern __inline__ int atomic_add_return(atomic_t i, atomic_t * v) +{ + unsigned long temp, result; + + __asm__ __volatile__( + ".set\tnoreorder\n" + "1:\tll\t%1,%2\n\t" + "addu\t%0,%1,%3\n\t" + "sc\t%0,%2\n\t" + "beqz\t%0,1b\n\t" + "addu\t%0,%1,%3\n\t" + ".set\treorder" + :"=&r" (result), + "=&r" (temp), + "=m" (__atomic_fool_gcc(v)) + :"Ir" (i), + "m" (__atomic_fool_gcc(v))); + + return result; +} + +extern __inline__ int atomic_sub_return(atomic_t i, atomic_t * v) +{ + unsigned long temp, result; + + __asm__ __volatile__( + ".set\tnoreorder\n" + "1:\tll\t%1,%2\n\t" + "subu\t%0,%1,%3\n\t" + "sc\t%0,%2\n\t" + "beqz\t%0,1b\n\t" + "subu\t%0,%1,%3\n\t" + ".set\treorder" + :"=&r" (result), + "=&r" (temp), + "=m" (__atomic_fool_gcc(v)) + :"Ir" (i), + "m" (__atomic_fool_gcc(v))); + + return result; +} +#endif + +#define atomic_dec_return(v) atomic_sub_return(1,(v)) +#define atomic_inc_return(v) atomic_add_return(1,(v)) + +#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) + +#define atomic_inc(v) atomic_add(1,(v)) +#define atomic_dec(v) atomic_sub(1,(v)) + +#endif /* __ASM_MIPS_ATOMIC_H */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 255ec9ee2..4a7f8ab89 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -5,13 +5,33 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1994, 1995 Ralf Baechle + * Copyright (c) 1994, 1995, 1996 Ralf Baechle */ #ifndef __ASM_MIPS_BITOPS_H #define __ASM_MIPS_BITOPS_H -#ifdef __R4000__ +#include <asm/sgidefs.h> +/* + * Note that the bit operations are defined on arrays of 32 bit sized + * elements. With respect to a future 64 bit implementation it is + * wrong to use long *. Use u32 * or int *. + */ +extern __inline__ int set_bit(int nr, void *addr); +extern __inline__ int clear_bit(int nr, void *addr); +extern __inline__ int change_bit(int nr, void *addr); +extern __inline__ int test_bit(int nr, const void *addr); +extern __inline__ int find_first_zero_bit (void *addr, unsigned size); +extern __inline__ int find_next_zero_bit (void * addr, int size, int offset); +extern __inline__ unsigned long ffz(unsigned long word); + +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) + +/* + * These functions for MIPS ISA > 1 are interrupt and SMP proof and + * interrupt friendly + */ #include <asm/mipsregs.h> /* @@ -62,19 +82,29 @@ extern __inline__ int change_bit(int nr, void *addr) return retval; } -#else /* !defined(__R4000__) */ +#else /* MIPS I */ +#ifdef __KERNEL__ +/* + * These functions are only used for MIPS ISA 1 CPUs. Since I don't + * believe that someone ever will run Linux/SMP on such a beast I don't + * worry about making them SMP proof. + */ #include <asm/system.h> -#ifdef __KERNEL__ /* - * Only disable interrupt for kernelmode stuff to keep some - * usermode stuff alive + * Only disable interrupt for kernel mode stuff to keep usermode stuff + * that dares to use kernel include files alive. */ #define __flags unsigned long flags #define __cli() cli() #define __save_flags(x) save_flags(x) #define __restore_flags(x) restore_flags(x) +#else +#define __flags +#define __cli() +#define __save_flags(x) +#define __restore_flags(x) #endif /* __KERNEL__ */ extern __inline__ int set_bit(int nr, void * addr) @@ -133,48 +163,56 @@ extern __inline__ int change_bit(int nr, void * addr) #undef __save_flags(x) #undef __restore_flags(x) -#endif /* !defined(__R4000__) */ +#endif /* MIPS I */ -extern __inline__ int test_bit(int nr, void *addr) +extern __inline__ int test_bit(int nr, const void *addr) { - int mask; - unsigned long *a; - - a = addr; - addr += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); + return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; } extern __inline__ int find_first_zero_bit (void *addr, unsigned size) { + unsigned long dummy; int res; if (!size) return 0; - __asm__(".set\tnoreorder\n\t" + __asm__ (".set\tnoreorder\n\t" ".set\tnoat\n" - "1:\tsubu\t$1,%2,%0\n\t" + "1:\tsubu\t$1,%6,%0\n\t" "blez\t$1,2f\n\t" - "lw\t$1,(%4)\n\t" - "addiu\t%4,%4,4\n\t" + "lw\t$1,(%5)\n\t" + "addiu\t%5,4\n\t" +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) "beql\t%1,$1,1b\n\t" - "addiu\t%0,%0,32\n\t" + "addiu\t%0,32\n\t" +#else + "addiu\t%0,32\n\t" + "beq\t%1,$1,1b\n\t" + "nop\n\t" + "subu\t%0,32\n\t" +#endif +#ifdef __MIPSEB__ +#error "Fix this for big endian" +#endif /* __MIPSEB__ */ "li\t%1,1\n" - "1:\tand\t%4,$1,%1\n\t" - "beq\t$0,%4,2f\n\t" + "1:\tand\t%2,$1,%1\n\t" + "beqz\t%2,2f\n\t" "sll\t%1,%1,1\n\t" - "bne\t$0,%1,1b\n\t" + "bnez\t%1,1b\n\t" "add\t%0,%0,1\n\t" ".set\tat\n\t" ".set\treorder\n" "2:" - : "=r" (res) - : "r" ((unsigned int) 0xffffffff), - "r" (size), - "0" ((signed int) 0), - "r" (addr) + : "=r" (res), + "=r" (dummy), + "=r" (addr) + : "0" ((signed int) 0), + "1" ((unsigned int) 0xffffffff), + "2" (addr), + "r" (size) : "$1"); return res; @@ -182,26 +220,32 @@ extern __inline__ int find_first_zero_bit (void *addr, unsigned size) extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) { - unsigned long * p = ((unsigned long *) addr) + (offset >> 5); + unsigned int *p = ((unsigned int *) addr) + (offset >> 5); int set = 0, bit = offset & 31, res; + unsigned long dummy; if (bit) { /* * Look for zero in first byte */ +#ifdef __MIPSEB__ +#error "Fix this for big endian byte order" +#endif __asm__(".set\tnoreorder\n\t" ".set\tnoat\n" - "1:\tand\t$1,%2,%1\n\t" - "beq\t$0,$1,2f\n\t" - "sll\t%2,%2,1\n\t" - "bne\t$0,%2,1b\n\t" - "addiu\t%0,%0,1\n\t" + "1:\tand\t$1,%4,%1\n\t" + "beqz\t$1,1f\n\t" + "sll\t%1,%1,1\n\t" + "bnez\t%1,1b\n\t" + "addiu\t%0,1\n\t" ".set\tat\n\t" ".set\treorder\n" - : "=r" (set) - : "r" (*p >> bit), - "r" (1), - "0" (0) + "1:" + : "=r" (set), + "=r" (dummy) + : "0" (0), + "1" (1 << bit), + "r" (*p) : "$1"); if (set < (32 - bit)) return set + offset; @@ -211,8 +255,8 @@ extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) /* * No zero yet, search remaining full bytes for a zero */ - res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr)); - return (offset + set + res); + res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr)); + return offset + set + res; } /* @@ -224,25 +268,36 @@ extern __inline__ unsigned long ffz(unsigned long word) unsigned int __res; unsigned int mask = 1; - __asm__ __volatile__ ( + __asm__ ( ".set\tnoreorder\n\t" ".set\tnoat\n\t" - "li\t%2,1\n" + "move\t%0,$0\n" "1:\tand\t$1,%2,%1\n\t" "beqz\t$1,2f\n\t" - "sll\t%2,1\n\t" - "bnez\t%2,1b\n\t" + "sll\t%1,1\n\t" + "bnez\t%1,1b\n\t" "addiu\t%0,1\n\t" ".set\tat\n\t" ".set\treorder\n" "2:\n\t" - : "=r" (__res), "=r" (word), "=r" (mask) - : "1" (~(word)), - "2" (mask), - "0" (0) + : "=&r" (__res), "=r" (mask) + : "r" (word), "1" (mask) : "$1"); return __res; } +#ifdef __KERNEL__ +#ifdef __MIPSEB__ +#error "Aieee... fix these sources for big endian machines" +#endif /* __MIPSEB__ */ + +#define ext2_set_bit set_bit +#define ext2_clear_bit clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +#endif /* __KERNEL__ */ + #endif /* __ASM_MIPS_BITOPS_H */ diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 594b45b5d..a7e712b96 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -1,11 +1,8 @@ /* * bootinfo.h -- Definition of the Linux/MIPS boot information structure * - * Copyright (C) 1994 by Waldorf Electronics - * Written by Ralf Baechle and Andreas Busse - * - * Based on Linux/68k linux/include/linux/bootstrap.h - * Copyright (C) 1992 by Greg Harp + * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, + * Stoned Elipot and Paul M. Antoine. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file README.legal in the main directory of this archive @@ -15,14 +12,64 @@ #define __ASM_MIPS_BOOTINFO_H /* - * Valid machtype values + * Valid machgroup values + */ +#define MACH_GROUP_UNKNOWN 0 /* whatever... */ +#define MACH_GROUP_JAZZ 1 /* Acer Pica 61, Mips Magnum 4000, Olivetti */ + /* M700-10 */ +#define MACH_GROUP_DEC 2 /* Digital */ +#define MACH_GROUP_ARC 3 /* Deskstation Tyne, rpc44, possibly other */ +#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ +#define MACH_GROUP_ACN 5 + +#define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN" } + +/* + * Valid machtype values for group unknown (low order halfword of mips_machtype) + */ +#define MACH_UNKNOWN 0 /* whatever... */ + +#define GROUP_UNKNOWN_NAMES { "unknown" } + +/* + * Valid machtype values for group JAZZ + */ +#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ +#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ +#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ + +#define GROUP_JAZZ_NAMES { "Acer PICA 61", "Mips Magnum 4000", "Olivetti M700" } + +/* + * Valid machtype for group DEC + */ +/* FIXME: this is a very fuzzy name, and we got a big "name space now" */ +/* So otiginal DEC codes can be used -Stoned */ +#define MACH_DECSTATION 0 /* DECStation 5000/2x for now */ + +#define GROUP_DEC_NAMES { "3min" } + +/* + * Valid machtype for group ARC + */ +#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ +#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ + +#define GROUP_ARC_NAMES { "Deskstation rPC44", "Deskstation Tyne" } + +/* + * Valid machtype for group SNI_RM */ -#define MACH_UNKNOWN 0 /* whatever... */ -#define MACH_DESKSTATION_RPC44 1 /* Deskstation rPC44 */ -#define MACH_DESKSTATION_TYNE 2 /* Deskstation Tyne */ -#define MACH_ACER_PICA_61 3 /* Acer PICA-61 (PICA1) */ -#define MACH_MIPS_MAGNUM_4000 4 /* Mips Magnum 4000 "RC4030" */ -#define MACH_OLIVETTI_M700 5 /* Olivetti M700 */ +#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ + +#define GROUP_SNI_RM_NAMES { "RM200 PCI" } + +/* + * Valid machtype for group SNI_RM + */ +#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ + +#define GROUP_ACN_NAMES { "ACN" } /* * Valid cputype values @@ -48,200 +95,182 @@ #define CPU_R6000A 18 #define CPU_R8000 19 #define CPU_R10000 20 -#define CPU_LAST 20 - -#define CPU_NAMES { "UNKNOWN", "R2000", "R3000", "R3000A", "R3041", "R3051", \ +#define CPU_R4300 21 +#define CPU_R4650 22 +#define CPU_R4700 23 +#define CPU_R5000 24 +#define CPU_R5000A 25 +#define CPU_R4640 26 +#define CPU_LAST 26 + +#define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \ "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \ "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \ - "R6000A", "R8000", "R10000" } + "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \ + "R5000A", "R4640" } #define CL_SIZE (80) #ifndef __LANGUAGE_ASSEMBLY__ /* - * Some machine parameters passed by MILO. Note that bootinfo - * *must* be in the data segment since the kernel clears the - * bss segment directly after startup. + * Some machine parameters passed by the bootloaders. */ struct drive_info_struct { char dummy[32]; - }; - -struct bootinfo { - /* - * machine type - */ - unsigned long machtype; - - /* - * system CPU & FPU - */ - unsigned long cputype; - - /* - * Installed RAM - */ - unsigned long memlower; - unsigned long memupper; - - /* - * Cache Sizes (0xffffffff = unknown) - */ - unsigned long icache_size; - unsigned long icache_linesize; - unsigned long dcache_size; - unsigned long dcache_linesize; - unsigned long scache_size; - unsigned long scache_linesize; - - /* - * TLB Info - */ - unsigned long tlb_entries; - - /* - * DMA buffer size (Deskstation only) - */ - unsigned long dma_cache_size; - unsigned long dma_cache_base; - - /* - * Ramdisk Info - */ - unsigned long ramdisk_size; /* ramdisk size in 1024 byte blocks */ - unsigned long ramdisk_base; /* address of the ram disk in mem */ - - /* - * Boot flags for the kernel - */ - unsigned long mount_root_rdonly; - struct drive_info_struct drive_info; - - /* - * Video ram info (not in tty.h) - */ - unsigned long vram_base; /* video ram base address */ - - char command_line[CL_SIZE]; /* kernel command line parameters */ - }; -#if 0 +/* This is the same as in Milo but renamed for the sake of kernel's */ +/* namespace */ +typedef struct mips_arc_DisplayInfo /* video adapter information */ +{ + unsigned short cursor_x; + unsigned short cursor_y; + unsigned short columns; + unsigned short lines; +} mips_arc_DisplayInfo; + /* * New style bootinfo * * Add new tags only at the end of the enum; *never* remove any tags * or you'll break compatibility! + * Which compatibility ? compatibility consideration lead to + * MS-DOG :) -Stoned */ -enum bi_tag { - /* - * not a real tag - */ - dummy, - - /* - * machine type - */ - machtype, - - /* - * system CPU & FPU - */ - cputype, +enum bi_tag { + /* + * not a real tag + */ + tag_dummy, + + /* + * machine type + */ + tag_machtype, + + /* + * system CPU & FPU + */ + tag_cputype, + + /* + * Installed RAM + */ + tag_memlower, + tag_memupper, + + /* + * Cache Sizes (0xffffffff = unknown) + */ + tag_icache_size, + tag_icache_linesize, + tag_dcache_size, + tag_dcache_linesize, + tag_scache_size, + tag_scache_linesize, + + /* + * TLB Info + */ + tag_tlb_entries, + + /* + * DMA buffer size (Deskstation only) + */ + tag_dma_cache_size, + tag_dma_cache_base, + + /* + * Ramdisk Info + */ + tag_ramdisk_size, /* ramdisk size in 1024 byte blocks */ + tag_ramdisk_base, /* address of the ram disk in mem */ + + /* + * Boot flags for the kernel + */ + tag_mount_root_rdonly, /* No longer used; use "ro" command + line argument instead. */ + tag_drive_info, + + /* + * Video ram info (not in tty.h) + */ + tag_vram_base, /* video ram base address */ + + tag_command_line, /* kernel command line parameters */ + + /* + * machine group + */ + tag_machgroup, /* - * Installed RAM + * info on the display from the ARC BIOS */ - memlower, - memupper, + tag_arcdisplayinfo, /* - * Cache Sizes (0xffffffff = unknown) + * tag to pass a complete struct screen_info */ - icache_size, - icache_linesize, - dcache_size, - dcache_linesize, - scache_size, - scache_linesize, + tag_screen_info - /* - * TLB Info - */ - tlb_entries, - - /* - * DMA buffer size (Deskstation only) - */ - dma_cache_size, - dma_cache_base, - - /* - * Ramdisk Info - */ - ramdisk_size, /* ramdisk size in 1024 byte blocks */ - ramdisk_base, /* address of the ram disk in mem */ - - /* - * Boot flags for the kernel - */ - mount_root_rdonly, - drive_info, - - /* - * Video ram info (not in tty.h) - */ - vram_base, /* video ram base address */ - - command_line /* kernel command line parameters */ - }; +/* struct defining a tag */ typedef struct { - bi_tag tag; - unsigned long size; + enum bi_tag tag; + unsigned long size; } tag; -#endif - -extern struct bootinfo boot_info; -/* - * Defaults, may be overwritten by milo. We initialize - * them to make sure that both boot_info and screen_info - * are in the .data segment since the .bss segment is - * cleared during startup. - */ -#define BOOT_INFO { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, {{0,}}, 0, "" } -#define SCREEN_INFO {0, 0, {0, }, 52, 3, 80, 4626, 3, 9, 50} - -#else /* !__LANGUAGE_ASSEMBLY__ */ +/* struct to define a tag and it's data */ +typedef struct { + tag t; + void* d; +} tag_def; + +/* macros for parsing tag list */ +#define TAGVALPTR(t) ((void*)(((void*)(t)) - ((t)->size))) +#define NEXTTAGPTR(t) ((void*)(TAGVALPTR(t) - (sizeof(tag)))) + +/* size macros for tag size field */ +#define UCHARSIZE (sizeof(unsigned char)) +#define ULONGSIZE (sizeof(unsigned long)) +#define UINTSIZE (sizeof(unsigned int)) +#define DRVINFOSIZE (sizeof(struct drive_info_struct)) +#define CMDLINESIZE (sizeof(char[CL_SIZE]) + +/* For tag readers aka the kernel */ +tag *bi_TagFind(enum bi_tag type); +void bi_EarlySnarf(void); + +/* For tag creators aka bootloaders */ +/* Now implemented in Milo 0.26 */ +int bi_TagAdd(enum bi_tag type, unsigned long size, void *data); +int bi_TagAddList(tag_def* taglist); +void bi_TagWalk(void); + +/* default values for screen_info variable */ +#define DEFAULT_SCREEN_INFO {0, 0, {0, }, 52, 3, 80, 4626, 3, 9, 50} +/* default values for drive info */ +#define DEFAULT_DRIVE_INFO { {0,}} /* - * Same structure, but as offsets for usage within assembler source. - * Don't mess with struct bootinfo without changing offsets too! + * These are the kernel variables initialized from + * the tag. And they have to be initialized to dummy/default + * values in setup.c (or whereever suitable) so they are in + * .data section */ - -#define OFFSET_BOOTINFO_MACHTYPE 0 -#define OFFSET_BOOTINFO_CPUTYPE 4 -#define OFFSET_BOOTINFO_MEMLOWER 8 -#define OFFSET_BOOTINFO_MEMUPPER 12 -#define OFFSET_BOOTINFO_ICACHE_SIZE 16 -#define OFFSET_BOOTINFO_ICACHE_LINESIZE 20 -#define OFFSET_BOOTINFO_DCACHE_SIZE 24 -#define OFFSET_BOOTINFO_DCACHE_LINESIZE 28 -#define OFFSET_BOOTINFO_SCACHE_SIZE 32 -#define OFFSET_BOOTINFO_SCACHE_LINESIZE 36 -#define OFFSET_BOOTINFO_TLB_ENTRIES 40 -#define OFFSET_BOOTINFO_DMA_CACHE_SIZE 44 -#define OFFSET_BOOTINFO_DMA_CACHE_BASE 48 -#define OFFSET_BOOTINFO_RAMDISK_SIZE 52 -#define OFFSET_BOOTINFO_RAMDISK_BASE 56 -#define OFFSET_BOOTINFO_MOUNT_RD_ONLY 60 -#define OFFSET_BOOTINFO_DRIVE_INFO 64 -#define OFFSET_BOOTINFO_VRAM_BASE 96 -#define OFFSET_BOOTINFO_COMMAND_LINE 100 +extern unsigned long mips_memory_upper; +extern unsigned long mips_cputype; +extern unsigned long mips_machtype; +extern unsigned long mips_machgroup; +extern unsigned long mips_tlb_entries; +extern unsigned long mips_vram_base; +extern unsigned long mips_dma_cache_size; +extern unsigned long mips_dma_cache_base; #endif /* __LANGUAGE_ASSEMBLY__ */ diff --git a/include/asm-mips/branch.h b/include/asm-mips/branch.h new file mode 100644 index 000000000..abca807ec --- /dev/null +++ b/include/asm-mips/branch.h @@ -0,0 +1,26 @@ +/* + * Branch and jump emulation. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#include <asm/ptrace.h> + +extern inline int delay_slot(struct pt_regs *regs) +{ + return regs->cp0_cause & CAUSEF_BD; +} + +extern int __compute_return_epc(struct pt_regs *regs); +extern inline int compute_return_epc(struct pt_regs *regs) +{ + if (delay_slot(regs)) { + return __compute_return_epc(regs); + } + + regs->cp0_epc += 4; + return 0; +} diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h index 41ca73366..f2c12e853 100644 --- a/include/asm-mips/bugs.h +++ b/include/asm-mips/bugs.h @@ -13,12 +13,11 @@ * void check_bugs(void); */ -extern struct bootinfo boot_info; static void check_wait(void) { printk("Checking for 'wait' instruction... "); - switch(boot_info.cputype) { + switch(mips_cputype) { case CPU_R4200: case CPU_R4600: wait_available = 1; diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index 45abf2350..bf4c54a1f 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -1,94 +1,117 @@ +/* + * Functions depending of the byteorder. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ #ifndef __ASM_MIPS_BYTEORDER_H #define __ASM_MIPS_BYTEORDER_H +extern unsigned long int ntohl(unsigned long int __x); +extern unsigned short int ntohs(unsigned short int __x); +extern unsigned short int htons(unsigned short int __x); +extern unsigned long int htonl(unsigned long int __x); + +#define __swap32(x) \ + ((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \ + (((unsigned long int)(x) & 0x0000ff00U) << 8) | \ + (((unsigned long int)(x) & 0x00ff0000U) >> 8) | \ + (((unsigned long int)(x) & 0xff000000U) >> 24))) +#define __swap16(x) \ + ((unsigned short int)((((unsigned short int)(x) & 0x00ff) << 8) | \ + (((unsigned short int)(x) & 0xff00) >> 8))) + +#if defined (__MIPSEB__) + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN +#endif + +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif + +#define __constant_ntohl(x) (x) +#define __constant_ntohs(x) (x) +#define __constant_htonl(x) (x) +#define __constant_htons(x) (x) + +#ifdef __KERNEL__ + /* - * FIXME: Add big endian support + * In-kernel byte order macros to handle stuff like + * byte-order-dependent filesystems etc. */ -#undef ntohl -#undef ntohs -#undef htonl -#undef htons - -#ifdef __MIPSEL__ -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 1234 -#endif +#define cpu_to_le32(x) __swap32((x)) +#define le32_to_cpu(x) __swap32((x)) +#define cpu_to_le16(x) __swap16((x)) +#define le16_to_cpu(x) __swap16((x)) + +#define cpu_to_be32(x) (x) +#define be32_to_cpu(x) (x) +#define cpu_to_be16(x) (x) +#define be16_to_cpu(x) (x) + +#endif /* __KERNEL__ */ + +#elif defined (__MIPSEL__) -#ifndef LITTLE_ENDIAN_BITFIELD -#define LITTLE_ENDIAN_BITFIELD +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN #endif -#elif __MIPSEB__ -#define BIG_ENDIAN 4321 -#define BIG_ENDIAN_BITFIELD -#else -#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" + +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD #endif -extern unsigned long int ntohl(unsigned long int); -extern unsigned short int ntohs(unsigned short int); -extern unsigned long int htonl(unsigned long int); -extern unsigned short int htons(unsigned short int); +#define __constant_ntohl(x) __swap32(x) +#define __constant_ntohs(x) __swap16(x) +#define __constant_htonl(x) __swap32(x) +#define __constant_htons(x) __swap16(x) -extern unsigned long int __ntohl(unsigned long int); -extern unsigned short int __ntohs(unsigned short int); -extern unsigned long int __constant_ntohl(unsigned long int); -extern unsigned short int __constant_ntohs(unsigned short int); +#ifdef __KERNEL__ /* - * The constant and non-constant versions here are the same. - * Maybe I'll come up with an mips-optimized routine for the - * non-constant ones (the constant ones don't need it: gcc - * will optimize it to the correct constant) + * In-kernel byte order macros to handle stuff like + * byte-order-dependent filesystems etc. */ +#define cpu_to_le32(x) (x) +#define le32_to_cpu(x) (x) +#define cpu_to_le16(x) (x) +#define le16_to_cpu(x) (x) + +#define cpu_to_be32(x) __swap32((x)) +#define be32_to_cpu(x) __swap32((x)) +#define cpu_to_be16(x) __swap16((x)) +#define be16_to_cpu(x) __swap16((x)) + +#endif /* __KERNEL__ */ -extern __inline__ unsigned long int -__ntohl(unsigned long int x) +#else +#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" +#endif + +extern __inline__ unsigned long int ntohl(unsigned long int __x) { - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | - ((x & 0xff000000U) >> 24)); + return __constant_ntohl(__x); } -#define __constant_ntohl(x) \ - ((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \ - (((unsigned long int)(x) & 0x0000ff00U) << 8) | \ - (((unsigned long int)(x) & 0x00ff0000U) >> 8) | \ - (((unsigned long int)(x) & 0xff000000U) >> 24))) +extern __inline__ unsigned short int ntohs(unsigned short int __x) +{ + return __constant_ntohs(__x); +} -extern __inline__ unsigned short int -__ntohs(unsigned short int x) +extern __inline__ unsigned long int htonl(unsigned long int __x) { - return (((x & 0x00ff) << 8) | - ((x & 0xff00) >> 8)); + return __constant_htonl(__x); } -#define __constant_ntohs(x) \ - ((unsigned short int)((((unsigned short int)(x) & 0x00ff) << 8) | \ - (((unsigned short int)(x) & 0xff00) >> 8))) \ - -#define __htonl(x) __ntohl(x) -#define __htons(x) __ntohs(x) -#define __constant_htonl(x) __constant_ntohl(x) -#define __constant_htons(x) __constant_ntohs(x) - -#ifdef __OPTIMIZE__ -# define ntohl(x) \ -(__builtin_constant_p((long)(x)) ? \ - __constant_ntohl((x)) : \ - __ntohl((x))) -# define ntohs(x) \ -(__builtin_constant_p((short)(x)) ? \ - __constant_ntohs((x)) : \ - __ntohs((x))) -# define htonl(x) \ -(__builtin_constant_p((long)(x)) ? \ - __constant_htonl((x)) : \ - __htonl((x))) -# define htons(x) \ -(__builtin_constant_p((short)(x)) ? \ - __constant_htons((x)) : \ - __htons((x))) -#endif +extern __inline__ unsigned short int htons(unsigned short int __x) +{ + return __constant_htons(__x); +} #endif /* __ASM_MIPS_BYTEORDER_H */ diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h new file mode 100644 index 000000000..7add64caa --- /dev/null +++ b/include/asm-mips/cache.h @@ -0,0 +1,67 @@ +/* + * Defines related to MIPS caches. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CACHE +#define __ASM_MIPS_CACHE + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 + /* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + /* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b + /* 0x1c is unused */ + /* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * Flags for internal cacheflush call + * FIXME: CF_DMA is not implemented yet. + */ +#define CF_ICACHE (1<<0) /* flush instruction cache */ +#define CF_DCACHE (1<<1) /* writeback and flush data cache */ +#define CF_BCACHE (CF_ICACHE|CF_DCACHE) /* writeback and flush data cache */ +#define CF_VIRTUAL (1<<2) /* operate only on virtual caches */ +#define CF_PHYSICAL (1<<4) /* operate only on physical caches */ +#define CF_ALL (CF_VIRTUAL|CF_PHYSICAL)/* work on all cache types */ +#define CF_DMA (1<<5) /* Do DMA cache maintenance */ + +#ifndef __LANGUAGE_ASSEMBLY__ + +#include <linux/linkage.h> + +extern void (*mips_cache_init)(void); +extern asmlinkage void (*cacheflush)(unsigned long addr, unsigned long nbytes, unsigned int flags); + +#endif /* !__LANGUAGE_ASSEMBLY__ */ +#endif /* __ASM_MIPS_CACHE */ diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h index 68105fb69..214d28918 100644 --- a/include/asm-mips/cachectl.h +++ b/include/asm-mips/cachectl.h @@ -1,37 +1,24 @@ /* - * include/asm-mips/cachectl.h + * cachectl.h -- defines for MIPS cache control system calls * - * Written by Ralf Baechle, - * Copyright (C) 1994 by Waldorf GMBH + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ #ifndef __ASM_MIPS_CACHECTL #define __ASM_MIPS_CACHECTL /* - * cachectl.h -- defines for MIPS cache control system calls - */ - -/* * Options for cacheflush system call */ #define ICACHE (1<<0) /* flush instruction cache */ #define DCACHE (1<<1) /* writeback and flush data cache */ #define BCACHE (ICACHE|DCACHE) /* flush both caches */ -#define CACHELINES 512 /* number of cachelines (kludgy) */ - /* - * Cache Operations - for use by assembler code + * Caching modes for the cachectl(2) call + * + * cachctl(2) is currently not supported and returns ENOSYS. */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_D 0x05 - -#ifdef __KERNEL__ -#ifndef __LANGUAGE_ASSEMBLY__ - -extern int sys_cacheflush(void *addr, int nbytes, int cache); +#define CACHEABLE 0 /* make pages cacheable */ +#define UNCACHEABLE 1 /* make pages uncacheable */ -#endif -#endif #endif /* __ASM_MIPS_CACHECTL */ diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h new file mode 100644 index 000000000..08dd07707 --- /dev/null +++ b/include/asm-mips/checksum.h @@ -0,0 +1,251 @@ +/* + * include/asm-mips/checksum.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CHECKSUM_H +#define __ASM_MIPS_CHECKSUM_H + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ +unsigned int csum_partial_copy(const char *src, char *dst, int len, unsigned int sum); + +/* + * the same as csum_partial, but copies from user space (but on MIPS + * we have just one address space, so this is identical to the above) + */ +#define csum_partial_copy_fromuser csum_partial_copy + +/* + * Fold a partial checksum without adding pseudo headers + */ +static inline unsigned short int csum_fold(unsigned int sum) +{ + unsigned int __res; + + __asm__(" + .set noat + srl $1,%0,16 + andi %0,0xffff + addu $1,%0 + srl %0,$1,16 # addup halfword carry + andi $1,0xffff + addu $1,%0 + nor %0,$0,$1 + .set at" + : "=r"(__res) + : "0" (sum) + : "$1"); + + return __res; +} + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + * + * By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by + * Arnt Gulbrandsen. + */ +static inline unsigned short ip_fast_csum(unsigned char * iph, + unsigned int ihl) +{ + unsigned int sum; + unsigned long dummy; + + /* + * This is for 32-bit MIPS processors. + */ + __asm__ __volatile__(" + .set noreorder + .set noat + lw %0,(%1) + subu %2,4 + #blez %2,2f + sll %2,2 # delay slot + + lw %3,4(%1) + addu %2,%1 # delay slot + addu %0,%3 + sltu $1,%0,%3 + lw %3,8(%1) + addu %0,$1 + addu %0,%3 + sltu $1,%0,%3 + lw %3,12(%1) + addu %0,$1 + addu %0,%3 + sltu $1,%0,%3 + addu %0,$1 + +1: lw %3,16(%1) + addiu %1,4 + addu %0,%3 + sltu $1,%0,%3 + bne %2,%1,1b + addu %0,$1 # delay slot + +2: .set at + .set reorder" + : "=&r" (sum), "=&r" (iph), "=&r" (ihl), "=&r" (dummy) + : "1" (iph), "2" (ihl) + : "$1"); + + return csum_fold(sum); +} + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ +static inline unsigned short int csum_tcpudp_magic(unsigned long saddr, + unsigned long daddr, + unsigned short len, + unsigned short proto, + unsigned int sum) +{ + __asm__(" + .set noat + addu %0,%2 + sltu $1,%0,%2 + addu %0,$1 + addu %0,%3 + sltu $1,%0,%3 + addu %0,$1 + addu %0,%4 + sltu $1,%0,%4 + addu %0,$1 + + srl $1,%0,16 + andi %0,0xffff + addu %0,$1 + srl $1,%0,16 # addup halfword carry + andi %0,0xffff + addu %0,$1 + nor %0,$0,%0 + .set at" + : "=r" (sum) + : "0" (daddr), "r"(saddr), "r"((ntohs(len)<<16)+proto*256), "r"(sum) + : "$1"); + + return (unsigned short)sum; +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ +static inline unsigned short ip_compute_csum(unsigned char * buff, int len) +{ + unsigned short int sum; + + __asm__(" + .set noat + srl $1,%0,16 + andi %0,0xffff + addu %0,$1 + sltu $1,%0,$1 + addu %0,$1 + nor %0,$0,%0 + .set at" + : "=r"(sum) + : "0" (csum_partial(buff, len, 0)) + : "$1"); + + return sum; +} + +#define _HAVE_ARCH_IPV6_CSUM +static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, + struct in6_addr *daddr, + __u16 len, + unsigned short proto, + unsigned int sum) +{ + __asm__(" + .set noreorder + .set noat + addu %0,%5 # proto (long in network byte order) + sltu $1,%0,%5 + addu %0,$1 + + addu %0,%6 # csum + sltu $1,%0,%6 + lw %1,0(%2) # four words source address + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,4(%2) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,8(%2) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,12(%2) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,0(%3) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,4(%3) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,8(%3) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + + lw %1,12(%3) + addu %0,$1 + addu %0,%1 + sltu $1,%0,$1 + .set noat + .set noreorder + " + : "=r" (sum), + "=r" (proto) + : "r" (saddr), + "r" (daddr), + "0" (htonl((__u32) (len))), + "1" (htonl(proto)), + "r"(sum) + : "$1"); + + return csum_fold(sum); +} + +#endif /* __ASM_MIPS_CHECKSUM_H */ diff --git a/include/asm-mips/dec/decstation.h b/include/asm-mips/dec/decstation.h new file mode 100644 index 000000000..cae4302d2 --- /dev/null +++ b/include/asm-mips/dec/decstation.h @@ -0,0 +1,54 @@ +/* + * General info common to all DECstation systems + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. + * + * This file is under construction - you were warned! + */ + +#ifndef __ASM_DEC_DECSTATION_H +#define __ASM_DEC_DECSTATION_H + +/* + * REX functions -- these are for the new TURBOchannel style ROMs + */ +#define REX_PROM_MAGIC 0x30464354 /* passed in a2 */ + +#define REX_GETBITMAP 0x84 /* get mem bitmap */ +#define REX_GETCHAR 0x24 /* getch() */ +#define REX_PUTCHAR 0x13 /* putch() */ +#define REX_HALT 0x9c /* halt the system */ +#define REX_PRINTF 0x30 /* printf() */ +#define REX_PUTS 0x2c /* puts() */ +#define REX_SLOTADDR 0x6c /* slotaddr */ +#define REX_GETENV 0x64 /* get env. variable */ +#define REX_GETSYSID 0x80 /* get system id */ +#define REX_OPEN 0x54 /* open() */ +#define REX_READ 0x58 /* read() */ + + + +#ifndef __LANGUAGE_ASSEMBLY__ + +/* + * A structure to allow calling of the various DEC boot prom routines. + * FIXME: Don't know how well different DECStation boot prom revisions + * are accomodated. + */ +struct dec_prom { + void (*dec_prom_printf)(char *format, ...); + char *(*dec_prom_getenv)(char *name); + unsigned long (*dec_prom_getbitmap)(void); + unsigned long (*dec_prom_getsysid)(void); + char *(*dec_prom_gets)(char *s); + void (*dec_prom_halt)(const unsigned int); +}; + +#endif + +#endif /* __ASM_DEC_DECSTATION_H */ diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h new file mode 100644 index 000000000..61df7b512 --- /dev/null +++ b/include/asm-mips/dec/kn02.h @@ -0,0 +1,52 @@ +/* + * Hardware info about DEC DECstation 5000/2xx systems (otherwise known + * as 3max or kn02. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. + * + * This file is under construction - you were warned! + */ +#include <asm/segment.h> +#ifndef __ASM_MIPS_PMAX_H +#define __ASM_MIPS_PMAX_H + +/* + * The addresses below are virtual address. The mappings are + * created on startup via wired entries in the tlb. + */ + +#define PMAX_LOCAL_IO_SPACE 0xe0000000 + +/* + * Motherboard regs (kseg1 addresses) + */ +#define PMAX_SSR_ADDR KSEG1ADDR(0x1ff00000) /* system control & status reg */ + +/* + * SSR defines + */ +#define PMAX_SSR_LEDMASK 0x0000001000 /* diagnostic LED */ + +#ifndef __LANGUAGE_ASSEMBLY__ + +extern __inline__ void pmax_set_led(unsigned int bits) +{ + volatile unsigned int *led_register = (unsigned int *) PMAX_SSR_ADDR; + + *led_register = bits & PMAX_SSR_LEDMASK; +} + +#endif + +/* + * Some port addresses... + * FIXME: these addresses are incomplete and need tidying up! + */ +#define PMAX_RTC_BASE (KSEG1ADDR(0x1fe80000 + 0x200000)) /* ASIC + SL8 */ + +#endif /* __ASM_MIPS_PMAX_H */ diff --git a/include/asm-mips/dec/maxine.h b/include/asm-mips/dec/maxine.h new file mode 100644 index 000000000..3f908d5fb --- /dev/null +++ b/include/asm-mips/dec/maxine.h @@ -0,0 +1,52 @@ +/* + * Hardware info about DEC Personal DECStation systems (otherwise known + * as maxine (internal DEC codename). + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. + * + * This file is under construction - you were warned! + */ + +#ifndef __ASM_DEC_MAXINE_H +#define __ASM_DEC_MAXINE_H + +/* + * The addresses below are virtual address. The mappings are + * created on startup via wired entries in the tlb. + */ + +#define PMAX_LOCAL_IO_SPACE 0xe0000000 + +/* + * Motherboard regs (kseg1 addresses) + */ +#define PMAX_SSR_ADDR KSEG1ADDR(0x1c040100) /* system support reg */ + +/* + * SSR defines + */ +#define PMAX_SSR_LEDMASK 0x00000001 /* power LED */ + +#ifndef __LANGUAGE_ASSEMBLY__ + +extern __inline__ void pmax_set_led(unsigned int bits) +{ + volatile unsigned int *led_register = (unsigned int *) PMAX_SSR_ADDR; + + *led_register = bits & PMAX_SSR_LEDMASK; +} + +#endif + +/* + * Some port addresses... + * FIXME: these addresses are incomplete and need tidying up! + */ +#define PMAX_RTC_BASE (KSEG1ADDR(0x1c000000 + 0x200000)) /* ASIC + SL8 */ + +#endif /* __ASM_DEC_MAXINE_H */ diff --git a/include/asm-mips/decstation.h b/include/asm-mips/decstation.h new file mode 100644 index 000000000..ac04ff097 --- /dev/null +++ b/include/asm-mips/decstation.h @@ -0,0 +1,254 @@ +/* + * Hardware info about DEC Personal DECStation systems (otherwise known + * as maxine or pmax (internal DEC codenames). + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Paul M. Antoine, some code and definitions are + * by curteousy of Chris Fraser. + * + * This file is under construction - you were warned! + */ + +#ifndef __ASM_MIPS_PMAX_H +#define __ASM_MIPS_PMAX_H + +/* + * The addresses below are virtual address. The mappings are + * created on startup via wired entries in the tlb. + */ + +#define PMAX_LOCAL_IO_SPACE 0xe0000000 + +/* + * Motherboard regs (kseg1 addresses) + */ +#define PMAX_SSR_ADDR 0xbc040100 /* system support reg */ + +/* + * SSR defines + */ +#define PMAX_SSR_LEDMASK 0x00000001 /* power LED */ + +/* + * REX functions -- these are for the new TURBOchannel style ROMs + */ +#define REX_PROM_MAGIC 0x30464354 /* passed in a2 */ + +#define REX_GETBITMAP 0x84 /* get mem bitmap */ +#define REX_GETCHAR 0x24 /* getch() */ +#define REX_PUTCHAR 0x13 /* putch() */ +#define REX_HALT 0x9c /* halt the system */ +#define REX_PRINTF 0x30 /* printf() */ +#define REX_PUTS 0x2c /* puts() */ +#define REX_SLOTADDR 0x6c /* slotaddr */ + +#ifndef __LANGUAGE_ASSEMBLY__ + +extern __inline__ void pmax_set_led(unsigned int bits) +{ + volatile unsigned int *led_register = (unsigned int *) PMAX_SSR_ADDR; + + *led_register = bits & PMAX_SSR_LEDMASK; +} + +/* + * Glue code to call the PMAX boot proms. + */ +extern asmlinkage void pmax_printf(const char *); + +#endif + +/* + * These are just hacked out of the JAZZ ones, no ideas really. + */ +#define PMAX_KEYBOARD_ADDRESS 0xe0005000 +#define PMAX_KEYBOARD_DATA 0xe0005000 +#define PMAX_KEYBOARD_COMMAND 0xe0005001 + +#ifndef __LANGUAGE_ASSEMBLY__ + +typedef struct { + unsigned char data; + unsigned char command; +} pmax_keyboard_hardware; + +typedef struct { + unsigned char pad0[3]; + unsigned char data; + unsigned char pad1[3]; + unsigned char command; +} mips_keyboard_hardware; + +/* + * For now. + */ +#define keyboard_hardware pmax_keyboard_hardware + +#endif + +/* + * Serial ports on DEC - maybe! + */ + +#define PMAX_SERIAL1_BASE (unsigned int)0xe0006000 +#define PMAX_SERIAL2_BASE (unsigned int)0xe0007000 + +/* + * Dummy Device Address. Used in pmaxdma.c + */ + +#define PMAX_DUMMY_DEVICE 0xe000d000 + +/* + * PMAX timer registers and interrupt no. + * Note that the hardware timer interrupt is actually on + * cpu level 6, but to keep compatibility with PC stuff + * it is remapped to vector 0. See arch/mips/kernel/entry.S. + */ +#define PMAX_TIMER_INTERVAL 0xe0000228 +#define PMAX_TIMER_REGISTER 0xe0000230 + +/* + * DRAM configuration register + */ +#ifndef __LANGUAGE_ASSEMBLY__ +#ifdef __MIPSEL__ +typedef struct { + unsigned int bank2 : 3; + unsigned int bank1 : 3; + unsigned int mem_bus_width : 1; + unsigned int reserved2 : 1; + unsigned int page_mode : 1; + unsigned int reserved1 : 23; +} dram_configuration; +#else /* defined (__MIPSEB__) */ +typedef struct { + unsigned int reserved1 : 23; + unsigned int page_mode : 1; + unsigned int reserved2 : 1; + unsigned int mem_bus_width : 1; + unsigned int bank1 : 3; + unsigned int bank2 : 3; +} dram_configuration; +#endif +#endif /* __LANGUAGE_ASSEMBLY__ */ + +#define PMAX_DRAM_CONFIG 0xe00fffe0 + +/* + * PMAX interrupt control registers + */ +#define PMAX_IO_IRQ_SOURCE 0xe0100000 +#define PMAX_IO_IRQ_ENABLE 0xe0100002 + +/* + * PMAX interrupt enable bits + */ +#define PMAX_IE_PARALLEL (1 << 0) +#define PMAX_IE_FLOPPY (1 << 1) +#define PMAX_IE_SOUND (1 << 2) +#define PMAX_IE_VIDEO (1 << 3) +#define PMAX_IE_ETHERNET (1 << 4) +#define PMAX_IE_SCSI (1 << 5) +#define PMAX_IE_KEYBOARD (1 << 6) +#define PMAX_IE_MOUSE (1 << 7) +#define PMAX_IE_SERIAL1 (1 << 8) +#define PMAX_IE_SERIAL2 (1 << 9) + +/* + * PMAX Interrupt Level definitions + */ + +#define PMAX_TIMER_IRQ 0 +#define PMAX_KEYBOARD_IRQ 1 +#define PMAX_ETHERNET_IRQ 2 /* 15 */ +#define PMAX_SERIAL1_IRQ 3 +#define PMAX_SERIAL2_IRQ 4 +#define PMAX_PARALLEL_IRQ 5 +#define PMAX_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */ + +/* + * PMAX DMA Channels + * Note: Channels 4...7 are not used with respect to the Acer PICA-61 + * chipset which does not provide these DMA channels. + */ + +#define PMAX_SCSI_DMA 0 /* SCSI */ +#define PMAX_FLOPPY_DMA 1 /* FLOPPY */ +#define PMAX_AUDIOL_DMA 2 /* AUDIO L */ +#define PMAX_AUDIOR_DMA 3 /* AUDIO R */ + +/* + * PMAX R4030 MCT_ADR chip (DMA controller) + * Note: Virtual Addresses ! + */ + +#define PMAX_R4030_CONFIG 0xE0000000 /* R4030 config register */ +#define PMAX_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */ +#define PMAX_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */ + +#define PMAX_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */ +#define PMAX_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */ +#define PMAX_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */ + +#define PMAX_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */ +#define PMAX_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */ +#define PMAX_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Adresss */ + +#define PMAX_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */ +#define PMAX_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */ +#define PMAX_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */ +#define PMAX_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */ + +/* + * Remote Speed Registers. + * + * 0: free, 1: Ethernet, 2: SCSI, 3: Floppy, + * 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2, + * 8: parallel, 9: NVRAM, 10: CPU, 11: PROM, + * 12: reserved, 13: free, 14: 7seg LED, 15: ??? + */ + +#define PMAX_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */ + /* 0xE0000070,78,80... 0xE00000E8 */ +#define PMAX_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */ + +#define PMAX_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Reg */ +#define PMAX_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */ + + +/* + * Access the R4030 DMA and I/O Controller + */ + +#ifndef __LANGUAGE_ASSEMBLY__ + +extern inline unsigned short r4030_read_reg16(unsigned addr) { + unsigned short ret = *((volatile unsigned short *)addr); + __asm__ __volatile__("nop; nop; nop; nop;"); + return ret; +} + +extern inline unsigned int r4030_read_reg32(unsigned addr) { + unsigned int ret = *((volatile unsigned int *)addr); + __asm__ __volatile__("nop; nop; nop; nop;"); + return ret; +} + +extern inline void r4030_write_reg16(unsigned addr, unsigned val) { + *((volatile unsigned short *)addr) = val; + __asm__ __volatile__("nop; nop; nop; nop;"); +} + +extern inline unsigned int r4030_write_reg32(unsigned addr, unsigned val) { + *((volatile unsigned int *)addr) = val; + __asm__ __volatile__("nop; nop; nop; nop;"); +} + +#endif /* !LANGUAGE_ASSEMBLY__ */ + + +#endif /* __ASM_MIPS_PMAX_H */ diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index b35498dc1..d7d6e269d 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -4,11 +4,9 @@ extern __inline__ void __delay(int loops) { __asm__ __volatile__ ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "1:\tbne\t$0,%0,1b\n\t" - "subu\t%0,%0,1\n\t" - ".set\tat\n\t" + ".set\tnoreorder\n" + "1:\tbnez\t%0,1b\n\t" + "subu\t%0,1\n\t" ".set\treorder" :"=r" (loops) :"0" (loops)); @@ -36,7 +34,7 @@ extern __inline__ void udelay(unsigned long usecs) /* * The different variants for 32/64 bit are pure paranoia. The typical - * range of numbers that apprears for MIPS machines avoids overflows. + * range of numbers that appears for MIPS machines avoids overflows. */ extern __inline__ unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c) { diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h index 14f1f0dae..c3fd31d58 100644 --- a/include/asm-mips/dma.h +++ b/include/asm-mips/dma.h @@ -5,7 +5,7 @@ * and John Boyd, Nov. 1992. * * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards - * and can only be used for expansion cards. Onboard DMA controller, such + * and can only be used for expansion cards. Onboard DMA controllers, such * as the R4030 on Jazz boards behave totally different! */ @@ -73,11 +73,13 @@ #define MAX_DMA_CHANNELS 8 -/* The maximum address that we can perform a DMA transfer to on this platform */ -#define MAX_DMA_ADDRESS 0x1000000 - -/* The maximum address that we can perform a DMA transfer to on this platform */ -#define MAX_DMA_ADDRESS 0x1000000 +/* + * The maximum address in KSEG0 that we can perform a DMA transfer to on this + * platform. This describes only the PC style part of the DMA logic like on + * Deskstations or Acer PICA but not the much more versatile DMA logic used + * for the local devices on Acer PICA or Magnums. + */ +#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) /* 8237 DMA controllers */ #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ @@ -271,8 +273,7 @@ static __inline__ int get_dma_residue(unsigned int dmanr) /* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, char * device_id); /* reserve a DMA channel */ +extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ - #endif /* __ASM_MIPS_DMA_H */ diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h new file mode 100644 index 000000000..527352711 --- /dev/null +++ b/include/asm-mips/elf.h @@ -0,0 +1,47 @@ +#ifndef __ASM_MIPS_ELF_H +#define __ASM_MIPS_ELF_H + +/* + * ELF register definitions + * This is "make it compile" stuff! + */ +#define ELF_NGREG 32 +#define ELF_NFPREG 32 + +typedef unsigned long elf_greg_t; +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef double elf_fpreg_t; +typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + * Using EM_MIPS is actually wrong - this one is reserved for big endian + * machines only but there is no EM_ constant for little endian ... + */ +#define elf_check_arch(x) ((x) == EM_MIPS || (x) == EM_MIPS_RS4_BE) + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#ifdef __MIPSEB__ +#define ELF_DATA ELFDATA2MSB; +#elif __MIPSEL__ +#define ELF_DATA ELFDATA2LSB; +#endif +#define ELF_ARCH EM_MIPS + + /* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program + starts %edx contains a pointer to a function which might be + registered using `atexit'. This provides a mean for the + dynamic linker to call DT_FINI functions for shared libraries + that have been loaded before the code runs. + + A value of 0 tells we have no such handler. */ +#define ELF_PLAT_INIT(_r) _r->regs[2] = 0 + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* __ASM_MIPS_ELF_H */ diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h index f31e2b19f..dc4072a94 100644 --- a/include/asm-mips/errno.h +++ b/include/asm-mips/errno.h @@ -65,7 +65,14 @@ #define ENOANO 53 /* No anode */ #define EBADRQC 54 /* Invalid request code */ #define EBADSLT 55 /* Invalid slot */ +#if 0 #define EDEADLOCK 56 /* File locking deadlock error */ +#else +/* + * This needs to be fixed - DEADLOCK should be 45. + */ +#define EDEADLOCK EDEADLK /* File locking deadlock error */ +#endif #define EBFONT 59 /* Bad font file format */ #define ENOSTR 60 /* Device not a stream */ #define ENODATA 61 /* No data available */ @@ -137,6 +144,16 @@ #define EINPROGRESS 150 /* Operation now in progress */ #define ESTALE 151 /* Stale NFS file handle */ #define ECANCELED 158 /* AIO operation canceled */ + +/* + * IRIX 5 error number start from 1000. + * Stupid enough; ECANCELED gets redefined with a different value ... +#define ECANCELED 1000 + */ + +/* + * IRIX 4 compatibility error numbers. + */ #define EDQUOT 1133 /* Quota exceeded */ #define ENFSREMOTE 1134 /* ??? */ diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h index 2a41e3da9..3606b252a 100644 --- a/include/asm-mips/fcntl.h +++ b/include/asm-mips/fcntl.h @@ -1,5 +1,5 @@ -#ifndef _I386_FCNTL_H -#define _I386_FCNTL_H +#ifndef __ASM_MIPS_FCNTL_H +#define __ASM_MIPS_FCNTL_H /* open/fcntl - O_SYNC is only implemented on blocks devices and on files located on an ext2 file system */ @@ -49,19 +49,14 @@ blocking */ #define LOCK_UN 8 /* remove lock */ -#ifdef __KERNEL__ -#define F_POSIX 1 -#define F_FLOCK 2 -#endif /* __KERNEL__ */ - typedef struct flock { short l_type; short l_whence; - off_t l_start; - off_t l_len; + __kernel_off_t l_start; + __kernel_off_t l_len; long l_sysid; /* XXXXXXXXXXXXXXXXXXXXXXXXX */ - pid_t l_pid; + __kernel_pid_t l_pid; long pad[4]; /* ZZZZZZZZZZZZZZZZZZZZZZZZZZ */ } flock_t; -#endif +#endif /* __ASM_MIPS_FCNTL_H */ diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h new file mode 100644 index 000000000..f639f5aed --- /dev/null +++ b/include/asm-mips/floppy.h @@ -0,0 +1,113 @@ +/* + * Architecture specific parts of the Floppy driver + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 + */ +#ifndef __ASM_MIPS_FLOPPY_H +#define __ASM_MIPS_FLOPPY_H + +#include <linux/config.h> +#include <asm/bootinfo.h> +#include <asm/jazz.h> +#include <asm/jazzdma.h> +#include <asm/mipsconfig.h> +#include <asm/vector.h> + +#define fd_inb(port) feature->fd_inb(port) +#define fd_outb(value,port) feature->fd_outb(value,port) + +#define fd_enable_dma() feature->fd_enable_dma() +#define fd_disable_dma() feature->fd_disable_dma() +#define fd_request_dma() feature->fd_request_dma() +#define fd_free_dma() feature->fd_free_dma() +#define fd_clear_dma_ff() feature->fd_clear_dma_ff() +#define fd_set_dma_mode(mode) feature->fd_set_dma_mode(mode) +#define fd_set_dma_addr(addr) feature->fd_set_dma_addr(virt_to_bus(addr)) +#define fd_set_dma_count(count) feature->fd_set_dma_count(count) +#define fd_get_dma_residue() feature->fd_get_dma_residue() +#define fd_enable_irq() feature->fd_enable_irq() +#define fd_disable_irq() feature->fd_disable_irq() +#define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt, \ + SA_INTERRUPT|SA_SAMPLE_RANDOM, \ + "floppy", NULL) +#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); + +#define MAX_BUFFER_SECTORS 24 + +/* Pure 2^n version of get_order */ +extern __inline__ int __get_order(unsigned long size) +{ + int order; + + size = (size-1) >> (PAGE_SHIFT-1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +extern __inline__ unsigned long mips_dma_mem_alloc(unsigned long size) +{ + int order = __get_order(size); + unsigned long mem; + + mem = __get_dma_pages(GFP_KERNEL,order); + if(!mem) + return 0; +#ifdef CONFIG_MIPS_JAZZ + if (mips_machgroup == MACH_GROUP_JAZZ) + vdma_alloc(PHYSADDR(mem), size); +#endif + return mem; +} + +extern __inline__ void mips_dma_mem_free(unsigned long addr, unsigned long size) +{ +#ifdef CONFIG_MIPS_JAZZ + if (mips_machgroup == MACH_GROUP_JAZZ) + vdma_free(PHYSADDR(addr)); +#endif + free_pages(addr, __get_order(size)); +} + +#define fd_dma_mem_alloc(size) mips_dma_mem_alloc(size) +#define fd_dma_mem_free(mem,size) mips_dma_mem_free(mem,size) + +/* + * And on Mips's the CMOS info fails also ... + * + * FIXME: This information should come from the ARC configuration tree + * or whereever a particular machine has stored this ... + */ +#define FLOPPY0_TYPE 4 /* this is wrong for the Olli M700, but who cares... */ +#define FLOPPY1_TYPE 0 + +#define FDC1 ((mips_machgroup == MACH_GROUP_JAZZ) ? \ + JAZZ_FDC_BASE : 0x3f0) +static int FDC2=-1; + +#define N_FDC 1 /* do you *really* want a second controller? */ +#define N_DRIVE 8 + +/* + * The DMA channel used by the floppy controller cannot access data at + * addresses >= 16MB + * + * Went back to the 1MB limit, as some people had problems with the floppy + * driver otherwise. It doesn't matter much for performance anyway, as most + * floppy accesses go through the track buffer. + * + * On MIPSes using vdma, this actually means that *all* transfers go thru + * the * track buffer since 0x1000000 is always smaller than KSEG0/1. + * Actually this needs to be a bit more complicated since the so much different + * hardware available with MIPS CPUs ... + */ +#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) + +#endif /* __ASM_MIPS_FLOPPY_H */ diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h new file mode 100644 index 000000000..b942b1831 --- /dev/null +++ b/include/asm-mips/fpregdef.h @@ -0,0 +1,52 @@ +/* + * Definitions for the FPU register names + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ +#ifndef __ASM_MIPS_FPREGDEF_H +#define __ASM_MIPS_FPREGDEF_H + +/* + * These definitions only cover the R3000-ish 16/32 register model. + * But we're trying to be R3000 friendly anyway ... + */ +#define fv0 $f0 /* return value */ +#define fv0f $f1 +#define fv1 $f2 +#define fv1f $f3 +#define fa0 $f12 /* argument registers */ +#define fa0f $f13 +#define fa1 $f14 +#define fa1f $f15 +#define ft0 $f4 /* caller saved */ +#define ft0f $f5 +#define ft1 $f6 +#define ft1f $f7 +#define ft2 $f8 +#define ft2f $f9 +#define ft3 $f10 +#define ft3f $f11 +#define ft4 $f16 +#define ft4f $f17 +#define ft5 $f18 +#define ft5f $f19 +#define fs0 $f20 /* callee saved */ +#define fs0f $f21 +#define fs1 $f22 +#define fs1f $f23 +#define fs2 $f24 +#define fs2f $f25 +#define fs3 $f26 +#define fs3f $f27 +#define fs4 $f28 +#define fs4f $f29 +#define fs5 $f30 +#define fs5f $f31 + +#define fcr31 $31 /* FPU status register */ + +#endif /* !defined (__ASM_MIPS_FPREGDEF_H) */ diff --git a/include/asm-mips/ide.h b/include/asm-mips/ide.h new file mode 100644 index 000000000..e6f925e64 --- /dev/null +++ b/include/asm-mips/ide.h @@ -0,0 +1,119 @@ +/* + * linux/include/asm-mips/ide.h + * + * Copyright (C) 1994-1996 Linus Torvalds & authors + */ + +/* + * This file contains the MIPS architecture specific IDE code. + */ + +#ifndef __ASM_MIPS_IDE_H +#define __ASM_MIPS_IDE_H + +#ifdef __KERNEL__ + +typedef unsigned short ide_ioreg_t; + +#ifndef MAX_HWIFS +#define MAX_HWIFS 4 +#endif + +#define ide_sti() sti() + +static __inline__ int ide_default_irq(ide_ioreg_t base) +{ + switch (base) { + case 0x1f0: return 14; + case 0x170: return 15; + case 0x1e8: return 11; + case 0x168: return 10; + default: + return 0; + } +} + +static __inline__ ide_ioreg_t ide_default_io_base(int index) +{ + switch (index) { + case 0: return 0x1f0; + case 1: return 0x170; + case 2: return 0x1e8; + case 3: return 0x168; + default: + return 0; + } +} + +static __inline__ void ide_init_hwif_ports (ide_ioreg_t *p, ide_ioreg_t base, int *irq) +{ + ide_ioreg_t port = base; + int i = 8; + + while (i--) + *p++ = port++; + *p++ = base + 0x206; + if (irq != NULL) + *irq = 0; +} + +typedef union { + unsigned all : 8; /* all of the bits together */ + struct { + unsigned head : 4; /* always zeros here */ + unsigned unit : 1; /* drive select number, 0 or 1 */ + unsigned bit5 : 1; /* always 1 */ + unsigned lba : 1; /* using LBA instead of CHS */ + unsigned bit7 : 1; /* always 1 */ + } b; + } select_t; + +static __inline__ int ide_request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), + unsigned long flags, const char *device, void *dev_id) +{ + return request_irq(irq, handler, flags, device, dev_id); +} + +static __inline__ void ide_free_irq(unsigned int irq, void *dev_id) +{ + free_irq(irq, dev_id); +} + +static __inline__ int ide_check_region (ide_ioreg_t from, unsigned int extent) +{ + return check_region(from, extent); +} + +static __inline__ void ide_request_region (ide_ioreg_t from, unsigned int extent, const char *name) +{ + request_region(from, extent, name); +} + +static __inline__ void ide_release_region (ide_ioreg_t from, unsigned int extent) +{ + release_region(from, extent); +} + +/* + * The following are not needed for the non-m68k ports + */ +static __inline__ int ide_ack_intr (ide_ioreg_t base_port, ide_ioreg_t irq_port) +{ + return(1); +} + +static __inline__ void ide_fix_driveid(struct hd_driveid *id) +{ +} + +static __inline__ void ide_release_lock (int *ide_lock) +{ +} + +static __inline__ void ide_get_lock (int *ide_lock, void (*handler)(int, void *, struct pt_regs *), void *data) +{ +} + +#endif /* __KERNEL__ */ + +#endif /* __ASM_MIPS_IDE_H */ diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h new file mode 100644 index 000000000..c4e291aeb --- /dev/null +++ b/include/asm-mips/inst.h @@ -0,0 +1,304 @@ +/* + * Format of an instruction in memory. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_INST_H +#define __ASM_MIPS_INST_H + +/* + * Major opcodes; before MIPS IV cop1x was called cop3. + */ +enum major_op { + spec_op, bcond_op, j_op, jal_op, + beq_op, bne_op, blez_op, bgtz_op, + addi_op, addiu_op, slti_op, sltiu_op, + andi_op, ori_op, xori_op, lui_op, + cop0_op, cop1_op, cop2_op, cop1x_op, + beql_op, bnel_op, blezl_op, bgtzl_op, + daddi_op, daddiu_op, ldl_op, ldr_op, + major_1c_op, major_1d_op, major_1e_op, major_1f_op, + lb_op, lh_op, lwl_op, lw_op, + lbu_op, lhu_op, lwr_op, lwu_op, + sb_op, sh_op, swl_op, sw_op, + sdl_op, sdr_op, swr_op, cache_op, + ll_op, lwc1_op, lwc2_op, pref_op, + lld_op, ldc1_op, ldc2_op, ld_op, + sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ + scd_op, sdc1_op, sdc2_op, sd_op, +}; + +/* + * func field of spec opcode. + */ +enum spec_op { + sll_op, movc_op, srl_op, sra_op, + sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ + jr_op, jalr_op, movz_op, movn_op, + syscall_op, break_op, spim_op, sync_op, + mfhi_op, mthi_op, mflo_op, mtlo_op, + dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, + mult_op, multu_op, div_op, divu_op, + dmult_op, dmultu_op, ddiv_op, ddivu_op, + add_op, addu_op, sub_op, subu_op, + and_op, or_op, xor_op, nor_op, + spec3_unused_op, spec4_unused_op, slt_op, sltu_op, + dadd_op, daddu_op, dsub_op, dsubu_op, + tge_op, tgeu_op, tlt_op, tltu_op, + teq_op, spec5_unused_op, tne_op, spec6_unused_op, + dsll_op, spec7_unused_op, dsrl_op, dsra_op, + dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op, +}; + +/* + * rt field of bcond opcodes. + */ +enum rt_op { + bltz_op, bgez_op, bltzl_op, bgezl_op, + spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, + tgei_op, tgeiu_op, tlti_op, tltiu_op, + teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, + bltzal_op, bgezal_op, bltzall_op, bgezall_op + /* + * The others (0x14 - 0x1f) are unused. + */ +}; + +/* + * rs field of cop opcodes. + */ +enum cop_op { + mfc_op = 0x00, dmfc_op = 0x01, + cfc_op = 0x02, mtc_op = 0x04, + dmtc_op = 0x05, ctc_op = 0x06, + bc_op = 0x08, cop_op = 0x10, + copm_op = 0x18, +}; + +/* + * func field of cop0 coi opcodes. + */ +enum cop0_coi_func { + tlbr_op = 0x01, tlbwi_op = 0x02, + tlbwr_op = 0x06, tlbp_op = 0x08, + rfe_op = 0x10, eret_op = 0x18 +}; + +/* + * func field of cop0 com opcodes. + */ +enum cop0_com_func { + tlbr1_op = 0x01, tlbw_op = 0x02, + tlbp1_op = 0x08, dctr_op = 0x09, + dctw_op = 0x0a +}; + +/* + * fmt field of cop1 opcodes. + */ +enum cop1_fmt { + s_fmt, d_fmt, e_fmt, q_fmt, + w_fmt, l_fmt +}; + +/* + * func field of cop1 instructions using d, s or w format. + */ +enum cop1_sdw_func { + fadd_op = 0x00, fsub_op = 0x01, + fmul_op = 0x02, fdiv_op = 0x03, + fsqrt_op = 0x04, fabs_op = 0x05, + fmov_op = 0x06, fneg_op = 0x07, + froundl_op = 0x08, ftruncl_op = 0x09, + fceill_op = 0x0a, ffloorl_op = 0x0b, + fround_op = 0x0c, ftrunc_op = 0x0d, + fceil_op = 0x0e, ffloor_op = 0x0f, + fmovc_op = 0x11, fmovz_op = 0x12, + fmovn_op = 0x13, frecip_op = 0x15, + frsqrt_op = 0x16, fcvts_op = 0x20, + fcvtd_op = 0x21, fcvte_op = 0x22, + fcvtw_op = 0x24, fcvtl_op = 0x25, + fcmp_op = 0x30 +}; + +/* + * func field of cop1x opcodes (MIPS IV). + */ +enum cop1x_func { + lwxc1_op = 0x00, ldxc1_op = 0x01, + pfetch_op = 0x07, swxc1_op = 0x08, + sdxc1_op = 0x09, madd_s_op = 0x20, + madd_d_op = 0x21, madd_e_op = 0x22, + msub_s_op = 0x28, msub_d_op = 0x29, + msub_e_op = 0x2a, nmadd_s_op = 0x30, + nmadd_d_op = 0x31, nmadd_e_op = 0x32, + nmsub_s_op = 0x38, nmsub_d_op = 0x39, + nmsub_e_op = 0x3a +}; + +/* + * func field for mad opcodes (MIPS IV). + */ +enum mad_func { + madd_op = 0x08, msub_op = 0x0a, + nmadd_op = 0x0c, nmsub_op = 0x0e +}; + +/* + * Damn ... bitfields depend from byteorder :-( + */ +#ifdef __MIPSEB__ +struct j_format { /* Jump format */ + unsigned int opcode : 6; + unsigned int target : 26; +}; + +struct i_format { /* Immediate format (addi, lw, ...) */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + signed int simmediate : 16; +}; + +struct u_format { /* Unsigned immediate format (ori, xori, ...) */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + unsigned int uimmediate : 16; +}; + +struct c_format { /* Cache (>= R6000) format */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int c_op : 3; + unsigned int cache : 2; + unsigned int simmediate : 16; +}; + +struct r_format { /* Register format */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + unsigned int rd : 5; + unsigned int re : 5; + unsigned int func : 6; +}; + +struct p_format { /* Performance counter format (R10000) */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + unsigned int rd : 5; + unsigned int re : 5; + unsigned int func : 6; +}; + +struct f_format { /* FPU register format */ + unsigned int opcode : 6; + unsigned int : 1; + unsigned int fmt : 4; + unsigned int rt : 5; + unsigned int rd : 5; + unsigned int re : 5; + unsigned int func : 6; +}; + +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int opcode : 6; + unsigned int fr : 5; + unsigned int ft : 5; + unsigned int fs : 5; + unsigned int fd : 5; + unsigned int func : 4; + unsigned int fmt : 2; +}; + +#elif defined(__MIPSEL__) + +struct j_format { /* Jump format */ + unsigned int target : 26; + unsigned int opcode : 6; +}; + +struct i_format { /* Immediate format */ + signed int simmediate : 16; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct u_format { /* Unsigned immediate format */ + unsigned int uimmediate : 16; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct c_format { /* Cache (>= R6000) format */ + unsigned int simmediate : 16; + unsigned int cache : 2; + unsigned int c_op : 3; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct r_format { /* Register format */ + unsigned int func : 6; + unsigned int re : 5; + unsigned int rd : 5; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct p_format { /* Performance counter format (R10000) */ + unsigned int func : 6; + unsigned int re : 5; + unsigned int rd : 5; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct f_format { /* FPU register format */ + unsigned int func : 6; + unsigned int re : 5; + unsigned int rd : 5; + unsigned int rt : 5; + unsigned int fmt : 4; + unsigned int : 1; + unsigned int opcode : 6; +}; + +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int fmt : 2; + unsigned int func : 4; + unsigned int fd : 5; + unsigned int fs : 5; + unsigned int ft : 5; + unsigned int fr : 5; + unsigned int opcode : 6; +}; + +#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ +#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" +#endif + +union mips_instruction { + unsigned int word; + unsigned short halfword[2]; + unsigned char byte[4]; + struct j_format j_format; + struct i_format i_format; + struct u_format u_format; + struct c_format c_format; + struct r_format r_format; + struct f_format f_format; + struct ma_format ma_format; +}; + +#endif /* __ASM_MIPS_INST_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 94f099066..591f6f46d 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -2,12 +2,15 @@ #define __ASM_MIPS_IO_H #include <asm/mipsconfig.h> +#include <asm/addrspace.h> /* * This file contains the definitions for the MIPS counterpart of the * x86 in/out instructions. This heap of macros and C results in much - * better code than the approach of doing it in plain C, though that's - * probably not needed. + * better code than the approach of doing it in plain C. The macros + * result in code that is to fast for certain hardware. On the other + * side the performance of the string functions should be improved for + * sake of certain devices like EIDE disks that do highspeed polled I/O. * * Ralf * @@ -46,6 +49,90 @@ #endif /* + * Change virtual addresses to physical addresses and vv. + * These are trivial on the 1:1 Linux/MIPS mapping + */ +extern inline unsigned long virt_to_phys(volatile void * address) +{ + return (unsigned long) address - KSEG0; +} + +extern inline void * phys_to_virt(unsigned long address) +{ + return (void *) address + KSEG0; +} + +extern void * ioremap(unsigned long phys_addr, unsigned long size); +extern void iounmap(void *addr); + +/* + * IO bus memory addresses are also 1:1 with the physical address + * FIXME: This assumption is wrong for the Deskstation Tyne + */ +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +/* + * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped + * for the processor. + */ +extern unsigned long isa_slot_offset; + +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the x86 architecture, we just read/write the + * memory location directly. + * + * On MIPS, we have the whole physical address space mapped at all + * times, so "ioremap()" and "iounmap()" do not need to do anything. + * (This isn't true for all machines but we still handle these cases + * with wired TLB entries anyway ...) + */ +extern inline void * ioremap(unsigned long phys_addr, unsigned long size) +{ + return (void *) KSEG1ADDR(phys_addr); +} + +extern inline void iounmap(void *addr) +{ +} + +#define readb(addr) (*(volatile unsigned char *) (isa_slot_offset + (unsigned long)(addr))) +#define readw(addr) (*(volatile unsigned short *) (isa_slot_offset + (unsigned long)(addr))) +#define readl(addr) (*(volatile unsigned int *) (isa_slot_offset + (unsigned long)(addr))) + +#define writeb(b,addr) (*(volatile unsigned char *) (isa_slot_offset + (unsigned long)(addr)) = (b)) +#define writew(b,addr) (*(volatile unsigned short *) (isa_slot_offset + (unsigned long)(addr)) = (b)) +#define writel(b,addr) (*(volatile unsigned int *) (isa_slot_offset + (unsigned long)(addr)) = (b)) + +#define memset_io(a,b,c) memset((void *)(isa_slot_offset + (unsigned long)a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(isa_slot_offset + (unsigned long)(b)),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(isa_slot_offset + (unsigned long)(a)),(b),(c)) + +/* + * We don't have csum_partial_copy_fromio() yet, so we cheat here and + * just copy it. The net code will then do the checksum later. + */ +#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) + +static inline int check_signature(unsigned long io_addr, + const unsigned char *signature, int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +/* * Talk about misusing macros.. */ @@ -57,35 +144,36 @@ __asm__ __volatile__ ("s" #m "\t%0,%1(%2)" #define __OUT(m,s) \ __OUT1(s) __OUT2(m) : : "r" (value), "i" (0), "r" (PORT_BASE+port)); } \ -__OUT1(s##c) __OUT2(m) : : "r" (value), "i" (port), "r" (PORT_BASE)); } \ +__OUT1(s##c) __OUT2(m) : : "r" (value), "ir" (port), "r" (PORT_BASE)); } \ __OUT1(s##_p) __OUT2(m) : : "r" (value), "i" (0), "r" (PORT_BASE+port)); \ SLOW_DOWN_IO; } \ -__OUT1(s##c_p) __OUT2(m) : : "r" (value), "i" (port), "r" (PORT_BASE)); \ +__OUT1(s##c_p) __OUT2(m) : : "r" (value), "ir" (port), "r" (PORT_BASE)); \ SLOW_DOWN_IO; } -#define __IN1(s) \ -extern inline unsigned int __in##s(unsigned int port) { unsigned int _v; +#define __IN1(t,s) \ +extern __inline__ t __in##s(unsigned int port) { t _v; /* - * Useless nops will be removed by the assembler + * Required nops will be inserted by the assembler */ #define __IN2(m) \ -__asm__ __volatile__ ("l" #m "u\t%0,%1(%2)\n\tnop" +__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" -#define __IN(m,s) \ -__IN1(s) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); return _v; } \ -__IN1(s##c) __IN2(m) : "=r" (_v) : "i" (port), "r" (PORT_BASE)); return _v; } \ -__IN1(s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); SLOW_DOWN_IO; return _v; } \ -__IN1(s##c_p) __IN2(m) : "=r" (_v) : "i" (port), "r" (PORT_BASE)); SLOW_DOWN_IO; return _v; } +#define __IN(t,m,s) \ +__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); return _v; } \ +__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (PORT_BASE)); return _v; } \ +__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); SLOW_DOWN_IO; return _v; } \ +__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (PORT_BASE)); SLOW_DOWN_IO; return _v; } #define __INS1(s) \ extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { #define __INS2(m) \ +if (count) \ __asm__ __volatile__ ( \ ".set\tnoreorder\n\t" \ ".set\tnoat\n" \ - "1:\tl" #m "u\t$1,%4(%5)\n\t" \ + "1:\tl" #m "\t$1,%4(%5)\n\t" \ "subu\t%1,1\n\t" \ "s" #m "\t$1,(%0)\n\t" \ "bne\t$0,%1,1b\n\t" \ @@ -100,21 +188,22 @@ __INS1(s) __INS2(m) \ : "$1");} \ __INS1(s##c) __INS2(m) \ : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (port), "r" (PORT_BASE), "I" (i) \ + : "0" (addr), "1" (count), "ir" (port), "r" (PORT_BASE), "I" (i) \ : "$1");} #define __OUTS1(s) \ extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { #define __OUTS2(m) \ +if (count) \ __asm__ __volatile__ ( \ ".set\tnoreorder\n\t" \ ".set\tnoat\n" \ - "1:\tl" #m "u\t$1,(%0)\n\t" \ - "subu\t%1,%1,1\n\t" \ + "1:\tl" #m "\t$1,(%0)\n\t" \ + "subu\t%1,1\n\t" \ "s" #m "\t$1,%4(%5)\n\t" \ "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%0,%6\n\t" \ + "addiu\t%0,%6\n\t" \ ".set\tat\n\t" \ ".set\treorder" @@ -125,12 +214,12 @@ __OUTS1(s) __OUTS2(m) \ : "$1");} \ __OUTS1(s##c) __OUTS2(m) \ : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (port), "r" (PORT_BASE), "I" (i) \ + : "0" (addr), "1" (count), "ir" (port), "r" (PORT_BASE), "I" (i) \ : "$1");} -__IN(b,b) -__IN(h,w) -__IN(w,l) +__IN(unsigned char,b,b) +__IN(unsigned short,h,w) +__IN(unsigned int,w,l) __OUT(b,b) __OUT(h,w) @@ -146,7 +235,7 @@ __OUTS(w,l,4) /* * Note that due to the way __builtin_constant_p() works, you - * - can't use it inside a inline function (it will never be true) + * - can't use it inside an inline function (it will never be true) * - you don't have to worry about side effects within the __builtin.. */ #define outb(val,port) \ diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h new file mode 100644 index 000000000..360b22ce3 --- /dev/null +++ b/include/asm-mips/ioctl.h @@ -0,0 +1,90 @@ +/* + * Linux ioctl() stuff. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_IOCTL_H +#define __ASM_MIPS_IOCTL_H + +/* + * The original linux ioctl numbering scheme was just a general + * "anything goes" setup, where more or less random numbers were + * assigned. Sorry, I was clueless when I started out on this. + * + * On the alpha, we'll try to clean it up a bit, using a more sane + * ioctl numbering, and also trying to be compatible with OSF/1 in + * the process. I'd like to clean it up for the i386 as well, but + * it's so painful recognizing both the new and the old numbers.. + * + * The same applies for for the MIPS ABI; in fact even the macros + * from Linux/Alpha fit almost perfectly. + */ + +#define _IOC_NRBITS 8 +#define _IOC_TYPEBITS 8 +#define _IOC_SIZEBITS 13 +#define _IOC_DIRBITS 3 + +#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) +#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) +#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) +#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) + +#define _IOC_NRSHIFT 0 +#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) +#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) +#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) + +/* + * We to additionally limit parameters to a maximum 255 bytes. + */ +#define _IOC_SLMASK 0xff + +/* + * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. + * And this turns out useful to catch old ioctl numbers in header + * files for us. + */ +#define _IOC_NONE 1U +#define _IOC_READ 2U +#define _IOC_WRITE 4U + +/* + * The following are included for compatibility + */ +#define _IOC_VOID 0x20000000 +#define _IOC_OUT 0x40000000 +#define _IOC_IN 0x80000000 +#define _IOC_INOUT (IOC_IN|IOC_OUT) + +#define _IOC(dir,type,nr,size) \ + (((dir) << _IOC_DIRSHIFT) | \ + ((type) << _IOC_TYPESHIFT) | \ + ((nr) << _IOC_NRSHIFT) | \ + (((size) & _IOC_SLMASK) << _IOC_SIZESHIFT)) + +/* used to create numbers */ +#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) +#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) +#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) + +/* used to decode them.. */ +#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) +#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) +#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) +#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) + +/* ...and for the drivers/sound files... */ + +#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) +#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) +#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) +#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) +#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) + +#endif /* __ASM_MIPS_IOCTL_H */ diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h new file mode 100644 index 000000000..9ec2c0215 --- /dev/null +++ b/include/asm-mips/ioctls.h @@ -0,0 +1,112 @@ +/* + * ioctls for Linux/MIPS. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_IOCTLS_H +#define __ASM_MIPS_IOCTLS_H + +#include <asm/ioctl.h> + +#if defined(__USE_MISC) || defined (__KERNEL__) +#define tIOC ('t' << 8) +#endif + +#define TCGETA 0x5401 +#define TCSETA 0x5402 +#define TCSETAW 0x5403 +#define TCSETAF 0x5404 + +#define TCSBRK 0x5405 +#define TCXONC 0x5406 +#define TCFLSH 0x5407 + +#define TCGETS 0x540d +#define TCSETS 0x540e +#define TCSETSW 0x540f +#define TCSETSF 0x5410 + +#define TIOCEXCL 0x740d /* set exclusive use of tty */ +#define TIOCNXCL 0x740e /* reset exclusive use of tty */ +#define TIOCOUTQ 0x7472 /* output queue size */ +#define TIOCSTI 0x5472 /* simulate terminal input */ +#define TIOCMGET 0x741d /* get all modem bits */ +#define TIOCMBIS 0x741b /* bis modem bits */ +#define TIOCMBIC 0x741c /* bic modem bits */ +#define TIOCMSET 0x741a /* set all modem bits */ +#define TIOCPKT 0x5470 /* pty: set/clear packet mode */ +#define TIOCPKT_DATA 0x00 /* data packet */ +#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */ +#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */ +#define TIOCPKT_STOP 0x04 /* stop output */ +#define TIOCPKT_START 0x08 /* start output */ +#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */ +#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */ +#if 0 +#define TIOCPKT_IOCTL 0x40 /* state change of pty driver */ +#endif +#define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */ +#define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */ +#define TIOCNOTTY 0x5471 /* void tty association */ +#define TIOCSETD (tIOC | 1) +#define TIOCGETD (tIOC | 0) + +#define FIOCLEX 0x6601 +#define FIONCLEX 0x6602 /* these numbers need to be adjusted. */ +#define FIOASYNC 0x667d +#define FIONBIO 0x667e + +#if defined(__USE_MISC) || defined (__KERNEL__) +#define TIOCGLTC (tIOC | 116) /* get special local chars */ +#define TIOCSLTC (tIOC | 117) /* set special local chars */ +#endif +#define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */ +#define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */ +#define TIOCCONS _IOW('t', 120, int) /* become virtual console */ + +#define FIONREAD 0x467f +#define TIOCINQ FIONREAD + +#if defined(__USE_MISC) || defined (__KERNEL__) +#define TIOCGETP (tIOC | 8) +#define TIOCSETP (tIOC | 9) +#define TIOCSETN (tIOC | 10) /* TIOCSETP wo flush */ +#endif + +#if 0 +#define TIOCSETA _IOW('t', 20, struct termios) /* set termios struct */ +#define TIOCSETAW _IOW('t', 21, struct termios) /* drain output, set */ +#define TIOCSETAF _IOW('t', 22, struct termios) /* drn out, fls in, set */ +#define TIOCGETD _IOR('t', 26, int) /* get line discipline */ +#define TIOCSETD _IOW('t', 27, int) /* set line discipline */ + /* 127-124 compat */ +#endif + +/* I hope the range from 0x5480 on is free ... */ +#define TIOCSCTTY 0x5480 /* become controlling tty */ +#define TIOCGSOFTCAR 0x5481 +#define TIOCSSOFTCAR 0x5482 +#define TIOCLINUX 0x5483 +#define TIOCGSERIAL 0x5484 +#define TIOCSSERIAL 0x5485 + +#define TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */ +#define TIOCTTYGSTRUCT 0x5487 /* For debugging only */ + +#define TIOCSERCONFIG 0x5488 +#define TIOCSERGWILD 0x5489 +#define TIOCSERSWILD 0x548a +#define TIOCGLCKTRMIOS 0x548b +#define TIOCSLCKTRMIOS 0x548c +#define TIOCSERGSTRUCT 0x548d /* For debugging only */ +#define TIOCSERGETLSR 0x548e /* Get line status register */ +#define TIOCSERGETMULTI 0x548f /* Get multiport config */ +#define TIOCSERSETMULTI 0x5490 /* Set multiport config */ +#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */ +#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */ + +#endif /* __ASM_MIPS_IOCTLS_H */ diff --git a/include/asm-mips/ipc.h b/include/asm-mips/ipc.h new file mode 100644 index 000000000..3288c1e28 --- /dev/null +++ b/include/asm-mips/ipc.h @@ -0,0 +1,29 @@ +#ifndef __ASM_MIPS_IPC_H +#define __ASM_MIPS_IPC_H + +/* + * These are used to wrap system calls on MIPS. + * + * See arch/mips/kernel/sysmips.c for ugly details.. + * FIXME: split up into ordinary syscalls ... + */ +struct ipc_kludge { + struct msgbuf *msgp; + long msgtyp; +}; + +#define SEMOP 1 +#define SEMGET 2 +#define SEMCTL 3 +#define MSGSND 11 +#define MSGRCV 12 +#define MSGGET 13 +#define MSGCTL 14 +#define SHMAT 21 +#define SHMDT 22 +#define SHMGET 23 +#define SHMCTL 24 + +#define IPCCALL(version,op) ((version)<<16 | (op)) + +#endif /* __ASM_MIPS_IPC_H */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 4c5191fef..e6bc9ae3c 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -12,6 +12,15 @@ #ifndef __ASM_MIPS_IRQ_H #define __ASM_MIPS_IRQ_H +/* + * Actually this is a lie but we hide the local device's interrupts ... + */ +#define NR_IRQS 16 + +#define TIMER_IRQ 0 + +struct irqaction; +extern int setup_x86_irq(int irq, struct irqaction * new); extern void disable_irq(unsigned int); extern void enable_irq(unsigned int); diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h index 2e6a3cc2d..9a3dbccf0 100644 --- a/include/asm-mips/jazz.h +++ b/include/asm-mips/jazz.h @@ -9,7 +9,6 @@ * * This file is a mess. It really needs some reorganisation! */ - #ifndef __ASM_MIPS_JAZZ_H #define __ASM_MIPS_JAZZ_H @@ -53,7 +52,7 @@ * Some characters for the LED control registers * The original Mips machines seem to have a LED display * with integrated decoder while the Acer machines can - * control each of the seven segments and the dot independend. + * control each of the seven segments and the dot independently. * It's only a toy, anyway... */ #define LED_DOT 0x01 @@ -87,6 +86,16 @@ extern __inline__ void pica_set_led(unsigned int bits) #endif /* + * Base address of the Sonic Ethernet adapter in Jazz machines. + */ +#define JAZZ_ETHERNET_BASE 0xe0001000 + +/* + * Base address of the 53C94 SCSI hostadapter in Jazz machines. + */ +#define JAZZ_SCSI_BASE 0xe0002000 + +/* * i8042 keyboard controller for JAZZ and PICA chipsets. * This address is just a guess and seems to differ from * other mips machines such as RC3xxx... @@ -126,7 +135,6 @@ typedef struct { /* * Serial and parallel ports (WD 16C552) on the Mips JAZZ */ - #define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000 #define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000 #define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000 @@ -134,7 +142,6 @@ typedef struct { /* * Dummy Device Address. Used in jazzdma.c */ - #define JAZZ_DUMMY_DEVICE 0xe000d000 /* @@ -196,10 +203,9 @@ typedef struct { /* * JAZZ Interrupt Level definitions */ - #define JAZZ_TIMER_IRQ 0 #define JAZZ_KEYBOARD_IRQ 1 -#define JAZZ_ETHERNET_IRQ 2 /* 15 */ +#define JAZZ_ETHERNET_IRQ 13 #define JAZZ_SERIAL1_IRQ 3 #define JAZZ_SERIAL2_IRQ 4 #define JAZZ_PARALLEL_IRQ 5 @@ -211,7 +217,6 @@ typedef struct { * Note: Channels 4...7 are not used with respect to the Acer PICA-61 * chipset which does not provide these DMA channels. */ - #define JAZZ_SCSI_DMA 0 /* SCSI */ #define JAZZ_FLOPPY_DMA 1 /* FLOPPY */ #define JAZZ_AUDIOL_DMA 2 /* AUDIO L */ @@ -221,7 +226,6 @@ typedef struct { * JAZZ R4030 MCT_ADR chip (DMA controller) * Note: Virtual Addresses ! */ - #define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */ #define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */ #define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */ @@ -232,7 +236,7 @@ typedef struct { #define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */ #define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */ -#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Adresss */ +#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */ #define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */ #define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */ @@ -247,68 +251,64 @@ typedef struct { * 8: parallel, 9: NVRAM, 10: CPU, 11: PROM, * 12: reserved, 13: free, 14: 7seg LED, 15: ??? */ - #define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */ /* 0xE0000070,78,80... 0xE00000E8 */ #define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */ - -#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Reg */ +#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */ +#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */ #define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */ +/* + * Virtual (E)ISA controller address + */ +#define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */ /* * Access the R4030 DMA and I/O Controller */ - #ifndef __LANGUAGE_ASSEMBLY__ -extern inline unsigned short r4030_read_reg16(unsigned addr) { +extern inline void r4030_delay(void) +{ +__asm__ __volatile__( + ".set\tnoreorder\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\treorder"); +} + +extern inline unsigned short r4030_read_reg16(unsigned addr) +{ unsigned short ret = *((volatile unsigned short *)addr); - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".set\treorder"); + r4030_delay(); return ret; } -extern inline unsigned int r4030_read_reg32(unsigned addr) { +extern inline unsigned int r4030_read_reg32(unsigned addr) +{ unsigned int ret = *((volatile unsigned int *)addr); - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".set\treorder"); + r4030_delay(); return ret; } -extern inline void r4030_write_reg16(unsigned addr, unsigned val) { +extern inline void r4030_write_reg16(unsigned addr, unsigned val) +{ *((volatile unsigned short *)addr) = val; - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".set\treorder"); + r4030_delay(); } -extern inline unsigned int r4030_write_reg32(unsigned addr, unsigned val) { +extern inline unsigned int r4030_write_reg32(unsigned addr, unsigned val) +{ *((volatile unsigned int *)addr) = val; - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".set\treorder"); + r4030_delay(); } #endif /* !LANGUAGE_ASSEMBLY__ */ - +#define JAZZ_FDC_BASE 0xe0003000 + +#define JAZZ_RTC_BASE 0xe0004000 + #endif /* __ASM_MIPS_JAZZ_H */ diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h index 292a16177..c7f1730cf 100644 --- a/include/asm-mips/jazzdma.h +++ b/include/asm-mips/jazzdma.h @@ -1,14 +1,12 @@ /* * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support */ - -#ifndef __ASM_JAZZDMA_H -#define __ASM_JAZZDMA_H +#ifndef __ASM_MIPS_JAZZDMA_H +#define __ASM_MIPS_JAZZDMA_H /* * Prototypes and macros */ - unsigned long vdma_init(unsigned long memory_start, unsigned long memory_end); unsigned long vdma_alloc(unsigned long paddr, unsigned long size); int vdma_free(unsigned long laddr); @@ -27,7 +25,6 @@ int vdma_get_residue(int channel); /* * some definitions used by the driver functions */ - #define VDMA_PAGESIZE 4096 #define VDMA_PGTBL_ENTRIES 4096 #define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES) @@ -44,13 +41,11 @@ int vdma_get_residue(int channel); * error code returned by vdma_alloc() * (See also arch/mips/kernel/jazzdma.c) */ - #define VDMA_ERROR 0xffffffff /* * VDMA pagetable entry description */ - typedef volatile struct VDMA_PGTBL_ENTRY { unsigned int frame; /* physical frame no. */ @@ -62,7 +57,6 @@ typedef volatile struct VDMA_PGTBL_ENTRY * DMA channel control registers * in the R4030 MCT_ADR chip */ - #define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */ /* 0xE0000100,120,140... */ #define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ @@ -80,8 +74,9 @@ typedef volatile struct VDMA_PGTBL_ENTRY #define R4030_MEM_INTR (1<<9) #define R4030_ADDR_INTR (1<<10) -/* channel mode register bits */ - +/* + * Channel mode register bits + */ #define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ #define R4030_MODE_ATIME_80 (1) #define R4030_MODE_ATIME_120 (2) @@ -97,4 +92,4 @@ typedef volatile struct VDMA_PGTBL_ENTRY #define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ #define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ -#endif /* __ASM_JAZZDMA_H */ +#endif /* __ASM_MIPS_JAZZDMA_H */ diff --git a/include/asm-mips/keyboard.h b/include/asm-mips/keyboard.h new file mode 100644 index 000000000..3c5c7ce65 --- /dev/null +++ b/include/asm-mips/keyboard.h @@ -0,0 +1,309 @@ +/* + * CPU specific parts of the keyboard driver + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_MIPS_KEYBOARD_H +#define __ASM_MIPS_KEYBOARD_H + +#include <linux/config.h> + +/* + * The default IO slowdown is doing 'inb()'s from 0x61, which should be + * safe. But as that is the keyboard controller chip address, we do our + * slowdowns here by doing short jumps: the keyboard controller should + * be able to keep up + */ +#define REALLY_SLOW_IO +#define SLOW_IO_BY_JUMPING +#include <asm/io.h> +#include <asm/bootinfo.h> +#include <asm/jazz.h> + +/* + * Not true for Jazz machines, we cheat a bit for 'em. + */ +#define KEYBOARD_IRQ 1 + +static int initialize_kbd(void); + +int (*kbd_inb_p)(unsigned short port); +int (*kbd_inb)(unsigned short port); +void (*kbd_outb_p)(unsigned char data, unsigned short port); +void (*kbd_outb)(unsigned char data, unsigned short port); + +#ifdef CONFIG_MIPS_JAZZ +/* + * We want the full initialization for the keyboard controller. + */ +#define INIT_KBD + +static volatile keyboard_hardware *kh = (void *) JAZZ_KEYBOARD_ADDRESS; + +static int +jazz_kbd_inb_p(unsigned short port) +{ + int result; + + if(port == KBD_DATA_REG) + result = kh->data; + else /* Must be KBD_STATUS_REG */ + result = kh->command; + inb(0x80); + + return result; +} + +static int +jazz_kbd_inb(unsigned short port) +{ + int result; + + if(port == KBD_DATA_REG) + result = kh->data; + else /* Must be KBD_STATUS_REG */ + result = kh->command; + + return result; +} + +static void +jazz_kbd_outb_p(unsigned char data, unsigned short port) +{ + if(port == KBD_DATA_REG) + kh->data = data; + else if(port == KBD_CNTL_REG) + kh->command = data; + inb(0x80); +} + +static void +jazz_kbd_outb(unsigned char data, unsigned short port) +{ + if(port == KBD_DATA_REG) + kh->data = data; + else if(port == KBD_CNTL_REG) + kh->command = data; +} +#endif /* CONFIG_MIPS_JAZZ */ + +/* + * Most other MIPS machines access the keyboard controller via + * ordinary I/O ports. + */ +static int +port_kbd_inb_p(unsigned short port) +{ + return inb_p(port); +} + +static int +port_kbd_inb(unsigned short port) +{ + return inb(port); +} + +static void +port_kbd_outb_p(unsigned char data, unsigned short port) +{ + return outb_p(data, port); +} + +static void +port_kbd_outb(unsigned char data, unsigned short port) +{ + return outb(data, port); +} + +#ifdef INIT_KBD +static int +kbd_wait_for_input(void) +{ + int n; + int status, data; + + n = TIMEOUT_CONST; + do { + status = kbd_inb(KBD_STATUS_REG); + /* + * Wait for input data to become available. This bit will + * then be cleared by the following read of the DATA + * register. + */ + + if (!(status & KBD_OBF)) + continue; + + data = kbd_inb(KBD_DATA_REG); + + /* + * Check to see if a timeout error has occurred. This means + * that transmission was started but did not complete in the + * normal time cycle. PERR is set when a parity error occurred + * in the last transmission. + */ + if (status & (KBD_GTO | KBD_PERR)) { + continue; + } + return (data & 0xff); + } while (--n); + return (-1); /* timed-out if fell through to here... */ +} + +static void kbd_write(int address, int data) +{ + int status; + + do { + status = kbd_inb(KBD_STATUS_REG); /* spin until input buffer empty*/ + } while (status & KBD_IBF); + kbd_outb(data, address); /* write out the data*/ +} + +static int initialize_kbd(void) +{ + unsigned long flags; + + save_flags(flags); cli(); + + /* Flush any pending input. */ + while (kbd_wait_for_input() != -1) + continue; + + /* + * Test the keyboard interface. + * This seems to be the only way to get it going. + * If the test is successful a x55 is placed in the input buffer. + */ + kbd_write(KBD_CNTL_REG, KBD_SELF_TEST); + if (kbd_wait_for_input() != 0x55) { + printk(KERN_WARNING "initialize_kbd: " + "keyboard failed self test.\n"); + restore_flags(flags); + return(-1); + } + + /* + * Perform a keyboard interface test. This causes the controller + * to test the keyboard clock and data lines. The results of the + * test are placed in the input buffer. + */ + kbd_write(KBD_CNTL_REG, KBD_SELF_TEST2); + if (kbd_wait_for_input() != 0x00) { + printk(KERN_WARNING "initialize_kbd: " + "keyboard failed self test 2.\n"); + restore_flags(flags); + return(-1); + } + + /* Enable the keyboard by allowing the keyboard clock to run. */ + kbd_write(KBD_CNTL_REG, KBD_CNTL_ENABLE); + + /* + * Reset keyboard. If the read times out + * then the assumption is that no keyboard is + * plugged into the machine. + * This defaults the keyboard to scan-code set 2. + */ + kbd_write(KBD_DATA_REG, KBD_RESET); + if (kbd_wait_for_input() != KBD_ACK) { + printk(KERN_WARNING "initialize_kbd: " + "reset kbd failed, no ACK.\n"); + restore_flags(flags); + return(-1); + } + + /* + * Give the keyboard some time to breathe ... + * ... or it fucks up the floppy controller, too. Wiered. + */ + udelay(20); + + if (kbd_wait_for_input() != KBD_POR) { + printk(KERN_WARNING "initialize_kbd: " + "reset kbd failed, not POR.\n"); + restore_flags(flags); + return(-1); + } + + /* + * now do a DEFAULTS_DISABLE always + */ + kbd_write(KBD_DATA_REG, KBD_DISABLE); + if (kbd_wait_for_input() != KBD_ACK) { + printk(KERN_WARNING "initialize_kbd: " + "disable kbd failed, no ACK.\n"); + restore_flags(flags); + return(-1); + } + + /* + * Enable keyboard interrupt, operate in "sys" mode, + * enable keyboard (by clearing the disable keyboard bit), + * disable mouse, do conversion of keycodes. + */ + kbd_write(KBD_CNTL_REG, KBD_WRITE_MODE); + kbd_write(KBD_DATA_REG, KBD_EKI|KBD_SYS|KBD_DMS|KBD_KCC); + + /* + * now ENABLE the keyboard to set it scanning... + */ + kbd_write(KBD_DATA_REG, KBD_ENABLE); + if (kbd_wait_for_input() != KBD_ACK) { + printk(KERN_WARNING "initialize_kbd: " + "keyboard enable failed.\n"); + restore_flags(flags); + return(-1); + } + + restore_flags(flags); + + return (1); +} +#endif + +extern __inline__ void +keyboard_setup(void) +{ +#ifdef CONFIG_MIPS_JAZZ + if (mips_machgroup == MACH_GROUP_JAZZ) { + kbd_inb_p = jazz_kbd_inb_p; + kbd_inb = jazz_kbd_inb; + kbd_outb_p = jazz_kbd_outb_p; + kbd_outb = jazz_kbd_outb; + /* + * Enable keyboard interrupts. + */ + *((volatile u16 *)JAZZ_IO_IRQ_ENABLE) |= JAZZ_IE_KEYBOARD; + set_cp0_status(IE_IRQ1, IE_IRQ1); + initialize_kbd(); + } else +#endif + if (mips_machgroup == MACH_GROUP_ARC || /* this is for Deskstation */ + (mips_machgroup == MACH_GROUP_SNI_RM + && mips_machtype == MACH_SNI_RM200_PCI)) { + /* + * These machines address their keyboard via the normal + * port address range. + * + * Also enable Scan Mode 2. + */ + kbd_inb_p = port_kbd_inb_p; + kbd_inb = port_kbd_inb; + kbd_outb_p = port_kbd_outb_p; + kbd_outb = port_kbd_outb; + request_region(0x60,16,"keyboard"); + + kb_wait(); + kbd_outb(0x60, 0x64); /* 60 == PS/2 MODE ?? */ + kb_wait(); + kbd_outb(0x41, 0x60); /* 4d:same as freebsd, 41:KCC+EKI */ + kb_wait(); + if (!send_data(0xf0) || !send_data(0x02)) + printk("Scanmode 2 change failed\n"); + } +} + +#endif /* __ASM_MIPS_KEYBOARD_H */ diff --git a/include/asm-mips/mc146818rtc.h b/include/asm-mips/mc146818rtc.h new file mode 100644 index 000000000..0e2700526 --- /dev/null +++ b/include/asm-mips/mc146818rtc.h @@ -0,0 +1,26 @@ +/* + * Machine dependent access functions for RTC registers. + */ +#ifndef __ASM_MIPS_MC146818RTC_H +#define __ASM_MIPS_MC146818RTC_H + +#include <asm/io.h> +#include <asm/vector.h> + +#ifndef RTC_PORT +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_ALWAYS_BCD 0 /* RTC operates in binary mode */ +#endif + +/* + * The yet supported machines all access the RTC index register via + * an ISA port access but the way to access the date register differs ... + */ +#define CMOS_READ(addr) ({ \ +feature->rtc_read_data(addr); \ +}) +#define CMOS_WRITE(val, addr) ({ \ +feature->rtc_write_data(val, addr); \ +}) + +#endif /* __ASM_MIPS_MC146818RTC_H */ diff --git a/include/asm-mips/mipsconfig.h b/include/asm-mips/mipsconfig.h index 1648f7c7e..01316c11b 100644 --- a/include/asm-mips/mipsconfig.h +++ b/include/asm-mips/mipsconfig.h @@ -5,9 +5,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Waldorf Electronics - * written by Ralf Baechle + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * This file contains constant definitions and some MIPS specific debug and + * other compile time switches. */ + #ifndef __ASM_MIPS_MIPSCONFIG_H #define __ASM_MIPS_MIPSCONFIG_H @@ -15,13 +18,23 @@ * This is the virtual address to which all ports are being mapped. * Must be a value that can be load with a lui instruction. */ +#define PORT_BASE_SNI 0xb4000000 +#define PORT_BASE_RPC44 0xe2000000 +#define PORT_BASE_TYNE 0xe2000000 +#define PORT_BASE_JAZZ 0xe2000000 #ifndef PORT_BASE -#define PORT_BASE 0xe2000000 +#if !defined (__LANGUAGE_ASSEMBLY__) +extern unsigned long port_base; +#endif +#define PORT_BASE port_base #endif /* * Pagetables are 4MB mapped at 0xe4000000 * Must be a value that can be loaded with a single instruction. + * The xtlb exception handler assumes that bit 30 and 31 of TLBMAP + * are the same. This is true for all KSEG2 and KSEG3 addresses and + * will therefore not a problem. */ #define TLBMAP 0xe4000000 @@ -35,15 +48,4 @@ */ #define TLB_ROOT 0xe4390000 -/* - * Use this to activate extra TLB error checking - */ -#define CONFIG_DEBUG_TLB - -/* - * Use this to activate extra TLB profiling code - * (currently not implemented) - */ -#undef CONFIG_PROFILE_TLB - #endif /* __ASM_MIPS_MIPSCONFIG_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 466c8b12b..12666127e 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -5,17 +5,18 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Ralf Baechle + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * Modified for further R[236]000 support by Paul M. Antoine, 1996. */ - #ifndef __ASM_MIPS_MIPSREGS_H #define __ASM_MIPS_MIPSREGS_H +#include <linux/linkage.h> + /* * The following macros are especially useful for __asm__ * inline assembler. */ - #ifndef __STR #define __STR(x) #x #endif @@ -24,15 +25,21 @@ #endif /* - * On the R2000/3000 load instructions are not interlocked - - * we therefore sometimes need to fill load delay slots with a nop - * which would be useless for ISA >= 2. + * Assigned values for the product ID register. In order to detect a + * certain CPU type exactly eventually additional registers may need to + * be examined. */ -#if !defined (__R4000__) -#define FILL_LDS nop -#else -#define FILL_LDS -#endif +#define PRID_R3000A 0x02 +#define PRID_R4000 0x04 +#define PRID_R4400 0x04 +#define PRID_R4300 0x0b +#define PRID_R4600 0x20 +#define PRID_R4700 0x21 +#define PRID_R4640 0x22 +#define PRID_R4650 0x22 +#define PRID_R5000 0x23 +#define PRID_SONIC 0x24 +#define PRID_R10000 0x09 /* * Coprocessor 0 register names @@ -67,9 +74,22 @@ #define CP0_ERROREPC $30 /* - * Coprocessor 1 (FPU) register names + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 +/* + * Coprocessor 1 (FPU) register names + */ #define CP1_REVISION $0 #define CP1_STATUS $31 @@ -177,9 +197,14 @@ BUILD_SET_CP0(cause,CP0_CAUSE) /* * Inline code for use of the ll and sc instructions * - * FIXME: This instruction is only available on MIPS ISA >=3. + * FIXME: This instruction is only available on MIPS ISA >=2. * Since these operations are only being used for atomic operations * the easiest workaround for the R[23]00 is to disable interrupts. + * This fails for R3000 SMP machines which use that many different + * technologies as replacement that it is difficult to create even + * just a hook for for all machines to hook into. The only good + * thing is that there is currently no R3000 SMP machine on the + * Linux/MIPS target list ... */ #define load_linked(addr) \ ({ \ @@ -188,7 +213,7 @@ BUILD_SET_CP0(cause,CP0_CAUSE) __asm__ __volatile__( \ "ll\t%0,(%1)" \ : "=r" (__res) \ - : "r" ((unsigned int) (addr))); \ + : "r" ((unsigned long) (addr))); \ \ __res; \ }) @@ -206,10 +231,7 @@ BUILD_SET_CP0(cause,CP0_CAUSE) }) /* - * Bitfields in the cp0 status register - * - * Refer to the MIPS R4xx0 manuals, chapter 5 for explanation. - * FIXME: This doesn't cover all R4xx0 processors. + * Bitfields in the R4xx0 cp0 status register */ #define ST0_IE (1 << 0) #define ST0_EXL (1 << 1) @@ -221,6 +243,28 @@ BUILD_SET_CP0(cause,CP0_CAUSE) #define ST0_UX (1 << 5) #define ST0_SX (1 << 6) #define ST0_KX (1 << 7) + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC (1 << 0) +#define ST0_KUC (1 << 1) +#define ST0_IEP (1 << 2) +#define ST0_KUP (1 << 3) +#define ST0_IEO (1 << 4) +#define ST0_KUO (1 << 5) +/* bits 6 & 7 are reserved on R[23]000 */ + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM <1 << 4) +#define ST0_IL (1 << 23) +#define ST0_DL (1 << 24) + +/* + * Status register bits available in all MIPS CPUs. + */ #define ST0_IM (255 << 8) #define ST0_DE (1 << 16) #define ST0_CE (1 << 17) @@ -234,6 +278,7 @@ BUILD_SET_CP0(cause,CP0_CAUSE) #define ST0_CU1 (1 << 29) #define ST0_CU2 (1 << 30) #define ST0_CU3 (1 << 31) +#define ST0_XX (1 << 31) /* MIPS IV naming */ /* * Bitfields and bit numbers in the coprocessor 0 cause register. @@ -265,4 +310,77 @@ BUILD_SET_CP0(cause,CP0_CAUSE) #define CAUSEB_BD 31 #define CAUSEF_BD (1 << 31) +/* + * Bits in the coprozessor 0 config register. + */ +#define CONFIG_DB (1<<4) +#define CONFIG_IB (1<<5) +#define CONFIG_SC (1<<17) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + +#ifndef __LANGUAGE_ASSEMBLY__ +/* + * Functions to access the performance counter and control registers + */ +extern asmlinkage unsigned int read_perf_cntr(unsigned int counter); +extern asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val); +extern asmlinkage unsigned int read_perf_cntl(unsigned int counter); +extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val); +#endif + #endif /* __ASM_MIPS_MIPSREGS_H */ diff --git a/include/asm-mips/mman.h b/include/asm-mips/mman.h new file mode 100644 index 000000000..f95aec1e6 --- /dev/null +++ b/include/asm-mips/mman.h @@ -0,0 +1,63 @@ +/* + * Linux/MIPS memory manager definitions + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MMAN_H +#define __ASM_MIPS_MMAN_H + +/* + * Protections are chosen from these bits, OR'd together. The + * implementation does not necessarily support PROT_EXEC or PROT_WRITE + * without PROT_READ. The only guarantees are that no writing will be + * allowed without PROT_WRITE and no access will be allowed for PROT_NONE. + */ +#define PROT_NONE 0x0 /* page can not be accessed */ +#define PROT_READ 0x1 /* page can be read */ +#define PROT_WRITE 0x2 /* page can be written */ +#define PROT_EXEC 0x4 /* page can be executed */ + +/* + * Flags for mmap + */ +#define MAP_SHARED 0x001 /* Share changes */ +#define MAP_PRIVATE 0x002 /* Changes are private */ +#define MAP_TYPE 0x00f /* Mask for type of mapping */ +#define MAP_FIXED 0x010 /* Interpret addr exactly */ + +/* not used by linux, but here to make sure we don't clash with ABI defines */ +#define MAP_RENAME 0x020 /* Assign page to file */ +#define MAP_AUTOGROW 0x040 /* File may grow by writing */ +#define MAP_LOCAL 0x080 /* Copy on fork/sproc */ +#define MAP_AUTORSRV 0x100 /* Logical swap reserved on demand */ + +/* These are linux-specific */ +#define MAP_NORESERVE 0x0400 /* don't check for reservations */ +#define MAP_ANONYMOUS 0x0800 /* don't use a file */ +#define MAP_GROWSDOWN 0x1000 /* stack-like segment */ +#define MAP_DENYWRITE 0x2000 /* ETXTBSY */ +#define MAP_EXECUTABLE 0x4000 /* mark it as an executable */ +#define MAP_LOCKED 0x8000 /* pages are locked */ + +/* + * Flags for msync + */ +#define MS_SYNC 0 /* synchronous memory sync */ +#define MS_ASYNC 1 /* sync memory asynchronously */ +#define MS_INVALIDATE 2 /* invalidate mappings & caches */ + +/* + * Flags for mlockall + */ +#define MCL_CURRENT 1 /* lock all current mappings */ +#define MCL_FUTURE 2 /* lock all future mappings */ + +/* compatibility flags */ +#define MAP_ANON MAP_ANONYMOUS +#define MAP_FILE 0 + +#endif /* __ASM_MIPS_MMAN_H */ diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h new file mode 100644 index 000000000..5a61279da --- /dev/null +++ b/include/asm-mips/mmu_context.h @@ -0,0 +1,22 @@ +/* + * Switch a MMU context. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MMU_CONTEXT_H +#define __ASM_MIPS_MMU_CONTEXT_H + +/* + * Get a new mmu context. For MIPS we use resume() to change the + * PID (R3000)/ASID (R4000). Well, we will ... + */ +extern __inline__ void +get_mmu_context(struct task_struct *p) +{ +} + +#endif /* __ASM_MIPS_MMU_CONTEXT_H */ diff --git a/include/asm-mips/ncr53c94.h b/include/asm-mips/ncr53c94.h new file mode 100644 index 000000000..bf5c072f4 --- /dev/null +++ b/include/asm-mips/ncr53c94.h @@ -0,0 +1,121 @@ +/* + * Makefile for MIPS Linux main source directory + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ + +/* + * As far as I know there are some MIPS boxes which have their NCRs + * mapped with pad bytes. For these NCR_PAD will have to be redefined. + */ +#define NCR_PAD(name) +struct ncr53c94 { + NCR_PAD(pad0); + volatile unsigned char count_lo; + NCR_PAD(pad1); + volatile unsigned char count_hi; + NCR_PAD(pad2); + volatile unsigned char fifo; + NCR_PAD(pad3); + volatile unsigned char command; + NCR_PAD(pad4); + union { + volatile unsigned char status; + volatile unsigned char dest_id; + } s_d; + NCR_PAD(pad5); + union { + volatile unsigned char interrupts; + volatile unsigned char timeout; + } i_t; + NCR_PAD(pad6); + union { + volatile unsigned char seqn_step; + volatile unsigned char sync_period; + } s_p; + NCR_PAD(pad7); + union { + volatile unsigned char fifo_flags; + volatile unsigned char sync_offset; + } f_o; + NCR_PAD(pad8); + volatile unsigned char config1; + NCR_PAD(pad9); + volatile unsigned char clk_conv; + NCR_PAD(pad10); + volatile unsigned char test; + NCR_PAD(pad11); + volatile unsigned char config2; + NCR_PAD(pad12); + volatile unsigned char config3; + NCR_PAD(pad13); + volatile unsigned char unused; + NCR_PAD(pad14); + volatile unsigned char count_xhi; + NCR_PAD(pad15); + volatile unsigned char fifo_b; +}; + +/* + * Clock conversion factors + */ +#define CCV_10MHZ 0x2 /* 10 Mhz */ +#define CCV_15MHZ 0x3 /* 10.01 - 15 Mhz */ +#define CCV_20MHZ 0x4 /* 15.01 - 20 Mhz */ +#define CCV_25MHZ 0x5 /* 20.01 - 25 Mhz */ +#define CCV_30MHZ 0x6 /* 25.01 - 30 Mhz */ +#define CCV_35MHZ 0x7 /* 30.01 - 35 Mhz */ +#define CCV_40MHZ 0x0 /* 35.01 - 40 Mhz */ + +/* + * Set this additional to enable DMA for a command. + */ +#define NCR_DMA 0x80 + +/* + * Miscellaneous commands + */ +#define NCR_NOP 0x00 +#define NCR_FLUSH_FIFO 0x01 +#define NCR_RESET_NCR 0x02 +#define NCR_RESET_SCSI 0x03 + +/* + * Disconnected state commands + */ +#define NCR_SELECT_NO_ATN 0x41 +#define NCR_SELECT_ATN 0x42 +#define NCR_SELECT_ATN_STOP 0x43 +#define NCR_ENABLE_RESEL 0x44 +#define NCR_DISABLE_RESEL 0x45 +#define NCR_SELECT_ATN3 0x46 + +/* + * Initiator state commands + */ +#define NCR_TRANSFER 0x10 +#define NCR_CMD_CMP 0x11 +#define NCR_MSG_OK 0x12 +#define NCR_TRANSFER_PAD 0x18 +#define NCR_SET_ATN 0x1a +#define NCR_RESET_ATN 0x1b + +/* + * Target state commands + */ +#define NCR_SEND_MSG 0x20 +#define NCR_SEND_STATUS 0x21 +#define NCR_SEND_DATA 0x22 +#define NCR_DISC_SEQN 0x23 +#define NCR_TERM_SEQN 0x24 +#define NCR_CMD_COMP_SEQN 0x25 +#define NCR_DISC 0x27 +#define NCR_REC_MSG 0x28 +#define NCR_REC_CMD 0x29 +#define NCR_REC_DATA 0x2a +#define NCR_REC_CMD_SEQN 0x2b +#define NCR_ABORT_DMA 0x04 diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 4ea742d84..6339c0373 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -1,3 +1,12 @@ +/* + * Definitions for page handling + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + */ #ifndef __ASM_MIPS_PAGE_H #define __ASM_MIPS_PAGE_H @@ -8,13 +17,14 @@ #ifdef __KERNEL__ -#define CONFIG_STRICT_MM_TYPECHECKS +#define STRICT_MM_TYPECHECKS -#ifndef __LANGUAGE_ASSEMBLY__ +extern void (*clear_page)(unsigned long page); +extern void (*copy_page)(unsigned long to, unsigned long from); -#include <asm/cachectl.h> +#ifndef __LANGUAGE_ASSEMBLY__ -#ifdef CONFIG_STRICT_MM_TYPECHECKS +#ifdef STRICT_MM_TYPECHECKS /* * These are used to make use of C type-checking.. */ @@ -33,7 +43,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) -#else /* !defined (CONFIG_STRICT_MM_TYPECHECKS) */ +#else /* !defined (STRICT_MM_TYPECHECKS) */ /* * .. while these make it easier on the compiler */ @@ -52,18 +62,7 @@ typedef unsigned long pgprot_t; #define __pgd(x) (x) #define __pgprot(x) (x) -#endif /* !defined (CONFIG_STRICT_MM_TYPECHECKS) */ - -#include <linux/linkage.h> - -extern asmlinkage void tlbflush(void); -#define invalidate() ({sys_cacheflush(0, ~0, BCACHE);tlbflush();}) - -#if __mips == 3 -typedef unsigned int mem_map_t; -#else -typedef unsigned short mem_map_t; -#endif +#endif /* !defined (STRICT_MM_TYPECHECKS) */ #endif /* __LANGUAGE_ASSEMBLY__ */ @@ -71,32 +70,36 @@ typedef unsigned short mem_map_t; #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) /* This handles the memory map */ -#if __mips == 3 +#if 0 /* + * Kernel with 64 bit address space. * We handle pages at XKPHYS + 0x1800000000000000 (cachable, noncoherent) * Pagetables are at XKPHYS + 0x1000000000000000 (uncached) */ #define PAGE_OFFSET 0x9800000000000000UL #define PT_OFFSET 0x9000000000000000UL #define MAP_MASK 0x07ffffffffffffffUL -#define MAP_PAGE_RESERVED (1<<31) -#else +#else /* !defined (__mips64) */ /* + * Kernel with 32 bit address space. * We handle pages at KSEG0 (cachable, noncoherent) * Pagetables are at KSEG1 (uncached) */ -#define PAGE_OFFSET 0x80000000 -#define PT_OFFSET 0xa0000000 -#define MAP_MASK 0x1fffffff -#define MAP_PAGE_RESERVED (1<<15) -#endif +#define PAGE_OFFSET 0x80000000UL +#define PT_OFFSET 0xa0000000UL +#define MAP_MASK 0x1fffffffUL +#endif /* !defined (__mips64) */ + +/* + * __pa breaks when applied to a pagetable pointer on >= R4000. + */ +#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) +#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) #define MAP_NR(addr) ((((unsigned long)(addr)) & MAP_MASK) >> PAGE_SHIFT) #ifndef __LANGUAGE_ASSEMBLY__ -#define copy_page(from,to) __copy_page((unsigned long)from, (unsigned long)to) - extern unsigned long page_colour_mask; extern inline unsigned long @@ -105,21 +108,6 @@ page_colour(unsigned long page) return page & page_colour_mask; } -#if 0 -extern inline void __copy_page(unsigned long from, unsigned long to) -{ -printk("__copy_page(%08lx, %08lx)\n", from, to); - sys_cacheflush(0, ~0, DCACHE); - sync_mem(); - from += (PT_OFFSET - PAGE_OFFSET); - to += (PT_OFFSET - PAGE_OFFSET); - memcpy((void *) to, (void *) from, PAGE_SIZE); - sys_cacheflush(0, ~0, ICACHE); -} -#else -extern void __copy_page(unsigned long from, unsigned long to); -#endif - #endif /* defined (__LANGUAGE_ASSEMBLY__) */ #endif /* defined (__KERNEL__) */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index e2fb67cbe..2744d5c24 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -1,7 +1,56 @@ +/* + * Linux/MIPS pagetables + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ #ifndef __ASM_MIPS_PGTABLE_H #define __ASM_MIPS_PGTABLE_H -#include <asm/cachectl.h> +#include <asm/addrspace.h> +#include <asm/mipsconfig.h> + +#ifndef __LANGUAGE_ASSEMBLY__ + +#include <linux/linkage.h> +#include <asm/cache.h> + +extern inline void +flush_cache_all(void) +{ + cacheflush(0, ~0UL, CF_DCACHE|CF_VIRTUAL); +} + +extern inline void +flush_cache_mm(struct mm_struct *mm) +{ + cacheflush(0, ~0UL, CF_BCACHE|CF_VIRTUAL); +} + +extern inline void +flush_cache_range(struct mm_struct *mm, unsigned long start, unsigned long end) +{ + cacheflush(start, end - start, CF_DCACHE|CF_VIRTUAL); +} + +extern inline void +flush_cache_page(struct vm_area_struct * vma, unsigned long vmaddr) +{ + unsigned int flags; + + flags = (vma->vm_flags & VM_EXEC) ? CF_BCACHE|CF_VIRTUAL + : CF_DCACHE|CF_VIRTUAL; + cacheflush(vmaddr, PAGE_SIZE, flags); +} + +extern inline void +flush_page_to_ram(unsigned long page) +{ + cacheflush(page, PAGE_SIZE, CF_DCACHE|CF_VIRTUAL); +} /* * The Linux memory management assumes a three-level page table setup. In @@ -10,8 +59,58 @@ * i386 mmu expects. The 64 bit version uses a three level setup. * * This file contains the functions and defines necessary to modify and use - * the MIPS page table tree. + * the MIPS page table tree. Note the frequent conversion between addresses + * in KSEG0 and KSEG1. + * + * This is required due to the cache aliasing problem of the R4xx0 series. + * Sometimes doing uncached accesses also to improve the cache performance + * slightly. The R10000 caching mode "uncached accelerated" will help even + * further. + */ + +/* + * TLB invalidation: + * + * - flush_tlb() flushes the current mm struct TLB entries + * - flush_tlb_all() flushes all processes TLB entries + * - flush_tlb_mm(mm) flushes the specified mm context TLB entries + * - flush_tlb_page(mm, vmaddr) flushes a single page + * - flush_tlb_range(mm, start, end) flushes a range of pages + * + * FIXME: MIPS has full control of all TLB activity in the CPU. Though + * we just stick with complete flushing of TLBs for now. + * Currently this code only supports only R4000 and newer. Support + * for R3000 is in the works. The R6000 uses a 2x8 entry TLB slice + * and the R6000A an 16 entry TLB slice which is quite different + * from the memory management concepts of the other R-series CPUs. + * Only a few machines with this CPU still exist and I don't have one + * so chances for complete R6000 support are relativly low. */ +extern asmlinkage void tlbflush(void); +extern asmlinkage void tlbflush_page(unsigned long addr); +#define flush_tlb() tlbflush() +#define flush_tlb_all() flush_tlb() + +static inline void flush_tlb_mm(struct mm_struct *mm) +{ + if (mm == current->mm) + flush_tlb(); +} + +static inline void flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr) +{ + if (vma->vm_mm == current->mm) + tlbflush_page(addr); +} + +static inline void flush_tlb_range(struct mm_struct *mm, + unsigned long start, unsigned long end) +{ + if (mm == current->mm) + flush_tlb(); +} +#endif /* !defined (__LANGUAGE_ASSEMBLY__) */ /* PMD_SHIFT determines the size of the area a second-level page table can map */ #define PMD_SHIFT 22 @@ -40,16 +139,16 @@ * physical address by a single 'and' operation and gain 6 additional * bits for storing information which isn't present in a normal * MIPS page table. - * Since the Mips has choosen some quite missleading names for the + * Since the Mips has chosen some quite misleading names for the * valid and dirty bits they're defined here but only their synonyms * will be used. */ #define _PAGE_PRESENT (1<<0) /* implemented in software */ -#define _PAGE_COW (1<<1) /* implemented in software */ -#define _PAGE_READ (1<<2) /* implemented in software */ -#define _PAGE_WRITE (1<<3) /* implemented in software */ -#define _PAGE_ACCESSED (1<<4) /* implemented in software */ -#define _PAGE_MODIFIED (1<<5) /* implemented in software */ +#define _PAGE_READ (1<<1) /* implemented in software */ +#define _PAGE_WRITE (1<<2) /* implemented in software */ +#define _PAGE_ACCESSED (1<<3) /* implemented in software */ +#define _PAGE_MODIFIED (1<<4) /* implemented in software */ +#define _PAGE_UNUSED1 (1<<5) #define _PAGE_GLOBAL (1<<6) #define _PAGE_VALID (1<<7) #define _PAGE_SILENT_READ (1<<7) /* synonym */ @@ -75,7 +174,7 @@ #define PAGE_NONE __pgprot(_PAGE_PRESENT | __READABLE | _CACHE_UNCACHED) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ _PAGE_ACCESSED | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_COW | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE | \ _CACHE_CACHABLE_NONCOHERENT) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE | \ _CACHE_CACHABLE_NONCOHERENT) @@ -107,8 +206,8 @@ #if !defined (__LANGUAGE_ASSEMBLY__) -/* page table for 0-4MB for everybody */ -extern unsigned long pg0[1024]; +/* zero page used for uninitialized stuff */ +extern unsigned long empty_zero_page[1024]; /* * BAD_PAGETABLE is used when we need a bogus page-table, while @@ -124,7 +223,7 @@ extern unsigned long __zero_page(void); #define BAD_PAGETABLE __bad_pagetable() #define BAD_PAGE __bad_page() -#define ZERO_PAGE __zero_page() +#define ZERO_PAGE ((unsigned long)empty_zero_page) /* number of bits that fit into a memory pointer */ #define BITS_PER_PTR (8*sizeof(unsigned long)) @@ -133,9 +232,9 @@ extern unsigned long __zero_page(void); #define PTR_MASK (~(sizeof(void*)-1)) /* - * sizeof(void*)==1<<SIZEOF_PTR_LOG2 + * sizeof(void*) == (1 << SIZEOF_PTR_LOG2) */ -#if __mips == 3 +#ifdef 0 /* __mips64 */ #define SIZEOF_PTR_LOG2 3 #else #define SIZEOF_PTR_LOG2 2 @@ -145,18 +244,28 @@ extern unsigned long __zero_page(void); #define PAGE_PTR(address) \ ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) +extern void load_pgd(unsigned long pg_dir); + /* to set the page-dir */ #define SET_PAGE_DIR(tsk,pgdir) \ do { \ (tsk)->tss.pg_dir = ((unsigned long) (pgdir)) - PT_OFFSET; \ if ((tsk) == current) \ - invalidate(); \ + load_pgd((tsk)->tss.pg_dir); \ } while (0) -extern unsigned long high_memory; extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)]; /* + * Convert a page address to a page table pointer and vice versa. + * Due to the wiered virtual caches in the r-series we might run into + * problems with cache aliasing. We solve this problem by accessing + * the pagetables uncached. + */ +#define page_to_ptp(x) ((__typeof__(x))(((unsigned long) (x)) + (PT_OFFSET - PAGE_OFFSET))) +#define ptp_to_page(x) ((__typeof__(x))(((unsigned long) (x)) - (PT_OFFSET - PAGE_OFFSET))) + +/* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */ @@ -171,29 +280,32 @@ extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) extern inline int pte_none(pte_t pte) { return !pte_val(pte); } extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; } -extern inline int pte_inuse(pte_t *ptep) { return mem_map[MAP_NR(ptep)] != 1; } -extern inline void pte_clear(pte_t *ptep) { pte_val(*ptep) = 0; } -extern inline void pte_reuse(pte_t * ptep) + +/* + * Certain architectures need to do special things when pte's + * within a page table are directly modified. Thus, the following + * hook is made available. + */ +extern inline void set_pte(pte_t *ptep, pte_t pteval) { - if (!(mem_map[MAP_NR(ptep)] & MAP_PAGE_RESERVED)) - mem_map[MAP_NR(ptep)]++; + *ptep = pteval; +} + +extern inline void pte_clear(pte_t *ptep) +{ + pte_t pte; + + pte_val(pte) = 0; + set_pte(ptep, pte); } /* * Empty pgd/pmd entries point to the invalid_pte_table. */ extern inline int pmd_none(pmd_t pmd) { return (pmd_val(pmd) & PAGE_MASK) == ((unsigned long) invalid_pte_table - PAGE_OFFSET); } - -extern inline int pmd_bad(pmd_t pmd) -{ - return (pmd_val(pmd) & ~PAGE_MASK) != _PAGE_TABLE || - pmd_page(pmd) > high_memory || - pmd_page(pmd) < PAGE_OFFSET; -} +extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~PAGE_MASK) != _PAGE_TABLE; } extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_PRESENT; } -extern inline int pmd_inuse(pmd_t *pmdp) { return 0; } -extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = ((unsigned long) invalid_pte_table - PAGE_OFFSET); } -extern inline void pmd_reuse(pmd_t * pmdp) { } +extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = ((unsigned long) invalid_pte_table - PAGE_OFFSET) | _PAGE_TABLE; } /* * The "pgd_xxx()" functions here are trivial for a folded two-level @@ -203,13 +315,7 @@ extern inline void pmd_reuse(pmd_t * pmdp) { } extern inline int pgd_none(pgd_t pgd) { return 0; } extern inline int pgd_bad(pgd_t pgd) { return 0; } extern inline int pgd_present(pgd_t pgd) { return 1; } -extern inline int pgd_inuse(pgd_t * pgdp) { return mem_map[MAP_NR(pgdp)] != 1; } extern inline void pgd_clear(pgd_t * pgdp) { } -extern inline void pgd_reuse(pgd_t * pgdp) -{ - if (!(mem_map[MAP_NR(pgdp)] & MAP_PAGE_RESERVED)) - mem_map[MAP_NR(pgdp)]++; -} /* * The following only work if pte_present() is true. @@ -220,7 +326,6 @@ extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } extern inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_READ; } extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -extern inline int pte_cow(pte_t pte) { return pte_val(pte) & _PAGE_COW; } extern inline pte_t pte_wrprotect(pte_t pte) { @@ -237,7 +342,6 @@ extern inline pte_t pte_exprotect(pte_t pte) } extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); return pte; } extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ|_PAGE_SILENT_WRITE); return pte; } -extern inline pte_t pte_uncow(pte_t pte) { pte_val(pte) &= ~_PAGE_COW; return pte; } extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; @@ -277,11 +381,6 @@ extern inline pte_t pte_mkyoung(pte_t pte) } return pte; } -extern inline pte_t pte_mkcow(pte_t pte) -{ - pte_val(pte) |= _PAGE_COW; - return pte; -} /* * Conversion functions: convert a page and protection to a page entry, @@ -290,14 +389,16 @@ extern inline pte_t pte_mkcow(pte_t pte) extern inline pte_t mk_pte(unsigned long page, pgprot_t pgprot) { pte_t pte; pte_val(pte) = (page - PAGE_OFFSET) | pgprot_val(pgprot); return pte; } +extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) +{ pte_t pte; pte_val(pte) = physpage | pgprot_val(pgprot); return pte; } + extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } /* to find an entry in a page-table-directory */ -extern inline pgd_t * pgd_offset(struct task_struct * tsk, unsigned long address) +extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) { - return (pgd_t *) (tsk->tss.pg_dir + PT_OFFSET) + - (address >> PGDIR_SHIFT); + return mm->pgd + (address >> PGDIR_SHIFT); } /* Find an entry in the second-level page table.. */ @@ -309,40 +410,40 @@ extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) /* Find an entry in the third-level page table.. */ extern inline pte_t * pte_offset(pmd_t * dir, unsigned long address) { - return (pte_t *) (pmd_page(*dir) + (PT_OFFSET - PAGE_OFFSET)) + + return (pte_t *) (page_to_ptp(pmd_page(*dir))) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); } /* * Allocate and free page tables. The xxx_kernel() versions are * used to allocate a kernel page table - this turns on ASN bits - * if any, and marks the page tables reserved. + * if any. */ extern inline void pte_free_kernel(pte_t * pte) { unsigned long page = (unsigned long) pte; - mem_map[MAP_NR(pte)] = 1; if(!page) return; - page -= (PT_OFFSET - PAGE_OFFSET); - free_page(page); + /* + * Flush complete cache - we don't know the virtual address. + */ + cacheflush(0, ~0, CF_DCACHE|CF_VIRTUAL); + free_page(ptp_to_page(page)); } extern inline pte_t * pte_alloc_kernel(pmd_t *pmd, unsigned long address) { address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); if (pmd_none(*pmd)) { - unsigned long page = __get_free_page(GFP_KERNEL); + unsigned long page = get_free_page(GFP_KERNEL); if (pmd_none(*pmd)) { if (page) { - mem_map[MAP_NR(page)] = MAP_PAGE_RESERVED; - sys_cacheflush((void *)page, PAGE_SIZE, DCACHE); + cacheflush(page, PAGE_SIZE, CF_DCACHE|CF_VIRTUAL); sync_mem(); - page += (PT_OFFSET - PAGE_OFFSET); - memset((void *) page, 0, PAGE_SIZE); + page = page_to_ptp(page); pmd_set(pmd, (pte_t *)page); - return ((pte_t *)page) + address; + return (pte_t *)page + address; } pmd_set(pmd, (pte_t *) BAD_PAGETABLE); return NULL; @@ -354,7 +455,7 @@ extern inline pte_t * pte_alloc_kernel(pmd_t *pmd, unsigned long address) pmd_set(pmd, (pte_t *) BAD_PAGETABLE); return NULL; } - return (pte_t *) (pmd_page(*pmd) + (PT_OFFSET - PAGE_OFFSET)) + address; + return (pte_t *) page_to_ptp(pmd_page(*pmd)) + address; } /* @@ -376,23 +477,25 @@ extern inline void pte_free(pte_t * pte) if(!page) return; - page -= (PT_OFFSET - PAGE_OFFSET); - free_page(page); + /* + * Flush complete cache - we don't know the virtual address. + */ + cacheflush(0, ~0UL, CF_DCACHE|CF_VIRTUAL); + free_page(ptp_to_page(page)); } extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address) { address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); if (pmd_none(*pmd)) { - unsigned long page = __get_free_page(GFP_KERNEL); + unsigned long page = get_free_page(GFP_KERNEL); if (pmd_none(*pmd)) { if (page) { - sys_cacheflush((void *)page, PAGE_SIZE, DCACHE); + cacheflush(page, PAGE_SIZE, CF_DCACHE|CF_VIRTUAL); sync_mem(); - page += (PT_OFFSET - PAGE_OFFSET); - memset((void *) page, 0, PAGE_SIZE); + page = page_to_ptp(page); pmd_set(pmd, (pte_t *)page); - return ((pte_t *)page) + address; + return (pte_t *)page + address; } pmd_set(pmd, (pte_t *) BAD_PAGETABLE); return NULL; @@ -404,7 +507,7 @@ extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address) pmd_set(pmd, (pte_t *) BAD_PAGETABLE); return NULL; } - return (pte_t *) (pmd_page(*pmd) + (PT_OFFSET - PAGE_OFFSET)) + address; + return (pte_t *) page_to_ptp(pmd_page(*pmd)) + address; } /* @@ -426,59 +529,17 @@ extern inline void pgd_free(pgd_t * pgd) if(!page) return; - page -= (PT_OFFSET - PAGE_OFFSET); - free_page(page); + /* + * Flush complete cache - we don't know the virtual address. + */ + cacheflush(0, ~0UL, CF_DCACHE|CF_VIRTUAL); + free_page(ptp_to_page(page)); } /* * Initialize new page directory with pointers to invalid ptes */ -extern inline void pgd_init(unsigned long page) -{ - unsigned long dummy1, dummy2; - - page += (PT_OFFSET - PAGE_OFFSET); -#ifdef __R4000__ - /* - * Ich will Spass - ich geb Gas ich geb Gas... - */ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "dsll32\t$1,%2,0\n\t" - "dsrl32\t%2,$1,0\n\t" - "or\t%2,$1\n" - "1:\tsd\t%2,(%0)\n\t" - "subu\t%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,8\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), - "=r" (dummy2) - :"r" (((unsigned long) invalid_pte_table - PAGE_OFFSET) | - _PAGE_TABLE), - "0" (page), - "1" (PAGE_SIZE/(sizeof(pmd_t)*2)) - :"$1"); -#else - __asm__ __volatile__( - ".set\tnoreorder\n" - "1:\tsw\t%2,(%0)\n\t" - "subu\t%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,4\n\t" - ".set\treorder" - :"=r" (dummy1), - "=r" (dummy2) - :"r" (((unsigned long) invalid_pte_table - PAGE_OFFSET) | - _PAGE_TABLE), - "0" (page), - "1" (PAGE_SIZE/sizeof(pmd_t))); -#endif -} +extern void (*pgd_init)(unsigned long page); extern inline pgd_t * pgd_alloc(void) { @@ -486,33 +547,37 @@ extern inline pgd_t * pgd_alloc(void) if(!(page = __get_free_page(GFP_KERNEL))) return NULL; - - sys_cacheflush((void *)page, PAGE_SIZE, DCACHE); - sync_mem(); pgd_init(page); - return (pgd_t *) (page + (PT_OFFSET - PAGE_OFFSET)); + return (pgd_t *) page_to_ptp(page); } extern pgd_t swapper_pg_dir[1024]; -/* - * MIPS doesn't need any external MMU info: the kernel page - * tables contain all the necessary information. - */ extern inline void update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte) { + tlbflush_page(address); + /* + * FIXME: We should also reload a new entry into the TLB to + * avoid unnecessary exceptions. + */ } -#if __mips >= 3 +#if 0 /* defined(__mips64) */ +/* + * For true 64 bit kernel + */ #define SWP_TYPE(entry) (((entry) >> 32) & 0xff) #define SWP_OFFSET(entry) ((entry) >> 40) #define SWP_ENTRY(type,offset) pte_val(mk_swap_pte((type),(offset))) #else +/* + * Kernel with 32 bit address space + */ #define SWP_TYPE(entry) (((entry) >> 1) & 0x7f) #define SWP_OFFSET(entry) ((entry) >> 8) #define SWP_ENTRY(type,offset) (((type) << 1) | ((offset) << 8)) diff --git a/include/asm-mips/pica.h b/include/asm-mips/pica.h deleted file mode 100644 index 799dcf4a0..000000000 --- a/include/asm-mips/pica.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Hardware info about Acer PICA 61 and similar - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 by Andreas Busse and Ralf Baechle - */ -#ifndef __ASM_MIPS_PICA_H -#define __ASM_MIPS_PICA_H - -/* - * The addresses below are virtual address. The mappings are - * created on startup via wired entries in the tlb. The Mips - * Magnum R3000 and R4000 machines are similar in many aspects, - * but many hardware register are accessible at 0xb9000000 in - * instead of 0xe0000000. - */ - -/* - * Revision numbers in PICA_ASIC_REVISION - * - * 0xf0000000 - Rev1 - * 0xf0000001 - Rev2 - * 0xf0000002 - Rev3 - */ -#define PICA_ASIC_REVISION 0xe0000008 - -/* - * The segments of the seven segment LED are mapped - * to the control bits as follows: - * - * (7) - * --------- - * | | - * (2) | | (6) - * | (1) | - * --------- - * | | - * (3) | | (5) - * | (4) | - * --------- . (0) - */ -#define PICA_LED 0xe000f000 - -/* - * Some characters for the LED control registers - * The original Mips machines seem to have a LED display - * with integrated decoder while the Acer machines can - * control each of the seven segments and the dot independend. - * It only a toy, anyway... - */ -#define LED_DOT 0x01 -#define LED_SPACE 0x00 -#define LED_0 0xfc -#define LED_1 0x60 -#define LED_2 0xda -#define LED_3 0xf2 -#define LED_4 0x66 -#define LED_5 0xb6 -#define LED_6 0xbe -#define LED_7 0xe0 -#define LED_8 0xfe -#define LED_9 0xf6 -#define LED_A 0xee -#define LED_b 0x3e -#define LED_C 0x9c -#define LED_d 0x7a -#define LED_E 0x9e -#define LED_F 0x8e - -#ifndef __LANGUAGE_ASSEMBLY__ - -extern __inline__ void pica_set_led(unsigned int bits) -{ - volatile unsigned int *led_register = (unsigned int *) PICA_LED; - - *led_register = bits; -} - -#endif - -/* - * i8042 keyboard controller for PICA chipset. - * This address is just a guess and seems to differ - * from the other mips machines... - */ -#define PICA_KEYBOARD_ADDRESS 0xe0005000 -#define PICA_KEYBOARD_DATA 0xe0005000 -#define PICA_KEYBOARD_COMMAND 0xe0005001 - -#ifndef __LANGUAGE_ASSEMBLY__ - -typedef struct { - unsigned char data; - unsigned char command; -} pica_keyboard_hardware; - -typedef struct { - unsigned char pad0[3]; - unsigned char data; - unsigned char pad1[3]; - unsigned char command; -} mips_keyboard_hardware; - -/* - * For now - */ -#define keyboard_hardware pica_keyboard_hardware - -#endif - -/* - * i8042 keyboard controller for most other Mips machines. - */ -#define MIPS_KEYBOARD_ADDRESS 0xb9005000 -#define MIPS_KEYBOARD_DATA 0xb9005003 -#define MIPS_KEYBOARD_COMMAND 0xb9005007 - -#ifndef __LANGUAGE_ASSEMBLY__ - -#endif - -/* - * PICA timer registers and interrupt no. - * Note that the hardware timer interrupt is actually on - * cpu level 6, but to keep compatibility with PC stuff - * it is remapped to vector 0. See arch/mips/kernel/entry.S. - */ -#define PICA_TIMER_INTERVAL 0xe0000228 -#define PICA_TIMER_REGISTER 0xe0000230 - -/* - * DRAM configuration register - */ -#ifndef __LANGUAGE_ASSEMBLY__ -#ifdef __MIPSEL__ -typedef struct { - unsigned int bank2 : 3; - unsigned int bank1 : 3; - unsigned int mem_bus_width : 1; - unsigned int reserved2 : 1; - unsigned int page_mode : 1; - unsigned int reserved1 : 23; -} dram_configuration; -#else /* defined (__MIPSEB__) */ -typedef struct { - unsigned int reserved1 : 23; - unsigned int page_mode : 1; - unsigned int reserved2 : 1; - unsigned int mem_bus_width : 1; - unsigned int bank1 : 3; - unsigned int bank2 : 3; -} dram_configuration; -#endif -#endif /* __LANGUAGE_ASSEMBLY__ */ - -#define PICA_DRAM_CONFIG 0xe00fffe0 - -/* - * PICA interrupt control registers - */ -#define PICA_IO_IRQ_SOURCE 0xe0100000 -#define PICA_IO_IRQ_ENABLE 0xe0100002 - -/* - * Pica interrupt enable bits - */ -#define PIE_PARALLEL (1<<0) -#define PIE_FLOPPY (1<<1) -#define PIE_SOUND (1<<2) -#define PIE_VIDEO (1<<3) -#define PIE_ETHERNET (1<<4) -#define PIE_SCSI (1<<5) -#define PIE_KEYBOARD (1<<6) -#define PIE_MOUSE (1<<7) -#define PIE_SERIAL1 (1<<8) -#define PIE_SERIAL2 (1<<9) - -#endif /* __ASM_MIPS_PICA_H */ diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h new file mode 100644 index 000000000..21217ebae --- /dev/null +++ b/include/asm-mips/posix_types.h @@ -0,0 +1,117 @@ +/* + * POSIX types + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ARCH_MIPS_POSIX_TYPES_H +#define __ARCH_MIPS_POSIX_TYPES_H + +#define __need_size_t +#define __need_ptrdiff_t +#include <stddef.h> + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned long __kernel_mode_t; +typedef unsigned long __kernel_nlink_t; +typedef long __kernel_off_t; +typedef long __kernel_pid_t; +typedef long __kernel_ipc_pid_t; +typedef long __kernel_uid_t; +typedef long __kernel_gid_t; +typedef __SIZE_TYPE__ __kernel_size_t; +typedef __SSIZE_TYPE__ __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_clock_t; +typedef long __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned long __kernel_sigset_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { + long val[2]; +} __kernel_fsid_t; + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* __ARCH_MIPS_POSIX_TYPES_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 8e3e00267..be6d26a61 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -1,15 +1,18 @@ /* * include/asm-mips/processor.h * - * Copyright (C) 1994 Waldorf Electronics - * written by Ralf Baechle + * Copyright (C) 1994, 1995 by Waldorf Electronics + * Copyright (C) 1995, 1996 by Ralf Baechle + * Modified further for R[236]000 compatibility by Paul M. Antoine */ - #ifndef __ASM_MIPS_PROCESSOR_H #define __ASM_MIPS_PROCESSOR_H +#include <asm/sgidefs.h> + #if !defined (__LANGUAGE_ASSEMBLY__) -#include <asm/cachectl.h> +#include <asm/mipsregs.h> +#include <asm/reg.h> #include <asm/system.h> /* @@ -22,24 +25,19 @@ extern unsigned long event; /* * Bus types (default is ISA, but people can check others with these..) - * MCA_bus hardcoded to 0 for now. + * There are no Microchannel MIPS machines. * * This needs to be extended since MIPS systems are being delivered with * numerous different types of bus systems. */ extern int EISA_bus; #define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* - * MIPS has no problems with write protection - */ -#define wp_works_ok 1 -#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ /* * User space process size: 2GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. + * so don't change it unless you know what you are doing. TASK_SIZE + * for a 64 bit kernel is expandable to 8192PB, of which the current MIPS + * implementations will "only" be able to use 1TB ... */ #define TASK_SIZE (0x80000000UL) @@ -78,24 +76,28 @@ struct thread_struct { /* * saved main processor registers */ - unsigned long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; - unsigned long reg28, reg29, reg30, reg31; + __register_t reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; + __register_t reg28, reg29, reg30, reg31; /* * saved cp0 stuff */ - unsigned long cp0_status; + unsigned int cp0_status; /* * saved fpu/fpu emulator stuff */ union mips_fpu_union fpu; /* - * Other stuff associated with the process + * Other stuff associated with the thread */ - unsigned long cp0_badvaddr; + long cp0_badvaddr; unsigned long error_code; unsigned long trap_no; - unsigned long ksp; /* Top of kernel stack */ - unsigned long pg_dir; /* L1 page table pointer */ + long ksp; /* Top of kernel stack */ + long pg_dir; /* L1 page table pointer */ +#define MF_FIXADE 1 /* Fix address errors in software */ +#define MF_LOGADE 2 /* Log address errors to syslog */ + unsigned long mflags; + unsigned long segment; }; #endif /* !defined (__LANGUAGE_ASSEMBLY__) */ @@ -104,31 +106,32 @@ struct thread_struct { * If you change the #defines remember to change thread_struct above too! */ #define TOFF_REG16 0 -#define TOFF_REG17 (TOFF_REG16+4) -#define TOFF_REG18 (TOFF_REG17+4) -#define TOFF_REG19 (TOFF_REG18+4) -#define TOFF_REG20 (TOFF_REG19+4) -#define TOFF_REG21 (TOFF_REG20+4) -#define TOFF_REG22 (TOFF_REG21+4) -#define TOFF_REG23 (TOFF_REG22+4) -#define TOFF_REG28 (TOFF_REG23+4) -#define TOFF_REG29 (TOFF_REG28+4) -#define TOFF_REG30 (TOFF_REG29+4) -#define TOFF_REG31 (TOFF_REG30+4) -#define TOFF_CP0_STATUS (TOFF_REG31+4) +#define TOFF_REG17 (TOFF_REG16+SZREG) +#define TOFF_REG18 (TOFF_REG17+SZREG) +#define TOFF_REG19 (TOFF_REG18+SZREG) +#define TOFF_REG20 (TOFF_REG19+SZREG) +#define TOFF_REG21 (TOFF_REG20+SZREG) +#define TOFF_REG22 (TOFF_REG21+SZREG) +#define TOFF_REG23 (TOFF_REG22+SZREG) +#define TOFF_REG28 (TOFF_REG23+SZREG) +#define TOFF_REG29 (TOFF_REG28+SZREG) +#define TOFF_REG30 (TOFF_REG29+SZREG) +#define TOFF_REG31 (TOFF_REG30+SZREG) +#define TOFF_CP0_STATUS (TOFF_REG31+SZREG) /* * Pad for 8 byte boundary! */ -#define TOFF_FPU (((TOFF_CP0_STATUS+4)+(8-1))&~(8-1)) +#define TOFF_FPU (((TOFF_CP0_STATUS+SZREG)+(8-1))&~(8-1)) #define TOFF_CP0_BADVADDR (TOFF_FPU+264) #define TOFF_ERROR_CODE (TOFF_CP0_BADVADDR+4) #define TOFF_TRAP_NO (TOFF_ERROR_CODE+4) #define TOFF_KSP (TOFF_TRAP_NO+4) #define TOFF_PG_DIR (TOFF_KSP+4) +#define TOFF_MFLAGS (TOFF_PG_DIR+4) +#define TOFF_EX (TOFF_PG_MFLAGS+4) -#if !defined (__LANGUAGE_ASSEMBLY__) - -#define INIT_MMAP { &init_task, 0, 0x40000000, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC } +#define INIT_MMAP { &init_mm, KSEG0, KSEG1, PAGE_SHARED, \ + VM_READ | VM_WRITE | VM_EXEC } #define INIT_TSS { \ /* \ @@ -145,54 +148,73 @@ struct thread_struct { */ \ INIT_FPU, \ /* \ - * Other stuff associated with the process\ + * Other stuff associated with the process \ */ \ 0, 0, 0, sizeof(init_kernel_stack) + (unsigned long)init_kernel_stack - 8, \ - (unsigned long) swapper_pg_dir - PT_OFFSET \ + (unsigned long) swapper_pg_dir - PT_OFFSET, \ + /* \ + * For now the default is to fix address errors \ + */ \ + MF_FIXADE, \ + KERNEL_DS \ } /* - * Do necessary setup to start up a newly executed thread. + * Paul, please check if 4kb stack are sufficient for the R3000. With 4kb + * I never had a stack overflows on 32 bit R4000 kernels but the almost + * completly 64bit R4000 kernels from 1.3.63 on need more stack even in + * trivial situations. */ -static __inline__ -void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) -{ - sys_cacheflush(0, ~0, BCACHE); - sync_mem(); - regs->cp0_epc = pc; - /* - * New thread looses kernel priviledges - */ - regs->cp0_status = (regs->cp0_status & ~ST0_KSU) | KSU_USER; - regs->reg29 = sp; -} +#define KERNEL_STACK_SIZE 8192 -#ifdef __KERNEL__ +#if !defined (__LANGUAGE_ASSEMBLY__) +extern unsigned long alloc_kernel_stack(void); +extern void free_kernel_stack(unsigned long stack); /* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. + * Return saved PC of a blocked thread. */ -asmlinkage void resume(struct task_struct *tsk, int offset); +extern unsigned long (*thread_saved_pc)(struct thread_struct *t); -#define switch_to(n) \ - resume(n, ((int)(&((struct task_struct *)0)->tss))) +/* + * Do necessary setup to start up a newly executed thread. + */ +extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); /* * Does the process account for user or for system time? */ -#if defined (__R4000__) - -#define USES_USER_TIME(regs) (!((regs)->cp0_status & 0x18)) - -#else /* !defined (__R4000__) */ - +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) #define USES_USER_TIME(regs) (!((regs)->cp0_status & 0x4)) +#endif +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define USES_USER_TIME(regs) (!((regs)->cp0_status & 0x18)) +#endif -#endif /* !defined (__R4000__) */ - -#endif /* __KERNEL__ */ - +/* + * Return_address is a replacement for __builtin_return_address(count) + * which on certain architectures cannot reasonably be implemented in GCC + * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). + * Note that __builtin_return_address(x>=1) is forbidden because GCC + * aborts compilation on some CPUs. It's simply not possible to unwind + * some CPU's stackframes. + */ +#if (__GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8)) +/* + * __builtin_return_address works only for non-leaf functions. We avoid the + * overhead of a function call by forcing the compiler to save the return + * address register on the stack. + */ +#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) +#else +/* + * __builtin_return_address is not implemented at all. Calling it + * will return senseless values. Return NULL which at least is an obviously + * senseless value. + */ +#define return_address() NULL +#endif #endif /* !defined (__LANGUAGE_ASSEMBLY__) */ #endif /* __ASM_MIPS_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 18cdb8387..ade150d90 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -5,8 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Waldorf GMBH - * written by Ralf Baechle + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle * * Machine dependent structs and defines to help the user use * the ptrace system call. @@ -14,101 +13,72 @@ #ifndef __ASM_MIPS_PTRACE_H #define __ASM_MIPS_PTRACE_H +#include <asm/sgidefs.h> +#include <asm/register.h> + /* - * This defines/structures correspond to the register layout on stack - - * if the order here is changed, it needs to be updated in - * include/asm-mips/stackframe.h - */ -#define IN_REG1 5 -#define IN_REG2 6 -#define IN_REG3 7 -#define IN_REG4 8 -#define IN_REG5 9 -#define IN_REG6 10 -#define IN_REG7 11 -#define IN_REG8 12 -#define IN_REG9 13 -#define IN_REG10 14 -#define IN_REG11 15 -#define IN_REG12 16 -#define IN_REG13 17 -#define IN_REG14 18 -#define IN_REG15 19 -#define IN_REG16 20 -#define IN_REG17 21 -#define IN_REG18 22 -#define IN_REG19 23 -#define IN_REG20 24 -#define IN_REG21 25 -#define IN_REG22 26 -#define IN_REG23 27 -#define IN_REG24 28 -#define IN_REG25 29 -/* - * k0/k1 unsaved + * General purpose registers. */ -#define IN_REG28 30 -#define IN_REG29 31 -#define IN_REG30 32 -#define IN_REG31 33 +#define GPR_BASE 0 +#define NGP_REGS 32 /* - * Saved special registers + * Floating point registers. */ -#define IN_LO 34 -#define IN_HI 35 +#define FPR_BASE (GPR_BASE + NGP_REGS) +#define NFP_REGS 32 /* - * saved cp0 registers + * Signal handlers */ -#define IN_CP0_STATUS 36 -#define IN_CP0_EPC 37 -#define IN_CP0_CAUSE 38 +#define SIG_BASE (FPR_BASE + NFP_REGS) +#define NSIG_HNDLRS 32 /* - * Some goodies + * Special registers. */ -#define IN_INTERRUPT 39 -#define IN_ORIG_REG2 40 +#define SPEC_BASE (SIG_BASE + NSIG_HNDLRS) +#define NSPEC_REGS 7 +#define PC SPEC_BASE +#define CAUSE (PC + 1) +#define BADVADDR (CAUSE + 1) +#define MMHI (BADVADDR + 1) +#define MMLO (MMHI + 1) +#define FPC_CSR (MMLO + 1) +#define FPC_EIR (FPC_CSR + 1) +#define NPTRC_REGS (FPC_EIR + 1) /* * This struct defines the way the registers are stored on the stack during a - * system call/exception. As usual the registers k0/k1 aren't being saved. + * system call/exception. As usual the registers zero/k0/k1 aren't being saved. */ struct pt_regs { /* * Pad bytes for argument save space on the stack * 20/40 Bytes for 32/64 bit code */ - unsigned long pad0[5]; + __register_t pad0[6]; /* extra word for alignment */ /* - * saved main processor registers + * Saved main processor registers */ - long reg1, reg2, reg3, reg4, reg5, reg6, reg7; - long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15; - long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; - long reg24, reg25, reg28, reg29, reg30, reg31; + __register_t regs[32]; /* - * Saved special registers + * Other saved registers */ - long lo; - long hi; + __register_t lo; + __register_t hi; + __register_t orig_reg2; + __register_t orig_reg7; /* * saved cp0 registers */ - unsigned long cp0_status; - unsigned long cp0_epc; - unsigned long cp0_cause; - - /* - * Some goodies... - */ - unsigned long interrupt; - long orig_reg2; - long pad1; + __register_t cp0_epc; + __register_t cp0_badvaddr; + unsigned int cp0_status; + unsigned int cp0_cause; }; #ifdef __KERNEL__ @@ -116,16 +86,15 @@ struct pt_regs { /* * Does the process account for user or for system time? */ -#if defined (__R4000__) - -#define user_mode(regs) ((regs)->cp0_status & 0x10) - -#else /* !defined (__R4000__) */ - +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) #define user_mode(regs) (!((regs)->cp0_status & 0x8)) +#endif +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define user_mode(regs) ((regs)->cp0_status & 0x10) +#endif -#endif /* !defined (__R4000__) */ - +#define instruction_pointer(regs) ((regs)->cp0_epc) extern void show_regs(struct pt_regs *); #endif diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h new file mode 100644 index 000000000..196a1a133 --- /dev/null +++ b/include/asm-mips/reg.h @@ -0,0 +1,81 @@ +/* + * Makefile for MIPS Linux main source directory + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ +#ifndef __ASM_MIPS_REG_H +#define __ASM_MIPS_REG_H + +/* + * This defines/structures correspond to the register layout on stack - + * if the order here is changed, it needs to be updated in + * include/asm-mips/stackframe.h + */ +#define EF_REG1 5 +#define EF_REG2 6 +#define EF_REG3 7 +#define EF_REG4 8 +#define EF_REG5 9 +#define EF_REG6 10 +#define EF_REG7 11 +#define EF_REG8 12 +#define EF_REG9 13 +#define EF_REG10 14 +#define EF_REG11 15 +#define EF_REG12 16 +#define EF_REG13 17 +#define EF_REG14 18 +#define EF_REG15 19 +#define EF_REG16 20 +#define EF_REG17 21 +#define EF_REG18 22 +#define EF_REG19 23 +#define EF_REG20 24 +#define EF_REG21 25 +#define EF_REG22 26 +#define EF_REG23 27 +#define EF_REG24 28 +#define EF_REG25 29 +/* + * k0/k1 unsaved + */ +#define EF_REG28 30 +#define EF_REG29 31 +#define EF_REG30 32 +#define EF_REG31 33 + +/* + * Saved special registers + */ +#define EF_LO 34 +#define EF_HI 35 +#define EF_ORIG_REG2 36 + +#if 0 +/* + * saved cp0 registers + */ +#define EF_CP0_EPC 37 +#define EF_CP0_STATUS 36 +#define EF_CP0_CAUSE 38 +#endif + +#ifdef __mips64 +#define EF_SIZE 304 +#else +#define EF_SIZE 160 +#endif + +#if 0 +/* + * Map register number into core file offset. + */ +#define CORE_REG(reg, ubase) \ + (((unsigned long *)((unsigned long)(ubase)))[reg]) +#endif + +#endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h index ec455790e..691d047b6 100644 --- a/include/asm-mips/regdef.h +++ b/include/asm-mips/regdef.h @@ -12,7 +12,7 @@ #define __ASM_MIPS_REGDEF_H /* - * Symbolic register names + * Symbolic register names for 32 bit ABI */ #define zero $0 /* wired zero */ #define AT $1 /* assembler temp - uppercase because of ".set at" */ @@ -40,11 +40,13 @@ #define s7 $23 #define t8 $24 /* caller saved */ #define t9 $25 +#define jp $25 /* PIC jump register */ #define k0 $26 /* kernel scratch */ #define k1 $27 #define gp $28 /* global pointer */ #define sp $29 /* stack pointer */ #define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ #define ra $31 /* return address */ #endif /* __ASM_MIPS_REGDEF_H */ diff --git a/include/asm-mips/register.h b/include/asm-mips/register.h new file mode 100644 index 000000000..9a19187e0 --- /dev/null +++ b/include/asm-mips/register.h @@ -0,0 +1,34 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_REGISTER_H +#define __ASM_MIPS_REGISTER_H + +/* + * Types to represent a register + */ +#ifdef __mips64 +/* + * The R4000 port makes use of the 64 bit wide registers + */ +#ifndef __LANGUAGE_ASSEMBLY__ +typedef long long __register_t; +typedef unsigned long long __uregister_t; +#endif + +#else + +/* + * Good 'ole R3000 has only 32 bit wide registers + */ +#ifndef __LANGUAGE_ASSEMBLY__ +typedef long __register_t; +typedef unsigned long __uregister_t; +#endif +#endif + +#endif /* __ASM_MIPS_REGISTER_H */ diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h index 001f92435..16c83544d 100644 --- a/include/asm-mips/resource.h +++ b/include/asm-mips/resource.h @@ -1,25 +1,47 @@ +/* + * Process resource limits + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ #ifndef __ASM_MIPS_RESOURCE_H #define __ASM_MIPS_RESOURCE_H /* * Resource limits */ +#define RLIMIT_CPU 0 /* CPU time in ms */ +#define RLIMIT_FSIZE 1 /* Maximum filesize */ +#define RLIMIT_DATA 2 /* max data size */ +#define RLIMIT_STACK 3 /* max stack size */ +#define RLIMIT_CORE 4 /* max core file size */ +#define RLIMIT_NOFILE 5 /* max number of open files */ +#define RLIMIT_AS 6 /* mapped memory */ +#define RLIMIT_RSS 7 /* max resident set size */ +#define RLIMIT_NPROC 8 /* max number of processes */ +#define RLIMIT_MEMLOCK 9 /* max locked-in-memory address space */ + +#define RLIM_NLIMITS 10 /* Number of limit flavors. */ -#define RLIMIT_CPU 0 /* CPU time in ms */ -#define RLIMIT_FSIZE 1 /* Maximum filesize */ -#define RLIMIT_DATA 2 /* max data size */ -#define RLIMIT_STACK 3 /* max stack size */ -#define RLIMIT_CORE 4 /* max core file size */ -#define RLIMIT_NOFILE 5 /* max number of open files */ -#define RLIMIT_VMEM 6 /* mapped memory */ -#define RLIMIT_AS RLIMIT_VMEM -#define RLIMIT_RSS 7 /* max resident set size */ -#define RLIMIT_NPROC 8 /* max number of processes */ +#ifdef __KERNEL__ -#ifdef notdef -#define RLIMIT_MEMLOCK 8 /* max locked-in-memory address space*/ -#endif +#define INIT_RLIMITS \ +{ \ + {LONG_MAX, LONG_MAX}, \ + {LONG_MAX, LONG_MAX}, \ + {LONG_MAX, LONG_MAX}, \ + {_STK_LIM, _STK_LIM}, \ + { 0, LONG_MAX}, \ + {NR_OPEN, NR_OPEN}, \ + {LONG_MAX, LONG_MAX}, \ + {LONG_MAX, LONG_MAX}, \ + {MAX_TASKS_PER_USER, MAX_TASKS_PER_USER}, \ + { LONG_MAX, LONG_MAX }, \ +} -#define RLIM_NLIMITS 9 +#endif /* __KERNEL__ */ #endif /* __ASM_MIPS_RESOURCE_H */ diff --git a/include/asm-mips/segment.h b/include/asm-mips/segment.h index 73c0de45f..c6a684e8d 100644 --- a/include/asm-mips/segment.h +++ b/include/asm-mips/segment.h @@ -1,197 +1,6 @@ -/* - * include/asm-mips/segment.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995 by Ralf Baechle - * - */ -#ifndef __ASM_MIPS_SEGMENT_H -#define __ASM_MIPS_SEGMENT_H +#ifndef __MIPS_SEGMENT_H +#define __MIPS_SEGMENT_H -#ifndef __LANGUAGE_ASSEMBLY__ -/* - * Uh, these should become the main single-value transfer routines.. - * They automatically use the right size if we just have the right - * pointer type.. - */ -#define put_user(x,ptr) __put_user((unsigned long)(x),(ptr),sizeof(*(ptr))) -#define get_user(ptr) __get_user((ptr),sizeof(*(ptr))) +/* Only here because we have some old header files that expect it.. */ -/* - * This is a silly but good way to make sure that - * the __put_user function is indeed always optimized, - * and that we use the correct sizes.. - */ -extern int bad_user_access_length(void); - -/* I should make this use unaligned transfers etc.. */ -static inline void __put_user(unsigned long x, void * y, int size) -{ - switch (size) { - case 1: - *(char *) y = x; - break; - case 2: - *(short *) y = x; - break; - case 4: - *(int *) y = x; - break; - case 8: - *(long *) y = x; - break; - default: - bad_user_access_length(); - } -} - -/* I should make this use unaligned transfers etc.. */ -static inline unsigned long __get_user(void * y, int size) -{ - switch (size) { - case 1: - return *(unsigned char *) y; - case 2: - return *(unsigned short *) y; - case 4: - return *(unsigned int *) y; - case 8: - return *(unsigned long *) y; - default: - return bad_user_access_length(); - } -} -#endif /* __LANGUAGE_ASSEMBLY__ */ - -/* - * Memory segments (32bit kernel mode addresses) - */ -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -/* - * Returns the kernel segment base of a given address - */ -#define KSEGX(a) (a & 0xe0000000) - -/* - * Returns the physical address of a KSEG0/KSEG1 address - */ - -#define PHYSADDR(a) ((unsigned long)a & 0x1fffffff) - -/* - * Map an address to a certain kernel segment - */ - -#define KSEG0ADDR(a) (((unsigned long)a & 0x1fffffff) | KSEG0) -#define KSEG1ADDR(a) (((unsigned long)a & 0x1fffffff) | KSEG1) -#define KSEG2ADDR(a) (((unsigned long)a & 0x1fffffff) | KSEG2) -#define KSEG3ADDR(a) (((unsigned long)a & 0x1fffffff) | KSEG3) - - -/* - * Memory segments (64bit kernel mode addresses) - */ -#define XKUSEG 0x0000 0000 0000 0000 -#define XKSSEG 0x4000 0000 0000 0000 -#define XKPHYS 0x8000 0000 0000 0000 -#define XKSEG 0xc000 0000 0000 0000 -#define CKSEG0 0xffff ffff 8000 0000 -#define CKSEG1 0xffff ffff a000 0000 -#define CKSSEG 0xffff ffff c000 0000 -#define CKSEG3 0xffff ffff e000 0000 - -#ifndef __LANGUAGE_ASSEMBLY__ -/* - * These are deprecated - */ - -#define get_fs_byte(addr) get_user_byte((char *)(addr)) -static inline unsigned char get_user_byte(const char *addr) -{ - return *addr; -} - -/* - * Beware: the xxx_fs_word functions work on 16bit words! - */ -#define get_fs_word(addr) get_user_word((short *)(addr)) -static inline unsigned short get_user_word(const short *addr) -{ - return *addr; -} - -#define get_fs_long(addr) get_user_long((int *)(addr)) -static inline unsigned long get_user_long(const int *addr) -{ - return *addr; -} - -#define get_fs_dlong(addr) get_user_dlong((long long *)(addr)) -static inline unsigned long get_user_dlong(const long long *addr) -{ - return *addr; -} - -#define put_fs_byte(x,addr) put_user_byte((x),(char *)(addr)) -static inline void put_user_byte(char val,char *addr) -{ - *addr = val; -} - -#define put_fs_word(x,addr) put_user_word((x),(short *)(addr)) -static inline void put_user_word(short val,short * addr) -{ - *addr = val; -} - -#define put_fs_long(x,addr) put_user_long((x),(int *)(addr)) -static inline void put_user_long(unsigned long val,int * addr) -{ - *addr = val; -} - -#define put_fs_dlong(x,addr) put_user_dlong((x),(int *)(addr)) -static inline void put_user_dlong(unsigned long val,long long * addr) -{ - *addr = val; -} - -#define memcpy_fromfs(to, from, n) memcpy((to),(from),(n)) - -#define memcpy_tofs(to, from, n) memcpy((to),(from),(n)) - -/* - * For segmented architectures, these are used to specify which segment - * to use for the above functions. - * - * MIPS is not segmented, so these are just dummies. - */ - -#define KERNEL_DS 0 -#define USER_DS 1 - -static inline unsigned long get_fs(void) -{ - return 0; -} - -static inline unsigned long get_ds(void) -{ - return 0; -} - -static inline void set_fs(unsigned long val) -{ -} - -#endif /* !__LANGUAGE_ASSEMBLY__ */ - -#endif /* __ASM_MIPS_SEGMENT_H */ +#endif /* __MIPS_SEGMENT_H */ diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h new file mode 100644 index 000000000..f093fe519 --- /dev/null +++ b/include/asm-mips/semaphore.h @@ -0,0 +1,46 @@ +/* + * SMP- and interrupt-safe semaphores.. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996 Linus Torvalds, Ralf Baechle + */ +#ifndef __ASM_MIPS_SEMAPHORE_H +#define __ASM_MIPS_SEMAPHORE_H + +#include <asm/atomic.h> + +struct semaphore { + atomic_t count; + atomic_t waiting; + struct wait_queue * wait; +}; + +#define MUTEX ((struct semaphore) { 1, 0, NULL }) +#define MUTEX_LOCKED ((struct semaphore) { 0, 0, NULL }) + +extern void __down(struct semaphore * sem); +extern void __up(struct semaphore * sem); + +extern inline void down(struct semaphore * sem) +{ + while (1) { + if (atomic_dec_return(&sem->count) >= 0) + break; + __down(sem); + } +} + +/* + * Note! This is subtle. We jump to wake people up only if + * the semaphore was negative (== somebody was waiting on it). + */ +extern inline void up(struct semaphore * sem) +{ + if (atomic_inc_return(&sem->count) <= 0) + __up(sem); +} + +#endif /* __ASM_MIPS_SEMAPHORE_H */ diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h new file mode 100644 index 000000000..23dc0447f --- /dev/null +++ b/include/asm-mips/sgidefs.h @@ -0,0 +1,82 @@ +/* + * Makefile for MIPS Linux main source directory + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + * + * Definitions commonly used in SGI style code. + */ +#ifndef __ASM_SGIDEFS_H +#define __ASM_SGIDEFS_H + +/* + * There are compilers out there that don't define _MIPS_ISA, _MIPS_SIM, + * _MIPS_SZINT, _MIPS_SZLONG, _MIPS_SZPTR. So we notify the user about this + * problem. The kernel sources are aware of this problem, so we don't warn + * when compiling the kernel. + */ +#if (!defined(_MIPS_ISA) || \ + !defined(_MIPS_SIM) || \ + !defined(_MIPS_SZINT) || \ + !defined(_MIPS_SZLONG) || \ + !defined(_MIPS_SZPTR)) && !defined(__KERNEL__) +#warning "Please update your GCC to GCC 2.7.2-3 or newer" +#endif + +/* + * Now lets try our best to supply some reasonable default values for + * whatever defines GCC didn't supply. This cannot be done correct for + * all possible combinations of options, so be careful with your options + * to GCC. Best bet is to keep your fingers off the a.out GCC and use + * ELF GCC 2.7.2-3 where possible. + */ +#ifndef _MIPS_ISA +#if __mips == 1 +#define _MIPS_ISA _MIPS_ISA_MIPS1 +/* It is impossible to handle the -mips2 case correct. */ +#elif __mips == 3 +#define _MIPS_ISA _MIPS_ISA_MIPS3 +#elif __mips == 4 +#define _MIPS_ISA _MIPS_ISA_MIPS4 +#else /* __mips must be 5 */ +#define _MIPS_ISA _MIPS_ISA_MIPS5 +#endif +#endif +#ifndef _MIPS_SIM +#define _MIPS_SIM _MIPS_SIM_ABI32 +#endif +#ifndef _MIPS_SZINT +#define _MIPS_SZINT 32 +#endif +#ifndef _MIPS_SZLONG +#define _MIPS_SZLONG 32 +#endif +#ifndef _MIPS_SZPTR +#define _MIPS_SZPTR 32 +#endif + +/* + * Definitions for the ISA level + */ +#define _MIPS_ISA_MIPS1 1 +#define _MIPS_ISA_MIPS2 2 +#define _MIPS_ISA_MIPS3 3 +#define _MIPS_ISA_MIPS4 4 +#define _MIPS_ISA_MIPS5 5 + +/* + * Subprogram calling convention + * + * At the moment only _MIPS_SIM_ABI32 is in use. This will change rsn. + * Until GCC 2.8.0 is released don't rely on this definitions because the + * 64bit code is essentially using the 32bit interface model just with + * 64bit registers. + */ +#define _MIPS_SIM_ABI32 1 +#define _MIPS_SIM_NABI32 2 +#define _MIPS_SIM_ABI64 3 + +#endif /* __ASM_SGIDEFS_H */ diff --git a/include/asm-mips/shmparam.h b/include/asm-mips/shmparam.h new file mode 100644 index 000000000..9c5a38a40 --- /dev/null +++ b/include/asm-mips/shmparam.h @@ -0,0 +1,47 @@ +#ifndef __ASM_MIPS_SHMPARAM_H +#define __ASM_MIPS_SHMPARAM_H + +/* address range for shared memory attaches if no address passed to shmat() */ +#define SHM_RANGE_START 0x50000000 +#define SHM_RANGE_END 0x60000000 + +/* + * Format of a swap-entry for shared memory pages currently out in + * swap space (see also mm/swap.c). + * + * SWP_TYPE = SHM_SWP_TYPE + * SWP_OFFSET is used as follows: + * + * bits 0..6 : id of shared memory segment page belongs to (SHM_ID) + * bits 7..21: index of page within shared memory segment (SHM_IDX) + * (actually fewer bits get used since SHMMAX is so low) + */ + +/* + * Keep _SHM_ID_BITS as low as possible since SHMMNI depends on it and + * there is a static array of size SHMMNI. + */ +#define _SHM_ID_BITS 7 +#define SHM_ID_MASK ((1<<_SHM_ID_BITS)-1) + +#define SHM_IDX_SHIFT (_SHM_ID_BITS) +#define _SHM_IDX_BITS 15 +#define SHM_IDX_MASK ((1<<_SHM_IDX_BITS)-1) + +/* + * _SHM_ID_BITS + _SHM_IDX_BITS must be <= 24 on the i386 and + * SHMMAX <= (PAGE_SIZE << _SHM_IDX_BITS). + */ + +#define SHMMAX 0x1000000 /* max shared seg size (bytes) */ +#define SHMMIN 1 /* really PAGE_SIZE */ /* min shared seg size (bytes) */ +#define SHMMNI (1<<_SHM_ID_BITS) /* max num of segs system wide */ +#define SHMALL /* max shm system wide (pages) */ \ + (1<<(_SHM_IDX_BITS+_SHM_ID_BITS)) +/* + * This constant is very large but the ABI in its wisdom says ... + */ +#define SHMLBA 0x40000 /* attach addr a multiple of this */ +#define SHMSEG SHMMNI /* max shared segs per process */ + +#endif /* __ASM_MIPS_SHMPARAM_H */ diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h new file mode 100644 index 000000000..135d83df6 --- /dev/null +++ b/include/asm-mips/sigcontext.h @@ -0,0 +1,48 @@ +#ifndef __ASM_MIPS_SIGCONTEXT_H +#define __ASM_MIPS_SIGCONTEXT_H + +#ifdef __LANGUAGE_ASSEMBLY__ + +#define SC_REGMASK 0 +#define SC_STATUS 4 +#define SC_PC 8 +#define SC_REGS 16 +#define SC_FPREGS 272 +#define SC_OWNEDFP 528 +#define SC_FPC_CSR 532 +#define SC_FPC_EIR 536 +#define SC_SSFLAGS 540 +#define SC_MDHI 544 +#define SC_MDLO 552 + +#endif + +#if defined(__LANGUAGE_C__) || \ + defined(__LANGUAGE_C_PLUS_PLUS__) || \ + defined(__LANGUAGE_OBJECTIVE_C__) + +/* + * Whenever this structure is changed you must update the offsets in + * arch/mips/mips<isa>/fp-context.S. + */ +struct sigcontext { + unsigned int sc_regmask; /* Unused */ + unsigned int sc_status; + unsigned long long sc_pc; + unsigned long long sc_regs[32]; + unsigned long long sc_fpregs[32]; /* Unused */ + unsigned int sc_ownedfp; + unsigned int sc_fpc_csr; /* Unused */ + unsigned int sc_fpc_eir; /* Unused */ + unsigned int sc_ssflags; /* Unused */ + unsigned long long sc_mdhi; + unsigned long long sc_mdlo; + + unsigned int sc_cause; /* Unused */ + unsigned int sc_badvaddr; /* Unused */ + + sigset_t sc_sigset; +}; +#endif + +#endif /* __ASM_MIPS_SIGCONTEXT_H */ diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 998d95c14..ced9ee9e3 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -1,63 +1,89 @@ +/* + * Linux/MIPS specific definitions for signals. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ #ifndef __ASM_MIPS_SIGNAL_H -#define __ASM_MIPS_SIGNAL_H -#if 0 -/* The Linux/i386 definition */ -typedef unsigned long sigset_t; /* at least 32 bits */ +#include <asm/sgidefs.h> + +/* Any one of these symbols __need_* means that GNU libc + wants us just to define one data type. So don't define + the symbols that indicate this file's entire job has been done. */ +#if !defined(__need_signums) && !defined(__need_fake_sigfuns) && \ + !defined(__need__nsig) +#define __ASM_MIPS_SIGNAL_H #endif -#if 1 -/* For now ... */ -#include <asm/types.h> -typedef __u64 sigset_t; -#else -/* This is what we should really use ... */ +#ifdef __ASM_MIPS_SIGNAL_H +/* + * This is what we should really use but the kernel can't handle + * a non-scalar type yet. Since we use 64 signals only anyway we + * just use __u64 and pad another 64 bits in the kernel for now ... + */ typedef struct { - unsigned int sigbits[4]; + unsigned int __sigbits[4]; } sigset_t; -#endif +#endif /* __ASM_MIPS_SIGNAL_H */ +#if !defined (___nsig_defined) && \ + (defined (__ASM_MIPS_SIGNAL_H) || defined (__need__nsig)) +#define ___nsig_defined #define _NSIG 65 +#endif +#undef __need__nsig +#ifdef __KERNEL__ #define NSIG _NSIG +#endif +#if !defined (__signums_defined) && \ + (defined (__ASM_MIPS_SIGNAL_H) || defined (__need_signums)) +#define __signums_defined /* * For 1.3.0 Linux/MIPS changed the signal numbers to be compatible the ABI. */ -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGIOT 6 -#define SIGABRT SIGIOT +#define SIGHUP 1 /* Hangup (POSIX). */ +#define SIGINT 2 /* Interrupt (ANSI). */ +#define SIGQUIT 3 /* Quit (POSIX). */ +#define SIGILL 4 /* Illegal instruction (ANSI). */ +#define SIGTRAP 5 /* Trace trap (POSIX). */ +#define SIGIOT 6 /* IOT trap (4.2 BSD). */ +#define SIGABRT SIGIOT /* Abort (ANSI). */ #define SIGEMT 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGBUS 10 -#define SIGSEGV 11 +#define SIGFPE 8 /* Floating-point exception (ANSI). */ +#define SIGKILL 9 /* Kill, unblockable (POSIX). */ +#define SIGBUS 10 /* BUS error (4.2 BSD). */ +#define SIGSEGV 11 /* Segmentation violation (ANSI). */ #define SIGSYS 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGUSR1 16 -#define SIGUSR2 17 -#define SIGCHLD 18 -#define SIGCLD SIGCHLD -#define SIGPWR 19 -#define SIGWINCH 20 -#define SIGURG 21 -#define SIGIO 22 -#define SIGPOLL SIGIO -#define SIGSTOP 23 -#define SIGTSTP 24 -#define SIGCONT 25 -#define SIGTTIN 26 -#define SIGTTOU 27 -#define SIGVTALRM 28 -#define SIGPROF 29 -#define SIGXCPU 30 -#define SIGXFSZ 31 +#define SIGPIPE 13 /* Broken pipe (POSIX). */ +#define SIGALRM 14 /* Alarm clock (POSIX). */ +#define SIGTERM 15 /* Termination (ANSI). */ +#define SIGUSR1 16 /* User-defined signal 1 (POSIX). */ +#define SIGUSR2 17 /* User-defined signal 2 (POSIX). */ +#define SIGCHLD 18 /* Child status has changed (POSIX). */ +#define SIGCLD SIGCHLD /* Same as SIGCHLD (System V). */ +#define SIGPWR 19 /* Power failure restart (System V). */ +#define SIGWINCH 20 /* Window size change (4.3 BSD, Sun). */ +#define SIGURG 21 /* Urgent condition on socket (4.2 BSD). */ +#define SIGIO 22 /* I/O now possible (4.2 BSD). */ +#define SIGPOLL SIGIO /* Pollable event occurred (System V). */ +#define SIGSTOP 23 /* Stop, unblockable (POSIX). */ +#define SIGTSTP 24 /* Keyboard stop (POSIX). */ +#define SIGCONT 25 /* Continue (POSIX). */ +#define SIGTTIN 26 /* Background read from tty (POSIX). */ +#define SIGTTOU 27 /* Background write to tty (POSIX). */ +#define SIGVTALRM 28 /* Virtual alarm clock (4.2 BSD). */ +#define SIGPROF 29 /* Profiling alarm clock (4.2 BSD). */ +#define SIGXCPU 30 /* CPU limit exceeded (4.2 BSD). */ +#define SIGXFSZ 31 /* File size limit exceeded (4.2 BSD). */ +#endif /* need signums */ +#undef __need_signums +#ifdef __ASM_MIPS_SIGNAL_H /* * sa_flags values: SA_STACK is not currently supported, but will allow the * usage of signal stacks by using the (now obsolete) sa_restorer field in @@ -65,6 +91,7 @@ typedef struct { * the changes in signal handling. LBT 010493. * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_SHIRQ flag is for shared interrupt support on PCI and EISA. */ #define SA_STACK 0x1 #define SA_ONSTACK SA_STACK @@ -74,51 +101,124 @@ typedef struct { #define SA_INTERRUPT 0x01000000 #define SA_NOMASK 0x02000000 #define SA_ONESHOT 0x04000000 +#define SA_SHIRQ 0x08000000 + +#ifdef __KERNEL__ +/* + * These values of sa_flags are used only by the kernel as part of the + * irq handling routines. + * + * SA_INTERRUPT is also used by the irq handling routines. + */ +#define SA_PROBE SA_ONESHOT +#define SA_SAMPLE_RANDOM SA_RESTART +#endif /* __KERNEL__ */ -#define SIG_BLOCK 1 /* for blocking signals */ -#define SIG_UNBLOCK 2 /* for unblocking signals */ -#define SIG_SETMASK 3 /* for setting the signal mask */ +#define SIG_BLOCK 1 /* for blocking signals */ +#define SIG_UNBLOCK 2 /* for unblocking signals */ +#define SIG_SETMASK 3 /* for setting the signal mask */ +#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: + set only the low 32 bit of the sigset. */ +#ifndef __sighandler_t_defined +#define __sighandler_t_defined /* Type of a signal handler. */ typedef void (*__sighandler_t)(int); +#endif +#endif +#if !defined (__fake_sigfuns_defined) && \ + (defined (__ASM_MIPS_SIGNAL_H) || defined (__need_fake_sigfuns)) +#define __fake_sigfuns_defined +/* Fake signal functions */ #define SIG_DFL ((__sighandler_t)0) /* default signal handling */ #define SIG_IGN ((__sighandler_t)1) /* ignore signal */ #define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#endif +#undef __need_fake_sigfuns +#ifdef __ASM_MIPS_SIGNAL_H struct sigaction { unsigned int sa_flags; __sighandler_t sa_handler; sigset_t sa_mask; + + /* Abi says here follows reserved int[2] */ void (*sa_restorer)(void); -#if __mips <= 3 +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) /* * For 32 bit code we have to pad struct sigaction to get * constant size for the ABI */ - int pad0[2]; /* reserved */ + int pad0[1]; /* reserved */ #endif }; #ifdef __KERNEL__ +#include <asm/sigcontext.h> +/* + * This type is used by the kernel internal for it's sigsets. + */ +typedef unsigned long k_sigset_t; + +extern __inline__ k_sigset_t * +to_k_sigset_t(sigset_t *set) +{ + return (k_sigset_t *) set->__sigbits; +} + +#define copy_sigbits32(set, bits) ((set)->__sigbits[0] = (bits)) + +/* + * Clear a userland sigset_t. + */ +extern __inline__ void +u_sigemptyset (sigset_t *set) +{ + set->__sigbits[0] = set->__sigbits[1] = + set->__sigbits[2] = set->__sigbits[3] = 0; +} /* - * This struct isn't in the ABI, so we continue to use the old - * pre 1.3 definition. Needs to be changed for 64 bit kernels, - * but it's 4am ... + * Add/delete sigbits from a k_sigset_t. */ -struct sigcontext_struct { - unsigned long sc_at, sc_v0, sc_v1, sc_a0, sc_a1, sc_a2, sc_a3; - unsigned long sc_t0, sc_t1, sc_t2, sc_t3, sc_t4, sc_t5, sc_t6, sc_t7; - unsigned long sc_s0, sc_s1, sc_s2, sc_s3, sc_s4, sc_s5, sc_s6, sc_s7; - unsigned long sc_t8, sc_t9, sc_gp, sc_sp, sc_fp, sc_ra; +#define __KSSMASK(nr) (1 << ((nr) - 1)) - unsigned long sc_epc; - unsigned long sc_cause; +extern __inline__ void +k_sigaddset (k_sigset_t *set, int sig) +{ + *set |= __KSSMASK (sig); +} - unsigned long oldmask; -}; +extern __inline__ void +k_sigdelset (k_sigset_t *set, int sig) +{ + *set &= ~__KSSMASK (sig); +} -#endif +#endif /* __KERNEL__ */ -#endif /* __ASM_MIPS_SIGNAL_H */ +#if defined (__KERNEL__) || defined (__USE_MISC) +/* + * The following break codes are or were in use for specific purposes in + * other MIPS operating systems. Linux/MIPS doesn't use all of them. The + * unused ones are here as placeholders; we might encounter them in + * non-Linux/MIPS object files or make use of them in the future. + */ +#define BRK_USERBP 0 /* User bp (used by debuggers) */ +#define BRK_KERNELBP 1 /* Break in the kernel */ +#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */ +#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */ +#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */ +#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */ +#define BRK_OVERFLOW 6 /* Overflow check */ +#define BRK_DIVZERO 7 /* Divide by zero check */ +#define BRK_RANGE 8 /* Range error check */ +#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ +#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ +#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ +#define BRK_MULOVF 1023 /* Multiply overflow */ +#endif /* defined (__KERNEL__) || defined (__USE_MISC) */ +#endif /* defined (__ASM_MIPS_SIGNAL_H) */ + +#endif /* !defined (__ASM_MIPS_SIGNAL_H) */ diff --git a/include/asm-mips/slots.h b/include/asm-mips/slots.h index 4b9eb358c..387802333 100644 --- a/include/asm-mips/slots.h +++ b/include/asm-mips/slots.h @@ -7,11 +7,17 @@ #ifndef __ASM_MIPS_SLOTS_H #define __ASM_MIPS_SLOTS_H +#include <linux/config.h> + /* * SLOTSPACE is the address to which the physical address 0 * of the Slotspace is mapped by the chipset in the main CPU's * address space. */ +#ifdef CONFIG_DESKSTATION_RPC44 +#define SLOTSPACE 0xa0000000 +#else #define SLOTSPACE 0xe1000000 +#endif #endif /* __ASM_MIPS_SLOTS_H */ diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h new file mode 100644 index 000000000..acf771ead --- /dev/null +++ b/include/asm-mips/smp.h @@ -0,0 +1,9 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 Ralf Baechle + * + * Linux/MIPS SMP support. Just a dummy to make building possible. + */ diff --git a/include/asm-mips/smp_lock.h b/include/asm-mips/smp_lock.h new file mode 100644 index 000000000..acf771ead --- /dev/null +++ b/include/asm-mips/smp_lock.h @@ -0,0 +1,9 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 Ralf Baechle + * + * Linux/MIPS SMP support. Just a dummy to make building possible. + */ diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h new file mode 100644 index 000000000..e5ddb6a17 --- /dev/null +++ b/include/asm-mips/socket.h @@ -0,0 +1,68 @@ +#ifndef __ASM_MIPS_SOCKET_H +#define __ASM_MIPS_SOCKET_H + +#include <linux/types.h> +#include <asm/sockios.h> + +/* + * For setsockoptions(2) + * + * This defines are ABI conformant as far as Linux supports these ... + */ +#define SOL_SOCKET 0xffff + +enum +{ + SO_DEBUG = 0x0001, /* Record debugging information. */ + SO_REUSEADDR = 0x0004, /* Allow reuse of local addresses. */ + SO_KEEPALIVE = 0x0008, /* Keep connections alive and send + SIGPIPE when they die. */ + SO_DONTROUTE = 0x0010, /* Don't do local routing. */ + SO_BROADCAST = 0x0020, /* Allow transmission of + broadcast messages. */ + SO_LINGER = 0x0080, /* Block on close of a reliable + socket to transmit pending data. */ + SO_OOBINLINE = 0x0100, /* Receive out-of-band data in-band. */ +#if 0 +To add: SO_REUSEPORT = 0x0200, /* Allow local address and port reuse. */ +#endif + + SO_TYPE = 0x1008, /* Compatible name for SO_STYLE. */ + SO_STYLE = SO_TYPE, /* Synonym */ + SO_ERROR = 0x1007, /* get error status and clear */ + SO_SNDBUF = 0x1001, /* Send buffer size. */ + SO_RCVBUF = 0x1002, /* Receive buffer. */ + SO_SNDLOWAT = 0x1003, /* send low-water mark */ + SO_RCVLOWAT = 0x1004, /* receive low-water mark */ + SO_SNDTIMEO = 0x1005, /* send timeout */ + SO_RCVTIMEO = 0x1006, /* receive timeout */ + +/* linux-specific, might as well be the same as on i386 */ + SO_NO_CHECK = 11, + SO_PRIORITY = 12, + SO_BSDCOMPAT = 14, +}; + +/* + * Weird. The existing SVr4 port to MIPS use two different definitions for + * SOCK_STREAM and SOCK_DGRAM with swapped values. I choose to be compatible + * with the newer definitions though that looks wrong ... + */ + +/* Types of sockets. */ +enum __socket_type +{ + SOCK_DGRAM = 1, /* Connectionless, unreliable datagrams + of fixed maximum length. */ + SOCK_STREAM = 2, /* Sequenced, reliable, connection-based + byte streams. */ + SOCK_RAW = 3, /* Raw protocol interface. */ + SOCK_RDM = 4, /* Reliably-delivered messages. */ + SOCK_SEQPACKET = 5, /* Sequenced, reliable, connection-based, + datagrams of fixed maximum length. */ + SOCK_PACKET = 10, /* linux specific way of getting packets at + the dev level. For writing rarp and + other similar things on the user level. */ +}; + +#endif /* __ASM_MIPS_SOCKET_H */ diff --git a/include/asm-mips/sockios.h b/include/asm-mips/sockios.h new file mode 100644 index 000000000..18ca5f9a4 --- /dev/null +++ b/include/asm-mips/sockios.h @@ -0,0 +1,25 @@ +/* + * Socket-level I/O control calls. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ +#ifndef __ASM_MIPS_SOCKIOS_H +#define __ASM_MIPS_SOCKIOS_H + +#include <asm/ioctl.h> + +/* Socket-level I/O control calls. */ +#define FIOGETOWN _IOR('f', 123, int) +#define FIOSETOWN _IOW('f', 124, int) + +#define SIOCATMARK _IOR('s', 7, int) +#define SIOCSPGRP _IOW('s', 8, pid_t) +#define SIOCGPGRP _IOR('s', 9, pid_t) + +#define SIOCGSTAMP 0x8906 /* Get stamp - linux-specific */ + +#endif /* __ASM_MIPS_SOCKIOS_H */ diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index b3b69f3c6..3cdbb61ef 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -1,109 +1,141 @@ /* - * include/asm-mips/stackframe.h + * Makefile for MIPS Linux main source directory * - * Copyright (C) 1994, 1995 Waldorf Electronics - * written by Ralf Baechle + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Paul M. Antoine. + * Additional R3000 support by Didier Frick <dfrick@dial.eunet.ch> + * for ACN S.A, Copyright (C) 1996 by ACN S.A */ - #ifndef __ASM_MIPS_STACKFRAME_H #define __ASM_MIPS_STACKFRAME_H +#include <asm/sgidefs.h> +#include <asm/asm.h> + /* * Stack layout for all exceptions: * * ptrace needs to have all regs on the stack. If the order here is changed, * it needs to be updated in include/asm-mips/ptrace.h * - * The first PTRSIZE*5 bytes are argument save space for C subroutines. + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + * zero doesn't get saved; it's just a placeholder. */ -#define FR_REG1 (PTRSIZE*5) -#define FR_REG2 ((FR_REG1) + 4) -#define FR_REG3 ((FR_REG2) + 4) -#define FR_REG4 ((FR_REG3) + 4) -#define FR_REG5 ((FR_REG4) + 4) -#define FR_REG6 ((FR_REG5) + 4) -#define FR_REG7 ((FR_REG6) + 4) -#define FR_REG8 ((FR_REG7) + 4) -#define FR_REG9 ((FR_REG8) + 4) -#define FR_REG10 ((FR_REG9) + 4) -#define FR_REG11 ((FR_REG10) + 4) -#define FR_REG12 ((FR_REG11) + 4) -#define FR_REG13 ((FR_REG12) + 4) -#define FR_REG14 ((FR_REG13) + 4) -#define FR_REG15 ((FR_REG14) + 4) -#define FR_REG16 ((FR_REG15) + 4) -#define FR_REG17 ((FR_REG16) + 4) -#define FR_REG18 ((FR_REG17) + 4) -#define FR_REG19 ((FR_REG18) + 4) -#define FR_REG20 ((FR_REG19) + 4) -#define FR_REG21 ((FR_REG20) + 4) -#define FR_REG22 ((FR_REG21) + 4) -#define FR_REG23 ((FR_REG22) + 4) -#define FR_REG24 ((FR_REG23) + 4) -#define FR_REG25 ((FR_REG24) + 4) +#define FR_REG0 (SZREG*6) +#define FR_REG1 ((FR_REG0) + SZREG) +#define FR_REG2 ((FR_REG1) + SZREG) +#define FR_REG3 ((FR_REG2) + SZREG) +#define FR_REG4 ((FR_REG3) + SZREG) +#define FR_REG5 ((FR_REG4) + SZREG) +#define FR_REG6 ((FR_REG5) + SZREG) +#define FR_REG7 ((FR_REG6) + SZREG) +#define FR_REG8 ((FR_REG7) + SZREG) +#define FR_REG9 ((FR_REG8) + SZREG) +#define FR_REG10 ((FR_REG9) + SZREG) +#define FR_REG11 ((FR_REG10) + SZREG) +#define FR_REG12 ((FR_REG11) + SZREG) +#define FR_REG13 ((FR_REG12) + SZREG) +#define FR_REG14 ((FR_REG13) + SZREG) +#define FR_REG15 ((FR_REG14) + SZREG) +#define FR_REG16 ((FR_REG15) + SZREG) +#define FR_REG17 ((FR_REG16) + SZREG) +#define FR_REG18 ((FR_REG17) + SZREG) +#define FR_REG19 ((FR_REG18) + SZREG) +#define FR_REG20 ((FR_REG19) + SZREG) +#define FR_REG21 ((FR_REG20) + SZREG) +#define FR_REG22 ((FR_REG21) + SZREG) +#define FR_REG23 ((FR_REG22) + SZREG) +#define FR_REG24 ((FR_REG23) + SZREG) +#define FR_REG25 ((FR_REG24) + SZREG) /* - * $26 (k0) and $27 (k1) not saved + * $26 (k0) and $27 (k1) not saved - just placeholders */ -#define FR_REG28 ((FR_REG25) + 4) -#define FR_REG29 ((FR_REG28) + 4) -#define FR_REG30 ((FR_REG29) + 4) -#define FR_REG31 ((FR_REG30) + 4) +#define FR_REG26 ((FR_REG25) + SZREG) +#define FR_REG27 ((FR_REG26) + SZREG) + +#define FR_REG28 ((FR_REG27) + SZREG) +#define FR_REG29 ((FR_REG28) + SZREG) +#define FR_REG30 ((FR_REG29) + SZREG) +#define FR_REG31 ((FR_REG30) + SZREG) /* * Saved special registers */ -#define FR_LO ((FR_REG31) + 4) -#define FR_HI ((FR_LO) + 4) +#define FR_LO ((FR_REG31) + SZREG) +#define FR_HI ((FR_LO) + SZREG) +#define FR_ORIG_REG2 ((FR_HI) + SZREG) +#define FR_ORIG_REG7 ((FR_ORIG_REG2) + SZREG) /* * Saved cp0 registers follow */ -#define FR_STATUS ((FR_HI) + 4) -#define FR_EPC ((FR_STATUS) + 4) -#define FR_CAUSE ((FR_EPC) + 4) +#define FR_EPC ((FR_ORIG_REG7) + SZREG) +#define FR_BADVADDR ((FR_EPC) + SZREG) +#define FR_STATUS ((FR_BADVADDR) + SZREG) +#define FR_CAUSE ((FR_STATUS) + 4) /* - * Some goodies... + * Size of stack frame, word/double word alignment */ -#define FR_INTERRUPT ((FR_CAUSE) + 4) -#define FR_ORIG_REG2 ((FR_INTERRUPT) + 4) -#define FR_PAD1 ((FR_ORIG_REG2) + 4) +#define FR_SIZE (((FR_CAUSE + 4) + ALSZ) & ALMASK) /* - * Size of stack frame, word/double word alignment + * Load the global pointer. Only for ELF executables global pointer + * optimization is possible, so we only load the global pointer for + * ELF kernels. */ -#define FR_SIZE ((((FR_PAD1) + 4) + (PTRSIZE-1)) & ~(PTRSIZE-1)) +#if 0 +#define LOAD_GP la gp,_gp +#else +#define LOAD_GP +#endif -#ifdef __R4000__ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) #define SAVE_ALL \ mfc0 k0,CP0_STATUS; \ - sll k0,3; /* extract cu0 bit */ \ - bltz k0,8f; \ + li k1,ST0_CU0; \ + and k0,k1; \ + bnez k0,8f; \ move k1,sp; \ + nop; \ /* \ * Called from user mode, new stack \ */ \ - lui k1,%hi(kernelsp); \ - lw k1,%lo(kernelsp)(k1); \ + lw k1,kernelsp; \ 8: move k0,sp; \ subu sp,k1,FR_SIZE; \ sw k0,FR_REG29(sp); \ - sw $2,FR_REG2(sp); \ - sw $2,FR_ORIG_REG2(sp); \ - mfc0 v0,CP0_STATUS; \ - sw v0,FR_STATUS(sp); \ - mfc0 v0,CP0_CAUSE; \ - sw v0,FR_CAUSE(sp); \ - mfc0 v0,CP0_EPC; \ - sw v0,FR_EPC(sp); \ - mfhi v0; \ - sw v0,FR_HI(sp); \ - mflo v0; \ - sw v0,FR_LO(sp); \ - sw $1,FR_REG1(sp); \ sw $3,FR_REG3(sp); \ + mfc0 $3,CP0_STATUS; \ + nop; \ + sw $3,FR_STATUS(sp); \ + li k1,ST0_CU0; \ + or k1,$3; \ + mtc0 k1,CP0_STATUS; \ + nop; \ + mfc0 $3,CP0_ENTRYHI; \ + nop; \ + sw $3,FR_ENTRYHI(sp); \ + mfc0 $3,CP0_CAUSE; \ + nop; \ + sw $3,FR_CAUSE(sp); \ + mfc0 $3,CP0_EPC; \ + nop; \ + sw $3,FR_EPC(sp); \ + mfc0 $3,CP0_BADVADDR; \ + nop; \ + sw $3,FR_BADVADDR(sp); \ + mfhi $3; \ + sw $3,FR_HI(sp); \ + mflo $3; \ + sw $3,FR_LO(sp); \ + sw $1,FR_REG1(sp); \ + sw $2,FR_REG2(sp); \ sw $4,FR_REG4(sp); \ sw $5,FR_REG5(sp); \ sw $6,FR_REG6(sp); \ @@ -128,24 +160,25 @@ sw $25,FR_REG25(sp); \ sw $28,FR_REG28(sp); \ sw $30,FR_REG30(sp); \ - sw $31,FR_REG31(sp) + sw $31,FR_REG31(sp); \ + LOAD_GP /* * Note that we restore the IE flags from stack. This means * that a modified IE mask will be nullified. */ -#define RESTORE_ALL \ - .set mips3; \ +/* + * FIXME: Don't need to clear these bits on R[236]000's?? + * mfc0 t0,CP0_STATUS; \ ori t0,0x1f; \ xori t0,0x1f; \ mtc0 t0,CP0_STATUS; \ - \ - lw v0,FR_STATUS(sp); \ + */ +#define RESTORE_ALL \ lw v1,FR_LO(sp); \ - mtc0 v0,CP0_STATUS; \ - mtlo v1; \ lw v0,FR_HI(sp); \ + mtlo v1; \ lw v1,FR_EPC(sp); \ mthi v0; \ mtc0 v1,CP0_EPC; \ @@ -177,13 +210,169 @@ lw $3,FR_REG3(sp); \ lw $2,FR_REG2(sp); \ lw $1,FR_REG1(sp); \ - lw sp,FR_REG29(sp); /* Deallocate stack */ \ - .set mips0 + lw k1,FR_STATUS(sp); \ + lw sp,FR_REG29(sp); \ + ori k1,3; \ + xori k1,3; \ + mtc0 k1,CP0_STATUS; \ + nop + +/* + * We disable interrupts when restoring the status register because: + * 1) the ret_from_syscall routine uses k0/k1 to preserve values around + * the RESTORE_ALL + * 2) the rfe instruction will restore the IE and KU flags to their + * previous value. + */ + +#define CLI \ + mfc0 t1,$12; \ + li t0,ST0_CU0|1; \ + or t1,t1,t0; \ + xori t1,1; \ + mtc0 t1,$12; \ + nop; \ + nop + +#define STI \ + mfc0 t1,$12; \ + li t0,ST0_CU0|1; \ + or t1,t1,t0; \ + mtc0 t1,$12; \ + nop; \ + nop + +#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) */ -#else /* !defined (__R4000__) */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) -#error "Implement SAVE_ALL and RESTORE_ALL!" +#define SAVE_ALL \ + mfc0 k0,CP0_STATUS; \ + sll k0,3; /* extract cu0 bit */ \ + bltz k0,8f; \ + move k1,sp; \ + /* \ + * Called from user mode, new stack \ + */ \ + lw k1,kernelsp; \ +8: move k0,sp; \ + subu sp,k1,FR_SIZE; \ + sd k0,FR_REG29(sp); \ + sd $3,FR_REG3(sp); \ + mfc0 $3,CP0_STATUS; \ + sw $3,FR_STATUS(sp); \ + mfc0 $3,CP0_CAUSE; \ + sw $3,FR_CAUSE(sp); \ + dmfc0 $3,CP0_EPC; \ + sd $3,FR_EPC(sp); \ + mfhi $3; \ + sd $3,FR_HI(sp); \ + mflo $3; \ + sd $3,FR_LO(sp); \ + sd $1,FR_REG1(sp); \ + sd $2,FR_REG2(sp); \ + sd $4,FR_REG4(sp); \ + sd $5,FR_REG5(sp); \ + sd $6,FR_REG6(sp); \ + sd $7,FR_REG7(sp); \ + sd $8,FR_REG8(sp); \ + sd $9,FR_REG9(sp); \ + sd $10,FR_REG10(sp); \ + sd $11,FR_REG11(sp); \ + sd $12,FR_REG12(sp); \ + sd $13,FR_REG13(sp); \ + sd $14,FR_REG14(sp); \ + sd $15,FR_REG15(sp); \ + sd $16,FR_REG16(sp); \ + sd $17,FR_REG17(sp); \ + sd $18,FR_REG18(sp); \ + sd $19,FR_REG19(sp); \ + sd $20,FR_REG20(sp); \ + sd $21,FR_REG21(sp); \ + sd $22,FR_REG22(sp); \ + sd $23,FR_REG23(sp); \ + sd $24,FR_REG24(sp); \ + sd $25,FR_REG25(sp); \ + sd $28,FR_REG28(sp); \ + sd $30,FR_REG30(sp); \ + sd $31,FR_REG31(sp); \ + LOAD_GP + +/* + * Note that we restore the IE flags from stack. This means + * that a modified IE mask will be nullified. + */ +#define RESTORE_ALL \ + mfc0 t0,CP0_STATUS; \ + ori t0,0x1f; \ + xori t0,0x1f; \ + mtc0 t0,CP0_STATUS; \ + \ + lw v0,FR_STATUS(sp); \ + ld v1,FR_LO(sp); \ + mtc0 v0,CP0_STATUS; \ + mtlo v1; \ + ld v0,FR_HI(sp); \ + ld v1,FR_EPC(sp); \ + mthi v0; \ + dmtc0 v1,CP0_EPC; \ + ld $31,FR_REG31(sp); \ + ld $30,FR_REG30(sp); \ + ld $28,FR_REG28(sp); \ + ld $25,FR_REG25(sp); \ + ld $24,FR_REG24(sp); \ + ld $23,FR_REG23(sp); \ + ld $22,FR_REG22(sp); \ + ld $21,FR_REG21(sp); \ + ld $20,FR_REG20(sp); \ + ld $19,FR_REG19(sp); \ + ld $18,FR_REG18(sp); \ + ld $17,FR_REG17(sp); \ + ld $16,FR_REG16(sp); \ + ld $15,FR_REG15(sp); \ + ld $14,FR_REG14(sp); \ + ld $13,FR_REG13(sp); \ + ld $12,FR_REG12(sp); \ + ld $11,FR_REG11(sp); \ + ld $10,FR_REG10(sp); \ + ld $9,FR_REG9(sp); \ + ld $8,FR_REG8(sp); \ + ld $7,FR_REG7(sp); \ + ld $6,FR_REG6(sp); \ + ld $5,FR_REG5(sp); \ + ld $4,FR_REG4(sp); \ + ld $3,FR_REG3(sp); \ + ld $2,FR_REG2(sp); \ + ld $1,FR_REG1(sp); \ + ld sp,FR_REG29(sp) /* Deallocate stack */ \ + +/* + * Move to kernel mode and disable interrupts. + * Set cp0 enable bit as sign that we're running on the kernel stack + */ +#define CLI \ + mfc0 t0,CP0_STATUS; \ + li t1,ST0_CU0|0x1f; \ + or t0,t1; \ + xori t0,0x1f; \ + mtc0 t0,CP0_STATUS + +/* + * Move to kernel mode and enable interrupts. + * Set cp0 enable bit as sign that we're running on the kernel stack + * + * Note that the mtc0 will be effective on R4000 pipeline stage 7. This + * means that another three instructions will be executed with interrupts + * disabled. Arch/mips/mips3/r4xx0.S makes use of this fact. + */ +#define STI \ + mfc0 t0,CP0_STATUS; \ + li t1,ST0_CU0|0x1f; \ + or t0,t1; \ + xori t0,0x1e; \ + mtc0 t0,CP0_STATUS -#endif /* !defined (__R4000__) */ +#endif /* _MIPS_ISA >= MIPS3 */ #endif /* __ASM_MIPS_STACKFRAME_H */ diff --git a/include/asm-mips/stat.h b/include/asm-mips/stat.h index ffae5bbcf..9b2f48ed9 100644 --- a/include/asm-mips/stat.h +++ b/include/asm-mips/stat.h @@ -1,9 +1,9 @@ #ifndef __ASM_MIPS_STAT_H #define __ASM_MIPS_STAT_H -#include <asm/types.h> +#include <linux/types.h> -struct old_stat { +struct __old_kernel_stat { unsigned int st_dev; unsigned int st_ino; unsigned int st_mode; @@ -15,13 +15,13 @@ struct old_stat { unsigned int st_atime, st_res1; unsigned int st_mtime, st_res2; unsigned int st_ctime, st_res3; - unsigned int st_blkize; + unsigned int st_blksize; int st_blocks; unsigned int st_flags; unsigned int st_gen; }; -struct new_stat { +struct stat { dev_t st_dev; long st_pad1[3]; /* Reserved for network id */ ino_t st_ino; diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h index 3cae73206..500f6f1b6 100644 --- a/include/asm-mips/statfs.h +++ b/include/asm-mips/statfs.h @@ -1,25 +1,40 @@ +/* + * Definitions for the statfs(2) call. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ #ifndef __ASM_MIPS_STATFS_H #define __ASM_MIPS_STATFS_H -typedef struct { - long val[2]; -} fsid_t; +#include <linux/posix_types.h> + +#ifndef __KERNEL_STRICT_NAMES + +#include <linux/types.h> + +typedef __kernel_fsid_t fsid_t; + +#endif struct statfs { - long f_type; + long f_type; #define f_fstyp f_type - long f_bsize; - long f_frsize; /* Fragment size - unsupported */ - long f_blocks; - long f_bfree; - long f_files; - long f_ffree; + long f_bsize; + long f_frsize; /* Fragment size - unsupported */ + long f_blocks; + long f_bfree; + long f_files; + long f_ffree; /* Linux specials */ long f_bavail; - fsid_t f_fsid; - long f_namelen; - long f_spare[6]; + __kernel_fsid_t f_fsid; + long f_namelen; + long f_spare[6]; }; #endif /* __ASM_MIPS_STATFS_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 1142eaf30..1773abd81 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -5,15 +5,20 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1994, 1995 Waldorf Electronics - * written by Ralf Baechle + * Copyright (c) 1994, 1995, 1996 by Ralf Baechle */ #ifndef __ASM_MIPS_STRING_H #define __ASM_MIPS_STRING_H -extern __inline__ char * strcpy(char * dest, const char *src) +#ifdef __KERNEL__ + +#include <linux/linkage.h> +#include <asm/sgidefs.h> + +#define __HAVE_ARCH_STRCPY +extern __inline__ char *strcpy(char *__dest, __const__ char *__src) { - char *xdest = dest; + char *__xdest = __dest; __asm__ __volatile__( ".set\tnoreorder\n\t" @@ -25,41 +30,43 @@ extern __inline__ char * strcpy(char * dest, const char *src) "addiu\t%0,1\n\t" ".set\tat\n\t" ".set\treorder" - : "=r" (dest), "=r" (src) - : "0" (dest), "1" (src) + : "=r" (__dest), "=r" (__src) + : "0" (__dest), "1" (__src) : "$1","memory"); - return xdest; + return __xdest; } -extern __inline__ char * strncpy(char *dest, const char *src, size_t n) +#define __HAVE_ARCH_STRNCPY +extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) { - char *xdest = dest; + char *__xdest = __dest; - if (n == 0) - return xdest; + if (__n == 0) + return __xdest; __asm__ __volatile__( ".set\tnoreorder\n\t" ".set\tnoat\n" "1:\tlbu\t$1,(%1)\n\t" - "subu\t%2,%2,1\n\t" + "subu\t%2,1\n\t" "sb\t$1,(%0)\n\t" "beqz\t$1,2f\n\t" - "addiu\t%0,%0,1\n\t" + "addiu\t%0,1\n\t" "bnez\t%2,1b\n\t" - "addiu\t%1,%1,1\n" + "addiu\t%1,1\n" "2:\n\t" ".set\tat\n\t" - ".set\treorder\n\t" - : "=r" (dest), "=r" (src), "=r" (n) - : "0" (dest), "1" (src), "2" (n) + ".set\treorder" + : "=r" (__dest), "=r" (__src), "=r" (__n) + : "0" (__dest), "1" (__src), "2" (__n) : "$1","memory"); - return dest; + return __dest; } -extern __inline__ int strcmp(const char * cs, const char * ct) +#define __HAVE_ARCH_STRCMP +extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) { int __res; @@ -73,21 +80,22 @@ extern __inline__ int strcmp(const char * cs, const char * ct) "addiu\t%1,1\n\t" "bnez\t%2,1b\n\t" "lbu\t%2,(%0)\n\t" -#ifndef __R4000__ +#if _MIPS_ISA == _MIPS_ISA_MIPS1 "nop\n\t" #endif "move\t%2,$1\n" "2:\tsubu\t%2,$1\n" "3:\t.set\tat\n\t" ".set\treorder" - : "=d" (cs), "=d" (ct), "=d" (__res) - : "0" (cs), "1" (ct) + : "=r" (__cs), "=r" (__ct), "=r" (__res) + : "0" (__cs), "1" (__ct) : "$1"); return __res; } -extern __inline__ int strncmp(const char * cs, const char * ct, size_t count) +#define __HAVE_ARCH_STRNCMP +extern __inline__ int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) { char __res; @@ -106,114 +114,350 @@ extern __inline__ int strncmp(const char * cs, const char * ct, size_t count) "3:\tsubu\t%3,$1\n\t" ".set\tat\n\t" ".set\treorder" - : "=d" (cs), "=d" (ct), "=d" (count), "=d" (__res) - : "0" (cs), "1" (ct), "2" (count) + : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) + : "0" (__cs), "1" (__ct), "2" (__count) : "$1"); return __res; } -extern __inline__ void * memset(void * s, int c, size_t count) +#define __HAVE_ARCH_MEMSET +/* + * Ok, this definately looks braindead. I tried several other variants + * some of which GCC wasn't able to optimize or which made GCC consume + * extreme amounts of memory. + * This code attempts never to generate address errors which require + * expensive software emulation. For this purpose GCC's __alignof__ + * seems to be perfect. Unfortunately GCC 2.7.2 complains about + * __alignof__(*p) when p is a pointer to void. For now I ignore these + * warnings. + */ + +extern void __generic_memset_b(void *__s, int __c, size_t __count); +extern void __generic_memset_dw(void *__s, unsigned long long __c, + size_t __count); + +/* + * The constant c handling looks wired but it combines minimal code + * size with fast execution. + */ +#define __generic_memset(s, c, count, const_c) \ +({if(const_c) { \ + unsigned long long __dwc; \ +\ + __dwc = c & 0xff; \ + __dwc = (__dwc << 8) | __dwc; \ + __dwc = (__dwc << 16) | __dwc; \ + __dwc = (__dwc << 32) | __dwc; \ + __generic_memset_dw(s, __dwc, count); \ + } \ +else \ + __generic_memset_b(s, c, count); \ +}) + +extern __inline__ void __const_count_memset1(void *__s, int __c, size_t __count, + int __const_c) { - void *xs = s; + switch(__count) { + case 0: return; + case 1: *(0+(char *)__s) = __c; + return; + case 2: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + return; + case 3: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + *(2+(char *)__s) = __c; + return; + case 4: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + *(2+(char *)__s) = __c; + *(3+(char *)__s) = __c; + return; + case 5: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + *(2+(char *)__s) = __c; + *(3+(char *)__s) = __c; + *(4+(char *)__s) = __c; + return; + case 6: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + *(2+(char *)__s) = __c; + *(3+(char *)__s) = __c; + *(4+(char *)__s) = __c; + *(5+(char *)__s) = __c; + return; + case 7: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + *(2+(char *)__s) = __c; + *(3+(char *)__s) = __c; + *(4+(char *)__s) = __c; + *(5+(char *)__s) = __c; + *(6+(char *)__s) = __c; + return; + case 8: *(0+(char *)__s) = __c; + *(1+(char *)__s) = __c; + *(2+(char *)__s) = __c; + *(3+(char *)__s) = __c; + *(4+(char *)__s) = __c; + *(5+(char *)__s) = __c; + *(6+(char *)__s) = __c; + *(7+(char *)__s) = __c; + return; + } + __generic_memset(__s, __c, __count, __const_c); + return; +} - if (!count) - return xs; - __asm__ __volatile__( - ".set\tnoreorder\n" - "1:\tsb\t%3,(%0)\n\t" - "bne\t%0,%1,1b\n\t" - "addiu\t%0,%0,1\n\t" - ".set\treorder" - : "=r" (s), "=r" (count) - : "0" (s), "r" (c), "1" (s + count - 1) - : "memory"); +extern __inline__ void __const_count_memset2(void *__s, int __c, size_t __count, + int __const_c) +{ + switch(__count) { + case 0: return; + case 2: *(0+(short *)__s) = 0x0101 * __c; + return; + case 4: *(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + return; + case 6: *(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + *(2+(short *)__s) = 0x0101 * __c; + return; + case 8: *(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + *(2+(short *)__s) = 0x0101 * __c; + *(3+(short *)__s) = 0x0101 * __c; + return; + case 10:*(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + *(2+(short *)__s) = 0x0101 * __c; + *(3+(short *)__s) = 0x0101 * __c; + *(4+(short *)__s) = 0x0101 * __c; + return; + case 12:*(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + *(2+(short *)__s) = 0x0101 * __c; + *(3+(short *)__s) = 0x0101 * __c; + *(4+(short *)__s) = 0x0101 * __c; + *(5+(short *)__s) = 0x0101 * __c; + return; + case 14:*(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + *(2+(short *)__s) = 0x0101 * __c; + *(3+(short *)__s) = 0x0101 * __c; + *(4+(short *)__s) = 0x0101 * __c; + *(5+(short *)__s) = 0x0101 * __c; + *(6+(short *)__s) = 0x0101 * __c; + return; + case 16:*(0+(short *)__s) = 0x0101 * __c; + *(1+(short *)__s) = 0x0101 * __c; + *(2+(short *)__s) = 0x0101 * __c; + *(3+(short *)__s) = 0x0101 * __c; + *(4+(short *)__s) = 0x0101 * __c; + *(5+(short *)__s) = 0x0101 * __c; + *(6+(short *)__s) = 0x0101 * __c; + *(7+(short *)__s) = 0x0101 * __c; + return; + } + __generic_memset(__s, __c, __count, __const_c); + return; +} - return xs; +extern __inline__ void __const_count_memset4(void *__s, int __c, size_t __count, + int __const_c) +{ + switch(__count) { + case 0: return; + case 4: *(0+(int *)__s) = 0x01010101 * __c; + return; + case 8: *(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + return; + case 12:*(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + *(2+(int *)__s) = 0x01010101 * __c; + return; + case 16:*(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + *(2+(int *)__s) = 0x01010101 * __c; + *(3+(int *)__s) = 0x01010101 * __c; + return; + case 20:*(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + *(2+(int *)__s) = 0x01010101 * __c; + *(3+(int *)__s) = 0x01010101 * __c; + *(4+(int *)__s) = 0x01010101 * __c; + return; + case 24:*(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + *(2+(int *)__s) = 0x01010101 * __c; + *(3+(int *)__s) = 0x01010101 * __c; + *(4+(int *)__s) = 0x01010101 * __c; + *(5+(int *)__s) = 0x01010101 * __c; + return; + case 28:*(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + *(2+(int *)__s) = 0x01010101 * __c; + *(3+(int *)__s) = 0x01010101 * __c; + *(4+(int *)__s) = 0x01010101 * __c; + *(5+(int *)__s) = 0x01010101 * __c; + *(6+(int *)__s) = 0x01010101 * __c; + return; + case 32:*(0+(int *)__s) = 0x01010101 * __c; + *(1+(int *)__s) = 0x01010101 * __c; + *(2+(int *)__s) = 0x01010101 * __c; + *(3+(int *)__s) = 0x01010101 * __c; + *(4+(int *)__s) = 0x01010101 * __c; + *(5+(int *)__s) = 0x01010101 * __c; + *(6+(int *)__s) = 0x01010101 * __c; + *(7+(int *)__s) = 0x01010101 * __c; + return; + } + __generic_memset(__s, __c, __count, __const_c); + return; } -extern __inline__ void * memcpy(void * to, const void * from, size_t n) +extern __inline__ void __const_count_memset8(void *__s, int __c, size_t __count, + int __const_c) { - void *xto = to; + unsigned long long __dwc; - if (!n) - return xto; - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%1,1\n\t" - "sb\t$1,(%0)\n\t" - "subu\t%2,1\n\t" - "bnez\t%2,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (to), "=r" (from), "=r" (n) - : "0" (to), "1" (from), "2" (n) - : "$1","memory" ); - return xto; + __dwc = __c & 0xff; + __dwc = (__dwc << 8) | __dwc; + __dwc = (__dwc << 16) | __dwc; + __dwc = (__dwc << 32) | __dwc; + switch(__count) { + case 0: return; + case 8: *(0+(long long *)__s) = __dwc; + return; + case 16:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + return; + case 24:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + *(2+(long long *)__s) = __dwc; + return; + case 32:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + *(2+(long long *)__s) = __dwc; + *(3+(long long *)__s) = __dwc; + return; + case 40:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + *(2+(long long *)__s) = __dwc; + *(3+(long long *)__s) = __dwc; + *(4+(long long *)__s) = __dwc; + return; + case 48:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + *(2+(long long *)__s) = __dwc; + *(3+(long long *)__s) = __dwc; + *(4+(long long *)__s) = __dwc; + *(5+(long long *)__s) = __dwc; + return; + case 56:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + *(2+(long long *)__s) = __dwc; + *(3+(long long *)__s) = __dwc; + *(4+(long long *)__s) = __dwc; + *(5+(long long *)__s) = __dwc; + *(6+(long long *)__s) = __dwc; + return; + case 64:*(0+(long long *)__s) = __dwc; + *(1+(long long *)__s) = __dwc; + *(2+(long long *)__s) = __dwc; + *(3+(long long *)__s) = __dwc; + *(4+(long long *)__s) = __dwc; + *(5+(long long *)__s) = __dwc; + *(6+(long long *)__s) = __dwc; + *(7+(long long *)__s) = __dwc; + return; + } + __generic_memset(__s, __c, __count, __const_c); + return; } -extern __inline__ void * memmove(void * dest,const void * src, size_t n) +extern __inline__ void * __const_count_memset(void *__s, int __c, + size_t __count, int __align, + int __const_c) { - void *xdest = dest; + switch(__align) { + /* + * We only want this for the 64 bit CPUs; this gets + * too bloated on 32 bit. + */ + case 1: __const_count_memset1(__s, __c, __count, __const_c); + return __s; + case 2: __const_count_memset2(__s, __c, __count, __const_c); + return __s; + case 4: __const_count_memset4(__s, __c, __count, __const_c); + return __s; +#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS5) + case 8: __const_count_memset8(__s, __c, __count, __const_c); + return __s; +#endif + } + __generic_memset(__s, __c, __count, __const_c); + return __s; +} - if (!n) - return xdest; +#define memset(s, c, count) \ +(__builtin_constant_p(count) ? \ + __const_count_memset((s),(c),(count),__alignof__(*(s)), \ + __builtin_constant_p(c)) : \ + __generic_memset((s),(c),(count),__builtin_constant_p(c))) - if (dest < src) - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%1,1\n\t" - "sb\t$1,(%0)\n\t" - "subu\t%2,1\n\t" - "bnez\t%2,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (dest), "=r" (src), "=r" (n) - : "0" (dest), "1" (src), "2" (n) - : "$1","memory" ); - else - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,-1(%1)\n\t" - "subu\t%1,1\n\t" - "sb\t$1,-1(%0)\n\t" - "subu\t%2,1\n\t" - "bnez\t%2,1b\n\t" - "subu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (dest), "=r" (src), "=r" (n) - : "0" (dest+n), "1" (src+n), "2" (n) - : "$1","memory" ); - return xdest; +#define __HAVE_ARCH_MEMCPY +extern void __memcpy(void *__to, __const__ void *__from, size_t __n); +extern __inline__ void *memcpy(void *__to, __const__ void *__from, size_t __n) +{ + __memcpy(__to, __from, __n); + + return __to; +} + +#define __HAVE_ARCH_MEMMOVE +extern void __memmove(void *__dest, __const__ void *__src, size_t __n); +extern __inline__ void *memmove(void *__dest, __const__ void *__src, size_t __n) +{ + __memmove(__dest, __src, __n); + + return __dest; } -extern __inline__ void * memscan(void * addr, int c, size_t size) +#define __HAVE_ARCH_BCOPY +extern __inline__ char *bcopy(__const__ char *__src, char *__dest, size_t __count) { - if (!size) - return addr; - __asm__(".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tbeqz\t%1,2f\n\t" - "lbu\t$1,(%0)\n\t" - "subu\t%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,1\n\t" + __memmove(__dest, __src, __count); + + return __dest; +} + +#define __HAVE_ARCH_MEMSCAN +extern __inline__ void *memscan(void *__addr, int __c, size_t __size) +{ + char *__end = (char *)__addr + __size; + + if (!__size) + return __addr; + __asm__(".set\tnoat\n" + "1:\tlbu\t$1,(%0)\n\t" + ".set\tnoreorder\n\t" + "beq\t$1,%3,2f\n\t" + "addiu\t%0,1\t\t\t# delay slot\n\t" + ".set\treorder\n\t" ".set\tat\n\t" - ".set\treorder\n" - "2:" - : "=r" (addr), "=r" (size) - : "0" (addr), "1" (size), "r" (c) + "bne\t%0,%2,1b\n\t" + "2:\n" + : "=r" (__addr) + : "0" (__addr), "1" (__end), "r" (__c) : "$1"); - return addr; + return __addr; } +#endif /* __KERNEL__ */ + #endif /* __ASM_MIPS_STRING_H */ diff --git a/include/asm-mips/sysmips.h b/include/asm-mips/sysmips.h new file mode 100644 index 000000000..f0d13cfd5 --- /dev/null +++ b/include/asm-mips/sysmips.h @@ -0,0 +1,25 @@ +/* + * Definitions for the MIPS sysmips(2) call + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 by Ralf Baechle + */ +#ifndef __ASM_MIPS_SYSMIPS_H +#define __ASM_MIPS_SYSMIPS_H + +/* + * Commands for the sysmips(2) call + * + * sysmips(2) is deprecated - though some existing software uses it. + * We only support the following commands. + */ +#define SETNAME 1 /* set hostname */ +#define FLUSH_CACHE 3 /* writeback and invalidate caches */ +#define MIPS_FIXADE 7 /* control address error fixing */ +#define MIPS_RDNVRAM 10 /* read NVRAM */ +#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ + +#endif /* __ASM_MIPS_SYSMIPS_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index ef8c51b21..5489dd87a 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -5,108 +5,136 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Ralf Baechle + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle, Paul M. Antoine */ #ifndef __ASM_MIPS_SYSTEM_H #define __ASM_MIPS_SYSTEM_H -#if defined (__R4000__) -#define sti() \ -__asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "mfc0\t$1,$12\n\t" \ - "ori\t$1,0x1f\n\t" \ - "xori\t$1,0x1e\n\t" \ - "mtc0\t$1,$12\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - : /* no outputs */ \ - : /* no inputs */ \ - : "$1") +#include <linux/linkage.h> +#include <asm/sgidefs.h> -#define cli() \ -__asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "mfc0\t$1,$12\n\t" \ - "ori\t$1,1\n\t" \ - "xori\t$1,1\n\t" \ - "mtc0\t$1,$12\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - : /* no outputs */ \ - : /* no inputs */ \ - : "$1") +/* + * sti/cli/save_flags use a memory clobber to make shure GCC doesn't + * move memory references around calls to these functions. + */ +extern __inline__ void +sti(void) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,1\n\t" + "mtc0\t$1,$12\n\t" + ".set\tat\n\t" + ".set\treorder" + : /* no outputs */ + : /* no inputs */ + : "$1","memory"); +} -#else /* !defined (__R4000__) */ /* - * Untested goodies for the R3000 based DECstation et al. + * For cli() we have to make shure that the new c0_status value has + * really arrived in the status register at the end of the inline + * function using worst case scheduling. The worst case is the R4000 + * which needs three nops. */ -#define sti() \ -__asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "mfc0\t$1,$12\n\t" \ - "ori\t$1,0x01\n\t" \ - "mtc0\t$1,$12\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - : /* no outputs */ \ - : /* no inputs */ \ - : "$1") +extern __inline__ void +cli(void) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,1\n\t" + "xori\t$1,1\n\t" + "mtc0\t$1,$12\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\tat\n\t" + ".set\treorder" + : /* no outputs */ + : /* no inputs */ + : "$1","memory"); +} -#define cli() \ +#define save_flags(x) \ __asm__ __volatile__( \ ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "mfc0\t$1,$12\n\t" \ - "ori\t$1,1\n\t" \ - "xori\t$1,1\n\t" \ - "mtc0\t$1,$12\n\t" \ - ".set\tat\n\t" \ + "mfc0\t%0,$12\n\t" \ ".set\treorder" \ - : /* no outputs */ \ + : "=r" (x) \ : /* no inputs */ \ - : "$1") -#endif /* !defined (__R4000__) */ + : "memory") -#define nop() __asm__ __volatile__ ("nop") +extern void __inline__ +restore_flags(int flags) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + "mtc0\t%0,$12\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\treorder" + : /* no output */ + : "r" (flags) + : "memory"); +} -#define save_flags(x) \ +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) +#define sync_mem() \ __asm__ __volatile__( \ ".set\tnoreorder\n\t" \ - "mfc0\t%0,$12\n\t" \ + "sync\n\t" \ ".set\treorder" \ - : "=r" (x)) \ - -#define restore_flags(x) \ + : /* no output */ \ + : /* no input */ \ + : "memory") +#else +/* + * FIXME: Don't really know what to do here for the R[236]000's. + * Should probably bfc0 until write buffer is empty? - PMA + * Not shure if wb flushing is really required but sounds reasonable. + * The code below does this for R2000/R3000. - Ralf + */ +#define sync_mem() \ __asm__ __volatile__( \ ".set\tnoreorder\n\t" \ - "mtc0\t%0,$12\n\t" \ + "nop;nop;nop;nop;\n" \ + "1:\tbc0f\t1b\n\t" \ + "nop\n\t" \ ".set\treorder" \ - : /* no output */ \ - : "r" (x)) \ + : /* no output */ \ + : /* no input */ \ + : "memory") +#endif -#define sync_mem() \ -__asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - "sync\n\t" \ - ".set\treorder") \ +/* + * switch_to(n) should switch tasks to task nr n, first + * checking that n isn't the current task, in which case it does nothing. + */ +struct task_struct; +asmlinkage void resume(struct task_struct *tsk, int offset); + +/* + * FIXME: resume() assumes current == prev + */ +#define switch_to(prev,next) \ + resume(next, ((int)(&((struct task_struct *)0)->tss))); /* * The 8 and 16 bit variants have to disable interrupts temporarily. * Both are currently unused. */ -extern inline unsigned long xchg_u8(char * m, unsigned long val) +extern __inline__ unsigned long xchg_u8(volatile char * m, unsigned long val) { unsigned long flags, retval; save_flags(flags); - sti(); + cli(); retval = *m; *m = val; restore_flags(flags); @@ -114,12 +142,12 @@ extern inline unsigned long xchg_u8(char * m, unsigned long val) return retval; } -extern inline unsigned long xchg_u16(short * m, unsigned long val) +extern __inline__ unsigned long xchg_u16(volatile short * m, unsigned long val) { unsigned long flags, retval; save_flags(flags); - sti(); + cli(); retval = *m; *m = val; restore_flags(flags); @@ -131,8 +159,10 @@ extern inline unsigned long xchg_u16(short * m, unsigned long val) * For 32 and 64 bit operands we can take advantage of ll and sc. * FIXME: This doesn't work for R3000 machines. */ -extern inline unsigned long xchg_u32(int * m, unsigned long val) +extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) { +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) unsigned long dummy; __asm__ __volatile__( @@ -147,14 +177,23 @@ extern inline unsigned long xchg_u32(int * m, unsigned long val) ".set\treorder" : "=r" (val), "=r" (m), "=r" (dummy) : "1" (m), "2" (val)); +#else /* FIXME: Brain-dead approach, but then again, I AM hacking - PMA */ + unsigned long flags, retval; + save_flags(flags); + cli(); + retval = *m; + *m = val; + restore_flags(flags); + +#endif /* Processor-dependent optimization */ return val; } /* * Only used for 64 bit kernel. */ -extern inline unsigned long xchg_u64(long * m, unsigned long val) +extern __inline__ unsigned long xchg_u64(volatile long * m, unsigned long val) { unsigned long dummy; @@ -174,13 +213,33 @@ extern inline unsigned long xchg_u64(long * m, unsigned long val) return val; } -extern inline void * xchg_ptr(void * m, void * val) +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid xchg(). + * + * This only works if the compiler isn't horribly bad at optimizing. + * gcc-2.5.8 reportedly can't handle this, but I define that one to + * be dead anyway. + */ +extern void __xchg_called_with_bad_pointer(void); + +static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size) { -#if __mips == 3 - return (void *) xchg_u64(m, (unsigned long) val); -#else - return (void *) xchg_u32(m, (unsigned long) val); -#endif + switch (size) { + case 1: + return xchg_u8(ptr, x); + case 2: + return xchg_u16(ptr, x); + case 4: + return xchg_u32(ptr, x); + case 8: + return xchg_u64(ptr, x); + } + __xchg_called_with_bad_pointer(); + return x; } extern unsigned long IRQ_vectors[16]; @@ -192,4 +251,9 @@ extern unsigned long exception_handlers[32]; #define set_except_vector(n,addr) \ exception_handlers[n] = (unsigned long) (addr) +/* + * Reset the machine. + */ +extern void (*hard_reset_now)(void); + #endif /* __ASM_MIPS_SYSTEM_H */ diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h new file mode 100644 index 000000000..336915bce --- /dev/null +++ b/include/asm-mips/termbits.h @@ -0,0 +1,217 @@ +/* + * termbits stuff for Linux/MIPS. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_TERMBITS_H +#define __ASM_MIPS_TERMBITS_H + +#include <linux/posix_types.h> + +typedef unsigned char cc_t; +typedef unsigned long speed_t; +typedef unsigned long tcflag_t; + +/* + * The ABI says nothing about NCC but seems to use NCCS as + * replacement for it in struct termio + */ +#define NCCS 23 +struct termios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + /* + * Seems nonexistent in the ABI, but Linux assumes existence ... + */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +/* c_cc characters */ +#define VINTR 0 /* Interrupt character [ISIG]. */ +#define VQUIT 1 /* Quit character [ISIG]. */ +#define VERASE 2 /* Erase character [ICANON]. */ +#define VKILL 3 /* Kill-line character [ICANON]. */ +#define VEOF 4 /* End-of-file character [ICANON]. */ +#define VMIN VEOF /* Minimum number of bytes read at once [!ICANON]. */ +#define VEOL 5 /* End-of-line character [ICANON]. */ +#define VTIME VEOL /* Time-out value (tenths of a second) [!ICANON]. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define VEOL2 6 /* Second EOL character [ICANON]. */ +/* The next two are guesses ... */ +#define VSWTC 7 /* ??? */ +#endif +#define VSWTCH VSWTC +#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF]. */ +#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF]. */ +#define VSUSP 10 /* Suspend character [ISIG]. */ +#if 0 +/* + * VDSUSP is not supported + */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define VDSUSP 11 /* Delayed suspend character [ISIG]. */ +#endif +#endif +#if defined (__USE_BSD) || defined (__KERNEL__) +#define VREPRINT 12 /* Reprint-line character [ICANON]. */ +#endif +#if defined (__USE_BSD) || defined (__KERNEL__) +#define VDISCARD 13 /* Discard character [IEXTEN]. */ +#define VWERASE 14 /* Word-erase character [ICANON]. */ +#define VLNEXT 15 /* Literal-next character [IEXTEN]. */ +#endif +/* + * 17 - 19 are reserved + */ + +/* c_iflag bits */ +#define IGNBRK 0000001 /* Ignore break condition. */ +#define BRKINT 0000002 /* Signal interrupt on break. */ +#define IGNPAR 0000004 /* Ignore characters with parity errors. */ +#define PARMRK 0000010 /* Mark parity and framing errors. */ +#define INPCK 0000020 /* Enable input parity check. */ +#define ISTRIP 0000040 /* Strip 8th bit off characters. */ +#define INLCR 0000100 /* Map NL to CR on input. */ +#define IGNCR 0000200 /* Ignore CR. */ +#define ICRNL 0000400 /* Map CR to NL on input. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define IUCLC 0001000 /* Map upper case to lower case on input. */ +#endif +#define IXON 0002000 /* Enable start/stop output control. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define IXANY 0004000 /* Any character will restart after stop. */ +#endif +#define IXOFF 0010000 /* Enable start/stop input control. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define IMAXBEL 0020000 /* Ring bell when input queue is full. */ +#endif + +/* c_oflag bits */ +#define OPOST 0000001 /* Perform output processing. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define OLCUC 0000002 /* Map lower case to upper case on output. */ +#define ONLCR 0000004 /* Map NL to CR-NL on output. */ +#define OCRNL 0000010 +#define ONOCR 0000020 +#define ONLRET 0000040 +#define OFILL 0000100 +#define OFDEL 0000200 +#define NLDLY 0000400 +#define NL0 0000000 +#define NL1 0000400 +#define CRDLY 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 +#define TABDLY 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 +#define BSDLY 0020000 +#define BS0 0000000 +#define BS1 0020000 +#define VTDLY 0040000 +#define VT0 0000000 +#define VT1 0040000 +#define FFDLY 0100000 +#define FF0 0000000 +#define FF1 0100000 +/* +#define PAGEOUT ??? +#define WRAP ??? + */ +#endif + +/* c_cflag bit meaning */ +#define CBAUD 0010017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 +#define EXTA B19200 +#define EXTB B38400 +#define CSIZE 0000060 /* Number of bits per byte (mask). */ +#define CS5 0000000 /* 5 bits per byte. */ +#define CS6 0000020 /* 6 bits per byte. */ +#define CS7 0000040 /* 7 bits per byte. */ +#define CS8 0000060 /* 8 bits per byte. */ +#define CSTOPB 0000100 /* Two stop bits instead of one. */ +#define CREAD 0000200 /* Enable receiver. */ +#define PARENB 0000400 /* Parity enable. */ +#define PARODD 0001000 /* Odd parity instead of even. */ +#define HUPCL 0002000 /* Hang up on last close. */ +#define CLOCAL 0004000 /* Ignore modem status lines. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define CBAUDEX 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 +#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CRTSCTS 020000000000 /* flow control */ +#endif + +/* c_lflag bits */ +#define ISIG 0000001 /* Enable signals. */ +#define ICANON 0000002 /* Do erase and kill processing. */ +#define XCASE 0000004 +#define ECHO 0000010 /* Enable echo. */ +#define ECHOE 0000020 /* Visual erase for ERASE. */ +#define ECHOK 0000040 /* Echo NL after KILL. */ +#define ECHONL 0000100 /* Echo NL even if ECHO is off. */ +#define NOFLSH 0000200 /* Disable flush after interrupt. */ +#define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */ +#if defined (__USE_BSD) || defined (__KERNEL__) +#define ECHOCTL 0001000 /* Echo control characters as ^X. */ +#define ECHOPRT 0002000 /* Hardcopy visual erase. */ +#define ECHOKE 0004000 /* Visual erase for KILL. */ +#endif +#define FLUSHO 0020000 +#if defined (__USE_BSD) || defined (__KERNEL__) +#define PENDIN 0040000 /* Retype pending input (state). */ +#endif +#define TOSTOP 0100000 /* Send SIGTTOU for background output. */ +#define ITOSTOP TOSTOP + +/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ +#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ + +/* tcflow() and TCXONC use these */ +#define TCOOFF 0 /* Suspend output. */ +#define TCOON 1 /* Restart suspended output. */ +#define TCIOFF 2 /* Send a STOP character. */ +#define TCION 3 /* Send a START character. */ + +/* tcflush() and TCFLSH use these */ +#define TCIFLUSH 0 /* Discard data received but not yet read. */ +#define TCOFLUSH 1 /* Discard data written but not yet sent. */ +#define TCIOFLUSH 2 /* Discard all pending data. */ + +/* tcsetattr uses these */ +#define TCSANOW 0x540e /* Same as TCSETS; change immediately. */ +#define TCSADRAIN 0x540f /* Same as TCSETSW; change when pending output is written. */ +#define TCSAFLUSH 0x5410 /* Same as TCSETSF; flush pending input before changing. */ + +#endif /* __ASM_MIPS_TERMBITS_H */ diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h new file mode 100644 index 000000000..57fcbeef7 --- /dev/null +++ b/include/asm-mips/termios.h @@ -0,0 +1,127 @@ +/* + * ioctls for Linux/MIPS. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_TERMIOS_H + +#include <asm/termbits.h> +#include <asm/ioctls.h> + +struct sgttyb { + char sg_ispeed; + char sg_ospeed; + char sg_erase; + char sg_kill; + int sg_flags; /* SGI special - int, not short */ +}; + +struct tchars { + char t_intrc; + char t_quitc; + char t_startc; + char t_stopc; + char t_eofc; + char t_brkc; +}; + +struct ltchars { + char t_suspc; /* stop process signal */ + char t_dsuspc; /* delayed stop process signal */ + char t_rprntc; /* reprint line */ + char t_flushc; /* flush output (toggles) */ + char t_werasc; /* word erase */ + char t_lnextc; /* literal next character */ +}; + +/* TIOCGSIZE, TIOCSSIZE not defined yet. Only needed for SunOS source + compatibility anyway ... */ + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define NCC 8 +struct termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + char c_line; /* line discipline */ + unsigned char c_cc[NCCS]; /* control characters */ +}; + +#ifdef __KERNEL__ +/* + * intr=^C quit=^\ erase=del kill=^U + * eof=^D eol=time=\0 eol2=\0 swtc=\0 + * start=^Q stop=^S susp=^Z vdsusp= + * reprint=^R discard=^U werase=^W lnext=^V + */ +#define INIT_C_CC "\003\034\177\025\004\0\0\0\021\023\032\0\022\017\027\026" +#endif + +/* modem lines */ +#define TIOCM_LE 0x001 /* line enable */ +#define TIOCM_DTR 0x002 /* data terminal ready */ +#define TIOCM_RTS 0x004 /* request to send */ +#define TIOCM_ST 0x010 /* secondary transmit */ +#define TIOCM_SR 0x020 /* secondary receive */ +#define TIOCM_CTS 0x040 /* clear to send */ +#define TIOCM_CAR 0x100 /* carrier detect */ +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RNG 0x200 /* ring */ +#define TIOCM_RI TIOCM_RNG +#define TIOCM_DSR 0x400 /* data set ready */ + +/* line disciplines */ +#define N_TTY 0 +#define N_SLIP 1 +#define N_MOUSE 2 +#define N_PPP 3 +#define N_STRIP 4 +#define N_AX25 5 + +#ifdef __KERNEL__ + +#include <linux/string.h> + +/* + * Translate a "termio" structure into a "termios". Ugh. + */ +extern inline void trans_from_termio(struct termio * termio, + struct termios * termios) +{ +#define SET_LOW_BITS(x,y) ((x) = (0xffff0000 & (x)) | (y)) + SET_LOW_BITS(termios->c_iflag, termio->c_iflag); + SET_LOW_BITS(termios->c_oflag, termio->c_oflag); + SET_LOW_BITS(termios->c_cflag, termio->c_cflag); + SET_LOW_BITS(termios->c_lflag, termio->c_lflag); +#undef SET_LOW_BITS + memcpy(termios->c_cc, termio->c_cc, NCC); +} + +/* + * Translate a "termios" structure into a "termio". Ugh. + */ +extern inline void trans_to_termio(struct termios * termios, + struct termio * termio) +{ + termio->c_iflag = termios->c_iflag; + termio->c_oflag = termios->c_oflag; + termio->c_cflag = termios->c_cflag; + termio->c_lflag = termios->c_lflag; + termio->c_line = termios->c_line; + memcpy(termio->c_cc, termios->c_cc, NCC); +} + +#endif /* defined(__KERNEL__) */ + +#endif /* __ASM_MIPS_TERMIOS_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index da0310a02..4d27f768b 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -5,36 +5,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Waldorf GMBH - * written by Ralf Baechle + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ #ifndef __ASM_MIPS_TYPES_H #define __ASM_MIPS_TYPES_H -#ifndef _SIZE_T -#define _SIZE_T -typedef __SIZE_TYPE__ size_t; -#endif - -#ifndef _SSIZE_T -#define _SSIZE_T -typedef __SSIZE_TYPE__ ssize_t; -#endif - -#ifndef _PTRDIFF_T -#define _PTRDIFF_T -typedef __PTRDIFF_TYPE__ ptrdiff_t; -#endif - -#ifndef _TIME_T -#define _TIME_T -typedef long time_t; -#endif - -#ifndef _CLOCK_T -#define _CLOCK_T -typedef long clock_t; -#endif +typedef unsigned long umode_t; /* * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the @@ -94,33 +70,4 @@ typedef unsigned long u64; #endif /* __KERNEL__ */ -typedef __s32 pid_t; -typedef __s32 uid_t; -typedef __s32 gid_t; -typedef __u32 dev_t; -typedef __u32 ino_t; -typedef __u32 mode_t; -typedef __u32 umode_t; -typedef __u32 nlink_t; -typedef long daddr_t; -typedef long off_t; - -#if 0 -/* - * These definitions double the definitions from <gnu/types.h>. - */ -#undef __FDELT -#define __FDELT(d) ((d) / __NFDBITS) -#undef __FDMASK -#define __FDMASK(d) (1 << ((d) % __NFDBITS)) -#undef __FD_SET -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) -#undef __FD_CLR -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) -#undef __FD_ISSET -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif - #endif /* __ASM_MIPS_TYPES_H */ diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h new file mode 100644 index 000000000..48a205077 --- /dev/null +++ b/include/asm-mips/uaccess.h @@ -0,0 +1,314 @@ +/* + * include/asm-mips/uaccess.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_UACCESS_H +#define __ASM_MIPS_UACCESS_H + +#include <linux/errno.h> +#include <linux/sched.h> +#include <asm/asm.h> + +#define STR(x) __STR(x) +#define __STR(x) #x + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + * + * For historical reasons, these macros are grossly misnamed. + */ +#define KERNEL_DS 0 +#define USER_DS 1 + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +#define get_fs() (current->tss.segment) +#define set_fs(x) (current->tss.segment=(x)) + +static inline unsigned long get_ds(void) +{ + return KERNEL_DS; +} + +/* + * Is a address valid? This does a straighforward calculation rather + * than tests. + * + * Address valid if: + * - "addr" doesn't have any high-bits set + * - AND "size" doesn't have any high-bits set + * - AND "addr+size" doesn't have any high-bits set + * - OR we are in kernel mode. + */ +#define __access_ok(addr,size,mask) \ + (((__signed__ long)((mask)&(addr | size | (addr+size)))) >= 0) +#define __access_mask (-(long)get_fs()) + +#define access_ok(type,addr,size) \ +__access_ok(((unsigned long)(addr)),(size),__access_mask) + +extern inline int verify_area(int type, const void * addr, unsigned long size) +{ + return access_ok(type,addr,size) ? 0 : -EFAULT; +} + +/* + * Uh, these should become the main single-value transfer routines ... + * They automatically use the right size if we just have the right + * pointer type ... + * + * As MIPS uses the same address space for kernel and user data, we + * can just do these as direct assignments. + * + * Careful to not + * (a) re-use the arguments for side effects (sizeof is ok) + * (b) require any knowledge of processes at this stage + */ +#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr)),__access_mask) +#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr)),__access_mask) + +/* + * The "__xxx" versions do not do address space checking, useful when + * doing multiple accesses to the same area (the user has to do the + * checks by hand with "access_ok()") + */ +#define __put_user(x,ptr) __put_user_nocheck((x),(ptr),sizeof(*(ptr))) +#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr))) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct *)(x)) + +#define copy_to_user(to,from,n) __copy_tofrom_user((to),(from),(n),__cu_to) +#define copy_from_user(to,from,n) __copy_tofrom_user((to),(from),(n),__cu_from) + +extern size_t __copy_user(void *__to, const void *__from, size_t __n); + +#define __copy_tofrom_user(to,from,n,v) ({ \ + void * __cu_to; \ + const void * __cu_from; \ + long __cu_len; \ + \ + __cu_to = (to); \ + __cu_from = (from); \ + __cu_len = (n); \ + if (__access_ok(((unsigned long)(v)),__cu_len,__access_mask)) \ + __cu_len = __copy_user(__cu_to, __cu_from, __cu_len); \ + __cu_len; \ +}) + +#define __get_user_nocheck(x,ptr,size) ({ \ +long __gu_err; \ +long __gu_val; \ +long __gu_addr; \ +__asm__("":"=r" (__gu_val)); \ +__gu_addr = (long) (ptr); \ +__gu_err = 0; \ +switch (size) { \ +case 1: __get_user_nocheck_asm("lb"); break; \ +case 2: __get_user_nocheck_asm("lh"); break; \ +case 4: __get_user_nocheck_asm("lw"); break; \ +case 8: __get_user_nocheck_asm("ld"); break; \ +default: __get_user_unknown(); break; \ +} x = (__typeof__(*(ptr))) __gu_val; __gu_err; }) + +#define __get_user_nocheck_asm(insn) \ +({ \ +__asm__ __volatile__( \ + "1:\t" insn "\t%1,%3\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\t.set\tnoat\n\t" \ + "la\t$1,2b\n\t" \ + "li\t%0,%4\n\t" \ + "jr\t$1\n\t" \ + ".set\tat\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b,3b\n\t" \ + ".text" \ + :"=r" (__gu_err), "=r" (__gu_val) \ + :"0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT) \ + :"$1"); }) + +#define __get_user_check(x,ptr,size,mask) ({ \ +long __gu_err; \ +long __gu_val; \ +long __gu_addr; \ +__asm__("":"=r" (__gu_val)); \ +__gu_addr = (long) (ptr); \ +__gu_err = -EFAULT; \ +if (__access_ok(__gu_addr,size,mask)) { \ +switch (size) { \ +case 1: __get_user_check_asm("lb"); break; \ +case 2: __get_user_check_asm("lh"); break; \ +case 4: __get_user_check_asm("lw"); break; \ +case 8: __get_user_check_asm("ld"); break; \ +default: __get_user_unknown(); break; \ +} } x = (__typeof__(*(ptr))) __gu_val; __gu_err; }) + +#define __get_user_check_asm(insn) \ +({ \ +__asm__ __volatile__( \ + "1:\t" insn "\t%1,%2\n\t" \ + "move\t%0,$0\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\t.set\tnoat\n\t" \ + "la\t$1,2b\n\t" \ + "jr\t$1\n\t" \ + ".set\tat\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b,3b\n\t" \ + ".text" \ + :"=r" (__gu_err), "=r" (__gu_val) \ + :"o" (__m(__gu_addr)) \ + :"$1"); }) + +extern void __get_user_unknown(void); + +#define __put_user_nocheck(x,ptr,size) ({ \ +long __pu_err; \ +__typeof__(*(ptr)) __pu_val; \ +long __pu_addr; \ +__pu_val = (x); \ +__pu_addr = (long) (ptr); \ +__pu_err = 0; \ +switch (size) { \ +case 1: __put_user_nocheck_asm("sb"); break; \ +case 2: __put_user_nocheck_asm("sh"); break; \ +case 4: __put_user_nocheck_asm("sw"); break; \ +case 8: __put_user_nocheck_asm("sd"); break; \ +default: __put_user_unknown(); break; \ +} __pu_err; }) + +#define __put_user_nocheck_asm(insn) \ +({ \ +__asm__ __volatile__( \ + "1:\t" insn "\t%1,%2\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\t.set\tnoat\n\t" \ + "la\t$1,2b\n\t" \ + "li\t%0,%3\n\t" \ + "jr\t$1\n\t" \ + ".set\tat\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b,3b\n\t" \ + ".text" \ + :"=r" (__pu_err) \ + :"r" (__pu_val), "o" (__m(__pu_addr)), "i" (-EFAULT) \ + :"$1"); }) + +#define __put_user_check(x,ptr,size,mask) ({ \ +long __pu_err; \ +__typeof__(*(ptr)) __pu_val; \ +long __pu_addr; \ +__pu_val = (x); \ +__pu_addr = (long) (ptr); \ +__pu_err = -EFAULT; \ +if (__access_ok(__pu_addr,size,mask)) { \ +switch (size) { \ +case 1: __put_user_check_asm("sb"); break; \ +case 2: __put_user_check_asm("sh"); break; \ +case 4: __put_user_check_asm("sw"); break; \ +case 8: __put_user_check_asm("sd"); break; \ +default: __put_user_unknown(); break; \ +} } __pu_err; }) + +#define __put_user_check_asm(insn) \ +({ \ +__asm__ __volatile__( \ + "1:\t" insn "\t%1,%2\n\t" \ + "move\t%0,$0\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\t.set\tnoat\n\t" \ + "la\t$1,2b\n\t" \ + "jr\t$1\n\t" \ + ".set\tat\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b,3b\n\t" \ + ".text" \ + :"=r" (__pu_err) \ + :"r" (__pu_val), "o" (__m(__pu_addr)) \ + :"$1"); }) + +extern void __put_user_unknown(void); + +#define __clear_user(addr,size) \ +({ \ + void *__cu_end; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + "1:\tsb\t$0,(%0)\n\t" \ + "bne\t%0,%1,1b\n\t" \ + "addiu\t%0,1\n" \ + "2:\t.set\treorder\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\t.set\tnoat\n\t" \ + "la\t$1,2b\n\t" \ + "jr\t$1\n\t" \ + ".set\tat\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b,3b\n\t" \ + ".text" \ + :"=r" (addr), "=r" (__cu_end) \ + :"0" (addr), "1" (addr + size - 1), "i" (-EFAULT) \ + :"$1","memory"); \ + size = __cu_end - (addr) - 1; \ +}) + +#define clear_user(addr,n) ({ \ +void * __cl_addr = (addr); \ +unsigned long __cl_size = (n); \ +if (__cl_size && __access_ok(VERIFY_WRITE, ((unsigned long)(__cl_addr)), __cl_size)) \ +__clear_user(__cl_addr, __cl_size); \ +__cl_size; }) + +/* + * Returns: -EFAULT if exception before terminator, N if the entire + * buffer filled, else strlen. + */ +extern long __strncpy_from_user(char *__to, const char *__from, long __to_len); + +#define strncpy_from_user(dest,src,count) ({ \ + const void * __sc_src = (src); \ + long __sc_res = -EFAULT; \ + if (access_ok(VERIFY_READ, __sc_src, 0)) { \ + __sc_res = __strncpy_from_user(dest, __sc_src, count); \ +} __sc_res; }) + +/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ +extern long __strlen_user(const char *); + +extern inline long strlen_user(const char *str) +{ + long len = __strlen_user(str); + if (!access_ok(VERIFY_READ, str, len)) + len = 0; + return len; +} + +struct exception_table_entry +{ + unsigned long insn; + unsigned long nextinsn; +}; + +/* Returns 0 if exception not found and fixup.unit otherwise. */ +extern unsigned long search_exception_table(unsigned long addr); + +/* Returns the new pc */ +#define fixup_exception(map_reg, fixup_unit, pc) \ +({ \ + fixup_unit; \ +}) + +#endif /* __ASM_MIPS_UACCESS_H */ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h new file mode 100644 index 000000000..95eb47f55 --- /dev/null +++ b/include/asm-mips/unaligned.h @@ -0,0 +1,176 @@ +/* + * Inline functions to do unaligned accesses. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_UNALIGNED_H +#define __ASM_MIPS_UNALIGNED_H + +#if 0 +/* + * The following macros are the portable and efficient versions of + * get_unaligned()/put_unaligned(). They work but due to some lackings in the + * MIPS machine description of GCC generate only good code only for accessing + * word sized data. We only use get_unaligned() for accessing unaligned ints + * and then GCC makes full score anyway ... + */ +#define get_unaligned(ptr) \ + ({ \ + struct __unal { \ + __typeof__(*(ptr)) __x __attribute__((packed)); \ + }; \ + \ + ((struct __unal *)(ptr))->__x; \ + }) + +#define put_unaligned(ptr,val) \ + ({ \ + struct __unal { \ + __typeof__(*(ptr)) __x __attribute__((packed)); \ + }; \ + \ + ((struct __unal *)(ptr))->__x = (val); \ + }) +#else + +/* + * The main single-value unaligned transfer routines. + */ +#define get_unaligned(ptr) \ + ((__typeof__(*(ptr)))__get_unaligned((ptr), sizeof(*(ptr)))) +#define put_unaligned(x,ptr) \ + __put_unaligned((unsigned long)(x), (ptr), sizeof(*(ptr))) + +/* + * This is a silly but good way to make sure that + * the get/put functions are indeed always optimized, + * and that we use the correct sizes. + */ +extern void bad_unaligned_access_length(void); + +/* + * Load unaligned doubleword. + */ +extern __inline__ unsigned long __uld(const unsigned long long * __addr) +{ + unsigned long long __res; + + __asm__("uld\t%0,(%1)" + :"=&r" (__res) + :"r" (__addr)); + + return __res; +} + +/* + * Load unaligned word. + */ +extern __inline__ unsigned long __ulw(const unsigned int * __addr) +{ + unsigned long __res; + + __asm__("ulw\t%0,(%1)" + :"=&r" (__res) + :"r" (__addr)); + + return __res; +} + +/* + * Load unaligned halfword. + */ +extern __inline__ unsigned long __ulh(const unsigned short * __addr) +{ + unsigned long __res; + + __asm__("ulh\t%0,(%1)" + :"=&r" (__res) + :"r" (__addr)); + + return __res; +} + +/* + * Store unaligned doubleword. + */ +extern __inline__ void __usd(unsigned long __val, unsigned long long * __addr) +{ + __asm__ __volatile__( + "usd\t%0,(%1)" + : /* No results */ + :"r" (__val), + "r" (__addr)); +} + +/* + * Store unaligned word. + */ +extern __inline__ void __usw(unsigned long __val, unsigned int * __addr) +{ + __asm__ __volatile__( + "usw\t%0,(%1)" + : /* No results */ + :"r" (__val), + "r" (__addr)); +} + +/* + * Store unaligned halfword. + */ +extern __inline__ void __ush(unsigned long __val, unsigned short * __addr) +{ + __asm__ __volatile__( + "ush\t%0,(%1)" + : /* No results */ + :"r" (__val), + "r" (__addr)); +} + +extern inline unsigned long __get_unaligned(const void *ptr, size_t size) +{ + unsigned long val; + switch (size) { + case 1: + val = *(const unsigned char *)ptr; + break; + case 2: + val = __ulh((const unsigned short *)ptr); + break; + case 4: + val = __ulw((const unsigned int *)ptr); + break; + case 8: + val = __uld((const unsigned long long *)ptr); + break; + default: + bad_unaligned_access_length(); + } + return val; +} + +extern inline void __put_unaligned(unsigned long val, void *ptr, size_t size) +{ + switch (size) { + case 1: + *(unsigned char *)ptr = (val); + break; + case 2: + __ush(val, (unsigned short *)ptr); + break; + case 4: + __usw(val, (unsigned int *)ptr); + break; + case 8: + __usd(val, (unsigned long long *)ptr); + break; + default: + bad_unaligned_access_length(); + } +} +#endif + +#endif /* __ASM_MIPS_UNALIGNED_H */ diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 94878e595..8db0d3cee 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -1,32 +1,1222 @@ +/* + * This file contains the system call numbers. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996 by Ralf Baechle + * + * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto + * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A + */ #ifndef __ASM_MIPS_UNISTD_H #define __ASM_MIPS_UNISTD_H +/* + * The syscalls 0 - 3999 are reserved for a down to the root syscall + * compatibility with RISC/os and IRIX. None of these syscalls has yet been + * implemented. We'll see how to deal with the various "real" BSD variants + * like Ultrix, NetBSD ... + */ + +/* + * SVR4 syscalls are in the range from 1 to 999 + */ +#define __NR_SVR4 0 +#define __NR_SVR4_syscall (__NR_SVR4 + 0) +#define __NR_SVR4_exit (__NR_SVR4 + 1) +#define __NR_SVR4_fork (__NR_SVR4 + 2) +#define __NR_SVR4_read (__NR_SVR4 + 3) +#define __NR_SVR4_write (__NR_SVR4 + 4) +#define __NR_SVR4_open (__NR_SVR4 + 5) +#define __NR_SVR4_close (__NR_SVR4 + 6) +#define __NR_SVR4_wait (__NR_SVR4 + 7) +#define __NR_SVR4_creat (__NR_SVR4 + 8) +#define __NR_SVR4_link (__NR_SVR4 + 9) +#define __NR_SVR4_unlink (__NR_SVR4 + 10) +#define __NR_SVR4_exec (__NR_SVR4 + 11) +#define __NR_SVR4_chdir (__NR_SVR4 + 12) +#define __NR_SVR4_gtime (__NR_SVR4 + 13) +#define __NR_SVR4_mknod (__NR_SVR4 + 14) +#define __NR_SVR4_chmod (__NR_SVR4 + 15) +#define __NR_SVR4_chown (__NR_SVR4 + 16) +#define __NR_SVR4_sbreak (__NR_SVR4 + 17) +#define __NR_SVR4_stat (__NR_SVR4 + 18) +#define __NR_SVR4_lseek (__NR_SVR4 + 19) +#define __NR_SVR4_getpid (__NR_SVR4 + 20) +#define __NR_SVR4_mount (__NR_SVR4 + 21) +#define __NR_SVR4_umount (__NR_SVR4 + 22) +#define __NR_SVR4_setuid (__NR_SVR4 + 23) +#define __NR_SVR4_getuid (__NR_SVR4 + 24) +#define __NR_SVR4_stime (__NR_SVR4 + 25) +#define __NR_SVR4_ptrace (__NR_SVR4 + 26) +#define __NR_SVR4_alarm (__NR_SVR4 + 27) +#define __NR_SVR4_fstat (__NR_SVR4 + 28) +#define __NR_SVR4_pause (__NR_SVR4 + 29) +#define __NR_SVR4_utime (__NR_SVR4 + 30) +#define __NR_SVR4_stty (__NR_SVR4 + 31) +#define __NR_SVR4_gtty (__NR_SVR4 + 32) +#define __NR_SVR4_access (__NR_SVR4 + 33) +#define __NR_SVR4_nice (__NR_SVR4 + 34) +#define __NR_SVR4_statfs (__NR_SVR4 + 35) +#define __NR_SVR4_sync (__NR_SVR4 + 36) +#define __NR_SVR4_kill (__NR_SVR4 + 37) +#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) +#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) +#define __NR_SVR4_cxenix (__NR_SVR4 + 40) +#define __NR_SVR4_dup (__NR_SVR4 + 41) +#define __NR_SVR4_pipe (__NR_SVR4 + 42) +#define __NR_SVR4_times (__NR_SVR4 + 43) +#define __NR_SVR4_profil (__NR_SVR4 + 44) +#define __NR_SVR4_plock (__NR_SVR4 + 45) +#define __NR_SVR4_setgid (__NR_SVR4 + 46) +#define __NR_SVR4_getgid (__NR_SVR4 + 47) +#define __NR_SVR4_sig (__NR_SVR4 + 48) +#define __NR_SVR4_msgsys (__NR_SVR4 + 49) +#define __NR_SVR4_sysmips (__NR_SVR4 + 50) +#define __NR_SVR4_sysacct (__NR_SVR4 + 51) +#define __NR_SVR4_shmsys (__NR_SVR4 + 52) +#define __NR_SVR4_semsys (__NR_SVR4 + 53) +#define __NR_SVR4_ioctl (__NR_SVR4 + 54) +#define __NR_SVR4_uadmin (__NR_SVR4 + 55) +#define __NR_SVR4_exch (__NR_SVR4 + 56) +#define __NR_SVR4_utssys (__NR_SVR4 + 57) +#define __NR_SVR4_fsync (__NR_SVR4 + 58) +#define __NR_SVR4_exece (__NR_SVR4 + 59) +#define __NR_SVR4_umask (__NR_SVR4 + 60) +#define __NR_SVR4_chroot (__NR_SVR4 + 61) +#define __NR_SVR4_fcntl (__NR_SVR4 + 62) +#define __NR_SVR4_ulimit (__NR_SVR4 + 63) +#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) +#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) +#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) +#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) +#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) +#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) +#define __NR_SVR4_advfs (__NR_SVR4 + 70) +#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) +#define __NR_SVR4_unused1 (__NR_SVR4 + 72) +#define __NR_SVR4_unused2 (__NR_SVR4 + 73) +#define __NR_SVR4_rfstart (__NR_SVR4 + 74) +#define __NR_SVR4_unused3 (__NR_SVR4 + 75) +#define __NR_SVR4_rdebug (__NR_SVR4 + 76) +#define __NR_SVR4_rfstop (__NR_SVR4 + 77) +#define __NR_SVR4_rfsys (__NR_SVR4 + 78) +#define __NR_SVR4_rmdir (__NR_SVR4 + 79) +#define __NR_SVR4_mkdir (__NR_SVR4 + 80) +#define __NR_SVR4_getdents (__NR_SVR4 + 81) +#define __NR_SVR4_libattach (__NR_SVR4 + 82) +#define __NR_SVR4_libdetach (__NR_SVR4 + 83) +#define __NR_SVR4_sysfs (__NR_SVR4 + 84) +#define __NR_SVR4_getmsg (__NR_SVR4 + 85) +#define __NR_SVR4_putmsg (__NR_SVR4 + 86) +#define __NR_SVR4_poll (__NR_SVR4 + 87) +#define __NR_SVR4_lstat (__NR_SVR4 + 88) +#define __NR_SVR4_symlink (__NR_SVR4 + 89) +#define __NR_SVR4_readlink (__NR_SVR4 + 90) +#define __NR_SVR4_setgroups (__NR_SVR4 + 91) +#define __NR_SVR4_getgroups (__NR_SVR4 + 92) +#define __NR_SVR4_fchmod (__NR_SVR4 + 93) +#define __NR_SVR4_fchown (__NR_SVR4 + 94) +#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) +#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) +#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) +#define __NR_SVR4_sigaction (__NR_SVR4 + 98) +#define __NR_SVR4_sigpending (__NR_SVR4 + 99) +#define __NR_SVR4_setcontext (__NR_SVR4 + 100) +#define __NR_SVR4_evsys (__NR_SVR4 + 101) +#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) +#define __NR_SVR4_statvfs (__NR_SVR4 + 103) +#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) +#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) +#define __NR_SVR4_nfssys (__NR_SVR4 + 106) +#define __NR_SVR4_waitid (__NR_SVR4 + 107) +#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) +#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) +#define __NR_SVR4_acancel (__NR_SVR4 + 110) +#define __NR_SVR4_async (__NR_SVR4 + 111) +#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) +#define __NR_SVR4_pathconf (__NR_SVR4 + 113) +#define __NR_SVR4_mincore (__NR_SVR4 + 114) +#define __NR_SVR4_mmap (__NR_SVR4 + 115) +#define __NR_SVR4_mprotect (__NR_SVR4 + 116) +#define __NR_SVR4_munmap (__NR_SVR4 + 117) +#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) +#define __NR_SVR4_vfork (__NR_SVR4 + 119) +#define __NR_SVR4_fchdir (__NR_SVR4 + 120) +#define __NR_SVR4_readv (__NR_SVR4 + 121) +#define __NR_SVR4_writev (__NR_SVR4 + 122) +#define __NR_SVR4_xstat (__NR_SVR4 + 123) +#define __NR_SVR4_lxstat (__NR_SVR4 + 124) +#define __NR_SVR4_fxstat (__NR_SVR4 + 125) +#define __NR_SVR4_xmknod (__NR_SVR4 + 126) +#define __NR_SVR4_clocal (__NR_SVR4 + 127) +#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) +#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) +#define __NR_SVR4_lchown (__NR_SVR4 + 130) +#define __NR_SVR4_memcntl (__NR_SVR4 + 131) +#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) +#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) +#define __NR_SVR4_rename (__NR_SVR4 + 134) +#define __NR_SVR4_nuname (__NR_SVR4 + 135) +#define __NR_SVR4_setegid (__NR_SVR4 + 136) +#define __NR_SVR4_sysconf (__NR_SVR4 + 137) +#define __NR_SVR4_adjtime (__NR_SVR4 + 138) +#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) +#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) +#define __NR_SVR4_seteuid (__NR_SVR4 + 141) +#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) +#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) +#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) +#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) +#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) +#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) +#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) +#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) +#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) +#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) +#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) +#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) +#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) +#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) +#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) +#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) +#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) +#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) +#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) +#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) +#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) +#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) +#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) +#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) +#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) +#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) +#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) +#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) +#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) +#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) +#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) +#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) +#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) +#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) +#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) +#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) +#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) +#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) +#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) +#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) +#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) +#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) +#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) +#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) +#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) +#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) +#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) +#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) +#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) +#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) +#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) +#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) +#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) +#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) +#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) +#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) +#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) +#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) +#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) +#define __NR_SVR4_aread (__NR_SVR4 + 201) +#define __NR_SVR4_awrite (__NR_SVR4 + 202) +#define __NR_SVR4_listio (__NR_SVR4 + 203) +#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) +#define __NR_SVR4_astatus (__NR_SVR4 + 205) +#define __NR_SVR4_await (__NR_SVR4 + 206) +#define __NR_SVR4_areadv (__NR_SVR4 + 207) +#define __NR_SVR4_awritev (__NR_SVR4 + 208) +#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) +#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) +#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) +#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) +#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) +#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) +#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) +#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) +#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) +#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) +#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) +#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) +#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) +#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) +#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) +#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) +#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) +#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) +#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) +#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) +#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) +#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) +#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) +#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) +#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) +#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) +#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) +#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) +#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) +#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) +#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) +#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) + +/* + * SYS V syscalls are in the range from 1000 to 1999 + */ +#define __NR_SYSV 1000 +#define __NR_SYSV_syscall (__NR_SYSV + 0) +#define __NR_SYSV_exit (__NR_SYSV + 1) +#define __NR_SYSV_fork (__NR_SYSV + 2) +#define __NR_SYSV_read (__NR_SYSV + 3) +#define __NR_SYSV_write (__NR_SYSV + 4) +#define __NR_SYSV_open (__NR_SYSV + 5) +#define __NR_SYSV_close (__NR_SYSV + 6) +#define __NR_SYSV_wait (__NR_SYSV + 7) +#define __NR_SYSV_creat (__NR_SYSV + 8) +#define __NR_SYSV_link (__NR_SYSV + 9) +#define __NR_SYSV_unlink (__NR_SYSV + 10) +#define __NR_SYSV_execv (__NR_SYSV + 11) +#define __NR_SYSV_chdir (__NR_SYSV + 12) +#define __NR_SYSV_time (__NR_SYSV + 13) +#define __NR_SYSV_mknod (__NR_SYSV + 14) +#define __NR_SYSV_chmod (__NR_SYSV + 15) +#define __NR_SYSV_chown (__NR_SYSV + 16) +#define __NR_SYSV_brk (__NR_SYSV + 17) +#define __NR_SYSV_stat (__NR_SYSV + 18) +#define __NR_SYSV_lseek (__NR_SYSV + 19) +#define __NR_SYSV_getpid (__NR_SYSV + 20) +#define __NR_SYSV_mount (__NR_SYSV + 21) +#define __NR_SYSV_umount (__NR_SYSV + 22) +#define __NR_SYSV_setuid (__NR_SYSV + 23) +#define __NR_SYSV_getuid (__NR_SYSV + 24) +#define __NR_SYSV_stime (__NR_SYSV + 25) +#define __NR_SYSV_ptrace (__NR_SYSV + 26) +#define __NR_SYSV_alarm (__NR_SYSV + 27) +#define __NR_SYSV_fstat (__NR_SYSV + 28) +#define __NR_SYSV_pause (__NR_SYSV + 29) +#define __NR_SYSV_utime (__NR_SYSV + 30) +#define __NR_SYSV_stty (__NR_SYSV + 31) +#define __NR_SYSV_gtty (__NR_SYSV + 32) +#define __NR_SYSV_access (__NR_SYSV + 33) +#define __NR_SYSV_nice (__NR_SYSV + 34) +#define __NR_SYSV_statfs (__NR_SYSV + 35) +#define __NR_SYSV_sync (__NR_SYSV + 36) +#define __NR_SYSV_kill (__NR_SYSV + 37) +#define __NR_SYSV_fstatfs (__NR_SYSV + 38) +#define __NR_SYSV_setpgrp (__NR_SYSV + 39) +#define __NR_SYSV_syssgi (__NR_SYSV + 40) +#define __NR_SYSV_dup (__NR_SYSV + 41) +#define __NR_SYSV_pipe (__NR_SYSV + 42) +#define __NR_SYSV_times (__NR_SYSV + 43) +#define __NR_SYSV_profil (__NR_SYSV + 44) +#define __NR_SYSV_plock (__NR_SYSV + 45) +#define __NR_SYSV_setgid (__NR_SYSV + 46) +#define __NR_SYSV_getgid (__NR_SYSV + 47) +#define __NR_SYSV_sig (__NR_SYSV + 48) +#define __NR_SYSV_msgsys (__NR_SYSV + 49) +#define __NR_SYSV_sysmips (__NR_SYSV + 50) +#define __NR_SYSV_acct (__NR_SYSV + 51) +#define __NR_SYSV_shmsys (__NR_SYSV + 52) +#define __NR_SYSV_semsys (__NR_SYSV + 53) +#define __NR_SYSV_ioctl (__NR_SYSV + 54) +#define __NR_SYSV_uadmin (__NR_SYSV + 55) +#define __NR_SYSV_sysmp (__NR_SYSV + 56) +#define __NR_SYSV_utssys (__NR_SYSV + 57) +#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) +#define __NR_SYSV_execve (__NR_SYSV + 59) +#define __NR_SYSV_umask (__NR_SYSV + 60) +#define __NR_SYSV_chroot (__NR_SYSV + 61) +#define __NR_SYSV_fcntl (__NR_SYSV + 62) +#define __NR_SYSV_ulimit (__NR_SYSV + 63) +#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) +#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) +#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) +#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) +#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) +#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) +#define __NR_SYSV_advfs (__NR_SYSV + 70) +#define __NR_SYSV_unadvfs (__NR_SYSV + 71) +#define __NR_SYSV_rmount (__NR_SYSV + 72) +#define __NR_SYSV_rumount (__NR_SYSV + 73) +#define __NR_SYSV_rfstart (__NR_SYSV + 74) +#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) +#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) +#define __NR_SYSV_nanosleep (__NR_SYSV + 77) +#define __NR_SYSV_lseek64 (__NR_SYSV + 78) +#define __NR_SYSV_rmdir (__NR_SYSV + 79) +#define __NR_SYSV_mkdir (__NR_SYSV + 80) +#define __NR_SYSV_getdents (__NR_SYSV + 81) +#define __NR_SYSV_sginap (__NR_SYSV + 82) +#define __NR_SYSV_sgikopt (__NR_SYSV + 83) +#define __NR_SYSV_sysfs (__NR_SYSV + 84) +#define __NR_SYSV_getmsg (__NR_SYSV + 85) +#define __NR_SYSV_putmsg (__NR_SYSV + 86) +#define __NR_SYSV_poll (__NR_SYSV + 87) +#define __NR_SYSV_sigreturn (__NR_SYSV + 88) +#define __NR_SYSV_accept (__NR_SYSV + 89) +#define __NR_SYSV_bind (__NR_SYSV + 90) +#define __NR_SYSV_connect (__NR_SYSV + 91) +#define __NR_SYSV_gethostid (__NR_SYSV + 92) +#define __NR_SYSV_getpeername (__NR_SYSV + 93) +#define __NR_SYSV_getsockname (__NR_SYSV + 94) +#define __NR_SYSV_getsockopt (__NR_SYSV + 95) +#define __NR_SYSV_listen (__NR_SYSV + 96) +#define __NR_SYSV_recv (__NR_SYSV + 97) +#define __NR_SYSV_recvfrom (__NR_SYSV + 98) +#define __NR_SYSV_recvmsg (__NR_SYSV + 99) +#define __NR_SYSV_select (__NR_SYSV + 100) +#define __NR_SYSV_send (__NR_SYSV + 101) +#define __NR_SYSV_sendmsg (__NR_SYSV + 102) +#define __NR_SYSV_sendto (__NR_SYSV + 103) +#define __NR_SYSV_sethostid (__NR_SYSV + 104) +#define __NR_SYSV_setsockopt (__NR_SYSV + 105) +#define __NR_SYSV_shutdown (__NR_SYSV + 106) +#define __NR_SYSV_socket (__NR_SYSV + 107) +#define __NR_SYSV_gethostname (__NR_SYSV + 108) +#define __NR_SYSV_sethostname (__NR_SYSV + 109) +#define __NR_SYSV_getdomainname (__NR_SYSV + 110) +#define __NR_SYSV_setdomainname (__NR_SYSV + 111) +#define __NR_SYSV_truncate (__NR_SYSV + 112) +#define __NR_SYSV_ftruncate (__NR_SYSV + 113) +#define __NR_SYSV_rename (__NR_SYSV + 114) +#define __NR_SYSV_symlink (__NR_SYSV + 115) +#define __NR_SYSV_readlink (__NR_SYSV + 116) +#define __NR_SYSV_lstat (__NR_SYSV + 117) +#define __NR_SYSV_nfsmount (__NR_SYSV + 118) +#define __NR_SYSV_nfssvc (__NR_SYSV + 119) +#define __NR_SYSV_getfh (__NR_SYSV + 120) +#define __NR_SYSV_async_daemon (__NR_SYSV + 121) +#define __NR_SYSV_exportfs (__NR_SYSV + 122) +#define __NR_SYSV_setregid (__NR_SYSV + 123) +#define __NR_SYSV_setreuid (__NR_SYSV + 124) +#define __NR_SYSV_getitimer (__NR_SYSV + 125) +#define __NR_SYSV_setitimer (__NR_SYSV + 126) +#define __NR_SYSV_adjtime (__NR_SYSV + 127) +#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) +#define __NR_SYSV_sproc (__NR_SYSV + 129) +#define __NR_SYSV_prctl (__NR_SYSV + 130) +#define __NR_SYSV_procblk (__NR_SYSV + 131) +#define __NR_SYSV_sprocsp (__NR_SYSV + 132) +#define __NR_SYSV_sgigsc (__NR_SYSV + 133) +#define __NR_SYSV_mmap (__NR_SYSV + 134) +#define __NR_SYSV_munmap (__NR_SYSV + 135) +#define __NR_SYSV_mprotect (__NR_SYSV + 136) +#define __NR_SYSV_msync (__NR_SYSV + 137) +#define __NR_SYSV_madvise (__NR_SYSV + 138) +#define __NR_SYSV_pagelock (__NR_SYSV + 139) +#define __NR_SYSV_getpagesize (__NR_SYSV + 140) +#define __NR_SYSV_quotactl (__NR_SYSV + 141) +#define __NR_SYSV_libdetach (__NR_SYSV + 142) +#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) +#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) +#define __NR_SYSV_vhangup (__NR_SYSV + 145) +#define __NR_SYSV_fsync (__NR_SYSV + 146) +#define __NR_SYSV_fchdir (__NR_SYSV + 147) +#define __NR_SYSV_getrlimit (__NR_SYSV + 148) +#define __NR_SYSV_setrlimit (__NR_SYSV + 149) +#define __NR_SYSV_cacheflush (__NR_SYSV + 150) +#define __NR_SYSV_cachectl (__NR_SYSV + 151) +#define __NR_SYSV_fchown (__NR_SYSV + 152) +#define __NR_SYSV_fchmod (__NR_SYSV + 153) +#define __NR_SYSV_wait3 (__NR_SYSV + 154) +#define __NR_SYSV_socketpair (__NR_SYSV + 155) +#define __NR_SYSV_sysinfo (__NR_SYSV + 156) +#define __NR_SYSV_nuname (__NR_SYSV + 157) +#define __NR_SYSV_xstat (__NR_SYSV + 158) +#define __NR_SYSV_lxstat (__NR_SYSV + 159) +#define __NR_SYSV_fxstat (__NR_SYSV + 160) +#define __NR_SYSV_xmknod (__NR_SYSV + 161) +#define __NR_SYSV_ksigaction (__NR_SYSV + 162) +#define __NR_SYSV_sigpending (__NR_SYSV + 163) +#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) +#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) +#define __NR_SYSV_sigpoll (__NR_SYSV + 166) +#define __NR_SYSV_swapctl (__NR_SYSV + 167) +#define __NR_SYSV_getcontext (__NR_SYSV + 168) +#define __NR_SYSV_setcontext (__NR_SYSV + 169) +#define __NR_SYSV_waitsys (__NR_SYSV + 170) +#define __NR_SYSV_sigstack (__NR_SYSV + 171) +#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) +#define __NR_SYSV_sigsendset (__NR_SYSV + 173) +#define __NR_SYSV_statvfs (__NR_SYSV + 174) +#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) +#define __NR_SYSV_getpmsg (__NR_SYSV + 176) +#define __NR_SYSV_putpmsg (__NR_SYSV + 177) +#define __NR_SYSV_lchown (__NR_SYSV + 178) +#define __NR_SYSV_priocntl (__NR_SYSV + 179) +#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) +#define __NR_SYSV_readv (__NR_SYSV + 181) +#define __NR_SYSV_writev (__NR_SYSV + 182) +#define __NR_SYSV_truncate64 (__NR_SYSV + 183) +#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) +#define __NR_SYSV_mmap64 (__NR_SYSV + 185) +#define __NR_SYSV_dmi (__NR_SYSV + 186) +#define __NR_SYSV_pread (__NR_SYSV + 187) +#define __NR_SYSV_pwrite (__NR_SYSV + 188) + +/* + * BSD 4.3 syscalls are in the range from 2000 to 2999 + */ +#define __NR_BSD43 2000 +#define __NR_BSD43_syscall (__NR_BSD43 + 0) +#define __NR_BSD43_exit (__NR_BSD43 + 1) +#define __NR_BSD43_fork (__NR_BSD43 + 2) +#define __NR_BSD43_read (__NR_BSD43 + 3) +#define __NR_BSD43_write (__NR_BSD43 + 4) +#define __NR_BSD43_open (__NR_BSD43 + 5) +#define __NR_BSD43_close (__NR_BSD43 + 6) +#define __NR_BSD43_wait (__NR_BSD43 + 7) +#define __NR_BSD43_creat (__NR_BSD43 + 8) +#define __NR_BSD43_link (__NR_BSD43 + 9) +#define __NR_BSD43_unlink (__NR_BSD43 + 10) +#define __NR_BSD43_exec (__NR_BSD43 + 11) +#define __NR_BSD43_chdir (__NR_BSD43 + 12) +#define __NR_BSD43_time (__NR_BSD43 + 13) +#define __NR_BSD43_mknod (__NR_BSD43 + 14) +#define __NR_BSD43_chmod (__NR_BSD43 + 15) +#define __NR_BSD43_chown (__NR_BSD43 + 16) +#define __NR_BSD43_sbreak (__NR_BSD43 + 17) +#define __NR_BSD43_oldstat (__NR_BSD43 + 18) +#define __NR_BSD43_lseek (__NR_BSD43 + 19) +#define __NR_BSD43_getpid (__NR_BSD43 + 20) +#define __NR_BSD43_oldmount (__NR_BSD43 + 21) +#define __NR_BSD43_umount (__NR_BSD43 + 22) +#define __NR_BSD43_setuid (__NR_BSD43 + 23) +#define __NR_BSD43_getuid (__NR_BSD43 + 24) +#define __NR_BSD43_stime (__NR_BSD43 + 25) +#define __NR_BSD43_ptrace (__NR_BSD43 + 26) +#define __NR_BSD43_alarm (__NR_BSD43 + 27) +#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) +#define __NR_BSD43_pause (__NR_BSD43 + 29) +#define __NR_BSD43_utime (__NR_BSD43 + 30) +#define __NR_BSD43_stty (__NR_BSD43 + 31) +#define __NR_BSD43_gtty (__NR_BSD43 + 32) +#define __NR_BSD43_access (__NR_BSD43 + 33) +#define __NR_BSD43_nice (__NR_BSD43 + 34) +#define __NR_BSD43_ftime (__NR_BSD43 + 35) +#define __NR_BSD43_sync (__NR_BSD43 + 36) +#define __NR_BSD43_kill (__NR_BSD43 + 37) +#define __NR_BSD43_stat (__NR_BSD43 + 38) +#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) +#define __NR_BSD43_lstat (__NR_BSD43 + 40) +#define __NR_BSD43_dup (__NR_BSD43 + 41) +#define __NR_BSD43_pipe (__NR_BSD43 + 42) +#define __NR_BSD43_times (__NR_BSD43 + 43) +#define __NR_BSD43_profil (__NR_BSD43 + 44) +#define __NR_BSD43_msgsys (__NR_BSD43 + 45) +#define __NR_BSD43_setgid (__NR_BSD43 + 46) +#define __NR_BSD43_getgid (__NR_BSD43 + 47) +#define __NR_BSD43_ssig (__NR_BSD43 + 48) +#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) +#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) +#define __NR_BSD43_sysacct (__NR_BSD43 + 51) +#define __NR_BSD43_phys (__NR_BSD43 + 52) +#define __NR_BSD43_lock (__NR_BSD43 + 53) +#define __NR_BSD43_ioctl (__NR_BSD43 + 54) +#define __NR_BSD43_reboot (__NR_BSD43 + 55) +#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) +#define __NR_BSD43_symlink (__NR_BSD43 + 57) +#define __NR_BSD43_readlink (__NR_BSD43 + 58) +#define __NR_BSD43_execve (__NR_BSD43 + 59) +#define __NR_BSD43_umask (__NR_BSD43 + 60) +#define __NR_BSD43_chroot (__NR_BSD43 + 61) +#define __NR_BSD43_fstat (__NR_BSD43 + 62) +#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) +#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) +#define __NR_BSD43_mremap (__NR_BSD43 + 65) +#define __NR_BSD43_vfork (__NR_BSD43 + 66) +#define __NR_BSD43_vread (__NR_BSD43 + 67) +#define __NR_BSD43_vwrite (__NR_BSD43 + 68) +#define __NR_BSD43_sbrk (__NR_BSD43 + 69) +#define __NR_BSD43_sstk (__NR_BSD43 + 70) +#define __NR_BSD43_mmap (__NR_BSD43 + 71) +#define __NR_BSD43_vadvise (__NR_BSD43 + 72) +#define __NR_BSD43_munmap (__NR_BSD43 + 73) +#define __NR_BSD43_mprotect (__NR_BSD43 + 74) +#define __NR_BSD43_madvise (__NR_BSD43 + 75) +#define __NR_BSD43_vhangup (__NR_BSD43 + 76) +#define __NR_BSD43_vlimit (__NR_BSD43 + 77) +#define __NR_BSD43_mincore (__NR_BSD43 + 78) +#define __NR_BSD43_getgroups (__NR_BSD43 + 79) +#define __NR_BSD43_setgroups (__NR_BSD43 + 80) +#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) +#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) +#define __NR_BSD43_setitimer (__NR_BSD43 + 83) +#define __NR_BSD43_wait3 (__NR_BSD43 + 84) +#define __NR_BSD43_swapon (__NR_BSD43 + 85) +#define __NR_BSD43_getitimer (__NR_BSD43 + 86) +#define __NR_BSD43_gethostname (__NR_BSD43 + 87) +#define __NR_BSD43_sethostname (__NR_BSD43 + 88) +#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) +#define __NR_BSD43_dup2 (__NR_BSD43 + 90) +#define __NR_BSD43_getdopt (__NR_BSD43 + 91) +#define __NR_BSD43_fcntl (__NR_BSD43 + 92) +#define __NR_BSD43_select (__NR_BSD43 + 93) +#define __NR_BSD43_setdopt (__NR_BSD43 + 94) +#define __NR_BSD43_fsync (__NR_BSD43 + 95) +#define __NR_BSD43_setpriority (__NR_BSD43 + 96) +#define __NR_BSD43_socket (__NR_BSD43 + 97) +#define __NR_BSD43_connect (__NR_BSD43 + 98) +#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) +#define __NR_BSD43_getpriority (__NR_BSD43 + 100) +#define __NR_BSD43_send (__NR_BSD43 + 101) +#define __NR_BSD43_recv (__NR_BSD43 + 102) +#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) +#define __NR_BSD43_bind (__NR_BSD43 + 104) +#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) +#define __NR_BSD43_listen (__NR_BSD43 + 106) +#define __NR_BSD43_vtimes (__NR_BSD43 + 107) +#define __NR_BSD43_sigvec (__NR_BSD43 + 108) +#define __NR_BSD43_sigblock (__NR_BSD43 + 109) +#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) +#define __NR_BSD43_sigpause (__NR_BSD43 + 111) +#define __NR_BSD43_sigstack (__NR_BSD43 + 112) +#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) +#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) +#define __NR_BSD43_vtrace (__NR_BSD43 + 115) +#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) +#define __NR_BSD43_getrusage (__NR_BSD43 + 117) +#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) +#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) +#define __NR_BSD43_readv (__NR_BSD43 + 120) +#define __NR_BSD43_writev (__NR_BSD43 + 121) +#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) +#define __NR_BSD43_fchown (__NR_BSD43 + 123) +#define __NR_BSD43_fchmod (__NR_BSD43 + 124) +#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) +#define __NR_BSD43_setreuid (__NR_BSD43 + 126) +#define __NR_BSD43_setregid (__NR_BSD43 + 127) +#define __NR_BSD43_rename (__NR_BSD43 + 128) +#define __NR_BSD43_truncate (__NR_BSD43 + 129) +#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) +#define __NR_BSD43_flock (__NR_BSD43 + 131) +#define __NR_BSD43_semsys (__NR_BSD43 + 132) +#define __NR_BSD43_sendto (__NR_BSD43 + 133) +#define __NR_BSD43_shutdown (__NR_BSD43 + 134) +#define __NR_BSD43_socketpair (__NR_BSD43 + 135) +#define __NR_BSD43_mkdir (__NR_BSD43 + 136) +#define __NR_BSD43_rmdir (__NR_BSD43 + 137) +#define __NR_BSD43_utimes (__NR_BSD43 + 138) +#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) +#define __NR_BSD43_adjtime (__NR_BSD43 + 140) +#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) +#define __NR_BSD43_gethostid (__NR_BSD43 + 142) +#define __NR_BSD43_sethostid (__NR_BSD43 + 143) +#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) +#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) +#define __NR_BSD43_killpg (__NR_BSD43 + 146) +#define __NR_BSD43_shmsys (__NR_BSD43 + 147) +#define __NR_BSD43_quota (__NR_BSD43 + 148) +#define __NR_BSD43_qquota (__NR_BSD43 + 149) +#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) +#define __NR_BSD43_sysmips (__NR_BSD43 + 151) +#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) +#define __NR_BSD43_cachectl (__NR_BSD43 + 153) +#define __NR_BSD43_debug (__NR_BSD43 + 154) +#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) +#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) +#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) +#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) +#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) +#define __NR_BSD43_statfs (__NR_BSD43 + 160) +#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) +#define __NR_BSD43_unmount (__NR_BSD43 + 162) +#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) +#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) +#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) +#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) +#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) +#define __NR_BSD43_quotactl (__NR_BSD43 + 168) +#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) +#define __NR_BSD43_smount (__NR_BSD43 + 170) +#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) +#define __NR_BSD43_exportfs (__NR_BSD43 + 172) +#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) +#define __NR_BSD43_libattach (__NR_BSD43 + 174) +#define __NR_BSD43_libdetach (__NR_BSD43 + 175) +#define __NR_BSD43_accept (__NR_BSD43 + 176) +#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) +#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) +#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) +#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) +#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) +#define __NR_BSD43_getpeername (__NR_BSD43 + 182) +#define __NR_BSD43_getsockname (__NR_BSD43 + 183) +#define __NR_BSD43_aread (__NR_BSD43 + 184) +#define __NR_BSD43_awrite (__NR_BSD43 + 185) +#define __NR_BSD43_listio (__NR_BSD43 + 186) +#define __NR_BSD43_acancel (__NR_BSD43 + 187) +#define __NR_BSD43_astatus (__NR_BSD43 + 188) +#define __NR_BSD43_await (__NR_BSD43 + 189) +#define __NR_BSD43_areadv (__NR_BSD43 + 190) +#define __NR_BSD43_awritev (__NR_BSD43 + 191) + +/* + * POSIX syscalls are in the range from 3000 to 3999 + */ +#define __NR_POSIX 3000 +#define __NR_POSIX_syscall (__NR_POSIX + 0) +#define __NR_POSIX_exit (__NR_POSIX + 1) +#define __NR_POSIX_fork (__NR_POSIX + 2) +#define __NR_POSIX_read (__NR_POSIX + 3) +#define __NR_POSIX_write (__NR_POSIX + 4) +#define __NR_POSIX_open (__NR_POSIX + 5) +#define __NR_POSIX_close (__NR_POSIX + 6) +#define __NR_POSIX_wait (__NR_POSIX + 7) +#define __NR_POSIX_creat (__NR_POSIX + 8) +#define __NR_POSIX_link (__NR_POSIX + 9) +#define __NR_POSIX_unlink (__NR_POSIX + 10) +#define __NR_POSIX_exec (__NR_POSIX + 11) +#define __NR_POSIX_chdir (__NR_POSIX + 12) +#define __NR_POSIX_gtime (__NR_POSIX + 13) +#define __NR_POSIX_mknod (__NR_POSIX + 14) +#define __NR_POSIX_chmod (__NR_POSIX + 15) +#define __NR_POSIX_chown (__NR_POSIX + 16) +#define __NR_POSIX_sbreak (__NR_POSIX + 17) +#define __NR_POSIX_stat (__NR_POSIX + 18) +#define __NR_POSIX_lseek (__NR_POSIX + 19) +#define __NR_POSIX_getpid (__NR_POSIX + 20) +#define __NR_POSIX_mount (__NR_POSIX + 21) +#define __NR_POSIX_umount (__NR_POSIX + 22) +#define __NR_POSIX_setuid (__NR_POSIX + 23) +#define __NR_POSIX_getuid (__NR_POSIX + 24) +#define __NR_POSIX_stime (__NR_POSIX + 25) +#define __NR_POSIX_ptrace (__NR_POSIX + 26) +#define __NR_POSIX_alarm (__NR_POSIX + 27) +#define __NR_POSIX_fstat (__NR_POSIX + 28) +#define __NR_POSIX_pause (__NR_POSIX + 29) +#define __NR_POSIX_utime (__NR_POSIX + 30) +#define __NR_POSIX_stty (__NR_POSIX + 31) +#define __NR_POSIX_gtty (__NR_POSIX + 32) +#define __NR_POSIX_access (__NR_POSIX + 33) +#define __NR_POSIX_nice (__NR_POSIX + 34) +#define __NR_POSIX_statfs (__NR_POSIX + 35) +#define __NR_POSIX_sync (__NR_POSIX + 36) +#define __NR_POSIX_kill (__NR_POSIX + 37) +#define __NR_POSIX_fstatfs (__NR_POSIX + 38) +#define __NR_POSIX_getpgrp (__NR_POSIX + 39) +#define __NR_POSIX_syssgi (__NR_POSIX + 40) +#define __NR_POSIX_dup (__NR_POSIX + 41) +#define __NR_POSIX_pipe (__NR_POSIX + 42) +#define __NR_POSIX_times (__NR_POSIX + 43) +#define __NR_POSIX_profil (__NR_POSIX + 44) +#define __NR_POSIX_lock (__NR_POSIX + 45) +#define __NR_POSIX_setgid (__NR_POSIX + 46) +#define __NR_POSIX_getgid (__NR_POSIX + 47) +#define __NR_POSIX_sig (__NR_POSIX + 48) +#define __NR_POSIX_msgsys (__NR_POSIX + 49) +#define __NR_POSIX_sysmips (__NR_POSIX + 50) +#define __NR_POSIX_sysacct (__NR_POSIX + 51) +#define __NR_POSIX_shmsys (__NR_POSIX + 52) +#define __NR_POSIX_semsys (__NR_POSIX + 53) +#define __NR_POSIX_ioctl (__NR_POSIX + 54) +#define __NR_POSIX_uadmin (__NR_POSIX + 55) +#define __NR_POSIX_exch (__NR_POSIX + 56) +#define __NR_POSIX_utssys (__NR_POSIX + 57) +#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) +#define __NR_POSIX_exece (__NR_POSIX + 59) +#define __NR_POSIX_umask (__NR_POSIX + 60) +#define __NR_POSIX_chroot (__NR_POSIX + 61) +#define __NR_POSIX_fcntl (__NR_POSIX + 62) +#define __NR_POSIX_ulimit (__NR_POSIX + 63) +#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) +#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) +#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) +#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) +#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) +#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) +#define __NR_POSIX_advfs (__NR_POSIX + 70) +#define __NR_POSIX_unadvfs (__NR_POSIX + 71) +#define __NR_POSIX_rmount (__NR_POSIX + 72) +#define __NR_POSIX_rumount (__NR_POSIX + 73) +#define __NR_POSIX_rfstart (__NR_POSIX + 74) +#define __NR_POSIX_reserved1 (__NR_POSIX + 75) +#define __NR_POSIX_rdebug (__NR_POSIX + 76) +#define __NR_POSIX_rfstop (__NR_POSIX + 77) +#define __NR_POSIX_rfsys (__NR_POSIX + 78) +#define __NR_POSIX_rmdir (__NR_POSIX + 79) +#define __NR_POSIX_mkdir (__NR_POSIX + 80) +#define __NR_POSIX_getdents (__NR_POSIX + 81) +#define __NR_POSIX_sginap (__NR_POSIX + 82) +#define __NR_POSIX_sgikopt (__NR_POSIX + 83) +#define __NR_POSIX_sysfs (__NR_POSIX + 84) +#define __NR_POSIX_getmsg (__NR_POSIX + 85) +#define __NR_POSIX_putmsg (__NR_POSIX + 86) +#define __NR_POSIX_poll (__NR_POSIX + 87) +#define __NR_POSIX_sigreturn (__NR_POSIX + 88) +#define __NR_POSIX_accept (__NR_POSIX + 89) +#define __NR_POSIX_bind (__NR_POSIX + 90) +#define __NR_POSIX_connect (__NR_POSIX + 91) +#define __NR_POSIX_gethostid (__NR_POSIX + 92) +#define __NR_POSIX_getpeername (__NR_POSIX + 93) +#define __NR_POSIX_getsockname (__NR_POSIX + 94) +#define __NR_POSIX_getsockopt (__NR_POSIX + 95) +#define __NR_POSIX_listen (__NR_POSIX + 96) +#define __NR_POSIX_recv (__NR_POSIX + 97) +#define __NR_POSIX_recvfrom (__NR_POSIX + 98) +#define __NR_POSIX_recvmsg (__NR_POSIX + 99) +#define __NR_POSIX_select (__NR_POSIX + 100) +#define __NR_POSIX_send (__NR_POSIX + 101) +#define __NR_POSIX_sendmsg (__NR_POSIX + 102) +#define __NR_POSIX_sendto (__NR_POSIX + 103) +#define __NR_POSIX_sethostid (__NR_POSIX + 104) +#define __NR_POSIX_setsockopt (__NR_POSIX + 105) +#define __NR_POSIX_shutdown (__NR_POSIX + 106) +#define __NR_POSIX_socket (__NR_POSIX + 107) +#define __NR_POSIX_gethostname (__NR_POSIX + 108) +#define __NR_POSIX_sethostname (__NR_POSIX + 109) +#define __NR_POSIX_getdomainname (__NR_POSIX + 110) +#define __NR_POSIX_setdomainname (__NR_POSIX + 111) +#define __NR_POSIX_truncate (__NR_POSIX + 112) +#define __NR_POSIX_ftruncate (__NR_POSIX + 113) +#define __NR_POSIX_rename (__NR_POSIX + 114) +#define __NR_POSIX_symlink (__NR_POSIX + 115) +#define __NR_POSIX_readlink (__NR_POSIX + 116) +#define __NR_POSIX_lstat (__NR_POSIX + 117) +#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) +#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) +#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) +#define __NR_POSIX_async_daemon (__NR_POSIX + 121) +#define __NR_POSIX_exportfs (__NR_POSIX + 122) +#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) +#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) +#define __NR_POSIX_getitimer (__NR_POSIX + 125) +#define __NR_POSIX_setitimer (__NR_POSIX + 126) +#define __NR_POSIX_adjtime (__NR_POSIX + 127) +#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) +#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) +#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) +#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) +#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) +#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) +#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) +#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) +#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) +#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) +#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) +#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) +#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) +#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) +#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) +#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) +#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) +#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) +#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) +#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) +#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) +#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) +#define __NR_POSIX_cacheflush (__NR_POSIX + 150) +#define __NR_POSIX_cachectl (__NR_POSIX + 151) +#define __NR_POSIX_fchown (__NR_POSIX + 152) +#define __NR_POSIX_fchmod (__NR_POSIX + 153) +#define __NR_POSIX_wait3 (__NR_POSIX + 154) +#define __NR_POSIX_mmap (__NR_POSIX + 155) +#define __NR_POSIX_munmap (__NR_POSIX + 156) +#define __NR_POSIX_madvise (__NR_POSIX + 157) +#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) +#define __NR_POSIX_setreuid (__NR_POSIX + 159) +#define __NR_POSIX_setregid (__NR_POSIX + 160) +#define __NR_POSIX_setpgid (__NR_POSIX + 161) +#define __NR_POSIX_getgroups (__NR_POSIX + 162) +#define __NR_POSIX_setgroups (__NR_POSIX + 163) +#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) +#define __NR_POSIX_getrusage (__NR_POSIX + 165) +#define __NR_POSIX_getrlimit (__NR_POSIX + 166) +#define __NR_POSIX_setrlimit (__NR_POSIX + 167) +#define __NR_POSIX_waitpid (__NR_POSIX + 168) +#define __NR_POSIX_dup2 (__NR_POSIX + 169) +#define __NR_POSIX_reserved2 (__NR_POSIX + 170) +#define __NR_POSIX_reserved3 (__NR_POSIX + 171) +#define __NR_POSIX_reserved4 (__NR_POSIX + 172) +#define __NR_POSIX_reserved5 (__NR_POSIX + 173) +#define __NR_POSIX_reserved6 (__NR_POSIX + 174) +#define __NR_POSIX_reserved7 (__NR_POSIX + 175) +#define __NR_POSIX_reserved8 (__NR_POSIX + 176) +#define __NR_POSIX_reserved9 (__NR_POSIX + 177) +#define __NR_POSIX_reserved10 (__NR_POSIX + 178) +#define __NR_POSIX_reserved11 (__NR_POSIX + 179) +#define __NR_POSIX_reserved12 (__NR_POSIX + 180) +#define __NR_POSIX_reserved13 (__NR_POSIX + 181) +#define __NR_POSIX_reserved14 (__NR_POSIX + 182) +#define __NR_POSIX_reserved15 (__NR_POSIX + 183) +#define __NR_POSIX_reserved16 (__NR_POSIX + 184) +#define __NR_POSIX_reserved17 (__NR_POSIX + 185) +#define __NR_POSIX_reserved18 (__NR_POSIX + 186) +#define __NR_POSIX_reserved19 (__NR_POSIX + 187) +#define __NR_POSIX_reserved20 (__NR_POSIX + 188) +#define __NR_POSIX_reserved21 (__NR_POSIX + 189) +#define __NR_POSIX_reserved22 (__NR_POSIX + 190) +#define __NR_POSIX_reserved23 (__NR_POSIX + 191) +#define __NR_POSIX_reserved24 (__NR_POSIX + 192) +#define __NR_POSIX_reserved25 (__NR_POSIX + 193) +#define __NR_POSIX_reserved26 (__NR_POSIX + 194) +#define __NR_POSIX_reserved27 (__NR_POSIX + 195) +#define __NR_POSIX_reserved28 (__NR_POSIX + 196) +#define __NR_POSIX_reserved29 (__NR_POSIX + 197) +#define __NR_POSIX_reserved30 (__NR_POSIX + 198) +#define __NR_POSIX_reserved31 (__NR_POSIX + 199) +#define __NR_POSIX_reserved32 (__NR_POSIX + 200) +#define __NR_POSIX_reserved33 (__NR_POSIX + 201) +#define __NR_POSIX_reserved34 (__NR_POSIX + 202) +#define __NR_POSIX_reserved35 (__NR_POSIX + 203) +#define __NR_POSIX_reserved36 (__NR_POSIX + 204) +#define __NR_POSIX_reserved37 (__NR_POSIX + 205) +#define __NR_POSIX_reserved38 (__NR_POSIX + 206) +#define __NR_POSIX_reserved39 (__NR_POSIX + 207) +#define __NR_POSIX_reserved40 (__NR_POSIX + 208) +#define __NR_POSIX_reserved41 (__NR_POSIX + 209) +#define __NR_POSIX_reserved42 (__NR_POSIX + 210) +#define __NR_POSIX_reserved43 (__NR_POSIX + 211) +#define __NR_POSIX_reserved44 (__NR_POSIX + 212) +#define __NR_POSIX_reserved45 (__NR_POSIX + 213) +#define __NR_POSIX_reserved46 (__NR_POSIX + 214) +#define __NR_POSIX_reserved47 (__NR_POSIX + 215) +#define __NR_POSIX_reserved48 (__NR_POSIX + 216) +#define __NR_POSIX_reserved49 (__NR_POSIX + 217) +#define __NR_POSIX_reserved50 (__NR_POSIX + 218) +#define __NR_POSIX_reserved51 (__NR_POSIX + 219) +#define __NR_POSIX_reserved52 (__NR_POSIX + 220) +#define __NR_POSIX_reserved53 (__NR_POSIX + 221) +#define __NR_POSIX_reserved54 (__NR_POSIX + 222) +#define __NR_POSIX_reserved55 (__NR_POSIX + 223) +#define __NR_POSIX_reserved56 (__NR_POSIX + 224) +#define __NR_POSIX_reserved57 (__NR_POSIX + 225) +#define __NR_POSIX_reserved58 (__NR_POSIX + 226) +#define __NR_POSIX_reserved59 (__NR_POSIX + 227) +#define __NR_POSIX_reserved60 (__NR_POSIX + 228) +#define __NR_POSIX_reserved61 (__NR_POSIX + 229) +#define __NR_POSIX_reserved62 (__NR_POSIX + 230) +#define __NR_POSIX_reserved63 (__NR_POSIX + 231) +#define __NR_POSIX_reserved64 (__NR_POSIX + 232) +#define __NR_POSIX_reserved65 (__NR_POSIX + 233) +#define __NR_POSIX_reserved66 (__NR_POSIX + 234) +#define __NR_POSIX_reserved67 (__NR_POSIX + 235) +#define __NR_POSIX_reserved68 (__NR_POSIX + 236) +#define __NR_POSIX_reserved69 (__NR_POSIX + 237) +#define __NR_POSIX_reserved70 (__NR_POSIX + 238) +#define __NR_POSIX_reserved71 (__NR_POSIX + 239) +#define __NR_POSIX_reserved72 (__NR_POSIX + 240) +#define __NR_POSIX_reserved73 (__NR_POSIX + 241) +#define __NR_POSIX_reserved74 (__NR_POSIX + 242) +#define __NR_POSIX_reserved75 (__NR_POSIX + 243) +#define __NR_POSIX_reserved76 (__NR_POSIX + 244) +#define __NR_POSIX_reserved77 (__NR_POSIX + 245) +#define __NR_POSIX_reserved78 (__NR_POSIX + 246) +#define __NR_POSIX_reserved79 (__NR_POSIX + 247) +#define __NR_POSIX_reserved80 (__NR_POSIX + 248) +#define __NR_POSIX_reserved81 (__NR_POSIX + 249) +#define __NR_POSIX_reserved82 (__NR_POSIX + 250) +#define __NR_POSIX_reserved83 (__NR_POSIX + 251) +#define __NR_POSIX_reserved84 (__NR_POSIX + 252) +#define __NR_POSIX_reserved85 (__NR_POSIX + 253) +#define __NR_POSIX_reserved86 (__NR_POSIX + 254) +#define __NR_POSIX_reserved87 (__NR_POSIX + 255) +#define __NR_POSIX_reserved88 (__NR_POSIX + 256) +#define __NR_POSIX_reserved89 (__NR_POSIX + 257) +#define __NR_POSIX_reserved90 (__NR_POSIX + 258) +#define __NR_POSIX_reserved91 (__NR_POSIX + 259) +#define __NR_POSIX_netboot (__NR_POSIX + 260) +#define __NR_POSIX_netunboot (__NR_POSIX + 261) +#define __NR_POSIX_rdump (__NR_POSIX + 262) +#define __NR_POSIX_setsid (__NR_POSIX + 263) +#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) +#define __NR_POSIX_sigpending (__NR_POSIX + 265) +#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) +#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) +#define __NR_POSIX_sigaction (__NR_POSIX + 268) +#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) +#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) +#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) +#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) +#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) +#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) +#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) +#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) +#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) +#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) +#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) +#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) +#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) +#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) +#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) +#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) +#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) +#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) +#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) +#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) +#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) +#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) +#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) +#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) +#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) +#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) +#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) +#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) +#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) +#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) +#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) +#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) +#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) +#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) +#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) +#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) +#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) +#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) +#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) +#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) +#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) +#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) +#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) +#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) +#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) +#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) +#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) +#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) +#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) +#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) +#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) + +/* + * Linux syscalls are in the range from 4000 to 4999 + * Hopefully these syscall numbers are unused ... If not everyone using + * statically linked binaries is pretty upsh*t. You've been warned. + */ +#define __NR_Linux 4000 +#define __NR_syscall (__NR_Linux + 0) +#define __NR_exit (__NR_Linux + 1) +#define __NR_fork (__NR_Linux + 2) +#define __NR_read (__NR_Linux + 3) +#define __NR_write (__NR_Linux + 4) +#define __NR_open (__NR_Linux + 5) +#define __NR_close (__NR_Linux + 6) +#define __NR_waitpid (__NR_Linux + 7) +#define __NR_creat (__NR_Linux + 8) +#define __NR_link (__NR_Linux + 9) +#define __NR_unlink (__NR_Linux + 10) +#define __NR_execve (__NR_Linux + 11) +#define __NR_chdir (__NR_Linux + 12) +#define __NR_time (__NR_Linux + 13) +#define __NR_mknod (__NR_Linux + 14) +#define __NR_chmod (__NR_Linux + 15) +#define __NR_chown (__NR_Linux + 16) +#define __NR_break (__NR_Linux + 17) +#define __NR_oldstat (__NR_Linux + 18) +#define __NR_lseek (__NR_Linux + 19) +#define __NR_getpid (__NR_Linux + 20) +#define __NR_mount (__NR_Linux + 21) +#define __NR_umount (__NR_Linux + 22) +#define __NR_setuid (__NR_Linux + 23) +#define __NR_getuid (__NR_Linux + 24) +#define __NR_stime (__NR_Linux + 25) +#define __NR_ptrace (__NR_Linux + 26) +#define __NR_alarm (__NR_Linux + 27) +#define __NR_oldfstat (__NR_Linux + 28) +#define __NR_pause (__NR_Linux + 29) +#define __NR_utime (__NR_Linux + 30) +#define __NR_stty (__NR_Linux + 31) +#define __NR_gtty (__NR_Linux + 32) +#define __NR_access (__NR_Linux + 33) +#define __NR_nice (__NR_Linux + 34) +#define __NR_ftime (__NR_Linux + 35) +#define __NR_sync (__NR_Linux + 36) +#define __NR_kill (__NR_Linux + 37) +#define __NR_rename (__NR_Linux + 38) +#define __NR_mkdir (__NR_Linux + 39) +#define __NR_rmdir (__NR_Linux + 40) +#define __NR_dup (__NR_Linux + 41) +#define __NR_pipe (__NR_Linux + 42) +#define __NR_times (__NR_Linux + 43) +#define __NR_prof (__NR_Linux + 44) +#define __NR_brk (__NR_Linux + 45) +#define __NR_setgid (__NR_Linux + 46) +#define __NR_getgid (__NR_Linux + 47) +#define __NR_signal (__NR_Linux + 48) +#define __NR_geteuid (__NR_Linux + 49) +#define __NR_getegid (__NR_Linux + 50) +#define __NR_acct (__NR_Linux + 51) +#define __NR_phys (__NR_Linux + 52) +#define __NR_lock (__NR_Linux + 53) +#define __NR_ioctl (__NR_Linux + 54) +#define __NR_fcntl (__NR_Linux + 55) +#define __NR_mpx (__NR_Linux + 56) +#define __NR_setpgid (__NR_Linux + 57) +#define __NR_ulimit (__NR_Linux + 58) +#define __NR_oldolduname (__NR_Linux + 59) +#define __NR_umask (__NR_Linux + 60) +#define __NR_chroot (__NR_Linux + 61) +#define __NR_ustat (__NR_Linux + 62) +#define __NR_dup2 (__NR_Linux + 63) +#define __NR_getppid (__NR_Linux + 64) +#define __NR_getpgrp (__NR_Linux + 65) +#define __NR_setsid (__NR_Linux + 66) +#define __NR_sigaction (__NR_Linux + 67) +#define __NR_sgetmask (__NR_Linux + 68) +#define __NR_ssetmask (__NR_Linux + 69) +#define __NR_setreuid (__NR_Linux + 70) +#define __NR_setregid (__NR_Linux + 71) +#define __NR_sigsuspend (__NR_Linux + 72) +#define __NR_sigpending (__NR_Linux + 73) +#define __NR_sethostname (__NR_Linux + 74) +#define __NR_setrlimit (__NR_Linux + 75) +#define __NR_getrlimit (__NR_Linux + 76) +#define __NR_getrusage (__NR_Linux + 77) +#define __NR_gettimeofday (__NR_Linux + 78) +#define __NR_settimeofday (__NR_Linux + 79) +#define __NR_getgroups (__NR_Linux + 80) +#define __NR_setgroups (__NR_Linux + 81) +#define __NR_reserved82 (__NR_Linux + 82) +#define __NR_symlink (__NR_Linux + 83) +#define __NR_oldlstat (__NR_Linux + 84) +#define __NR_readlink (__NR_Linux + 85) +#define __NR_uselib (__NR_Linux + 86) +#define __NR_swapon (__NR_Linux + 87) +#define __NR_reboot (__NR_Linux + 88) +#define __NR_readdir (__NR_Linux + 89) +#define __NR_mmap (__NR_Linux + 90) +#define __NR_munmap (__NR_Linux + 91) +#define __NR_truncate (__NR_Linux + 92) +#define __NR_ftruncate (__NR_Linux + 93) +#define __NR_fchmod (__NR_Linux + 94) +#define __NR_fchown (__NR_Linux + 95) +#define __NR_getpriority (__NR_Linux + 96) +#define __NR_setpriority (__NR_Linux + 97) +#define __NR_profil (__NR_Linux + 98) +#define __NR_statfs (__NR_Linux + 99) +#define __NR_fstatfs (__NR_Linux + 100) +#define __NR_ioperm (__NR_Linux + 101) +#define __NR_socketcall (__NR_Linux + 102) +#define __NR_syslog (__NR_Linux + 103) +#define __NR_setitimer (__NR_Linux + 104) +#define __NR_getitimer (__NR_Linux + 105) +#define __NR_stat (__NR_Linux + 106) +#define __NR_lstat (__NR_Linux + 107) +#define __NR_fstat (__NR_Linux + 108) +#define __NR_olduname (__NR_Linux + 109) +#define __NR_iopl (__NR_Linux + 110) +#define __NR_vhangup (__NR_Linux + 111) +#define __NR_idle (__NR_Linux + 112) +#define __NR_vm86 (__NR_Linux + 113) +#define __NR_wait4 (__NR_Linux + 114) +#define __NR_swapoff (__NR_Linux + 115) +#define __NR_sysinfo (__NR_Linux + 116) +#define __NR_ipc (__NR_Linux + 117) +#define __NR_fsync (__NR_Linux + 118) +#define __NR_sigreturn (__NR_Linux + 119) +#define __NR_clone (__NR_Linux + 120) +#define __NR_setdomainname (__NR_Linux + 121) +#define __NR_uname (__NR_Linux + 122) +#define __NR_modify_ldt (__NR_Linux + 123) +#define __NR_adjtimex (__NR_Linux + 124) +#define __NR_mprotect (__NR_Linux + 125) +#define __NR_sigprocmask (__NR_Linux + 126) +#define __NR_create_module (__NR_Linux + 127) +#define __NR_init_module (__NR_Linux + 128) +#define __NR_delete_module (__NR_Linux + 129) +#define __NR_get_kernel_syms (__NR_Linux + 130) +#define __NR_quotactl (__NR_Linux + 131) +#define __NR_getpgid (__NR_Linux + 132) +#define __NR_fchdir (__NR_Linux + 133) +#define __NR_bdflush (__NR_Linux + 134) +#define __NR_sysfs (__NR_Linux + 135) +#define __NR_personality (__NR_Linux + 136) +#define __NR_afs_syscall (__NR_Linux + 137) /* Syscall for Andrew File System */ +#define __NR_setfsuid (__NR_Linux + 138) +#define __NR_setfsgid (__NR_Linux + 139) +#define __NR__llseek (__NR_Linux + 140) +#define __NR_getdents (__NR_Linux + 141) +#define __NR__newselect (__NR_Linux + 142) +#define __NR_flock (__NR_Linux + 143) +#define __NR_msync (__NR_Linux + 144) +#define __NR_readv (__NR_Linux + 145) +#define __NR_writev (__NR_Linux + 146) +#define __NR_cacheflush (__NR_Linux + 147) +#define __NR_cachectl (__NR_Linux + 148) +#define __NR_sysmips (__NR_Linux + 149) +#define __NR_setup (__NR_Linux + 150) /* used only by init, to get system going */ +#define __NR_getsid (__NR_Linux + 151) +#define __NR_fdatasync (__NR_Linux + 152) +#define __NR__sysctl (__NR_Linux + 153) +#define __NR_mlock (__NR_Linux + 154) +#define __NR_munlock (__NR_Linux + 155) +#define __NR_mlockall (__NR_Linux + 156) +#define __NR_munlockall (__NR_Linux + 157) +#define __NR_sched_setparam (__NR_Linux + 158) +#define __NR_sched_getparam (__NR_Linux + 159) +#define __NR_sched_setscheduler (__NR_Linux + 160) +#define __NR_sched_getscheduler (__NR_Linux + 161) +#define __NR_sched_yield (__NR_Linux + 162) +#define __NR_sched_get_priority_max (__NR_Linux + 163) +#define __NR_sched_get_priority_min (__NR_Linux + 164) +#define __NR_sched_rr_get_interval (__NR_Linux + 165) +#define __NR_nanosleep (__NR_Linux + 166) +#define __NR_mremap (__NR_Linux + 167) +#define __NR_accept (__NR_Linux + 168) +#define __NR_bind (__NR_Linux + 169) +#define __NR_connect (__NR_Linux + 170) +#define __NR_getpeername (__NR_Linux + 171) +#define __NR_getsockname (__NR_Linux + 172) +#define __NR_getsockopt (__NR_Linux + 173) +#define __NR_listen (__NR_Linux + 174) +#define __NR_recv (__NR_Linux + 175) +#define __NR_recvfrom (__NR_Linux + 176) +#define __NR_recvmsg (__NR_Linux + 177) +#define __NR_send (__NR_Linux + 178) +#define __NR_sendmsg (__NR_Linux + 179) +#define __NR_sendto (__NR_Linux + 180) +#define __NR_setsockopt (__NR_Linux + 181) +#define __NR_shutdown (__NR_Linux + 182) +#define __NR_socket (__NR_Linux + 183) +#define __NR_socketpair (__NR_Linux + 184) +#define __NR_setresuid (__NR_Linux + 185) +#define __NR_getresuid (__NR_Linux + 186) + +/* + * Offset of the last Linux flavoured syscall + */ +#define __NR_Linux_syscalls 186 + +#ifndef __LANGUAGE_ASSEMBLY__ + /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ #define _syscall0(type,name) \ type name(void) \ { \ register long __res __asm__ ("$2"); \ -__asm__ volatile ("syscall" \ - : "=r" (__res) \ - : "0" (__NR_##name)); \ -if (__res >= 0) \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("li\t$2,%2\n\t" \ + "syscall" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name)); \ +if (__err == 0) \ return (type) __res; \ -errno = -__res; \ +errno = __res; \ return -1; \ } +/* + * DANGER: This macro isn't usable for the pipe(2) call + * which has a unusual return convention. + */ #define _syscall1(type,name,atype,a) \ type name(atype a) \ { \ register long __res __asm__ ("$2"); \ -__asm__ volatile ("move\t$4,%2\n\t" \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "li\t$2,%2\n\t" \ "syscall" \ - : "=r" (__res) \ - : "0" (__NR_##name),"r" ((long)(a)) \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)) \ : "$4"); \ -if (__res >= 0) \ +if (__err == 0) \ return (type) __res; \ -errno = -__res; \ +errno = __res; \ return -1; \ } @@ -34,16 +1224,18 @@ return -1; \ type name(atype a,btype b) \ { \ register long __res __asm__ ("$2"); \ -__asm__ volatile ("move\t$4,%2\n\t" \ - "move\t$5,%3\n\t" \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "li\t$2,%2\n\t" \ "syscall" \ - : "=r" (__res) \ - : "0" (__NR_##name),"r" ((long)(a)), \ - "r" ((long)(b))); \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)) \ : "$4","$5"); \ -if (__res >= 0) \ +if (__err == 0) \ return (type) __res; \ -errno = -__res; \ +errno = __res; \ return -1; \ } @@ -51,18 +1243,20 @@ return -1; \ type name (atype a, btype b, ctype c) \ { \ register long __res __asm__ ("$2"); \ -__asm__ volatile ("move\t$4,%2\n\t" \ - "move\t$5,%3\n\t" \ - "move\t$6,%4\n\t" \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "li\t$2,%2\n\t" \ "syscall" \ - : "=r" (__res) \ - : "0" (__NR_##name),"r" ((long)(a)), \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ "r" ((long)(b)), \ "r" ((long)(c)) \ : "$4","$5","$6"); \ -if (__res>=0) \ +if (__err == 0) \ return (type) __res; \ -errno=-__res; \ +errno = __res; \ return -1; \ } @@ -70,20 +1264,22 @@ return -1; \ type name (atype a, btype b, ctype c, dtype d) \ { \ register long __res __asm__ ("$2"); \ -__asm__ volatile ("move\t$4,%2\n\t" \ - "move\t$5,%3\n\t" \ - "move\t$6,%4\n\t" \ - "move\t$7,%5\n\t" \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "move\t$7,%6\n\t" \ + "li\t$2,%2\n\t" \ "syscall" \ - : "=r" (__res) \ - : "0" (__NR_##name),"r" ((long)(a)), \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ "r" ((long)(b)), \ "r" ((long)(c)), \ "r" ((long)(d)) \ - : "$4","$5","$6","$7"); \ -if (__res>=0) \ + : "$4","$5","$6"); \ +if (__err == 0) \ return (type) __res; \ -errno=-__res; \ +errno = __res; \ return -1; \ } @@ -91,22 +1287,92 @@ return -1; \ type name (atype a,btype b,ctype c,dtype d,etype e) \ { \ register long __res __asm__ ("$2"); \ -__asm__ volatile ("move\t$4,%2\n\t" \ - "move\t$5,%3\n\t" \ - "move\t$6,%4\n\t" \ - "move\t$7,%5\n\t" \ - "move\t$3,%6\n\t" \ - "syscall" \ - : "=r" (__res) \ - : "0" (__NR_##name),"r" ((long)(a)), \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "lw\t$2,%7\n\t" \ + "move\t$7,%6\n\t" \ + "subu\t$29,24\n\t" \ + "sw\t$2,16($29)\n\t" \ + "li\t$2,%2\n\t" \ + "syscall\n\t" \ + "addiu\t$29,24" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)), \ + "r" ((long)(c)), \ + "r" ((long)(d)), \ + "m" ((long)(e)) \ + : "$2","$4","$5","$6","$7"); \ +if (__err == 0) \ + return (type) __res; \ +errno = __res; \ +return -1; \ +} + +#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ +type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ +{ \ +register long __res __asm__ ("$2"); \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "lw\t$2,%7\n\t" \ + "lw\t$3,%8\n\t" \ + "move\t$7,%6\n\t" \ + "subu\t$29,24\n\t" \ + "sw\t$2,16($29)\n\t" \ + "sw\t$3,20($29)\n\t" \ + "li\t$2,%2\n\t" \ + "syscall\n\t" \ + "addiu\t$29,24" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)), \ + "r" ((long)(c)), \ + "r" ((long)(d)), \ + "m" ((long)(e)), \ + "m" ((long)(f)) \ + : "$2","$3","$4","$5","$6","$7"); \ +if (__err == 0) \ + return (type) __res; \ +errno = __res; \ +return -1; \ +} + +#define _syscall7(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f,gtype,g) \ +type name (atype a,btype b,ctype c,dtype d,etype e,ftype f,gtype g) \ +{ \ +register long __res __asm__ ("$2"); \ +register long __err __asm__ ("$7"); \ +__asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "lw\t$2,%7\n\t" \ + "lw\t$3,%8\n\t" \ + "move\t$7,%6\n\t" \ + "subu\t$29,32\n\t" \ + "sw\t$2,16($29)\n\t" \ + "lw\t$2,%9\n\t" \ + "sw\t$3,20($29)\n\t" \ + "sw\t$2,24($29)\n\t" \ + "li\t$2,%2\n\t" \ + "syscall\n\t" \ + "addiu\t$29,32" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ "r" ((long)(b)), \ "r" ((long)(c)), \ "r" ((long)(d)), \ - "r" ((long)(e)) \ - : "$3","$4","$5","$6","$7"); \ -if (__res>=0) \ + "m" ((long)(e)), \ + "m" ((long)(f)), \ + "m" ((long)(g)) \ + : "$2","$3","$4","$5","$6","$7"); \ +if (__err == 0) \ return (type) __res; \ -errno=-__res; \ +errno = __res; \ return -1; \ } @@ -127,6 +1393,7 @@ return -1; \ #define __NR__exit __NR_exit static inline _syscall0(int,idle) static inline _syscall0(int,fork) +static inline _syscall2(int,clone,unsigned long,flags,char *,esp) static inline _syscall0(int,pause) static inline _syscall0(int,setup) static inline _syscall0(int,sync) @@ -144,6 +1411,49 @@ static inline pid_t wait(int * wait_stat) return waitpid(-1,wait_stat,0); } -#endif +/* + * This is the mechanism for creating a new kernel thread. + * + * NOTE! Only a kernel-only process(ie the swapper or direct descendants + * who haven't done an "execve()") should use this: it will work within + * a system call from a "real" process, but the process memory space will + * not be free'd until both the parent and the child have exited. + */ +static inline pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) +{ + long retval; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + "move\t$8,$sp\n\t" + "move\t$4,%5\n\t" + "li\t$2,%1\n\t" + "syscall\n\t" + "beq\t$8,$sp,1f\n\t" + "subu\t$sp,32\n\t" /* delay slot */ + "jalr\t%4\n\t" + "move\t$4,%3\n\t" /* delay slot */ + "move\t$4,$2\n\t" + "li\t$2,%2\n\t" + "syscall\n" + "1:\taddiu\t$sp,32\n\t" + "move\t%0,$2\n\t" + ".set\treorder" + :"=r" (retval) + :"i" (__NR_clone), "i" (__NR_exit), + "r" (arg), "r" (fn), + "r" (flags | CLONE_VM) + /* + * The called subroutine might have destroyed any of the + * at, result, argument or temporary registers ... + */ + :"$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9","$10","$11","$12","$13","$14","$15","$24","$25"); + + return retval; +} + +#endif /* !defined (__KERNEL_SYSCALLS__) */ +#endif /* !defined (__LANGUAGE_ASSEMBLY__) */ #endif /* __ASM_MIPS_UNISTD_H */ diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h new file mode 100644 index 000000000..64069dd60 --- /dev/null +++ b/include/asm-mips/user.h @@ -0,0 +1,52 @@ +#ifndef __ASM_MIPS_USER_H +#define __ASM_MIPS_USER_H + +#include <linux/ptrace.h> + +#include <asm/page.h> +#include <asm/reg.h> + +/* + * Core file format: The core file is written in such a way that gdb + * can understand it and provide useful information to the user (under + * linux we use the `trad-core' bfd, NOT the osf-core). The file contents + * are as follows: + * + * upage: 1 page consisting of a user struct that tells gdb + * what is present in the file. Directly after this is a + * copy of the task_struct, which is currently not used by gdb, + * but it may come in handy at some point. All of the registers + * are stored as part of the upage. The upage should always be + * only one page long. + * data: The data segment follows next. We use current->end_text to + * current->brk to pick up all of the user variables, plus any memory + * that may have been sbrk'ed. No attempt is made to determine if a + * page is demand-zero or if a page is totally unused, we just cover + * the entire range. All of the addresses are rounded in such a way + * that an integral number of pages is written. + * stack: We need the stack information in order to get a meaningful + * backtrace. We need to write the data from usp to + * current->start_stack, so we round each of these in order to be able + * to write an integer number of pages. + */ +struct user { + unsigned long regs[EF_SIZE/8+32]; /* integer and fp regs */ + size_t u_tsize; /* text size (pages) */ + size_t u_dsize; /* data size (pages) */ + size_t u_ssize; /* stack size (pages) */ + unsigned long start_code; /* text starting address */ + unsigned long start_data; /* data starting address */ + unsigned long start_stack; /* stack starting address */ + long int signal; /* signal causing core dump */ + struct regs * u_ar0; /* help gdb find registers */ + unsigned long magic; /* identifies a core file */ + char u_comm[32]; /* user command name */ +}; + +#define NBPG PAGE_SIZE +#define UPAGES 1 +#define HOST_TEXT_START_ADDR (u.start_code) +#define HOST_DATA_START_ADDR (u.start_data) +#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) + +#endif /* __ASM_MIPS_USER_H */ diff --git a/include/asm-mips/vector.h b/include/asm-mips/vector.h index bc0d85e3b..23c5b8385 100644 --- a/include/asm-mips/vector.h +++ b/include/asm-mips/vector.h @@ -5,28 +5,50 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995 by Ralf Baechle + * Copyright (C) 1995, 1996 by Ralf Baechle */ +#ifndef __ASM_MIPS_VECTOR_H +#define __ASM_MIPS_VECTOR_H /* - * This structure defines how to access various features of - * different machine types and how to access them. - * - * FIXME: More things need to be accessed via this vector. + * These vector structures are not very good to maintain - they'd probably + * grow to at leat three times the size - so I'll remove 'em and replace + * the with lots of ordinary variables. */ -struct feature { - void (*handle_int)(void); -}; +extern void (*irq_setup)(void); +extern asmlinkage void (*fd_cacheflush)(const void *addr, size_t size); /* - * Similar to the above this is a structure that describes various - * CPU dependend features. - * - * FIXME: This vector isn't being used yet + * This structure defines how to access various features of + * different machine types and how to access them. */ -struct cpu { - int dummy; /* keep GCC from complaining */ +struct feature { + /* + * How to access the floppy controller's ports. + */ + unsigned char (*fd_inb)(unsigned int port); + void (*fd_outb)(unsigned char value, unsigned int port); + /* + * How to access the floppy DMA functions. + */ + void (*fd_enable_dma)(void); + void (*fd_disable_dma)(void); + int (*fd_request_dma)(void); + void (*fd_free_dma)(void); + void (*fd_clear_dma_ff)(void); + void (*fd_set_dma_mode)(char mode); + void (*fd_set_dma_addr)(unsigned int a); + void (*fd_set_dma_count)(unsigned int count); + int (*fd_get_dma_residue)(void); + void (*fd_enable_irq)(void); + void (*fd_disable_irq)(void); + /* + * How to access the RTC register of the DS1287? + */ + unsigned char (*rtc_read_data)(unsigned long addr); + void (*rtc_write_data)(unsigned char data, unsigned long addr); }; extern struct feature *feature; -extern struct cpu *cpu; + +#endif /* __ASM_MIPS_VECTOR_H */ diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h new file mode 100644 index 000000000..9c44856ef --- /dev/null +++ b/include/asm-mips/watch.h @@ -0,0 +1,38 @@ +/* + * Functions to use the watch register debugging functionality. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef __ASM_WATCH_H +#define __ASM_WATCH_H + +#include <linux/linkage.h> + +/* + * Types of reference for watch_set() + */ +enum wref_type { + wr_save = 1, + wr_load = 2 +}; + +extern asmlinkage unsigned int watch_available; +extern asmlinkage __watch_set(unsigned long addr, enum wref_type ref); +extern asmlinkage __watch_clear(void); +extern asmlinkage __watch_reenable(void); + +#define watch_set(addr, ref) \ + if (watch_available) \ + __watch_set(addr, ref) +#define watch_clear() \ + if (watch_available) \ + __watch_clear() +#define watch_reenable() \ + if (watch_available) \ + __watch_reenable() + +#endif __ASM_WATCH_H |