o Merge with Linux 2.1.116.

 o New Newport console code.
 o New G364 console code.

33 files changed, 1148 insertions, 551 deletions

diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 89668887e..d1b1d7152 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -372,6 +372,27 @@ extern __inline__ unsigned long ffz(unsigned long word)
 	return __res;
 }
 
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x) generic_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
 #ifdef __MIPSEB__
 /* For now I steal the Sparc C versions, no need for speed, just need to
  * get it working.
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index d20831322..f41ecd19e 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -1,4 +1,5 @@
-/*
+/* $Id: bootinfo.h,v 1.5 1998/08/19 21:58:10 ralf Exp $
+ *
  * bootinfo.h -- Definition of the Linux/MIPS boot information structure
  *
  * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse,
@@ -7,8 +8,6 @@
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file COPYING in the main directory of this archive
  * for more details.
- *
- * $Id: bootinfo.h,v 1.3 1997/09/19 08:37:44 ralf Exp $
  */
 #ifndef __ASM_MIPS_BOOTINFO_H
 #define __ASM_MIPS_BOOTINFO_H
@@ -26,10 +25,10 @@
 #define MACH_GROUP_SNI_RM	4 /* Siemens Nixdorf RM series                */
 #define MACH_GROUP_ACN		5
 #define MACH_GROUP_SGI          6 /* Silicon Graphics workstations and servers */
-#define MACH_GROUP_RESERVED     7 /* No Such Architecture	 	      */
+#define MACH_GROUP_COBALT       7 /* Cobalt servers		 	      */
 
 #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \
-                      "SNI", "ACN", "SGI", "NSA" }
+                      "SNI", "ACN", "SGI", "Cobalt" }
 
 /*
  * Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -86,6 +85,13 @@
 #define GROUP_SGI_NAMES { "Indy" }
 
 /*
+ * Valid machtype for group COBALT
+ */
+#define MACH_COBALT_27 		 0	/* Proto "27" hardware */
+
+#define GROUP_COBALT_NAMES { "Microserver 27" }
+
+/*
  * Valid cputype values
  */
 #define CPU_UNKNOWN		0
@@ -126,7 +132,7 @@
 
 #define CL_SIZE      (80)
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 /*
  * Some machine parameters passed by the bootloaders. 
@@ -266,20 +272,18 @@ void bi_TagWalk(void);
 
 
 #ifdef CONFIG_SGI
-
 /* screen info will dissapear... soon */
-#define DEFAULT_SCREEN_INFO {0, 0, {0, 0, }, 0, 0, 158, 0, 0, 0, 62, 0, 16}
+//#define DEFAULT_SCREEN_INFO {0, 0, 0, 0, 0, 158, 0, 0, 0, 62, 0, 16}
+#define DEFAULT_SCREEN_INFO {0, 0, 0, 0, 0, 160, 0, 0, 0, 64, 0, 16}
 #define DEFAULT_DRIVE_INFO { {0,}}
-
 #else
-
 /* default values for screen_info variable */
-#define DEFAULT_SCREEN_INFO {0, 0, {0, }, 52, 3, 80, 4626, 3, 9, 50}
+#define DEFAULT_SCREEN_INFO {0, 0, 0, 52, 3, 80, 4626, 3, 9, 50}
+#endif
+
 /* default values for drive info */
 #define DEFAULT_DRIVE_INFO { {0,}}
 
-#endif
-
 
 /*
  * These are the kernel variables initialized from
@@ -296,6 +300,6 @@ extern unsigned long mips_vram_base;
 extern unsigned long mips_dma_cache_size;
 extern unsigned long mips_dma_cache_base;
 
-#endif /* __LANGUAGE_ASSEMBLY__ */
+#endif /* _LANGUAGE_ASSEMBLY */
 
 #endif /* __ASM_MIPS_BOOTINFO_H */
diff --git a/include/asm-mips/current.h b/include/asm-mips/current.h
index 30facf94b..bcaf22b5c 100644
--- a/include/asm-mips/current.h
+++ b/include/asm-mips/current.h
@@ -1,13 +1,21 @@
+/* $Id: current.h,v 1.4 1998/07/20 17:52:19 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ralf Baechle
+ */
 #ifndef __ASM_MIPS_CURRENT_H
 #define __ASM_MIPS_CURRENT_H
 
-#ifdef __LANGUAGE_C__
+#ifdef _LANGUAGE_C
 
 /* MIPS rules... */
 register struct task_struct *current asm("$28");
 
-#endif /* __LANGUAGE_C__ */
-#ifdef __LANGUAGE_ASSEMBLY__
+#endif /* _LANGUAGE_C */
+#ifdef _LANGUAGE_ASSEMBLY
 
 /*
  * Special variant for use by exception handlers when the stack pointer
diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h
index d0e757c9b..0bf2aafb9 100644
--- a/include/asm-mips/gdb-stub.h
+++ b/include/asm-mips/gdb-stub.h
@@ -1,9 +1,11 @@
-/*
- *  include/asm-mips/gdb-stub.h
+/* $Id: gdb-stub.h,v 1.3 1998/07/20 17:52:19 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- *  Copyright (C) 1995 Andreas Busse
+ * Copyright (C) 1995 Andreas Busse
  */
-
 #ifndef __ASM_MIPS_GDB_STUB_H
 #define __ASM_MIPS_GDB_STUB_H
 
@@ -131,7 +133,7 @@
 
 #define GDB_FR_SIZE		((((GDB_FR_CP0_PRID) + 4) + (PTRSIZE-1)) & ~(PTRSIZE-1))
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 /*
  * This is the same as above, but for the high-level
@@ -207,5 +209,5 @@ struct gdb_regs {
 
 void set_debug_traps(void);
 
-#endif /* __LANGUAGE_ASSEMBLY */
+#endif /* _LANGUAGE_ASSEMBLY */
 #endif /* __ASM_MIPS_GDB_STUB_H */
diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h
index 9a666e6c5..f651556c0 100644
--- a/include/asm-mips/hardirq.h
+++ b/include/asm-mips/hardirq.h
@@ -1,3 +1,11 @@
+/* $Id: hardirq.h,v 1.4 1998/08/20 11:26:19 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1998 by Ralf Baechle
+ */
 #ifndef __ASM_MIPS_HARDIRQ_H
 #define __ASM_MIPS_HARDIRQ_H
 
@@ -5,6 +13,13 @@
 
 extern unsigned int local_irq_count[NR_CPUS];
 
+/*
+ * Are we in an interrupt context? Either doing bottom half
+ * or hardware interrupt processing?
+ */
+#define in_interrupt() ({ int __cpu = smp_processor_id(); \
+	(local_irq_count[__cpu] + local_bh_count[__cpu] != 0); })
+
 #ifndef __SMP__
 
 #define hardirq_trylock(cpu)	(local_irq_count[cpu] == 0)
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
index c7142ceb2..5e268a1c5 100644
--- a/include/asm-mips/ioctls.h
+++ b/include/asm-mips/ioctls.h
@@ -1,5 +1,4 @@
-/*
- * ioctls for Linux/MIPS.
+/* $Id: ioctls.h,v 1.5 1998/08/19 21:58:11 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -113,5 +112,7 @@
 #define TIOCSERSETMULTI 0x5490 /* Set multiport config */
 #define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
 #define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
+#define TIOCGHAYESESP	0x5493 /* Get Hayes ESP configuration */
+#define TIOCSHAYESESP	0x5494 /* Set Hayes ESP configuration */
 
 #endif /* __ASM_MIPS_IOCTLS_H */
diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h
index 7cd009438..f57cf7b95 100644
--- a/include/asm-mips/jazz.h
+++ b/include/asm-mips/jazz.h
@@ -1,15 +1,10 @@
-/*
- * Hardware info about Mips JAZZ and similar systems
+/* $Id: jazz.h,v 1.6 1998/08/18 20:46:39 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995 by Andreas Busse and Ralf Baechle
- *
- * This file is a mess. It really needs some reorganisation!
- *
- * $Id: jazz.h,v 1.5 1997/12/01 21:26:48 ralf Exp $
+ * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
  */
 #ifndef __ASM_MIPS_JAZZ_H 
 #define __ASM_MIPS_JAZZ_H 
@@ -76,7 +71,7 @@
 #define LED_E                   0x9e
 #define LED_F                   0x8e
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 extern __inline__ void pica_set_led(unsigned int bits)
 {
@@ -106,7 +101,7 @@ extern __inline__ void pica_set_led(unsigned int bits)
 #define JAZZ_KEYBOARD_DATA      0xe0005000
 #define JAZZ_KEYBOARD_COMMAND   0xe0005001
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 typedef struct {
 	unsigned char data;
@@ -158,7 +153,7 @@ typedef struct {
 /*
  * DRAM configuration register
  */
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 #ifdef __MIPSEL__
 typedef struct {
 	unsigned int bank2 : 3;
@@ -178,7 +173,7 @@ typedef struct {
 	unsigned int bank2 : 3;
 } dram_configuration;
 #endif
-#endif /* __LANGUAGE_ASSEMBLY__ */
+#endif /* _LANGUAGE_ASSEMBLY */
 
 #define PICA_DRAM_CONFIG        0xe00fffe0
 
@@ -213,7 +208,6 @@ typedef struct {
 #define JAZZ_SERIAL1_IRQ        18
 #define JAZZ_SERIAL2_IRQ        19
 #define JAZZ_PARALLEL_IRQ       20
-#define JAZZ_MOUSE_IRQ          21
 
 /*
  * JAZZ DMA Channels
@@ -269,7 +263,7 @@ typedef struct {
 /*
  * Access the R4030 DMA and I/O Controller
  */
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 extern inline void r4030_delay(void)
 {
@@ -302,7 +296,7 @@ extern inline void r4030_write_reg16(unsigned addr, unsigned val)
 	r4030_delay();
 }
 
-extern inline unsigned int r4030_write_reg32(unsigned addr, unsigned val)
+extern inline void r4030_write_reg32(unsigned addr, unsigned val)
 {
 	*((volatile unsigned int *)addr) = val;
 	r4030_delay();
diff --git a/include/asm-mips/keyboard.h b/include/asm-mips/keyboard.h
index bba0a1876..6b393c032 100644
--- a/include/asm-mips/keyboard.h
+++ b/include/asm-mips/keyboard.h
@@ -5,7 +5,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * $Id: keyboard.h,v 1.7 1998/05/07 03:02:50 ralf Exp $
+ * $Id: keyboard.h,v 1.8 1998/07/13 23:27:07 tsbogend Exp $
  */
 #ifndef __ASM_MIPS_KEYBOARD_H
 #define __ASM_MIPS_KEYBOARD_H
@@ -52,13 +52,11 @@ void (*keyboard_setup)(void);
 #ifdef CONFIG_MIPS_JAZZ
 
 /* Not true for Jazz machines, we cheat a bit for 'em. */
-#define KEYBOARD_IRQ    1
-
-extern int jazz_ps2_request_irq(void);
-extern void jazz_ps2_free_irq(void);
+#define KEYBOARD_IRQ 1
 
-#define ps2_request_irq()      jazz_ps2_request_irq()
-#define ps2_free_irq(inode)    jazz_ps2_free_irq()
+/*
+ * No PS/2 style mouse support for Jazz machines
+ */
 
 #endif /* CONFIG_MIPS_JAZZ */
 
@@ -78,6 +76,10 @@ extern void jazz_ps2_free_irq(void);
 
 #endif /* CONFIG_SGI */
 
+#ifdef CONFIG_COBALT_MICRO_SERVER
+#define KEYBOARD_IRQ 1
+#endif
+
 #if defined(CONFIG_ACER_PICA_61) || defined(CONFIG_SNI_RM200_PCI)
 #define CONF_KEYBOARD_USES_IO_PORTS
 #endif
diff --git a/include/asm-mips/linux_logo.h b/include/asm-mips/linux_logo.h
new file mode 100644
index 000000000..b4ad836a3
--- /dev/null
+++ b/include/asm-mips/linux_logo.h
@@ -0,0 +1,69 @@
+/* $Id: linux_logo.h,v 1.1 1998/08/19 21:58:12 ralf Exp $
+ * include/asm-mips/linux_logo.h: This is a linux logo
+ *                                 to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * You can put anything here, but:
+ * LINUX_LOGO_COLORS has to be less than 224
+ * image size has to be 80x80
+ * values have to start from 0x20
+ * (i.e. RGB(linux_logo_red[0],
+ *	     linux_logo_green[0],
+ *	     linux_logo_blue[0]) is color 0x20)
+ * BW image has to be 80x80 as well, with MS bit
+ * on the left
+ * Serial_console ascii image can be any size,
+ * but should contain %s to display the version
+ */
+ 
+#include <linux/init.h>
+#include <linux/version.h>
+
+#define linux_logo_banner "Linux/m68k version " UTS_RELEASE
+
+#define LINUX_LOGO_COLORS 221
+
+#ifdef INCLUDE_LINUX_LOGO_DATA
+
+#define INCLUDE_LINUX_LOGO16
+#include <linux/linux_logo.h>
+
+/* Painted by Johnny Stenback <jst@uwasa.fi> */
+
+unsigned char *linux_serial_image __initdata = "\n"
+"         .u$e.\n"
+"       .$$$$$:S\n"
+"       $\"*$/\"*$$\n"
+"       $.`$ . ^F\n"
+"       4k+#+T.$F\n"
+"       4P+++\"$\"$\n"
+"       :R\"+  t$$B\n"
+"    ___#       $$$\n"
+"    |  |       R$$k\n"
+"   dd. | Linux  $!$\n"
+"   ddd |  MIPS  $9$F\n"
+" '!!!!!$       !!#!`\n"
+"  !!!!!*     .!!!!!`\n"
+"'!!!!!!!W..e$$!!!!!!`    %s\n"
+" \"~^^~         ^~~^\n"
+"\n";
+
+#else
+
+/* prototypes only */
+extern unsigned char linux_logo_red[];
+extern unsigned char linux_logo_green[];
+extern unsigned char linux_logo_blue[];
+extern unsigned char linux_logo[];
+extern unsigned char linux_logo_bw[];
+extern unsigned char linux_logo16_red[];
+extern unsigned char linux_logo16_green[];
+extern unsigned char linux_logo16_blue[];
+extern unsigned char linux_logo16[];
+extern unsigned char *linux_serial_image;
+
+extern int (*console_show_logo)(void);
+
+#endif
diff --git a/include/asm-mips/md.h b/include/asm-mips/md.h
new file mode 100644
index 000000000..aff87490d
--- /dev/null
+++ b/include/asm-mips/md.h
@@ -0,0 +1,14 @@
+/* $Id: md.h,v 1.1 1998/08/17 10:20:14 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_MD_H
+#define __ASM_MD_H
+
+/* #define HAVE_ARCH_XORBLOCK */
+
+#define MD_XORBLOCK_ALIGNMENT	sizeof(long)
+
+#endif /* __ASM_MD_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 2a563efb9..4b26fa496 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -1,5 +1,4 @@
-/*
- * include/asm-mips/mipsregs.h
+/* $Id: mipsregs.h,v 1.6 1998/08/17 11:27:08 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -7,8 +6,6 @@
  *
  * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle
  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- *
- * $Id: mipsregs.h,v 1.4 1997/09/20 19:02:46 root Exp $
  */
 #ifndef __ASM_MIPS_MIPSREGS_H
 #define __ASM_MIPS_MIPSREGS_H
@@ -157,7 +154,7 @@
 #define C_IRQ4          (1<<14)
 #define C_IRQ5          (1<<15)
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 /*
  * Manipulate the status register.
  * Mostly used to access the interrupt bits.
@@ -181,7 +178,7 @@ __BUILD_SET_CP0(status,CP0_STATUS)
 __BUILD_SET_CP0(cause,CP0_CAUSE)
 __BUILD_SET_CP0(config,CP0_CONFIG)
 
-#endif /* defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* defined (_LANGUAGE_ASSEMBLY) */
 
 /*
  * Inline code for use of the ll and sc instructions
@@ -319,18 +316,18 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
 /*
  * Bits in the coprozessor 0 config register.
  */
-#define CONFIG_CM_CACHABLE_NO_WA	0
-#define CONFIG_CM_CACHABLE_WA		1
-#define CONFIG_CM_UNCACHED		2
-#define CONFIG_CM_CACHABLE_NONCOHERENT	3
-#define CONFIG_CM_CACHABLE_CE		4
-#define CONFIG_CM_CACHABLE_COW		5
-#define CONFIG_CM_CACHABLE_CUW		6
-#define CONFIG_CM_CACHABLE_ACCELERATED	7
-#define CONFIG_CM_CMASK			7
-#define CONFIG_DB			(1 <<  4)
-#define CONFIG_IB			(1 <<  5)
-#define CONFIG_SC			(1 << 17)
+#define CONF_CM_CACHABLE_NO_WA		0
+#define CONF_CM_CACHABLE_WA		1
+#define CONF_CM_UNCACHED		2
+#define CONF_CM_CACHABLE_NONCOHERENT	3
+#define CONF_CM_CACHABLE_CE		4
+#define CONF_CM_CACHABLE_COW		5
+#define CONF_CM_CACHABLE_CUW		6
+#define CONF_CM_CACHABLE_ACCELERATED	7
+#define CONF_CM_CMASK			7
+#define CONF_DB				(1 <<  4)
+#define CONF_IB				(1 <<  5)
+#define CONF_SC				(1 << 17)
 
 /*
  * R10000 performance counter definitions.
@@ -388,7 +385,7 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
 #define CEB_KERNEL	2	/* Count events in kernel mode EXL = ERL = 0 */
 #define CEB_EXL		1	/* Count events with EXL = 1, ERL = 0 */
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 /*
  * Functions to access the performance counter and control registers
  */
diff --git a/include/asm-mips/ncr53c94.h b/include/asm-mips/ncr53c94.h
deleted file mode 100644
index bf5c072f4..000000000
--- a/include/asm-mips/ncr53c94.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Makefile for MIPS Linux main source directory
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996 by Ralf Baechle
- */
-
-/*
- * As far as I know there are some MIPS boxes which have their NCRs
- * mapped with pad bytes.  For these NCR_PAD will have to be redefined.
- */
-#define NCR_PAD(name)
-struct ncr53c94 {
-	NCR_PAD(pad0);
-	volatile unsigned char count_lo;
-	NCR_PAD(pad1);
-	volatile unsigned char count_hi;
-	NCR_PAD(pad2);
-	volatile unsigned char fifo;
-	NCR_PAD(pad3);
-	volatile unsigned char command;
-	NCR_PAD(pad4);
-	union {
-		volatile unsigned char status;
-		volatile unsigned char dest_id;
-	} s_d;
-	NCR_PAD(pad5);
-	union {
-		volatile unsigned char interrupts;
-		volatile unsigned char timeout;
-	} i_t;
-	NCR_PAD(pad6);
-	union {
-		volatile unsigned char seqn_step;
-		volatile unsigned char sync_period;
-	} s_p;
-	NCR_PAD(pad7);
-	union {
-		volatile unsigned char fifo_flags;
-		volatile unsigned char sync_offset;
-	} f_o;
-	NCR_PAD(pad8);
-	volatile unsigned char config1;
-	NCR_PAD(pad9);
-	volatile unsigned char clk_conv;
-	NCR_PAD(pad10);
-	volatile unsigned char test;
-	NCR_PAD(pad11);
-	volatile unsigned char config2;
-	NCR_PAD(pad12);
-	volatile unsigned char config3;
-	NCR_PAD(pad13);
-	volatile unsigned char unused;
-	NCR_PAD(pad14);
-	volatile unsigned char count_xhi;
-	NCR_PAD(pad15);
-	volatile unsigned char fifo_b;
-};
-
-/*
- * Clock conversion factors
- */
-#define CCV_10MHZ	0x2		/* 10 Mhz         */
-#define CCV_15MHZ	0x3		/* 10.01 - 15 Mhz */
-#define CCV_20MHZ	0x4		/* 15.01 - 20 Mhz */
-#define CCV_25MHZ	0x5		/* 20.01 - 25 Mhz */
-#define CCV_30MHZ	0x6		/* 25.01 - 30 Mhz */
-#define CCV_35MHZ	0x7		/* 30.01 - 35 Mhz */
-#define CCV_40MHZ	0x0		/* 35.01 - 40 Mhz */
-
-/*
- * Set this additional to enable DMA for a command.
- */
-#define NCR_DMA			0x80
-
-/*
- * Miscellaneous commands
- */
-#define NCR_NOP			0x00
-#define NCR_FLUSH_FIFO		0x01
-#define NCR_RESET_NCR		0x02
-#define NCR_RESET_SCSI		0x03
-
-/*
- * Disconnected state commands
- */
-#define NCR_SELECT_NO_ATN	0x41
-#define NCR_SELECT_ATN		0x42
-#define NCR_SELECT_ATN_STOP	0x43
-#define NCR_ENABLE_RESEL	0x44
-#define NCR_DISABLE_RESEL	0x45
-#define NCR_SELECT_ATN3		0x46
-
-/*
- * Initiator state commands
- */
-#define NCR_TRANSFER		0x10
-#define NCR_CMD_CMP		0x11
-#define NCR_MSG_OK		0x12
-#define NCR_TRANSFER_PAD	0x18
-#define NCR_SET_ATN		0x1a
-#define NCR_RESET_ATN		0x1b
-
-/*
- * Target state commands
- */
-#define NCR_SEND_MSG		0x20
-#define NCR_SEND_STATUS		0x21
-#define NCR_SEND_DATA		0x22
-#define NCR_DISC_SEQN		0x23
-#define NCR_TERM_SEQN		0x24
-#define NCR_CMD_COMP_SEQN	0x25
-#define NCR_DISC		0x27
-#define NCR_REC_MSG		0x28
-#define NCR_REC_CMD		0x29
-#define NCR_REC_DATA		0x2a
-#define NCR_REC_CMD_SEQN	0x2b
-#define NCR_ABORT_DMA		0x04
diff --git a/include/asm-mips/newport.h b/include/asm-mips/newport.h
new file mode 100644
index 000000000..a9ef5b3e5
--- /dev/null
+++ b/include/asm-mips/newport.h
@@ -0,0 +1,586 @@
+/* $Id: newport.h,v 1.1 1998/08/19 21:58:12 ralf Exp $
+ *
+ * newport.h: Defines and register layout for NEWPORT graphics
+ *            hardware.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ */
+
+#ifndef _SGI_NEWPORT_H
+#define _SGI_NEWPORT_H
+
+
+typedef volatile unsigned long npireg_t;
+
+union npfloat {
+	volatile float f;
+	npireg_t       i;
+};
+
+typedef union npfloat npfreg_t;
+
+union np_dcb {
+	npireg_t all;
+	struct { volatile unsigned short s0, s1; } hwords;
+	struct { volatile unsigned char b0, b1, b2, b3; } bytes;
+};
+
+struct newport_rexregs {
+	npireg_t drawmode1;      /* GL extra mode bits */
+	
+#define DM1_PLANES         0x00000007
+#define    DM1_NOPLANES    0x00000000
+#define    DM1_RGBPLANES   0x00000001
+#define    DM1_RGBAPLANES  0x00000002
+#define    DM1_OLAYPLANES  0x00000004
+#define    DM1_PUPPLANES   0x00000005
+#define    DM1_CIDPLANES   0x00000006
+	
+#define NPORT_DMODE1_DDMASK      0x00000018
+#define NPORT_DMODE1_DD4         0x00000000
+#define NPORT_DMODE1_DD8         0x00000008
+#define NPORT_DMODE1_DD12        0x00000010
+#define NPORT_DMODE1_DD24        0x00000018
+#define NPORT_DMODE1_DSRC        0x00000020
+#define NPORT_DMODE1_YFLIP       0x00000040
+#define NPORT_DMODE1_RWPCKD      0x00000080
+#define NPORT_DMODE1_HDMASK      0x00000300
+#define NPORT_DMODE1_HD4         0x00000000
+#define NPORT_DMODE1_HD8         0x00000100
+#define NPORT_DMODE1_HD12        0x00000200
+#define NPORT_DMODE1_HD32        0x00000300
+#define NPORT_DMODE1_RWDBL       0x00000400
+#define NPORT_DMODE1_ESWAP       0x00000800 /* Endian swap */
+#define NPORT_DMODE1_CCMASK      0x00007000
+#define NPORT_DMODE1_CCLT        0x00001000
+#define NPORT_DMODE1_CCEQ        0x00002000
+#define NPORT_DMODE1_CCGT        0x00004000
+#define NPORT_DMODE1_RGBMD       0x00008000
+#define NPORT_DMODE1_DENAB       0x00010000 /* Dither enable */
+#define NPORT_DMODE1_FCLR        0x00020000 /* Fast clear */
+#define NPORT_DMODE1_BENAB       0x00040000 /* Blend enable */
+#define NPORT_DMODE1_SFMASK      0x00380000
+#define NPORT_DMODE1_SF0         0x00000000
+#define NPORT_DMODE1_SF1         0x00080000
+#define NPORT_DMODE1_SFDC        0x00100000
+#define NPORT_DMODE1_SFMDC       0x00180000
+#define NPORT_DMODE1_SFSA        0x00200000
+#define NPORT_DMODE1_SFMSA       0x00280000
+#define NPORT_DMODE1_DFMASK      0x01c00000
+#define NPORT_DMODE1_DF0         0x00000000
+#define NPORT_DMODE1_DF1         0x00400000
+#define NPORT_DMODE1_DFSC        0x00800000
+#define NPORT_DMODE1_DFMSC       0x00c00000
+#define NPORT_DMODE1_DFSA        0x01000000
+#define NPORT_DMODE1_DFMSA       0x01400000
+#define NPORT_DMODE1_BBENAB      0x02000000 /* Back blend enable */
+#define NPORT_DMODE1_PFENAB      0x04000000 /* Pre-fetch enable */
+#define NPORT_DMODE1_ABLEND      0x08000000 /* Alpha blend */
+#define NPORT_DMODE1_LOMASK      0xf0000000
+#define NPORT_DMODE1_LOZERO      0x00000000
+#define NPORT_DMODE1_LOAND       0x10000000
+#define NPORT_DMODE1_LOANDR      0x20000000
+#define NPORT_DMODE1_LOSRC       0x30000000
+#define NPORT_DMODE1_LOANDI      0x40000000
+#define NPORT_DMODE1_LODST       0x50000000
+#define NPORT_DMODE1_LOXOR       0x60000000
+#define NPORT_DMODE1_LOOR        0x70000000
+#define NPORT_DMODE1_LONOR       0x80000000
+#define NPORT_DMODE1_LOXNOR      0x90000000
+#define NPORT_DMODE1_LONDST      0xa0000000
+#define NPORT_DMODE1_LOORR       0xb0000000
+#define NPORT_DMODE1_LONSRC      0xc0000000
+#define NPORT_DMODE1_LOORI       0xd0000000
+#define NPORT_DMODE1_LONAND      0xe0000000
+#define NPORT_DMODE1_LOONE       0xf0000000
+
+	npireg_t drawmode0;      /* REX command register */
+
+	/* These bits define the graphics opcode being performed. */
+#define NPORT_DMODE0_OPMASK   0x00000003 /* Opcode mask */
+#define NPORT_DMODE0_NOP      0x00000000 /* No operation */
+#define NPORT_DMODE0_RD       0x00000001 /* Read operation */
+#define NPORT_DMODE0_DRAW     0x00000002 /* Draw operation */
+#define NPORT_DMODE0_S2S      0x00000003 /* Screen to screen operation */
+
+	/* The following decide what addressing mode(s) are to be used */
+#define NPORT_DMODE0_AMMASK   0x0000001c /* Address mode mask */
+#define NPORT_DMODE0_SPAN     0x00000000 /* Spanning address mode */
+#define NPORT_DMODE0_BLOCK    0x00000004 /* Block address mode */
+#define NPORT_DMODE0_ILINE    0x00000008 /* Iline address mode */
+#define NPORT_DMODE0_FLINE    0x0000000c /* Fline address mode */
+#define NPORT_DMODE0_ALINE    0x00000010 /* Aline address mode */
+#define NPORT_DMODE0_TLINE    0x00000014 /* Tline address mode */
+#define NPORT_DMODE0_BLINE    0x00000018 /* Bline address mode */
+
+	/* And now some misc. operation control bits. */
+#define NPORT_DMODE0_DOSETUP  0x00000020
+#define NPORT_DMODE0_CHOST    0x00000040
+#define NPORT_DMODE0_AHOST    0x00000080
+#define NPORT_DMODE0_STOPX    0x00000100
+#define NPORT_DMODE0_STOPY    0x00000200
+#define NPORT_DMODE0_SK1ST    0x00000400
+#define NPORT_DMODE0_SKLST    0x00000800
+#define NPORT_DMODE0_ZPENAB   0x00001000
+#define NPORT_DMODE0_LISPENAB 0x00002000
+#define NPORT_DMODE0_LISLST   0x00004000
+#define NPORT_DMODE0_L32      0x00008000
+#define NPORT_DMODE0_ZOPQ     0x00010000
+#define NPORT_DMODE0_LISOPQ   0x00020000
+#define NPORT_DMODE0_SHADE    0x00040000
+#define NPORT_DMODE0_LRONLY   0x00080000
+#define NPORT_DMODE0_XYOFF    0x00100000
+#define NPORT_DMODE0_CLAMP    0x00200000
+#define NPORT_DMODE0_ENDPF    0x00400000
+#define NPORT_DMODE0_YSTR     0x00800000
+
+	npireg_t lsmode;      /* Mode for line stipple ops */
+	npireg_t lspattern;   /* Pattern for line stipple ops */
+	npireg_t lspatsave;   /* Backup save pattern */
+	npireg_t zpattern;    /* Pixel zpattern */
+	npireg_t colorback;   /* Background color */
+	npireg_t colorvram;   /* Clear color for fast vram */
+	npireg_t alpharef;    /* Reference value for afunctions */
+	unsigned long pad0;
+	npireg_t smask0x;     /* Window GL relative screen mask 0 */
+	npireg_t smask0y;     /* Window GL relative screen mask 0 */
+	npireg_t _setup;
+	npireg_t _stepz;
+	npireg_t _lsrestore;
+	npireg_t _lssave;
+
+	unsigned long _pad1[0x30];
+
+	/* Iterators, full state for context switch */
+	npfreg_t _xstart;	/* X-start point (current) */
+	npfreg_t _ystart;	/* Y-start point (current) */
+	npfreg_t _xend;		/* x-end point */
+	npfreg_t _yend;		/* y-end point */
+	npireg_t xsave;		/* copy of xstart integer value for BLOCk addressing MODE */
+	npireg_t xymove;	/* x.y offset from xstart, ystart for relative operations */
+	npfreg_t bresd;
+	npfreg_t bress1;;
+	npireg_t bresoctinc1;
+	volatile int bresrndinc2;
+	npireg_t brese1;
+	npireg_t bress2;
+	npireg_t aweight0;
+	npireg_t aweight1;
+	npfreg_t xstartf;
+	npfreg_t ystartf;
+	npfreg_t xendf;
+	npfreg_t yendf;
+	npireg_t xstarti;
+	npfreg_t xendf1;
+	npireg_t xystarti;
+	npireg_t xyendi;
+	npireg_t xstartendi;
+
+	unsigned long _unused2[0x29];
+
+	npfreg_t colorred;
+	npfreg_t coloralpha;
+	npfreg_t colorgrn;
+	npfreg_t colorblue;
+	npfreg_t slopered;
+	npfreg_t slopealpha;
+	npfreg_t slopegrn;
+	npfreg_t slopeblue;
+	npireg_t wrmask;
+	npireg_t colori;
+	npfreg_t colorx;
+	npfreg_t slopered1;
+	npireg_t hostrw0;
+	npireg_t hostrw1;
+	npireg_t dcbmode;
+#define NPORT_DMODE_WMASK   0x00000003
+#define NPORT_DMODE_W4      0x00000000
+#define NPORT_DMODE_W1      0x00000001
+#define NPORT_DMODE_W2      0x00000002
+#define NPORT_DMODE_W3      0x00000003
+#define NPORT_DMODE_EDPACK  0x00000004
+#define NPORT_DMODE_ECINC   0x00000008
+#define NPORT_DMODE_CMASK   0x00000070
+#define NPORT_DMODE_AMASK   0x00000780
+#define NPORT_DMODE_AVC2    0x00000000
+#define NPORT_DMODE_ACMALL  0x00000080
+#define NPORT_DMODE_ACM0    0x00000100
+#define NPORT_DMODE_ACM1    0x00000180
+#define NPORT_DMODE_AXMALL  0x00000200
+#define NPORT_DMODE_AXM0    0x00000280
+#define NPORT_DMODE_AXM1    0x00000300
+#define NPORT_DMODE_ABT     0x00000380
+#define NPORT_DMODE_AVCC1   0x00000400
+#define NPORT_DMODE_AVAB1   0x00000480
+#define NPORT_DMODE_ALG3V0  0x00000500
+#define NPORT_DMODE_A1562   0x00000580
+#define NPORT_DMODE_ESACK   0x00000800
+#define NPORT_DMODE_EASACK  0x00001000
+#define NPORT_DMODE_CWMASK  0x0003e000
+#define NPORT_DMODE_CHMASK  0x007c0000
+#define NPORT_DMODE_CSMASK  0x0f800000
+#define NPORT_DMODE_SENDIAN 0x10000000
+
+	unsigned long _unused3;
+
+	union np_dcb dcbdata0;
+	npireg_t dcbdata1;
+};
+
+struct newport_cregs {
+	npireg_t smask1x;
+	npireg_t smask1y;
+	npireg_t smask2x;
+	npireg_t smask2y;
+	npireg_t smask3x;
+	npireg_t smask3y;
+	npireg_t smask4x;
+	npireg_t smask4y;
+	npireg_t topscan;
+	npireg_t xywin;
+	npireg_t clipmode;
+#define NPORT_CMODE_SM0   0x00000001
+#define NPORT_CMODE_SM1   0x00000002
+#define NPORT_CMODE_SM2   0x00000004
+#define NPORT_CMODE_SM3   0x00000008
+#define NPORT_CMODE_SM4   0x00000010
+#define NPORT_CMODE_CMSK  0x00001e00
+
+	unsigned long _unused0;
+	unsigned long config;
+#define NPORT_CFG_G32MD   0x00000001
+#define NPORT_CFG_BWIDTH  0x00000002
+#define NPORT_CFG_ERCVR   0x00000004
+#define NPORT_CFG_BDMSK   0x00000078
+#define NPORT_CFG_GDMSK   0x00000f80
+#define NPORT_CFG_GD0     0x00000080
+#define NPORT_CFG_GD1     0x00000100
+#define NPORT_CFG_GD2     0x00000200
+#define NPORT_CFG_GD3     0x00000400
+#define NPORT_CFG_GD4     0x00000800
+#define NPORT_CFG_GFAINT  0x00001000
+#define NPORT_CFG_TOMSK   0x0000e000
+#define NPORT_CFG_VRMSK   0x00070000
+#define NPORT_CFG_FBTYP   0x00080000
+
+	npireg_t _unused1;
+	npireg_t stat;
+#define NPORT_STAT_VERS   0x00000007
+#define NPORT_STAT_GBUSY  0x00000008
+#define NPORT_STAT_BBUSY  0x00000010
+#define NPORT_STAT_VRINT  0x00000020
+#define NPORT_STAT_VIDINT 0x00000040
+#define NPORT_STAT_GLMSK  0x00001f80
+#define NPORT_STAT_BLMSK  0x0007e000
+#define NPORT_STAT_BFIRQ  0x00080000
+#define NPORT_STAT_GFIRQ  0x00100000
+
+	npireg_t ustat;
+	npireg_t dreset;
+};
+
+struct newport_regs {
+	struct newport_rexregs set;
+	unsigned long _unused0[0x16e];
+	struct newport_rexregs go;
+	unsigned long _unused1[0x22e];
+	struct newport_cregs cset;
+	unsigned long _unused2[0x1ef];
+	struct newport_cregs cgo;
+};
+extern struct newport_regs *npregs;
+
+
+typedef struct {
+	unsigned int drawmode1;
+	unsigned int drawmode0;
+	unsigned int lsmode;   
+	unsigned int lspattern;
+	unsigned int lspatsave;
+	unsigned int zpattern; 
+	unsigned int colorback;
+	unsigned int colorvram;
+	unsigned int alpharef; 
+	unsigned int smask0x;  
+	unsigned int smask0y;  
+	unsigned int _xstart;  
+	unsigned int _ystart;  
+	unsigned int _xend;    
+	unsigned int _yend;    
+	unsigned int xsave;    
+	unsigned int xymove;   
+	unsigned int bresd;    
+	unsigned int bress1;   
+	unsigned int bresoctinc1;
+	unsigned int bresrndinc2;
+	unsigned int brese1;     
+	unsigned int bress2;     
+	
+	unsigned int aweight0;    
+	unsigned int aweight1;    
+	unsigned int colorred;    
+	unsigned int coloralpha;  
+	unsigned int colorgrn;    
+	unsigned int colorblue;   
+	unsigned int slopered;    
+	unsigned int slopealpha;  
+	unsigned int slopegrn;    
+	unsigned int slopeblue;   
+	unsigned int wrmask;      
+	unsigned int hostrw0;     
+	unsigned int hostrw1;     
+	
+        /* configregs */
+	
+	unsigned int smask1x;    
+	unsigned int smask1y;    
+	unsigned int smask2x;    
+	unsigned int smask2y;    
+	unsigned int smask3x;    
+	unsigned int smask3y;    
+	unsigned int smask4x;    
+	unsigned int smask4y;    
+	unsigned int topscan;    
+	unsigned int xywin;      
+	unsigned int clipmode;   
+	unsigned int config;     
+	
+        /* dcb registers */
+	unsigned int dcbmode;   
+	unsigned int dcbdata0;  
+	unsigned int dcbdata1;
+} newport_ctx;
+
+/* Reading/writing VC2 registers. */
+#define VC2_REGADDR_INDEX      0x00000000
+#define VC2_REGADDR_IREG       0x00000010
+#define VC2_REGADDR_RAM        0x00000030
+#define VC2_PROTOCOL           (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
+
+#define VC2_VLINET_ADDR        0x000
+#define VC2_VFRAMET_ADDR       0x400
+#define VC2_CGLYPH_ADDR        0x500
+
+/* Now the Indexed registers of the VC2. */
+#define VC2_IREG_VENTRY        0x00
+#define VC2_IREG_CENTRY        0x01
+#define VC2_IREG_CURSX         0x02
+#define VC2_IREG_CURSY         0x03
+#define VC2_IREG_CCURSX        0x04
+#define VC2_IREG_DENTRY        0x05
+#define VC2_IREG_SLEN          0x06
+#define VC2_IREG_RADDR         0x07
+#define VC2_IREG_VFPTR         0x08
+#define VC2_IREG_VLSPTR        0x09
+#define VC2_IREG_VLIR          0x0a
+#define VC2_IREG_VLCTR         0x0b
+#define VC2_IREG_CTPTR         0x0c
+#define VC2_IREG_WCURSY        0x0d
+#define VC2_IREG_DFPTR         0x0e
+#define VC2_IREG_DLTPTR        0x0f
+#define VC2_IREG_CONTROL       0x10
+#define VC2_IREG_CONFIG        0x20
+
+extern inline void newport_vc2_set(struct newport_regs *regs, unsigned char vc2ireg,
+				   unsigned short val)
+{
+	regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 |
+			   NPORT_DMODE_ECINC | VC2_PROTOCOL);
+	regs->set.dcbdata0.all = (vc2ireg << 24) | (val << 8);
+}
+
+extern inline unsigned short newport_vc2_get(struct newport_regs *regs,
+					     unsigned char vc2ireg)
+{
+	regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 |
+			   NPORT_DMODE_ECINC | VC2_PROTOCOL);
+	regs->set.dcbdata0.bytes.b3 = vc2ireg;
+	regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 |
+			   NPORT_DMODE_ECINC | VC2_PROTOCOL);
+	return regs->set.dcbdata0.hwords.s1;
+}
+
+/* VC2 Control register bits */
+#define VC2_CTRL_EVIRQ     0x0001
+#define VC2_CTRL_EDISP     0x0002
+#define VC2_CTRL_EVIDEO    0x0004
+#define VC2_CTRL_EDIDS     0x0008
+#define VC2_CTRL_ECURS     0x0010
+#define VC2_CTRL_EGSYNC    0x0020
+#define VC2_CTRL_EILACE    0x0040
+#define VC2_CTRL_ECDISP    0x0080
+#define VC2_CTRL_ECCURS    0x0100
+#define VC2_CTRL_ECG64     0x0200
+#define VC2_CTRL_GLSEL     0x0400
+
+/* Controlling the color map on NEWPORT. */
+#define NCMAP_REGADDR_AREG   0x00000000
+#define NCMAP_REGADDR_ALO    0x00000000
+#define NCMAP_REGADDR_AHI    0x00000010
+#define NCMAP_REGADDR_PBUF   0x00000020
+#define NCMAP_REGADDR_CREG   0x00000030
+#define NCMAP_REGADDR_SREG   0x00000040
+#define NCMAP_REGADDR_RREG   0x00000060
+#define NCMAP_PROTOCOL       (0x00008000 | 0x00040000 | 0x00800000)
+
+static inline void newport_cmap_setaddr(struct newport_regs *regs,
+					unsigned short addr)
+{
+	regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
+			   NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC |
+			   NCMAP_REGADDR_AREG | NPORT_DMODE_W2);
+	regs->set.dcbdata0.hwords.s1 = addr;
+	regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
+			   NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);
+}
+
+static inline void newport_cmap_setrgb(struct newport_regs *regs,
+				       unsigned char red,
+				       unsigned char green,
+				       unsigned char blue)
+{
+	regs->set.dcbdata0.all =
+		(red << 24) |
+		(green << 16) |
+		(blue << 8);
+}
+
+/* Miscellaneous NEWPORT routines. */
+#define BUSY_TIMEOUT 100000
+static inline int newport_wait(void)
+{
+	int i = 0;
+
+	while(i < BUSY_TIMEOUT)
+		if(!(npregs->cset.stat & NPORT_STAT_GBUSY))
+			break;
+	if(i == BUSY_TIMEOUT)
+		return 1;
+	return 0;
+}
+
+static inline int newport_bfwait(void)
+{
+	int i = 0;
+
+	while(i < BUSY_TIMEOUT)
+		if(!(npregs->cset.stat & NPORT_STAT_BBUSY))
+			break;
+	if(i == BUSY_TIMEOUT)
+		return 1;
+	return 0;
+}
+
+/* newport.c and cons_newport.c routines */
+extern struct graphics_ops *newport_probe (int, const char **);
+
+void newport_save    (void *);
+void newport_restore (void *);
+void newport_reset   (void);
+int  newport_ioctl   (int card, int cmd, unsigned long arg);
+
+/*
+ * DCBMODE register defines:
+ */
+
+/* Widht of the data being transfered for each DCBDATA[01] word */
+#define DCB_DATAWIDTH_4 0x0
+#define DCB_DATAWIDTH_1 0x1
+#define DCB_DATAWIDTH_2 0x2
+#define DCB_DATAWIDTH_3 0x3
+
+/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */
+#define DCB_ENDATAPACK   (1 << 2)
+
+/* Enables DCBCRS auto increment after each DCB transfer */
+#define DCB_ENCRSINC     (1 << 3)
+
+/* shift for accessing the control register select address (DBCCRS, 3 bits) */
+#define DCB_CRS_SHIFT    4
+
+/* DCBADDR (4 bits): display bus slave address */
+#define DCB_ADDR_SHIFT   7
+#define DCB_VC2          (0 <<  DCB_ADDR_SHIFT)
+#define DCB_CMAP_ALL     (1 <<  DCB_ADDR_SHIFT)
+#define DCB_CMAP0        (2 <<  DCB_ADDR_SHIFT)
+#define DCB_CMAP1        (3 <<  DCB_ADDR_SHIFT)
+#define DCB_XMAP_ALL     (4 <<  DCB_ADDR_SHIFT)
+#define DCB_XMAP0        (5 <<  DCB_ADDR_SHIFT)
+#define DCB_XMAP1        (6 <<  DCB_ADDR_SHIFT)
+#define DCB_BT445        (7 <<  DCB_ADDR_SHIFT)
+#define DCB_VCC1         (8 <<  DCB_ADDR_SHIFT)
+#define DCB_VAB1         (9 <<  DCB_ADDR_SHIFT)
+#define DCB_LG3_BDVERS0  (10 << DCB_ADDR_SHIFT)
+#define DCB_LG3_ICS1562  (11 << DCB_ADDR_SHIFT)
+#define DCB_RESERVED     (15 << DCB_ADDR_SHIFT)
+
+/* DCB protocol ack types */
+#define DCB_ENSYNCACK    (1 << 11)
+#define DCB_ENASYNCACK   (1 << 12)
+
+#define DCB_CSWIDTH_SHIFT 13
+#define DCB_CSHOLD_SHIFT  18
+#define DCB_CSSETUP_SHIFT 23
+
+/* XMAP9 specific defines */
+/*   XMAP9 -- registers as seen on the DCBMODE register*/
+#   define XM9_CRS_CONFIG            (0 << DCB_CRS_SHIFT)
+#       define XM9_PUPMODE           (1 << 0)
+#       define XM9_ODD_PIXEL         (1 << 1)
+#       define XM9_8_BITPLANES       (1 << 2)
+#       define XM9_SLOW_DCB          (1 << 3)
+#       define XM9_VIDEO_RGBMAP_MASK (3 << 4)
+#       define XM9_EXPRESS_VIDEO     (1 << 6)
+#       define XM9_VIDEO_OPTION      (1 << 7)
+#   define XM9_CRS_REVISION          (1 << DCB_CRS_SHIFT)
+#   define XM9_CRS_FIFO_AVAIL        (2 << DCB_CRS_SHIFT)
+#       define XM9_FIFO_0_AVAIL      0
+#       define XM9_FIFO_1_AVAIL      1
+#       define XM9_FIFO_2_AVAIL      3
+#       define XM9_FIFO_3_AVAIL      2
+#       define XM9_FIFO_FULL         XM9_FIFO_0_AVAIL
+#       define XM9_FIFO_EMPTY        XM9_FIFO_3_AVAIL
+#   define XM9_CRS_CURS_CMAP_MSB     (3 << DCB_CRS_SHIFT)
+#   define XM9_CRS_PUP_CMAP_MSB      (4 << DCB_CRS_SHIFT)
+#   define XM9_CRS_MODE_REG_DATA     (5 << DCB_CRS_SHIFT)
+#   define XM9_CRS_MODE_REG_INDEX    (7 << DCB_CRS_SHIFT)
+
+
+#define DCB_CYCLES(setup,hold,width)                \
+                  ((hold << DCB_CSHOLD_SHIFT)  |    \
+		   (setup << DCB_CSSETUP_SHIFT)|    \
+		   (width << DCB_CSWIDTH_SHIFT))
+
+#define W_DCB_XMAP9_PROTOCOL       DCB_CYCLES (2, 1, 0)
+#define WSLOW_DCB_XMAP9_PROTOCOL   DCB_CYCLES (5, 5, 0)
+#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
+#define R_DCB_XMAP9_PROTOCOL       DCB_CYCLES (2, 1, 3)
+
+static inline void
+xmap9FIFOWait (struct newport_regs *rex)
+{
+        rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |
+		DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;
+        newport_bfwait ();
+	
+        while ((rex->set.dcbdata0.bytes.b3 & 3) != XM9_FIFO_EMPTY)
+		;
+}
+
+static inline void
+xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq)
+{
+        if (cfreq > 119)
+            rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
+                        DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;
+        else if (cfreq > 59)
+            rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
+		    DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;    
+        else
+            rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
+                        DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; 
+        rex->set.dcbdata0.all = ((modereg) << 24) | (data24 & 0xffffff);
+}
+
+#endif /* !(_SGI_NEWPORT_H) */
+
diff --git a/include/asm-mips/offset.h b/include/asm-mips/offset.h
index 5f89c2852..6f7a5b019 100644
--- a/include/asm-mips/offset.h
+++ b/include/asm-mips/offset.h
@@ -46,35 +46,36 @@
 
 /* MIPS task_struct offsets. */
 #define TASK_STATE         0
-#define TASK_COUNTER       52
-#define TASK_PRIORITY      56
 #define TASK_FLAGS         4
 #define TASK_SIGPENDING    8
-#define TASK_MM            936
+#define TASK_NEED_RESCHED  20
+#define TASK_COUNTER       24
+#define TASK_PRIORITY      28
+#define TASK_MM            928
 
 /* MIPS specific thread_struct offsets. */
-#define THREAD_REG16   576
-#define THREAD_REG17   580
-#define THREAD_REG18   584
-#define THREAD_REG19   588
-#define THREAD_REG20   592
-#define THREAD_REG21   596
-#define THREAD_REG22   600
-#define THREAD_REG23   604
-#define THREAD_REG29   608
-#define THREAD_REG30   612
-#define THREAD_REG31   616
-#define THREAD_STATUS  620
-#define THREAD_FPU     624
-#define THREAD_BVADDR  888
-#define THREAD_BUADDR  892
-#define THREAD_ECODE   896
-#define THREAD_TRAPNO  900
-#define THREAD_PGDIR   904
-#define THREAD_MFLAGS  908
-#define THREAD_CURDS   912
-#define THREAD_TRAMP   916
-#define THREAD_OLDCTX  920
+#define THREAD_REG16   568
+#define THREAD_REG17   572
+#define THREAD_REG18   576
+#define THREAD_REG19   580
+#define THREAD_REG20   584
+#define THREAD_REG21   588
+#define THREAD_REG22   592
+#define THREAD_REG23   596
+#define THREAD_REG29   600
+#define THREAD_REG30   604
+#define THREAD_REG31   608
+#define THREAD_STATUS  612
+#define THREAD_FPU     616
+#define THREAD_BVADDR  880
+#define THREAD_BUADDR  884
+#define THREAD_ECODE   888
+#define THREAD_TRAPNO  892
+#define THREAD_PGDIR   896
+#define THREAD_MFLAGS  900
+#define THREAD_CURDS   904
+#define THREAD_TRAMP   908
+#define THREAD_OLDCTX  912
 
 /* Linux mm_struct offsets. */
 #define MM_COUNT      12
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 1bde35833..36c0a73e2 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -1,4 +1,4 @@
-/* $Id: page.h,v 1.2 1998/06/30 00:23:11 ralf Exp $
+/* $Id: page.h,v 1.3 1998/07/13 23:29:09 tsbogend Exp $
  *
  * Definitions for page handling
  *
@@ -20,7 +20,7 @@
 
 #define STRICT_MM_TYPECHECKS
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 #ifdef __SMP__
 #define ULOCK_DECLARE extern spinlock_t user_page_lock;
@@ -117,7 +117,7 @@ typedef unsigned long pgprot_t;
 
 #endif /* !defined (STRICT_MM_TYPECHECKS) */
 
-#endif /* __LANGUAGE_ASSEMBLY__ */
+#endif /* _LANGUAGE_ASSEMBLY */
 
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)	(((addr)+PAGE_SIZE-1)&PAGE_MASK)
@@ -129,7 +129,8 @@ typedef unsigned long pgprot_t;
 #define PAGE_OFFSET	0x80000000UL
 #define __pa(x)		((unsigned long) (x) - PAGE_OFFSET)
 #define __va(x)		((void *)((unsigned long) (x) + PAGE_OFFSET))
-#define MAP_NR(addr)	(__pa(addr) >> PAGE_SHIFT)
+#define MAP_MASK        0x1fffffffUL
+#define MAP_NR(addr)	((((unsigned long)(addr)) & MAP_MASK) >> PAGE_SHIFT)
 
 #endif /* defined (__KERNEL__) */
 
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index d2ff867f2..40781ed92 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -1,12 +1,10 @@
-/* $Id: pci.h,v 1.2 1997/12/01 18:00:40 ralf Exp $
+/* $Id: pci.h,v 1.3 1998/05/07 14:18:11 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Declarations for the MIPS specific implementation of the PCI BIOS32 services.
- *
- * Copyright (C) 1997, 1998 Ralf Baechle
  */
 #ifndef __ASM_MIPS_PCI_H
 #define __ASM_MIPS_PCI_H
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index e84692a40..dccd199ad 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -1,4 +1,4 @@
-/* $Id: pgtable.h,v 1.11 1998/07/14 09:31:48 ralf Exp $
+/* $Id: pgtable.h,v 1.14 1998/07/16 19:10:04 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,7 @@
 #include <asm/addrspace.h>
 #include <asm/mipsconfig.h>
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 #include <linux/linkage.h>
 #include <asm/cachectl.h>
@@ -61,7 +61,7 @@ extern void (*add_wired_entry)(unsigned long entrylo0, unsigned long entrylo1,
  * works even with the cache aliasing problem the R4k and above have.
  */
 
-#endif /* !defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 /* PMD_SHIFT determines the size of the area a second-level page table can map */
 #define PMD_SHIFT	22
@@ -79,9 +79,11 @@ extern void (*add_wired_entry)(unsigned long entrylo0, unsigned long entrylo1,
 #define PTRS_PER_PTE	1024
 #define PTRS_PER_PMD	1
 #define PTRS_PER_PGD	1024
+#define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
 
 #define VMALLOC_START     KSEG2
 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       KSEG3
 
 /* Note that we shift the lower 32bits of each EntryLo[01] entry
  * 6 bits to the left. That way we can convert the PFN into the
@@ -166,7 +168,7 @@ extern void (*add_wired_entry)(unsigned long entrylo0, unsigned long entrylo1,
 #define __S110	PAGE_SHARED
 #define __S111	PAGE_SHARED
 
-#if !defined (__LANGUAGE_ASSEMBLY__)
+#if !defined (_LANGUAGE_ASSEMBLY)
 
 /*
  * BAD_PAGETABLE is used when we need a bogus page-table, while
@@ -354,7 +356,7 @@ extern inline pte_t mk_pte(unsigned long page, pgprot_t pgprot)
 
 extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 {
-	return __pte(physpage | pgprot_val(pgprot));
+	return __pte((physpage - PAGE_OFFSET) | pgprot_val(pgprot));
 }
 
 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
@@ -385,77 +387,141 @@ extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
 }
 
 /*
+ * Initialize new page directory with pointers to invalid ptes
+ */
+extern void (*pgd_init)(unsigned long page);
+
+/*
  * Allocate and free page tables. The xxx_kernel() versions are
  * used to allocate a kernel page table - this turns on ASN bits
  * if any.
  */
-extern inline void pte_free_kernel(pte_t *pte)
+
+#define pgd_quicklist (current_cpu_data.pgd_quick)
+#define pmd_quicklist ((unsigned long *)0)
+#define pte_quicklist (current_cpu_data.pte_quick)
+#define pgtable_cache_size (current_cpu_data.pgtable_cache_sz)
+
+extern __inline__ pgd_t *get_pgd_slow(void)
 {
-	free_page((unsigned long) pte);
+	pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL), *init;
+
+	if (ret) {
+		init = pgd_offset(&init_mm, 0);
+		pgd_init((unsigned long)ret);
+		memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+	}
+	return ret;
 }
 
-extern const char bad_pmd_string[];
+extern __inline__ pgd_t *get_pgd_fast(void)
+{
+	unsigned long *ret;
+
+	if((ret = pgd_quicklist) != NULL) {
+		pgd_quicklist = (unsigned long *)(*ret);
+		ret[0] = ret[1];
+		pgtable_cache_size--;
+	} else
+		ret = (unsigned long *)get_pgd_slow();
+	return (pgd_t *)ret;
+}
 
-extern inline pte_t *pte_alloc_kernel(pmd_t *pmd, unsigned long address)
+extern __inline__ void free_pgd_fast(pgd_t *pgd)
 {
-	address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
-	if (pmd_none(*pmd)) {
-		pte_t *page = (pte_t *) get_free_page(GFP_KERNEL);
-		if (pmd_none(*pmd)) {
-			if (page) {
-				pmd_set(pmd, page);
-				return page + address;
-			}
-			pmd_set(pmd, (pte_t *) BAD_PAGETABLE);
-			return NULL;
-		}
-		free_page((unsigned long) page);
-	}
-	if (pmd_bad(*pmd)) {
-		printk(bad_pmd_string, pmd_val(*pmd));
-		pmd_set(pmd, (pte_t *) BAD_PAGETABLE);
-		return NULL;
+	*(unsigned long *)pgd = (unsigned long) pgd_quicklist;
+	pgd_quicklist = (unsigned long *) pgd;
+	pgtable_cache_size++;
+}
+
+extern __inline__ void free_pgd_slow(pgd_t *pgd)
+{
+	free_page((unsigned long)pgd);
+}
+
+extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
+extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long address_preadjusted);
+
+extern __inline__ pte_t *get_pte_fast(void)
+{
+	unsigned long *ret;
+
+	if((ret = (unsigned long *)pte_quicklist) != NULL) {
+		pte_quicklist = (unsigned long *)(*ret);
+		ret[0] = ret[1];
+		pgtable_cache_size--;
 	}
-	return (pte_t *) pmd_page(*pmd) + address;
+	return (pte_t *)ret;
 }
 
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- */
-extern inline void pmd_free_kernel(pmd_t *pmd)
+extern __inline__ void free_pte_fast(pte_t *pte)
 {
-	pmd_val(*pmd) = ((unsigned long) invalid_pte_table);
+	*(unsigned long *)pte = (unsigned long) pte_quicklist;
+	pte_quicklist = (unsigned long *) pte;
+	pgtable_cache_size++;
 }
 
-extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address)
+extern __inline__ void free_pte_slow(pte_t *pte)
 {
-	return (pmd_t *) pgd;
+	free_page((unsigned long)pte);
 }
 
-extern inline void pte_free(pte_t *pte)
+/* We don't use pmd cache, so these are dummy routines */
+extern __inline__ pmd_t *get_pmd_fast(void)
 {
-	free_page((unsigned long) pte);
+	return (pmd_t *)0;
 }
 
-extern inline pte_t *pte_alloc(pmd_t *pmd, unsigned long address)
+extern __inline__ void free_pmd_fast(pmd_t *pmd)
+{
+}
+
+extern __inline__ void free_pmd_slow(pmd_t *pmd)
+{
+}
+
+extern void __bad_pte(pmd_t *pmd);
+extern void __bad_pte_kernel(pmd_t *pmd);
+
+#define pte_free_kernel(pte)    free_pte_fast(pte)
+#define pte_free(pte)           free_pte_fast(pte)
+#define pgd_free(pgd)           free_pgd_fast(pgd)
+#define pgd_alloc()             get_pgd_fast()
+
+extern inline pte_t * pte_alloc_kernel(pmd_t * pmd, unsigned long address)
+{
+	address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+
+	if (pmd_none(*pmd)) {
+		pte_t *page = get_pte_fast();
+		if (page) {
+			pmd_val(*pmd) = (unsigned long)page;
+			return page + address;
+		}
+		return get_pte_kernel_slow(pmd, address);
+	}
+	if (pmd_bad(*pmd)) {
+		__bad_pte_kernel(pmd);
+		return NULL;
+	}
+	return (pte_t *) pmd_page(*pmd) + address;
+}
+
+extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
 {
 	address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+
 	if (pmd_none(*pmd)) {
-		pte_t *page = (pte_t *) get_free_page(GFP_KERNEL);
-		if (pmd_none(*pmd)) {
-			if (page) {
-				pmd_set(pmd, page);
-				return page + address;
-			}
-			pmd_set(pmd, (pte_t *) BAD_PAGETABLE);
-			return NULL;
+		pte_t *page = get_pte_fast();
+		if (page) {
+			pmd_val(*pmd) = (unsigned long)page;
+			return page + address;
 		}
-		free_page((unsigned long) page);
+		return get_pte_slow(pmd, address);
 	}
 	if (pmd_bad(*pmd)) {
-		printk(bad_pmd_string, pmd_val(*pmd));
-		pmd_set(pmd, (pte_t *) BAD_PAGETABLE);
+		__bad_pte(pmd);
 		return NULL;
 	}
 	return (pte_t *) pmd_page(*pmd) + address;
@@ -465,36 +531,45 @@ extern inline pte_t *pte_alloc(pmd_t *pmd, unsigned long address)
  * allocating and freeing a pmd is trivial: the 1-entry pmd is
  * inside the pgd, so has no extra memory associated with it.
  */
-extern inline void pmd_free(pmd_t *pmd)
+extern inline void pmd_free(pmd_t * pmd)
 {
-	pmd_val(*pmd) = ((unsigned long) invalid_pte_table);
 }
 
-extern inline pmd_t *pmd_alloc(pgd_t *pgd, unsigned long address)
+extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
 {
 	return (pmd_t *) pgd;
 }
 
-extern inline void pgd_free(pgd_t *pgd)
-{
-	free_page((unsigned long) pgd);
-}
+#define pmd_free_kernel		pmd_free
+#define pmd_alloc_kernel	pmd_alloc
 
-/*
- * Initialize new page directory with pointers to invalid ptes
- */
-extern void (*pgd_init)(unsigned long page);
+extern int do_check_pgt_cache(int, int);
 
-extern inline pgd_t *pgd_alloc(void)
+extern inline void set_pgdir(unsigned long address, pgd_t entry)
 {
-	unsigned long page;
-
-	if(!(page = __get_free_page(GFP_KERNEL)))
-		return NULL;
-
-	pgd_init(page);
-
-	return (pgd_t *) page;
+	struct task_struct * p;
+	pgd_t *pgd;
+#ifdef __SMP__
+	int i;
+#endif	
+        
+	read_lock(&tasklist_lock);
+	for_each_task(p) {
+		if (!p->mm)
+			continue;
+		*pgd_offset(p->mm,address) = entry;
+	}
+	read_unlock(&tasklist_lock);
+#ifndef __SMP__
+	for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+		pgd[address >> PGDIR_SHIFT] = entry;
+#else
+	/* To pgd_alloc/pgd_free, one holds master kernel lock and so does our
+	   callee, so we can modify pgd caches of other CPUs as well. -jj */
+	for (i = 0; i < NR_CPUS; i++)
+		for (pgd = (pgd_t *)cpu_data[i].pgd_quick; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+			pgd[address >> PGDIR_SHIFT] = entry;
+#endif
 }
 
 extern pgd_t swapper_pg_dir[1024];
@@ -512,6 +587,9 @@ extern void (*update_mmu_cache)(struct vm_area_struct *vma,
 #define module_map      vmalloc
 #define module_unmap    vfree
 
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define PageSkip(page)		(0)
+
 /* TLB operations. */
 extern inline void tlb_probe(void)
 {
@@ -781,6 +859,6 @@ extern inline void set_context(unsigned long val)
 		: : "r" (val));
 }
 
-#endif /* !defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #endif /* __ASM_MIPS_PGTABLE_H */
diff --git a/include/asm-mips/pica.h b/include/asm-mips/pica.h
deleted file mode 100644
index a1056f845..000000000
--- a/include/asm-mips/pica.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Hardware info about Acer PICA 61 and similar
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995 by Andreas Busse and Ralf Baechle
- */
-#ifndef __ASM_MIPS_PICA_H 
-#define __ASM_MIPS_PICA_H 
-
-/*
- * The addresses below are virtual address. The mappings are
- * created on startup via wired entries in the tlb. The Mips
- * Magnum R3000 and R4000 machines are similar in many aspects,
- * but many hardware register are accessible at 0xb9000000 in
- * instead of 0xe0000000.
- */
-
-/*
- * Revision numbers in PICA_ASIC_REVISION
- *
- * 0xf0000000 - Rev1
- * 0xf0000001 - Rev2
- * 0xf0000002 - Rev3
- */
-#define PICA_ASIC_REVISION      0xe0000008
-
-/*
- * The segments of the seven segment LED are mapped
- * to the control bits as follows:
- *
- *         (7)
- *      ---------
- *      |       |
- *  (2) |       | (6)
- *      |  (1)  |
- *      ---------
- *      |       |
- *  (3) |       | (5)
- *      |  (4)  |
- *      --------- . (0)
- */
-#define PICA_LED                0xe000f000
-
-/*
- * Some characters for the LED control registers
- * The original Mips machines seem to have a LED display
- * with integrated decoder while the Acer machines can
- * control each of the seven segments and the dot independently.
- * It only a toy, anyway...
- */
-#define LED_DOT                 0x01
-#define LED_SPACE               0x00
-#define LED_0                   0xfc
-#define LED_1                   0x60
-#define LED_2                   0xda
-#define LED_3                   0xf2
-#define LED_4                   0x66
-#define LED_5                   0xb6
-#define LED_6                   0xbe
-#define LED_7                   0xe0
-#define LED_8                   0xfe
-#define LED_9                   0xf6
-#define LED_A                   0xee
-#define LED_b                   0x3e
-#define LED_C                   0x9c
-#define LED_d                   0x7a
-#define LED_E                   0x9e
-#define LED_F                   0x8e
-
-#ifndef __LANGUAGE_ASSEMBLY__
-
-extern __inline__ void pica_set_led(unsigned int bits)
-{
-	volatile unsigned int *led_register = (unsigned int *) PICA_LED;
-
-	*led_register = bits;
-}
-
-#endif
-
-/*
- * i8042 keyboard controller for PICA chipset.
- * This address is just a guess and seems to differ
- * from the other mips machines...
- */
-#define PICA_KEYBOARD_ADDRESS   0xe0005000
-#define PICA_KEYBOARD_DATA      0xe0005000
-#define PICA_KEYBOARD_COMMAND   0xe0005001
-
-#ifndef __LANGUAGE_ASSEMBLY__
-
-typedef struct {
-	unsigned char data;
-	unsigned char command;
-} pica_keyboard_hardware;
-
-typedef struct {
-	unsigned char pad0[3];
-	unsigned char data;
-	unsigned char pad1[3];
-	unsigned char command;
-} mips_keyboard_hardware;
-
-/*
- * For now
- */
-#define keyboard_hardware       pica_keyboard_hardware
-
-#endif
-
-/*
- * i8042 keyboard controller for most other Mips machines.
- */
-#define MIPS_KEYBOARD_ADDRESS   0xb9005000
-#define MIPS_KEYBOARD_DATA      0xb9005003
-#define MIPS_KEYBOARD_COMMAND   0xb9005007
-
-#ifndef __LANGUAGE_ASSEMBLY__
-
-#endif
-
-/*
- * PICA timer registers and interrupt no.
- * Note that the hardware timer interrupt is actually on
- * cpu level 6, but to keep compatibility with PC stuff
- * it is remapped to vector 0. See arch/mips/kernel/entry.S.
- */
-#define PICA_TIMER_INTERVAL     0xe0000228
-#define PICA_TIMER_REGISTER     0xe0000230
-
-/*
- * DRAM configuration register
- */
-#ifndef __LANGUAGE_ASSEMBLY__
-#ifdef __MIPSEL__
-typedef struct {
-	unsigned int bank2 : 3;
-	unsigned int bank1 : 3;
-	unsigned int mem_bus_width : 1;
-	unsigned int reserved2 : 1;
-	unsigned int page_mode : 1;
-	unsigned int reserved1 : 23;
-} dram_configuration;
-#else /* defined (__MIPSEB__) */
-typedef struct {
-	unsigned int reserved1 : 23;
-	unsigned int page_mode : 1;
-	unsigned int reserved2 : 1;
-	unsigned int mem_bus_width : 1;
-	unsigned int bank1 : 3;
-	unsigned int bank2 : 3;
-} dram_configuration;
-#endif
-#endif /* __LANGUAGE_ASSEMBLY__ */
-
-#define PICA_DRAM_CONFIG        0xe00fffe0
-
-/*
- * PICA interrupt control registers
- */
-#define PICA_IO_IRQ_SOURCE      0xe0100000
-#define PICA_IO_IRQ_ENABLE      0xe0100002
-
-/*
- * Pica interrupt enable bits
- */
-#define PIE_PARALLEL            (1<<0)
-#define PIE_FLOPPY              (1<<1)
-#define PIE_SOUND               (1<<2)
-#define PIE_VIDEO               (1<<3)
-#define PIE_ETHERNET            (1<<4)
-#define PIE_SCSI                (1<<5)
-#define PIE_KEYBOARD            (1<<6)
-#define PIE_MOUSE               (1<<7)
-#define PIE_SERIAL1             (1<<8)
-#define PIE_SERIAL2             (1<<9)
-
-#endif /* __ASM_MIPS_PICA_H */
diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h
index 6ae7982d1..057a44df8 100644
--- a/include/asm-mips/posix_types.h
+++ b/include/asm-mips/posix_types.h
@@ -1,11 +1,10 @@
-/*
- * POSIX types
+/* $Id: posix_types.h,v 1.5 1998/08/17 13:59:34 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996 by Ralf Baechle
+ * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
  */
 #ifndef __ARCH_MIPS_POSIX_TYPES_H
 #define __ARCH_MIPS_POSIX_TYPES_H
@@ -46,6 +45,8 @@ typedef struct {
         long    val[2];
 } __kernel_fsid_t;
 
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
 #undef __FD_SET
 static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
 {
@@ -114,4 +115,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
 	}
 }
 
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
 #endif /* __ARCH_MIPS_POSIX_TYPES_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 63d721720..614c7aa64 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -1,28 +1,46 @@
-/*
- * include/asm-mips/processor.h
+/* $Id: processor.h,v 1.17 1998/08/18 20:46:41 ralf Exp $
  *
- * Copyright (C) 1994  Waldorf Electronics
- * written by Ralf Baechle
- * Modified further for R[236]000 compatibility by Paul M. Antoine
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- * $Id: processor.h,v 1.10 1998/05/04 09:13:01 ralf Exp $
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998 Ralf Baechle
+ * Modified further for R[236]000 compatibility by Paul M. Antoine
  */
 #ifndef __ASM_MIPS_PROCESSOR_H
 #define __ASM_MIPS_PROCESSOR_H
 
-#if !defined (__LANGUAGE_ASSEMBLY__)
+#if !defined (_LANGUAGE_ASSEMBLY)
 #include <asm/cachectl.h>
 #include <asm/mipsregs.h>
 #include <asm/reg.h>
 #include <asm/system.h>
 
+struct mips_cpuinfo {
+	unsigned long *pgd_quick;
+	unsigned long *pte_quick;
+	unsigned long pgtable_cache_sz;
+};
+
 /*
  * System setup and hardware flags..
+ * XXX: Should go into mips_cpuinfo.
  */
 extern char wait_available;		/* only available on R4[26]00 */
 extern char cyclecounter_available;	/* only available from R4000 upwards. */
 extern char dedicated_iv_available;	/* some embedded MIPS like Nevada */
 
+extern struct mips_cpuinfo boot_cpu_data;
+
+#ifdef __SMP__
+extern struct mips_cpuinfo cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data &boot_cpu_data
+#define current_cpu_data boot_cpu_data
+#endif
+
 /*
  * Bus types (default is ISA, but people can check others with these..)
  * MCA_bus hardcoded to 0 for now.
@@ -40,6 +58,9 @@ extern int EISA_bus;
 #define wp_works_ok 1
 #define wp_works_ok__is_a_macro /* for versions in ksyms.c */
 
+/* Lazy FPU handling on uni-processor */
+extern struct task_struct *last_task_used_math;
+
 /*
  * User space process size: 2GB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.  TASK_SIZE
@@ -114,7 +135,7 @@ struct thread_struct {
 	unsigned long irix_oldctx;
 };
 
-#endif /* !defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #define INIT_MMAP { &init_mm, KSEG0, KSEG1, PAGE_SHARED, \
                     VM_READ | VM_WRITE | VM_EXEC, NULL, &init_mm.mmap }
@@ -147,7 +168,7 @@ struct thread_struct {
 
 #define KERNEL_STACK_SIZE 8192
 
-#if !defined (__LANGUAGE_ASSEMBLY__)
+#if !defined (_LANGUAGE_ASSEMBLY)
 
 /* Free all resources held by a thread. */
 extern void release_thread(struct task_struct *);
@@ -188,7 +209,7 @@ extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long
 #define init_task	(init_task_union.task)
 #define init_stack	(init_task_union.stack)
 
-#endif /* !defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 #endif /* __KERNEL__ */
 
 /*
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index faf916974..7d4f6ecfe 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -15,14 +15,9 @@
  */
 #define BASE_BAUD ( 1843200 / 16 )
 
-#ifndef CONFIG_OLIVETTI_M700
 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
    exactly which ones ... XXX */
 #define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
-#else
-/* but the M700 isn't such a strange beast */
-#define JAZZ_BASE_BAUD BASE_BAUD
-#endif
 
 /* Standard COM flags (except for COM4, because of the 8514 problem) */
 #ifdef CONFIG_SERIAL_DETECT_IRQ
diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h
index 72d25346a..06c94226f 100644
--- a/include/asm-mips/sgidefs.h
+++ b/include/asm-mips/sgidefs.h
@@ -45,7 +45,7 @@
 #endif
 
 /*
- * Now lets try our best to supply some reasonable default values for
+ * Now let's try our best to supply some reasonable default values for
  * whatever defines GCC didn't supply.  This cannot be done correct for
  * all possible combinations of options, so be careful with your options
  * to GCC.  Best bet is to keep your fingers off the a.out GCC and use
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index d4e6f4145..2cf7fd22e 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -43,6 +43,7 @@ typedef struct siginfo {
 		/* SIGCHLD */
 		struct {
 			pid_t _pid;		/* which child */
+			uid_t _uid;		/* sender's uid */
 			int _status;		/* exit code */
 			clock_t _utime;
 			clock_t _stime;
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 0f5988610..e195bc6b2 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -1,13 +1,10 @@
-/*
- * Linux/MIPS specific definitions for signals.
+/* $Id: signal.h,v 1.4 1998/08/18 20:46:42 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
- *
- * $Id: signal.h,v 1.3 1997/12/14 18:57:19 ralf Exp $
+ * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
  */
 #ifndef __ASM_MIPS_SIGNAL_H
 #define __ASM_MIPS_SIGNAL_H
@@ -66,7 +63,7 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 /*
  * SA_FLAGS values:
  *
- * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
+ * SA_ONSTACK indicates that a registered stack_t will be used.
  * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
  * SA_RESTART flag to get restarting signals (which were the default long ago)
  * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
@@ -85,8 +82,17 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define SA_NOCLDWAIT	0x00010000	/* Not supported yet */
 #define SA_NOCLDSTOP	0x00020000
 
-#define SA_NOMASK	SA_NODEFER	/* DANGER: was 0x02000000 */
-#define SA_ONESHOT	SA_RESETHAND	/* DANGER: was 0x04000000 */
+#define SA_NOMASK	SA_NODEFER
+#define SA_ONESHOT	SA_RESETHAND
+
+/* 
+ * sigaltstack controls
+ */
+#define SS_ONSTACK     1
+#define SS_DISABLE     2
+
+#define MINSIGSTKSZ    2048
+#define SIGSTKSZ       8192
 
 #ifdef __KERNEL__
 /*
@@ -130,6 +136,13 @@ struct k_sigaction {
 	void (*ka_restorer)(void);
 };
 
+/* IRIX compatible stack_t  */
+typedef struct sigaltstack {
+	void *ss_sp;
+	size_t ss_size;
+	int ss_flags;
+} stack_t;
+
 #ifdef __KERNEL__
 #include <asm/sigcontext.h>
 #endif
diff --git a/include/asm-mips/smp_lock.h b/include/asm-mips/smp_lock.h
deleted file mode 100644
index c9482ab7d..000000000
--- a/include/asm-mips/smp_lock.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996  Ralf Baechle
- *
- * Linux/MIPS SMP support.  Just a dummy to make building possible.
- */
-#ifndef __ASM_MIPS_SMPLOCK_H
-#define __ASM_MIPS_SMPLOCK_H
-
-#ifndef __SMP__
-
-#define lock_kernel()		do { } while(0)
-#define unlock_kernel()		do { } while(0)
-#define release_kernel_lock(task, cpu, depth)  ((depth) = 1)
-#define reacquire_kernel_lock(task, cpu, depth) do { } while(0)
-
-#else
-
-#error "We do not support SMP on MIPS yet"
-
-#endif /* __SMP__ */
-
-#endif /* __ASM_MIPS_SMPLOCK_H */
diff --git a/include/asm-mips/smplock.h b/include/asm-mips/smplock.h
new file mode 100644
index 000000000..61bf3ff9c
--- /dev/null
+++ b/include/asm-mips/smplock.h
@@ -0,0 +1,52 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Default SMP lock implementation
+ */
+#include <linux/interrupt.h>
+#include <asm/spinlock.h>
+
+extern spinlock_t kernel_flag;
+
+/*
+ * Release global kernel lock and global interrupt lock
+ */
+#define release_kernel_lock(task, cpu) \
+do { \
+	if (task->lock_depth >= 0) \
+		spin_unlock(&kernel_flag); \
+	release_irqlock(cpu); \
+	__sti(); \
+} while (0)
+
+/*
+ * Re-acquire the kernel lock
+ */
+#define reacquire_kernel_lock(task) \
+do { \
+	if (task->lock_depth >= 0) \
+		spin_lock(&kernel_flag); \
+} while (0)
+
+
+/*
+ * Getting the big kernel lock.
+ *
+ * This cannot happen asynchronously,
+ * so we only need to worry about other
+ * CPU's.
+ */
+extern __inline__ void lock_kernel(void)
+{
+	if (!++current->lock_depth)
+		spin_lock(&kernel_flag);
+}
+
+extern __inline__ void unlock_kernel(void)
+{
+	if (--current->lock_depth < 0)
+		spin_unlock(&kernel_flag);
+}
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
index 7f4bded24..989ebd73e 100644
--- a/include/asm-mips/string.h
+++ b/include/asm-mips/string.h
@@ -1,13 +1,10 @@
-/*
- * include/asm-mips/string.h
+/* $Id: string.h,v 1.6 1998/07/20 17:52:21 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1994, 1995, 1996, 1997 by Ralf Baechle
- *
- * $Id: string.h,v 1.7 1998/03/25 00:24:10 ralf Exp $
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
  */
 #ifndef __ASM_MIPS_STRING_H
 #define __ASM_MIPS_STRING_H
@@ -127,11 +124,8 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
 #define __HAVE_ARCH_MEMMOVE
 extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
 
+/* Don't build bcopy at all ...  */
 #define __HAVE_ARCH_BCOPY
-extern __inline__ char * bcopy(const char * src, char * dest, int count)
-{
-	memmove(dest, src, count);
-}
 
 #define __HAVE_ARCH_MEMSCAN
 extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index dd5aa3422..c16163a32 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -1,10 +1,10 @@
-/* $Id: system.h,v 1.7 1998/05/04 03:53:22 ralf Exp $
+/* $Id: system.h,v 1.8 1998/07/20 17:52:21 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1994, 1995 by Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
  * Modified further for R[236]000 by Paul M. Antoine, 1996
  */
 #ifndef __ASM_MIPS_SYSTEM_H
@@ -118,13 +118,13 @@ __asm__ __volatile__(					\
 	: /* no input */				\
 	: "memory")
 
-#if !defined (__LANGUAGE_ASSEMBLY__)
+#if !defined (_LANGUAGE_ASSEMBLY)
 /*
  * switch_to(n) should switch tasks to task nr n, first
  * checking that n isn't the current task, in which case it does nothing.
  */
 extern asmlinkage void (*resume)(void *tsk);
-#endif /* !defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #define switch_to(prev,next) \
 do { \
diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h
index 8293b5df1..ae1e770aa 100644
--- a/include/asm-mips/termios.h
+++ b/include/asm-mips/termios.h
@@ -93,6 +93,7 @@ struct termio {
 #define N_AX25		5
 #define N_X25		6		/* X.25 async */
 #define N_6PACK		7
+#define N_MASC		8	/* Reserved fo Mobitex module <kaz@cafe.net> */
 
 #ifdef __KERNEL__
 
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
new file mode 100644
index 000000000..dd4aea511
--- /dev/null
+++ b/include/asm-mips/timex.h
@@ -0,0 +1,20 @@
+/* $Id: timex.h,v 1.1 1998/08/17 10:20:18 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 by Ralf Baechle
+ *
+ * FIXME: For some of the supported machines this is dead wrong.
+ */
+#ifndef __ASM_MIPS_TIMEX_H
+#define __ASM_MIPS_TIMEX_H
+
+#define CLOCK_TICK_RATE	1193180 /* Underlying HZ */
+#define CLOCK_TICK_FACTOR	20	/* Factor of both 1000000 and CLOCK_TICK_RATE */
+#define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
+	(1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
+		<< (SHIFT_SCALE-SHIFT_HZ)) / HZ)
+
+#endif /*  __ASM_MIPS_TIMEX_H */
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index a9640faa5..28079fe00 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -1,6 +1,4 @@
-/* $Id: unistd.h,v 1.13 1998/05/07 15:21:41 ralf Exp $
- *
- * This file contains the system call numbers.
+/* $Id: unistd.h,v 1.18 1998/08/20 16:34:48 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -1010,7 +1008,7 @@
 #define __NR_lseek			(__NR_Linux +  19)
 #define __NR_getpid			(__NR_Linux +  20)
 #define __NR_mount			(__NR_Linux +  21)
-#define __NR_umount			(__NR_Linux +  22)
+#define __NR_oldumount			(__NR_Linux +  22)
 #define __NR_setuid			(__NR_Linux +  23)
 #define __NR_getuid			(__NR_Linux +  24)
 #define __NR_stime			(__NR_Linux +  25)
@@ -1040,7 +1038,7 @@
 #define __NR_geteuid			(__NR_Linux +  49)
 #define __NR_getegid			(__NR_Linux +  50)
 #define __NR_acct			(__NR_Linux +  51)
-#define __NR_phys			(__NR_Linux +  52)
+#define __NR_umount			(__NR_Linux +  52)
 #define __NR_lock			(__NR_Linux +  53)
 #define __NR_ioctl			(__NR_Linux +  54)
 #define __NR_fcntl			(__NR_Linux +  55)
@@ -1194,13 +1192,17 @@
 #define __NR_getcwd			(__NR_Linux + 203)
 #define __NR_capget			(__NR_Linux + 204)
 #define __NR_capset			(__NR_Linux + 205)
+#define __NR_sigaltstack		(__NR_Linux + 206)
+#define __NR_sendfile			(__NR_Linux + 207)
+#define __NR_streams1			(__NR_Linux + 208)
+#define __NR_streams2			(__NR_Linux + 209)
 
 /*
  * Offset of the last Linux flavoured syscall
  */
-#define __NR_Linux_syscalls		205
+#define __NR_Linux_syscalls		209
 
-#ifndef __LANGUAGE_ASSEMBLY__
+#ifndef _LANGUAGE_ASSEMBLY
 
 /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
 #define _syscall0(type,name) \
@@ -1479,6 +1481,6 @@ static inline pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long f
 }
 
 #endif /* !defined (__KERNEL_SYSCALLS__) */
-#endif /* !defined (__LANGUAGE_ASSEMBLY__) */
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #endif /* __ASM_MIPS_UNISTD_H */
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
new file mode 100644
index 000000000..5fc680563
--- /dev/null
+++ b/include/asm-mips/vga.h
@@ -0,0 +1,35 @@
+/*
+ *	Access to VGA videoram
+ *
+ *	(c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+#ifndef _LINUX_ASM_VGA_H_
+#define _LINUX_ASM_VGA_H_
+
+#include <asm/io.h>
+
+#define VT_BUF_HAVE_RW
+
+extern inline void scr_writew(u16 val, u16 *addr)
+{
+	if ((long) addr < 0)
+		*addr = val;
+	else
+		writew(val, (unsigned long) addr);
+}
+
+extern inline u16 scr_readw(u16 *addr)
+{
+	if ((long) addr < 0)
+		return *addr;
+	else
+		return readw((unsigned long) addr);
+}
+
+#define vga_readb readb
+#define vga_writeb writeb
+
+#define VGA_MAP_MEM(x) (x)
+
+#endif
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h
index 6fcde8428..abfc622ef 100644
--- a/include/asm-mips/watch.h
+++ b/include/asm-mips/watch.h
@@ -1,13 +1,10 @@
-/*
- * Functions to use the watch register debugging functionality.
+/* $Id: watch.h,v 1.3 1998/08/19 21:58:15 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996, 1997 by Ralf Baechle
- *
- * $Id: watch.h,v 1.2 1997/09/19 08:37:44 ralf Exp $
+ * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
  */
 #ifndef __ASM_WATCH_H
 #define __ASM_WATCH_H
@@ -24,9 +21,9 @@ enum wref_type {
 
 extern char watch_available;
 
-extern asmlinkage __watch_set(unsigned long addr, enum wref_type ref);
-extern asmlinkage __watch_clear(void);
-extern asmlinkage __watch_reenable(void);
+extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref);
+extern asmlinkage void __watch_clear(void);
+extern asmlinkage void __watch_reenable(void);
 
 #define watch_set(addr, ref)					\
 	if (watch_available)					\