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authorRalf Baechle <ralf@linux-mips.org>2000-06-19 22:45:37 +0000
committerRalf Baechle <ralf@linux-mips.org>2000-06-19 22:45:37 +0000
commit6d403070f28cd44860fdb3a53be5da0275c65cf4 (patch)
tree0d0e7fe7b5fb7568d19e11d7d862b77a866ce081 /include/asm-ppc/io.h
parentecf1bf5f6c2e668d03b0a9fb026db7aa41e292e1 (diff)
Merge with 2.4.0-test1-ac21 + pile of MIPS cleanups to make merging
possible. Chainsawed RM200 kernel to compile again. Jazz machine status unknown.
Diffstat (limited to 'include/asm-ppc/io.h')
-rw-r--r--include/asm-ppc/io.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index a4be6b7e2..6e5a57ad6 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -161,6 +161,20 @@ extern inline void * bus_to_virt(unsigned long address)
}
/*
+ * The PCI bus bridge can translate addresses issued by the processor(s)
+ * into a different address on the PCI bus. On 32-bit cpus, we assume
+ * this mapping is 1-1, but on 64-bit systems it often isn't.
+ */
+#ifndef CONFIG_PPC64BRIDGE
+#define phys_to_bus(x) (x)
+#define bus_to_phys(x) (x)
+
+#else
+extern unsigned long phys_to_bus(unsigned long pa);
+extern unsigned long bus_to_phys(unsigned int ba, int busnr);
+#endif /* CONFIG_PPC64BRIDGE */
+
+/*
* Change virtual addresses to physical addresses and vv, for
* addresses in the area where the kernel has the RAM mapped.
*/