diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-10-05 01:18:40 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-10-05 01:18:40 +0000 |
| commit | 012bb3e61e5eced6c610f9e036372bf0c8def2d1 (patch) | |
| tree | 87efc733f9b164e8c85c0336f92c8fb7eff6d183 /include/asm-ppc | |
| parent | 625a1589d3d6464b5d90b8a0918789e3afffd220 (diff) | |
Merge with Linux 2.4.0-test9. Please check DECstation, I had a number
of rejects to fixup while integrating Linus patches. I also found
that this kernel will only boot SMP on Origin; the UP kernel freeze
soon after bootup with SCSI timeout messages. I commit this anyway
since I found that the last CVS versions had the same problem.
Diffstat (limited to 'include/asm-ppc')
33 files changed, 910 insertions, 191 deletions
diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h index c3c5133d6..cf0e122dc 100644 --- a/include/asm-ppc/atomic.h +++ b/include/asm-ppc/atomic.h @@ -5,13 +5,7 @@ #ifndef _ASM_PPC_ATOMIC_H_ #define _ASM_PPC_ATOMIC_H_ -#include <linux/config.h> - -#ifdef CONFIG_SMP typedef struct { volatile int counter; } atomic_t; -#else -typedef struct { int counter; } atomic_t; -#endif #define ATOMIC_INIT(i) { (i) } @@ -21,7 +15,7 @@ typedef struct { int counter; } atomic_t; extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); extern void atomic_set_mask(unsigned long mask, unsigned long *addr); -extern __inline__ int atomic_add_return(int a, atomic_t *v) +static __inline__ int atomic_add_return(int a, atomic_t *v) { int t; @@ -30,14 +24,14 @@ extern __inline__ int atomic_add_return(int a, atomic_t *v) add %0,%2,%0\n\ stwcx. %0,0,%3\n\ bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (a), "r" (v), "m" (*v) + : "=&r" (t), "=m" (v->counter) + : "r" (a), "r" (v), "m" (v->counter) : "cc"); return t; } -extern __inline__ int atomic_sub_return(int a, atomic_t *v) +static __inline__ int atomic_sub_return(int a, atomic_t *v) { int t; @@ -46,14 +40,14 @@ extern __inline__ int atomic_sub_return(int a, atomic_t *v) subf %0,%2,%0\n\ stwcx. %0,0,%3\n\ bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (a), "r" (v), "m" (*v) + : "=&r" (t), "=m" (v->counter) + : "r" (a), "r" (v), "m" (v->counter) : "cc"); return t; } -extern __inline__ int atomic_inc_return(atomic_t *v) +static __inline__ int atomic_inc_return(atomic_t *v) { int t; @@ -62,14 +56,14 @@ extern __inline__ int atomic_inc_return(atomic_t *v) addic %0,%0,1\n\ stwcx. %0,0,%2\n\ bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (v), "m" (*v) + : "=&r" (t), "=m" (v->counter) + : "r" (v), "m" (v->counter) : "cc"); return t; } -extern __inline__ int atomic_dec_return(atomic_t *v) +static __inline__ int atomic_dec_return(atomic_t *v) { int t; @@ -78,8 +72,8 @@ extern __inline__ int atomic_dec_return(atomic_t *v) addic %0,%0,-1\n\ stwcx. %0,0,%2\n\ bne 1b" - : "=&r" (t), "=m" (*v) - : "r" (v), "m" (*v) + : "=&r" (t), "=m" (v->counter) + : "r" (v), "m" (v->counter) : "cc"); return t; diff --git a/include/asm-ppc/backlight.h b/include/asm-ppc/backlight.h index db315e677..79756eca3 100644 --- a/include/asm-ppc/backlight.h +++ b/include/asm-ppc/backlight.h @@ -25,4 +25,4 @@ extern int get_backlight_enable(void); extern int set_backlight_level(int level); extern int get_backlight_level(void); -#endif
\ No newline at end of file +#endif diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index ccb0f199f..b82a9fc21 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -9,17 +9,9 @@ #include <linux/config.h> #include <asm/byteorder.h> -extern void set_bit(int nr, volatile void *addr); -extern void clear_bit(int nr, volatile void *addr); -extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); -extern int test_and_clear_bit(int nr, volatile void *addr); -extern int test_and_change_bit(int nr, volatile void *addr); - /* - * Arguably these bit operations don't imply any memory barrier or - * SMP ordering, but in fact a lot of drivers expect them to imply - * both, since they do on x86 cpus. + * The test_and_*_bit operations are taken to imply a memory barrier + * on SMP systems. */ #ifdef CONFIG_SMP #define SMP_WMB "eieio\n" @@ -36,58 +28,75 @@ extern int test_and_change_bit(int nr, volatile void *addr); * These used to be if'd out here because using : "cc" as a constraint * resulted in errors from egcs. Things may be OK with gcc-2.95. */ -extern __inline__ void set_bit(int nr, volatile void * addr) +static __inline__ void set_bit(int nr, volatile void * addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - __asm__ __volatile__(SMP_WMB "\ + __asm__ __volatile__("\ 1: lwarx %0,0,%3 or %0,%0,%2 stwcx. %0,0,%3 - bne 1b" - SMP_MB + bne- 1b" : "=&r" (old), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) : "cc" ); } -extern __inline__ void clear_bit(int nr, volatile void *addr) +/* + * non-atomic version + */ +static __inline__ void __set_bit(int nr, volatile void *addr) +{ + unsigned long mask = 1 << (nr & 0x1f); + unsigned long *p = ((unsigned long *)addr) + (nr >> 5); + + *p |= mask; +} + +/* + * clear_bit doesn't imply a memory barrier + */ +#define smp_mb__before_clear_bit() smp_mb() +#define smp_mb__after_clear_bit() smp_mb() + +static __inline__ void clear_bit(int nr, volatile void *addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - __asm__ __volatile__(SMP_WMB "\ + __asm__ __volatile__("\ 1: lwarx %0,0,%3 andc %0,%0,%2 stwcx. %0,0,%3 - bne 1b" - SMP_MB + bne- 1b" : "=&r" (old), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) : "cc"); } -extern __inline__ void change_bit(int nr, volatile void *addr) +static __inline__ void change_bit(int nr, volatile void *addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - __asm__ __volatile__(SMP_WMB "\ + __asm__ __volatile__("\ 1: lwarx %0,0,%3 xor %0,%0,%2 stwcx. %0,0,%3 - bne 1b" - SMP_MB + bne- 1b" : "=&r" (old), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) : "cc"); } -extern __inline__ int test_and_set_bit(int nr, volatile void *addr) +/* + * test_and_*_bit do imply a memory barrier (?) + */ +static __inline__ int test_and_set_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -101,12 +110,25 @@ extern __inline__ int test_and_set_bit(int nr, volatile void *addr) SMP_MB : "=&r" (old), "=&r" (t), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) - : "cc"); + : "cc", "memory"); return (old & mask) != 0; } -extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) +/* + * non-atomic version + */ +static __inline__ int __test_and_set_bit(int nr, volatile void *addr) +{ + unsigned long mask = 1 << (nr & 0x1f); + unsigned long *p = ((unsigned long *)addr) + (nr >> 5); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +static __inline__ int test_and_clear_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -120,12 +142,25 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) SMP_MB : "=&r" (old), "=&r" (t), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) - : "cc"); + : "cc", "memory"); return (old & mask) != 0; } -extern __inline__ int test_and_change_bit(int nr, volatile void *addr) +/* + * non-atomic version + */ +static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned long mask = 1 << (nr & 0x1f); + unsigned long *p = ((unsigned long *)addr) + (nr >> 5); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +static __inline__ int test_and_change_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -139,13 +174,22 @@ extern __inline__ int test_and_change_bit(int nr, volatile void *addr) SMP_MB : "=&r" (old), "=&r" (t), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) - : "cc"); + : "cc", "memory"); return (old & mask) != 0; } +#else /* __INLINE_BITOPS */ + +extern void set_bit(int nr, volatile void *addr); +extern void clear_bit(int nr, volatile void *addr); +extern void change_bit(int nr, volatile void *addr); +extern int test_and_set_bit(int nr, volatile void *addr); +extern int test_and_clear_bit(int nr, volatile void *addr); +extern int test_and_change_bit(int nr, volatile void *addr); + #endif /* __INLINE_BITOPS */ -extern __inline__ int test_bit(int nr, __const__ volatile void *addr) +static __inline__ int test_bit(int nr, __const__ volatile void *addr) { __const__ unsigned int *p = (__const__ unsigned int *) addr; @@ -153,7 +197,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) } /* Return the bit position of the most significant 1 bit in a word */ -extern __inline__ int __ilog2(unsigned int x) +static __inline__ int __ilog2(unsigned int x) { int lz; @@ -161,7 +205,7 @@ extern __inline__ int __ilog2(unsigned int x) return 31 - lz; } -extern __inline__ int ffz(unsigned int x) +static __inline__ int ffz(unsigned int x) { if ((x = ~x) == 0) return 32; @@ -175,7 +219,7 @@ extern __inline__ int ffz(unsigned int x) * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ -extern __inline__ int ffs(int x) +static __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } @@ -198,7 +242,7 @@ extern __inline__ int ffs(int x) #define find_first_zero_bit(addr, size) \ find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long find_next_zero_bit(void * addr, +static __inline__ unsigned long find_next_zero_bit(void * addr, unsigned long size, unsigned long offset) { unsigned int * p = ((unsigned int *) addr) + (offset >> 5); @@ -230,6 +274,8 @@ extern __inline__ unsigned long find_next_zero_bit(void * addr, tmp = *p; found_first: tmp |= ~0UL << size; + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ found_middle: return result + ffz(tmp); } @@ -238,42 +284,11 @@ found_middle: #define _EXT2_HAVE_ASM_BITOPS_ #ifdef __KERNEL__ -/* - * test_and_{set,clear}_bit guarantee atomicity without - * disabling interrupts. - */ -#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 0x18, addr) -#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) -#else -extern __inline__ int ext2_set_bit(int nr, void * addr) -{ - int mask; - unsigned char *ADDR = (unsigned char *) addr; - int oldbit; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - oldbit = (*ADDR & mask) ? 1 : 0; - *ADDR |= mask; - return oldbit; -} - -extern __inline__ int ext2_clear_bit(int nr, void * addr) -{ - int mask; - unsigned char *ADDR = (unsigned char *) addr; - int oldbit; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - oldbit = (*ADDR & mask) ? 1 : 0; - *ADDR = *ADDR & ~mask; - return oldbit; -} -#endif /* __KERNEL__ */ +#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 0x18, addr) +#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x18, addr) -extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) +static __inline__ int ext2_test_bit(int nr, __const__ void * addr) { __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; @@ -288,7 +303,7 @@ extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) #define ext2_find_first_zero_bit(addr, size) \ ext2_find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, +static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { unsigned int *p = ((unsigned int *) addr) + (offset >> 5); @@ -320,6 +335,8 @@ extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, tmp = cpu_to_le32p(p); found_first: tmp |= ~0U << size; + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ found_middle: return result + ffz(tmp); } @@ -331,4 +348,6 @@ found_middle: #define minix_test_bit(nr,addr) ext2_test_bit(nr,addr) #define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size) +#endif /* __KERNEL__ */ + #endif /* _PPC_BITOPS_H */ diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h index 5674bd0f9..90c79cdb7 100644 --- a/include/asm-ppc/bootx.h +++ b/include/asm-ppc/bootx.h @@ -133,4 +133,3 @@ typedef struct boot_infos #endif #endif -
\ No newline at end of file diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index 5f500d5c3..427ec1884 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -85,6 +85,7 @@ #define CPM_DATAONLY_BASE ((uint)128) #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) #define CPM_DP_NOSPACE ((uint)0x7fffffff) +#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) /* The number of pages of host memory we allocate for CPM. This is * done early in kernel initialization to get physically contiguous @@ -97,8 +98,8 @@ * and dual port ram. */ extern cpm8260_t *cpmp; /* Pointer to comm processor */ -uint m8260_cpm_dpalloc(uint size); -uint m8260_cpm_hostalloc(uint size); +uint m8260_cpm_dpalloc(uint size, uint align); +uint m8260_cpm_hostalloc(uint size, uint align); void m8260_cpm_setbrg(uint brg, uint rate); void m8260_cpm_fastbrg(uint brg, uint rate, int div16); @@ -153,7 +154,7 @@ typedef struct cpm_buf_desc { #define PROFF_REVNUM ((uint)0x8af0) #define PROFF_RAND ((uint)0x8af8) #define PROFF_I2C_BASE ((uint)0x8afc) -#define PROFF_IDMA4_BASE ((uint)0x89fe) +#define PROFF_IDMA4_BASE ((uint)0x8afe) /* The SMCs are relocated to any of the first eight DPRAM pages. * We will fix these at the first locations of DPRAM, until we @@ -403,40 +404,44 @@ typedef struct scc_enet { #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ -/* SCC Mode Register (PMSR) as used by Ethernet. +/* SCC Mode Register (PSMR) as used by Ethernet. */ -#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ /* Buffer descriptor control/status used by Ethernet receive. -*/ + * Common to SCC and FCC. + */ #define BD_ENET_RX_EMPTY ((ushort)0x8000) #define BD_ENET_RX_WRAP ((ushort)0x2000) #define BD_ENET_RX_INTR ((ushort)0x1000) #define BD_ENET_RX_LAST ((ushort)0x0800) #define BD_ENET_RX_FIRST ((ushort)0x0400) #define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ #define BD_ENET_RX_LG ((ushort)0x0020) #define BD_ENET_RX_NO ((ushort)0x0010) #define BD_ENET_RX_SH ((ushort)0x0008) #define BD_ENET_RX_CR ((ushort)0x0004) #define BD_ENET_RX_OV ((ushort)0x0002) #define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ +#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ /* Buffer descriptor control/status used by Ethernet transmit. -*/ + * Common to SCC and FCC. + */ #define BD_ENET_TX_READY ((ushort)0x8000) #define BD_ENET_TX_PAD ((ushort)0x4000) #define BD_ENET_TX_WRAP ((ushort)0x2000) @@ -523,6 +528,152 @@ typedef struct scc_trans { #define BD_SCC_TX_LAST ((ushort)0x0800) +/* How about some FCCs..... +*/ +#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) +#define FCC_GFMR_DIAG_LE ((uint)0x40000000) +#define FCC_GFMR_DIAG_AE ((uint)0x80000000) +#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) +#define FCC_GFMR_TCI ((uint)0x20000000) +#define FCC_GFMR_TRX ((uint)0x10000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_CDP ((uint)0x04000000) +#define FCC_GFMR_CTSP ((uint)0x02000000) +#define FCC_GFMR_CDS ((uint)0x01000000) +#define FCC_GFMR_CTSS ((uint)0x00800000) +#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) +#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) +#define FCC_GFMR_SYNL_8 ((uint)0x00008000) +#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) +#define FCC_GFMR_RTSM ((uint)0x00002000) +#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) +#define FCC_GFMR_REVD ((uint)0x00000400) +#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) +#define FCC_GFMR_TCRC_16 ((uint)0x00000000) +#define FCC_GFMR_TCRC_32 ((uint)0x00000080) +#define FCC_GFMR_ENR ((uint)0x00000020) +#define FCC_GFMR_ENT ((uint)0x00000010) +#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) +#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) +#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) + +/* Generic FCC parameter ram. +*/ +typedef struct fcc_param { + ushort fcc_riptr; /* Rx Internal temp pointer */ + ushort fcc_tiptr; /* Tx Internal temp pointer */ + ushort fcc_res1; + ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ + uint fcc_rstate; /* Upper byte is Func code, must be set */ + uint fcc_rbase; /* Receive BD base */ + ushort fcc_rbdstat; /* RxBD status */ + ushort fcc_rbdlen; /* RxBD down counter */ + uint fcc_rdptr; /* RxBD internal data pointer */ + uint fcc_tstate; /* Upper byte is Func code, must be set */ + uint fcc_tbase; /* Transmit BD base */ + ushort fcc_tbdstat; /* TxBD status */ + ushort fcc_tbdlen; /* TxBD down counter */ + uint fcc_tdptr; /* TxBD internal data pointer */ + uint fcc_rbptr; /* Rx BD Internal buf pointer */ + uint fcc_tbptr; /* Tx BD Internal buf pointer */ + uint fcc_rcrc; /* Rx temp CRC */ + uint fcc_res2; + uint fcc_tcrc; /* Tx temp CRC */ +} fccp_t; + + +/* Ethernet controller through FCC. +*/ +typedef struct fcc_enet { + fccp_t fen_genfcc; + uint fen_statbuf; /* Internal status buffer */ + uint fen_camptr; /* CAM address */ + uint fen_cmask; /* Constant mask for CRC */ + uint fen_cpres; /* Preset CRC */ + uint fen_crcec; /* CRC Error counter */ + uint fen_alec; /* alignment error counter */ + uint fen_disfc; /* discard frame counter */ + ushort fen_retlim; /* Retry limit */ + ushort fen_retcnt; /* Retry counter */ + ushort fen_pper; /* Persistence */ + ushort fen_boffcnt; /* backoff counter */ + uint fen_gaddrh; /* Group address filter, high 32-bits */ + uint fen_gaddrl; /* Group address filter, low 32-bits */ + ushort fen_tfcstat; /* out of sequence TxBD */ + ushort fen_tfclen; + uint fen_tfcptr; + ushort fen_mflr; /* Maximum frame length (1518) */ + ushort fen_paddrh; /* MAC address */ + ushort fen_paddrm; + ushort fen_paddrl; + ushort fen_ibdcount; /* Internal BD counter */ + ushort fen_idbstart; /* Internal BD start pointer */ + ushort fen_ibdend; /* Internal BD end pointer */ + ushort fen_txlen; /* Internal Tx frame length counter */ + uint fen_ibdbase[8]; /* Internal use */ + uint fen_iaddrh; /* Individual address filter */ + uint fen_iaddrl; + ushort fen_minflr; /* Minimum frame length (64) */ + ushort fen_taddrh; /* Filter transfer MAC address */ + ushort fen_taddrm; + ushort fen_taddrl; + ushort fen_padptr; /* Pointer to pad byte buffer */ + ushort fen_cftype; /* control frame type */ + ushort fen_cfrange; /* control frame range */ + ushort fen_maxb; /* maximum BD count */ + ushort fen_maxd1; /* Max DMA1 length (1520) */ + ushort fen_maxd2; /* Max DMA2 length (1520) */ + ushort fen_maxd; /* internal max DMA count */ + ushort fen_dmacnt; /* internal DMA counter */ + uint fen_octc; /* Total octect counter */ + uint fen_colc; /* Total collision counter */ + uint fen_broc; /* Total broadcast packet counter */ + uint fen_mulc; /* Total multicast packet count */ + uint fen_uspc; /* Total packets < 64 bytes */ + uint fen_frgc; /* Total packets < 64 bytes with errors */ + uint fen_ospc; /* Total packets > 1518 */ + uint fen_jbrc; /* Total packets > 1518 with errors */ + uint fen_p64c; /* Total packets == 64 bytes */ + uint fen_p65c; /* Total packets 64 < bytes <= 127 */ + uint fen_p128c; /* Total packets 127 < bytes <= 255 */ + uint fen_p256c; /* Total packets 256 < bytes <= 511 */ + uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ + uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ + uint fen_cambuf; /* Internal CAM buffer poiner */ + ushort fen_rfthr; /* Received frames threshold */ + ushort fen_rfcnt; /* Received frames count */ +} fcc_enet_t; + +/* FCC Event/Mask register as used by Ethernet. +*/ +#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ +#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ +#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ +#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* FCC Mode Register (FPSMR) as used by Ethernet. +*/ +#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ +#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ +#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ +#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ +#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ +#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ +#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ +#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ +#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ +#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ +#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ +#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ +#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ + /* IIC parameter RAM. */ typedef struct iic { diff --git a/include/asm-ppc/fcntl.h b/include/asm-ppc/fcntl.h index 6250eba7c..f8181d44d 100644 --- a/include/asm-ppc/fcntl.h +++ b/include/asm-ppc/fcntl.h @@ -35,6 +35,10 @@ #define F_SETSIG 10 /* for sockets. */ #define F_GETSIG 11 /* for sockets. */ +#define F_GETLK64 12 /* using 'struct flock64' */ +#define F_SETLK64 13 +#define F_SETLKW64 14 + /* for F_[GET|SET]FL */ #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ @@ -47,6 +51,9 @@ #define F_EXLCK 4 /* or 3 */ #define F_SHLCK 8 /* or 4 */ +/* for leases */ +#define F_INPROGRESS 16 + /* operations for bsd flock(), also used by the kernel implementation */ #define LOCK_SH 1 /* shared lock */ #define LOCK_EX 2 /* exclusive lock */ @@ -54,6 +61,11 @@ blocking */ #define LOCK_UN 8 /* remove lock */ +#define LOCK_MAND 32 /* This is a mandatory flock */ +#define LOCK_READ 64 /* ... Which allows concurrent read operations */ +#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */ +#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */ + #ifdef __KERNEL__ #define F_POSIX 1 #define F_FLOCK 2 @@ -68,4 +80,13 @@ struct flock { pid_t l_pid; }; +struct flock64 { + short l_type; + short l_whence; + loff_t l_start; + loff_t l_len; + pid_t l_pid; +}; + +#define F_LINUX_SPECIFIC_BASE 1024 #endif diff --git a/include/asm-ppc/feature.h b/include/asm-ppc/feature.h index c9f2d2eac..ca4ca4692 100644 --- a/include/asm-ppc/feature.h +++ b/include/asm-ppc/feature.h @@ -7,7 +7,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1998 Paul Mackerras. + * Copyright (C) 1998 Paul Mackerras & + * Ben. Herrenschmidt. + * * */ #ifndef __ASM_PPC_FEATURE_H @@ -76,6 +78,9 @@ extern void feature_init(void); */ extern void feature_set_gmac_power(struct device_node* device, int power); + /* use constants in KeyLargo.h for the reset parameter */ +extern void feature_set_gmac_phy_reset(struct device_node* device, int reset); + extern void feature_set_usb_power(struct device_node* device, int power); extern void feature_set_firewire_power(struct device_node* device, int power); diff --git a/include/asm-ppc/hardirq.h b/include/asm-ppc/hardirq.h index 07398997a..f7c12df77 100644 --- a/include/asm-ppc/hardirq.h +++ b/include/asm-ppc/hardirq.h @@ -5,16 +5,23 @@ #include <asm/smp.h> /* entry.S is sensitive to the offsets of these fields */ +/* The __last_jiffy_stamp field is needed to ensure that no decrementer + * interrupt is lost on SMP machines. Since on most CPUs it is in the same + * cache line as local_irq_count, it is cheap to access and is also used on UP + * for uniformity. + */ typedef struct { unsigned int __softirq_active; unsigned int __softirq_mask; unsigned int __local_irq_count; unsigned int __local_bh_count; unsigned int __syscall_count; + unsigned int __last_jiffy_stamp; } ____cacheline_aligned irq_cpustat_t; #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ +#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp) /* * Are we in an interrupt context? Either doing bottom half * or hardware interrupt processing? diff --git a/include/asm-ppc/heathrow.h b/include/asm-ppc/heathrow.h index 647c63261..039f22158 100644 --- a/include/asm-ppc/heathrow.h +++ b/include/asm-ppc/heathrow.h @@ -44,4 +44,9 @@ #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */ #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */ +/* We OR those features at boot on desktop G3s */ +#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE) + +/* Those seem to be different on paddington */ #define PADD_MODEM_POWER_N 0x00000001 /* modem power on paddington */ +#define PADD_RESET_SCC 0x02000000 /* check this please */ diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h new file mode 100644 index 000000000..428a59d1c --- /dev/null +++ b/include/asm-ppc/highmem.h @@ -0,0 +1,121 @@ +/* + * highmem.h: virtual kernel memory mappings for high memory + * + * PowerPC version, stolen from the i386 version. + * + * Used in CONFIG_HIGHMEM systems for memory pages which + * are not addressable by direct kernel virtual adresses. + * + * Copyright (C) 1999 Gerhard Wichert, Siemens AG + * Gerhard.Wichert@pdb.siemens.de + * + * + * Redesigned the x86 32-bit VM architecture to deal with + * up to 16 Terrabyte physical memory. With current x86 CPUs + * we now support up to 64 Gigabytes physical RAM. + * + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> + */ + +#ifndef _ASM_HIGHMEM_H +#define _ASM_HIGHMEM_H + +#ifdef __KERNEL__ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <asm/kmap_types.h> +#include <asm/pgtable.h> + +/* undef for production */ +#define HIGHMEM_DEBUG 1 + +extern pte_t *kmap_pte; +extern pgprot_t kmap_prot; +extern pte_t *pkmap_page_table; + +extern void kmap_init(void) __init; + +/* + * Right now we initialize only a single pte table. It can be extended + * easily, subsequent pte tables have to be allocated in one physical + * chunk of RAM. + */ +#define PKMAP_BASE (0xfe000000UL) +#define LAST_PKMAP 1024 +#define LAST_PKMAP_MASK (LAST_PKMAP-1) +#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) +#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) + +#define KMAP_FIX_BEGIN (0xfe400000UL) + +extern unsigned long kmap_high(struct page *page); +extern void kunmap_high(struct page *page); + +extern inline unsigned long kmap(struct page *page) +{ + if (in_interrupt()) + BUG(); + if (page < highmem_start_page) + return (unsigned long) page_address(page); + return kmap_high(page); +} + +extern inline void kunmap(struct page *page) +{ + if (in_interrupt()) + BUG(); + if (page < highmem_start_page) + return; + kunmap_high(page); +} + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need + * it. + */ +extern inline unsigned long kmap_atomic(struct page *page, enum km_type type) +{ + unsigned int idx; + unsigned long vaddr; + + if (page < highmem_start_page) + return (unsigned long) page_address(page); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; +#if HIGHMEM_DEBUG + if (!pte_none(*(kmap_pte+idx))) + BUG(); +#endif + set_pte(kmap_pte+idx, mk_pte(page, kmap_prot)); + flush_hash_page(0, vaddr); + + return vaddr; +} + +extern inline void kunmap_atomic(unsigned long vaddr, enum km_type type) +{ +#if HIGHMEM_DEBUG + unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < KMAP_FIX_BEGIN) // FIXME + return; + + if (vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE) + BUG(); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(kmap_pte+idx); + flush_hash_page(0, vaddr); +#endif +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-ppc/ide.h b/include/asm-ppc/ide.h index 198132fa4..8b50f862b 100644 --- a/include/asm-ppc/ide.h +++ b/include/asm-ppc/ide.h @@ -63,7 +63,6 @@ void ide_insw(ide_ioreg_t port, void *buf, int ns); void ide_outsw(ide_ioreg_t port, void *buf, int ns); void ppc_generic_ide_fix_driveid(struct hd_driveid *id); -#if 0 #undef insw #define insw(port, buf, ns) do { \ ppc_ide_md.insw((port), (buf), (ns)); \ @@ -73,7 +72,6 @@ void ppc_generic_ide_fix_driveid(struct hd_driveid *id); #define outsw(port, buf, ns) do { \ ppc_ide_md.outsw((port), (buf), (ns)); \ } while (0) -#endif #undef SUPPORT_SLOW_DATA_PORTS #define SUPPORT_SLOW_DATA_PORTS 0 diff --git a/include/asm-ppc/immap_8260.h b/include/asm-ppc/immap_8260.h index 407cbf04c..298276363 100644 --- a/include/asm-ppc/immap_8260.h +++ b/include/asm-ppc/immap_8260.h @@ -241,10 +241,12 @@ typedef struct fcc { char res1[2]; ushort fcc_fdsr; char res2[2]; - uint fcc_fcce; - uint fcc_fccm; + ushort fcc_fcce; + char res3[2]; + ushort fcc_fccm; + char res4[2]; u_char fcc_fccs; - char res3[3]; + char res5[3]; u_char fcc_ftirr_phy[4]; } fcc_t; diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 6e5a57ad6..45b2531a3 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -25,12 +25,12 @@ #include <asm/mpc8xx.h> #elif defined(CONFIG_8260) #include <asm/mpc8260.h> -#else +#else /* 4xx/8xx/8260 */ #ifdef CONFIG_APUS #define _IO_BASE 0 #define _ISA_MEM_BASE 0 #define PCI_DRAM_OFFSET 0 -#else +#else /* CONFIG_APUS */ extern unsigned long isa_io_base; extern unsigned long isa_mem_base; extern unsigned long pci_dram_offset; @@ -54,6 +54,14 @@ extern unsigned long pci_dram_offset; #define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) #endif + +#define __raw_readb(addr) (*(volatile unsigned char *)(addr)) +#define __raw_readw(addr) (*(volatile unsigned short *)(addr)) +#define __raw_readl(addr) (*(volatile unsigned int *)(addr)) +#define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v)) +#define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v)) +#define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v)) + /* * The insw/outsw/insl/outsl macros don't do byte-swapping. * They are only used in practice for transferring buffers which @@ -67,26 +75,76 @@ extern unsigned long pci_dram_offset; #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#ifdef CONFIG_ALL_PPC +/* + * We have to handle possible machine checks here on powermacs + * and potentially some CHRPs -- paulus. + */ +#define __do_in_asm(name, op) \ +extern __inline__ unsigned int name(unsigned int port) \ +{ \ + unsigned int x; \ + __asm__ __volatile__( \ + op " %0,0,%1\n" \ + "1: sync\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".previous\n" \ + ".section __ex_table,\"ax\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".previous" \ + : "=&r" (x) \ + : "r" (port + _IO_BASE)); \ + return x; \ +} + +#define __do_out_asm(name, op) \ +extern __inline__ void name(unsigned int val, unsigned int port) \ +{ \ + __asm__ __volatile__( \ + op " %0,0,%1\n" \ + "1: sync\n" \ + "2:\n" \ + ".section __ex_table,\"ax\"\n" \ + " .align 2\n" \ + " .long 1b,2b\n" \ + ".previous" \ + : : "r" (val), "r" (port + _IO_BASE)); \ +} + +__do_in_asm(inb, "lbzx") +__do_in_asm(inw, "lhbrx") +__do_in_asm(inl, "lwbrx") +__do_out_asm(outb, "stbx") +__do_out_asm(outw, "sthbrx") +__do_out_asm(outl, "stwbrx") + +#elif defined(CONFIG_APUS) #define inb(port) in_8((u8 *)((port)+_IO_BASE)) #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#if defined(CONFIG_APUS) #define inw(port) in_be16((u16 *)((port)+_IO_BASE)) #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) #define inl(port) in_be32((u32 *)((port)+_IO_BASE)) #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) -#else + +#else /* not APUS or ALL_PPC */ +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) #define inw(port) in_le16((u16 *)((port)+_IO_BASE)) #define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) #define inl(port) in_le32((u32 *)((port)+_IO_BASE)) #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) #endif -#define inb_p(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#define inb_p(port) inb((port)) +#define outb_p(val, port) outb((val), (port)) +#define inw_p(port) inw((port)) +#define outw_p(val, port) outw((val), (port)) +#define inl_p(port) inl((port)) +#define outl_p(val, port) outl((val), (port)) extern void _insb(volatile u8 *port, void *buf, int ns); extern void _outsb(volatile u8 *port, const void *buf, int ns); @@ -123,6 +181,8 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); */ extern void *__ioremap(unsigned long address, unsigned long size, unsigned long flags); +extern void *__ioremap_at(unsigned long phys, unsigned long size, + unsigned long flags); extern void *ioremap(unsigned long address, unsigned long size); #define ioremap_nocache(addr, size) ioremap((addr), (size)) extern void iounmap(void *addr); diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index 0f1972ddf..86647a0e6 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h @@ -184,6 +184,9 @@ extern irq_node_t *new_irq_node(void); */ #define SIU_INT_SMC1 ((uint)0x04) #define SIU_INT_SMC2 ((uint)0x05) +#define SIU_INT_FCC1 ((uint)0x20) +#define SIU_INT_FCC2 ((uint)0x21) +#define SIU_INT_FCC3 ((uint)0x22) #define SIU_INT_SCC1 ((uint)0x28) #define SIU_INT_SCC2 ((uint)0x29) #define SIU_INT_SCC3 ((uint)0x2a) diff --git a/include/asm-ppc/keylargo.h b/include/asm-ppc/keylargo.h new file mode 100644 index 000000000..5408262a1 --- /dev/null +++ b/include/asm-ppc/keylargo.h @@ -0,0 +1,103 @@ +/* + * keylargo.h: definitions for using the "KeyLargo" I/O controller chip. + * + */ + +/* offset from base for feature control registers */ +#define KEYLARGO_MBCR 0x34 /* Media bay control/status */ +#define KEYLARGO_FCR0 0x38 +#define KEYLARGO_FCR1 0x3c +#define KEYLARGO_FCR2 0x40 +#define KEYLARGO_FCR3 0x44 +#define KEYLARGO_FCR4 0x48 + +/* GPIO registers */ +#define KEYLARGO_GPIO_LEVELS0 0x50 +#define KEYLARGO_GPIO_LEVELS1 0x54 +#define KEYLARGO_GPIO_EXTINT_0 0x58 +#define KEYLARGO_GPIO_EXTINT_CNT 18 +#define KEYLARGO_GPIO_0 0x6A +#define KEYLARGO_GPIO_CNT 17 + +/* Specific GPIO regs */ +#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10) +#define KL_GPIO_ETH_PHY_RESET_ASSERT 0x04 +#define KL_GPIO_ETH_PHY_RESET_RELEASE 0x05 +#define KL_GPIO_ETH_PHY_RESET_TRISTATE 0x00 +/* + * Bits in feature control register + */ +#define KL_MBCR_MBDEV_ENABLE 0x00001000 + +#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* ??? */ +#define KL0_SCC_A_INTF_ENABLE 0x00000002 /* ??? */ +#define KL0_SCC_SLOWPCLK 0x00000004 +#define KL0_SCC_RESET 0x00000008 +#define KL0_SCCA_ENABLE 0x00000010 +#define KL0_SCCB_ENABLE 0x00000020 +#define KL0_SCC_CELL_ENABLE 0x00000040 +#define KL0_IRDA_ENABLE 0x00008000 +#define KL0_IRDA_CLK32_ENABLE 0x00010000 +#define KL0_IRDA_CLK19_ENABLE 0x00020000 +#define KL0_USB0_PAD_SUSPEND0 0x00040000 +#define KL0_USB0_PAD_SUSPEND1 0x00080000 +#define KL0_USB0_CELL_ENABLE 0x00100000 +#define KL0_USB1_PAD_SUSPEND0 0x00400000 +#define KL0_USB1_PAD_SUSPEND1 0x00800000 +#define KL0_USB1_CELL_ENABLE 0x01000000 +#define KL0_USB_REF_SUSPEND 0x10000000 + +#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \ + KL0_SCC_SLOWPCLK | \ + KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE) + +#define KL1_AUDIO_SEL_22MCLK 0x00000002 +#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 +#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* Burgundy only ? */ +#define KL1_AUDIO_CELL_ENABLE 0x00000040 +#define KL1_AUDIO_CHOOSE 0x00000080 /* Burgundy only ? */ +#define KL1_I2S0_CELL_ENABLE 0x00000400 +#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000 +#define KL1_I2S0_ENABLE 0x00002000 +#define KL1_I2S1_CELL_ENABLE 0x00020000 +#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000 +#define KL1_I2S1_ENABLE 0x00100000 +#define KL1_EIDE0_ENABLE 0x00800000 +#define KL1_EIDE0_RESET_N 0x01000000 +#define KL1_EIDE1_ENABLE 0x04000000 +#define KL1_EIDE1_RESET_N 0x08000000 +#define KL1_UIDE_ENABLE 0x20000000 +#define KL1_UIDE_RESET_N 0x40000000 + +#define KL2_IOBUS_ENABLE 0x00000002 +#define KL2_SLEEP_STATE_BIT 0x00000100 +#define KL2_MPIC_ENABLE 0x00020000 +#define KL2_MODEM_POWER_N 0x02000000 +#define KL2_AIRPORT_RESET_N 0x08000000 /* Or power ? */ + +#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 +#define KL3_SHUTDOWN_PLLKW6 0x00000002 +#define KL3_SHUTDOWN_PLLKW4 0x00000004 +#define KL3_SHUTDOWN_PLLKW35 0x00000008 +#define KL3_SHUTDOWN_PLLKW12 0x00000010 +#define KL3_PLL_RESET 0x00000020 +#define KL3_SHUTDOWN_PLL2X 0x00000080 +#define KL3_CLK66_ENABLE 0x00000100 +#define KL3_CLK49_ENABLE 0x00000200 +#define KL3_CLK45_ENABLE 0x00000400 +#define KL3_CLK31_ENABLE 0x00000800 +#define KL3_TIMER_CLK18_ENABLE 0x00001000 +#define KL3_I2S1_CLK18_ENABLE 0x00002000 +#define KL3_I2S0_CLK18_ENABLE 0x00004000 +#define KL3_VIA_CLK16_ENABLE 0x00008000 +#define KL3_STOPPING33_ENABLED 0x00080000 + +/* Port 0,1 : bus 0, port 2,3 : bus 1 */ +#define KL4_SET_PORT_ENABLE(p) (0x00000008 << (p<<3)) +#define KL4_SET_PORT_RESUME(p) (0x00000004 << (p<<3)) +#define KL4_SET_PORT_CONNECT(p) (0x00000002 << (p<<3)) +#define KL4_SET_PORT_DISCONNECT(p) (0x00000001 << (p<<3)) +#define KL4_GET_PORT_RESUME(p) (0x00000040 << (p<<3)) +#define KL4_GET_PORT_CONNECT(p) (0x00000020 << (p<<3)) +#define KL4_GET_PORT_DISCONNECT(p) (0x00000010 << (p<<3)) + diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h new file mode 100644 index 000000000..d92d81b20 --- /dev/null +++ b/include/asm-ppc/kmap_types.h @@ -0,0 +1,10 @@ +#ifndef _ASM_KMAP_TYPES_H +#define _ASM_KMAP_TYPES_H + +enum km_type { + KM_BOUNCE_READ, + KM_BOUNCE_WRITE, + KM_TYPE_NR +}; + +#endif diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h index 306fc2b21..709827f29 100644 --- a/include/asm-ppc/machdep.h +++ b/include/asm-ppc/machdep.h @@ -31,7 +31,7 @@ struct machdep_calls { void (*power_off)(void); void (*halt)(void); - void (*time_init)(void); /* Optional, may be NULL */ + long (*time_init)(void); /* Optional, may be NULL */ int (*set_rtc_time)(unsigned long nowtime); unsigned long (*get_rtc_time)(void); void (*calibrate_decr)(void); @@ -75,7 +75,7 @@ struct machdep_calls { void (*pcibios_fixup)(void); void (*pcibios_fixup_bus)(struct pci_bus *); - void* (*pci_dev_io_base)(unsigned char bus, unsigned char devfn); + void* (*pci_dev_io_base)(unsigned char bus, unsigned char devfn, int physical); void* (*pci_dev_mem_base)(unsigned char bus, unsigned char devfn); int (*pci_dev_root_bridge)(unsigned char bus, unsigned char devfn); diff --git a/include/asm-ppc/mbx.h b/include/asm-ppc/mbx.h index e67e0344f..6c84b8955 100644 --- a/include/asm-ppc/mbx.h +++ b/include/asm-ppc/mbx.h @@ -25,6 +25,7 @@ typedef struct bd_info { unsigned int bi_busfreq; /* Bus Freq, in Hz */ unsigned int bi_clun; /* Boot device controller */ unsigned int bi_dlun; /* Boot device logical dev */ + unsigned int bi_baudrate; /* ...to be like everyone else */ } bd_t; /* Memory map for the MBX as configured by EPPC-Bug. We could reprogram diff --git a/include/asm-ppc/mman.h b/include/asm-ppc/mman.h index 99a5c8386..64abf0c58 100644 --- a/include/asm-ppc/mman.h +++ b/include/asm-ppc/mman.h @@ -22,8 +22,8 @@ #define MS_INVALIDATE 2 /* invalidate the caches */ #define MS_SYNC 4 /* synchronous memory sync */ -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ +#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */ +#define MCL_FUTURE 0x4000 /* lock all additions to address space */ #define MADV_NORMAL 0x0 /* default page-in behavior */ #define MADV_RANDOM 0x1 /* page-in minimum required */ diff --git a/include/asm-ppc/nvram.h b/include/asm-ppc/nvram.h index 985d2a321..144d518b9 100644 --- a/include/asm-ppc/nvram.h +++ b/include/asm-ppc/nvram.h @@ -38,6 +38,8 @@ enum { pmac_nvram_NR /* MacOS Name Registry partition */ }; +#ifdef __KERNEL__ + /* Return partition offset in nvram */ extern int pmac_get_partition(int partition); @@ -45,15 +47,20 @@ extern int pmac_get_partition(int partition); extern u8 pmac_xpram_read(int xpaddr); extern void pmac_xpram_write(int xpaddr, u8 data); +#endif /* __KERNEL__ */ + /* Some offsets in XPRAM */ #define PMAC_XPRAM_MACHINE_LOC 0xe4 #define PMAC_XPRAM_SOUND_VOLUME 0x08 /* Machine location structure in XPRAM */ struct pmac_machine_location { - u32 latitude; /* 2+30 bit Fractional number */ - u32 longitude; /* 2+30 bit Fractional number */ - u32 delta; /* mix of GMT delta and DLS */ + unsigned int latitude; /* 2+30 bit Fractional number */ + unsigned int longitude; /* 2+30 bit Fractional number */ + unsigned int delta; /* mix of GMT delta and DLS */ }; +/* /dev/nvram ioctls */ +#define PMAC_NVRAM_GET_OFFSET _IOWR('p', 0x40, int) /* Get NVRAM partition offset */ + #endif diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h index ca893118a..5aa72d3a2 100644 --- a/include/asm-ppc/pci-bridge.h +++ b/include/asm-ppc/pci-bridge.h @@ -15,8 +15,12 @@ void *pci_io_base(unsigned int bus); /* This version handles the new Uni-N host bridge, the iobase is now * a per-device thing. I also added the memory base so PReP can * be fixed to return 0xc0000000 (I didn't actually implement it) + * + * pci_dev_io_base() returns either a virtual (ioremap'ed) address or + * a physical address. In-kernel clients will use logical while the + * sys_pciconfig_iobase syscall returns a physical one to userland. */ -void *pci_dev_io_base(unsigned char bus, unsigned char devfn); +void *pci_dev_io_base(unsigned char bus, unsigned char devfn, int physical); void *pci_dev_mem_base(unsigned char bus, unsigned char devfn); /* Returns the root-bridge number (Uni-N number) of a device */ @@ -33,7 +37,8 @@ int pci_device_loc(struct device_node *dev, unsigned char *bus_ptr, struct bridge_data { volatile unsigned int *cfg_addr; volatile unsigned char *cfg_data; - void *io_base; + void *io_base; /* virtual */ + unsigned long io_base_phys; int bus_number; int max_bus; struct bridge_data *next; diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 348404828..c5a90fba0 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -69,7 +69,7 @@ extern inline void flush_tlb_pgtables(struct mm_struct *mm, extern void flush_icache_range(unsigned long, unsigned long); extern void __flush_page_to_ram(unsigned long page_va); -#define flush_page_to_ram(page) __flush_page_to_ram((unsigned long) page_address(page)) +extern void flush_page_to_ram(struct page *page); #define flush_dcache_page(page) do { } while (0) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 4fd684705..f99eb4abe 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -287,6 +287,7 @@ #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ #define SPRN_XER 0x001 /* Fixed Point Exception Register */ #define SPRN_ZPR 0x3B0 /* Zone Protection Register */ diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h index a3d6e5d22..dc98c596d 100644 --- a/include/asm-ppc/prom.h +++ b/include/asm-ppc/prom.h @@ -7,11 +7,16 @@ #ifndef _PPC_PROM_H #define _PPC_PROM_H +#include <linux/config.h> + typedef void *phandle; typedef void *ihandle; extern char *prom_display_paths[]; extern unsigned int prom_num_displays; +#ifndef CONFIG_MACH_SPECIFIC +extern int have_of; +#endif struct address_range { unsigned int space; diff --git a/include/asm-ppc/resource.h b/include/asm-ppc/resource.h index d31976a3d..956b34602 100644 --- a/include/asm-ppc/resource.h +++ b/include/asm-ppc/resource.h @@ -11,8 +11,9 @@ #define RLIMIT_NOFILE 7 /* max number of open files */ #define RLIMIT_MEMLOCK 8 /* max locked-in-memory address space */ #define RLIMIT_AS 9 /* address space limit(?) */ +#define RLIMIT_LOCKS 10 /* maximum file locks held */ -#define RLIM_NLIMITS 10 +#define RLIM_NLIMITS 11 #ifdef __KERNEL__ @@ -35,6 +36,7 @@ { INR_OPEN, INR_OPEN }, \ { RLIM_INFINITY, RLIM_INFINITY }, \ { RLIM_INFINITY, RLIM_INFINITY }, \ + { RLIM_INFINITY, RLIM_INFINITY }, \ } #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index 61d3412b9..b6b89dc79 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h @@ -23,16 +23,6 @@ #define RS_TABLE_SIZE 4 #endif -#ifdef CONFIG_PMAC -/* - * Auto-probing will cause machine checks on powermacs. - */ -#define SERIAL_PORT_DFNS -#else -/* - * PReP, CHRP, etc. - */ - /* Standard COM flags (except for COM4, because of the 8514 problem) */ #ifdef CONFIG_SERIAL_DETECT_IRQ #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) @@ -136,5 +126,4 @@ HUB6_SERIAL_PORT_DFNS \ MCA_SERIAL_PORT_DFNS -#endif /* CONFIG_PMAC */ #endif /* CONFIG_GEMINI */ diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h index aec727670..abbd0ca0c 100644 --- a/include/asm-ppc/smp.h +++ b/include/asm-ppc/smp.h @@ -24,10 +24,11 @@ extern struct cpuinfo_PPC cpu_data[NR_CPUS]; extern unsigned long smp_proc_in_lock[NR_CPUS]; -extern void smp_message_pass(int target, int msg, unsigned long data, int wait); extern void smp_store_cpu_info(int id); -extern void smp_message_recv(int); -void smp_send_tlb_invalidate(int); +extern void smp_send_tlb_invalidate(int); +extern void smp_send_xmon_break(int cpu); +struct pt_regs; +extern void smp_message_recv(int, struct pt_regs *); #define NO_PROC_ID 0xFF /* No processor magic marker */ #define PROC_CHANGE_PENALTY 20 diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h index 5e7e2a19e..292406736 100644 --- a/include/asm-ppc/spinlock.h +++ b/include/asm-ppc/spinlock.h @@ -41,6 +41,7 @@ typedef struct { } rwlock_t; #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 } +#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0) extern void _read_lock(rwlock_t *rw); extern void _read_unlock(rwlock_t *rw); diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index 153e1c49d..523a427a0 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -36,6 +36,16 @@ #define set_mb(var, value) do { var = value; mb(); } while (0) #define set_wmb(var, value) do { var = value; wmb(); } while (0) +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() __asm__ __volatile__("": : :"memory") +#define smp_rmb() __asm__ __volatile__("": : :"memory") +#define smp_wmb() __asm__ __volatile__("": : :"memory") +#endif /* CONFIG_SMP */ + extern void xmon_irq(int, void *, struct pt_regs *); extern void xmon(struct pt_regs *excp); @@ -67,6 +77,7 @@ extern void cvt_fd(float *from, double *to, unsigned long *fpscr); extern void cvt_df(double *from, float *to, unsigned long *fpscr); extern int call_rtas(const char *, int, int, unsigned long *, ...); extern int abs(int); +extern void cacheable_memzero(void *p, unsigned int nb); struct device_node; extern void note_scsi_host(struct device_node *, void *); @@ -114,16 +125,25 @@ extern void __global_restore_flags(unsigned long); #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -extern unsigned long xchg_u64(void *ptr, unsigned long val); -extern unsigned long xchg_u32(void *ptr, unsigned long val); +static __inline__ unsigned long +xchg_u32(volatile void *p, unsigned long val) +{ + unsigned long prev; + + __asm__ __volatile__ (" +1: lwarx %0,0,%2 + stwcx. %3,0,%2 + bne- 1b" + : "=&r" (prev), "=m" (*(volatile unsigned long *)p) + : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) + : "cc", "memory"); + + return prev; +} /* * This function doesn't exist, so you'll get a linker error * if something tries to do an invalid xchg(). - * - * This only works if the compiler isn't horribly bad at optimizing. - * gcc-2.5.8 reportedly can't handle this, but as that doesn't work - * too well on the alpha anyway.. */ extern void __xchg_called_with_bad_pointer(void); @@ -135,8 +155,10 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) switch (size) { case 4: return (unsigned long )xchg_u32(ptr, x); +#if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ case 8: return (unsigned long )xchg_u64(ptr, x); +#endif /* 0 */ } __xchg_called_with_bad_pointer(); return x; @@ -149,4 +171,56 @@ extern inline void * xchg_ptr(void * m, void * val) return (void *) xchg_u32(m, (unsigned long) val); } -#endif + +#define __HAVE_ARCH_CMPXCHG 1 + +static __inline__ unsigned long +__cmpxchg_u32(volatile int *p, int old, int new) +{ + int prev; + + __asm__ __volatile__ (" +1: lwarx %0,0,%2 + cmpw 0,%0,%3 + bne 2f + stwcx. %4,0,%2 + bne- 1b\n" +#ifdef CONFIG_SMP +" sync\n" +#endif /* CONFIG_SMP */ +"2:" + : "=&r" (prev), "=m" (*p) + : "r" (p), "r" (old), "r" (new), "m" (*p) + : "cc", "memory"); + + return prev; +} + +/* This function doesn't exist, so you'll get a linker error + if something tries to do an invalid cmpxchg(). */ +extern void __cmpxchg_called_with_bad_pointer(void); + +static __inline__ unsigned long +__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32(ptr, old, new); +#if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ + case 8: + return __cmpxchg_u64(ptr, old, new); +#endif /* 0 */ + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr,o,n) \ + ({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr))); \ + }) + +#endif /* __PPC_SYSTEM_H */ diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h index 05d791546..1eb0ae9f0 100644 --- a/include/asm-ppc/time.h +++ b/include/asm-ppc/time.h @@ -12,11 +12,10 @@ #include <asm/processor.h> /* time.c */ -extern unsigned decrementer_count; -extern unsigned count_period_num; -extern unsigned count_period_den; -extern unsigned long mktime(unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int); +extern unsigned tb_ticks_per_jiffy; +extern unsigned tb_to_us; +extern unsigned tb_last_stamp; + extern void to_tm(int tim, struct rtc_time * tm); extern time_t last_rtc_update; @@ -37,6 +36,80 @@ static __inline__ void set_dec(unsigned int val) #if defined(CONFIG_4xx) mtspr(SPRN_PIT, val); #else +#ifdef CONFIG_8xx_CPU6 + set_dec_cpu6(val); +#else mtspr(SPRN_DEC, val); #endif +#endif +} + +/* Accessor functions for the timebase (RTC on 601) registers. */ +/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ +#ifdef CONFIG_6xx +extern __inline__ int const __USE_RTC(void) { + return (mfspr(SPRN_PVR)>>16) == 1; +} +#else +#define __USE_RTC() 0 +#endif + +extern __inline__ unsigned long get_tbl(void) { + unsigned long tbl; + asm volatile("mftb %0" : "=r" (tbl)); + return tbl; } + +extern __inline__ unsigned long get_rtcl(void) { + unsigned long rtcl; + asm volatile("mfrtcl %0" : "=r" (rtcl)); + return rtcl; +} + +extern __inline__ unsigned get_native_tbl(void) { + if (__USE_RTC()) + return get_rtcl(); + else + return get_tbl(); +} + +/* On machines with RTC, this function can only be used safely + * after the timestamp and for 1 second. It is only used by gettimeofday + * however so it should not matter. + */ +extern __inline__ unsigned tb_ticks_since(unsigned tstamp) { + if (__USE_RTC()) { + int delta = get_rtcl() - tstamp; + return delta<0 ? delta + 1000000000 : delta; + } else { + return get_tbl() - tstamp; + } +} + +#if 0 +extern __inline__ unsigned long get_bin_rtcl(void) { + unsigned long rtcl, rtcu1, rtcu2; + asm volatile("\ +1: mfrtcu %0\n\ + mfrtcl %1\n\ + mfrtcu %2\n\ + cmpw %0,%2\n\ + bne- 1b\n" + : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2) + : : "cr0"); + return rtcu2*1000000000+rtcl; +} + +extern __inline__ unsigned binary_tbl(void) { + if (__USE_RTC()) + return get_bin_rtcl(); + else + return get_tbl(); +} +#endif + +/* Use mulhwu to scale processor timebase to timeval */ +#define mulhwu(x,y) \ +({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) + +unsigned mulhwu_scale_factor(unsigned, unsigned); diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h index 3eafdbd91..628373b15 100644 --- a/include/asm-ppc/uaccess.h +++ b/include/asm-ppc/uaccess.h @@ -57,7 +57,7 @@ struct exception_table_entry /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); - +extern void sort_exception_table(void); /* * These are the main single-value transfer routines. They automatically @@ -87,25 +87,6 @@ extern unsigned long search_exception_table(unsigned long); #define __put_user(x,ptr) \ __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) -/* - * The "xxx_ret" versions return constant specified in third argument, if - * something bad happens. These macros can be optimized for the - * case of just returning from the function xxx_ret is used. - */ - -#define put_user_ret(x,ptr,ret) ({ \ -if (put_user(x,ptr)) return ret; }) - -#define get_user_ret(x,ptr,ret) ({ \ -if (get_user(x,ptr)) return ret; }) - -#define __put_user_ret(x,ptr,ret) ({ \ -if (__put_user(x,ptr)) return ret; }) - -#define __get_user_ret(x,ptr,ret) ({ \ -if (__get_user(x,ptr)) return ret; }) - - extern long __put_user_bad(void); #define __put_user_nocheck(x,ptr,size) \ @@ -150,10 +131,11 @@ struct __large_struct { unsigned long buf[100]; }; ".section .fixup,\"ax\"\n" \ "3: li %0,%3\n" \ " b 2b\n" \ + ".previous\n" \ ".section __ex_table,\"a\"\n" \ " .align 2\n" \ " .long 1b,3b\n" \ - ".text" \ + ".previous" \ : "=r"(err) \ : "r"(x), "b"(addr), "i"(-EFAULT), "0"(err)) @@ -197,10 +179,11 @@ do { \ "3: li %0,%3\n" \ " li %1,0\n" \ " b 2b\n" \ + ".previous\n" \ ".section __ex_table,\"a\"\n" \ " .align 2\n" \ " .long 1b,3b\n" \ - ".text" \ + ".previous" \ : "=r"(err), "=r"(x) \ : "b"(addr), "i"(-EFAULT), "0"(err)) @@ -236,10 +219,6 @@ copy_to_user(void *to, const void *from, unsigned long n) return n; } -#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) - -#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) - #define __copy_from_user(to, from, size) \ __copy_tofrom_user((to), (from), (size)) #define __copy_to_user(to, from, size) \ diff --git a/include/asm-ppc/uninorth.h b/include/asm-ppc/uninorth.h new file mode 100644 index 000000000..eefe4389c --- /dev/null +++ b/include/asm-ppc/uninorth.h @@ -0,0 +1,83 @@ +/* + * uninorth.h: definitions for using the "UniNorth" host bridge chip + * from Apple. This chip is used on "Core99" machines + * + */ + + +/* + * Uni-N config space reg. definitions + * + * (Little endian) + */ + +/* Address ranges selection. This one should work with Bandit too */ +#define UNI_N_ADDR_SELECT 0x48 +#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */ +#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */ + +/* AGP registers */ +#define UNI_N_CFG_GART_BASE 0x8c +#define UNI_N_CFG_AGP_BASE 0x90 +#define UNI_N_CFG_GART_CTRL 0x94 +#define UNI_N_CFG_INTERNAL_STATUS 0x98 + +/* UNI_N_CFG_GART_CTRL bits definitions */ +#define UNI_N_CFG_GART_INVAL 0x00000001 +#define UNI_N_CFG_GART_ENABLE 0x00000100 +#define UNI_N_CFG_GART_2xRESET 0x00010000 + + +/* + * Uni-N memory mapped reg. definitions + * + * Those registers are Big-Endian !! + * + * Their meaning come from either Darwin and/or from experiments I made with + * the bootrom, I'm not sure about their exact meaning yet + * + */ + +/* Version of the UniNorth chip */ +#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */ + +/* This register is used to enable/disable various parts */ +#define UNI_N_CLOCK_CNTL 0x0020 +#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* guess ? */ +#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 +#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* guess ? */ + +/* Power Management control ? (from Darwin) */ +#define UNI_N_POWER_MGT 0x0030 +#define UNI_N_POWER_MGT_NORMAL 0x00 +#define UNI_N_POWER_MGT_IDLE2 0x01 +#define UNI_N_POWER_MGT_SLEEP 0x02 + +/* This register is configured by Darwin depending on the UniN + * revision + */ +#define UNI_N_ARB_CTRL 0x0040 +#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15 +#define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000 +#define UNI_N_ARB_CTRL_QACK_DELAY 0x30 +#define UNI_N_ARB_CTRL_QACK_DELAY105 0x00 + +/* This one _might_ return the CPU number of the CPU reading it; + * the bootROM decides wether to boot or to sleep/spinloop depending + * on this register beeing 0 or not + */ +#define UNI_N_CPU_NUMBER 0x0050 + +/* This register appear to be read by the bootROM to decide what + * to do on a non-recoverable reset (powerup or wakeup) + */ +#define UNI_N_HWINIT_STATE 0x0070 +#define UNI_N_HWINIT_STATE_SLEEPING 0x01 +#define UNI_N_HWINIT_STATE_RUNNING 0x02 +/* This last bit appear to be used by the bootROM to know the second + * CPU has started and will enter it's sleep loop with IP=0 + */ +#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000 + + + diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h index 3b884cbb4..5c432792b 100644 --- a/include/asm-ppc/unistd.h +++ b/include/asm-ppc/unistd.h @@ -201,10 +201,10 @@ #define __NR_stat64 195 #define __NR_lstat64 196 #define __NR_fstat64 197 -#define __NR_sys_pciconfig_read 198 -#define __NR_sys_pciconfig_write 199 -#define __NR_sys_pciconfig_iobase 200 -#define __NR_multiplexer 201 +#define __NR_pciconfig_read 198 +#define __NR_pciconfig_write 199 +#define __NR_pciconfig_iobase 200 +#define __NR_multiplexer 201 #define __NR_getdents64 202 #define __NR(n) #n |