diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1997-04-29 21:13:14 +0000 |
|---|---|---|
| committer | <ralf@linux-mips.org> | 1997-04-29 21:13:14 +0000 |
| commit | 19c9bba94152148523ba0f7ef7cffe3d45656b11 (patch) | |
| tree | 40b1cb534496a7f1ca0f5c314a523c69f1fee464 /include/asm-sparc/cache.h | |
| parent | 7206675c40394c78a90e74812bbdbf8cf3cca1be (diff) | |
Import of Linux/MIPS 2.1.36
Diffstat (limited to 'include/asm-sparc/cache.h')
| -rw-r--r-- | include/asm-sparc/cache.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h index f537c5cc3..f1e694ea6 100644 --- a/include/asm-sparc/cache.h +++ b/include/asm-sparc/cache.h @@ -1,4 +1,4 @@ -/* $Id: cache.h,v 1.5 1996/08/29 09:48:06 davem Exp $ +/* $Id: cache.h,v 1.6 1996/12/28 19:55:12 davem Exp $ * cache.h: Cache specific code for the Sparc. These include flushing * and direct tag/data line access. * @@ -10,6 +10,8 @@ #include <asm/asi.h> +#define L1_CACHE_BYTES 32 + /* Direct access to the instruction cache is provided through and * alternate address space. The IDC bit must be off in the ICCR on * HyperSparcs for these accesses to work. The code below does not do |