diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1999-10-09 00:00:47 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 1999-10-09 00:00:47 +0000 |
| commit | d6434e1042f3b0a6dfe1b1f615af369486f9b1fa (patch) | |
| tree | e2be02f33984c48ec019c654051d27964e42c441 /include/asm-sparc/cache.h | |
| parent | 609d1e803baf519487233b765eb487f9ec227a18 (diff) | |
Merge with 2.3.19.
Diffstat (limited to 'include/asm-sparc/cache.h')
| -rw-r--r-- | include/asm-sparc/cache.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h index 19885d7e9..6a5b74bb0 100644 --- a/include/asm-sparc/cache.h +++ b/include/asm-sparc/cache.h @@ -1,4 +1,4 @@ -/* $Id: cache.h,v 1.8 1999/03/11 00:14:45 davem Exp $ +/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $ * cache.h: Cache specific code for the Sparc. These include flushing * and direct tag/data line access. * @@ -15,6 +15,14 @@ #define SMP_CACHE_BYTES 32 +#ifdef MODULE +#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) +#else +#define __cacheline_aligned \ + __attribute__((__aligned__(SMP_CACHE_BYTES), \ + __section__(".data.cacheline_aligned"))) +#endif + /* Direct access to the instruction cache is provided through and * alternate address space. The IDC bit must be off in the ICCR on * HyperSparcs for these accesses to work. The code below does not do |