The rest of 2.3.6.

2 files changed, 325 insertions, 0 deletions

diff --git a/include/net/irda/smc-ircc.h b/include/net/irda/smc-ircc.h
new file mode 100644
index 000000000..2c5cbf4fd
--- /dev/null
+++ b/include/net/irda/smc-ircc.h
@@ -0,0 +1,160 @@
+/*********************************************************************
+ *                
+ * Filename:      smc.h
+ * Version:       
+ * Description:   
+ * Status:        Experimental.
+ * Author:        Thomas Davis (tadavis@jps.net)
+ *
+ *     Copyright (c) 1998, 1999 Thomas Davis (tadavis@jps.net>
+ *     All Rights Reserved
+ *      
+ *     This program is free software; you can redistribute it and/or 
+ *     modify it under the terms of the GNU General Public License as 
+ *     published by the Free Software Foundation; either version 2 of 
+ *     the License, or (at your option) any later version.
+ *  
+ *     I, Thomas Davis, admit no liability nor provide warranty for any
+ *     of this software. This material is provided "AS-IS" and at no charge.
+ *     
+ * Definitions for the SMC IrCC controller.
+ *
+ ********************************************************************/
+
+#ifndef SMC_IRCC_H
+#define SMC_IRCC_H
+
+#define UART_MASTER			0x07
+#define UART_MASTER_POWERDOWN	1<<7
+#define UART_MASTER_RESET		1<<6
+#define UART_MASTER_INT_EN		1<<5
+#define UART_MASTER_ERROR_RESET	1<<4
+
+/* Register block 0 */
+
+#define UART_IIR	0x01
+#define UART_IER	0x02
+#define UART_LSR	0x03
+#define UART_LCR_A	0x04
+#define UART_LCR_B	0x05
+#define UART_BSR	0x06
+
+#define UART_IIR_ACTIVE_FRAME	1<<7
+#define UART_IIR_EOM 		1<<6
+#define UART_IIR_RAW_MODE		1<<5
+#define UART_IIR_FIFO		1<<4
+
+#define UART_IER_ACTIVE_FRAME	1<<7
+#define UART_IER_EOM 		1<<6
+#define UART_IER_RAW_MODE		1<<5
+#define UART_IER_FIFO		1<<4
+
+#define UART_LSR_UNDERRUN		1<<7
+#define UART_LSR_OVERRUN		1<<6
+#define UART_LSR_FRAME_ERROR 	1<<5
+#define UART_LSR_SIZE_ERROR		1<<4
+#define UART_LSR_CRC_ERROR		1<<3
+#define UART_LSR_FRAME_ABORT 	1<<2
+
+#define UART_LCR_A_FIFO_RESET        1<<7
+#define UART_LCR_A_FAST              1<<6
+#define UART_LCR_A_GP_DATA           1<<5
+#define UART_LCR_A_RAW_TX            1<<4
+#define UART_LCR_A_RAW_RX            1<<3
+#define UART_LCR_A_ABORT             1<<2
+#define UART_LCR_A_DATA_DONE         1<<1
+
+#define UART_LCR_B_SCE_DISABLED 	0x00<<6
+#define UART_LCR_B_SCE_TRANSMIT 	0x01<<6
+#define UART_LCR_B_SCE_RECEIVE		0x02<<6
+#define UART_LCR_B_SCE_UNDEFINED	0x03<<6
+#define UART_LCR_B_SIP_ENABLE		1<<5
+#define UART_LCR_B_BRICK_WALL		1<<4
+
+#define UART_BSR_NOT_EMPTY	1<<7
+#define UART_BSR_FIFO_FULL	1<<6
+#define UART_BSR_TIMEOUT	1<<5
+
+/* Register block 1 */
+
+#define UART_SCE_CFGA	0x00
+#define UART_SCE_CFGB	0x01
+#define UART_FIFO_THRESHOLD	0x02
+
+#define UART_CFGA_AUX_IR		0x01<<7
+#define UART_CFGA_HALF_DUPLEX	0x01<<2
+#define UART_CFGA_TX_POLARITY	0x01<<1
+#define UART_CFGA_RX_POLARITY	0x01
+
+#define UART_CFGA_COM		0x00<<3
+#define UART_CFGA_IRDA_SIR_A	0x01<<3
+#define UART_CFGA_ASK_SIR		0x02<<3
+#define UART_CFGA_IRDA_SIR_B	0x03<<3
+#define UART_CFGA_IRDA_HDLC 	0x04<<3
+#define UART_CFGA_IRDA_4PPM 	0x05<<3
+#define UART_CFGA_CONSUMER		0x06<<3
+#define UART_CFGA_RAW_IR		0x07<<3
+#define UART_CFGA_OTHER		0x08<<3
+
+#define UART_IR_HDLC			0x04
+#define UART_IR_4PPM			0x01
+#define UART_IR_CONSUMER		0x02
+
+#define UART_CFGB_LOOPBACK		0x01<<5
+#define UART_CFGB_LPBCK_TX_CRC	0x01<<4
+#define UART_CFGB_NOWAIT		0x01<<3
+#define UART_CFGB_STRING_MOVE	0x01<<2
+#define UART_CFGB_DMA_BURST 	0x01<<1
+#define UART_CFGB_DMA_ENABLE	0x01
+
+#define UART_CFGB_COM		0x00<<6
+#define UART_CFGB_IR		0x01<<6
+#define UART_CFGB_AUX		0x02<<6
+#define UART_CFGB_INACTIVE		0x03<<6
+
+/* Register block 2 - Consumer IR - not used */
+
+/* Register block 3 - Identification Registers! */
+
+#define UART_ID_HIGH	0x00   /* 0x10 */
+#define UART_ID_LOW	0x01   /* 0xB8 */
+#define UART_CHIP_ID 	0x02   /* 0xF1 */
+#define UART_VERSION	0x03   /* 0x01 */
+#define UART_INTERFACE	0x04   /* low 4 = DMA, high 4 = IRQ */
+
+/* Register block 4 - IrDA */
+#define UART_CONTROL        0x00
+#define UART_BOF_COUNT_LO      0x01
+#define UART_BRICKWALL_CNT_LO 0x02
+#define UART_BRICKWALL_TX_CNT_HI   0x03
+#define UART_TX_SIZE_LO   0x04
+#define UART_RX_SIZE_HI   0x05
+#define UART_RX_SIZE_LO   0x06
+
+#define UART_1152     0x01<<7
+#define UART_CRC      0x01<<6
+
+/* For storing entries in the status FIFO */
+struct st_fifo_entry {
+	int status;
+	int len;
+};
+
+struct st_fifo {
+	struct st_fifo_entry entries[10];
+	int head;
+	int tail;
+	int len;
+};
+
+/* Private data for each instance */
+struct ircc_cb {
+	struct st_fifo st_fifo;
+
+	int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
+	int tx_len;          /* Number of frames in tx_buff */
+
+	struct irda_device idev;
+};
+
+#endif
diff --git a/include/net/irda/toshoboe.h b/include/net/irda/toshoboe.h
new file mode 100644
index 000000000..b2f5b953b
--- /dev/null
+++ b/include/net/irda/toshoboe.h
@@ -0,0 +1,165 @@
+/*********************************************************************
+ *                
+ * Filename:      toshoboe.h
+ * Version:       0.1
+ * Description:   Driver for the Toshiba OBOE (or type-O)
+ *                FIR Chipset. 
+ * Status:        Experimental.
+ * Author:        James McKenzie <james@fishsoup.dhs.org>
+ * Created at:    Sat May 8  12:35:27 1999
+ * 
+ *     Copyright (c) 1999 James McKenzie, All Rights Reserved.
+ *      
+ *     This program is free software; you can redistribute it and/or 
+ *     modify it under the terms of the GNU General Public License as 
+ *     published by the Free Software Foundation; either version 2 of 
+ *     the License, or (at your option) any later version.
+ *  
+ *     Neither James McKenzie nor Cambridge University admit liability nor
+ *     provide warranty for any of this software. This material is 
+ *     provided "AS-IS" and at no charge.
+ *
+ *     Applicable Models : Libretto 100CT. and many more
+ *
+ ********************************************************************/
+
+/*
+ * $Log: toshoboe.h,v $
+ * Revision 1.2  1999/05/09 01:43:08  root
+ * *** empty log message ***
+ *
+ * Revision 1.1  1999/05/09 01:25:58  root
+ * Initial revision
+ *
+ */
+
+#ifndef TOSHOBOE_H
+#define TOSHOBOE_H
+
+/* Registers */
+/*Receive and transmit task registers (read only) */
+#define OBOE_RCVT	(0x00+(self->base))
+#define OBOE_XMTT	(0x01+(self->base))
+#define OBOE_XMTT_OFFSET	0x40
+
+/*Page pointers to the TaskFile structure */
+#define OBOE_TFP2	(0x02+(self->base))
+#define OBOE_TFP0	(0x04+(self->base))
+#define OBOE_TFP1	(0x05+(self->base))
+
+/*Dunno */
+#define OBOE_REG_3	(0x03+(self->base))
+
+/*Number of tasks to use in Xmit and Recv queues */
+#define OBOE_NTR	(0x07+(self->base))
+#define OBOE_NTR_XMIT4	0x00
+#define OBOE_NTR_XMIT8	0x10
+#define OBOE_NTR_XMIT16	0x30
+#define OBOE_NTR_XMIT32	0x70
+#define OBOE_NTR_XMIT64	0xf0
+#define OBOE_NTR_RECV4	0x00
+#define OBOE_NTR_RECV8	0x01
+#define OBOE_NTR_RECV6	0x03
+#define OBOE_NTR_RECV32	0x07
+#define OBOE_NTR_RECV64	0x0f
+
+/* Dunno */
+#define OBOE_REG_9	(0x09+(self->base))
+
+/* Interrupt Status Register */
+#define OBOE_ISR	(0x0c+(self->base))
+#define OBOE_ISR_TXDONE	0x80
+#define OBOE_ISR_RXDONE	0x40
+#define OBOE_ISR_20	0x20
+#define OBOE_ISR_10	0x10
+#define OBOE_ISR_8	0x08         /*This is collision or parity or something */
+#define OBOE_ISR_4	0x08
+#define OBOE_ISR_2	0x08
+#define OBOE_ISR_1	0x08
+
+/*Dunno */
+#define OBOE_REG_D	(0x0d+(self->base))
+
+/*Register Lock Register */
+#define OBOE_LOCK	((self->base)+0x0e)
+
+
+
+/*Speed control registers */
+#define OBOE_PMDL	(0x10+(self->base))
+#define OBOE_PMDL_SIR	0x18
+#define OBOE_PMDL_MIR	0xa0
+#define OBOE_PMDL_FIR	0x40
+
+#define OBOE_SMDL	(0x18+(self->base))
+#define OBOE_SMDL_SIR	0x20
+#define OBOE_SMDL_MIR	0x01
+#define OBOE_SMDL_FIR	0x0f
+
+#define OBOE_UDIV	(0x19+(self->base))
+
+/*Dunno */
+#define OBOE_REG_11	(0x11+(self->base))
+
+/*Chip Reset Register */
+#define OBOE_RST	(0x15+(self->base))
+#define OBOE_RST_WRAP	0x8
+
+/*Dunno */
+#define OBOE_REG_1A	(0x1a+(self->base))
+#define OBOE_REG_1B	(0x1b+(self->base))
+
+/* The PCI ID of the OBOE chip */
+#ifndef PCI_DEVICE_ID_FIR701
+#define PCI_DEVICE_ID_FIR701 	0x0701
+#endif
+
+typedef unsigned int dword;
+typedef unsigned short int word;
+typedef unsigned char byte;
+typedef dword Paddr;
+
+struct OboeTask
+  {
+    __u16 len;
+    __u8 unused;
+    __u8 control;
+    __u32 buffer;
+  };
+
+#define OBOE_NTASKS 64
+
+struct OboeTaskFile
+  {
+    struct OboeTask recv[OBOE_NTASKS];
+    struct OboeTask xmit[OBOE_NTASKS];
+  };
+
+#define OBOE_TASK_BUF_LEN (sizeof(struct OboeTaskFile) << 1)
+
+/*These set the number of slots in use */
+#define TX_SLOTS	4
+#define RX_SLOTS	4
+
+/* You need also to change this, toshiba uses 4,8 and 4,4 */
+/* It makes no difference if you are only going to use ONETASK mode */
+/* remember each buffer use XX_BUF_SZ more _PHYSICAL_ memory */
+#define OBOE_NTR_VAL 	(OBOE_NTR_XMIT4 | OBOE_NTR_RECV4)
+
+struct toshoboe_cb
+  {
+    struct irda_device idev;    /*IRDA device */
+    struct pci_dev *pdev;       /*PCI device */
+    int base;                   /*IO base */
+    int txpending;              /*how many tx's are pending */
+    int txs, rxs;               /*Which slots are we at  */
+    void *taskfilebuf;          /*The unaligned taskfile buffer */
+    struct OboeTaskFile *taskfile;  /*The taskfile   */
+    void *xmit_bufs[TX_SLOTS];  /*The buffers   */
+    void *recv_bufs[RX_SLOTS];
+  };
+
+
+#endif
+
+