- Set caching mode for KSEG0 to cached-noncoherent for all machines.

  On some MIPS boxes the firmware doesn't do that for us.
- We still had two unprotected loads in the sys_sigrestore(2).  Use
  __get_user().
- Handle QED-style L1 caches != 16kb per cache correctly.
- Protect the cacheflush instructions for the signal trampoline
  just like the loads in __get_user().  Otherwise the following
  code will result in a nice "Can not handle kernel paging request"
  message:

    #include <signal.h>

    static void hurz(void)
    {
    }

    main()
    {
            signal(SIGSEGV, hurz);
            /* Chainsaw the stack pointer ...  */
            asm("move $29,%0" : :"r"(0x70000000));
            *(int *) 8 = 0;
    }

  With the fix applied I still get the error message.  The cause of
  this problem is that gas produces an __ex_table section with wrong
  contents.  Oh well, how good that I have a nice working post 2.8.1
  binutils version at home in good ol' Germany ...

2 files changed, 58 insertions, 8 deletions

diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index bf2340305..0dcd71a44 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -5,8 +5,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle
  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ *
+ * $Id: mipsregs.h,v 1.2 1997/09/12 22:25:34 ralf Exp $
  */
 #ifndef __ASM_MIPS_MIPSREGS_H
 #define __ASM_MIPS_MIPSREGS_H
@@ -160,7 +162,7 @@
  * Manipulate the status register.
  * Mostly used to access the interrupt bits.
  */
-#define BUILD_SET_CP0(name,register)                            \
+#define __BUILD_SET_CP0(name,register)                          \
 extern __inline__ unsigned int                                  \
 set_cp0_##name(unsigned int change, unsigned int new)           \
 {                                                               \
@@ -175,8 +177,9 @@ set_cp0_##name(unsigned int change, unsigned int new)           \
 	return res;                                             \
 }
 
-BUILD_SET_CP0(status,CP0_STATUS)
-BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
 
 #endif /* defined (__LANGUAGE_ASSEMBLY__) */
 
@@ -298,9 +301,18 @@ BUILD_SET_CP0(cause,CP0_CAUSE)
 /*
  * Bits in the coprozessor 0 config register.
  */
-#define CONFIG_DB		(1 <<  4)
-#define CONFIG_IB		(1 <<  5)
-#define CONFIG_SC		(1 << 17)
+#define CONFIG_CM_CACHABLE_NO_WA	0
+#define CONFIG_CM_CACHABLE_WA		1
+#define CONFIG_CM_UNCACHED		2
+#define CONFIG_CM_CACHABLE_NONCOHERENT	3
+#define CONFIG_CM_CACHABLE_CE		4
+#define CONFIG_CM_CACHABLE_COW		5
+#define CONFIG_CM_CACHABLE_CUW		6
+#define CONFIG_CM_CACHABLE_ACCELERATED	7
+#define CONFIG_CM_CMASK			7
+#define CONFIG_DB			(1 <<  4)
+#define CONFIG_IB			(1 <<  5)
+#define CONFIG_SC			(1 << 17)
 
 /*
  * R10000 performance counter definitions.
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index a7c835550..8813b7570 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -1,11 +1,14 @@
-/* $Id: r4kcache.h,v 1.2 1997/06/23 06:50:07 ralf Exp $
+/*
  * r4kcache.h: Inline assembly cache operations.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ *
+ * $Id: r4kcache.h,v 1.3 1997/09/12 22:25:35 ralf Exp $
  */
 #ifndef _MIPS_R4KCACHE_H
 #define _MIPS_R4KCACHE_H
 
+#include <asm/asm.h>
 #include <asm/cacheops.h>
 
 extern inline void flush_icache_line_indexed(unsigned long addr)
@@ -86,6 +89,41 @@ extern inline void flush_scache_line(unsigned long addr)
 		  "i" (Hit_Writeback_Inv_SD));
 }
 
+/*
+ * The next two are for badland addresses like signal trampolines.
+ */
+extern inline void protected_flush_icache_line(unsigned long addr)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n"
+		"1:\tcache %1,(%0)\n"
+		"2:\t.set mips0\n\t"
+		".set reorder\n\t"
+		".section\t__ex_table,\"a\"\n\t"
+		STR(PTR)"\t1b,2b\n\t"
+		".previous"
+		:
+		: "r" (addr),
+		  "i" (Hit_Invalidate_I));
+}
+
+extern inline void protected_writeback_dcache_line(unsigned long addr)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n"
+		"1:\tcache %1,(%0)\n"
+		"2:\t.set mips0\n\t"
+		".set reorder\n\t"
+		".section\t__ex_table,\"a\"\n\t"
+		STR(PTR)"\t1b,2b\n\t"
+		".previous"
+		:
+		: "r" (addr),
+		  "i" (Hit_Writeback_D));
+}
+
 extern inline void blast_dcache16(void)
 {
 	unsigned long start = KSEG0;