MIPS 64, day 2.

29 files changed, 3574 insertions, 188 deletions

diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 0c580f128..5733d0999 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -1,14 +1,13 @@
-/*
- * include/asm-mips/bitops.h
+/* $Id$
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1994 - 1997  Ralf Baechle (ralf@gnu.org)
+ * Copyright (c) 1994 - 1997, 1999  Ralf Baechle (ralf@gnu.org)
  */
-#ifndef __ASM_MIPS_BITOPS_H
-#define __ASM_MIPS_BITOPS_H
+#ifndef _ASM_BITOPS_H
+#define _ASM_BITOPS_H
 
 #include <linux/types.h>
 #include <asm/byteorder.h>		/* sigh ... */
@@ -26,11 +25,13 @@
 #define __bi_flags unsigned long flags
 #define __bi_cli() __cli()
 #define __bi_save_flags(x) __save_flags(x)
+#define __bi_save_and_cli(x) __save_and_cli(x)
 #define __bi_restore_flags(x) __restore_flags(x)
 #else
 #define __bi_flags
 #define __bi_cli()
 #define __bi_save_flags(x)
+#define __bi_save_and_cli(x)
 #define __bi_restore_flags(x)
 #endif /* __KERNEL__ */
 
@@ -154,8 +155,7 @@ extern __inline__ void set_bit(int nr, void * addr)
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	__bi_save_flags(flags);
-	__bi_cli();
+	__bi_save_and_cli(flags);
 	*a |= mask;
 	__bi_restore_flags(flags);
 }
@@ -168,8 +168,7 @@ extern __inline__ void clear_bit(int nr, void * addr)
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	__bi_save_flags(flags);
-	__bi_cli();
+	__bi_save_and_cli(flags);
 	*a &= ~mask;
 	__bi_restore_flags(flags);
 }
@@ -182,8 +181,7 @@ extern __inline__ void change_bit(int nr, void * addr)
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	__bi_save_flags(flags);
-	__bi_cli();
+	__bi_save_and_cli(flags);
 	*a ^= mask;
 	__bi_restore_flags(flags);
 }
@@ -196,8 +194,7 @@ extern __inline__ int test_and_set_bit(int nr, void * addr)
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	__bi_save_flags(flags);
-	__bi_cli();
+	__bi_save_and_cli(flags);
 	retval = (mask & *a) != 0;
 	*a |= mask;
 	__bi_restore_flags(flags);
@@ -213,8 +210,7 @@ extern __inline__ int test_and_clear_bit(int nr, void * addr)
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	__bi_save_flags(flags);
-	__bi_cli();
+	__bi_save_and_cli(flags);
 	retval = (mask & *a) != 0;
 	*a &= ~mask;
 	__bi_restore_flags(flags);
@@ -230,8 +226,7 @@ extern __inline__ int test_and_change_bit(int nr, void * addr)
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	__bi_save_flags(flags);
-	__bi_cli();
+	__bi_save_and_cli(flags);
 	retval = (mask & *a) != 0;
 	*a ^= mask;
 	__bi_restore_flags(flags);
@@ -459,7 +454,7 @@ extern __inline__ int ext2_set_bit(int nr,void * addr)
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
-	save_flags(flags); cli();
+	save_and_cli(flags);
 	retval = (mask & *ADDR) != 0;
 	*ADDR |= mask;
 	restore_flags(flags);
@@ -473,7 +468,7 @@ extern __inline__ int ext2_clear_bit(int nr, void * addr)
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
-	save_flags(flags); cli();
+	save_and_cli(flags);
 	retval = (mask & *ADDR) != 0;
 	*ADDR &= ~mask;
 	restore_flags(flags);
@@ -564,4 +559,4 @@ found_middle:
 #define minix_test_bit(nr,addr) test_bit(nr,addr)
 #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
 
-#endif /* __ASM_MIPS_BITOPS_H */
+#endif /* _ASM_BITOPS_H */
diff --git a/include/asm-mips/ds1286.h b/include/asm-mips/ds1286.h
index a4014bf64..2d60fb89d 100644
--- a/include/asm-mips/ds1286.h
+++ b/include/asm-mips/ds1286.h
@@ -1,16 +1,18 @@
-/* $Id: ds1286.h,v 1.1 1998/07/09 20:01:30 ralf Exp $
+/* $Id: ds1286.h,v 1.1 1998/07/10 01:14:55 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
  * mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
  * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
  * derived from Data Sheet, Copyright Motorola 1984 (!).
  * It was written to be part of the Linux operating system.
+ *
+ * Copyright (C) 1998, 1999 Ralf Baechle
  */
-/* permission is hereby granted to copy, modify and redistribute this code
- * in terms of the GNU Library General Public License, Version 2 or later,
- * at your option.
- */
-#ifndef _MC146818RTC_H
-#define _MC146818RTC_H
+#ifndef _ASM_DS1286_h
+#define _ASM_DS1286_h
 
 #include <asm/mc146818rtc.h>
 
@@ -66,4 +68,4 @@
 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
 #endif
 
-#endif /* _MC146818RTC_H */
+#endif /* _ASM_DS1286_h */
diff --git a/include/asm-mips/gfx.h b/include/asm-mips/gfx.h
index c76c3c2a2..7cda7a69f 100644
--- a/include/asm-mips/gfx.h
+++ b/include/asm-mips/gfx.h
@@ -1,4 +1,9 @@
-/*
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
  * This is the user-visible SGI GFX interface.
  *
  * This must be used verbatim into the GNU libc.  It does not include
@@ -6,6 +11,8 @@
  *
  * miguel@nuclecu.unam.mx
  */
+#ifndef _ASM_GFX_H
+#define _ASM_GFX_H
 
 /* The iocls, yes, they do not make sense, but such is life */
 #define GFX_BASE             100
@@ -45,3 +52,5 @@ extern void remove_mapping (struct task_struct *, unsigned long, unsigned long);
 extern void *vmalloc_uncached (unsigned long size);
 extern int vmap_page_range (unsigned long from, unsigned long size, unsigned long vaddr);
 #endif
+
+#endif /* _ASM_GFX_H */
diff --git a/include/asm-mips/keyboard.h b/include/asm-mips/keyboard.h
index 9b30c45c2..6748eb8c2 100644
--- a/include/asm-mips/keyboard.h
+++ b/include/asm-mips/keyboard.h
@@ -1,14 +1,13 @@
-/*
- * CPU specific parts of the keyboard driver
+/* $Id$
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * $Id: keyboard.h,v 1.12 1999/01/04 16:09:22 ralf Exp $
+ * Copyright (C) 1994 - 1999 Ralf Baechle
  */
-#ifndef __ASM_MIPS_KEYBOARD_H
-#define __ASM_MIPS_KEYBOARD_H
+#ifndef _ASM_KEYBOARD_H
+#define _ASM_KEYBOARD_H
 
 #ifdef __KERNEL__
 
@@ -73,4 +72,4 @@ extern struct kbd_ops *kbd_ops;
 
 #endif /* __KERNEL */
 
-#endif /* __ASM_MIPS_KEYBOARD_H */
+#endif /* _ASM_KEYBOARD_H */
diff --git a/include/asm-mips/mc146818rtc.h b/include/asm-mips/mc146818rtc.h
index 2b455951e..4ed782fc6 100644
--- a/include/asm-mips/mc146818rtc.h
+++ b/include/asm-mips/mc146818rtc.h
@@ -1,4 +1,4 @@
-/* $Id: mc146818rtc.h,v 1.3 1998/06/25 20:19:26 ralf Exp $
+/* $Id: mc146818rtc.h,v 1.2 1998/06/30 00:23:10 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -8,8 +8,8 @@
  *
  * Copyright (C) 1996, 1997, 1998 Ralf Baechle
  */
-#ifndef __ASM_MIPS_MC146818RTC_H
-#define __ASM_MIPS_MC146818RTC_H
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
 
 #include <asm/io.h>
 
@@ -43,4 +43,4 @@ struct rtc_ops {
 
 extern struct rtc_ops *rtc_ops;
 
-#endif /* __ASM_MIPS_MC146818RTC_H */
+#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-mips/ng1.h b/include/asm-mips/ng1.h
index 370ac27ad..7c7104415 100644
--- a/include/asm-mips/ng1.h
+++ b/include/asm-mips/ng1.h
@@ -1,7 +1,13 @@
-/*
- * SGI/Newport video card ioctl definitions
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
+ * SGI/Newport video card ioctl definitions
  */
+#ifndef _ASM_NG1_H
+#define _ASM_NG1_H
 
 typedef struct {
         int flags;
@@ -47,4 +53,4 @@ struct ng1_setgammaramp_args {
         unsigned char blue  [256];
 };
 
-
+#endif /* _ASM_NG1_H */
diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h
index 8a68d5b98..622e1e977 100644
--- a/include/asm-mips/unaligned.h
+++ b/include/asm-mips/unaligned.h
@@ -1,16 +1,16 @@
-/*
- * Inline functions to do unaligned accesses.
+/* $Id$
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996 by Ralf Baechle
+ * Copyright (C) 1996, 1999 by Ralf Baechle
  */
-#ifndef __ASM_MIPS_UNALIGNED_H
-#define __ASM_MIPS_UNALIGNED_H
+#ifndef _ASM_UNALIGNED_H
+#define _ASM_UNALIGNED_H
 
-#include <asm/string.h>
+extern void __get_unaligned_bad_length(void);
+extern void __put_unaligned_bad_length(void);
 
 /*
  * Load quad unaligned.
@@ -94,18 +94,21 @@ extern inline unsigned long __get_unaligned(const void *ptr, size_t size)
 {
 	unsigned long val;
 	switch (size) {
-	      case 1:
+	case 1:
 		val = *(const unsigned char *)ptr;
 		break;
-	      case 2:
+	case 2:
 		val = ldw_u((const unsigned short *)ptr);
 		break;
-	      case 4:
+	case 4:
 		val = ldl_u((const unsigned int *)ptr);
 		break;
-	      case 8:
+	case 8:
 		val = ldq_u((const unsigned long long *)ptr);
 		break;
+	default:
+		__get_unaligned_bad_length();
+		break;
 	}
 	return val;
 }
@@ -113,18 +116,21 @@ extern inline unsigned long __get_unaligned(const void *ptr, size_t size)
 extern inline void __put_unaligned(unsigned long val, void *ptr, size_t size)
 {
 	switch (size) {
-	      case 1:
+	case 1:
 		*(unsigned char *)ptr = (val);
-	        break;
-	      case 2:
+		break;
+	case 2:
 		stw_u(val, (unsigned short *)ptr);
 		break;
-	      case 4:
+	case 4:
 		stl_u(val, (unsigned int *)ptr);
 		break;
-	      case 8:
+	case 8:
 		stq_u(val, (unsigned long long *)ptr);
 		break;
+	default:
+		__put_unaligned_bad_length();
+		break;
 	}
 }
 
@@ -136,4 +142,4 @@ extern inline void __put_unaligned(unsigned long val, void *ptr, size_t size)
 #define put_unaligned(x,ptr) \
 	__put_unaligned((unsigned long)(x), (ptr), sizeof(*(ptr)))
 
-#endif /* __ASM_MIPS_UNALIGNED_H */
+#endif /* _ASM_UNALIGNED_H */
diff --git a/include/asm-mips64/bitops.h b/include/asm-mips64/bitops.h
index 69ee4419d..a9edabe72 100644
--- a/include/asm-mips64/bitops.h
+++ b/include/asm-mips64/bitops.h
@@ -1,12 +1,11 @@
-/*
- * include/asm-mips/bitops.h
+/* $Id$
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (c) 1994 - 1999  Ralf Baechle (ralf@gnu.org)
- * Copyright (c) 1999  Silicon Graphics
+ * Copyright (c) 1999  Silicon Graphics, Inc.
  */
 #ifndef _ASM_BITOPS_H
 #define _ASM_BITOPS_H
@@ -15,114 +14,19 @@
 #include <linux/byteorder/swab.h>		/* sigh ... */
 
 #ifdef __KERNEL__
+#include <asm/system.h>
 #include <asm/sgidefs.h>
 #include <asm/mipsregs.h>
 #endif
 
-/* Note that the bit operations are defined on arrays of 32 bit sized
-   elements.  */
-extern __inline__ void set_bit(int nr, void *addr);
-extern __inline__ void clear_bit(int nr, void *addr);
-extern __inline__ void change_bit(int nr, void *addr);
-extern __inline__ int test_and_set_bit(int nr, void *addr);
-extern __inline__ int test_and_clear_bit(int nr, void *addr);
-extern __inline__ int test_and_change_bit(int nr, void *addr);
-
-extern __inline__ int test_bit(int nr, const void *addr);
-#ifndef __MIPSEB__
-extern __inline__ int find_first_zero_bit (void *addr, unsigned size);
-#endif
-extern __inline__ int find_next_zero_bit (void * addr, int size, int offset);
-extern __inline__ unsigned long ffz(unsigned long word);
-
-#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
-
-/*
- * These functions for MIPS ISA > 1 are interrupt and SMP proof and
- * interrupt friendly
+/* This gets exported to userland, so we need to have a MIPS I versions
+ * as well ...
  */
 
-extern __inline__ void set_bit(int nr, void *addr)
-{
-	int	mask, mw;
-
-	addr += ((nr >> 3) & ~3);
-	mask = 1 << (nr & 0x1f);
-	do {
-		mw = load_linked(addr);
-	} while (!store_conditional(addr, mw|mask));
-}
-
-extern __inline__ void clear_bit(int nr, void *addr)
-{
-	int	mask, mw;
-
-	addr += ((nr >> 3) & ~3);
-	mask = 1 << (nr & 0x1f);
-	do {
-		mw = load_linked(addr);
-		}
-	while (!store_conditional(addr, mw & ~mask));
-}
-
-extern __inline__ void change_bit(int nr, void *addr)
-{
-	int	mask, mw;
-
-	addr += ((nr >> 3) & ~3);
-	mask = 1 << (nr & 0x1f);
-	do {
-		mw = load_linked(addr);
-	} while (!store_conditional(addr, mw ^ mask));
-}
-
-extern __inline__ int test_and_set_bit(int nr, void *addr)
-{
-	int	mask, retval, mw;
-
-	addr += ((nr >> 3) & ~3);
-	mask = 1 << (nr & 0x1f);
-	do {
-		mw = load_linked(addr);
-		retval = (mask & mw) != 0;
-	} while (!store_conditional(addr, mw|mask));
-
-	return retval;
-}
-
-extern __inline__ int test_and_clear_bit(int nr, void *addr)
-{
-	int	mask, retval, mw;
-
-	addr += ((nr >> 3) & ~3);
-	mask = 1 << (nr & 0x1f);
-	do {
-		mw = load_linked(addr);
-		retval = (mask & mw) != 0;
-		}
-	while (!store_conditional(addr, mw & ~mask));
-
-	return retval;
-}
-
-extern __inline__ int test_and_change_bit(int nr, void *addr)
-{
-	int	mask, retval, mw;
-
-	addr += ((nr >> 3) & ~3);
-	mask = 1 << (nr & 0x1f);
-	do {
-		mw = load_linked(addr);
-		retval = (mask & mw) != 0;
-	} while (!store_conditional(addr, mw ^ mask));
-
-	return retval;
-}
+#ifndef __KERNEL__
 
-#else /* MIPS I */
-
-extern __inline__ void set_bit(int nr, void * addr)
+extern __inline__ void
+set_bit(unsigned long nr, void * addr)
 {
 	int	mask;
 	int	*a = addr;
@@ -132,7 +36,8 @@ extern __inline__ void set_bit(int nr, void * addr)
 	*a |= mask;
 }
 
-extern __inline__ void clear_bit(int nr, void * addr)
+extern __inline__ void
+clear_bit(unsigned long nr, void * addr)
 {
 	int	mask;
 	int	*a = addr;
@@ -142,7 +47,8 @@ extern __inline__ void clear_bit(int nr, void * addr)
 	*a &= ~mask;
 }
 
-extern __inline__ void change_bit(int nr, void * addr)
+extern __inline__ void
+change_bit(unsigned long nr, void * addr)
 {
 	int	mask;
 	int	*a = addr;
@@ -152,7 +58,8 @@ extern __inline__ void change_bit(int nr, void * addr)
 	*a ^= mask;
 }
 
-extern __inline__ int test_and_set_bit(int nr, void * addr)
+extern __inline__ unsigned long
+test_and_set_bit(unsigned long nr, void * addr)
 {
 	int	mask, retval;
 	int	*a = addr;
@@ -165,7 +72,8 @@ extern __inline__ int test_and_set_bit(int nr, void * addr)
 	return retval;
 }
 
-extern __inline__ int test_and_clear_bit(int nr, void * addr)
+extern __inline__ unsigned long
+test_and_clear_bit(unsigned long nr, void * addr)
 {
 	int	mask, retval;
 	int	*a = addr;
@@ -178,7 +86,8 @@ extern __inline__ int test_and_clear_bit(int nr, void * addr)
 	return retval;
 }
 
-extern __inline__ int test_and_change_bit(int nr, void * addr)
+extern __inline__ unsigned long
+test_and_change_bit(unsigned long nr, void * addr)
 {
 	int	mask, retval;
 	int	*a = addr;
@@ -191,18 +100,142 @@ extern __inline__ int test_and_change_bit(int nr, void * addr)
 	return retval;
 }
 
-#endif /* MIPS I */
+#else /* __KERNEL__ */
+
+/*
+ * These functions for MIPS ISA > 1 are interrupt and SMP proof and
+ * interrupt friendly
+ */
+
+extern __inline__ void
+set_bit(unsigned long nr, void *addr)
+{
+	unsigned int *m = ((unsigned int *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# set_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqzl\t%0,1b\n\t"
+		" ll\t%0, %1\n\t"
+		".set\treorder"
+		:"=&r" (temp), "=m" (*m)
+		:"ir" (1UL << (nr & 31)), "m" (*m));
+}
+
+extern __inline__ void
+clear_bit(unsigned long nr, void *addr)
+{
+	unsigned int *m = ((unsigned int *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# clear_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"and\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqzl\t%0,1b\n\t"
+		" ll\t%0, %1\n\t"
+		".set\treorder"
+		:"=&r" (temp), "=m" (*m)
+		:"ir" (~(1UL << (nr & 31))), "m" (*m));
+}
+
+extern __inline__ void
+change_bit(unsigned long nr, void *addr)
+{
+	unsigned int *m = ((unsigned int *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# change_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"xor\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqzl\t%0,1b\n\t"
+		" ll\t%0, %1\n\t"
+		".set\treorder"
+		:"=&r" (temp), "=m" (*m)
+		:"ir" (1UL << (nr & 31)), "m" (*m));
+}
+
+extern __inline__ unsigned long
+test_and_set_bit(unsigned long nr, void *addr)
+{
+	unsigned int *m = ((unsigned int *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_set_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%2, %0, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2,1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		:"=&r" (temp), "=m" (*m), "=&r" (res)
+		:"r" (1UL << (nr & 31)), "m" (*m));
+
+	return res != 0;
+}
+
+extern __inline__ unsigned long
+test_and_clear_bit(unsigned long nr, void *addr)
+{
+	unsigned int *m = ((unsigned int *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_clear_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%2, %0, %3\n\t"
+		"xor\t%2, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2,1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		:"=&r" (temp), "=m" (*m), "=&r" (res)
+		:"r" (1UL << (nr & 31)), "m" (*m));
+
+	return res != 0;
+}
 
-extern __inline__ int test_bit(int nr, const void *addr)
+extern __inline__ unsigned long
+test_and_change_bit(unsigned long nr, void *addr)
 {
-	return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
+	unsigned int *m = ((unsigned int *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_change_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"xor\t%2, %0, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2,1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		:"=&r" (temp), "=m" (*m), "=&r" (res)
+		:"r" (1UL << (nr & 31)), "m" (*m));
+
+	return res != 0;
+}
+
+#endif /* __KERNEL__ */
+
+extern __inline__ unsigned long
+test_bit(int nr, volatile void * addr)
+{
+	return 1UL & (((const int *) addr)[nr >> 5] >> (nr & 31));
 }
 
 #ifndef __MIPSEB__
 
 /* Little endian versions. */
 
-extern __inline__ int find_first_zero_bit (void *addr, unsigned size)
+extern __inline__ int
+find_first_zero_bit (void *addr, unsigned size)
 {
 	unsigned long dummy;
 	int res;
@@ -250,7 +283,8 @@ extern __inline__ int find_first_zero_bit (void *addr, unsigned size)
 	return res;
 }
 
-extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+extern __inline__ int
+find_next_zero_bit (void * addr, int size, int offset)
 {
 	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
 	int set = 0, bit = offset & 31, res;
@@ -297,7 +331,8 @@ extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
  * ffz = Find First Zero in word. Undefined if no zero exists,
  * so code should check against ~0UL first..
  */
-extern __inline__ unsigned long ffz(unsigned long word)
+extern __inline__ unsigned long
+ffz(unsigned long word)
 {
 	unsigned int	__res;
 	unsigned int	mask = 1;
@@ -338,20 +373,20 @@ extern __inline__ unsigned long ffz(unsigned long word)
 
 #define hweight32(x) generic_hweight32(x)
 #define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
+#define hweight8(x)  generic_hweight8(x)
 
 #endif /* __KERNEL__ */
 
 #ifdef __MIPSEB__
-/* For now I steal the Sparc C versions, no need for speed, just need to
- * get it working.
- */
-/* find_next_zero_bit() finds the first zero bit in a bit string of length
+
+/*
+ * find_next_zero_bit() finds the first zero bit in a bit string of length
  * 'size' bits, starting the search at bit 'offset'. This is largely based
  * on Linus's ALPHA routines, which are pretty portable BTW.
  */
 
-extern __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+extern __inline__ int
+find_next_zero_bit(void *addr, int size, int offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
@@ -395,35 +430,39 @@ found_middle:
 /* Now for the ext2 filesystem bit operations and helper routines. */
 
 #ifdef __MIPSEB__
-extern __inline__ int ext2_set_bit(int nr,void * addr)
+
+extern inline int
+ext2_set_bit(int nr,void * addr)
 {
 	int		mask, retval, flags;
 	unsigned char	*ADDR = (unsigned char *) addr;
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
-	save_flags(flags); cli();
+	save_and_cli(flags);
 	retval = (mask & *ADDR) != 0;
 	*ADDR |= mask;
 	restore_flags(flags);
 	return retval;
 }
 
-extern __inline__ int ext2_clear_bit(int nr, void * addr)
+extern inline int
+ext2_clear_bit(int nr, void * addr)
 {
 	int		mask, retval, flags;
 	unsigned char	*ADDR = (unsigned char *) addr;
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
-	save_flags(flags); cli();
+	save_and_cli(flags);
 	retval = (mask & *ADDR) != 0;
 	*ADDR &= ~mask;
 	restore_flags(flags);
 	return retval;
 }
 
-extern __inline__ int ext2_test_bit(int nr, const void * addr)
+extern inline int
+ext2_test_bit(int nr, const void * addr)
 {
 	int			mask;
 	const unsigned char	*ADDR = (const unsigned char *) addr;
@@ -436,7 +475,8 @@ extern __inline__ int ext2_test_bit(int nr, const void * addr)
 #define ext2_find_first_zero_bit(addr, size) \
         ext2_find_next_zero_bit((addr), (size), 0)
 
-extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+extern inline unsigned long
+ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
diff --git a/include/asm-mips64/dma.h b/include/asm-mips64/dma.h
new file mode 100644
index 000000000..3a3c1ec2b
--- /dev/null
+++ b/include/asm-mips64/dma.h
@@ -0,0 +1,303 @@
+/* $Id$
+ *
+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ *
+ * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
+ * and can only be used for expansion cards. Onboard DMA controllers, such
+ * as the R4030 on Jazz boards behave totally different!
+ */
+
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#include <linux/config.h>
+#include <asm/io.h>			/* need byte IO */
+#include <asm/spinlock.h>		/* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+
+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
+#define dma_outb	outb_p
+#else
+#define dma_outb	outb
+#endif
+
+#define dma_inb		inb
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.  
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0   
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
+ *
+ */
+
+#define MAX_DMA_CHANNELS	8
+
+/*
+ * The maximum address in KSEG0 that we can perform a DMA transfer to on this
+ * platform.  This describes only the PC style part of the DMA logic like on
+ * Deskstations or Acer PICA but not the much more versatile DMA logic used
+ * for the local devices on Acer PICA or Magnums.
+ */
+#ifndef CONFIG_SGI
+#define MAX_DMA_ADDRESS		(PAGE_OFFSET + 0x01000000)
+#else
+#define MAX_DMA_ADDRESS		(~0UL)
+#endif
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG		0x08	/* command register (w) */
+#define DMA1_STAT_REG		0x08	/* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
+#define DMA1_MODE_REG		0x0B	/* mode register (w) */
+#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG		0xD0	/* command register (w) */
+#define DMA2_STAT_REG		0xD0	/* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
+#define DMA2_MODE_REG		0xD6	/* mode register (w) */
+#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0              0x00    /* DMA address registers */
+#define DMA_ADDR_1              0x02
+#define DMA_ADDR_2              0x04
+#define DMA_ADDR_3              0x06
+#define DMA_ADDR_4              0xC0
+#define DMA_ADDR_5              0xC4
+#define DMA_ADDR_6              0xC8
+#define DMA_ADDR_7              0xCC
+
+#define DMA_CNT_0               0x01    /* DMA count registers */
+#define DMA_CNT_1               0x03
+#define DMA_CNT_2               0x05
+#define DMA_CNT_3               0x07
+#define DMA_CNT_4               0xC2
+#define DMA_CNT_5               0xC6
+#define DMA_CNT_6               0xCA
+#define DMA_CNT_7               0xCE
+
+#define DMA_PAGE_0              0x87    /* DMA page registers */
+#define DMA_PAGE_1              0x83
+#define DMA_PAGE_2              0x81
+#define DMA_PAGE_3              0x82
+#define DMA_PAGE_5              0x8B
+#define DMA_PAGE_6              0x89
+#define DMA_PAGE_7              0x8A
+
+#define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&dma_spin_lock, flags);
+	return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+	spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+	if (dmanr<=3)
+		dma_outb(dmanr,  DMA1_MASK_REG);
+	else
+		dma_outb(dmanr & 3,  DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+	if (dmanr<=3)
+		dma_outb(dmanr | 4,  DMA1_MASK_REG);
+	else
+		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+	if (dmanr<=3)
+		dma_outb(0,  DMA1_CLEAR_FF_REG);
+	else
+		dma_outb(0,  DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+	if (dmanr<=3)
+		dma_outb(mode | dmanr,  DMA1_MODE_REG);
+	else
+		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+	switch(dmanr) {
+		case 0:
+			dma_outb(pagenr, DMA_PAGE_0);
+			break;
+		case 1:
+			dma_outb(pagenr, DMA_PAGE_1);
+			break;
+		case 2:
+			dma_outb(pagenr, DMA_PAGE_2);
+			break;
+		case 3:
+			dma_outb(pagenr, DMA_PAGE_3);
+			break;
+		case 5:
+			dma_outb(pagenr & 0xfe, DMA_PAGE_5);
+			break;
+		case 6:
+			dma_outb(pagenr & 0xfe, DMA_PAGE_6);
+			break;
+		case 7:
+			dma_outb(pagenr & 0xfe, DMA_PAGE_7);
+			break;
+	}
+}
+
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+	set_dma_page(dmanr, a>>16);
+	if (dmanr <= 3)  {
+	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+	}  else  {
+	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+	}
+}
+
+
+/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+	if (dmanr <= 3)  {
+	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+        } else {
+	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+        }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+	unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
+					 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
+
+	/* using short to get 16-bit wrap around */
+	unsigned short count;
+
+	count = 1 + dma_inb(io_port);
+	count += dma_inb(io_port) << 8;
+	
+	return (dmanr<=3)? count : (count<<1);
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr);	/* release it again */
+
+#endif /* _ASM_DMA_H */
diff --git a/include/asm-mips64/ds1286.h b/include/asm-mips64/ds1286.h
new file mode 100644
index 000000000..bf279ebcb
--- /dev/null
+++ b/include/asm-mips64/ds1286.h
@@ -0,0 +1,71 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
+ * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
+ * derived from Data Sheet, Copyright Motorola 1984 (!).
+ * It was written to be part of the Linux operating system.
+ *
+ * Copyright (C) 1998, 1999 Ralf Baechle
+ */
+#ifndef _ASM_DS1286_h
+#define _ASM_DS1286_h
+
+#include <asm/mc146818rtc.h>
+
+/**********************************************************************
+ * register summary
+ **********************************************************************/
+#define RTC_HUNDREDTH_SECOND	0
+#define RTC_SECONDS		1
+#define RTC_MINUTES		2
+#define RTC_MINUTES_ALARM	3
+#define RTC_HOURS		4
+#define RTC_HOURS_ALARM		5
+#define RTC_DAY			6
+#define RTC_DAY_ALARM		7
+#define RTC_DATE		8
+#define RTC_MONTH		9
+#define RTC_YEAR		10
+#define RTC_CMD			11
+#define RTC_WHSEC		12
+#define RTC_WSEC		13
+#define RTC_UNUSED		14
+
+/* RTC_*_alarm is always true if 2 MSBs are set */
+# define RTC_ALARM_DONT_CARE 	0xC0
+
+
+/*
+ * Bits in the month register
+ */
+#define RTC_EOSC		0x80
+#define RTC_ESQW		0x40
+
+/*
+ * Bits in the Command register
+ */
+#define RTC_TDF			0x01
+#define RTC_WAF			0x02
+#define RTC_TDM			0x04
+#define RTC_WAM			0x08
+#define RTC_PU_LVL		0x10
+#define RTC_IBH_LO		0x20
+#define RTC_IPSW		0x40
+#define RTC_TE			0x80
+
+/*
+ * Conversion between binary and BCD.
+ */
+#ifndef BCD_TO_BIN
+#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
+#endif
+
+#ifndef BIN_TO_BCD
+#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
+#endif
+
+#endif /* _ASM_DS1286_h */
diff --git a/include/asm-mips64/gfx.h b/include/asm-mips64/gfx.h
new file mode 100644
index 000000000..7cda7a69f
--- /dev/null
+++ b/include/asm-mips64/gfx.h
@@ -0,0 +1,56 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This is the user-visible SGI GFX interface.
+ *
+ * This must be used verbatim into the GNU libc.  It does not include
+ * any kernel-only bits on it.  
+ *
+ * miguel@nuclecu.unam.mx
+ */
+#ifndef _ASM_GFX_H
+#define _ASM_GFX_H
+
+/* The iocls, yes, they do not make sense, but such is life */
+#define GFX_BASE             100
+#define GFX_GETNUM_BOARDS    (GFX_BASE + 1)
+#define GFX_GETBOARD_INFO    (GFX_BASE + 2)
+#define GFX_ATTACH_BOARD     (GFX_BASE + 3)
+#define GFX_DETACH_BOARD     (GFX_BASE + 4)
+#define GFX_IS_MANAGED       (GFX_BASE + 5)
+
+#define GFX_MAPALL           (GFX_BASE + 10)
+#define GFX_LABEL            (GFX_BASE + 11)
+
+#define GFX_INFO_NAME_SIZE  16
+#define GFX_INFO_LABEL_SIZE 16
+
+struct gfx_info {
+	char name  [GFX_INFO_NAME_SIZE];  /* board name */
+	char label [GFX_INFO_LABEL_SIZE]; /* label name */
+	unsigned short int xpmax, ypmax;  /* screen resolution */
+	unsigned int lenght;	          /* size of a complete gfx_info for this board */
+};
+
+struct gfx_getboardinfo_args {
+	unsigned int board;     /* board number.  starting from zero */
+	void *buf;              /* pointer to gfx_info */
+	unsigned int len;       /* buffer size of buf */
+};
+
+struct gfx_attach_board_args {
+	unsigned int board;	/* board number, starting from zero */
+	void        *vaddr;	/* address where the board registers should be mapped */
+};
+
+#ifdef __KERNEL__
+/* umap.c */
+extern void remove_mapping (struct task_struct *, unsigned long, unsigned long);
+extern void *vmalloc_uncached (unsigned long size);
+extern int vmap_page_range (unsigned long from, unsigned long size, unsigned long vaddr);
+#endif
+
+#endif /* _ASM_GFX_H */
diff --git a/include/asm-mips64/hardirq.h b/include/asm-mips64/hardirq.h
new file mode 100644
index 000000000..3bcdae01a
--- /dev/null
+++ b/include/asm-mips64/hardirq.h
@@ -0,0 +1,39 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_HARDIRQ_H
+#define _ASM_HARDIRQ_H
+
+#include <linux/tasks.h>
+
+extern unsigned int local_irq_count[NR_CPUS];
+
+/*
+ * Are we in an interrupt context? Either doing bottom half
+ * or hardware interrupt processing?
+ */
+#define in_interrupt() ({ int __cpu = smp_processor_id(); \
+	(local_irq_count[__cpu] + local_bh_count[__cpu] != 0); })
+
+#ifndef __SMP__
+
+#define hardirq_trylock(cpu)	(local_irq_count[cpu] == 0)
+#define hardirq_endlock(cpu)	do { } while (0)
+
+#define hardirq_enter(cpu)	(local_irq_count[cpu]++)
+#define hardirq_exit(cpu)	(local_irq_count[cpu]--)
+
+#define synchronize_irq()	barrier();
+
+#else
+
+#error No habla MIPS SMP
+
+#endif /* __SMP__ */
+#endif /* _ASM_HARDIRQ_H */
diff --git a/include/asm-mips64/irq.h b/include/asm-mips64/irq.h
new file mode 100644
index 000000000..5baa58f6e
--- /dev/null
+++ b/include/asm-mips64/irq.h
@@ -0,0 +1,28 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995 - 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#define NR_IRQS 64
+
+#define TIMER_IRQ 0
+
+extern int (*irq_cannonicalize)(int irq);
+
+struct irqaction;
+extern int i8259_setup_irq(int irq, struct irqaction * new);
+extern void disable_irq(unsigned int);
+extern void enable_irq(unsigned int);
+
+/* Machine specific interrupt initialization  */
+extern void (*irq_setup)(void);
+
+#endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips64/keyboard.h b/include/asm-mips64/keyboard.h
new file mode 100644
index 000000000..6748eb8c2
--- /dev/null
+++ b/include/asm-mips64/keyboard.h
@@ -0,0 +1,75 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999 Ralf Baechle
+ */
+#ifndef _ASM_KEYBOARD_H
+#define _ASM_KEYBOARD_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <asm/bootinfo.h>
+
+#define DISABLE_KBD_DURING_INTERRUPTS 0
+
+extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
+extern int pckbd_getkeycode(unsigned int scancode);
+extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
+			   char raw_mode);
+extern char pckbd_unexpected_up(unsigned char keycode);
+extern void pckbd_leds(unsigned char leds);
+extern void pckbd_init_hw(void);
+extern unsigned char pckbd_sysrq_xlate[128];
+
+#define kbd_setkeycode		pckbd_setkeycode
+#define kbd_getkeycode		pckbd_getkeycode
+#define kbd_translate		pckbd_translate
+#define kbd_unexpected_up	pckbd_unexpected_up
+#define kbd_leds		pckbd_leds
+#define kbd_init_hw		pckbd_init_hw
+#define kbd_sysrq_xlate         pckbd_sysrq_xlate
+
+#define SYSRQ_KEY 0x54
+
+/* Some stoneage hardware needs delays after some operations.  */
+#define kbd_pause() do { } while(0)
+
+struct kbd_ops {
+	/* Keyboard driver resource allocation  */
+	void (*kbd_request_region)(void);
+	int (*kbd_request_irq)(void (*handler)(int, void *, struct pt_regs *));
+
+	/* PSaux driver resource managment  */
+	int (*aux_request_irq)(void (*handler)(int, void *, struct pt_regs *));
+	void (*aux_free_irq)(void);
+
+	/* Methods to access the keyboard processor's I/O registers  */
+	unsigned char (*kbd_read_input)(void);
+	void (*kbd_write_output)(unsigned char val);
+	void (*kbd_write_command)(unsigned char val);
+	unsigned char (*kbd_read_status)(void);
+};
+
+extern struct kbd_ops *kbd_ops;
+
+/* Do the actual calls via kbd_ops vector  */
+#define kbd_request_region() kbd_ops->kbd_request_region()
+#define kbd_request_irq(handler) kbd_ops->kbd_request_irq(handler)
+
+#define aux_request_irq(hand, dev_id) kbd_ops->aux_request_irq(hand)
+#define aux_free_irq(dev_id) kbd_ops->aux_free_irq()
+
+#define kbd_read_input() kbd_ops->kbd_read_input()
+#define kbd_write_output(val) kbd_ops->kbd_write_output(val)
+#define kbd_write_command(val) kbd_ops->kbd_write_command(val)
+#define kbd_read_status() kbd_ops->kbd_read_status()
+
+#endif /* __KERNEL */
+
+#endif /* _ASM_KEYBOARD_H */
diff --git a/include/asm-mips64/linux_logo.h b/include/asm-mips64/linux_logo.h
new file mode 100644
index 000000000..a6a2816e7
--- /dev/null
+++ b/include/asm-mips64/linux_logo.h
@@ -0,0 +1,941 @@
+/* $Id$
+ *
+ * include/asm-mips/linux_logo.h: This is a linux logo
+ *                                to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * You can put anything here, but:
+ * LINUX_LOGO_COLORS has to be less than 224
+ * image size has to be 80x80
+ * values have to start from 0x20
+ * (i.e. RGB(linux_logo_red[0],
+ *	     linux_logo_green[0],
+ *	     linux_logo_blue[0]) is color 0x20)
+ * BW image has to be 80x80 as well, with MS bit
+ * on the left
+ * Serial_console ascii image can be any size,
+ * but should contain %s to display the version
+ */
+ 
+#include <linux/init.h>
+#include <linux/version.h>
+
+#define linux_logo_banner "Linux/MIPS64 version " UTS_RELEASE
+
+#define LINUX_LOGO_COLORS 212
+
+#ifdef INCLUDE_LINUX_LOGO_DATA
+
+unsigned char linux_logo_red[] __initdata = {
+  0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0,
+  0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4,
+  0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED,
+  0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4,
+  0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA,
+  0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26,
+  0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5,
+  0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F,
+  0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE,
+  0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB,
+  0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC,
+  0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6,
+  0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E,
+  0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE,
+  0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF,
+  0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A,
+  0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE,
+  0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E,
+  0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9,
+  0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3,
+  0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8,
+  0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36,
+  0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A,
+  0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6,
+  0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6,
+  0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3,
+  0xED, 0xDC, 0xF4, 0x72
+};
+
+unsigned char linux_logo_green[] __initdata = {
+  0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4,
+  0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94,
+  0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4,
+  0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77,
+  0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2,
+  0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12,
+  0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC,
+  0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06,
+  0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA,
+  0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD,
+  0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D,
+  0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6,
+  0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E,
+  0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6,
+  0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB,
+  0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B,
+  0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B,
+  0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E,
+  0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91,
+  0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72,
+  0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92,
+  0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A,
+  0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72,
+  0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6,
+  0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79,
+  0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D,
+  0xAE, 0xA4, 0xD4, 0x56
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+  0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78,
+  0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D,
+  0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22,
+  0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A,
+  0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C,
+  0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04,
+  0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B,
+  0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09,
+  0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4,
+  0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15,
+  0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C,
+  0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10,
+  0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C,
+  0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C,
+  0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91,
+  0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C,
+  0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11,
+  0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C,
+  0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14,
+  0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09,
+  0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64,
+  0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04,
+  0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C,
+  0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4,
+  0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07,
+  0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17,
+  0x17, 0x18, 0x21, 0x24
+};
+
+unsigned char linux_logo[] __initdata = {
+  0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
+  0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C,
+  0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA,
+  0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9,
+  0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A,
+  0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85,
+  0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
+  0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA,
+  0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A,
+  0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
+  0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
+  0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C,
+  0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
+  0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA,
+  0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C,
+  0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
+  0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA,
+  0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA,
+  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
+  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D,
+  0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
+  0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C,
+  0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85,
+  0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85,
+  0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9,
+  0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA,
+  0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85,
+  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF,
+  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95,
+  0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
+  0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20,
+  0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA,
+  0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
+  0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA,
+  0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
+  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
+  0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9,
+  0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC,
+  0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C,
+  0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA,
+  0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
+  0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
+  0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF,
+  0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC,
+  0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C,
+  0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9,
+  0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA,
+  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48,
+  0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA,
+  0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
+  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
+  0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF,
+  0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
+  0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC,
+  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20,
+  0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85,
+  0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C,
+  0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
+  0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9,
+  0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC,
+  0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41,
+  0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85,
+  0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C,
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+  0xD9, 0x95, 0xAC, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
+  0x7D, 0xD6, 0xD6, 0xD9, 0xAC, 0xAF, 0x8A, 0xBC,
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+  0xD9, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
+  0x85, 0xD9, 0xAF, 0xDA, 0xDA, 0x85, 0xAC, 0x21,
+  0xB2, 0x2A, 0xBA, 0x57, 0x2E, 0x2E, 0x2E, 0x7A,
+  0x32, 0x62, 0x8B, 0x4B, 0x8B, 0x4B, 0x4B, 0x4B,
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+  0x62, 0x62, 0xA6, 0x2A, 0xD9, 0xD9, 0xD9, 0xD9,
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+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
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+  0x2C, 0x8C, 0xBA, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
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+  0x3E, 0x8B, 0x32, 0xC9, 0x22, 0x68, 0x88, 0x33,
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+  0x2C, 0xDA, 0x40, 0xEF, 0x62, 0x62, 0x4B, 0x4B,
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+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
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+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
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+  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
+  0xD9, 0x95, 0x21, 0x48, 0xD6, 0xAC, 0x85, 0x85,
+  0xAF, 0xB6, 0x5D, 0x2E, 0x32, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x2E, 0x45, 0xDE,
+  0xDA, 0x5C, 0xE8, 0x5C, 0xE8, 0xE8, 0x5C, 0xE8,
+  0x5C, 0x5C, 0xA3, 0xAC, 0x2B, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x34, 0x23, 0x29, 0x62, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x3E, 0x3E, 0x63, 0x40, 0x97, 0x28, 0xDA,
+  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
+  0xA1, 0xB2, 0xB2, 0xA1, 0x21, 0xAC, 0x85, 0x2C,
+  0xDA, 0x36, 0x77, 0x72, 0x62, 0x8B, 0x62, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
+  0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0xEC, 0x2F, 0x51,
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+  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
+  0xA1, 0xD6, 0xD6, 0xB2, 0xD6, 0xAC, 0x85, 0x85,
+  0x4D, 0xBE, 0x39, 0x4C, 0x57, 0x2E, 0x2E, 0x2E,
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+  0x54, 0x6B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x6B, 0x7B, 0xC3, 0xE7, 0x39, 0x72, 0x62, 0x62,
+  0x62, 0x62, 0x62, 0x2E, 0x29, 0x77, 0xA7, 0x36,
+  0xB8, 0x85, 0x85, 0x8D, 0x8D, 0x85, 0xB2, 0x2D,
+  0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
+  0x2A, 0x85, 0xAC, 0x95, 0x95, 0xAF, 0x85, 0x85,
+  0xAF, 0x8C, 0xDF, 0xC6, 0xB1, 0xD1, 0xE5, 0xE7,
+  0x83, 0x23, 0x5D, 0x60, 0x39, 0x77, 0xEC, 0x2E,
+  0x2E, 0x32, 0x32, 0x2E, 0x7C, 0x5D, 0x35, 0xA2,
+  0x54, 0x6B, 0x6B, 0x20, 0x6B, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x6B, 0x88, 0xC1, 0x35, 0xE1, 0x77, 0x57, 0x2E,
+  0x2E, 0x72, 0x29, 0x77, 0x60, 0xB5, 0x44, 0xE2,
+  0x2C, 0x2C, 0xDA, 0x8A, 0xDA, 0xAF, 0xA1, 0x2D,
+  0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85,
+  0xEE, 0xAF, 0xD9, 0x7D, 0xD9, 0x2C, 0xDA, 0x85,
+  0xAC, 0xAF, 0x85, 0xDA, 0x8A, 0x2A, 0xE2, 0x50,
+  0x86, 0xD7, 0x75, 0x35, 0xA8, 0xE7, 0xE1, 0x5D,
+  0x68, 0x7C, 0xF1, 0x68, 0xE1, 0xBF, 0xA2, 0xC1,
+  0x52, 0x2B, 0x7D, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x95,
+  0xE9, 0x74, 0xCE, 0xE0, 0xE7, 0x60, 0x77, 0x77,
+  0x7C, 0xEF, 0x5D, 0x23, 0x3F, 0xB6, 0x8A, 0x2C,
+  0xAC, 0xAF, 0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48,
+  0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85,
+  0xD3, 0xB2, 0x21, 0x7D, 0xAC, 0x2C, 0xDA, 0x85,
+  0xAC, 0xAC, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0x2C,
+  0xDA, 0x8C, 0x79, 0xC7, 0xB0, 0x51, 0xB3, 0x35,
+  0xBF, 0xE5, 0xE7, 0xA8, 0xE0, 0xA2, 0xC1, 0x34,
+  0x7D, 0x85, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC, 0xAC,
+  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0x85,
+  0xC8, 0xCD, 0x6A, 0x26, 0x35, 0x3F, 0x83, 0x23,
+  0x23, 0xE7, 0xBF, 0x96, 0xEB, 0xDA, 0xDA, 0x2C,
+  0x2C, 0x2C, 0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48,
+  0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF,
+  0xAF, 0x2D, 0xE9, 0x7D, 0xAC, 0x2C, 0x85, 0x2C,
+  0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0x2C,
+  0x2C, 0x85, 0xD9, 0x21, 0xAC, 0x2C, 0xBD, 0xA5,
+  0xC3, 0xA2, 0xA2, 0xA2, 0x26, 0xC1, 0xCE, 0x2A,
+  0xAF, 0x95, 0xD9, 0x2C, 0x2C, 0x85, 0x2C, 0xAF,
+  0xAC, 0x2C, 0x85, 0x2C, 0xAF, 0x2C, 0x85, 0xDA,
+  0x8D, 0x2A, 0x85, 0x34, 0xC1, 0xB3, 0x76, 0x35,
+  0xE0, 0x30, 0xA5, 0xB6, 0x2C, 0x85, 0x85, 0x85,
+  0xAF, 0x2C, 0x85, 0x85, 0xD9, 0xD6, 0xA1, 0xA1,
+  0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9,
+  0xB2, 0x2D, 0x48, 0xD9, 0xAF, 0x2C, 0x2C, 0x85,
+  0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x85, 0xAF, 0xAC,
+  0xAC, 0x2C, 0xD9, 0xD6, 0xD6, 0x21, 0xB2, 0x2C,
+  0xC8, 0x3B, 0x65, 0xC5, 0xCE, 0x8E, 0xC8, 0x2C,
+  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC,
+  0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x2C, 0x2C, 0x85,
+  0xDA, 0x2C, 0xD6, 0xAF, 0x59, 0x65, 0xDE, 0xF3,
+  0xF3, 0x59, 0xBC, 0xAC, 0xAF, 0x85, 0x85, 0x85,
+  0xAF, 0xD9, 0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6,
+  0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9,
+  0xB2, 0xA1, 0xD6, 0xAC, 0x2C, 0x2C, 0x2C, 0x85,
+  0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9,
+  0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC,
+  0x85, 0x2A, 0x4D, 0xBC, 0x85, 0xAC, 0xAF, 0xAF,
+  0xAC, 0xD9, 0xAF, 0x2C, 0xAF, 0xD9, 0xD9, 0xAC,
+  0xAC, 0xAF, 0x85, 0x2C, 0x85, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xD9, 0xB2, 0xD4, 0xD6, 0x2C, 0x8A, 0xDA,
+  0xC8, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85,
+  0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
+  0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95,
+  0x95, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
+  0x2C, 0xAF, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0xAC,
+  0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
+  0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0x95, 0xAC, 0xAC,
+  0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
+  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C,
+  0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85,
+  0xAF, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9,
+  0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x85, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0xAC,
+  0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0xDA, 0xDA,
+  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0xD9, 0xAC, 0xD9,
+  0xD6, 0xD6, 0x7D, 0x95, 0x7D, 0xD9, 0xAF, 0xAF,
+  0xAF, 0x2C, 0x85, 0x85, 0xDA, 0x85, 0x2C, 0x85,
+  0x85, 0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
+  0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85,
+  0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9
+};
+
+#define INCLUDE_LINUX_LOGOBW
+#define INCLUDE_LINUX_LOGO16
+#include <linux/linux_logo.h>
+
+#else
+
+/* prototypes only */
+extern unsigned char linux_logo_red[];
+extern unsigned char linux_logo_green[];
+extern unsigned char linux_logo_blue[];
+extern unsigned char linux_logo[];
+extern unsigned char linux_logo_bw[];
+extern unsigned char linux_logo16_red[];
+extern unsigned char linux_logo16_green[];
+extern unsigned char linux_logo16_blue[];
+extern unsigned char linux_logo16[];
+
+#endif
diff --git a/include/asm-mips64/mc146818rtc.h b/include/asm-mips64/mc146818rtc.h
new file mode 100644
index 000000000..f9e51fa61
--- /dev/null
+++ b/include/asm-mips64/mc146818rtc.h
@@ -0,0 +1,46 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ *
+ * Copyright (C) 1996, 1997, 1998 Ralf Baechle
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x)	(0x70 + (x))
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+rtc_ops->rtc_read_data(addr); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+rtc_ops->rtc_write_data(val, addr); \
+})
+#define RTC_ALWAYS_BCD \
+rtc_ops->rtc_bcd_mode()
+
+/*
+ * This structure defines how to access various features of
+ * different machine types and how to access them.
+ */
+struct rtc_ops {
+	/* How to access the RTC register in a DS1287.  */
+	unsigned char (*rtc_read_data)(unsigned long addr);
+	void (*rtc_write_data)(unsigned char data, unsigned long addr);
+	int (*rtc_bcd_mode)(void);
+};
+
+extern struct rtc_ops *rtc_ops;
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-mips64/mman.h b/include/asm-mips64/mman.h
new file mode 100644
index 000000000..4cbaec4d0
--- /dev/null
+++ b/include/asm-mips64/mman.h
@@ -0,0 +1,62 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_MMAN_H
+#define _ASM_MMAN_H
+
+/*
+ * Protections are chosen from these bits, OR'd together.  The
+ * implementation does not necessarily support PROT_EXEC or PROT_WRITE
+ * without PROT_READ.  The only guarantees are that no writing will be
+ * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
+ */
+#define PROT_NONE	0x0		/* page can not be accessed */
+#define PROT_READ	0x1		/* page can be read */
+#define PROT_WRITE	0x2		/* page can be written */
+#define PROT_EXEC	0x4		/* page can be executed */
+
+/*
+ * Flags for mmap
+ */
+#define MAP_SHARED	0x001		/* Share changes */
+#define MAP_PRIVATE	0x002		/* Changes are private */
+#define MAP_TYPE	0x00f		/* Mask for type of mapping */
+#define MAP_FIXED	0x010		/* Interpret addr exactly */
+
+/* not used by linux, but here to make sure we don't clash with ABI defines */
+#define MAP_RENAME	0x020		/* Assign page to file */
+#define MAP_AUTOGROW	0x040		/* File may grow by writing */
+#define MAP_LOCAL	0x080		/* Copy on fork/sproc */
+#define MAP_AUTORSRV	0x100		/* Logical swap reserved on demand */
+
+/* These are linux-specific */
+#define MAP_NORESERVE	0x0400		/* don't check for reservations */
+#define MAP_ANONYMOUS	0x0800		/* don't use a file */
+#define MAP_GROWSDOWN	0x1000		/* stack-like segment */
+#define MAP_DENYWRITE	0x2000		/* ETXTBSY */
+#define MAP_EXECUTABLE	0x4000		/* mark it as an executable */
+#define MAP_LOCKED	0x8000		/* pages are locked */
+
+/*
+ * Flags for msync
+ */
+#define MS_SYNC		0		/* synchronous memory sync */
+#define MS_ASYNC	1		/* sync memory asynchronously */
+#define MS_INVALIDATE	2		/* invalidate mappings & caches */
+
+/*
+ * Flags for mlockall
+ */
+#define MCL_CURRENT	1		/* lock all current mappings */
+#define MCL_FUTURE	2		/* lock all future mappings */
+
+/* compatibility flags */
+#define MAP_ANON       MAP_ANONYMOUS
+#define MAP_FILE       0
+
+#endif /* _ASM_MMAN_H */
diff --git a/include/asm-mips64/mmu_context.h b/include/asm-mips64/mmu_context.h
new file mode 100644
index 000000000..70f3bab5d
--- /dev/null
+++ b/include/asm-mips64/mmu_context.h
@@ -0,0 +1,64 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996 - 1999 by Ralf Baechle
+ */
+#ifndef _ASM_MMU_CONTEXT_H
+#define _ASM_MMU_CONTEXT_H
+
+#define MAX_ASID 255
+
+extern unsigned long asid_cache;
+
+#define ASID_VERSION_SHIFT 16
+#define ASID_VERSION_MASK  ((~0UL) << ASID_VERSION_SHIFT)
+#define ASID_FIRST_VERSION (1UL << ASID_VERSION_SHIFT)
+
+extern inline void get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
+{
+	/* check if it's legal.. */
+	if ((asid & ~ASID_VERSION_MASK) > MAX_ASID) {
+		/* start a new version, invalidate all old asid's */
+		flush_tlb_all();
+		asid = (asid & ASID_VERSION_MASK) + ASID_FIRST_VERSION;
+		if (!asid)
+			asid = ASID_FIRST_VERSION;
+	}
+	asid_cache = asid + 1;
+	mm->context = asid;			 /* full version + asid */
+}
+
+extern inline void get_mmu_context(struct task_struct *p)
+{
+	struct mm_struct *mm = p->mm;
+
+	if (mm) {
+		unsigned long asid = asid_cache;
+		/* Check if our ASID is of an older version and thus invalid */
+		if ((mm->context ^ asid) & ASID_VERSION_MASK)
+			get_new_mmu_context(mm, asid);
+	}
+}
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+extern inline void init_new_context(struct mm_struct *mm)
+{
+	mm->context = 0;
+}
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+extern inline void destroy_context(struct mm_struct *mm)
+{
+	mm->context = 0;
+}
+
+#endif /* _ASM_MMU_CONTEXT_H */
diff --git a/include/asm-mips64/ng1.h b/include/asm-mips64/ng1.h
new file mode 100644
index 000000000..7c7104415
--- /dev/null
+++ b/include/asm-mips64/ng1.h
@@ -0,0 +1,56 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI/Newport video card ioctl definitions
+ */
+#ifndef _ASM_NG1_H
+#define _ASM_NG1_H
+
+typedef struct {
+        int flags;
+        __u16 w, h;
+        __u16 fields_sec;
+} ng1_vof_info_t;
+
+struct ng1_info {
+	struct gfx_info gfx_info;
+	__u8 boardrev;
+        __u8 rex3rev;
+        __u8 vc2rev;
+        __u8 monitortype;
+        __u8 videoinstalled;
+        __u8 mcrev;
+        __u8 bitplanes;
+        __u8 xmap9rev;
+        __u8 cmaprev;
+        ng1_vof_info_t ng1_vof_info;
+        __u8 bt445rev;
+        __u8 paneltype;
+};
+
+#define GFX_NAME_NEWPORT "NG1"
+
+/* ioctls */
+#define NG1_SET_CURSOR_HOTSPOT 21001
+struct ng1_set_cursor_hotspot {
+	unsigned short xhot;
+        unsigned short yhot;
+};
+
+#define NG1_SETDISPLAYMODE     21006
+struct ng1_setdisplaymode_args {
+        int wid;
+        unsigned int mode;
+};
+
+#define NG1_SETGAMMARAMP0      21007
+struct ng1_setgammaramp_args {
+        unsigned char red   [256];
+        unsigned char green [256];
+        unsigned char blue  [256];
+};
+
+#endif /* _ASM_NG1_H */
diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h
new file mode 100644
index 000000000..492ecc1f1
--- /dev/null
+++ b/include/asm-mips64/pgtable.h
@@ -0,0 +1,859 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999 by Ralf Baechle at alii
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_H
+#define _ASM_PGTABLE_H
+
+#include <asm/addrspace.h>
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+#include <linux/linkage.h>
+#include <asm/cachectl.h>
+
+/* Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_page(mm, vmaddr) flushes a single page
+ *  - flush_cache_range(mm, start, end) flushes a range of pages
+ *  - flush_page_to_ram(page) write back kernel page to ram
+ */
+extern void (*flush_cache_all)(void);
+extern void (*flush_cache_mm)(struct mm_struct *mm);
+extern void (*flush_cache_range)(struct mm_struct *mm, unsigned long start,
+				 unsigned long end);
+extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+extern void (*flush_cache_sigtramp)(unsigned long addr);
+extern void (*flush_page_to_ram)(unsigned long page);
+#define flush_icache_range(start, end) flush_cache_all()
+
+/* TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLB entries
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
+ *  - flush_tlb_page(mm, vmaddr) flushes a single page
+ *  - flush_tlb_range(mm, start, end) flushes a range of pages
+ */
+extern void (*flush_tlb_all)(void);
+extern void (*flush_tlb_mm)(struct mm_struct *mm);
+extern void (*flush_tlb_range)(struct mm_struct *mm, unsigned long start,
+			       unsigned long end);
+extern void (*flush_tlb_page)(struct vm_area_struct *vma, unsigned long page);
+
+
+/* Basically we have the same two-level (which is the logical three level
+ * Linux page table layout folded) page tables as the i386.  Some day
+ * when we have proper page coloring support we can have a 1% quicker
+ * tlb refill handling mechanism, but for now it is a bit slower but
+ * works even with the cache aliasing problem the R4k and above have.
+ */
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define PMD_SHIFT	22
+#define PMD_SIZE	(1UL << PMD_SHIFT)
+#define PMD_MASK	(~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT	22
+#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
+#define PGDIR_MASK	(~(PGDIR_SIZE-1))
+
+/* Entries per page directory level: we use two-level, so
+ * we don't really have any PMD directory physically.
+ */
+#define PTRS_PER_PTE	1024
+#define PTRS_PER_PMD	1
+#define PTRS_PER_PGD	1024
+#define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
+
+#define VMALLOC_START     KSEG2
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       KSEG3
+
+/* Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software.  We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page.  On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things.  The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
+#define _PAGE_READ                  (1<<1)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
+#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<6)
+#define _PAGE_VALID                 (1<<7)
+#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<8)
+#define _CACHE_CACHABLE_NO_WA       (0<<9)  /* R4600 only              */
+#define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
+#define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
+#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00 only           */
+#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00 only           */
+#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00 only           */
+#define _CACHE_CACHABLE_ACCELERATED (7<<9)  /* R10000 only             */
+#define _CACHE_MASK                 (7<<9)
+
+#define __READABLE	(_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
+
+#define PAGE_NONE	__pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+			_CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+			_CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+			_CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
+			_CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+			_CACHE_UNCACHED)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
+			_CACHE_UNCACHED)
+
+/*
+ * MIPS can't do page protection for execute, and considers that the same like
+ * read. Also, write permissions imply read permissions. This is the closest
+ * we can get by reasonable means..
+ */
+#define __P000	PAGE_NONE
+#define __P001	PAGE_READONLY
+#define __P010	PAGE_COPY
+#define __P011	PAGE_COPY
+#define __P100	PAGE_READONLY
+#define __P101	PAGE_READONLY
+#define __P110	PAGE_COPY
+#define __P111	PAGE_COPY
+
+#define __S000	PAGE_NONE
+#define __S001	PAGE_READONLY
+#define __S010	PAGE_SHARED
+#define __S011	PAGE_SHARED
+#define __S100	PAGE_READONLY
+#define __S101	PAGE_READONLY
+#define __S110	PAGE_SHARED
+#define __S111	PAGE_SHARED
+
+#if !defined (_LANGUAGE_ASSEMBLY)
+
+/*
+ * BAD_PAGETABLE is used when we need a bogus page-table, while
+ * BAD_PAGE is used for a bogus page.
+ *
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern pte_t __bad_page(void);
+extern pte_t *__bad_pagetable(void);
+
+extern unsigned long empty_zero_page;
+extern unsigned long zero_page_mask;
+
+#define BAD_PAGETABLE __bad_pagetable()
+#define BAD_PAGE __bad_page()
+#define ZERO_PAGE(__vaddr) \
+	(empty_zero_page + (((unsigned long)(__vaddr)) & zero_page_mask))
+
+/* number of bits that fit into a memory pointer */
+#define BITS_PER_PTR			(8*sizeof(unsigned long))
+
+/* to align the pointer to a pointer address */
+#define PTR_MASK			(~(sizeof(void*)-1))
+
+/*
+ * sizeof(void*) == (1 << SIZEOF_PTR_LOG2)
+ */
+#define SIZEOF_PTR_LOG2			2
+
+/* to find an entry in a page-table */
+#define PAGE_PTR(address) \
+((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
+
+extern void (*load_pgd)(unsigned long pg_dir);
+
+/* to set the page-dir */
+#define SET_PAGE_DIR(tsk,pgdir) (tsk)->tss.pg_dir = ((unsigned long) (pgdir))
+
+extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)];
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+extern inline unsigned long pte_page(pte_t pte)
+{
+	return PAGE_OFFSET + (pte_val(pte) & PAGE_MASK);
+}
+
+extern inline unsigned long pmd_page(pmd_t pmd)
+{
+	return pmd_val(pmd);
+}
+
+extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
+{
+	pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
+}
+
+extern inline int pte_none(pte_t pte)    { return !pte_val(pte); }
+extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
+
+/* Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+extern inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+	*ptep = pteval;
+}
+
+extern inline void pte_clear(pte_t *ptep)
+{
+	set_pte(ptep, __pte(0));
+}
+
+/*
+ * Empty pgd/pmd entries point to the invalid_pte_table.
+ */
+extern inline int pmd_none(pmd_t pmd)
+{
+	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+extern inline int pmd_bad(pmd_t pmd)
+{
+	return ((pmd_page(pmd) > (unsigned long) high_memory) ||
+	        (pmd_page(pmd) < PAGE_OFFSET));
+}
+
+extern inline int pmd_present(pmd_t pmd)
+{
+	return pmd_val(pmd);
+}
+
+extern inline void pmd_clear(pmd_t *pmdp)
+{
+	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+extern inline int pgd_none(pgd_t pgd)		{ return 0; }
+extern inline int pgd_bad(pgd_t pgd)		{ return 0; }
+extern inline int pgd_present(pgd_t pgd)	{ return 1; }
+extern inline void pgd_clear(pgd_t *pgdp)	{ }
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+extern inline int pte_read(pte_t pte)	{ return pte_val(pte) & _PAGE_READ; }
+extern inline int pte_write(pte_t pte)	{ return pte_val(pte) & _PAGE_WRITE; }
+extern inline int pte_dirty(pte_t pte)	{ return pte_val(pte) & _PAGE_MODIFIED; }
+extern inline int pte_young(pte_t pte)	{ return pte_val(pte) & _PAGE_ACCESSED; }
+
+extern inline pte_t pte_wrprotect(pte_t pte)
+{
+	pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+	return pte;
+}
+
+extern inline pte_t pte_rdprotect(pte_t pte)
+{
+	pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
+	return pte;
+}
+
+extern inline pte_t pte_mkclean(pte_t pte)
+{
+	pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
+	return pte;
+}
+
+extern inline pte_t pte_mkold(pte_t pte)
+{
+	pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+	return pte;
+}
+
+extern inline pte_t pte_mkwrite(pte_t pte)
+{
+	pte_val(pte) |= _PAGE_WRITE;
+	if (pte_val(pte) & _PAGE_MODIFIED)
+		pte_val(pte) |= _PAGE_SILENT_WRITE;
+	return pte;
+}
+
+extern inline pte_t pte_mkread(pte_t pte)
+{
+	pte_val(pte) |= _PAGE_READ;
+	if (pte_val(pte) & _PAGE_ACCESSED)
+		pte_val(pte) |= _PAGE_SILENT_READ;
+	return pte;
+}
+
+extern inline pte_t pte_mkdirty(pte_t pte)
+{
+	pte_val(pte) |= _PAGE_MODIFIED;
+	if (pte_val(pte) & _PAGE_WRITE)
+		pte_val(pte) |= _PAGE_SILENT_WRITE;
+	return pte;
+}
+
+extern inline pte_t pte_mkyoung(pte_t pte)
+{
+	pte_val(pte) |= _PAGE_ACCESSED;
+	if (pte_val(pte) & _PAGE_READ)
+		pte_val(pte) |= _PAGE_SILENT_READ;
+	return pte;
+}
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+extern inline pte_t mk_pte(unsigned long page, pgprot_t pgprot)
+{
+	return __pte(((page & PAGE_MASK) - PAGE_OFFSET) | pgprot_val(pgprot));
+}
+
+extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
+{
+	return __pte(physpage | pgprot_val(pgprot));
+}
+
+extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+}
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* to find an entry in a page-table-directory */
+extern inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
+{
+	return mm->pgd + (address >> PGDIR_SHIFT);
+}
+
+/* Find an entry in the second-level page table.. */
+extern inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
+{
+	return (pmd_t *) dir;
+}
+
+/* Find an entry in the third-level page table.. */ 
+extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
+{
+	return (pte_t *) (pmd_page(*dir)) +
+	       ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
+}
+
+/*
+ * Initialize new page directory with pointers to invalid ptes
+ */
+extern void (*pgd_init)(unsigned long page);
+
+/*
+ * Allocate and free page tables. The xxx_kernel() versions are
+ * used to allocate a kernel page table - this turns on ASN bits
+ * if any.
+ */
+
+#define pgd_quicklist (current_cpu_data.pgd_quick)
+#define pmd_quicklist ((unsigned long *)0)
+#define pte_quicklist (current_cpu_data.pte_quick)
+#define pgtable_cache_size (current_cpu_data.pgtable_cache_sz)
+
+extern __inline__ pgd_t *get_pgd_slow(void)
+{
+	pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL), *init;
+
+	if (ret) {
+		init = pgd_offset(&init_mm, 0);
+		pgd_init((unsigned long)ret);
+		memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+	}
+	return ret;
+}
+
+extern __inline__ pgd_t *get_pgd_fast(void)
+{
+	unsigned long *ret;
+
+	if((ret = pgd_quicklist) != NULL) {
+		pgd_quicklist = (unsigned long *)(*ret);
+		ret[0] = ret[1];
+		pgtable_cache_size--;
+	} else
+		ret = (unsigned long *)get_pgd_slow();
+	return (pgd_t *)ret;
+}
+
+extern __inline__ void free_pgd_fast(pgd_t *pgd)
+{
+	*(unsigned long *)pgd = (unsigned long) pgd_quicklist;
+	pgd_quicklist = (unsigned long *) pgd;
+	pgtable_cache_size++;
+}
+
+extern __inline__ void free_pgd_slow(pgd_t *pgd)
+{
+	free_page((unsigned long)pgd);
+}
+
+extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
+extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long address_preadjusted);
+
+extern __inline__ pte_t *get_pte_fast(void)
+{
+	unsigned long *ret;
+
+	if((ret = (unsigned long *)pte_quicklist) != NULL) {
+		pte_quicklist = (unsigned long *)(*ret);
+		ret[0] = ret[1];
+		pgtable_cache_size--;
+	}
+	return (pte_t *)ret;
+}
+
+extern __inline__ void free_pte_fast(pte_t *pte)
+{
+	*(unsigned long *)pte = (unsigned long) pte_quicklist;
+	pte_quicklist = (unsigned long *) pte;
+	pgtable_cache_size++;
+}
+
+extern __inline__ void free_pte_slow(pte_t *pte)
+{
+	free_page((unsigned long)pte);
+}
+
+/* We don't use pmd cache, so these are dummy routines */
+extern __inline__ pmd_t *get_pmd_fast(void)
+{
+	return (pmd_t *)0;
+}
+
+extern __inline__ void free_pmd_fast(pmd_t *pmd)
+{
+}
+
+extern __inline__ void free_pmd_slow(pmd_t *pmd)
+{
+}
+
+extern void __bad_pte(pmd_t *pmd);
+extern void __bad_pte_kernel(pmd_t *pmd);
+
+#define pte_free_kernel(pte)    free_pte_fast(pte)
+#define pte_free(pte)           free_pte_fast(pte)
+#define pgd_free(pgd)           free_pgd_fast(pgd)
+#define pgd_alloc()             get_pgd_fast()
+
+extern inline pte_t * pte_alloc_kernel(pmd_t * pmd, unsigned long address)
+{
+	address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+
+	if (pmd_none(*pmd)) {
+		pte_t *page = get_pte_fast();
+		if (page) {
+			pmd_val(*pmd) = (unsigned long)page;
+			return page + address;
+		}
+		return get_pte_kernel_slow(pmd, address);
+	}
+	if (pmd_bad(*pmd)) {
+		__bad_pte_kernel(pmd);
+		return NULL;
+	}
+	return (pte_t *) pmd_page(*pmd) + address;
+}
+
+extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
+{
+	address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+
+	if (pmd_none(*pmd)) {
+		pte_t *page = get_pte_fast();
+		if (page) {
+			pmd_val(*pmd) = (unsigned long)page;
+			return page + address;
+		}
+		return get_pte_slow(pmd, address);
+	}
+	if (pmd_bad(*pmd)) {
+		__bad_pte(pmd);
+		return NULL;
+	}
+	return (pte_t *) pmd_page(*pmd) + address;
+}
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+extern inline void pmd_free(pmd_t * pmd)
+{
+}
+
+extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
+{
+	return (pmd_t *) pgd;
+}
+
+#define pmd_free_kernel		pmd_free
+#define pmd_alloc_kernel	pmd_alloc
+
+extern int do_check_pgt_cache(int, int);
+
+extern inline void set_pgdir(unsigned long address, pgd_t entry)
+{
+	struct task_struct * p;
+	pgd_t *pgd;
+#ifdef __SMP__
+	int i;
+#endif	
+        
+	read_lock(&tasklist_lock);
+	for_each_task(p) {
+		if (!p->mm)
+			continue;
+		*pgd_offset(p->mm,address) = entry;
+	}
+	read_unlock(&tasklist_lock);
+#ifndef __SMP__
+	for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+		pgd[address >> PGDIR_SHIFT] = entry;
+#else
+	/* To pgd_alloc/pgd_free, one holds master kernel lock and so does our
+	   callee, so we can modify pgd caches of other CPUs as well. -jj */
+	for (i = 0; i < NR_CPUS; i++)
+		for (pgd = (pgd_t *)cpu_data[i].pgd_quick; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+			pgd[address >> PGDIR_SHIFT] = entry;
+#endif
+}
+
+extern pgd_t swapper_pg_dir[1024];
+
+extern void (*update_mmu_cache)(struct vm_area_struct *vma,
+				unsigned long address, pte_t pte);
+
+/*
+ * Kernel with 32 bit address space
+ */
+#define SWP_TYPE(entry) (((entry) >> 1) & 0x3f)
+#define SWP_OFFSET(entry) ((entry) >> 8)
+#define SWP_ENTRY(type,offset) (((type) << 1) | ((offset) << 8))
+
+#define module_map      vmalloc
+#define module_unmap    vfree
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define PageSkip(page)		(0)
+#define kern_addr_valid(addr)	(1)
+
+/* TLB operations. */
+extern inline void tlb_probe(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbp\n\t"
+		".set reorder");
+}
+
+extern inline void tlb_read(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbr\n\t"
+		".set reorder");
+}
+
+extern inline void tlb_write_indexed(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwi\n\t"
+		".set reorder");
+}
+
+extern inline void tlb_write_random(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwr\n\t"
+		".set reorder");
+}
+
+/* Dealing with various CP0 mmu/cache related registers. */
+
+/* CP0_PAGEMASK register */
+extern inline unsigned long get_pagemask(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $5\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+	return val;
+}
+
+extern inline void set_pagemask(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $5\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
+extern inline unsigned long get_entrylo0(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(	
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $2\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+	return val;
+}
+
+extern inline void set_entrylo0(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $2\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+extern inline unsigned long get_entrylo1(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $3\n\t"
+		".set mips0\n\t"
+		".set reorder" : "=r" (val));
+
+	return val;
+}
+
+extern inline void set_entrylo1(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $3\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+/* CP0_ENTRYHI register */
+extern inline unsigned long get_entryhi(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $10\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+
+	return val;
+}
+
+extern inline void set_entryhi(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $10\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+/* CP0_INDEX register */
+extern inline unsigned long get_index(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $0\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+	return val;
+}
+
+extern inline void set_index(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $0\n\t"
+		".set mips0\n\t"
+		".set reorder\n\t"
+		: : "r" (val));
+}
+
+/* CP0_WIRED register */
+extern inline unsigned long get_wired(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $6\n\t"
+		".set mips0\n\t"
+		".set reorder\n\t"
+		: "=r" (val));
+	return val;
+}
+
+extern inline void set_wired(unsigned long val)
+{
+	__asm__ __volatile__(
+		"\n\t.set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $6\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+/* CP0_TAGLO and CP0_TAGHI registers */
+extern inline unsigned long get_taglo(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $28\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+	return val;
+}
+
+extern inline void set_taglo(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $28\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+extern inline unsigned long get_taghi(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $29\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+	return val;
+}
+
+extern inline void set_taghi(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $29\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+/* CP0_CONTEXT register */
+extern inline unsigned long get_context(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mfc0 %0, $4\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: "=r" (val));
+
+	return val;
+}
+
+extern inline void set_context(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"mtc0 %0, $4\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		: : "r" (val));
+}
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#endif /* _ASM_PGTABLE_H */
diff --git a/include/asm-mips64/poll.h b/include/asm-mips64/poll.h
new file mode 100644
index 000000000..7d14790b9
--- /dev/null
+++ b/include/asm-mips64/poll.h
@@ -0,0 +1,34 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_POLL_H
+#define _ASM_POLL_H
+
+#define POLLIN		0x0001
+#define POLLPRI		0x0002
+#define POLLOUT		0x0004
+
+#define POLLERR		0x0008
+#define POLLHUP		0x0010
+#define POLLNVAL	0x0020
+
+#define POLLRDNORM	0x0040
+#define POLLRDBAND	0x0080
+#define POLLWRNORM	POLLOUT
+#define POLLWRBAND	0x0100
+
+/* XXX This one seems to be more-or-less nonstandard.  */
+#define POLLMSG		0x0400
+
+struct pollfd {
+	int fd;
+	short events;
+	short revents;
+};
+
+#endif /* _ASM_POLL_H */
diff --git a/include/asm-mips64/semaphore-helper.h b/include/asm-mips64/semaphore-helper.h
new file mode 100644
index 000000000..d685b89e6
--- /dev/null
+++ b/include/asm-mips64/semaphore-helper.h
@@ -0,0 +1,125 @@
+/* $Id$
+ *
+ * SMP- and interrupt-safe semaphores helper functions.
+ *
+ * (C) Copyright 1996 Linus Torvalds
+ * (C) Copyright 1999 Andrea Arcangeli
+ * (C) Copyright 1999 Ralf Baechle
+ */
+#ifndef _ASM_SEMAPHORE_HELPER_H
+#define _ASM_SEMAPHORE_HELPER_H
+
+/*
+ * These two _must_ execute atomically wrt each other.
+ */
+static inline void wake_one_more(struct semaphore * sem)
+{
+	atomic_inc(&sem->waking);
+}
+
+static inline int
+waking_non_zero(struct semaphore *sem)
+{
+	int ret, tmp;
+
+	__asm__ __volatile__(
+	"1:\tll\t%1,%2\n\t"
+	"blez\t%1,2f\n\t"
+	"subu\t%0,%1,1\n\t"
+	"sc\t%0,%2\n\t"
+	"beqz\t%0,1b\n\t"
+	"2:"
+	".text"
+	: "=r"(ret), "=r"(tmp), "=m"(__atomic_fool_gcc(&sem->waking))
+	: "0"(0));
+
+	return ret;
+}
+
+/*
+ * waking_non_zero_interruptible:
+ *	1	got the lock
+ *	0	go to sleep
+ *	-EINTR	interrupted
+ *
+ * We must undo the sem->count down_interruptible decrement
+ * simultaneously and atomicly with the sem->waking adjustment,
+ * otherwise we can race with wake_one_more.
+ *
+ * This is accomplished by doing a 64-bit ll/sc on the 2 32-bit words.
+ *
+ * This is crazy.  Normally it stricly forbidden to use 64-bit operation
+ * in the 32-bit MIPS kernel.  In this case it's however ok because if an
+ * interrupt has destroyed the upper half of registers sc will fail.
+ */
+static inline int
+waking_non_zero_interruptible(struct semaphore *sem, struct task_struct *tsk)
+{
+	long ret, tmp;
+
+#ifdef __MIPSEB__
+        __asm__ __volatile__("
+	.set	mips3
+	.set	push
+	.set	noat
+0:	lld	%1,%2
+	li	%0,0
+
+	bltz	%1, 1f
+	dli	$1, 0xffffffff00000000
+	daddu	%1, $1
+	li	%0, 1
+	b	2f
+1:
+
+	beqz	%3, 1f
+	addiu	$1, %1, 1
+	dsll32	$1, $1, 0
+	dsrl32	$1, $1, 0
+	dsrl32	%1, %1, 0
+	dsll32	%1, %1, 0
+	or	%1, $1
+	li	%0, %4
+	b	2f
+1:
+	scd	%1, %2
+2:
+	beqz	%1,0b
+	.set	pop
+	.set	mips0"
+	: "=&r"(ret), "=&r"(tmp), "=m"(*sem)
+	: "r"(signal_pending(tsk)), "i"(-EINTR));
+#endif
+
+#ifdef __MIPSEL__
+#error "FIXME: waking_non_zero_interruptible doesn't support little endian machines yet."
+#endif
+
+	return ret;
+}
+
+/*
+ * waking_non_zero_trylock:
+ *	1	failed to lock
+ *	0	got the lock
+ *
+ * XXX SMP ALERT
+ */
+#ifdef __SMP__
+#error FIXME, waking_non_zero_trylock is broken for SMP.
+#endif
+static inline int waking_non_zero_trylock(struct semaphore *sem)
+{
+        int ret = 1;
+
+	if (atomic_read(&sem->waking) <= 0)
+		atomic_inc(&sem->count);
+	else {
+		atomic_dec(&sem->waking);
+		ret = 0;
+	}
+
+	return ret;
+}
+
+#endif /* _ASM_SEMAPHORE_HELPER_H */
diff --git a/include/asm-mips64/shmiq.h b/include/asm-mips64/shmiq.h
new file mode 100644
index 000000000..cbce27212
--- /dev/null
+++ b/include/asm-mips64/shmiq.h
@@ -0,0 +1,234 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Please note that the comments on this file may be out of date
+ * and that they represent what I have figured about the shmiq device
+ * so far in IRIX.
+ *
+ * This also contains some streams and idev bits.
+ *
+ * They may contain errors, please, refer to the source code of the Linux  
+ * kernel for a definitive answer on what we have implemented
+ *
+ * Miguel.
+ */
+#ifndef _ASM_SHMIQ_H
+#define _ASM_SHMIQ_H
+
+/* STREAMs ioctls */
+#define STRIOC    ('S' << 8)
+#define I_STR     (STRIOC | 010)
+#define I_PUSH    (STRIOC | 02)
+#define I_LINK    (STRIOC | 014)
+#define I_UNLINK  (STRIOC | 015)
+
+/* Data structure passed on I_STR ioctls */
+struct strioctl {
+        int     ic_cmd;                 /* streams ioctl command */
+        int     ic_timout;              /* timeout */
+        int     ic_len;                 /* lenght of data */
+        void    *ic_dp;                 /* data */
+};
+
+/*
+ * For mapping the shared memory input queue, you have to:
+ *
+ * 1. Map /dev/zero for the number of bytes you want to use
+ *    for your shared memory input queue plus the size of the
+ *    sharedMemoryInputQueue structure + 4 (I still have not figured
+ *    what this one is for
+ *
+ * 2. Open /dev/shmiq
+ *
+ * 3. Open /dev/qcntlN N is [0..Nshmiqs]
+ *
+ * 4. Fill a shmiqreq structure.  user_vaddr should point to the return
+ *    address from the /dev/zero mmap.  Arg is the number of shmqevents
+ *    that fit into the /dev/zero region (remember that at the beginning there
+ *    is a sharedMemoryInputQueue header).
+ *
+ * 5. Issue the ioctl (qcntlfd, QIOCATTACH, &your_shmiqreq);
+ */
+
+struct shmiqreq {
+	char *user_vaddr;
+	int  arg;
+};
+
+/* map the shmiq into the process address space */
+#define QIOCATTACH       _IOW('Q',1,struct shmiqreq)
+
+/* remove mappings */
+#define QIOCDETACH       _IO('Q',2)
+
+/*
+ * A shared memory input queue event.
+ */
+struct shmqdata {
+	unsigned char device;          /* device major */
+        unsigned char which;           /* device minor */
+        unsigned char type;            /* event type */
+        unsigned char flags;           /* little event data */
+        union {
+            int pos;                   /* big event data */
+            short ptraxis [2];         /* event data for PTR events */
+        } un;
+};
+
+/* indetifies the shmiq and the device */
+struct shmiqlinkid {
+        short int devminor;
+        short int index;
+};
+
+struct shmqevent {
+	union {
+                int time;
+                struct shmiqlinkid id;
+        } un ;
+        struct shmqdata data ;
+};
+
+/*
+ * sharedMemoryInputQueue: this describes the shared memory input queue.
+ *
+ * head   is the user index into the events, user can modify this one.
+ * tail   is managed by the kernel.
+ * flags  is one of SHMIQ_OVERFLOW or SHMIQ_CORRUPTED
+ *        if OVERFLOW is set it seems ioctl QUIOCSERVICED should be called 
+ *        to notify the kernel.
+ * events where the kernel sticks the events.
+ */
+struct sharedMemoryInputQueue {
+	volatile int head;	     /* user's index into events */
+        volatile int tail;	     /* kernel's index into events */
+        volatile unsigned int flags; /* place for out-of-band data */
+#define SHMIQ_OVERFLOW  1
+#define SHMIQ_CORRUPTED 2
+        struct shmqevent events[1];  /* input event buffer */
+};
+
+/* have to figure this one out */
+#define QIOCGETINDX      _IOWR('Q', 8, int)
+
+
+/* acknowledge shmiq overflow */
+#define QIOCSERVICED     _IO('Q', 3)
+
+/* Double indirect I_STR ioctl, yeah, fun fun fun */
+
+struct muxioctl {
+        int index;		/* lower stream index */
+        int realcmd;		/* the actual command for the subdevice */
+};
+/* Double indirect ioctl */
+#define QIOCIISTR        _IOW('Q', 7, struct muxioctl)
+
+/* Cursor ioclts: */
+
+/* set cursor tracking mode */
+#define QIOCURSTRK      _IOW('Q', 4, int)
+
+/* set cursor filter box */
+#define QIOCURSIGN      _IOW('Q', 5, int [4])
+
+/* set cursor axes */
+struct shmiqsetcurs {
+        short index;
+        short axes;
+};
+
+#define QIOCSETCURS     _IOWR('Q',  9, struct shmiqsetcurs)
+
+/* set cursor position */
+struct shmiqsetcpos {
+        short   x;
+        short   y;
+};
+#define QIOCSETCPOS     _IOWR('Q', 10, struct shmiqsetcpos)
+
+/* get time since last event */
+#define QIOCGETITIME    _IOR('Q', 11, time_t)
+
+/* set curent screen */
+#define QIOCSETSCRN     _IOW('Q',6,int)
+
+
+/* -------------------- iDev stuff -------------------- */
+
+#define IDEV_MAX_NAME_LEN 15
+#define IDEV_MAX_TYPE_LEN 15
+
+typedef struct {
+        char            devName[IDEV_MAX_NAME_LEN+1];
+        char            devType[IDEV_MAX_TYPE_LEN+1];
+        unsigned short  nButtons;
+        unsigned short  nValuators;
+        unsigned short  nLEDs;
+        unsigned short  nStrDpys;
+        unsigned short  nIntDpys;
+        unsigned char   nBells;
+        unsigned char   flags;
+#define IDEV_HAS_KEYMAP		0x01
+#define IDEV_HAS_PROXIMITY 	0x02
+#define IDEV_HAS_PCKBD 		0x04
+} idevDesc;
+
+typedef struct {
+	char *nothing_for_now;
+} idevInfo;
+
+#define IDEV_KEYMAP_NAME_LEN 15
+
+typedef struct {
+        char name[IDEV_KEYMAP_NAME_LEN+1];
+} idevKeymapDesc;
+
+/* The valuator definition */
+typedef struct {
+        unsigned        hwMinRes;
+        unsigned        hwMaxRes;
+        int             hwMinVal;
+        int             hwMaxVal;
+	
+        unsigned char   possibleModes;
+#define IDEV_ABSOLUTE           0x0
+#define IDEV_RELATIVE           0x1
+#define IDEV_EITHER             0x2
+	
+        unsigned char   mode;	/* One of: IDEV_ABSOLUTE, IDEV_RELATIVE */
+	
+        unsigned short  resolution;
+        int             minVal;
+        int             maxVal;
+} idevValuatorDesc;
+
+/* This is used to query a specific valuator with the IDEVGETVALUATORDESC ioctl */
+typedef struct {
+        short                   valNum;
+        unsigned short          flags;
+        idevValuatorDesc        desc;
+} idevGetSetValDesc;
+
+#define IDEVGETDEVICEDESC	_IOWR('i', 0,  idevDesc)
+#define IDEVGETVALUATORDESC     _IOWR('i', 1,  idevGetSetValDesc)
+#define IDEVGETKEYMAPDESC	_IOWR('i', 2,  idevKeymapDesc)
+#define IDEVINITDEVICE		_IOW ('i', 51, unsigned int)
+
+
+#ifdef __KERNEL__
+
+/* These are only interpreted by SHMIQ-attacheable devices and are internal
+ * to the kernel
+ */
+#define SHMIQ_OFF        _IO('Q',1)
+#define SHMIQ_ON         _IO('Q',2)
+
+void shmiq_push_event (struct shmqevent *e);
+int get_sioc (struct strioctl *sioc, unsigned long arg);
+#endif
+
+#endif /* _ASM_SHMIQ_H */
diff --git a/include/asm-mips64/shmparam.h b/include/asm-mips64/shmparam.h
new file mode 100644
index 000000000..f20fd19a6
--- /dev/null
+++ b/include/asm-mips64/shmparam.h
@@ -0,0 +1,58 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * XXX These are obviously wrong for an 64-bit OS, let's see how we divide
+ * the address space later ...
+ */
+#ifndef _ASM_SHMPARAM_H
+#define _ASM_SHMPARAM_H
+
+/* address range for shared memory attaches if no address passed to shmat() */
+#define SHM_RANGE_START	0x50000000
+#define SHM_RANGE_END	0x60000000
+
+/*
+ * Format of a swap-entry for shared memory pages currently out in
+ * swap space (see also mm/swap.c).
+ *
+ * SWP_TYPE = SHM_SWP_TYPE
+ * SWP_OFFSET is used as follows:
+ *
+ *  bits 0..6 : id of shared memory segment page belongs to (SHM_ID)
+ *  bits 7..21: index of page within shared memory segment (SHM_IDX)
+ *		(actually fewer bits get used since SHMMAX is so low)
+ */
+
+/*
+ * Keep _SHM_ID_BITS as low as possible since SHMMNI depends on it and
+ * there is a static array of size SHMMNI.
+ */
+#define _SHM_ID_BITS	7
+#define SHM_ID_MASK	((1<<_SHM_ID_BITS)-1)
+
+#define SHM_IDX_SHIFT	(_SHM_ID_BITS)
+#define _SHM_IDX_BITS	15
+#define SHM_IDX_MASK	((1<<_SHM_IDX_BITS)-1)
+
+/*
+ * _SHM_ID_BITS + _SHM_IDX_BITS must be <= 24 on the i386 and
+ * SHMMAX <= (PAGE_SIZE << _SHM_IDX_BITS).
+ */
+
+#define SHMMAX 0x2000000		/* max shared seg size (bytes) */
+/* Try not to change the default shipped SHMMAX - people rely on it */
+
+#define SHMMIN 1 /* really PAGE_SIZE */	/* min shared seg size (bytes) */
+#define SHMMNI (1<<_SHM_ID_BITS)	/* max num of segs system wide */
+#define SHMALL				/* max shm system wide (pages) */ \
+	(1<<(_SHM_IDX_BITS+_SHM_ID_BITS))
+/*
+ * This constant is very large but the ABI in it's wisdom says ...
+ */
+#define	SHMLBA 0x40000			/* attach addr a multiple of this */
+#define SHMSEG SHMMNI			/* max shared segs per process */
+
+#endif /* _ASM_SHMPARAM_H */
diff --git a/include/asm-mips64/softirq.h b/include/asm-mips64/softirq.h
new file mode 100644
index 000000000..0c234fa50
--- /dev/null
+++ b/include/asm-mips64/softirq.h
@@ -0,0 +1,98 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1998, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SOFTIRQ_H
+#define _ASM_SOFTIRQ_H
+
+/* The locking mechanism for base handlers, to prevent re-entrancy,
+ * is entirely private to an implementation, it should not be
+ * referenced at all outside of this file.
+ */
+extern atomic_t __mips_bh_counter;
+
+extern unsigned int local_bh_count[NR_CPUS];
+
+#define cpu_bh_disable(cpu)    do { local_bh_count[(cpu)]++; barrier(); } while (0)
+#define cpu_bh_enable(cpu)     do { barrier(); local_bh_count[(cpu)]--; } while (0)
+
+#define cpu_bh_trylock(cpu)    (local_bh_count[(cpu)] ? 0 : (local_bh_count[(cpu)] = 1))
+#define cpu_bh_endlock(cpu)    (local_bh_count[(cpu)] = 0)
+
+#define local_bh_disable()     cpu_bh_disable(smp_processor_id())
+#define local_bh_enable()      cpu_bh_enable(smp_processor_id())
+
+#define get_active_bhs()	(bh_mask & bh_active)
+
+static inline void clear_active_bhs(unsigned long x)
+{
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0,%1\n\t"
+		"and\t%0,%2\n\t"
+		"sc\t%0,%1\n\t"
+		"beqz\t%0,1b"
+		:"=&r" (temp),
+		 "=m" (bh_active)
+		:"Ir" (~x),
+		 "m" (bh_active));
+}
+
+extern inline void init_bh(int nr, void (*routine)(void))
+{
+	bh_base[nr] = routine;
+	atomic_set(&bh_mask_count[nr], 0);
+	bh_mask |= 1 << nr;
+}
+
+extern inline void remove_bh(int nr)
+{
+	bh_mask &= ~(1 << nr);
+	mb();
+	bh_base[nr] = NULL;
+}
+
+extern inline void mark_bh(int nr)
+{
+	set_bit(nr, &bh_active);
+}
+
+/*
+ * These use a mask count to correctly handle
+ * nested disable/enable calls
+ */
+extern inline void disable_bh(int nr)
+{
+	bh_mask &= ~(1 << nr);
+	atomic_inc(&bh_mask_count[nr]);
+}
+
+extern inline void enable_bh(int nr)
+{
+	if (atomic_dec_and_test(&bh_mask_count[nr]))
+		bh_mask |= 1 << nr;
+}
+
+extern inline void start_bh_atomic(void)
+{
+	local_bh_disable();
+	barrier();
+}
+
+extern inline void end_bh_atomic(void)
+{
+	barrier();
+	local_bh_enable();
+}
+
+/* These are for the irq's testing the lock */
+#define softirq_trylock(cpu)   (cpu_bh_trylock(cpu))
+#define softirq_endlock(cpu)   (cpu_bh_endlock(cpu))
+#define synchronize_bh()	barrier()
+
+#endif /* _ASM_SOFTIRQ_H */
diff --git a/include/asm-mips64/uaccess.h b/include/asm-mips64/uaccess.h
index 0eb889679..1522748ff 100644
--- a/include/asm-mips64/uaccess.h
+++ b/include/asm-mips64/uaccess.h
@@ -1,10 +1,11 @@
-/* $Id$
+/* $Id: uaccess.h,v 1.1 1999/08/18 23:37:53 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
  */
 #ifndef _ASM_UACCESS_H
 #define _ASM_UACCESS_H
@@ -128,7 +129,7 @@ switch (size) { \
 case 1: __get_user_asm("lb"); break; \
 case 2: __get_user_asm("lh"); break; \
 case 4: __get_user_asm("lw"); break; \
-case 8: __get_user_asm("dw"); break; \
+case 8: __get_user_asm("ld"); break; \
 default: __get_user_unknown(); break; \
 } } x = (__typeof__(*(ptr))) __gu_val; __gu_err; })
 
diff --git a/include/asm-mips64/unaligned.h b/include/asm-mips64/unaligned.h
new file mode 100644
index 000000000..fecbd76be
--- /dev/null
+++ b/include/asm-mips64/unaligned.h
@@ -0,0 +1,146 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_UNALIGNED_H
+#define _ASM_UNALIGNED_H
+
+extern void __get_unaligned_bad_length(void);
+extern void __put_unaligned_bad_length(void);
+
+/*
+ * Load quad unaligned.
+ */
+extern __inline__ unsigned long ldq_u(const unsigned long long * __addr)
+{
+	unsigned long long __res;
+
+	__asm__("uld\t%0,(%1)"
+		:"=&r" (__res)
+		:"r" (__addr));
+
+	return __res;
+}
+
+/*
+ * Load long unaligned.
+ */
+extern __inline__ unsigned long ldl_u(const unsigned int * __addr)
+{
+	unsigned long __res;
+
+	__asm__("ulw\t%0,(%1)"
+		:"=&r" (__res)
+		:"r" (__addr));
+
+	return __res;
+}
+
+/*
+ * Load word unaligned.
+ */
+extern __inline__ unsigned long ldw_u(const unsigned short * __addr)
+{
+	unsigned long __res;
+
+	__asm__("ulh\t%0,(%1)"
+		:"=&r" (__res)
+		:"r" (__addr));
+
+	return __res;
+}
+
+/*
+ * Store quad ununaligned.
+ */
+extern __inline__ void stq_u(unsigned long __val, unsigned long long * __addr)
+{
+	__asm__ __volatile__(
+		"usd\t%0,(%1)"
+		: /* No results */
+		:"r" (__val),
+		 "r" (__addr));
+}
+
+/*
+ * Store long ununaligned.
+ */
+extern __inline__ void stl_u(unsigned long __val, unsigned int * __addr)
+{
+	__asm__ __volatile__(
+		"usw\t%0,(%1)"
+		: /* No results */
+		:"r" (__val),
+		 "r" (__addr));
+}
+
+/*
+ * Store word ununaligned.
+ */
+extern __inline__ void stw_u(unsigned long __val, unsigned short * __addr)
+{
+	__asm__ __volatile__(
+		"ush\t%0,(%1)"
+		: /* No results */
+		:"r" (__val),
+		 "r" (__addr));
+}
+
+extern inline unsigned long __get_unaligned(const void *ptr, size_t size)
+{
+	unsigned long val;
+	switch (size) {
+	case 1:
+		val = *(const unsigned char *)ptr;
+		break;
+	case 2:
+		val = ldw_u((const unsigned short *)ptr);
+		break;
+	case 4:
+		val = ldl_u((const unsigned int *)ptr);
+		break;
+	case 8:
+		val = ldq_u((const unsigned long long *)ptr);
+		break;
+	default:
+		__get_unaligned_bad_length();
+		break;
+	}
+	return val;
+}
+
+extern inline void __put_unaligned(unsigned long val, void *ptr, size_t size)
+{
+	switch (size) {
+	case 1:
+		*(unsigned char *)ptr = (val);
+		break;
+	case 2:
+		stw_u(val, (unsigned short *)ptr);
+		break;
+	case 4:
+		stl_u(val, (unsigned int *)ptr);
+		break;
+	case 8:
+		stq_u(val, (unsigned long long *)ptr);
+		break;
+	default:
+		__put_unaligned_bad_length();
+		break;
+	}
+}
+
+/* 
+ * The main single-value unaligned transfer routines.
+ */
+#define get_unaligned(ptr) \
+	((__typeof__(*(ptr)))__get_unaligned((ptr), sizeof(*(ptr))))
+#define put_unaligned(x,ptr) \
+	__put_unaligned((unsigned long)(x), (ptr), sizeof(*(ptr)))
+
+#endif /* _ASM_UNALIGNED_H */
diff --git a/include/asm-mips64/usioctl.h b/include/asm-mips64/usioctl.h
new file mode 100644
index 000000000..1f2d81cc1
--- /dev/null
+++ b/include/asm-mips64/usioctl.h
@@ -0,0 +1,33 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * usema/usemaclone-related stuff.
+ *
+ * `Inspired' by IRIX's sys/usioctl.h
+ *
+ * Mike.
+ */
+#ifndef _ASM_USIOCTL_H
+#define _ASM_USIOCTL_H
+
+/* ioctls */
+#define UIOC	('u' << 16 | 's' << 8)
+
+#define UIOCATTACHSEMA	(UIOC|2)	/* attach to sema */
+#define UIOCBLOCK	(UIOC|3)	/* block sync "intr"? */
+#define UIOCABLOCK	(UIOC|4)	/* block async */
+#define UIOCNOIBLOCK	(UIOC|5)	/* IRIX: block sync intr
+					   Linux: block sync nointr */
+#define UIOCUNBLOCK	(UIOC|6)	/* unblock sync */
+#define UIOCAUNBLOCK	(UIOC|7)	/* unblock async */
+#define UIOCINIT	(UIOC|8)	/* init sema (async) */
+
+typedef struct usattach_s {
+  dev_t	us_dev;		/* attach dev */
+  void	*us_handle;	/* userland semaphore handle */
+} usattach_t;
+
+#endif /* _ASM_USIOCTL_H */
diff --git a/include/asm-mips/newport.h b/include/video/newport.h
index de25d10a9..2f094e321 100644
--- a/include/asm-mips/newport.h
+++ b/include/video/newport.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $
  *
  * newport.h: Defines and register layout for NEWPORT graphics
  *            hardware.