diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-09-01 20:44:34 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-09-01 20:44:34 +0000 |
| commit | e0fc8c9572d7a4ddceb464dc8919591f6009da10 (patch) | |
| tree | 4a59c71f94ddbafd8a877163be5ebc777250911b /include | |
| parent | 49a3eb2420bbb4815461352ad25d810952f95ccf (diff) | |
Hopefully squash the R5k bug ...
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/bcache.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h index cd2a267cf..e7c8071b0 100644 --- a/include/asm-mips/bcache.h +++ b/include/asm-mips/bcache.h @@ -11,8 +11,6 @@ #include <linux/config.h> -#ifdef CONFIG_BOARD_SCACHE - /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, chipset implemented caches. On machines with other CPUs the CPU does the cache thing itself. */ @@ -26,7 +24,7 @@ struct bcache_ops { extern void indy_sc_init(void); extern void sni_pcimt_sc_init(void); -#define DECLARE_BCOPS struct bcache_ops *bcops +#ifdef CONFIG_BOARD_SCACHE extern struct bcache_ops *bcops; @@ -54,8 +52,6 @@ extern inline void bc_inv(unsigned long page, unsigned long size) /* Not R4000 / R4400 / R4600 / R5000. */ -#define DECLARE_BCOPS - #define bc_enable() do { } while (0) #define bc_disable() do { } while (0) #define bc_wback_inv(page, size) do { } while (0) |