Merge with Linux 2.4.0.

171 files changed, 37923 insertions, 1140 deletions

diff --git a/include/asm-alpha/delay.h b/include/asm-alpha/delay.h
index 74cb75ec2..5d3329f4d 100644
--- a/include/asm-alpha/delay.h
+++ b/include/asm-alpha/delay.h
@@ -2,12 +2,13 @@
 #define __ALPHA_DELAY_H
 
 #include <linux/config.h>
+#include <asm/param.h>
 #include <asm/smp.h>
 
 /*
  * Copyright (C) 1993, 2000 Linus Torvalds
  *
- * Delay routines, using a pre-computed "loops_per_second" value.
+ * Delay routines, using a pre-computed "loops_per_jiffy" value.
  */
 
 /*
@@ -32,16 +33,16 @@ __delay(int loops)
 }
 
 extern __inline__ void
-__udelay(unsigned long usecs, unsigned long lps)
+__udelay(unsigned long usecs, unsigned long lpj)
 {
-	usecs *= ((1UL << 32) / 1000000) * lps;
+	usecs *= (((unsigned long)HZ << 32) / 1000000) * lpj;
 	__delay((long)usecs >> 32);
 }
 
 #ifdef CONFIG_SMP
-#define udelay(u)  __udelay((u), cpu_data[smp_processor_id()].loops_per_sec)
+#define udelay(u)  __udelay((u), cpu_data[smp_processor_id()].loops_per_jiffy)
 #else
-#define udelay(u)  __udelay((u), loops_per_sec)
+#define udelay(u)  __udelay((u), loops_per_jiffy)
 #endif
 
 #endif /* defined(__ALPHA_DELAY_H) */
diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h
index 6331af6f2..f11e254f6 100644
--- a/include/asm-alpha/smp.h
+++ b/include/asm-alpha/smp.h
@@ -24,7 +24,7 @@ __hard_smp_processor_id(void)
 #include <asm/irq.h>
 
 struct cpuinfo_alpha {
-	unsigned long loops_per_sec;
+	unsigned long loops_per_jiffy;
 	unsigned long last_asn;
 	int need_new_asn;
 	int asn_lock;
diff --git a/include/asm-i386/floppy.h b/include/asm-i386/floppy.h
index 641fa495a..8e61b2f87 100644
--- a/include/asm-i386/floppy.h
+++ b/include/asm-i386/floppy.h
@@ -285,8 +285,28 @@ struct fd_routine_l {
 static int FDC1 = 0x3f0;
 static int FDC2 = -1;
 
-#define FLOPPY0_TYPE	((CMOS_READ(0x10) >> 4) & 15)
-#define FLOPPY1_TYPE	(CMOS_READ(0x10) & 15)
+/*
+ * Floppy types are stored in the rtc's CMOS RAM and so rtc_lock
+ * is needed to prevent corrupted CMOS RAM in case "insmod floppy"
+ * coincides with another rtc CMOS user.		Paul G.
+ */
+#define FLOPPY0_TYPE	({				\
+	unsigned long flags;				\
+	unsigned char val;				\
+	spin_lock_irqsave(&rtc_lock, flags);		\
+	val = (CMOS_READ(0x10) >> 4) & 15;		\
+	spin_unlock_irqrestore(&rtc_lock, flags);	\
+	val;						\
+})
+
+#define FLOPPY1_TYPE	({				\
+	unsigned long flags;				\
+	unsigned char val;				\
+	spin_lock_irqsave(&rtc_lock, flags);		\
+	val = CMOS_READ(0x10) & 15;			\
+	spin_unlock_irqrestore(&rtc_lock, flags);	\
+	val;						\
+})
 
 #define N_FDC 2
 #define N_DRIVE 8
diff --git a/include/asm-i386/semaphore.h b/include/asm-i386/semaphore.h
index ecceb0c7b..04d46c8d6 100644
--- a/include/asm-i386/semaphore.h
+++ b/include/asm-i386/semaphore.h
@@ -23,6 +23,12 @@
  *                     Optimized "0(ecx)" -> "(ecx)" (the assembler does not
  *                     do this). Changed calling sequences from push/jmp to
  *                     traditional call/ret.
+ * Modified 2001-01-01 Andreas Franck <afranck@gmx.de>
+ *		       Some hacks to ensure compatibility with recent
+ *		       GCC snapshots, to avoid stack corruption when compiling
+ *		       with -fomit-frame-pointer. It's not sure if this will
+ *		       be fixed in GCC, as our previous implementation was a
+ *		       bit dubious.
  *
  * If you would like to see an analysis of this implementation, please
  * ftp to gcom.com and download the file
@@ -113,14 +119,14 @@ static inline void down(struct semaphore * sem)
 
 	__asm__ __volatile__(
 		"# atomic down operation\n\t"
-		LOCK "decl (%0)\n\t"     /* --sem->count */
+		LOCK "decl %0\n\t"     /* --sem->count */
 		"js 2f\n"
 		"1:\n"
 		".section .text.lock,\"ax\"\n"
 		"2:\tcall __down_failed\n\t"
 		"jmp 1b\n"
 		".previous"
-		:/* no outputs */
+		:"=m" (sem->count)
 		:"c" (sem)
 		:"memory");
 }
@@ -135,7 +141,7 @@ static inline int down_interruptible(struct semaphore * sem)
 
 	__asm__ __volatile__(
 		"# atomic interruptible down operation\n\t"
-		LOCK "decl (%1)\n\t"     /* --sem->count */
+		LOCK "decl %1\n\t"     /* --sem->count */
 		"js 2f\n\t"
 		"xorl %0,%0\n"
 		"1:\n"
@@ -143,7 +149,7 @@ static inline int down_interruptible(struct semaphore * sem)
 		"2:\tcall __down_failed_interruptible\n\t"
 		"jmp 1b\n"
 		".previous"
-		:"=a" (result)
+		:"=a" (result), "=m" (sem->count)
 		:"c" (sem)
 		:"memory");
 	return result;
@@ -159,7 +165,7 @@ static inline int down_trylock(struct semaphore * sem)
 
 	__asm__ __volatile__(
 		"# atomic interruptible down operation\n\t"
-		LOCK "decl (%1)\n\t"     /* --sem->count */
+		LOCK "decl %1\n\t"     /* --sem->count */
 		"js 2f\n\t"
 		"xorl %0,%0\n"
 		"1:\n"
@@ -167,7 +173,7 @@ static inline int down_trylock(struct semaphore * sem)
 		"2:\tcall __down_failed_trylock\n\t"
 		"jmp 1b\n"
 		".previous"
-		:"=a" (result)
+		:"=a" (result), "=m" (sem->count)
 		:"c" (sem)
 		:"memory");
 	return result;
@@ -186,14 +192,14 @@ static inline void up(struct semaphore * sem)
 #endif
 	__asm__ __volatile__(
 		"# atomic up operation\n\t"
-		LOCK "incl (%0)\n\t"     /* ++sem->count */
+		LOCK "incl %0\n\t"     /* ++sem->count */
 		"jle 2f\n"
 		"1:\n"
 		".section .text.lock,\"ax\"\n"
 		"2:\tcall __up_wakeup\n\t"
 		"jmp 1b\n"
 		".previous"
-		:/* no outputs */
+		:"=m" (sem->count)
 		:"c" (sem)
 		:"memory");
 }
@@ -315,14 +321,15 @@ static inline void __up_read(struct rw_semaphore *sem)
 {
 	__asm__ __volatile__(
 		"# up_read\n\t"
-		LOCK "incl (%%eax)\n\t"
+		LOCK "incl %0\n\t"
 		"jz 2f\n"			/* only do the wake if result == 0 (ie, a writer) */
 		"1:\n\t"
 		".section .text.lock,\"ax\"\n"
 		"2:\tcall __rwsem_wake\n\t"
 		"jmp 1b\n"
 		".previous"
-		::"a" (sem)
+		:"=m" (sem->count)
+		:"a" (sem)
 		:"memory"
 		);
 }
@@ -334,14 +341,15 @@ static inline void __up_write(struct rw_semaphore *sem)
 {
 	__asm__ __volatile__(
 		"# up_write\n\t"
-		LOCK "addl $" RW_LOCK_BIAS_STR ",(%%eax)\n"
+		LOCK "addl $" RW_LOCK_BIAS_STR ",%0\n"
 		"jc 2f\n"			/* only do the wake if the result was -'ve to 0/+'ve */
 		"1:\n\t"
 		".section .text.lock,\"ax\"\n"
 		"2:\tcall __rwsem_wake\n\t"
 		"jmp 1b\n"
 		".previous"
-		::"a" (sem)
+		:"=m" (sem->count)
+		:"a" (sem)
 		:"memory"
 		);
 }
diff --git a/include/asm-ia64/a.out.h b/include/asm-ia64/a.out.h
index 2de8a2d0d..7cbd1f1b9 100644
--- a/include/asm-ia64/a.out.h
+++ b/include/asm-ia64/a.out.h
@@ -7,14 +7,13 @@
  * probably would be better to clean up binfmt_elf.c so it does not
  * necessarily depend on there being a.out support.
  *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/types.h>
 
-struct exec
-{
+struct exec {
 	unsigned long a_info;
 	unsigned long a_text;
 	unsigned long a_data;
@@ -31,7 +30,7 @@ struct exec
 #define N_TXTOFF(x)	0
 
 #ifdef __KERNEL__
-# define STACK_TOP	0xa000000000000000UL
+# define STACK_TOP	(0x8000000000000000UL + (1UL << (4*PAGE_SHIFT - 12)))
 # define IA64_RBS_BOT	(STACK_TOP - 0x80000000L)	/* bottom of register backing store */
 #endif
 
diff --git a/include/asm-ia64/acpi-ext.h b/include/asm-ia64/acpi-ext.h
index e5acd26a5..775934cbd 100644
--- a/include/asm-ia64/acpi-ext.h
+++ b/include/asm-ia64/acpi-ext.h
@@ -8,19 +8,27 @@
  * 
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ * Copyright (C) 2000 Intel Corp.
+ * Copyright (C) 2000 J.I. Lee <jung-ik.lee@intel.com>
+ *	ACPI 2.0 specification 
  */
 
 #include <linux/types.h>
 
+#pragma	pack(1)
 #define ACPI_RSDP_SIG "RSD PTR " /* Trailing space required */
 #define ACPI_RSDP_SIG_LEN 8
 typedef struct {
 	char signature[8];
 	u8 checksum;
 	char oem_id[6];
-	char reserved;		/* Must be 0 */
-	struct acpi_rsdt *rsdt;
-} acpi_rsdp_t;
+	u8 revision;
+	u32 rsdt;
+	u32 lenth;
+	struct acpi_xsdt *xsdt;
+	u8 ext_checksum;
+	u8 reserved[3];
+} acpi20_rsdp_t;
 
 typedef struct {
 	char signature[4];
@@ -32,13 +40,65 @@ typedef struct {
 	u32 oem_revision;
 	u32 creator_id;
 	u32 creator_revision;
-	char reserved[4];
 } acpi_desc_table_hdr_t;
 
 #define ACPI_RSDT_SIG "RSDT"
 #define ACPI_RSDT_SIG_LEN 4
-typedef struct acpi_rsdt {
+typedef struct {
+	acpi_desc_table_hdr_t header;
+	u8 reserved[4];
+	u32 entry_ptrs[1];	/* Not really . . . */
+} acpi20_rsdt_t;
+
+#define ACPI_XSDT_SIG "XSDT"
+#define ACPI_XSDT_SIG_LEN 4
+typedef struct acpi_xsdt {
+	acpi_desc_table_hdr_t header;
+	unsigned long entry_ptrs[1];	/* Not really . . . */
+} acpi_xsdt_t;
+
+/* Common structures for ACPI 2.0 and 0.71 */
+
+typedef struct acpi_entry_iosapic {
+	u8 type;
+	u8 length;
+	u8 id;
+	u8 reserved;
+	u32 irq_base;	/* start of IRQ's this IOSAPIC is responsible for. */
+	unsigned long address;	/* Address of this IOSAPIC */
+} acpi_entry_iosapic_t;
+
+/* Local SAPIC flags */
+#define LSAPIC_ENABLED                (1<<0)
+#define LSAPIC_PERFORMANCE_RESTRICTED (1<<1)
+#define LSAPIC_PRESENT                (1<<2)
+
+/* Defines legacy IRQ->pin mapping */
+typedef struct {
+	u8 type;
+	u8 length;
+	u8 bus;		/* Constant 0 == ISA */
+	u8 isa_irq;	/* ISA IRQ # */
+	u32 pin;		/* called vector in spec; really IOSAPIC pin number */
+	u16 flags;	/* Edge/Level trigger & High/Low active */
+} acpi_entry_int_override_t;
+
+#define INT_OVERRIDE_ACTIVE_LOW    0x03
+#define INT_OVERRIDE_LEVEL_TRIGGER 0x0d
+
+/* IA64 ext 0.71 */
+
+typedef struct {
+	char signature[8];
+	u8 checksum;
+	char oem_id[6];
+	char reserved;		/* Must be 0 */
+	struct acpi_rsdt *rsdt;
+} acpi_rsdp_t;
+
+typedef struct {
 	acpi_desc_table_hdr_t header;
+	u8 reserved[4];
 	unsigned long entry_ptrs[1];	/* Not really . . . */
 } acpi_rsdt_t;
 
@@ -46,6 +106,7 @@ typedef struct acpi_rsdt {
 #define ACPI_SAPIC_SIG_LEN 4
 typedef struct {
 	acpi_desc_table_hdr_t header;
+	u8 reserved[4];
 	unsigned long interrupt_block;
 } acpi_sapic_t;
 
@@ -55,11 +116,6 @@ typedef struct {
 #define ACPI_ENTRY_INT_SRC_OVERRIDE    2
 #define ACPI_ENTRY_PLATFORM_INT_SOURCE 3	/* Unimplemented */
 
-/* Local SAPIC flags */
-#define LSAPIC_ENABLED                (1<<0)
-#define LSAPIC_PERFORMANCE_RESTRICTED (1<<1)
-#define LSAPIC_PRESENT                (1<<2)
-
 typedef struct acpi_entry_lsapic {
 	u8 type;
 	u8 length;
@@ -69,42 +125,71 @@ typedef struct acpi_entry_lsapic {
 	u8 eid;
 } acpi_entry_lsapic_t;
 
-typedef struct acpi_entry_iosapic {
+typedef struct {
 	u8 type;
 	u8 length;
-	u16 reserved;
-	u32 irq_base;	/* start of IRQ's this IOSAPIC is responsible for. */
-	unsigned long address;	/* Address of this IOSAPIC */
-} acpi_entry_iosapic_t;
+	u16 flags;
+	u8 int_type;
+	u8 id;
+	u8 eid;
+	u8 iosapic_vector;
+	u8 reserved[4];
+	u32 global_vector;
+} acpi_entry_platform_src_t;
 
-/* Defines legacy IRQ->pin mapping */
+/* ACPI 2.0 with 1.3 errata specific structures */
+
+#define ACPI_MADT_SIG "APIC"
+#define ACPI_MADT_SIG_LEN 4
 typedef struct {
+	acpi_desc_table_hdr_t header;
+	u32 lapic_address;
+	u32 flags;
+} acpi_madt_t;
+
+/* acpi 2.0 MADT structure types */
+#define ACPI20_ENTRY_LOCAL_APIC                 0
+#define ACPI20_ENTRY_IO_APIC                    1
+#define ACPI20_ENTRY_INT_SRC_OVERRIDE           2
+#define ACPI20_ENTRY_NMI_SOURCE                 3
+#define ACPI20_ENTRY_LOCAL_APIC_NMI             4
+#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE   5
+#define ACPI20_ENTRY_IO_SAPIC                   6
+#define ACPI20_ENTRY_LOCAL_SAPIC                7
+#define ACPI20_ENTRY_PLATFORM_INT_SOURCE        8
+
+typedef struct acpi20_entry_lsapic {
 	u8 type;
 	u8 length;
-	u8 bus;	/* Constant 0 == ISA */
-	u8 isa_irq;	/* ISA IRQ # */
-	u8 pin;	/* called vector in spec; really IOSAPIC pin number */
-	u32 flags;	/* Edge/Level trigger & High/Low active */
-	u8 reserved[6];
-} acpi_entry_int_override_t;
-#define INT_OVERRIDE_ACTIVE_LOW    0x03
-#define INT_OVERRIDE_LEVEL_TRIGGER 0x0d
+	u8 acpi_processor_id;
+	u8 id;
+	u8 eid;
+	u8 reserved[3];
+	u32 flags;
+} acpi20_entry_lsapic_t;
+
+typedef struct acpi20_entry_lapic_addr_override {
+	u8 type;
+	u8 length;
+	u8 reserved[2];
+	unsigned long lapic_address;
+} acpi20_entry_lapic_addr_override_t;
 
 typedef struct {
 	u8 type;
 	u8 length;
-	u32 flags;
+	u16 flags;
 	u8 int_type;
 	u8 id;
 	u8 eid;
 	u8 iosapic_vector;
-	unsigned long reserved;
-	unsigned long global_vector;
-} acpi_entry_platform_src_t;
+	u32 global_vector;
+} acpi20_entry_platform_src_t;
 
+extern int acpi20_parse(acpi20_rsdp_t *);
 extern int acpi_parse(acpi_rsdp_t *);
 extern const char *acpi_get_sysname (void);
 
 extern void (*acpi_idle) (void);	/* power-management idle function, if any */
-
+#pragma	pack()
 #endif /* _ASM_IA64_ACPI_EXT_H */
diff --git a/include/asm-ia64/acpikcfg.h b/include/asm-ia64/acpikcfg.h
index 1bf49cf01..8020595cf 100644
--- a/include/asm-ia64/acpikcfg.h
+++ b/include/asm-ia64/acpikcfg.h
@@ -1,3 +1,5 @@
+#include <linux/config.h>
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG
 /*
  *  acpikcfg.h - ACPI based Kernel Configuration Manager External Interfaces
  *
@@ -5,9 +7,6 @@
  *  Copyright (C) 2000 J.I. Lee  <jung-ik.lee@intel.com>
  */
 
-#include <linux/config.h>
-
-#ifdef	CONFIG_ACPI_KERNEL_CONFIG
 
 u32	__init acpi_cf_init (void * rsdp);
 u32	__init acpi_cf_terminate (void );
diff --git a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
index 15035374f..9baef0ed2 100644
--- a/include/asm-ia64/cache.h
+++ b/include/asm-ia64/cache.h
@@ -9,11 +9,11 @@
  */
 
 /* Bytes per L1 (data) cache line.  */
-#define LOG_L1_CACHE_BYTES	6
-#define L1_CACHE_BYTES		(1 << LOG_L1_CACHE_BYTES)
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
 
 #ifdef CONFIG_SMP
-# define SMP_LOG_CACHE_BYTES	LOG_L1_CACHE_BYTES
+# define SMP_CACHE_SHIFT	L1_CACHE_SHIFT
 # define SMP_CACHE_BYTES	L1_CACHE_BYTES
 #else
   /*
@@ -21,7 +21,7 @@
    * safe and provides an easy way to avoid wasting space on a
    * uni-processor:
    */
-# define SMP_LOG_CACHE_BYTES	3
+# define SMP_CACHE_SHIFT	3
 # define SMP_CACHE_BYTES	(1 << 3)
 #endif
 
diff --git a/include/asm-ia64/delay.h b/include/asm-ia64/delay.h
index dda714e20..73a74101b 100644
--- a/include/asm-ia64/delay.h
+++ b/include/asm-ia64/delay.h
@@ -55,6 +55,10 @@ ia64_get_itc (void)
 	unsigned long result;
 
 	__asm__ __volatile__("mov %0=ar.itc" : "=r"(result) :: "memory");
+#ifdef CONFIG_ITANIUM
+	while (__builtin_expect ((__s32) result == -1, 0))
+		__asm__ __volatile__("mov %0=ar.itc" : "=r"(result) :: "memory");
+#endif
 	return result;
 }
 
diff --git a/include/asm-ia64/efi.h b/include/asm-ia64/efi.h
index cfdfd4efd..015c0aed4 100644
--- a/include/asm-ia64/efi.h
+++ b/include/asm-ia64/efi.h
@@ -168,6 +168,9 @@ typedef void efi_reset_system_t (int reset_type, efi_status_t status,
 #define ACPI_TABLE_GUID    \
     ((efi_guid_t) { 0xeb9d2d30, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d }})
 
+#define ACPI_20_TABLE_GUID    \
+    ((efi_guid_t) { 0x8868e871, 0xe4f1, 0x11d3, { 0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }})
+
 #define SMBIOS_TABLE_GUID    \
     ((efi_guid_t) { 0xeb9d2d31, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d }})
 	
@@ -204,7 +207,8 @@ typedef struct {
 extern struct efi {
 	efi_system_table_t *systab;	/* EFI system table */
 	void *mps;			/* MPS table */
-	void *acpi;			/* ACPI table */
+	void *acpi;			/* ACPI table  (IA64 ext 0.71) */
+	void *acpi20;			/* ACPI table  (ACPI 2.0) */
 	void *smbios;			/* SM BIOS table */
 	void *sal_systab;		/* SAL system table */
 	void *boot_info;		/* boot info table */
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
index 06528f8d2..b3a42bf5d 100644
--- a/include/asm-ia64/hw_irq.h
+++ b/include/asm-ia64/hw_irq.h
@@ -6,8 +6,10 @@
  * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
+#include <linux/sched.h>
 #include <linux/types.h>
 
+#include <asm/machvec.h>
 #include <asm/ptrace.h>
 #include <asm/smp.h>
 
@@ -29,13 +31,22 @@
 
 #define IA64_SPURIOUS_INT	0x0f
 
-#define IA64_MIN_VECTORED_IRQ	 16
-#define IA64_MAX_VECTORED_IRQ	255
+/*
+ * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
+ */
+#define PCE_IRQ			0x1e	/* platform corrected error interrupt vector */
+#define CMC_IRQ			0x1f	/* correctable machine-check interrupt vector */
+/*
+ * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
+ */
+#define FIRST_DEVICE_IRQ	0x30
+#define LAST_DEVICE_IRQ		0xe7
 
-#define PERFMON_IRQ		0x28	/* performanc monitor interrupt vector */
+#define MCA_RENDEZ_IRQ		0xe8	/* MCA rendez interrupt */
+#define PERFMON_IRQ		0xee	/* performanc monitor interrupt vector */
 #define TIMER_IRQ		0xef	/* use highest-prio group 15 interrupt for timer */
+#define	MCA_WAKEUP_IRQ		0xf0	/* MCA wakeup interrupt (must be higher than MCA_RENDEZ_IRQ) */
 #define IPI_IRQ			0xfe	/* inter-processor interrupt vector */
-#define CMC_IRQ			0xff	/* correctable machine-check interrupt vector */
 
 /* IA64 inter-cpu interrupt related definitions */
 
@@ -60,12 +71,13 @@ extern unsigned long ipi_base_addr;
 
 extern struct hw_interrupt_type irq_type_ia64_sapic;	/* CPU-internal interrupt controller */
 
-extern void ipi_send (int cpu, int vector, int delivery_mode, int redirect);
+extern int ia64_alloc_irq (void);	/* allocate a free irq */
+extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
 
 static inline void
 hw_resend_irq (struct hw_interrupt_type *h, unsigned int vector)
 {
-	ipi_send(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
+	platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
 }
 
 #endif /* _ASM_IA64_HW_IRQ_H */
diff --git a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h
index 48a6d0bd4..394cabb0d 100644
--- a/include/asm-ia64/ia32.h
+++ b/include/asm-ia64/ia32.h
@@ -5,6 +5,8 @@
 
 #ifdef CONFIG_IA32_SUPPORT
 
+#include <linux/param.h>
+
 /*
  * 32 bit structures for IA32 support.
  */
@@ -32,6 +34,8 @@ typedef __kernel_fsid_t	       __kernel_fsid_t32;
 
 #define IA32_PAGE_SHIFT		12	/* 4KB pages */
 #define IA32_PAGE_SIZE		(1ULL << IA32_PAGE_SHIFT)
+#define IA32_CLOCKS_PER_SEC	100	/* Cast in stone for IA32 Linux */
+#define IA32_TICK(tick)		((unsigned long long)(tick) * IA32_CLOCKS_PER_SEC / CLOCKS_PER_SEC)
 
 /* fcntl.h */
 struct flock32 {
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h
index 3dcc496fa..4ab52f448 100644
--- a/include/asm-ia64/io.h
+++ b/include/asm-ia64/io.h
@@ -29,6 +29,7 @@
 
 # ifdef __KERNEL__
 
+#include <asm/machvec.h>
 #include <asm/page.h>
 #include <asm/system.h>
 
@@ -54,8 +55,7 @@ phys_to_virt(unsigned long address)
 #define bus_to_virt	phys_to_virt
 #define virt_to_bus	virt_to_phys
 
-# else /* !KERNEL */
-# endif /* !KERNEL */
+# endif /* KERNEL */
 
 /*
  * Memory fence w/accept.  This should never be used in code that is
@@ -100,7 +100,7 @@ __ia64_mk_io_addr (unsigned long port)
  */
 
 static inline unsigned int
-__inb (unsigned long port)
+__ia64_inb (unsigned long port)
 {
 	volatile unsigned char *addr = __ia64_mk_io_addr(port);
 	unsigned char ret;
@@ -111,7 +111,7 @@ __inb (unsigned long port)
 }
 
 static inline unsigned int
-__inw (unsigned long port)
+__ia64_inw (unsigned long port)
 {
 	volatile unsigned short *addr = __ia64_mk_io_addr(port);
 	unsigned short ret;
@@ -122,7 +122,7 @@ __inw (unsigned long port)
 }
 
 static inline unsigned int
-__inl (unsigned long port)
+__ia64_inl (unsigned long port)
 {
 	volatile unsigned int *addr = __ia64_mk_io_addr(port);
 	unsigned int ret;
@@ -133,113 +133,149 @@ __inl (unsigned long port)
 }
 
 static inline void
-__insb (unsigned long port, void *dst, unsigned long count)
+__ia64_outb (unsigned char val, unsigned long port)
 {
 	volatile unsigned char *addr = __ia64_mk_io_addr(port);
-	unsigned char *dp = dst;
 
+	*addr = val;
 	__ia64_mf_a();
-	while (count--) {
-		*dp++ = *addr;
-	}
-	__ia64_mf_a();
-	return;
 }
 
 static inline void
-__insw (unsigned long port, void *dst, unsigned long count)
+__ia64_outw (unsigned short val, unsigned long port)
 {
 	volatile unsigned short *addr = __ia64_mk_io_addr(port);
-	unsigned short *dp = dst;
 
+	*addr = val;
 	__ia64_mf_a();
-	while (count--) {
-		*dp++ = *addr;
-	}
-	__ia64_mf_a();
-	return;
 }
 
 static inline void
-__insl (unsigned long port, void *dst, unsigned long count)
+__ia64_outl (unsigned int val, unsigned long port)
 {
 	volatile unsigned int *addr = __ia64_mk_io_addr(port);
-	unsigned int *dp = dst;
 
+	*addr = val;
 	__ia64_mf_a();
-	while (count--) {
-		*dp++ = *addr;
-	}
-	__ia64_mf_a();
-	return;
 }
 
 static inline void
-__outb (unsigned char val, unsigned long port)
+__insb (unsigned long port, void *dst, unsigned long count)
 {
-	volatile unsigned char *addr = __ia64_mk_io_addr(port);
+	unsigned char *dp = dst;
 
-	*addr = val;
-	__ia64_mf_a();
+	if (platform_inb == __ia64_inb) {
+		volatile unsigned char *addr = __ia64_mk_io_addr(port);
+
+		__ia64_mf_a();
+		while (count--)
+			*dp++ = *addr;
+		__ia64_mf_a();
+	} else
+		while (count--)
+			*dp++ = platform_inb(port);
+	return;
 }
 
 static inline void
-__outw (unsigned short val, unsigned long port)
+__insw (unsigned long port, void *dst, unsigned long count)
 {
-	volatile unsigned short *addr = __ia64_mk_io_addr(port);
+	unsigned short *dp = dst;
 
-	*addr = val;
-	__ia64_mf_a();
+	if (platform_inw == __ia64_inw) {
+		volatile unsigned short *addr = __ia64_mk_io_addr(port);
+
+		__ia64_mf_a();
+		while (count--)
+			*dp++ = *addr;
+		__ia64_mf_a();
+	} else
+		while (count--)
+			*dp++ = platform_inw(port);
+	return;
 }
 
 static inline void
-__outl (unsigned int val, unsigned long port)
+__insl (unsigned long port, void *dst, unsigned long count)
 {
-	volatile unsigned int *addr = __ia64_mk_io_addr(port);
+	unsigned int *dp = dst;
 
-	*addr = val;
-	__ia64_mf_a();
+	if (platform_inl == __ia64_inl) {
+		volatile unsigned int *addr = __ia64_mk_io_addr(port);
+
+		__ia64_mf_a();
+		while (count--)
+			*dp++ = *addr;
+		__ia64_mf_a();
+	} else
+		while (count--)
+			*dp++ = platform_inl(port);
+	return;
 }
 
 static inline void
 __outsb (unsigned long port, const void *src, unsigned long count)
 {
-	volatile unsigned char *addr = __ia64_mk_io_addr(port);
 	const unsigned char *sp = src;
 
-	while (count--) {
-		*addr = *sp++;
-	}
-	__ia64_mf_a();
+	if (platform_outb == __ia64_outb) {
+		volatile unsigned char *addr = __ia64_mk_io_addr(port);
+
+		while (count--)
+			*addr = *sp++;
+		__ia64_mf_a();
+	} else
+		while (count--)
+			platform_outb(*sp++, port);
 	return;
 }
 
 static inline void
 __outsw (unsigned long port, const void *src, unsigned long count)
 {
-	volatile unsigned short *addr = __ia64_mk_io_addr(port);
 	const unsigned short *sp = src;
 
-	while (count--) {
-		*addr = *sp++;
-	}
-	__ia64_mf_a();
+	if (platform_outw == __ia64_outw) {
+		volatile unsigned short *addr = __ia64_mk_io_addr(port);
+
+		while (count--)
+			*addr = *sp++;
+		__ia64_mf_a();
+	} else
+		while (count--)
+			platform_outw(*sp++, port);
 	return;
 }
 
 static inline void
 __outsl (unsigned long port, void *src, unsigned long count)
 {
-	volatile unsigned int *addr = __ia64_mk_io_addr(port);
 	const unsigned int *sp = src;
 
-	while (count--) {
-		*addr = *sp++;
-	}
-	__ia64_mf_a();
+	if (platform_outl == __ia64_outl) {
+		volatile unsigned int *addr = __ia64_mk_io_addr(port);
+
+		while (count--)
+			*addr = *sp++;
+		__ia64_mf_a();
+	} else
+		while (count--)
+			platform_outl(*sp++, port);
 	return;
 }
 
+/*
+ * Unfortunately, some platforms are broken and do not follow the
+ * IA-64 architecture specification regarding legacy I/O support.
+ * Thus, we have to make these operations platform dependent...
+ */
+#define __inb		platform_inb
+#define __inw		platform_inw
+#define __inl		platform_inl
+#define __outb		platform_outb
+#define __outw		platform_outw
+#define __outl		platform_outl
+
 #define inb		__inb
 #define inw		__inw
 #define inl		__inl
diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h
index 995c948ba..90ab8aacf 100644
--- a/include/asm-ia64/iosapic.h
+++ b/include/asm-ia64/iosapic.h
@@ -1,123 +1,60 @@
 #ifndef __ASM_IA64_IOSAPIC_H
 #define __ASM_IA64_IOSAPIC_H
 
-#include <linux/config.h>
+#define	IOSAPIC_DEFAULT_ADDR	0xFEC00000
 
-#define	IO_SAPIC_DEFAULT_ADDR	0xFEC00000
+#define	IOSAPIC_REG_SELECT	0x0
+#define	IOSAPIC_WINDOW		0x10
+#define	IOSAPIC_EOI		0x40
 
-#define	IO_SAPIC_REG_SELECT	0x0
-#define	IO_SAPIC_WINDOW		0x10
-#define	IO_SAPIC_EOI		0x40
-
-#define	IO_SAPIC_VERSION	0x1
+#define	IOSAPIC_VERSION	0x1
 
 /*
  * Redirection table entry
  */
+#define	IOSAPIC_RTE_LOW(i)	(0x10+i*2)
+#define	IOSAPIC_RTE_HIGH(i)	(0x11+i*2)
 
-#define	IO_SAPIC_RTE_LOW(i)	(0x10+i*2)
-#define	IO_SAPIC_RTE_HIGH(i)	(0x11+i*2)
-
-
-#define	IO_SAPIC_DEST_SHIFT		16
+#define	IOSAPIC_DEST_SHIFT		16
 
 /*
  * Delivery mode
  */
-
-#define	IO_SAPIC_DELIVERY_SHIFT		8
-#define	IO_SAPIC_FIXED			0x0
-#define	IO_SAPIC_LOWEST_PRIORITY	0x1
-#define	IO_SAPIC_PMI			0x2
-#define	IO_SAPIC_NMI			0x4
-#define	IO_SAPIC_INIT			0x5
-#define	IO_SAPIC_EXTINT			0x7
+#define	IOSAPIC_DELIVERY_SHIFT		8
+#define	IOSAPIC_FIXED			0x0
+#define	IOSAPIC_LOWEST_PRIORITY	0x1
+#define	IOSAPIC_PMI			0x2
+#define	IOSAPIC_NMI			0x4
+#define	IOSAPIC_INIT			0x5
+#define	IOSAPIC_EXTINT			0x7
 
 /*
  * Interrupt polarity
  */
-
-#define	IO_SAPIC_POLARITY_SHIFT		13
-#define	IO_SAPIC_POL_HIGH		0
-#define	IO_SAPIC_POL_LOW		1
+#define	IOSAPIC_POLARITY_SHIFT		13
+#define	IOSAPIC_POL_HIGH		0
+#define	IOSAPIC_POL_LOW		1
 
 /*
  * Trigger mode
  */
-
-#define	IO_SAPIC_TRIGGER_SHIFT		15
-#define	IO_SAPIC_EDGE			0
-#define	IO_SAPIC_LEVEL			1
+#define	IOSAPIC_TRIGGER_SHIFT		15
+#define	IOSAPIC_EDGE			0
+#define	IOSAPIC_LEVEL			1
 
 /*
  * Mask bit
  */
-
-#define	IO_SAPIC_MASK_SHIFT		16
-#define	IO_SAPIC_UNMASK			0
-#define	IO_SAPIC_MSAK			1
-
-/*
- * Bus types
- */
-#define  BUS_ISA         0               /* ISA Bus */
-#define  BUS_PCI         1               /* PCI Bus */
-
-#ifndef CONFIG_IA64_PCI_FIRMWARE_IRQ
-struct intr_routing_entry {
-      unsigned char srcbus;
-      unsigned char srcbusno;
-      unsigned char srcbusirq;
-      unsigned char iosapic_pin;
-      unsigned char dstiosapic;
-      unsigned char mode;
-      unsigned char trigger;
-      unsigned char polarity;
-};
-
-extern        struct  intr_routing_entry      intr_routing[];
-#endif
+#define	IOSAPIC_MASK_SHIFT		16
+#define	IOSAPIC_UNMASK			0
+#define	IOSAPIC_MSAK			1
 
 #ifndef __ASSEMBLY__
 
-#include <asm/irq.h>
-
-/*
- * IOSAPIC Version Register return 32 bit structure like:
- * {
- *	unsigned int version   : 8;
- *	unsigned int reserved1 : 8;
- *	unsigned int pins      : 8;
- *	unsigned int reserved2 : 8;
- * }
- */
-extern unsigned int iosapic_version(unsigned long);
-extern void iosapic_init(unsigned long, int);
-
-struct iosapic_vector {
-	unsigned long iosapic_base; /* IOSAPIC Base address */
-        char pin;		    /* IOSAPIC pin (-1 == No data) */
-	unsigned char bus;	    /* Bus number */
-	unsigned char baseirq;	    /* Base IRQ handled by this IOSAPIC */
-	unsigned char bustype;	    /* Bus type (ISA, PCI, etc) */
-	unsigned int busdata;	    /* Bus specific ID */
-        /* These bitfields use the values defined above */
-	unsigned char dmode        : 3;
-	unsigned char polarity     : 1;
-	unsigned char trigger      : 1; 
-	unsigned char UNUSED       : 3;
-};
-extern struct iosapic_vector iosapic_vector[NR_IRQS];
-
-#define iosapic_addr(v)     iosapic_vector[v].iosapic_base
-#define iosapic_pin(v)      iosapic_vector[v].pin
-#define iosapic_bus(v)      iosapic_vector[v].bus
-#define iosapic_baseirq(v)  iosapic_vector[v].baseirq
-#define iosapic_bustype(v)  iosapic_vector[v].bustype
-#define iosapic_busdata(v)  iosapic_vector[v].busdata
-#define iosapic_dmode(v)    iosapic_vector[v].dmode
-#define iosapic_trigger(v)  iosapic_vector[v].trigger
-#define iosapic_polarity(v) iosapic_vector[v].polarity
+extern void __init iosapic_init (unsigned long address, unsigned int base_irq);
+extern void iosapic_register_legacy_irq (unsigned long irq, unsigned long pin,
+					 unsigned long polarity, unsigned long trigger);
+extern void iosapic_pci_fixup (int);
 
 # endif /* !__ASSEMBLY__ */
 #endif /* __ASM_IA64_IOSAPIC_H */
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 3ac473f14..17427531d 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -14,24 +14,46 @@
 #include <linux/types.h>
 
 /* forward declarations: */
-struct hw_interrupt_type;
-struct irq_desc;
-struct mm_struct;
+struct pci_dev;
 struct pt_regs;
-struct task_struct;
-struct timeval;
-struct vm_area_struct;
-struct acpi_entry_iosapic;
+struct scatterlist;
 
 typedef void ia64_mv_setup_t (char **);
 typedef void ia64_mv_irq_init_t (void);
-typedef void ia64_mv_pci_fixup_t (void);
+typedef void ia64_mv_pci_fixup_t (int);
 typedef unsigned long ia64_mv_map_nr_t (unsigned long);
 typedef void ia64_mv_mca_init_t (void);
 typedef void ia64_mv_mca_handler_t (void);
 typedef void ia64_mv_cmci_handler_t (int, void *, struct pt_regs *);
 typedef void ia64_mv_log_print_t (void);
-typedef void ia64_mv_register_iosapic_t (struct acpi_entry_iosapic *);
+typedef void ia64_mv_send_ipi_t (int, int, int, int);
+
+/* PCI-DMA interface: */
+typedef void ia64_mv_pci_dma_init (void);
+typedef void *ia64_mv_pci_alloc_consistent (struct pci_dev *, size_t, dma_addr_t *);
+typedef void ia64_mv_pci_free_consistent (struct pci_dev *, size_t, void *, dma_addr_t);
+typedef dma_addr_t ia64_mv_pci_map_single (struct pci_dev *, void *, size_t, int);
+typedef void ia64_mv_pci_unmap_single (struct pci_dev *, dma_addr_t, size_t, int);
+typedef int ia64_mv_pci_map_sg (struct pci_dev *, struct scatterlist *, int, int);
+typedef void ia64_mv_pci_unmap_sg (struct pci_dev *, struct scatterlist *, int, int);
+typedef void ia64_mv_pci_dma_sync_single (struct pci_dev *, dma_addr_t, size_t, int);
+typedef void ia64_mv_pci_dma_sync_sg (struct pci_dev *, struct scatterlist *, int, int);
+typedef unsigned long ia64_mv_pci_dma_address (struct scatterlist *);
+/*
+ * WARNING: The legacy I/O space is _architected_.  Platforms are
+ * expected to follow this architected model (see Section 10.7 in the
+ * IA-64 Architecture Software Developer's Manual).  Unfortunately,
+ * some broken machines do not follow that model, which is why we have
+ * to make the inX/outX operations part of the machine vector.
+ * Platform designers should follow the architected model whenever
+ * possible.
+ */
+typedef unsigned int ia64_mv_inb_t (unsigned long);
+typedef unsigned int ia64_mv_inw_t (unsigned long);
+typedef unsigned int ia64_mv_inl_t (unsigned long);
+typedef void ia64_mv_outb_t (unsigned char, unsigned long);
+typedef void ia64_mv_outw_t (unsigned short, unsigned long);
+typedef void ia64_mv_outl_t (unsigned int, unsigned long);
 
 extern void machvec_noop (void);
 
@@ -39,7 +61,7 @@ extern void machvec_noop (void);
 #  include <asm/machvec_hpsim.h>
 # elif defined (CONFIG_IA64_DIG)
 #  include <asm/machvec_dig.h>
-# elif defined (CONFIG_IA64_SGI_SN1_SIM)
+# elif defined (CONFIG_IA64_SGI_SN1)
 #  include <asm/machvec_sn1.h>
 # elif defined (CONFIG_IA64_GENERIC)
 
@@ -55,7 +77,23 @@ extern void machvec_noop (void);
 #  define platform_cmci_handler	ia64_mv.cmci_handler
 #  define platform_log_print	ia64_mv.log_print
 #  define platform_pci_fixup	ia64_mv.pci_fixup
-#  define platform_register_iosapic	ia64_mv.register_iosapic
+#  define platform_send_ipi	ia64_mv.send_ipi
+#  define platform_pci_dma_init		ia64_mv.dma_init
+#  define platform_pci_alloc_consistent	ia64_mv.alloc_consistent
+#  define platform_pci_free_consistent	ia64_mv.free_consistent
+#  define platform_pci_map_single	ia64_mv.map_single
+#  define platform_pci_unmap_single	ia64_mv.unmap_single
+#  define platform_pci_map_sg		ia64_mv.map_sg
+#  define platform_pci_unmap_sg		ia64_mv.unmap_sg
+#  define platform_pci_dma_sync_single	ia64_mv.sync_single
+#  define platform_pci_dma_sync_sg	ia64_mv.sync_sg
+#  define platform_pci_dma_address	ia64_mv.dma_address
+#  define platform_inb		ia64_mv.inb
+#  define platform_inw		ia64_mv.inw
+#  define platform_inl		ia64_mv.inl
+#  define platform_outb		ia64_mv.outb
+#  define platform_outw		ia64_mv.outw
+#  define platform_outl		ia64_mv.outl
 # endif
 
 struct ia64_machine_vector {
@@ -68,7 +106,23 @@ struct ia64_machine_vector {
 	ia64_mv_mca_handler_t *mca_handler;
 	ia64_mv_cmci_handler_t *cmci_handler;
 	ia64_mv_log_print_t *log_print;
-	ia64_mv_register_iosapic_t *register_iosapic;
+	ia64_mv_send_ipi_t *send_ipi;
+	ia64_mv_pci_dma_init *dma_init;
+	ia64_mv_pci_alloc_consistent *alloc_consistent;
+	ia64_mv_pci_free_consistent *free_consistent;
+	ia64_mv_pci_map_single *map_single;
+	ia64_mv_pci_unmap_single *unmap_single;
+	ia64_mv_pci_map_sg *map_sg;
+	ia64_mv_pci_unmap_sg *unmap_sg;
+	ia64_mv_pci_dma_sync_single *sync_single;
+	ia64_mv_pci_dma_sync_sg *sync_sg;
+	ia64_mv_pci_dma_address *dma_address;
+	ia64_mv_inb_t *inb;
+	ia64_mv_inw_t *inw;
+	ia64_mv_inl_t *inl;
+	ia64_mv_outb_t *outb;
+	ia64_mv_outw_t *outw;
+	ia64_mv_outl_t *outl;
 };
 
 #define MACHVEC_INIT(name)			\
@@ -82,7 +136,23 @@ struct ia64_machine_vector {
 	platform_mca_handler,			\
 	platform_cmci_handler,			\
 	platform_log_print,			\
-	platform_register_iosapic			\
+	platform_send_ipi,			\
+	platform_pci_dma_init,			\
+	platform_pci_alloc_consistent,		\
+	platform_pci_free_consistent,		\
+	platform_pci_map_single,		\
+	platform_pci_unmap_single,		\
+	platform_pci_map_sg,			\
+	platform_pci_unmap_sg,			\
+	platform_pci_dma_sync_single,		\
+	platform_pci_dma_sync_sg,		\
+	platform_pci_dma_address,		\
+	platform_inb,				\
+	platform_inw,				\
+	platform_inl,				\
+	platform_outb,				\
+	platform_outw,				\
+	platform_outl				\
 }
 
 extern struct ia64_machine_vector ia64_mv;
@@ -93,6 +163,20 @@ extern void machvec_init (const char *name);
 # endif /* CONFIG_IA64_GENERIC */
 
 /*
+ * Declare default routines which aren't declared anywhere else:
+ */
+extern ia64_mv_pci_dma_init swiotlb_init;
+extern ia64_mv_pci_alloc_consistent swiotlb_alloc_consistent;
+extern ia64_mv_pci_free_consistent swiotlb_free_consistent;
+extern ia64_mv_pci_map_single swiotlb_map_single;
+extern ia64_mv_pci_unmap_single swiotlb_unmap_single;
+extern ia64_mv_pci_map_sg swiotlb_map_sg;
+extern ia64_mv_pci_unmap_sg swiotlb_unmap_sg;
+extern ia64_mv_pci_dma_sync_single swiotlb_sync_single;
+extern ia64_mv_pci_dma_sync_sg swiotlb_sync_sg;
+extern ia64_mv_pci_dma_address swiotlb_dma_address;
+
+/*
  * Define default versions so we can extend machvec for new platforms without having
  * to update the machvec files for all existing platforms.
  */
@@ -117,8 +201,56 @@ extern void machvec_init (const char *name);
 #ifndef platform_pci_fixup
 # define platform_pci_fixup	((ia64_mv_pci_fixup_t *) machvec_noop)
 #endif
-#ifndef platform_register_iosapic
-# define platform_register_iosapic	((ia64_mv_register_iosapic_t *) machvec_noop)
+#ifndef platform_send_ipi
+# define platform_send_ipi	ia64_send_ipi	/* default to architected version */
+#endif
+#ifndef platform_pci_dma_init
+# define platform_pci_dma_init		swiotlb_init
+#endif
+#ifndef platform_pci_alloc_consistent
+# define platform_pci_alloc_consistent	swiotlb_alloc_consistent
+#endif
+#ifndef platform_pci_free_consistent
+# define platform_pci_free_consistent	swiotlb_free_consistent
+#endif
+#ifndef platform_pci_map_single
+# define platform_pci_map_single	swiotlb_map_single
+#endif
+#ifndef platform_pci_unmap_single
+# define platform_pci_unmap_single	swiotlb_unmap_single
+#endif
+#ifndef platform_pci_map_sg
+# define platform_pci_map_sg		swiotlb_map_sg
+#endif
+#ifndef platform_pci_unmap_sg
+# define platform_pci_unmap_sg		swiotlb_unmap_sg
+#endif
+#ifndef platform_pci_dma_sync_single
+# define platform_pci_dma_sync_single	swiotlb_sync_single
+#endif
+#ifndef platform_pci_dma_sync_sg
+# define platform_pci_dma_sync_sg	swiotlb_sync_sg
+#endif
+#ifndef platform_pci_dma_address
+# define  platform_pci_dma_address	swiotlb_dma_address
+#endif
+#ifndef platform_inb
+# define platform_inb		__ia64_inb
+#endif
+#ifndef platform_inw
+# define platform_inw		__ia64_inw
+#endif
+#ifndef platform_inl
+# define platform_inl		__ia64_inl
+#endif
+#ifndef platform_outb
+# define platform_outb		__ia64_outb
+#endif
+#ifndef platform_outw
+# define platform_outw		__ia64_outw
+#endif
+#ifndef platform_outl
+# define platform_outl		__ia64_outl
 #endif
 
 #endif /* _ASM_IA64_MACHVEC_H */
diff --git a/include/asm-ia64/machvec_dig.h b/include/asm-ia64/machvec_dig.h
index dedf37cdd..5401fcfb7 100644
--- a/include/asm-ia64/machvec_dig.h
+++ b/include/asm-ia64/machvec_dig.h
@@ -3,9 +3,8 @@
 
 extern ia64_mv_setup_t dig_setup;
 extern ia64_mv_irq_init_t dig_irq_init;
-extern ia64_mv_pci_fixup_t dig_pci_fixup;
+extern ia64_mv_pci_fixup_t iosapic_pci_fixup;
 extern ia64_mv_map_nr_t map_nr_dense;
-extern ia64_mv_register_iosapic_t dig_register_iosapic;
 
 /*
  * This stuff has dual use!
@@ -17,8 +16,7 @@ extern ia64_mv_register_iosapic_t dig_register_iosapic;
 #define platform_name		"dig"
 #define platform_setup		dig_setup
 #define platform_irq_init	dig_irq_init
-#define platform_pci_fixup	dig_pci_fixup
+#define platform_pci_fixup	iosapic_pci_fixup
 #define platform_map_nr		map_nr_dense
-#define platform_register_iosapic dig_register_iosapic
 
 #endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/include/asm-ia64/machvec_hpsim.h b/include/asm-ia64/machvec_hpsim.h
index d36383fb7..9afb30cb5 100644
--- a/include/asm-ia64/machvec_hpsim.h
+++ b/include/asm-ia64/machvec_hpsim.h
@@ -15,7 +15,6 @@ extern ia64_mv_map_nr_t map_nr_dense;
 #define platform_name		"hpsim"
 #define platform_setup		hpsim_setup
 #define platform_irq_init	hpsim_irq_init
-#define platform_pci_fixup	hpsim_pci_fixup
 #define platform_map_nr		map_nr_dense
 
 #endif /* _ASM_IA64_MACHVEC_HPSIM_h */
diff --git a/include/asm-ia64/machvec_init.h b/include/asm-ia64/machvec_init.h
index 2cae5accf..8256910cc 100644
--- a/include/asm-ia64/machvec_init.h
+++ b/include/asm-ia64/machvec_init.h
@@ -4,6 +4,14 @@
 
 #include <asm/machvec.h>
 
+extern ia64_mv_send_ipi_t ia64_send_ipi;
+extern ia64_mv_inb_t __ia64_inb;
+extern ia64_mv_inw_t __ia64_inw;
+extern ia64_mv_inl_t __ia64_inl;
+extern ia64_mv_outb_t __ia64_outb;
+extern ia64_mv_outw_t __ia64_outw;
+extern ia64_mv_outl_t __ia64_outl;
+
 #define MACHVEC_HELPER(name)									\
  struct ia64_machine_vector machvec_##name __attribute__ ((unused, __section__ (".machvec")))	\
 	= MACHVEC_INIT(name);
diff --git a/include/asm-ia64/machvec_sn1.h b/include/asm-ia64/machvec_sn1.h
index bbee99952..0d9a34b87 100644
--- a/include/asm-ia64/machvec_sn1.h
+++ b/include/asm-ia64/machvec_sn1.h
@@ -4,6 +4,23 @@
 extern ia64_mv_setup_t sn1_setup;
 extern ia64_mv_irq_init_t sn1_irq_init;
 extern ia64_mv_map_nr_t sn1_map_nr;
+extern ia64_mv_send_ipi_t sn1_send_IPI;
+extern ia64_mv_pci_fixup_t sn1_pci_fixup;
+extern ia64_mv_inb_t sn1_inb;
+extern ia64_mv_inw_t sn1_inw;
+extern ia64_mv_inl_t sn1_inl;
+extern ia64_mv_outb_t sn1_outb;
+extern ia64_mv_outw_t sn1_outw;
+extern ia64_mv_outl_t sn1_outl;
+extern ia64_mv_pci_alloc_consistent	sn1_pci_alloc_consistent;
+extern ia64_mv_pci_free_consistent	sn1_pci_free_consistent;
+extern ia64_mv_pci_map_single		sn1_pci_map_single;
+extern ia64_mv_pci_unmap_single		sn1_pci_unmap_single;
+extern ia64_mv_pci_map_sg		sn1_pci_map_sg;
+extern ia64_mv_pci_unmap_sg		sn1_pci_unmap_sg;
+extern ia64_mv_pci_dma_sync_single	sn1_pci_dma_sync_single;
+extern ia64_mv_pci_dma_sync_sg		sn1_pci_dma_sync_sg;
+extern ia64_mv_pci_dma_address		sn1_dma_address;
 
 /*
  * This stuff has dual use!
@@ -16,5 +33,22 @@ extern ia64_mv_map_nr_t sn1_map_nr;
 #define platform_setup		sn1_setup
 #define platform_irq_init	sn1_irq_init
 #define platform_map_nr		sn1_map_nr
+#define platform_send_ipi	sn1_send_IPI
+#define platform_pci_fixup	sn1_pci_fixup
+#define platform_inb		sn1_inb
+#define platform_inw		sn1_inw
+#define platform_inl		sn1_inl
+#define platform_outb		sn1_outb
+#define platform_outw		sn1_outw
+#define platform_outl		sn1_outl
+#define platform_pci_alloc_consistent	sn1_pci_alloc_consistent
+#define platform_pci_free_consistent	sn1_pci_free_consistent
+#define platform_pci_map_single		sn1_pci_map_single
+#define platform_pci_unmap_single	sn1_pci_unmap_single
+#define platform_pci_map_sg		sn1_pci_map_sg
+#define platform_pci_unmap_sg		sn1_pci_unmap_sg
+#define platform_pci_dma_sync_single	sn1_pci_dma_sync_single
+#define platform_pci_dma_sync_sg	sn1_pci_dma_sync_sg
+#define platform_pci_dma_address	sn1_dma_address
 
 #endif /* _ASM_IA64_MACHVEC_SN1_h */
diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h
index 054b999f8..d433f4d05 100644
--- a/include/asm-ia64/mca.h
+++ b/include/asm-ia64/mca.h
@@ -18,6 +18,7 @@
 #include <asm/param.h>
 #include <asm/sal.h>
 #include <asm/processor.h>
+#include <asm/hw_irq.h>
 
 /* These are the return codes from all the IA64_MCA specific interfaces */
 typedef	int ia64_mca_return_code_t;
@@ -30,9 +31,9 @@ enum {
 #define IA64_MCA_RENDEZ_TIMEOUT		(100 * HZ)	/* 1000 milliseconds */
 
 /* Interrupt vectors reserved for MC handling. */
-#define IA64_MCA_RENDEZ_INT_VECTOR	0xF3	/* Rendez interrupt */
-#define IA64_MCA_WAKEUP_INT_VECTOR	0x12	/* Wakeup interrupt */
-#define IA64_MCA_CMC_INT_VECTOR		0xF2	/* Correctable machine check interrupt */
+#define IA64_MCA_RENDEZ_INT_VECTOR	MCA_RENDEZ_IRQ	/* Rendez interrupt */
+#define IA64_MCA_WAKEUP_INT_VECTOR	MCA_WAKEUP_IRQ	/* Wakeup interrupt */
+#define IA64_MCA_CMC_INT_VECTOR		CMC_IRQ	/* Correctable machine check interrupt */
 
 #define IA64_CMC_INT_DISABLE		0
 #define IA64_CMC_INT_ENABLE		1
@@ -45,11 +46,11 @@ typedef union cmcv_reg_u {
 	u64	cmcv_regval;
 	struct	{
 		u64  	cmcr_vector		: 8;
-		u64	cmcr_ignored1		: 47;
+		u64	cmcr_reserved1		: 4;
+		u64	cmcr_ignored1		: 1;
+		u64	cmcr_reserved2		: 3;
 		u64	cmcr_mask		: 1;
-		u64	cmcr_reserved1		: 3;
-		u64	cmcr_ignored2		: 1;
-		u64	cmcr_reserved2		: 4;
+		u64	cmcr_ignored2		: 47;
 	} cmcv_reg_s;
 
 } cmcv_reg_t;
diff --git a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h
index 8687682f9..7735da36c 100644
--- a/include/asm-ia64/mman.h
+++ b/include/asm-ia64/mman.h
@@ -23,6 +23,8 @@
 #define MAP_EXECUTABLE	0x1000		/* mark it as an executable */
 #define MAP_LOCKED	0x2000		/* pages are locked */
 #define MAP_NORESERVE	0x4000		/* don't check for reservations */
+#define MAP_WRITECOMBINED 0x10000	/* write-combine the area */
+#define MAP_NONCACHED	0x20000		/* don't cache the memory */
 
 #define MS_ASYNC	1		/* sync memory asynchronously */
 #define MS_INVALIDATE	2		/* invalidate the caches */
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index f385b15cb..c4a673e83 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -6,7 +6,6 @@
  * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
-#include <linux/config.h>
 #include <linux/sched.h>
 #include <linux/spinlock.h>
 
@@ -32,20 +31,11 @@
 
 #define IA64_REGION_ID_KERNEL	0 /* the kernel's region id (tlb.c depends on this being 0) */
 
-#define IA64_REGION_ID_BITS	18
-
-#ifdef CONFIG_IA64_TLB_CHECKS_REGION_NUMBER
-# define IA64_HW_CONTEXT_BITS	IA64_REGION_ID_BITS
-#else
-# define IA64_HW_CONTEXT_BITS	(IA64_REGION_ID_BITS - 3)
-#endif
-
-#define IA64_HW_CONTEXT_MASK	((1UL << IA64_HW_CONTEXT_BITS) - 1)
-
 struct ia64_ctx {
 	spinlock_t lock;
 	unsigned int next;	/* next context number to use */
 	unsigned int limit;	/* next >= limit => must call wrap_mmu_context() */
+	unsigned int max_ctx;	/* max. context value supported by all CPUs */
 };
 
 extern struct ia64_ctx ia64_ctx;
@@ -60,11 +50,7 @@ enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
 static inline unsigned long
 ia64_rid (unsigned long context, unsigned long region_addr)
 {
-# ifdef CONFIG_IA64_TLB_CHECKS_REGION_NUMBER
-	return context;
-# else
 	return context << 3 | (region_addr >> 61);
-# endif
 }
 
 static inline void
@@ -108,12 +94,8 @@ reload_context (struct mm_struct *mm)
 	unsigned long rid_incr = 0;
 	unsigned long rr0, rr1, rr2, rr3, rr4;
 
-	rid = mm->context;
-
-#ifndef CONFIG_IA64_TLB_CHECKS_REGION_NUMBER
-	rid <<= 3;	/* make space for encoding the region number */
+	rid = mm->context << 3;	/* make space for encoding the region number */
 	rid_incr = 1 << 8;
-#endif
 
 	/* encode the region id, preferred page size, and VHPT enable bit: */
 	rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
@@ -132,11 +114,10 @@ reload_context (struct mm_struct *mm)
 }
 
 /*
- * Switch from address space PREV to address space NEXT.  Note that
- * TSK may be NULL.
+ * Switch from address space PREV to address space NEXT.
  */
 static inline void
-switch_mm (struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk, unsigned cpu)
+activate_mm (struct mm_struct *prev, struct mm_struct *next)
 {
 	/*
 	 * We may get interrupts here, but that's OK because interrupt
@@ -147,7 +128,6 @@ switch_mm (struct mm_struct *prev, struct mm_struct *next, struct task_struct *t
 	reload_context(next);
 }
 
-#define activate_mm(prev,next)					\
-	switch_mm((prev), (next), NULL, smp_processor_id())
+#define switch_mm(prev_mm,next_mm,next_task,cpu)	activate_mm(prev_mm, next_mm)
 
 #endif /* _ASM_IA64_MMU_CONTEXT_H */
diff --git a/include/asm-ia64/module.h b/include/asm-ia64/module.h
index d8d19cb2f..3dc52e9bc 100644
--- a/include/asm-ia64/module.h
+++ b/include/asm-ia64/module.h
@@ -75,10 +75,10 @@ ia64_module_init(struct module *mod)
 	/*
 	 * Pointers are reasonable, add the module unwind table
 	 */
-	archdata->unw_table = unw_add_unwind_table(mod->name, archdata->segment_base,
+	archdata->unw_table = unw_add_unwind_table(mod->name,
+						   (unsigned long) archdata->segment_base,
 						   (unsigned long) archdata->gp,
-						   (unsigned long) archdata->unw_start,
-						   (unsigned long) archdata->unw_end);
+						   archdata->unw_start, archdata->unw_end);
 #endif /* CONFIG_IA64_NEW_UNWIND */
 	return 0;
 }
@@ -98,7 +98,7 @@ ia64_module_unmap(void * addr)
 		archdata = (struct archdata *)(mod->archdata_start);
 
 		if (archdata->unw_table != NULL)
-			unw_remove_unwind_table(archdata->unw_table);
+			unw_remove_unwind_table((void *) archdata->unw_table);
 	}
 #endif /* CONFIG_IA64_NEW_UNWIND */
 
diff --git a/include/asm-ia64/offsets.h b/include/asm-ia64/offsets.h
index 64e9f2fef..2d9f3f782 100644
--- a/include/asm-ia64/offsets.h
+++ b/include/asm-ia64/offsets.h
@@ -11,7 +11,7 @@
 #define PT_PTRACED_BIT			0
 #define PT_TRACESYS_BIT			1
 
-#define IA64_TASK_SIZE			3328	/* 0xd00 */
+#define IA64_TASK_SIZE			3376	/* 0xd30 */
 #define IA64_PT_REGS_SIZE		400	/* 0x190 */
 #define IA64_SWITCH_STACK_SIZE		560	/* 0x230 */
 #define IA64_SIGINFO_SIZE		128	/* 0x80 */
@@ -21,10 +21,10 @@
 #define IA64_TASK_SIGPENDING_OFFSET	16	/* 0x10 */
 #define IA64_TASK_NEED_RESCHED_OFFSET	40	/* 0x28 */
 #define IA64_TASK_PROCESSOR_OFFSET	100	/* 0x64 */
-#define IA64_TASK_THREAD_OFFSET		1424	/* 0x590 */
-#define IA64_TASK_THREAD_KSP_OFFSET	1424	/* 0x590 */
-#define IA64_TASK_THREAD_SIGMASK_OFFSET	3184	/* 0xc70 */
-#define IA64_TASK_PID_OFFSET		188	/* 0xbc */
+#define IA64_TASK_THREAD_OFFSET		1456	/* 0x5b0 */
+#define IA64_TASK_THREAD_KSP_OFFSET	1456	/* 0x5b0 */
+#define IA64_TASK_THREAD_SIGMASK_OFFSET	3224	/* 0xc98 */
+#define IA64_TASK_PID_OFFSET		196	/* 0xc4 */
 #define IA64_TASK_MM_OFFSET		88	/* 0x58 */
 #define IA64_PT_REGS_CR_IPSR_OFFSET	0	/* 0x0 */
 #define IA64_PT_REGS_CR_IIP_OFFSET	8	/* 0x8 */
@@ -115,7 +115,7 @@
 #define IA64_SWITCH_STACK_AR_UNAT_OFFSET	528	/* 0x210 */
 #define IA64_SWITCH_STACK_AR_RNAT_OFFSET	536	/* 0x218 */
 #define IA64_SWITCH_STACK_AR_BSPSTORE_OFFSET 544	/* 0x220 */
-#define IA64_SWITCH_STACK_PR_OFFSET	464	/* 0x1d0 */
+#define IA64_SWITCH_STACK_PR_OFFSET	552	/* 0x228 */
 #define IA64_SIGCONTEXT_AR_BSP_OFFSET	72	/* 0x48 */
 #define IA64_SIGCONTEXT_AR_RNAT_OFFSET	80	/* 0x50 */
 #define IA64_SIGCONTEXT_FLAGS_OFFSET	0	/* 0x0 */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index c81337e07..b98593094 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -40,9 +40,6 @@
 extern void clear_page (void *page);
 extern void copy_page (void *to, void *from);
 
-#define clear_user_page(page, vaddr)	clear_page(page)
-#define copy_user_page(to, from, vaddr)	copy_page(to, from)
-
 #  ifdef STRICT_MM_TYPECHECKS
 /*
  * These are used to make use of C type-checking..
@@ -58,7 +55,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define pgprot_val(x)	((x).pgprot)
 
 #define __pte(x)	((pte_t) { (x) } )
-#define __pgd(x)	((pgd_t) { (x) } )
 #define __pgprot(x)	((pgprot_t) { (x) } )
 
 #  else /* !STRICT_MM_TYPECHECKS */
@@ -93,21 +89,17 @@ typedef unsigned long pgprot_t;
  */
 #define MAP_NR_DENSE(addr)	(((unsigned long) (addr) - PAGE_OFFSET) >> PAGE_SHIFT)
 
-/*
- * This variant works well for the SGI SN1 architecture (which does have huge
- * holes in the memory address space).
- */
-#define MAP_NR_SN1(addr)	(((unsigned long) (addr) - PAGE_OFFSET) >> PAGE_SHIFT)
-
 #ifdef CONFIG_IA64_GENERIC
 # include <asm/machvec.h>
-# define virt_to_page(kaddr)   (mem_map + platform_map_nr(kaddr))
-#elif defined (CONFIG_IA64_SN_SN1)
-# define virt_to_page(kaddr)   (mem_map + MAP_NR_SN1(kaddr))
+# define virt_to_page(kaddr)	(mem_map + platform_map_nr(kaddr))
+#elif defined (CONFIG_IA64_SGI_SN1)
+# ifndef CONFIG_DISCONTIGMEM
+#  define virt_to_page(kaddr)	(mem_map + MAP_NR_DENSE(kaddr))
+# endif
 #else
-# define virt_to_page(kaddr)   (mem_map + MAP_NR_DENSE(kaddr))
+# define virt_to_page(kaddr)	(mem_map + MAP_NR_DENSE(kaddr))
 #endif
-#define VALID_PAGE(page)       ((page - mem_map) < max_mapnr)
+#define VALID_PAGE(page)	((page - mem_map) < max_mapnr)
 
 typedef union ia64_va {
 	struct {
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index 652aaffca..7b350ee52 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -21,125 +21,42 @@
 
 struct pci_dev;
 
-static inline void pcibios_set_master(struct pci_dev *dev)
+static inline void
+pcibios_set_master (struct pci_dev *dev)
 {
 	/* No special bus mastering setup handling */
 }
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void
+pcibios_penalize_isa_irq (int irq)
 {
 	/* We don't do dynamic PCI IRQ allocation */
 }
 
 /*
- * Dynamic DMA mapping API.
+ * Dynamic DMA mapping API.  See Documentation/DMA-mapping.txt for details.
  */
+#define pci_alloc_consistent		platform_pci_alloc_consistent
+#define pci_free_consistent		platform_pci_free_consistent
+#define pci_map_single			platform_pci_map_single
+#define pci_unmap_single		platform_pci_unmap_single
+#define pci_map_sg			platform_pci_map_sg
+#define pci_unmap_sg			platform_pci_unmap_sg
+#define pci_dma_sync_single		platform_pci_dma_sync_single
+#define pci_dma_sync_sg			platform_pci_dma_sync_sg
+#define sg_dma_address			platform_pci_dma_address
 
 /*
- * Allocate and map kernel buffer using consistent mode DMA for a device.
- * hwdev should be valid struct pci_dev pointer for PCI devices,
- * NULL for PCI-like buses (ISA, EISA).
- * Returns non-NULL cpu-view pointer to the buffer if successful and
- * sets *dma_addrp to the pci side dma address as well, else *dma_addrp
- * is undefined.
- */
-extern void *pci_alloc_consistent (struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
-
-/*
- * Free and unmap a consistent DMA buffer.
- * cpu_addr is what was returned from pci_alloc_consistent,
- * size must be the same as what as passed into pci_alloc_consistent,
- * and likewise dma_addr must be the same as what *dma_addrp was set to.
- *
- * References to the memory and mappings associated with cpu_addr/dma_addr
- * past this call are illegal.
- */
-extern void pci_free_consistent (struct pci_dev *hwdev, size_t size,
-				 void *vaddr, dma_addr_t dma_handle);
-
-/*
- * Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single is performed.
- */
-extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
-
-/*
- * Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-extern void pci_unmap_single (struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
-
-/*
- * Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
-
-/*
- * Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
-
-/*
- * Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so.  At the
- * next point you give the PCI dma address back to the card, the
- * device again owns the buffer.
- */
-extern void pci_dma_sync_single (struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
-
-/*
- * Make physical memory consistent for a set of streaming mode DMA
- * translations after a transfer.
- *
- * The same as pci_dma_sync_single but for a scatter-gather list,
- * same rules and usage.
- */
-extern void pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
-
-/* Return whether the given PCI device DMA address mask can
- * be supported properly.  For example, if your device can
- * only drive the low 24-bits during PCI bus mastering, then
+ * Return whether the given PCI device DMA address mask can be supported properly.  For
+ * example, if your device can only drive the low 24-bits during PCI bus mastering, then
  * you would pass 0x00ffffff as the mask to this function.
  */
 static inline int
-pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
+pci_dma_supported (struct pci_dev *hwdev, dma_addr_t mask)
 {
 	return 1;
 }
 
-/* These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns, or alternatively stop on the first sg_dma_len(sg) which
- * is 0.
- */
-#define sg_dma_address(sg)	(virt_to_bus((sg)->address))
 #define sg_dma_len(sg)		((sg)->length)
 
 #endif /* _ASM_IA64_PCI_H */
diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h
index 5256a4fff..800807df6 100644
--- a/include/asm-ia64/pgalloc.h
+++ b/include/asm-ia64/pgalloc.h
@@ -15,6 +15,7 @@
 
 #include <linux/config.h>
 
+#include <linux/mm.h>
 #include <linux/threads.h>
 
 #include <asm/mmu_context.h>
@@ -175,11 +176,8 @@ pmd_alloc (pgd_t *pgd, unsigned long vmaddr)
 		if (!pmd_page)
 			pmd_page = get_pmd_slow();
 		if (pmd_page) {
-			if (pgd_none(*pgd)) {
-				pgd_set(pgd, pmd_page);
-				return pmd_page + offset;
-			} else
-				free_pmd_fast(pmd_page);
+			pgd_set(pgd, pmd_page);
+			return pmd_page + offset;
 		} else
 			return NULL;
 	}
@@ -196,13 +194,6 @@ pmd_alloc (pgd_t *pgd, unsigned long vmaddr)
 extern int do_check_pgt_cache (int, int);
 
 /*
- * This establishes kernel virtual mappings (e.g., as a result of a
- * vmalloc call).  Since ia-64 uses a separate kernel page table,
- * there is nothing to do here... :)
- */
-#define set_pgdir(vmaddr, entry)	do { } while(0)
-
-/*
  * Now for some TLB flushing routines.  This is the kind of stuff that
  * can be very expensive, so try to avoid them whenever possible.
  */
@@ -249,7 +240,12 @@ extern void flush_tlb_range (struct mm_struct *mm, unsigned long start, unsigned
 static __inline__ void
 flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
 {
-	flush_tlb_range(vma->vm_mm, addr, addr + PAGE_SIZE);
+#ifdef CONFIG_SMP
+	flush_tlb_range(vma->vm_mm, (addr & PAGE_MASK), (addr & PAGE_MASK) + PAGE_SIZE);
+#else
+	if (vma->vm_mm == current->active_mm)
+		asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(PAGE_SHIFT << 2) : "memory");
+#endif
 }
 
 /*
@@ -259,14 +255,66 @@ flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
 static inline void
 flush_tlb_pgtables (struct mm_struct *mm, unsigned long start, unsigned long end)
 {
-	/*
-	 * XXX fix mmap(), munmap() et al to guarantee that there are no mappings
-	 * across region boundaries. --davidm 00/02/23
-	 */
-	if (rgn_index(start) != rgn_index(end)) {
+	if (rgn_index(start) != rgn_index(end))
 		printk("flush_tlb_pgtables: can't flush across regions!!\n");
-	}
 	flush_tlb_range(mm, ia64_thash(start), ia64_thash(end));
 }
 
+/*
+ * Now for some cache flushing routines.  This is the kind of stuff
+ * that can be very expensive, so try to avoid them whenever possible.
+ */
+
+/* Caches aren't brain-dead on the IA-64. */
+#define flush_cache_all()			do { } while (0)
+#define flush_cache_mm(mm)			do { } while (0)
+#define flush_cache_range(mm, start, end)	do { } while (0)
+#define flush_cache_page(vma, vmaddr)		do { } while (0)
+#define flush_page_to_ram(page)			do { } while (0)
+
+extern void flush_icache_range (unsigned long start, unsigned long end);
+
+static inline void
+flush_dcache_page (struct page *page)
+{
+	clear_bit(PG_arch_1, &page->flags);
+}
+
+static inline void
+clear_user_page (void *addr, unsigned long vaddr, struct page *page)
+{
+	clear_page(addr);
+	flush_dcache_page(page);
+}
+
+static inline void
+copy_user_page (void *to, void *from, unsigned long vaddr, struct page *page)
+{
+	copy_page(to, from);
+	flush_dcache_page(page);
+}
+
+/*
+ * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
+ * information.  However, we use this macro to take care of any (delayed) i-cache flushing
+ * that may be necessary.
+ */
+static inline void
+update_mmu_cache (struct vm_area_struct *vma, unsigned long address, pte_t pte)
+{
+	struct page *page;
+
+	if (!pte_exec(pte))
+		return;				/* not an executable page... */
+
+	page = pte_page(pte);
+	address &= PAGE_MASK;
+
+	if (test_bit(PG_arch_1, &page->flags))
+		return;				/* i-cache is already coherent with d-cache */
+
+	flush_icache_range(address, address + PAGE_SIZE);
+	set_bit(PG_arch_1, &page->flags);	/* mark page as clean */
+}
+
 #endif /* _ASM_IA64_PGALLOC_H */
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index 6fbed9cc1..28fc7e617 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -12,6 +12,7 @@
  * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
+#include <linux/config.h>
 #include <asm/mman.h>
 #include <asm/page.h>
 #include <asm/processor.h>
@@ -24,7 +25,11 @@
  * matches the VHPT short format, the firt doubleword of the VHPD long
  * format, and the first doubleword of the TLB insertion format.
  */
-#define _PAGE_P			(1 <<  0)	/* page present bit */
+#define _PAGE_P_BIT		0
+#define _PAGE_A_BIT		5
+#define _PAGE_D_BIT		6
+
+#define _PAGE_P			(1 << _PAGE_P_BIT)	/* page present bit */
 #define _PAGE_MA_WB		(0x0 <<  2)	/* write back memory attribute */
 #define _PAGE_MA_UC		(0x4 <<  2)	/* uncacheable memory attribute */
 #define _PAGE_MA_UCE		(0x5 <<  2)	/* UC exported attribute */
@@ -46,8 +51,8 @@
 #define _PAGE_AR_X_RX		(7 <<  9)	/* exec & promote / read & exec */
 #define _PAGE_AR_MASK		(7 <<  9)
 #define _PAGE_AR_SHIFT		9
-#define _PAGE_A			(1 <<  5)	/* page accessed bit */
-#define _PAGE_D			(1 <<  6)	/* page dirty bit */
+#define _PAGE_A			(1 << _PAGE_A_BIT)	/* page accessed bit */
+#define _PAGE_D			(1 << _PAGE_D_BIT)	/* page dirty bit */
 #define _PAGE_PPN_MASK		(((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
 #define _PAGE_ED		(__IA64_UL(1) << 52)	/* exception deferral */
 #define _PAGE_PROTNONE		(__IA64_UL(1) << 63)
@@ -79,7 +84,7 @@
 #define PGDIR_SIZE		(__IA64_UL(1) << PGDIR_SHIFT)
 #define PGDIR_MASK		(~(PGDIR_SIZE-1))
 #define PTRS_PER_PGD		(__IA64_UL(1) << (PAGE_SHIFT-3))
-#define USER_PTRS_PER_PGD	PTRS_PER_PGD
+#define USER_PTRS_PER_PGD	(5*PTRS_PER_PGD/8)	/* regions 0-4 are user regions */
 #define FIRST_USER_PGD_NR	0
 
 /*
@@ -98,9 +103,6 @@
  */
 #define PTRS_PER_PTE	(__IA64_UL(1) << (PAGE_SHIFT-3))
 
-/* Number of pointers that fit on a page:  this will go away. */
-#define PTRS_PER_PAGE	(__IA64_UL(1) << (PAGE_SHIFT-3))
-
 # ifndef __ASSEMBLY__
 
 #include <asm/bitops.h>
@@ -110,12 +112,17 @@
 /*
  * All the normal masks have the "page accessed" bits on, as any time
  * they are used, the page is accessed. They are cleared only by the
- * page-out routines
+ * page-out routines.  On the other hand, we do NOT turn on the
+ * execute bit on pages that are mapped writable.  For those pages, we
+ * turn on the X bit only when the program attempts to actually
+ * execute code in such a page (it's a "lazy execute bit", if you
+ * will).  This lets reduce the amount of i-cache flushing we have to
+ * do for data pages such as stack and heap pages.
  */
 #define PAGE_NONE	__pgprot(_PAGE_PROTNONE | _PAGE_A)
 #define PAGE_SHARED	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
 #define PAGE_READONLY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
-#define PAGE_COPY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
+#define PAGE_COPY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
 #define PAGE_GATE	__pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
 #define PAGE_KERNEL	__pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX)
 
@@ -132,19 +139,19 @@
 #define __P001	PAGE_READONLY
 #define __P010	PAGE_READONLY	/* write to priv pg -> copy & make writable */
 #define __P011	PAGE_READONLY	/* ditto */
-#define __P100	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_X_RX)
-#define __P101	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)
-#define __P110	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)
-#define __P111	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)
+#define __P100	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
+#define __P101	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
+#define __P110	PAGE_COPY
+#define __P111	PAGE_COPY
 
 #define __S000	PAGE_NONE
 #define __S001	PAGE_READONLY
 #define __S010	PAGE_SHARED	/* we don't have (and don't need) write-only */
 #define __S011	PAGE_SHARED
-#define __S100	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_X_RX)
-#define __S101	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)
-#define __S110	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_RWX)
-#define __S111	__pgprot(_PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_PL_3 | _PAGE_AR_RWX)
+#define __S100	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
+#define __S101	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
+#define __S110	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
+#define __S111	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
 
 #define pgd_ERROR(e)	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
 #define pmd_ERROR(e)	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
@@ -162,30 +169,8 @@
  */
 #define page_address(page)	((page)->virtual)
 
-/*
- * Now for some cache flushing routines.  This is the kind of stuff
- * that can be very expensive, so try to avoid them whenever possible.
- */
-
-/* Caches aren't brain-dead on the ia-64. */
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_range(mm, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr)		do { } while (0)
-#define flush_page_to_ram(page)			do { } while (0)
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_icache_range(start, end)		do { } while (0)
-
-extern void ia64_flush_icache_page (unsigned long addr);
-
-#define flush_icache_page(vma,pg)				\
-do {								\
-	if ((vma)->vm_flags & PROT_EXEC)			\
-		ia64_flush_icache_page((unsigned long) page_address(pg));	\
-} while (0)
-
 /* Quick test to see if ADDR is a (potentially) valid physical address. */
-static __inline__ long
+static inline long
 ia64_phys_addr_valid (unsigned long addr)
 {
 	return (addr & (my_cpu_data.unimpl_pa_mask)) == 0;
@@ -213,13 +198,17 @@ ia64_phys_addr_valid (unsigned long addr)
 
 /*
  * On some architectures, special things need to be done when setting
- * the PTE in a page table.  Nothing special needs to be on ia-64.
+ * the PTE in a page table.  Nothing special needs to be on IA-64.
  */
 #define set_pte(ptep, pteval)	(*(ptep) = (pteval))
 
-#define VMALLOC_START		(0xa000000000000000+2*PAGE_SIZE)
+#define RGN_SIZE	(1UL << 61)
+#define RGN_MAP_LIMIT	(1UL << (4*PAGE_SHIFT - 12))	/* limit of mappable area in region */
+#define RGN_KERNEL	7
+
+#define VMALLOC_START		(0xa000000000000000 + 2*PAGE_SIZE)
 #define VMALLOC_VMADDR(x)	((unsigned long)(x))
-#define VMALLOC_END		0xbfffffffffffffff
+#define VMALLOC_END		(0xa000000000000000 + RGN_MAP_LIMIT)
 
 /*
  * BAD_PAGETABLE is used when we need a bogus page-table, while
@@ -280,19 +269,19 @@ extern pmd_t *ia64_bad_pagetable (void);
  * The following have defined behavior only work if pte_present() is true.
  */
 #define pte_read(pte)		(((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
-#define pte_write(pte)	((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) < 4)
-#define pte_dirty(pte)		(pte_val(pte) & _PAGE_D)
-#define pte_young(pte)		(pte_val(pte) & _PAGE_A)
+#define pte_write(pte)	((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
+#define pte_exec(pte)		((pte_val(pte) & _PAGE_AR_RX) != 0)
+#define pte_dirty(pte)		((pte_val(pte) & _PAGE_D) != 0)
+#define pte_young(pte)		((pte_val(pte) & _PAGE_A) != 0)
 /*
- * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the
- * 2nd bit in the access rights:
+ * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
+ * access rights:
  */
 #define pte_wrprotect(pte)	(__pte(pte_val(pte) & ~_PAGE_AR_RW))
 #define pte_mkwrite(pte)	(__pte(pte_val(pte) | _PAGE_AR_RW))
-
+#define pte_mkexec(pte)		(__pte(pte_val(pte) | _PAGE_AR_RX))
 #define pte_mkold(pte)		(__pte(pte_val(pte) & ~_PAGE_A))
 #define pte_mkyoung(pte)	(__pte(pte_val(pte) | _PAGE_A))
-
 #define pte_mkclean(pte)	(__pte(pte_val(pte) & ~_PAGE_D))
 #define pte_mkdirty(pte)	(__pte(pte_val(pte) | _PAGE_D))
 
@@ -317,7 +306,7 @@ extern pmd_t *ia64_bad_pagetable (void);
 /*
  * Return the region index for virtual address ADDRESS.
  */
-static __inline__ unsigned long
+static inline unsigned long
 rgn_index (unsigned long address)
 {
 	ia64_va a;
@@ -329,7 +318,7 @@ rgn_index (unsigned long address)
 /*
  * Return the region offset for virtual address ADDRESS.
  */
-static __inline__ unsigned long
+static inline unsigned long
 rgn_offset (unsigned long address)
 {
 	ia64_va a;
@@ -338,10 +327,7 @@ rgn_offset (unsigned long address)
 	return a.f.off;
 }
 
-#define RGN_SIZE	(1UL << 61)
-#define RGN_KERNEL	7
-
-static __inline__ unsigned long
+static inline unsigned long
 pgd_index (unsigned long address)
 {
 	unsigned long region = address >> 61;
@@ -352,7 +338,7 @@ pgd_index (unsigned long address)
 
 /* The offset in the 1-level directory is given by the 3 region bits
    (61..63) and the seven level-1 bits (33-39).  */
-static __inline__ pgd_t*
+static inline pgd_t*
 pgd_offset (struct mm_struct *mm, unsigned long address)
 {
 	return mm->pgd + pgd_index(address);
@@ -371,56 +357,102 @@ pgd_offset (struct mm_struct *mm, unsigned long address)
 #define pte_offset(dir,addr) \
 	((pte_t *) pmd_page(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 
+/* atomic versions of the some PTE manipulations: */
 
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-extern void paging_init (void);
+static inline int
+ptep_test_and_clear_young (pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+	return test_and_clear_bit(_PAGE_A_BIT, ptep);
+#else
+	pte_t pte = *ptep;
+	if (!pte_young(pte))
+		return 0;
+	set_pte(ptep, pte_mkold(pte));
+	return 1;
+#endif
+}
 
-/*
- * IA-64 doesn't have any external MMU info: the page tables contain
- * all the necessary information.  However, we can use this macro
- * to pre-install (override) a PTE that we know is needed anyhow.
- *
- * Asit says that on Itanium, it is generally faster to let the VHPT
- * walker pick up a newly installed PTE (and VHPT misses should be
- * extremely rare compared to normal misses).  Also, since
- * pre-installing the PTE has the problem that we may evict another
- * TLB entry needlessly because we don't know for sure whether we need
- * to update the iTLB or dTLB, I tend to prefer this solution, too.
- * Also, this avoids nasty issues with forward progress (what if the
- * newly installed PTE gets replaced before we return to the previous
- * execution context?).
- *
- */
-#if 1
-# define update_mmu_cache(vma,address,pte)
+static inline int
+ptep_test_and_clear_dirty (pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+	return test_and_clear_bit(_PAGE_D_BIT, ptep);
 #else
-# define update_mmu_cache(vma,address,pte)							\
-do {												\
-	/*											\
-	 * XXX fix me!!										\
-	 *											\
-	 * It's not clear this is a win.  We may end up pollute the				\
-	 * dtlb with itlb entries and vice versa (e.g., consider stack				\
-	 * pages that are normally marked executable).  It would be				\
-	 * better to insert the TLB entry for the TLB cache that we				\
-	 * know needs the new entry.  However, the update_mmu_cache()				\
-	 * arguments don't tell us whether we got here through a data				\
-	 * access or through an instruction fetch.  Talk to Linus to				\
-	 * fix this.										\
-	 *											\
-	 * If you re-enable this code, you must disable the ptc code in				\
-	 * Entry 20 of the ivt.									\
-	 */											\
-	unsigned long flags;									\
-												\
-	ia64_clear_ic(flags);									\
-	ia64_itc((vma->vm_flags & PROT_EXEC) ? 0x3 : 0x2, address, pte_val(pte), PAGE_SHIFT);	\
-	__restore_flags(flags);									\
-} while (0)
+	pte_t pte = *ptep;
+	if (!pte_dirty(pte))
+		return 0;
+	set_pte(ptep, pte_mkclean(pte));
+	return 1;
 #endif
+}
+
+static inline pte_t
+ptep_get_and_clear (pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+	return __pte(xchg((long *) ptep, 0));
+#else
+	pte_t pte = *ptep;
+	pte_clear(ptep);
+	return pte;
+#endif
+}
+
+static inline void
+ptep_set_wrprotect (pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+	unsigned long new, old;
+
+	do {
+		old = pte_val(*ptep);
+		new = pte_val(pte_wrprotect(__pte (old)));
+	} while (cmpxchg((unsigned long *) ptep, old, new) != old);
+#else
+	pte_t old_pte = *ptep;
+	set_pte(ptep, pte_wrprotect(old_pte));
+#endif
+}
+
+static inline void
+ptep_mkdirty (pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+	set_bit(_PAGE_D_BIT, ptep);
+#else
+	pte_t old_pte = *ptep;
+	set_pte(ptep, pte_mkdirty(old_pte));
+#endif
+}
+
+static inline int
+pte_same (pte_t a, pte_t b)
+{
+	return pte_val(a) == pte_val(b);
+}
+
+/*
+ * Macros to check the type of access that triggered a page fault.
+ */
+
+static inline int
+is_write_access (int access_type)
+{
+	return (access_type & 0x2);
+}
+
+static inline int
+is_exec_access (int access_type)
+{
+	return (access_type & 0x4);
+}
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern void paging_init (void);
 
 #define SWP_TYPE(entry)			(((entry).val >> 1) & 0xff)
-#define SWP_OFFSET(entry)		((entry).val >> 9)
+#define SWP_OFFSET(entry)		(((entry).val << 1) >> 10)
 #define SWP_ENTRY(type,offset)		((swp_entry_t) { ((type) << 1) | ((offset) << 9) })
 #define pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
 #define swp_entry_to_pte(x)		((pte_t) { (x).val })
@@ -437,7 +469,8 @@ do {												\
 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 
-#include <asm-generic/pgtable.h>
+/* We provide our own get_unmapped_area to cope with VA holes for userland */
+#define HAVE_ARCH_UNMAPPED_AREA
 
 # endif /* !__ASSEMBLY__ */
 
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 2fb8e357f..c66306c4c 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -4,7 +4,7 @@
 /*
  * Copyright (C) 1998-2000 Hewlett-Packard Co
  * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998, 1999 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 1998-2000 Stephane Eranian <eranian@hpl.hp.com>
  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  *
@@ -19,15 +19,21 @@
 #include <asm/types.h>
 
 #define IA64_NUM_DBG_REGS	8
-#define IA64_NUM_PM_REGS	4
+/*
+ * Limits for PMC and PMD are set to less than maximum architected values
+ * but should be sufficient for a while
+ */
+#define IA64_NUM_PMC_REGS	32
+#define IA64_NUM_PMD_REGS	32
+#define IA64_NUM_PMD_COUNTERS	4
 
 /*
  * TASK_SIZE really is a mis-named.  It really is the maximum user
- * space address (plus one).  On ia-64, there are five regions of 2TB
+ * space address (plus one).  On IA-64, there are five regions of 2TB
  * each (assuming 8KB page size), for a total of 8TB of user virtual
  * address space.
  */
-#define TASK_SIZE		0xa000000000000000
+#define TASK_SIZE		(current->thread.task_size)
 
 /*
  * This decides where the kernel will search for a free chunk of vm
@@ -157,6 +163,7 @@
 #define IA64_THREAD_UAC_NOPRINT	(__IA64_UL(1) << 3)	/* don't log unaligned accesses */
 #define IA64_THREAD_UAC_SIGBUS	(__IA64_UL(1) << 4)	/* generate SIGBUS on unaligned acc. */
 #define IA64_THREAD_KRBS_SYNCED	(__IA64_UL(1) << 5)	/* krbs synced with process vm? */
+#define IA64_THREAD_MAP_SHARED	(__IA64_UL(1) << 6)	/* ugly: just a tmp flag for mmap() */
 #define IA64_KERNEL_DEATH	(__IA64_UL(1) << 63)	/* see die_if_kernel()... */
 
 #define IA64_THREAD_UAC_SHIFT	3
@@ -242,8 +249,11 @@ struct cpuinfo_ia64 {
 	__u64 usec_per_cyc;	/* 2^IA64_USEC_PER_CYC_SHIFT*1000000/itc_freq */
 	__u64 unimpl_va_mask;	/* mask of unimplemented virtual address bits (from PAL) */
 	__u64 unimpl_pa_mask;	/* mask of unimplemented physical address bits (from PAL) */
+	__u64 ptce_base;
+	__u32 ptce_count[2];
+	__u32 ptce_stride[2];
 #ifdef CONFIG_SMP
-	__u64 loops_per_sec;
+	__u64 loops_per_jiffy;
 	__u64 ipi_count;
 	__u64 prof_counter;
 	__u64 prof_multiplier;
@@ -252,12 +262,6 @@ struct cpuinfo_ia64 {
 
 #define my_cpu_data		cpu_data[smp_processor_id()]
 
-#ifdef CONFIG_SMP
-# define ia64_loops_per_sec()	my_cpu_data.loops_per_sec
-#else
-# define ia64_loops_per_sec()	loops_per_sec
-#endif
-
 extern struct cpuinfo_ia64 cpu_data[NR_CPUS];
 
 extern void identify_cpu (struct cpuinfo_ia64 *);
@@ -288,14 +292,20 @@ struct thread_struct {
 	__u64 dbr[IA64_NUM_DBG_REGS];
 	__u64 ibr[IA64_NUM_DBG_REGS];
 #ifdef CONFIG_PERFMON
-	__u64 pmc[IA64_NUM_PM_REGS];
-	__u64 pmd[IA64_NUM_PM_REGS];
-	__u64 pmod[IA64_NUM_PM_REGS];
-# define INIT_THREAD_PM		{0, }, {0, }, {0, },
+	__u64 pmc[IA64_NUM_PMC_REGS];
+	__u64 pmd[IA64_NUM_PMD_REGS];
+	struct {
+		__u64		val;	/* virtual 64bit counter */
+		__u64		rval;	/* reset value on overflow */
+		int		sig;	/* signal used to notify */
+		int		pid;	/* process to notify */
+	} pmu_counters[IA64_NUM_PMD_COUNTERS];
+# define INIT_THREAD_PM		{0, }, {0, }, {{ 0, 0, 0, 0}, },
 #else
 # define INIT_THREAD_PM
 #endif
-	__u64 map_base;			/* base address for mmap() */
+	__u64 map_base;			/* base address for get_unmapped_area() */
+	__u64 task_size;		/* limit for task size */
 #ifdef CONFIG_IA32_SUPPORT
 	__u64 eflag;			/* IA32 EFLAGS reg */
 	__u64 fsr;			/* IA32 floating pt status reg */
@@ -309,7 +319,7 @@ struct thread_struct {
 	union {
 		__u64 sigmask;		/* aligned mask for sigsuspend scall */
 	} un;
-# define INIT_THREAD_IA32	, 0, 0, 0x17800000037fULL, 0, 0, 0, 0, 0, 0, {0}
+# define INIT_THREAD_IA32	0, 0, 0x17800000037fULL, 0, 0, 0, 0, 0, 0, {0},
 #else
 # define INIT_THREAD_IA32
 #endif /* CONFIG_IA32_SUPPORT */
@@ -328,8 +338,9 @@ struct thread_struct {
 	{0, },				/* dbr */	\
 	{0, },				/* ibr */	\
 	INIT_THREAD_PM					\
-	0x2000000000000000		/* map_base */	\
-	INIT_THREAD_IA32,				\
+	0x2000000000000000,		/* map_base */	\
+	0xa000000000000000,		/* task_size */	\
+	INIT_THREAD_IA32				\
 	0				/* siginfo */	\
 }
 
@@ -422,8 +433,8 @@ extern void ia32_load_state (struct thread_struct *thread);
 #endif
 
 #ifdef CONFIG_PERFMON
-extern void ia64_save_pm_regs (struct thread_struct *thread);
-extern void ia64_load_pm_regs (struct thread_struct *thread);
+extern void ia64_save_pm_regs (struct task_struct *task);
+extern void ia64_load_pm_regs (struct task_struct *task);
 #endif
 
 #define ia64_fph_enable()	__asm__ __volatile__ (";; rsm psr.dfh;; srlz.d;;" ::: "memory");
diff --git a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h
index 68ebe286e..96b20f487 100644
--- a/include/asm-ia64/ptrace.h
+++ b/include/asm-ia64/ptrace.h
@@ -2,8 +2,8 @@
 #define _ASM_IA64_PTRACE_H
 
 /*
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1998, 1999 Stephane Eranian <eranian@hpl.hp.com>
  *
  * 12/07/98	S. Eranian	added pt_regs & switch_stack
@@ -74,6 +74,9 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/current.h>
+#include <asm/page.h>
+
 /*
  * This struct defines the way the registers are saved on system
  * calls.
@@ -236,7 +239,14 @@ struct switch_stack {
 
   extern void ia64_increment_ip (struct pt_regs *pt);
   extern void ia64_decrement_ip (struct pt_regs *pt);
-#endif
+
+static inline void
+force_successful_syscall_return (void)
+{
+	ia64_task_regs(current)->r8 = 0;
+}
+
+#endif /* !__KERNEL__ */
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
index 9f02ac571..bcacf50ae 100644
--- a/include/asm-ia64/sal.h
+++ b/include/asm-ia64/sal.h
@@ -24,7 +24,9 @@
 
 extern spinlock_t sal_lock;
 
-#define __SAL_CALL(result,args...)	result = (*ia64_sal)(args)
+/* SAL spec _requires_ eight args for each call. */
+#define __SAL_CALL(result,a0,a1,a2,a3,a4,a5,a6,a7)	\
+	result = (*ia64_sal)(a0,a1,a2,a3,a4,a5,a6,a7)
 
 #ifdef CONFIG_SMP
 # define SAL_CALL(result,args...) do {		\
@@ -60,10 +62,10 @@ struct ia64_sal_retval {
 	 * informational value should be printed (e.g., "reboot for
 	 * change to take effect").
 	 */
-	s64 	status;
-	u64 	v0;
-	u64 	v1;
-	u64 	v2;
+	s64 status;
+	u64 v0;
+	u64 v1;
+	u64 v2;
 };
 
 typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
@@ -78,24 +80,27 @@ enum {
  * The SAL system table is followed by a variable number of variable
  * length descriptors.  The structure of these descriptors follows
  * below.
+ * The defininition follows SAL specs from July 2000
  */
 struct ia64_sal_systab {
-	char signature[4];	/* should be "SST_" */
-	int size;		/* size of this table in bytes */
-	unsigned char sal_rev_minor;
-	unsigned char sal_rev_major;
-	unsigned short entry_count;	/* # of entries in variable portion */
-	unsigned char checksum;
-	char ia32_bios_present;
-	unsigned short reserved1;
-	char oem_id[32];	/* ASCII NUL terminated OEM id
-				   (terminating NUL is missing if
-				   string is exactly 32 bytes long). */
-	char product_id[32];	/* ASCII product id  */
-	char reserved2[16];
+	u8 signature[4];	/* should be "SST_" */
+	u32 size;		/* size of this table in bytes */
+	u8 sal_rev_minor;
+	u8 sal_rev_major;
+	u16 entry_count;	/* # of entries in variable portion */
+	u8 checksum;
+	u8 reserved1[7];
+	u8 sal_a_rev_minor;
+	u8 sal_a_rev_major;
+	u8 sal_b_rev_minor;
+	u8 sal_b_rev_major;
+	/* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
+	u8 oem_id[32];
+	u8 product_id[32];	/* ASCII product id  */
+	u8 reserved2[8];
 };
 
-enum SAL_Systab_Entry_Type {
+enum sal_systab_entry_type {
 	SAL_DESC_ENTRY_POINT = 0,
 	SAL_DESC_MEMORY = 1,
 	SAL_DESC_PLATFORM_FEATURE = 2,
@@ -115,75 +120,78 @@ enum SAL_Systab_Entry_Type {
  */
 #define SAL_DESC_SIZE(type)	"\060\040\020\040\020\020"[(unsigned) type]
 
-struct ia64_sal_desc_entry_point {
-	char type;
-	char reserved1[7];
-	s64 pal_proc;
-	s64 sal_proc;
-	s64 gp;
-	char reserved2[16];
-};
-
-struct ia64_sal_desc_memory {
-	char type;
-	char used_by_sal;	/* needs to be mapped for SAL? */
-	char mem_attr;		/* current memory attribute setting */
-	char access_rights;	/* access rights set up by SAL */
-	char mem_attr_mask;	/* mask of supported memory attributes */
-	char reserved1;
-	char mem_type;		/* memory type */
-	char mem_usage;		/* memory usage */
-	s64 addr;		/* physical address of memory */
-	unsigned int length;	/* length (multiple of 4KB pages) */
-	unsigned int reserved2;
-	char oem_reserved[8];
-};
+typedef struct ia64_sal_desc_entry_point {
+	u8 type;
+	u8 reserved1[7];
+	u64 pal_proc;
+	u64 sal_proc;
+	u64 gp;
+	u8 reserved2[16];
+}ia64_sal_desc_entry_point_t;
+
+typedef struct ia64_sal_desc_memory {
+	u8 type;
+	u8 used_by_sal;	/* needs to be mapped for SAL? */
+	u8 mem_attr;		/* current memory attribute setting */
+	u8 access_rights;	/* access rights set up by SAL */
+	u8 mem_attr_mask;	/* mask of supported memory attributes */
+	u8 reserved1;
+	u8 mem_type;		/* memory type */
+	u8 mem_usage;		/* memory usage */
+	u64 addr;		/* physical address of memory */
+	u32 length;	/* length (multiple of 4KB pages) */
+	u32 reserved2;
+	u8 oem_reserved[8];
+} ia64_sal_desc_memory_t;
 
 #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK		(1 << 0)
 #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT	(1 << 1)
 #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT	(1 << 2)
 
-struct ia64_sal_desc_platform_feature {
-	char type;
-	unsigned char feature_mask;
-	char reserved1[14];
-};
-
-struct ia64_sal_desc_tr {
-	char type;
-	char tr_type;		/* 0 == instruction, 1 == data */
-	char regnum;		/* translation register number */
-	char reserved1[5];
-	s64 addr;		/* virtual address of area covered */
-	s64 page_size;		/* encoded page size */
-	char reserved2[8];
-};
+typedef struct ia64_sal_desc_platform_feature {
+	u8 type;
+	u8 feature_mask;
+	u8 reserved1[14];
+} ia64_sal_desc_platform_feature_t;
+
+typedef struct ia64_sal_desc_tr {
+	u8 type;
+	u8 tr_type;		/* 0 == instruction, 1 == data */
+	u8 regnum;		/* translation register number */
+	u8 reserved1[5];
+	u64 addr;		/* virtual address of area covered */
+	u64 page_size;		/* encoded page size */
+	u8 reserved2[8];
+} ia64_sal_desc_tr_t;
 
 typedef struct ia64_sal_desc_ptc {
-	char type;
-	char reserved1[3];
-	unsigned int num_domains;	/* # of coherence domains */
-	s64  domain_info;		/* physical address of domain info table */
+	u8 type;
+	u8 reserved1[3];
+	u32 num_domains;	/* # of coherence domains */
+	u64 domain_info;	/* physical address of domain info table */
 } ia64_sal_desc_ptc_t;
 
 typedef struct ia64_sal_ptc_domain_info {
-	unsigned long proc_count;	/* number of processors in domain */
-	long proc_list;			/* physical address of LID array */
+	u64 proc_count;		/* number of processors in domain */
+	u64 proc_list;		/* physical address of LID array */
 } ia64_sal_ptc_domain_info_t;
 
 typedef struct ia64_sal_ptc_domain_proc_entry {
-	unsigned char id;		/* id of processor */
-	unsigned char eid;		/* eid of processor */
+	u64 reserved : 16;
+	u64 eid : 8;		/* eid of processor */
+	u64 id  : 8;		/* id of processor */
+	u64 ignored : 32;
 } ia64_sal_ptc_domain_proc_entry_t;
 
+
 #define IA64_SAL_AP_EXTERNAL_INT 0
 
-struct ia64_sal_desc_ap_wakeup {
-	char type;
-	char mechanism;		/* 0 == external interrupt */
-	char reserved1[6];
-	long vector;		/* interrupt vector in range 0x10-0xff */
-};
+typedef struct ia64_sal_desc_ap_wakeup {
+	u8 type;
+	u8 mechanism;		/* 0 == external interrupt */
+	u8 reserved1[6];
+	u64 vector;		/* interrupt vector in range 0x10-0xff */
+} ia64_sal_desc_ap_wakeup_t ;
 
 extern ia64_sal_handler ia64_sal;
 extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
@@ -218,24 +226,24 @@ enum {
 
 /* Encodings for vectors which can be registered by the OS with SAL */
 enum {
-	SAL_VECTOR_OS_MCA		=	0,
-	SAL_VECTOR_OS_INIT		=	1,
-	SAL_VECTOR_OS_BOOT_RENDEZ	=	2
+	SAL_VECTOR_OS_MCA		= 0,
+	SAL_VECTOR_OS_INIT		= 1,
+	SAL_VECTOR_OS_BOOT_RENDEZ	= 2
 };
 
 /* Definition of the SAL Error Log from the SAL spec */
 
 /* Definition of timestamp according to SAL spec for logging purposes */
 
-typedef struct sal_log_timestamp_s {
-	u8	slh_century;				/* Century (19, 20, 21, ...) */
-	u8	slh_year;				/* Year (00..99) */
-	u8	slh_month;				/* Month (1..12) */
-	u8	slh_day;				/* Day (1..31) */
-	u8	slh_reserved;					
-	u8	slh_hour;				/* Hour (0..23)	*/
-	u8	slh_minute;				/* Minute (0..59) */
-	u8	slh_second;				/* Second (0..59) */
+typedef struct sal_log_timestamp {
+	u8 slh_century;		/* Century (19, 20, 21, ...) */
+	u8 slh_year;		/* Year (00..99) */
+	u8 slh_month;		/* Month (1..12) */
+	u8 slh_day;		/* Day (1..31) */
+	u8 slh_reserved;					
+	u8 slh_hour;		/* Hour (0..23)	*/
+	u8 slh_minute;		/* Minute (0..59) */
+	u8 slh_second;		/* Second (0..59) */
 } sal_log_timestamp_t;
 
 
@@ -243,126 +251,126 @@ typedef struct sal_log_timestamp_s {
 #define MAX_TLB_ERRORS				6
 #define MAX_BUS_ERRORS				1
 
-typedef struct sal_log_processor_info_s {
+typedef struct sal_log_processor_info {
 	struct	{
-		u64		slpi_psi	: 1,
-				slpi_cache_check: MAX_CACHE_ERRORS,
-				slpi_tlb_check	: MAX_TLB_ERRORS,
-				slpi_bus_check	: MAX_BUS_ERRORS,
-				slpi_reserved2	: (31 - (MAX_TLB_ERRORS + MAX_CACHE_ERRORS
-							 + MAX_BUS_ERRORS)),
-				slpi_minstate	: 1,
-				slpi_bank1_gr	: 1,
-				slpi_br		: 1,
-				slpi_cr		: 1,
-				slpi_ar		: 1,
-				slpi_rr		: 1,
-				slpi_fr		: 1,
-				slpi_reserved1	: 25;
+		u64 slpi_psi		: 1,
+		    slpi_cache_check: MAX_CACHE_ERRORS,
+		    slpi_tlb_check	: MAX_TLB_ERRORS,
+		    slpi_bus_check	: MAX_BUS_ERRORS,
+		    slpi_reserved2	: (31 - (MAX_TLB_ERRORS + MAX_CACHE_ERRORS
+		    			 + MAX_BUS_ERRORS)),
+		    slpi_minstate	: 1,
+		    slpi_bank1_gr	: 1,
+		    slpi_br		: 1,
+		    slpi_cr		: 1,
+		    slpi_ar		: 1,
+		    slpi_rr		: 1,
+		    slpi_fr		: 1,
+		    slpi_reserved1	: 25;
 	} slpi_valid;
 
-	pal_processor_state_info_t	slpi_processor_state_info;
+	pal_processor_state_info_t slpi_processor_state_info;
 
 	struct {
-		pal_cache_check_info_t	slpi_cache_check;
-		u64			slpi_target_address;
+		pal_cache_check_info_t slpi_cache_check;
+		u64 slpi_target_address;
 	} slpi_cache_check_info[MAX_CACHE_ERRORS];
 		
-	pal_tlb_check_info_t		slpi_tlb_check_info[MAX_TLB_ERRORS];
+	pal_tlb_check_info_t slpi_tlb_check_info[MAX_TLB_ERRORS];
 
 	struct {
-		pal_bus_check_info_t	slpi_bus_check;
-		u64			slpi_requestor_addr;	
-		u64			slpi_responder_addr;	
-		u64			slpi_target_addr;
+		pal_bus_check_info_t slpi_bus_check;
+		u64 slpi_requestor_addr;	
+		u64 slpi_responder_addr;	
+		u64 slpi_target_addr;
 	} slpi_bus_check_info[MAX_BUS_ERRORS];
 
-	pal_min_state_area_t		slpi_min_state_area;
-	u64				slpi_br[8];
-	u64				slpi_cr[128];
-	u64				slpi_ar[128];
-	u64				slpi_rr[8];
-	u64				slpi_fr[128];
+	pal_min_state_area_t slpi_min_state_area;
+	u64 slpi_br[8];
+	u64 slpi_cr[128];
+	u64 slpi_ar[128];
+	u64 slpi_rr[8];
+	u64 slpi_fr[128];
 } sal_log_processor_info_t;
 
 /* platform error log structures */
 typedef struct platerr_logheader {
-	u64	nextlog;	/* next log offset if present */
-	u64	loglength;	/* log length */
-	u64	logsubtype;	/* log subtype memory/bus/component */
-	u64	eseverity;	/* error severity */
+	u64 nextlog;		/* next log offset if present */
+	u64 loglength;		/* log length */
+	u64 logsubtype;		/* log subtype memory/bus/component */
+	u64 eseverity;		/* error severity */
 } ehdr_t;
 
 typedef struct sysmem_errlog {
-	ehdr_t	lhdr;		/* header */
-	u64	vflag;		/* valid bits for each field in the log */
-	u64	addr;		/* memory address */
-	u64	data;		/* memory data */
-	u64	cmd;		/* command bus value if any */
-	u64	ctrl;		/* control bus value if any */
-	u64	addrsyndrome;	/* memory address ecc/parity syndrome bits */
-	u64	datasyndrome;	/* data ecc/parity syndrome */
-	u64	cacheinfo;	/* platform cache info as defined in pal spec. table 7-34 */
+	ehdr_t lhdr;		/* header */
+	u64 vflag;		/* valid bits for each field in the log */
+	u64 addr;		/* memory address */
+	u64 data;		/* memory data */
+	u64 cmd;		/* command bus value if any */
+	u64 ctrl;		/* control bus value if any */
+	u64 addrsyndrome;	/* memory address ecc/parity syndrome bits */
+	u64 datasyndrome;	/* data ecc/parity syndrome */
+	u64 cacheinfo;		/* platform cache info as defined in pal spec. table 7-34 */
 } merrlog_t;
 
 typedef struct sysbus_errlog {
-	ehdr_t	lhdr;		/* linkded list header */
-	u64	vflag;		/* valid bits for each field in the log */
-	u64	busnum;		/* bus number in error */
-	u64	reqaddr;	/* requestor address */
-	u64	resaddr;	/* responder address */
-	u64	taraddr;	/* target address */
-	u64	data;		/* requester r/w data */
-	u64	cmd;		/* bus commands */
-	u64	ctrl;		/* bus controls (be# &-0) */
-	u64	addrsyndrome;	/* addr bus ecc/parity bits */
-	u64	datasyndrome;	/* data bus ecc/parity bits */
-	u64	cmdsyndrome;	/* command bus ecc/parity bits */
-	u64	ctrlsyndrome;	/* control bus ecc/parity bits */
+	ehdr_t lhdr;		/* linkded list header */
+	u64 vflag;		/* valid bits for each field in the log */
+	u64 busnum;		/* bus number in error */
+	u64 reqaddr;		/* requestor address */
+	u64 resaddr;		/* responder address */
+	u64 taraddr;		/* target address */
+	u64 data;		/* requester r/w data */
+	u64 cmd;		/* bus commands */
+	u64 ctrl;		/* bus controls (be# &-0) */
+	u64 addrsyndrome;	/* addr bus ecc/parity bits */
+	u64 datasyndrome;	/* data bus ecc/parity bits */
+	u64 cmdsyndrome;	/* command bus ecc/parity bits */
+	u64 ctrlsyndrome;	/* control bus ecc/parity bits */
 } berrlog_t;
 
 /* platform error log structures */
 typedef struct syserr_chdr {	/* one header per component */
-	u64	busnum;		/* bus number on which the component resides */
-	u64	devnum;		/* same as device select */
-	u64	funcid;		/* function id of the device */
-	u64	devid;		/* pci device id */
-	u64	classcode;	/* pci class code for the device */
-	u64	cmdreg;		/* pci command reg value */
-	u64	statreg;	/* pci status reg value */
+	u64 busnum;		/* bus number on which the component resides */
+	u64 devnum;		/* same as device select */
+	u64 funcid;		/* function id of the device */
+	u64 devid;		/* pci device id */
+	u64 classcode;		/* pci class code for the device */
+	u64 cmdreg;		/* pci command reg value */
+	u64 statreg;		/* pci status reg value */
 } chdr_t;
 
 typedef struct cfginfo {
-	u64	cfgaddr;
-	u64	cfgval;
+	u64 cfgaddr;
+	u64 cfgval;
 } cfginfo_t;
 
 typedef struct sys_comperr {	/* per component */
-	ehdr_t	lhdr;		/* linked list header */
-	u64	vflag;		/* valid bits for each field in the log */
-	chdr_t	scomphdr;	
-	u64	numregpair;	/* number of reg addr/value pairs */
+	ehdr_t lhdr;		/* linked list header */
+	u64 vflag;		/* valid bits for each field in the log */
+	chdr_t scomphdr;	
+	u64 numregpair;		/* number of reg addr/value pairs */
 	cfginfo_t cfginfo;
 } cerrlog_t;
 
 typedef struct sel_records {
-	ehdr_t	lhdr;
-	u64	seldata;
+	ehdr_t lhdr;
+	u64 seldata;
 } isel_t;
 
 typedef struct plat_errlog {
-	u64	      mbcsvalid;	/* valid bits for each type of log */
-	merrlog_t     smemerrlog;	/* platform memory error logs */
-	berrlog_t     sbuserrlog;	/* platform bus error logs */
-	cerrlog_t     scomperrlog;	/* platform chipset error logs */
-	isel_t	      selrecord;	/* ipmi sel record */
+	u64 mbcsvalid;		/* valid bits for each type of log */
+	merrlog_t smemerrlog;	/* platform memory error logs */
+	berrlog_t sbuserrlog;	/* platform bus error logs */
+	cerrlog_t scomperrlog;	/* platform chipset error logs */
+	isel_t selrecord;	/* ipmi sel record */
 } platforminfo_t;
 
 /* over all log structure (processor+platform) */
 
 typedef union udev_specific_log {
-	sal_log_processor_info_t  proclog;
-	platforminfo_t		  platlog;
+	sal_log_processor_info_t proclog;
+	platforminfo_t platlog;
 } devicelog_t;
 
 
@@ -378,21 +386,18 @@ typedef union udev_specific_log {
 #define sal_log_processor_info_rr_valid			slpi_valid.slpi_rr
 #define sal_log_processor_info_fr_valid			slpi_valid.slpi_fr
 
-typedef struct sal_log_header_s {
-	u64			slh_next_log;		/* Offset of the next log from the 
-							 * beginning of  this structure.
-							 */
-	uint			slh_log_len;		/* Length of this error log in bytes */
-	ushort			slh_log_type;		/* Type of log (0 - cpu ,1 - platform) */
-	ushort			slh_log_sub_type;	/* SGI specific sub type */
-	sal_log_timestamp_t	slh_log_timestamp;	/* Timestamp */
+typedef struct sal_log_header {
+	u64 slh_next_log;	/* Offset of the next log from the beginning of this structure */
+	u32 slh_log_len;	/* Length of this error log in bytes */
+	u16 slh_log_type;	/* Type of log (0 - cpu ,1 - platform) */
+	u16 slh_log_sub_type;	/* SGI specific sub type */
+	sal_log_timestamp_t slh_log_timestamp;	/* Timestamp */
 } sal_log_header_t;
 
 /* SAL PSI log structure */
-typedef struct psilog
-{
-	sal_log_header_t   sal_elog_header;
-	devicelog_t        devlog;
+typedef struct psilog {
+	sal_log_header_t sal_elog_header;
+	devicelog_t devlog;
 } ia64_psilog_t;
 
 /*
@@ -405,7 +410,7 @@ ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
 {
 	struct ia64_sal_retval isrv;
 
-	SAL_CALL(isrv, SAL_FREQ_BASE, which);
+	SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0);
 	*ticks_per_second = isrv.v0;
 	*drift_info = isrv.v1;
 	return isrv.status;
@@ -416,7 +421,7 @@ static inline s64
 ia64_sal_cache_flush (u64 cache_type)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type);
+	SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
 	return isrv.status;
 }
 
@@ -427,7 +432,7 @@ static inline s64
 ia64_sal_cache_init (void)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_CACHE_INIT);
+	SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
 	return isrv.status;
 }
 
@@ -438,7 +443,8 @@ static inline s64
 ia64_sal_clear_state_info (u64 sal_info_type, u64 sal_info_sub_type)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, sal_info_sub_type);
+	SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, sal_info_sub_type,
+	         0, 0, 0, 0, 0);
 	return isrv.status;
 }
 
@@ -450,7 +456,8 @@ static inline u64
 ia64_sal_get_state_info (u64 sal_info_type, u64 sal_info_sub_type, u64 *sal_info)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_GET_STATE_INFO, sal_info_type, sal_info_sub_type, sal_info);
+	SAL_CALL(isrv, SAL_GET_STATE_INFO, sal_info_type, sal_info_sub_type,
+	         sal_info, 0, 0, 0, 0);
 	if (isrv.status)
 		return 0;
 	return isrv.v0;
@@ -462,7 +469,8 @@ static inline u64
 ia64_sal_get_state_info_size (u64 sal_info_type, u64 sal_info_sub_type)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, sal_info_sub_type);
+	SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, sal_info_sub_type,
+	         0, 0, 0, 0, 0);
 	if (isrv.status)
 		return 0;
 	return isrv.v0;
@@ -475,7 +483,7 @@ static inline s64
 ia64_sal_mc_rendez (void)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_MC_RENDEZ);
+	SAL_CALL(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
 	return isrv.status;
 }
 
@@ -487,7 +495,8 @@ static inline s64
 ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, timeout);
+	SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, timeout,
+	         0, 0, 0);
 	return isrv.status;
 }
 
@@ -496,19 +505,7 @@ static inline s64
 ia64_sal_pci_config_read (u64 pci_config_addr, u64 size, u64 *value)
 {
 	struct ia64_sal_retval isrv;
-#ifdef CONFIG_ITANIUM_A1_SPECIFIC
-	extern spinlock_t ivr_read_lock;
-	unsigned long flags;
-
-	/*
-	 * Avoid PCI configuration read/write overwrite -- A0 Interrupt loss workaround
-	 */
-	spin_lock_irqsave(&ivr_read_lock, flags);
-#endif
-	SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size);
-#ifdef CONFIG_ITANIUM_A1_SPECIFIC
-	spin_unlock_irqrestore(&ivr_read_lock, flags);
-#endif
+	SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, 0, 0, 0, 0, 0);
 	if (value)
 		*value = isrv.v0;
 	return isrv.status;
@@ -519,19 +516,8 @@ static inline s64
 ia64_sal_pci_config_write (u64 pci_config_addr, u64 size, u64 value)
 {
 	struct ia64_sal_retval isrv;
-#ifdef CONFIG_ITANIUM_A1_SPECIFIC
-	extern spinlock_t ivr_read_lock;
-	unsigned long flags;
-
-	/*
-	 * Avoid PCI configuration read/write overwrite -- A0 Interrupt loss workaround
-	 */
-	spin_lock_irqsave(&ivr_read_lock, flags);
-#endif
-	SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value);
-#ifdef CONFIG_ITANIUM_A1_SPECIFIC
-	spin_unlock_irqrestore(&ivr_read_lock, flags);
-#endif
+	SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
+	         0, 0, 0, 0);
 	return isrv.status;
 }
 
@@ -543,7 +529,8 @@ static inline s64
 ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr);
+	SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
+	         0, 0, 0, 0, 0);
 	return isrv.status;
 }
 
@@ -569,7 +556,8 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
 		     u64 *error_code, u64 *scratch_buf_size_needed)
 {
 	struct ia64_sal_retval isrv;
-	SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size);
+	SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
+	         0, 0, 0, 0);
 	if (error_code)
 		*error_code = isrv.v0;
 	if (scratch_buf_size_needed)
diff --git a/include/asm-ia64/shmparam.h b/include/asm-ia64/shmparam.h
index 5bbea62b5..d07508dc5 100644
--- a/include/asm-ia64/shmparam.h
+++ b/include/asm-ia64/shmparam.h
@@ -1,6 +1,12 @@
 #ifndef _ASM_IA64_SHMPARAM_H
 #define _ASM_IA64_SHMPARAM_H
 
-#define	SHMLBA	PAGE_SIZE		/* attach addr a multiple of this */
+/*
+ * SHMLBA controls minimum alignment at which shared memory segments
+ * get attached.  The IA-64 architecture says that there may be a
+ * performance degradation when there are virtual aliases within 1MB.
+ * To reduce the chance of this, we set SHMLBA to 1MB. --davidm 00/12/20
+ */
+#define	SHMLBA	(1024*1024)
 
 #endif /* _ASM_IA64_SHMPARAM_H */
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
new file mode 100644
index 000000000..0d2c98245
--- /dev/null
+++ b/include/asm-ia64/sn/addrs.h
@@ -0,0 +1,546 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_ADDRS_H
+#define _ASM_SN_ADDRS_H
+
+#include <linux/config.h>
+#if _LANGUAGE_C
+#include <linux/types.h>
+#endif /* _LANGUAGE_C */
+
+#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
+#include <asm/addrspace.h>
+#include <asm/reg.h>
+#include <asm/sn/kldir.h>
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+#if defined(CONFIG_IA64_SGI_IO)
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/addrs.h>
+#endif
+#endif	/* CONFIG_IA64_SGI_IO */
+
+
+#if _LANGUAGE_C
+
+#if defined(CONFIG_IA64_SGI_IO)	/* FIXME */
+#define PS_UINT_CAST		(__psunsigned_t)
+#define UINT64_CAST		(uint64_t)
+#else	/* CONFIG_IA64_SGI_IO */
+#define PS_UINT_CAST		(unsigned long)
+#define UINT64_CAST		(unsigned long)
+#endif	/* CONFIG_IA64_SGI_IO */
+
+#define HUBREG_CAST		(volatile hubreg_t *)
+
+#elif _LANGUAGE_ASSEMBLY
+
+#define PS_UINT_CAST
+#define UINT64_CAST
+#define HUBREG_CAST
+
+#endif
+
+
+#define NASID_GET_META(_n)	((_n) >> NASID_LOCAL_BITS)
+#if defined CONFIG_SGI_IP35 || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define NASID_GET_LOCAL(_n)	((_n) & 0x7f)
+#endif
+#define NASID_MAKE(_m, _l)	(((_m) << NASID_LOCAL_BITS) | (_l))
+
+#define NODE_ADDRSPACE_MASK	(NODE_ADDRSPACE_SIZE - 1)
+#define TO_NODE_ADDRSPACE(_pa)	(UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
+
+#define CHANGE_ADDR_NASID(_pa, _nasid)	\
+		((UINT64_CAST (_pa) & ~NASID_MASK) | \
+		 (UINT64_CAST(_nasid) <<  NASID_SHFT))
+
+
+/*
+ * The following macros are used to index to the beginning of a specific
+ * node's address space.
+ */
+
+#define NODE_OFFSET(_n)		(UINT64_CAST (_n) << NODE_SIZE_BITS)
+
+#define NODE_CAC_BASE(_n)	(CAC_BASE   + NODE_OFFSET(_n))
+#define NODE_HSPEC_BASE(_n)	(HSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_IO_BASE(_n)	(IO_BASE    + NODE_OFFSET(_n))
+#define NODE_MSPEC_BASE(_n)	(MSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_UNCAC_BASE(_n)	(UNCAC_BASE + NODE_OFFSET(_n))
+
+#define TO_NODE(_n, _x)		(NODE_OFFSET(_n)     | ((_x)		   ))
+#define TO_NODE_CAC(_n, _x)	(NODE_CAC_BASE(_n)   | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_UNCAC(_n, _x)	(NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_MSPEC(_n, _x)	(NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_HSPEC(_n, _x)	(NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+
+
+#define RAW_NODE_SWIN_BASE(nasid, widget)				\
+	(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+
+#define WIDGETID_GET(addr)	((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS		24
+#define SWIN_SIZE		(UINT64_CAST 1 << 24)
+#define	SWIN_SIZEMASK		(SWIN_SIZE - 1)
+#define	SWIN_WIDGET_MASK	0xF
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define	SWIN_WIDGETADDR(addr)	((addr) & SWIN_SIZEMASK)
+#define	SWIN_WIDGETNUM(addr)	(((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to small window address on node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+#define	NODE_SWIN_ADDR(nasid, addr)	\
+		(((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
+		 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
+		 ))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN.
+ *	UALIAS -- 256MB in size, reads in the UALIAS result in
+ *			uncached references to the memory of the reader's node.
+ *	CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
+ *			depending on which CPU does the access to provide
+ *			all CPUs with unique uncached memory at low addresses.
+ *	LBOOT  -- 256MB in size, reads in the LBOOT area result in
+ *			uncached references to the local hub's boot prom and
+ *			other directory-bus connected devices.
+ *	IALIAS -- 8MB in size, reads in the IALIAS result in uncached
+ *			references to the local hub's registers.
+ */
+
+#define UALIAS_BASE		HSPEC_BASE
+#define UALIAS_SIZE		0x10000000	/* 256 Megabytes */
+#define UALIAS_LIMIT		(UALIAS_BASE + UALIAS_SIZE)
+
+/*
+ * The bottom of ualias space is flipped depending on whether you're
+ * processor 0 or 1 within a node.
+ */
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define LREG_BASE		(HSPEC_BASE + 0x10000000)
+#define LREG_SIZE		0x8000000  /* 128 MB */
+#define LREG_LIMIT		(LREG_BASE + LREG_SIZE)
+#define LBOOT_BASE		(LREG_LIMIT)
+#define LBOOT_SIZE		0x8000000   /* 128 MB */
+#define LBOOT_LIMIT		(LBOOT_BASE + LBOOT_SIZE)
+#define LBOOT_STRIDE		0x2000000    /* two PROMs, on 32M boundaries */
+#endif
+
+#define	HUB_REGISTER_WIDGET	1
+#define IALIAS_BASE		NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
+#define IALIAS_SIZE		0x800000	/* 8 Megabytes */
+#define IS_IALIAS(_a)		(((_a) >= IALIAS_BASE) &&		\
+				 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
+
+/*
+ * Macro for referring to Hub's RBOOT space
+ */
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+
+#define NODE_LREG_BASE(_n)	(NODE_HSPEC_BASE(_n) + 0x30000000)
+#define NODE_LREG_LIMIT(_n)	(NODE_LREG_BASE(_n) + LREG_SIZE)
+#define RREG_BASE(_n)		(NODE_LREG_BASE(_n))
+#define RREG_LIMIT(_n)		(NODE_LREG_LIMIT(_n))
+#define RBOOT_SIZE		0x8000000	/* 128 Megabytes */
+#define NODE_RBOOT_BASE(_n)	(NODE_HSPEC_BASE(_n) + 0x38000000)
+#define NODE_RBOOT_LIMIT(_n)	(NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
+
+#endif
+
+/*
+ * Macros for referring the Hub's back door space
+ *
+ *   These macros correctly process addresses in any node's space.
+ *   WARNING: They won't work in assembler.
+ *
+ *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
+ *                  entry corresponding to a physical (Cac or Uncac) address.
+ *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
+ *   BDPRT_ENTRY    returns the address of the double-word protection entry
+ *                  corresponding to the page containing the physical address.
+ *   BDPRT_ENTRY_S  Stores the value into the protection entry.
+ *   BDPRT_ENTRY_L  Load the value from the protection entry.
+ *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
+ *                  double-word at a specified physical address.
+ *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
+ *                  quad-word at a specified physical address.
+ */
+#define NODE_BDOOR_BASE(_n)	(NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
+
+#define NODE_BDECC_BASE(_n)	(NODE_BDOOR_BASE(_n))
+#define NODE_BDDIR_BASE(_n)	(NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+/*
+ * Bedrock's directory entries are a single word:  no low/high
+ */
+
+#define BDDIR_ENTRY(_pa)	(HSPEC_BASE +				      \
+				  NODE_ADDRSPACE_SIZE * 7 / 8  		    | \
+				 UINT64_CAST (_pa)	& NASID_MASK	    | \
+				 UINT64_CAST (_pa) >> 3 & BDDIR_UPPER_MASK)
+
+#ifdef BRINGUP
+        /* minimize source changes by mapping *_LO() & *_HI()   */
+#define BDDIR_ENTRY_LO(_pa)     BDDIR_ENTRY(_pa)
+#define BDDIR_ENTRY_HI(_pa)     BDDIR_ENTRY(_pa)
+#endif /* BRINGUP */
+
+#define BDDIR_PAGE_MASK		(BDDIR_UPPER_MASK & 0x7ffff << 11)
+#define BDDIR_PAGE_BASE_MASK	(UINT64_CAST 0xfffffffffffff800)
+
+#ifdef _LANGUAGE_C
+
+#define BDPRT_ENTRY_ADDR(_pa, _rgn)      ((uint64_t *) ( (HSPEC_BASE +       \
+                                 NODE_ADDRSPACE_SIZE * 7 / 8 + 0x408)       | \
+                                (UINT64_CAST (_pa)      & NASID_MASK)        | \
+                                (UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK)   | \
+                                (UINT64_CAST (_pa) >> 3 & 0x3 << 4)          | \
+                                ((_rgn) & 0x1e) << 5))
+
+static __inline uint64_t BDPRT_ENTRY_L(paddr_t pa,uint32_t rgn) {
+	uint64_t word=*BDPRT_ENTRY_ADDR(pa,rgn);
+
+	if(rgn&0x20)			/*If the region is > 32, move it down*/
+		word = word >> 32;
+	if(rgn&0x1)			/*If the region is odd, get that part */
+		word = word >> 16;
+	word = word & 0xffff;		/*Get the 16 bits we are interested in*/
+
+	return word;
+}
+
+static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) {
+        uint64_t *addr=(uint64_t *)BDPRT_ENTRY_ADDR(pa,rgn);
+        uint64_t word,mask;
+
+        word=*addr;
+	mask=0;
+	if(rgn&0x1) {
+		mask|=0x0000ffff0000ffff;
+		val=val<<16;
+	}
+	else
+		mask|=0xffff0000ffff0000;
+	if(rgn&0x20) {
+		mask|=0x00000000ffffffff;
+		val=val<<32;
+	}
+	else
+		mask|=0xffffffff00000000;
+	word &= mask;
+	word |= val;
+
+	*(addr++)=word;
+	addr++;
+        *(addr++)=word;
+        addr++;
+        *(addr++)=word;
+        addr++;
+        *addr=word;
+}
+#endif	/*_LANGUAGE_C*/
+
+#define BDCNT_ENTRY(_pa)	(HSPEC_BASE +				      \
+				  NODE_ADDRSPACE_SIZE * 7 / 8 + 0x8    	    | \
+				 UINT64_CAST (_pa)	& NASID_MASK	    | \
+				 UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK   | \
+				 UINT64_CAST (_pa) >> 3 & 0x3 << 4)
+
+
+#ifdef    BRINGUP
+  /* little endian packing of ecc bytes requires a swizzle */ 
+  /* this is problemmatic for memory_init_ecc              */
+#endif /* BRINGUP */
+#define BDECC_ENTRY(_pa)	(HSPEC_BASE +				      \
+				  NODE_ADDRSPACE_SIZE * 5 / 8 		    | \
+				 UINT64_CAST (_pa)	& NASID_MASK	    | \
+				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
+				   		        ^ 0x7ULL)
+
+#define BDECC_SCRUB(_pa)	(HSPEC_BASE +				      \
+				  NODE_ADDRSPACE_SIZE / 2 		    | \
+				 UINT64_CAST (_pa)	& NASID_MASK	    | \
+				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
+				   		        ^ 0x7ULL)
+
+  /* address for Halfword backdoor ecc access. Note that   */
+  /* ecc bytes are packed in little endian order           */
+#define BDECC_ENTRY_H(_pa)	(HSPEC_BASE +                                 \
+				  NODE_ADDRSPACE_SIZE * 5 / 8		    | \
+				 UINT64_CAST (_pa)	 & NASID_MASK	    | \
+				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
+				   		        ^ 0x6ULL)
+
+/*
+ * Macro to convert a back door directory, protection, page counter, or ecc
+ * address into the raw physical address of the associated cache line
+ * or protection page.
+ */
+
+#define BDDIR_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK            | \
+				 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK) << 3)
+
+#ifdef BRINGUP
+/*
+ * This can't be done since there are 4 entries per address so you'd end up
+ * mapping back to 4 different physical addrs.
+ */
+  
+#define BDPRT_TO_MEM(_ba) 	(UINT64_CAST  (_ba) & NASID_MASK	    | \
+				 (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \
+				 (UINT64_CAST (_ba) & 0x3 << 4) << 3)
+#endif
+
+#define BDCNT_TO_MEM(_ba) 	(UINT64_CAST  (_ba) & NASID_MASK	    | \
+				 (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \
+				 (UINT64_CAST (_ba) & 0x3 << 4) << 3)
+
+#define BDECC_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK	    | \
+				 ((UINT64_CAST (_ba) ^ 0x7ULL)                \
+				                    & BDECC_UPPER_MASK) << 3 )
+
+#define BDECC_H_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK	    | \
+				 ((UINT64_CAST (_ba) ^ 0x6ULL)                \
+				                    & BDECC_UPPER_MASK) << 3 )
+
+#define BDADDR_IS_DIR(_ba)	((UINT64_CAST  (_ba) & 0x8) == 0)
+#define BDADDR_IS_PRT(_ba)	((UINT64_CAST  (_ba) & 0x408) == 0x408)
+#define BDADDR_IS_CNT(_ba)	((UINT64_CAST  (_ba) & 0x8) == 0x8)
+
+#endif /* CONFIG_SGI_IP35 */
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers.  The LOCAL_HUB_* macros produce the appropriate
+ * address for the local registers.  The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers.  The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for _x.
+ */
+
+/*
+ * WARNING:
+ *	When certain Hub chip workaround are defined, it's not sufficient
+ *	to dereference the *_HUB_ADDR() macros.  You should instead use
+ *	HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ *	They're always safe.
+ */
+#define LOCAL_HUB_ADDR(_x)	(HUBREG_CAST (IALIAS_BASE + (_x)))
+#define REMOTE_HUB_ADDR(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
+					      0x800000 + (_x)))
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define REMOTE_HUB_PI_ADDR(_n, _sn, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
+					      0x800000 + PIREG(_x, _sn)))
+#define LOCAL_HSPEC_ADDR(_x)		(HUBREG_CAST (LREG_BASE + (_x)))
+#define REMOTE_HSPEC_ADDR(_n, _x)	(HUBREG_CAST (RREG_BASE(_n) + (_x)))
+#endif /* CONFIG_SGI_IP35 */
+
+#if _LANGUAGE_C
+
+#define HUB_L(_a)			*(_a)
+#define	HUB_S(_a, _d)			*(_a) = (_d)
+
+#define LOCAL_HUB_L(_r)			HUB_L(LOCAL_HUB_ADDR(_r))
+#define LOCAL_HUB_S(_r, _d)		HUB_S(LOCAL_HUB_ADDR(_r), (_d))
+#define REMOTE_HUB_L(_n, _r)		HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
+#define REMOTE_HUB_S(_n, _r, _d)	HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
+#define REMOTE_HUB_PI_L(_n, _sn, _r)	HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
+#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define LOCAL_HSPEC_L(_r)	     HUB_L(LOCAL_HSPEC_ADDR(_r))
+#define LOCAL_HSPEC_S(_r, _d)	     HUB_S(LOCAL_HSPEC_ADDR(_r), (_d))
+#define REMOTE_HSPEC_L(_n, _r)	     HUB_L(REMOTE_HSPEC_ADDR((_n), (_r)))
+#define REMOTE_HSPEC_S(_n, _r, _d)   HUB_S(REMOTE_HSPEC_ADDR((_n), (_r)), (_d))
+#endif /* CONFIG_SGI_IP35 */
+
+#endif /* _LANGUAGE_C */
+
+/*
+ * The following macros are used to get to a hub/bridge register, given
+ * the base of the register space.
+ */
+#define HUB_REG_PTR(_base, _off)	\
+	(HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define HUB_REG_PTR_L(_base, _off)	\
+	HUB_L(HUB_REG_PTR((_base), (_off)))
+
+#define HUB_REG_PTR_S(_base, _off, _data)	\
+	HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
+
+/*
+ * Software structure locations -- permanently fixed
+ *    See diagram in kldir.h
+ */
+
+#define PHYS_RAMBASE		0x0
+#define K0_RAMBASE		PHYS_TO_K0(PHYS_RAMBASE)
+
+#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
+#define EX_HANDLER_ADDR(nasid, slice)					\
+	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
+#define EX_HANDLER_SIZE		0x0400
+
+#define EX_FRAME_OFFSET(slice)	((slice) << 16 | 0x400)
+#define EX_FRAME_ADDR(nasid, slice)					\
+	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
+#define EX_FRAME_SIZE		0x0c00
+
+#define ARCS_SPB_OFFSET		0x1000
+#define ARCS_SPB_ADDR(nasid)						\
+	PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
+#define ARCS_SPB_SIZE		0x0400
+
+#define KLDIR_OFFSET		0x2000
+#define KLDIR_ADDR(nasid)						\
+	TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
+#define KLDIR_SIZE		0x0400
+
+
+/*
+ * Software structure locations -- indirected through KLDIR
+ *    See diagram in kldir.h
+ *
+ * Important:	All low memory structures must only be accessed
+ *		uncached, except for the symmon stacks.
+ */
+
+#define KLI_LAUNCH		0		/* Dir. entries */
+#define KLI_KLCONFIG		1
+#define	KLI_NMI			2
+#define KLI_GDA			3
+#define KLI_FREEMEM		4
+#define	KLI_SYMMON_STK		5
+#define KLI_PI_ERROR		6
+#define KLI_KERN_VARS		7
+#define	KLI_KERN_XP		8
+#define	KLI_KERN_PARTID		9
+
+#if _LANGUAGE_C
+
+#define KLD_BASE(nasid)		((kldir_ent_t *) KLDIR_ADDR(nasid))
+#define KLD_LAUNCH(nasid)	(KLD_BASE(nasid) + KLI_LAUNCH)
+#define KLD_NMI(nasid)		(KLD_BASE(nasid) + KLI_NMI)
+#define KLD_KLCONFIG(nasid)	(KLD_BASE(nasid) + KLI_KLCONFIG)
+#define KLD_PI_ERROR(nasid)	(KLD_BASE(nasid) + KLI_PI_ERROR)
+#define KLD_GDA(nasid)		(KLD_BASE(nasid) + KLI_GDA)
+#define KLD_SYMMON_STK(nasid)	(KLD_BASE(nasid) + KLI_SYMMON_STK)
+#define KLD_FREEMEM(nasid)	(KLD_BASE(nasid) + KLI_FREEMEM)
+#define KLD_KERN_VARS(nasid)	(KLD_BASE(nasid) + KLI_KERN_VARS)
+#define	KLD_KERN_XP(nasid)	(KLD_BASE(nasid) + KLI_KERN_XP)
+#define	KLD_KERN_PARTID(nasid)	(KLD_BASE(nasid) + KLI_KERN_PARTID)
+
+#define LAUNCH_OFFSET(nasid, slice)					\
+	(KLD_LAUNCH(nasid)->offset +					\
+	 KLD_LAUNCH(nasid)->stride * (slice))
+#define LAUNCH_ADDR(nasid, slice)					\
+	TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
+#define LAUNCH_SIZE(nasid)	KLD_LAUNCH(nasid)->size
+
+#define NMI_OFFSET(nasid, slice)					\
+	(KLD_NMI(nasid)->offset +					\
+	 KLD_NMI(nasid)->stride * (slice))
+#define NMI_ADDR(nasid, slice)						\
+	TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
+#define NMI_SIZE(nasid)	KLD_NMI(nasid)->size
+
+#define KLCONFIG_OFFSET(nasid)	KLD_KLCONFIG(nasid)->offset
+#define KLCONFIG_ADDR(nasid)						\
+	TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
+#define KLCONFIG_SIZE(nasid)	KLD_KLCONFIG(nasid)->size
+
+#define GDA_ADDR(nasid)		KLD_GDA(nasid)->pointer
+#define GDA_SIZE(nasid)		KLD_GDA(nasid)->size
+
+#define SYMMON_STK_OFFSET(nasid, slice)					\
+	(KLD_SYMMON_STK(nasid)->offset +				\
+	 KLD_SYMMON_STK(nasid)->stride * (slice))
+#define SYMMON_STK_STRIDE(nasid)	KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_ADDR(nasid, slice)					\
+	TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
+
+#define SYMMON_STK_SIZE(nasid)	KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_END(nasid)	(SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
+
+/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
+ * relocatable program
+ */
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+/* update master.d/sn1_elspec.dbg, SN1/addrs.h/DEBUGUNIX_ADDR, and
+ * DBGLOADADDR in symmon's Makefile when changing this */
+#define UNIX_DEBUG_LOADADDR     0x310000
+#elif defined(SN0XXL)
+#define UNIX_DEBUG_LOADADDR     0x360000
+#else
+#define	UNIX_DEBUG_LOADADDR	0x300000
+#endif
+#define	SYMMON_LOADADDR(nasid)						\
+	TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
+
+#define FREEMEM_OFFSET(nasid)	KLD_FREEMEM(nasid)->offset
+#define FREEMEM_ADDR(nasid)	SYMMON_STK_END(nasid)
+/*
+ * XXX
+ * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
+ * Also, it should take into account what prom thinks to be a safe
+ * address
+	PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
+ */
+#define FREEMEM_SIZE(nasid)	KLD_FREEMEM(nasid)->size
+
+#define PI_ERROR_OFFSET(nasid)	KLD_PI_ERROR(nasid)->offset
+#define PI_ERROR_ADDR(nasid)						\
+	TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
+#define PI_ERROR_SIZE(nasid)	KLD_PI_ERROR(nasid)->size
+
+#define NODE_OFFSET_TO_K0(_nasid, _off)					\
+	(PAGE_OFFSET | NODE_OFFSET(_nasid) | (_off))
+#define K0_TO_NODE_OFFSET(_k0addr)					\
+	((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
+
+#define KERN_VARS_ADDR(nasid)	KLD_KERN_VARS(nasid)->pointer
+#define KERN_VARS_SIZE(nasid)	KLD_KERN_VARS(nasid)->size
+
+#define	KERN_XP_ADDR(nasid)	KLD_KERN_XP(nasid)->pointer
+#define	KERN_XP_SIZE(nasid)	KLD_KERN_XP(nasid)->size
+
+#define GPDA_ADDR(nasid)	TO_NODE_CAC(nasid, GPDA_OFFSET)
+
+#endif /* _LANGUAGE_C */
+
+
+#endif /* _ASM_SN_ADDRS_H */
diff --git a/include/asm-ia64/sn/agent.h b/include/asm-ia64/sn/agent.h
new file mode 100644
index 000000000..2e7117796
--- /dev/null
+++ b/include/asm-ia64/sn/agent.h
@@ -0,0 +1,46 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file has definitions for the hub and snac interfaces.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGI_SN_AGENT_H
+#define _ASM_SGI_SN_AGENT_H
+
+#include <linux/config.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+//#include <asm/sn/io.h>
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/bedrock.h>
+#endif	/* CONFIG_SGI_IP35 */
+
+/*
+ * NIC register macros
+ */
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define HUB_NIC_ADDR(_cpuid) 						   \
+	REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(_cpuid)),       \
+		LB_MICROLAN_CTL)
+#endif
+
+#define SET_HUB_NIC(_my_cpuid, _val) 				  	   \
+	(HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
+
+#define SET_MY_HUB_NIC(_v) 					           \
+	SET_HUB_NIC(cpuid(), (_v))
+
+#define GET_HUB_NIC(_my_cpuid) 						   \
+	(HUB_L(HUB_NIC_ADDR(_my_cpuid)))
+
+#define GET_MY_HUB_NIC() 						   \
+	GET_HUB_NIC(cpuid())
+
+#endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/include/asm-ia64/sn/alenlist.h b/include/asm-ia64/sn/alenlist.h
new file mode 100644
index 000000000..6e66e2711
--- /dev/null
+++ b/include/asm-ia64/sn/alenlist.h
@@ -0,0 +1,204 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_ALENLIST_H
+#define _ASM_SN_ALENLIST_H
+
+/* Definition of Address/Length List */
+
+/*
+ * An Address/Length List is used when setting up for an I/O DMA operation.
+ * A driver creates an Address/Length List that describes to the the DMA 
+ * interface where in memory the DMA should go.  The bus interface sets up 
+ * mapping registers, if required, and returns a suitable list of "physical 
+ * addresses" or "I/O address" to the driver.  The driver then uses these 
+ * to set up an appropriate scatter/gather operation(s).
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * An Address/Length List Address.  It'll get cast to the appropriate type,
+ * and must be big enough to hold the largest possible address in any
+ * supported address space.
+ */
+typedef u64 alenaddr_t;
+typedef u64 uvaddr_t;
+
+typedef struct alenlist_s *alenlist_t;
+
+/* 
+ * For tracking progress as we walk down an address/length list.
+ */
+typedef struct alenlist_cursor_s *alenlist_cursor_t;
+
+/*
+ * alenlist representation that can be passed via an idl
+ */
+struct external_alenlist {
+	alenaddr_t	addr;
+	size_t		len;
+};
+typedef struct external_alenlist *external_alenlist_t;
+
+
+/* Return codes from alenlist routines.  */
+#define ALENLIST_FAILURE -1
+#define ALENLIST_SUCCESS 0
+
+
+/* Flags to alenlist routines */
+#define AL_NOSLEEP	0x01		/* Do not sleep, waiting for memory */
+#define AL_NOCOMPACT	0x02		/* Do not try to compact adjacent entries */
+#define AL_LEAVE_CURSOR	0x04		/* Do not update cursor */
+
+
+/* Create an Address/Length List, and clear it of all entries.  */
+extern alenlist_t alenlist_create(unsigned flags);
+
+/* Grow/shrink an Address/Length List and FIX its size. */
+extern int alenlist_grow(alenlist_t, size_t npairs);
+
+/* Clear an Address/Length List so that it now describes 0 pairs. */
+extern void alenlist_clear(alenlist_t alenlist);
+
+/*
+ * Convenience function to create an Address/Length List and then append 
+ * the specified Address/Length Pair.  Exactly the same as alenlist_create 
+ * followed by alenlist_append.  Can be used when a small list (e.g. 1 pair)
+ * is adequate.
+ */
+extern alenlist_t
+alenpair_init(	alenaddr_t address, 			/* init to this address */
+		size_t length);				/* init to this length */
+
+/* 
+ * Peek at the head of an Address/Length List.  This does *NOT* update
+ * the internal cursor.
+ */
+extern int
+alenpair_get(	alenlist_t alenlist,		/* in: get from this List */
+		alenaddr_t *address,		/* out: address */
+		size_t *length);		/* out: length */
+
+/* Free the space consumed by an Address/Length List. */
+extern void alenlist_destroy(alenlist_t alenlist);
+
+/*
+ * Indicate that we're done using an Address/Length List.
+ * If we are the last user, destroy the List.
+ */
+extern void
+alenlist_done(alenlist_t alenlist);
+
+/* Append another Pair to a List */
+extern int alenlist_append(alenlist_t alenlist, 	/* append to this list */
+			alenaddr_t address,		/* address to append */
+			size_t length,			/* length to append */
+			unsigned flags);
+
+/* 
+ * Replace a Pair in the middle of a List, and return old values.
+ * (not generally useful for drivers; used by bus providers).
+ */
+extern int
+alenlist_replace(	alenlist_t alenlist, 		/* in: replace in this list */
+			alenlist_cursor_t cursorp,	/* inout: which item to replace */
+			alenaddr_t *addrp, 		/* inout: address */
+			size_t *lengthp,		/* inout: length */
+			unsigned flags);
+
+
+/* Get the next Pair from a List */
+extern int alenlist_get(alenlist_t alenlist, 		/* in: get from this list */
+			alenlist_cursor_t cursorp,	/* inout: which item to get */
+			size_t maxlength,		/* in: at most length */
+			alenaddr_t *addr, 		/* out: address */
+			size_t *length,			/* out: length */
+			unsigned flags);
+
+
+/* Return the number of Pairs stored in this List */
+extern int alenlist_size(alenlist_t alenlist);
+
+/* Concatenate two Lists. */
+extern void alenlist_concat(	alenlist_t from, 	/* copy from this list */
+				alenlist_t to);		/* to this list */
+
+/* Create a copy of an Address/Length List */
+extern alenlist_t alenlist_clone(alenlist_t old,	/* clone this list */
+				 unsigned flags);
+
+
+/* Allocate and initialize an Address/Length List Cursor */
+extern alenlist_cursor_t alenlist_cursor_create(alenlist_t alenlist, unsigned flags);
+
+/* Free an Address/Length List Cursor */
+extern void alenlist_cursor_destroy(alenlist_cursor_t cursorp);
+
+/*
+ * Initialize an Address/Length List Cursor in order to walk thru an
+ * Address/Length List from the beginning.
+ */
+extern int alenlist_cursor_init(alenlist_t alenlist, 
+				size_t offset, 
+				alenlist_cursor_t cursorp);
+
+/* Clone an Address/Length List Cursor. */
+extern int alenlist_cursor_clone(alenlist_t alenlist, 
+				alenlist_cursor_t cursorp_in, 
+				alenlist_cursor_t cursorp_out);
+
+/* 
+ * Return the number of bytes passed so far according to the specified
+ * Address/Length List Cursor.
+ */
+extern size_t alenlist_cursor_offset(alenlist_t alenlist, alenlist_cursor_t cursorp);
+
+
+
+
+/* Convert from a Kernel Virtual Address to a Physical Address/Length List */
+extern alenlist_t kvaddr_to_alenlist(	alenlist_t alenlist, 
+					caddr_t kvaddr, 
+					size_t length, 
+					unsigned flags);
+
+/* Convert from a User Virtual Address to a Physical Address/Length List */
+extern alenlist_t uvaddr_to_alenlist(	alenlist_t alenlist,
+					uvaddr_t vaddr, 
+					size_t length,
+					unsigned flags);
+
+/* Convert from a buf struct to a Physical Address/Length List */
+struct buf;
+extern alenlist_t buf_to_alenlist(	alenlist_t alenlist, 
+					struct buf *buf, 
+					unsigned flags);
+
+
+/* 
+ * Tracking position as we walk down an Address/Length List.
+ * This structure is NOT generally for use by device drivers.
+ */
+struct alenlist_cursor_s {
+	struct alenlist_s	*al_alenlist;	/* which list */
+	size_t			al_offset;	/* total bytes passed by cursor */
+	struct alenlist_chunk_s	*al_chunk;	/* which chunk in alenlist */
+	unsigned int		al_index;	/* which pair in chunk */
+	size_t			al_bcount;	/* offset into address/length pair */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASM_SN_ALENLIST_H */
diff --git a/include/asm-ia64/sn/arc/hinv.h b/include/asm-ia64/sn/arc/hinv.h
new file mode 100644
index 000000000..be91e55ab
--- /dev/null
+++ b/include/asm-ia64/sn/arc/hinv.h
@@ -0,0 +1,186 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ */
+
+
+/* $Id$
+ *
+ * ARCS hardware/memory inventory/configuration and system ID definitions.
+ */
+#ifndef _ASM_SN_ARC_HINV_H
+#define _ASM_SN_ARC_HINV_H
+
+#include <asm/sn/arc/types.h>
+
+/* configuration query defines */
+typedef enum configclass {
+	SystemClass,
+	ProcessorClass,
+	CacheClass,
+#ifndef	_NT_PROM
+	MemoryClass,
+	AdapterClass,
+	ControllerClass,
+	PeripheralClass
+#else	/* _NT_PROM */
+	AdapterClass,
+	ControllerClass,
+	PeripheralClass,
+	MemoryClass
+#endif	/* _NT_PROM */
+} CONFIGCLASS;
+
+typedef enum configtype {
+	ARC,
+	CPU,
+	FPU,
+	PrimaryICache,
+	PrimaryDCache,
+	SecondaryICache,
+	SecondaryDCache,
+	SecondaryCache,
+#ifndef	_NT_PROM
+	Memory,
+#endif
+	EISAAdapter,
+	TCAdapter,
+	SCSIAdapter,
+	DTIAdapter,
+	MultiFunctionAdapter,
+	DiskController,
+	TapeController,
+	CDROMController,
+	WORMController,
+	SerialController,
+	NetworkController,
+	DisplayController,
+	ParallelController,
+	PointerController,
+	KeyboardController,
+	AudioController,
+	OtherController,
+	DiskPeripheral,
+	FloppyDiskPeripheral,
+	TapePeripheral,
+	ModemPeripheral,
+	MonitorPeripheral,
+	PrinterPeripheral,
+	PointerPeripheral,
+	KeyboardPeripheral,
+	TerminalPeripheral,
+	LinePeripheral,
+	NetworkPeripheral,
+#ifdef	_NT_PROM
+	Memory,
+#endif
+	OtherPeripheral,
+
+	/* new stuff for IP30 */
+	/* added without moving anything */
+	/* except ANONYMOUS. */
+
+	XTalkAdapter,
+	PCIAdapter,
+	GIOAdapter,
+	TPUAdapter,
+
+	Anonymous
+} CONFIGTYPE;
+
+typedef enum {
+	Failed = 1,
+	ReadOnly = 2,
+	Removable = 4,
+	ConsoleIn = 8,
+	ConsoleOut = 16,
+	Input = 32,
+	Output = 64
+} IDENTIFIERFLAG;
+
+#ifndef NULL			/* for GetChild(NULL); */
+#define	NULL	0
+#endif
+
+union key_u {
+	struct {
+#ifdef	_MIPSEB
+		unsigned char  c_bsize;		/* block size in lines */
+		unsigned char  c_lsize;		/* line size in bytes/tag */
+		unsigned short c_size;		/* cache size in 4K pages */
+#else	/* _MIPSEL */
+		unsigned short c_size;		/* cache size in 4K pages */
+		unsigned char  c_lsize;		/* line size in bytes/tag */
+		unsigned char  c_bsize;		/* block size in lines */
+#endif	/* _MIPSEL */
+	} cache;
+	ULONG FullKey;
+};
+
+#if _MIPS_SIM == _ABI64
+#define SGI_ARCS_VERS	64			/* sgi 64-bit version */
+#define SGI_ARCS_REV	0			/* rev .00 */
+#else
+#define SGI_ARCS_VERS	1			/* first version */
+#define SGI_ARCS_REV	10			/* rev .10, 3/04/92 */
+#endif
+
+typedef struct component {
+	CONFIGCLASS	Class;
+	CONFIGTYPE	Type;
+	IDENTIFIERFLAG	Flags;
+	USHORT		Version;
+	USHORT		Revision;
+	ULONG 		Key;
+	ULONG		AffinityMask;
+	ULONG		ConfigurationDataSize;
+	ULONG		IdentifierLength;
+	char		*Identifier;
+} COMPONENT;
+
+/* internal structure that holds pathname parsing data */
+struct cfgdata {
+	char *name;			/* full name */
+	int minlen;			/* minimum length to match */
+	CONFIGTYPE type;		/* type of token */
+};
+
+/* System ID */
+typedef struct systemid {
+	CHAR VendorId[8];
+	CHAR ProductId[8];
+} SYSTEMID;
+
+/* memory query functions */
+typedef enum memorytype {
+	ExceptionBlock,
+	SPBPage,			/* ARCS == SystemParameterBlock */
+#ifndef	_NT_PROM
+	FreeContiguous,
+	FreeMemory,
+	BadMemory,
+	LoadedProgram,
+	FirmwareTemporary,
+	FirmwarePermanent
+#else	/* _NT_PROM */
+	FreeMemory,
+	BadMemory,
+	LoadedProgram,
+	FirmwareTemporary,
+	FirmwarePermanent,
+	FreeContiguous
+#endif	/* _NT_PROM */
+} MEMORYTYPE;
+
+typedef struct memorydescriptor {
+	MEMORYTYPE	Type;
+	LONG		BasePage;
+	LONG		PageCount;
+} MEMORYDESCRIPTOR;
+
+#endif /* _ASM_SN_ARC_HINV_H */
diff --git a/include/asm-ia64/sn/arc/types.h b/include/asm-ia64/sn/arc/types.h
new file mode 100644
index 000000000..0c8118d81
--- /dev/null
+++ b/include/asm-ia64/sn/arc/types.h
@@ -0,0 +1,41 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SN_ARC_TYPES_H
+#define _ASM_SN_ARC_TYPES_H
+
+typedef char		CHAR;
+typedef short		SHORT;
+typedef long		LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef	long		LONG __attribute__ ((__mode__ (__DI__)));
+typedef unsigned char	UCHAR;
+typedef unsigned short	USHORT;
+typedef unsigned long	ULONG __attribute__ ((__mode__ (__DI__)));
+typedef void		VOID;
+
+/* The pointer types.  We're 64-bit and the firmware is also 64-bit, so
+   live is sane ...  */
+typedef CHAR		*_PCHAR;
+typedef SHORT		*_PSHORT;
+typedef LARGE_INTEGER	*_PLARGE_INTEGER;
+typedef	LONG		*_PLONG;
+typedef UCHAR		*_PUCHAR;
+typedef USHORT		*_PUSHORT;
+typedef ULONG		*_PULONG;
+typedef VOID		*_PVOID;
+
+typedef CHAR		*PCHAR;
+typedef SHORT		*PSHORT;
+typedef LARGE_INTEGER	*PLARGE_INTEGER;
+typedef	LONG		*PLONG;
+typedef UCHAR		*PUCHAR;
+typedef USHORT		*PUSHORT;
+typedef ULONG		*PULONG;
+typedef VOID		*PVOID;
+
+#endif /* _ASM_SN_ARC_TYPES_H */
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
new file mode 100644
index 000000000..67a5b0199
--- /dev/null
+++ b/include/asm-ia64/sn/arch.h
@@ -0,0 +1,175 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_ARCH_H
+#define _ASM_SN_ARCH_H
+
+#include <linux/types.h>
+#include <linux/config.h>
+
+#if defined(CONFIG_IA64_SGI_IO)
+#include <asm/sn/types.h>
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_SGI_IP37) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/arch.h>
+#endif
+#endif	/* CONFIG_IA64_SGI_IO */
+
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+typedef u64	hubreg_t;
+typedef u64	nic_t;
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+typedef u64     bdrkreg_t;
+#endif	/* CONFIG_SGI_xxxxx */
+#endif	/* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define CPUS_PER_NODE		4	/* CPUs on a single hub */
+#define CPUS_PER_NODE_SHFT	2	/* Bits to shift in the node number */
+#define CPUS_PER_SUBNODE	2	/* CPUs on a single hub PI */
+#endif
+#define CNODE_NUM_CPUS(_cnode)		(NODEPDA(_cnode)->node_num_cpus)
+
+#define CNODE_TO_CPU_BASE(_cnode)	(NODEPDA(_cnode)->node_first_cpu)
+
+#define makespnum(_nasid, _slice)					\
+		(((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+
+/*
+ * There are 2 very similar macros for dealing with "slices". Make sure
+ * you use the right one. 
+ * Unfortunately, on all platforms except IP35 (currently), the 2 macros 
+ * are interchangible. 
+ *
+ * On IP35, there are 4 cpus per node. Each cpu is refered to by it's slice.
+ * The slices are numbered 0 thru 3. 
+ *
+ * There are also 2 PI interfaces per node. Each PI interface supports 2 cpus.
+ * The term "local slice" specifies the cpu number relative to the PI.
+ *
+ * The cpus on the node are numbered:
+ *	slice	localslice
+ *	  0          0
+ *	  1          1
+ *	  2          0
+ *	  3          1
+ *
+ *	cputoslice - returns a number 0..3 that is the slice of the specified cpu.
+ *	cputolocalslice - returns a number 0..1 that identifies the local slice of
+ *			the cpu within it's PI interface.
+ */
+#ifdef notyet
+	/* These are dummied up for now ..... */
+#define cputocnode(cpu)				\
+               (pdaindr[(cpu)].p_nodeid)
+#define cputonasid(cpu)				\
+               (pdaindr[(cpu)].p_nasid)
+#define cputoslice(cpu)				\
+               (ASSERT(pdaindr[(cpu)].pda), (pdaindr[(cpu)].pda->p_slice))
+#define cputolocalslice(cpu)			\
+               (ASSERT(pdaindr[(cpu)].pda), (LOCALCPU(pdaindr[(cpu)].pda->p_slice)))
+#define cputosubnode(cpu)			\
+		(ASSERT(pdaindr[(cpu)].pda), (SUBNODE(pdaindr[(cpu)].pda->p_slice)))
+#else
+#define cputocnode(cpu) 0
+#define cputonasid(cpu) 0
+#define cputoslice(cpu) 0
+#define cputolocalslice(cpu) 0
+#define cputosubnode(cpu) 0
+#endif	/* notyet */
+#endif	/* CONFIG_SGI_IP35 */
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+
+#define INVALID_NASID		(nasid_t)-1
+#define INVALID_CNODEID		(cnodeid_t)-1
+#define INVALID_PNODEID		(pnodeid_t)-1
+#define INVALID_MODULE		(moduleid_t)-1
+#define	INVALID_PARTID		(partid_t)-1
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+extern int     get_slice(void);
+extern cpuid_t get_cnode_cpu(cnodeid_t);
+extern int get_cpu_slice(cpuid_t);
+extern cpuid_t cnodetocpu(cnodeid_t);
+// extern cpuid_t cnode_slice_to_cpuid(cnodeid_t, int);
+
+extern int cnode_exists(cnodeid_t cnode);
+extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
+#endif	/* CONFIG_IP35 */
+
+extern nasid_t get_nasid(void);
+extern cnodeid_t get_cpu_cnode(int);
+extern int get_cpu_slice(cpuid_t);
+
+/*
+ * NO ONE should access these arrays directly.  The only reason we refer to
+ * them here is to avoid the procedure call that would be required in the
+ * macros below.  (Really want private data members here :-)
+ */
+extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
+extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+
+/*
+ * These macros are used by various parts of the kernel to convert
+ * between the three different kinds of node numbering.   At least some
+ * of them may change to procedure calls in the future, but the macros
+ * will continue to work.  Don't use the arrays above directly.
+ */
+
+#define	NASID_TO_REGION(nnode)	      	\
+    ((nnode) >> \
+     (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
+
+extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
+extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
+
+#if !defined(DEBUG)
+
+#define NASID_TO_COMPACT_NODEID(nnode)	(nasid_to_compact_node[nnode])
+#define COMPACT_TO_NASID_NODEID(cnode)	(compact_to_nasid_node[cnode])
+#define CPUID_TO_COMPACT_NODEID(cpu)	(cpuid_to_compact_node[(cpu)])
+#else
+
+/*
+ * These functions can do type checking and fail if they need to return
+ * a bad nodeid, but they're not as fast so just use 'em for debug kernels.
+ */
+cnodeid_t nasid_to_compact_nodeid(nasid_t nasid);
+nasid_t compact_to_nasid_nodeid(cnodeid_t cnode);
+
+#define NASID_TO_COMPACT_NODEID(nnode)	nasid_to_compact_nodeid(nnode)
+#define COMPACT_TO_NASID_NODEID(cnode)	compact_to_nasid_nodeid(cnode)
+#define CPUID_TO_COMPACT_NODEID(cpu)	(cpuid_to_compact_node[(cpu)])
+#endif
+
+extern int node_getlastslot(cnodeid_t);
+
+#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+
+#define SLOT_BITMASK    	(MAX_MEM_SLOTS - 1)
+#define SLOT_SIZE		(1LL<<SLOT_SHIFT)
+
+#define node_getnumslots(node)	(MAX_MEM_SLOTS)
+#define NODE_MAX_MEM_SIZE	SLOT_SIZE * MAX_MEM_SLOTS
+
+/*
+ * New stuff in here from Irix sys/pfdat.h.
+ */
+#define	SLOT_PFNSHIFT		(SLOT_SHIFT - PAGE_SHIFT)
+#define	PFN_NASIDSHFT		(NASID_SHFT - PAGE_SHIFT)
+#define mkpfn(nasid, off)	(((pfn_t)(nasid) << PFN_NASIDSHFT) | (off))
+#define slot_getbasepfn(node,slot) \
+		(mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT))
+#endif /* _ASM_SN_ARCH_H */
diff --git a/include/asm-ia64/sn/cdl.h b/include/asm-ia64/sn/cdl.h
new file mode 100644
index 000000000..226030741
--- /dev/null
+++ b/include/asm-ia64/sn/cdl.h
@@ -0,0 +1,179 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_CDL_H
+#define _ASM_SN_CDL_H
+
+#include <asm/sn/sgi.h>
+
+/*
+ *	cdl: connection/driver list
+ *
+ *	support code for bus infrastructure for busses
+ *	that have self-identifying devices; initially
+ *	constructed for xtalk, pciio and gioio modules.
+ */
+typedef struct cdl     *cdl_p;
+
+/*
+ *	cdl_itr_f is the type for the functions
+ *	that are handled by cdl_iterate.
+ */
+
+typedef void	
+cdl_iter_f		(devfs_handle_t vhdl);
+
+/*
+ *	If CDL_PRI_HI is specified in the flags
+ *	parameter for cdl_add_driver, then that driver's
+ *	attach routine will be called for future connect
+ *	points before any (non-CDL_PRI_HI) drivers.
+ *
+ *	The IOC3 driver uses this facility to make sure
+ *	that the ioc3_attach() function is called before
+ *	the attach routines of any subdevices.
+ *
+ *	Drivers for bridge-based crosstalk cards that
+ *	are almost but not quite generic can use it to
+ *	arrange that their attach() functions get called
+ *	before the generic bridge drivers, so they can
+ *	leave behind "hint" structures that will
+ *	properly configure the generic driver.
+ */
+#define	CDL_PRI_HI	0x0001
+
+/*
+ *	cdl_new: construct a new connection/driver list
+ *
+ *	Called once for each "kind" of bus. Returns an
+ *	opaque cookie representing the particular list
+ *	that will be operated on by the other calls.
+ */
+extern cdl_p		cdl_new(char *, char *, char *);
+
+/*
+ *	cdl_del: destroy a connection/driver list.
+ *
+ *	Releases all dynamically allocated resources
+ *	associated with the specified list. Forgets what
+ *	drivers might be involved in this kind of bus,
+ *	forgets what connection points have been noticed
+ *	on this kind of bus.
+ */
+extern void		cdl_del(cdl_p reg);
+
+/*
+ *	cdl_add_driver: register a device driver
+ *
+ *	Calls the driver's attach routine with all
+ *	connection points on the list that have the same
+ *	key information as the driver; then places the
+ *	driver on the list so that any connection points
+ *	discovered in the future that match the driver
+ *	can be handed off to the driver's attach
+ *	routine.
+ *
+ *	CDL_PRI_HI may be specified (see above).
+ */
+
+extern int		cdl_add_driver(cdl_p reg,
+				       int key1,
+				       int key2,
+				       char *prefix,
+				       int flags);
+
+/*
+ *	cdl_del_driver: remove a device driver
+ *
+ *	Calls the driver's detach routine with all
+ *	connection points on the list that match the
+ *	driver; then forgets about the driver. Future
+ *	calls to cdl_add_connpt with connections that
+ *	would match this driver no longer trigger calls
+ *	to the driver's attach routine.
+ *
+ *	NOTE: Yes, I said CONNECTION POINTS, not
+ *	verticies that the driver has been attached to
+ *	with hwgraph_driver_add(); this gives the driver
+ *	a chance to clean up anything it did to the
+ *	connection point in its attach routine. Also,
+ *	this is done whether or not the attach routine
+ *	was successful.
+ */
+extern void		cdl_del_driver(cdl_p reg, 
+				       char *prefix);
+
+/*
+ *	cdl_add_connpt: add a connection point
+ *
+ *	Calls the attach routines of all the drivers on
+ *	the list that match this connection point, in
+ *	the order that they were added to the list,
+ *	except that CDL_PRI_HI drivers are called first.
+ *
+ *	Then the vertex is added to the list, so it can
+ *	be presented to any matching drivers that may be
+ *	subsequently added to the list.
+ */
+extern int		cdl_add_connpt(cdl_p reg,
+				       int key1,
+				       int key2,
+				       devfs_handle_t conn);
+
+/*
+ *	cdl_del_connpt: delete a connection point
+ *
+ *	Calls the detach routines of all matching
+ *	drivers for this connection point, in the same
+ *	order that the attach routines were called; then
+ *	forgets about this vertex, so drivers added in
+ *	the future will not be told about it.
+ *
+ *	NOTE: Same caveat here about the detach calls as
+ *	in the cdl_del_driver() comment above.
+ */
+extern void		cdl_del_connpt(cdl_p reg,
+				       int key1,
+				       int key2,
+				       devfs_handle_t conn);
+
+/*
+ *	cdl_iterate: find all verticies in the registry
+ *	corresponding to the named driver and call them
+ *	with the specified function (giving the vertex
+ *	as the parameter).
+ */
+
+extern void		cdl_iterate(cdl_p reg,
+				    char *prefix,
+				    cdl_iter_f *func);
+
+/*
+ * An INFO_LBL_ASYNC_ATTACH label is attached to a vertex, pointing to
+ * an instance of async_attach_s to indicate that asynchronous
+ * attachment may be applied to that device ... if the corresponding
+ * driver allows it.
+ */
+
+struct async_attach_s {
+	sema_t async_sema;
+	int    async_count;
+};
+typedef struct async_attach_s *async_attach_t;
+
+async_attach_t	async_attach_new(void);
+void		async_attach_free(async_attach_t);
+async_attach_t  async_attach_get_info(devfs_handle_t);
+void            async_attach_add_info(devfs_handle_t, async_attach_t);
+void            async_attach_del_info(devfs_handle_t);
+void		async_attach_signal_start(async_attach_t);
+void		async_attach_signal_done(async_attach_t);
+void		async_attach_waitall(async_attach_t);
+
+#endif	/* _ASM_SN_CDL_H */
diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h
new file mode 100644
index 000000000..6a2d2c009
--- /dev/null
+++ b/include/asm-ia64/sn/clksupport.h
@@ -0,0 +1,64 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ */
+
+
+#ifndef  _ASM_KSYS_CLKSUPPORT_H
+#define _ASM_KSYS_CLKSUPPORT_H
+
+/* #include <sys/mips_addrspace.h> */
+
+#if SN
+#include <asm/sn/agent.h>
+#include <asm/sn/intr_public.h>
+typedef hubreg_t clkreg_t;
+extern nasid_t master_nasid;
+
+#define GET_LOCAL_RTC		(clkreg_t)LOCAL_HUB_L(PI_RT_COUNT)
+#define DISABLE_TMO_INTR()	if  (cpuid_to_localslice(cpuid())) \
+					REMOTE_HUB_PI_S(get_nasid(),\
+						cputosubnode(cpuid()),\
+						PI_RT_COMPARE_B, 0); \
+				else \
+					REMOTE_HUB_PI_S(get_nasid(),\
+						cputosubnode(cpuid()),\
+						PI_RT_COMPARE_A, 0);
+
+/* This is a hack; we really need to figure these values out dynamically */
+/* 
+ * Since 800 ns works very well with various HUB frequencies, such as
+ * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time.
+ */
+#define NSEC_PER_CYCLE		800
+#define CYCLE_PER_SEC		(NSEC_PER_SEC/NSEC_PER_CYCLE)
+/*
+ * Number of cycles per profiling intr 
+ */
+#define CLK_FCLOCK_FAST_FREQ	1250
+#define CLK_FCLOCK_SLOW_FREQ	0
+/* The is the address that the user will use to mmap the cycle counter */
+#define CLK_CYCLE_ADDRESS_FOR_USER LOCAL_HUB_ADDR(PI_RT_COUNT)
+
+#elif IP30
+#include <sys/cpu.h>
+typedef heartreg_t clkreg_t;
+#define NSEC_PER_CYCLE		80
+#define CYCLE_PER_SEC		(NSEC_PER_SEC/NSEC_PER_CYCLE)
+#define GET_LOCAL_RTC	*((volatile clkreg_t *)PHYS_TO_COMPATK1(HEART_COUNT))
+#define DISABLE_TMO_INTR()
+#define CLK_CYCLE_ADDRESS_FOR_USER PHYS_TO_K1(HEART_COUNT)
+#define CLK_FCLOCK_SLOW_FREQ (CYCLE_PER_SEC / HZ)
+#endif
+
+/* Prototypes */
+extern void init_timebase(void);
+extern void fastick_maint(struct eframe_s *);
+extern int audioclock;
+extern int prfclk_enabled_cnt;
+#endif  /* _ASM_KSYS_CLKSUPPORT_H */
diff --git a/include/asm-ia64/sn/cmn_err.h b/include/asm-ia64/sn/cmn_err.h
new file mode 100644
index 000000000..13a104026
--- /dev/null
+++ b/include/asm-ia64/sn/cmn_err.h
@@ -0,0 +1,120 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_CMN_ERR_H
+#define _ASM_SN_CMN_ERR_H
+
+/*
+** Common error handling severity levels.  Converted to be
+** represented by the associated 4.3BSD syslog priorities.
+*/
+
+#define CE_DEBUG	KERN_DEBUG	/* debug	*/
+#define CE_CONT		KERN_INFO	/* continuation	*/
+#define CE_NOTE		KERN_NOTICE	/* notice	*/
+#define CE_WARN		KERN_WARNING	/* warning	*/
+#define CE_ALERT	KERN_ALERT	/* alert	*/
+#define CE_PANIC	KERN_EMERG	/* panic	*/
+
+#define	CE_LEVELMASK	LOG_PRIMASK	/* mask for severity level	*/
+#define	CE_CPUID	0x8		/* prepend CPU id to output	*/
+#define CE_PHYSID	0x10		/* prepend CPU phys location    */
+#define CE_SYNC		0x20		/* wait for uart to drain before returning */
+
+/* Flags for Availmon Monitoring
+ * When a developer or's these bits into the cmn_err flags above,
+ * and they have availmon installed, certain "actions" will take
+ * place depending upon how they have the availmon software configured.
+ */
+#define CE_TOOKACTIONS   0x0100            /* Actions taken by some error   */
+#define CE_RUNNINGPOOR   0x0200            /* System running degraded       */
+#define CE_MAINTENANCE   0x0400            /* System needs maintenance      */
+#define CE_CONFIGERROR   0x0800            /* System configured incorrectly */
+
+/* Bitmasks for separating subtasks from priority levels */
+#define CE_PRIOLEVELMASK 0x00ff  /* bitmask for severity levels of cmn_err */
+#define CE_SUBTASKMASK   0xff00  /* bitmask for availmon actions of cmn_err */
+#define CE_AVAILMONALL   (CE_TOOKACTIONS|CE_RUNNINGPOOR| \
+                                 CE_MAINTENANCE|CE_CONFIGERROR)
+
+#ifdef __KERNEL__
+
+#define CE_PBPANIC	KERN_CRIT	/* Special define used to manipulate
+					 * putbufndx in kernel */
+
+/* Console output flushing flag and routine */
+
+extern int constrlen;		/* Length of current console string, if zero,
+				   there are no characters to flush */
+#define	CONBUF_LOCKED	0	/* conbuf is already locked */
+#define	CONBUF_UNLOCKED	1	/* need to reacquire lock */
+#define CONBUF_DRAIN	2	/* ensure output before returning */
+
+/*
+ * bit field descriptions for printf %r and %R formats
+ *
+ * printf("%r %R", val, reg_descp);
+ * struct reg_desc *reg_descp;
+ *
+ * the %r and %R formats allow formatted print of bit fields.  individual
+ * bit fields are described by a struct reg_desc, multiple bit fields within
+ * a single word can be described by multiple reg_desc structures.
+ * %r outputs a string of the format "<bit field descriptions>"
+ * %R outputs a string of the format "0x%x<bit field descriptions>"
+ *
+ * The fields in a reg_desc are:
+ *	__psunsigned_t rd_mask;	An appropriate mask to isolate the bit field
+ *				within a word, and'ed with val
+ *
+ *	int rd_shift;		A shift amount to be done to the isolated
+ *				bit field.  done before printing the isolate
+ *				bit field with rd_format and before searching
+ *				for symbolic value names in rd_values
+ *
+ *	char *rd_name;		If non-null, a bit field name to label any
+ *				out from rd_format or searching rd_values.
+ *				if neither rd_format or rd_values is non-null
+ *				rd_name is printed only if the isolated
+ *				bit field is non-null.
+ *
+ *	char *rd_format;	If non-null, the shifted bit field value
+ *				is printed using this format.
+ *
+ *	struct reg_values *rd_values;	If non-null, a pointer to a table
+ *				matching numeric values with symbolic names.
+ *				rd_values are searched and the symbolic
+ *				value is printed if a match is found, if no
+ *				match is found "???" is printed.
+ *				
+ */
+
+
+/*
+ * register values
+ * map between numeric values and symbolic values
+ */
+struct reg_values {
+	__psunsigned_t rv_value;
+	char *rv_name;
+};
+
+/*
+ * register descriptors are used for formatted prints of register values
+ * rd_mask and rd_shift must be defined, other entries may be null
+ */
+struct reg_desc {
+	k_machreg_t rd_mask;	/* mask to extract field */
+	int rd_shift;		/* shift for extracted value, - >>, + << */
+	char *rd_name;		/* field name */
+	char *rd_format;	/* format to print field */
+	struct reg_values *rd_values;	/* symbolic names of values */
+};
+
+#endif	/* __KERNEL__ */
+#endif	/* _ASM_SN_CMN_ERR_H */
diff --git a/include/asm-ia64/sn/dmamap.h b/include/asm-ia64/sn/dmamap.h
new file mode 100644
index 000000000..b927240b0
--- /dev/null
+++ b/include/asm-ia64/sn/dmamap.h
@@ -0,0 +1,88 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_DMAMAP_H
+#define _ASM_SN_DMAMAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Definitions for allocating, freeing, and using DMA maps
+ */
+
+/*
+ * DMA map types
+ */
+#define	DMA_SCSI	0
+#define	DMA_A24VME	1		/* Challenge/Onyx only 	*/
+#define	DMA_A32VME	2		/* Challenge/Onyx only 	*/
+#define	DMA_A64VME	3		/* SN0/Racer */
+
+#define	DMA_EISA	4
+
+#define	DMA_PCI32	5		/* SN0/Racer 	*/
+#define	DMA_PCI64	6		/* SN0/Racer 	*/
+
+/*
+ * DMA map structure as returned by dma_mapalloc()
+ */
+typedef struct dmamap {
+	int		dma_type;	/* Map type (see above) */
+	int		dma_adap;	/* I/O adapter */
+	int		dma_index;	/* Beginning map register to use */
+	int		dma_size;	/* Number of map registers to use */
+	paddr_t		dma_addr;	/* Corresponding bus addr for A24/A32 */
+	caddr_t		dma_virtaddr;	/* Beginning virtual address that is mapped */
+} dmamap_t;
+
+struct alenlist_s;
+
+/*
+ * Prototypes of exported functions
+ */
+extern dmamap_t	*dma_mapalloc(int, int, int, int);
+extern void	dma_mapfree(dmamap_t *);
+extern int	dma_map(dmamap_t *, caddr_t, int);
+extern int	dma_map2(dmamap_t *, caddr_t, caddr_t, int);
+extern paddr_t	dma_mapaddr(dmamap_t *, caddr_t);
+#ifdef IRIX
+extern int	dma_mapbp(dmamap_t *, buf_t *, int);
+#endif
+extern int	dma_map_alenlist(dmamap_t *, struct alenlist_s *, size_t);
+extern uint	ev_kvtoiopnum(caddr_t);
+
+/*
+ * These variables are defined in master.d/kernel
+ */
+extern struct map *a24map[];
+extern struct map *a32map[];
+
+extern int a24_mapsize;
+extern int a32_mapsize;
+
+extern lock_t dmamaplock;
+extern sv_t dmamapout;
+
+#ifdef __cplusplus
+}
+#endif
+
+/* standard flags values for pio_map routines,
+ * including {xtalk,pciio}_dmamap calls.
+ * NOTE: try to keep these in step with PIOMAP flags.
+ */
+#define DMAMAP_FIXED	0x1
+#define DMAMAP_NOSLEEP	0x2
+#define	DMAMAP_INPLACE	0x4
+
+#define	DMAMAP_FLAGS	0x7
+
+#endif /* _ASM_SN_DMAMAP_H */
diff --git a/include/asm-ia64/sn/driver.h b/include/asm-ia64/sn/driver.h
new file mode 100644
index 000000000..f71f4348b
--- /dev/null
+++ b/include/asm-ia64/sn/driver.h
@@ -0,0 +1,150 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_DRIVER_H
+#define _ASM_SN_DRIVER_H
+
+/*
+** Interface for device driver handle management.
+**
+** These functions are mostly for use by the loadable driver code, and
+** for use by I/O bus infrastructure code.
+*/
+
+typedef struct device_driver_s *device_driver_t;
+#define DEVICE_DRIVER_NONE (device_driver_t)NULL
+
+/* == Driver thread priority support == */
+typedef int ilvl_t;
+/* default driver thread priority level */
+#define DRIVER_THREAD_PRI_DEFAULT	(ilvl_t)230
+/* invalid driver thread priority level */
+#define DRIVER_THREAD_PRI_INVALID	(ilvl_t)-1
+
+/* Associate a thread priority with a driver */
+extern int device_driver_thread_pri_set(device_driver_t driver,
+					ilvl_t pri);
+
+/* Get the thread priority associated with the driver */
+extern ilvl_t device_driver_thread_pri_get(device_driver_t driver);
+
+/* Get the thread priority for a driver from the sysgen paramters */
+extern ilvl_t device_driver_sysgen_thread_pri_get(char *driver_prefix);
+
+/* Initialize device driver functions. */
+extern void device_driver_init(void);
+
+
+/* Allocate a driver handle */
+extern device_driver_t device_driver_alloc(char *prefix);
+
+
+/* Free a driver handle */
+extern void device_driver_free(device_driver_t driver);
+
+
+/* Given a device driver prefix, return a handle to the driver. */
+extern device_driver_t device_driver_get(char *prefix);
+
+/* Given a device, return a handle to the driver. */
+extern device_driver_t device_driver_getbydev(devfs_handle_t device);
+
+struct cdevsw;
+struct bdevsw;
+
+/* Associate a driver with bdevsw/cdevsw pointers. */
+extern int
+device_driver_devsw_put(device_driver_t driver,
+			struct bdevsw *my_bdevsw,
+			struct cdevsw *my_cdevsw);
+
+
+/* Given a driver, return the corresponding bdevsw and cdevsw pointers. */
+extern void
+device_driver_devsw_get(	device_driver_t driver, 
+				struct bdevsw **bdevswp,
+				struct cdevsw **cdevswp);
+
+/* Given a driver, return its name (prefix). */
+extern void device_driver_name_get(device_driver_t driver, char *buffer, int length);
+
+
+/* 
+ * A descriptor for every static device driver in the system.
+ * lboot creates a table of these and places in in master.c.
+ * device_driver_init runs through this table during initialization
+ * in order to "register" every static device driver.
+ */
+typedef struct static_device_driver_desc_s {
+	char 		*sdd_prefix;
+	struct bdevsw 	*sdd_bdevsw;
+	struct cdevsw 	*sdd_cdevsw;
+} *static_device_driver_desc_t;
+
+extern struct static_device_driver_desc_s static_device_driver_table[];
+extern int static_devsw_count;
+
+
+/*====== administration support ========== */
+/* structure of each entry in the table created by lboot for
+ * device / driver administration
+*/
+typedef struct dev_admin_info_s {
+	char	*dai_name;		/* name of the device or driver
+					 * prefix 
+					 */
+	char	*dai_param_name;	/* device or driver parameter name */
+	char	*dai_param_val;		/* value of the parameter */
+} dev_admin_info_t;
+
+
+/* Update all the administrative hints associated with the device */
+extern void 	device_admin_info_update(devfs_handle_t	dev_vhdl);
+
+/* Update all the administrative hints associated with the device driver */
+extern void	device_driver_admin_info_update(device_driver_t	driver);
+
+/* Get a particular administrative hint associated with a device */
+extern char 	*device_admin_info_get(devfs_handle_t	dev_vhdl,
+				       char		*info_lbl);
+
+/* Associate a particular administrative hint for a device */
+extern int	device_admin_info_set(devfs_handle_t	dev_vhdl,
+				      char		*info_lbl,
+				      char		*info_val);
+
+/* Get a particular administrative hint associated with a device driver*/
+extern char 	*device_driver_admin_info_get(char	*driver_prefix,	
+					      char	*info_name);
+
+/* Associate a particular administrative hint for a device driver*/
+extern int	device_driver_admin_info_set(char	*driver_prefix,
+					     char	*driver_info_lbl,
+					     char	*driver_info_val);
+
+/* Initialize the extended device administrative hint table */
+extern void	device_admin_table_init(void);
+
+/* Add a hint corresponding to a device to the extended device administrative
+ * hint table.
+ */
+extern void	device_admin_table_update(char *dev_name,
+					  char *param_name,
+					  char *param_val);
+
+/* Initialize the extended device driver administrative hint table */
+extern void	device_driver_admin_table_init(void);
+
+/* Add a hint corresponding to a device to the extended device driver 
+ * administrative hint table.
+ */
+extern void	device_driver_admin_table_update(char *drv_prefix,
+						 char *param_name,
+						 char *param_val);	
+#endif /* _ASM_SN_DRIVER_H */
diff --git a/include/asm-ia64/sn/eeprom.h b/include/asm-ia64/sn/eeprom.h
new file mode 100644
index 000000000..bb207cfc6
--- /dev/null
+++ b/include/asm-ia64/sn/eeprom.h
@@ -0,0 +1,402 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Public interface for reading Atmel EEPROMs via L1 system controllers
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_EEPROM_H
+#define _ASM_SN_EEPROM_H
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/vector.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/nic.h>
+
+/*
+ * The following structures are an implementation of the EEPROM info
+ * areas described in the SN1 EEPROM spec and the IPMI FRU Information
+ * Storage definition
+ */
+
+/* Maximum lengths for EEPROM fields
+ */
+#define EEPROM_PARTNUM_LEN	20
+#define EEPROM_SERNUM_LEN	10
+#define	EEPROM_MANUF_NAME_LEN	10
+#define EEPROM_PROD_NAME_LEN	14
+
+
+
+/* The EEPROM "common header", which contains offsets to the other
+ * info areas in the EEPROM
+ */
+typedef struct eeprom_common_hdr_t
+{
+    uchar_t	format;		/* common header format byte */
+    uchar_t	internal_use;	/* offsets to various info areas */
+    uchar_t	chassis;	/*  (in doubleword units)        */
+    uchar_t	board;
+    uchar_t	product;
+    uchar_t	multi_record;
+    uchar_t	pad;
+    uchar_t	checksum;
+} eeprom_common_hdr_t;
+
+
+/* The chassis (brick) info area 
+ */
+typedef struct eeprom_chassis_ia_t
+{
+    uchar_t	format;		/* format byte */
+    uchar_t	length;		/* info area length in doublewords */
+    uchar_t	type;		/* chassis type (always 0x17 "rack mount") */
+    uchar_t	part_num_tl;	/* type/length of part number field */
+
+    char	part_num[EEPROM_PARTNUM_LEN];
+    				/* ASCII part number */
+
+    uchar_t	serial_num_tl;	/* type/length of serial number field */
+
+    char	serial_num[EEPROM_SERNUM_LEN];
+    				/* ASCII serial number */
+
+    uchar_t	checksum;
+
+} eeprom_chassis_ia_t;
+
+
+/* The board info area
+ */
+typedef struct eeprom_board_ia_t
+{
+    uchar_t       format;         /* format byte */
+    uchar_t       length;         /* info area length in doublewords */
+    uchar_t	language;	/* language code, always 0x00 "English" */
+    int		mfg_date;	/* date & time of manufacture, in minutes
+				    since 0:00 1/1/96 */
+    uchar_t	manuf_tl;	/* type/length of manufacturer name field */
+
+    char	manuf[EEPROM_MANUF_NAME_LEN];
+				/* ASCII manufacturer name */
+
+    uchar_t	product_tl;	/* type/length of product name field */
+
+    char	product[EEPROM_PROD_NAME_LEN];
+				/* ASCII product name */
+
+    uchar_t	serial_num_tl;	/* type/length of board serial number */
+
+    char	serial_num[EEPROM_SERNUM_LEN];
+				/* ASCII serial number */
+
+    uchar_t	part_num_tl;	/* type/length of board part number */
+
+    char	part_num[EEPROM_PARTNUM_LEN];
+				/* ASCII part number */
+
+    /*
+     * "custom" fields -- see SN1 EEPROM Spec
+     */
+    uchar_t	board_rev_tl;	/* type/length of board rev (always 0xC2) */
+
+    char	board_rev[2];	/* ASCII board revision */
+
+    uchar_t	eeprom_size_tl; /* type/length of eeprom size field */
+    uchar_t	eeprom_size;	/* size code for eeprom */
+    uchar_t	temp_waiver_tl;	/* type/length of temp waiver field (0xC2) */
+    char	temp_waiver[2];	/* temp waiver */
+
+    
+    /*
+     * these fields only appear in main boards' EEPROMs
+     */
+    uchar_t	ekey_G_tl;	/* type/length of encryption key "G" */
+    uint32_t	ekey_G;		/* encryption key "G" */
+    uchar_t	ekey_P_tl;	/* type/length of encryption key "P" */
+    uint32_t	ekey_P;		/* encryption key "P" */
+    uchar_t	ekey_Y_tl;	/* type/length of encryption key "Y" */
+    uint32_t	ekey_Y;		/* encryption key "Y" */
+
+    
+    /*
+     * these fields are used for I bricks only
+     */
+    uchar_t	mac_addr_tl;	  /* type/length of MAC address */
+    char	mac_addr[12];	  /* MAC address */
+    uchar_t	ieee1394_cfg_tl;  /* type/length of IEEE 1394 info */
+    uchar_t	ieee1394_cfg[32]; /* IEEE 1394 config info */
+    
+
+    /*
+     * all boards have a checksum
+     */
+    uchar_t	checksum;
+
+} eeprom_board_ia_t;
+
+/* given a pointer to the three-byte little-endian EEPROM representation
+ * of date-of-manufacture, this function translates to a big-endian
+ * integer format
+ */
+int eeprom_xlate_board_mfr_date( uchar_t *src );
+
+
+/* EEPROM Serial Presence Detect record (used for DIMMs in IP35)
+ */
+typedef struct eeprom_spd_t
+{
+    /* 0*/ uchar_t spd_used; /* # of bytes written to serial memory by manufacturer */
+    /* 1*/ uchar_t spd_size; /* Total # of bytes of SPD memory device */
+    /* 2*/ uchar_t mem_type; /* Fundamental memory type (FPM, EDO, SDRAM..) */
+    /* 3*/ uchar_t num_rows; /* # of row addresses on this assembly */
+    /* 4*/ uchar_t num_cols; /* # Column Addresses on this assembly */
+    /* 5*/ uchar_t mod_rows; /* # Module Rows on this assembly */
+    /* 6*/ uchar_t data_width[2]; /* Data Width of this assembly (16b little-endian) */
+    /* 8*/ uchar_t volt_if; /* Voltage interface standard of this assembly */
+    /* 9*/ uchar_t cyc_time; /* SDRAM Cycle time, CL=X (highest CAS latency) */
+    /* A*/ uchar_t acc_time; /* SDRAM Access from Clock (highest CAS latency) */
+    /* B*/ uchar_t dimm_cfg; /* DIMM Configuration type (non-parity, ECC) */
+    /* C*/ uchar_t refresh_rt; /* Refresh Rate/Type */
+    /* D*/ uchar_t prim_width; /* Primary SDRAM Width */
+    /* E*/ uchar_t ec_width; /* Error Checking SDRAM width */
+    /* F*/ uchar_t min_delay; /* Min Clock Delay Back to Back Random Col Address */
+    /*10*/ uchar_t burst_len; /* Burst Lengths Supported */
+    /*11*/ uchar_t num_banks; /* # of Banks on Each SDRAM Device */
+    /*12*/ uchar_t cas_latencies; /* CAS# Latencies Supported */
+    /*13*/ uchar_t cs_latencies; /* CS# Latencies Supported */
+    /*14*/ uchar_t we_latencies; /* Write Latencies Supported */
+    /*15*/ uchar_t mod_attrib; /* SDRAM Module Attributes */
+    /*16*/ uchar_t dev_attrib; /* SDRAM Device Attributes: General */
+    /*17*/ uchar_t cyc_time2; /* Min SDRAM Cycle time at CL X-1 (2nd highest CAS latency) */
+    /*18*/ uchar_t acc_time2; /* SDRAM Access from Clock at CL X-1 (2nd highest CAS latency) */
+    /*19*/ uchar_t cyc_time3; /* Min SDRAM Cycle time at CL X-2 (3rd highest CAS latency) */
+    /*1A*/ uchar_t acc_time3; /* Max SDRAM Access from Clock at CL X-2 (3nd highest CAS latency) */
+    /*1B*/ uchar_t min_row_prechg; /* Min Row Precharge Time (Trp) */
+    /*1C*/ uchar_t min_ra_to_ra; /* Min Row Active to Row Active (Trrd) */
+    /*1D*/ uchar_t min_ras_to_cas; /* Min RAS to CAS Delay (Trcd) */
+    /*1E*/ uchar_t min_ras_pulse; /* Minimum RAS Pulse Width (Tras) */
+    /*1F*/ uchar_t row_density; /* Density of each row on module */
+    /*20*/ uchar_t ca_setup; /* Command and Address signal input setup time */
+    /*21*/ uchar_t ca_hold; /* Command and Address signal input hold time */
+    /*22*/ uchar_t d_setup; /* Data signal input setup time */
+    /*23*/ uchar_t d_hold; /* Data signal input hold time */
+
+    /*24*/ uchar_t pad0[26]; /* unused */
+    
+    /*3E*/ uchar_t data_rev; /* SPD Data Revision Code */
+    /*3F*/ uchar_t checksum; /* Checksum for bytes 0-62 */
+    /*40*/ uchar_t jedec_id[8]; /* Manufacturer's JEDEC ID code */
+    
+    /*48*/ uchar_t mfg_loc; /* Manufacturing Location */
+    /*49*/ uchar_t part_num[18]; /* Manufacturer's Part Number */
+
+    /*5B*/ uchar_t rev_code[2]; /* Revision Code */
+
+    /*5D*/ uchar_t mfg_date[2]; /* Manufacturing Date */
+
+    /*5F*/ uchar_t ser_num[4]; /* Assembly Serial Number */
+
+    /*63*/ uchar_t manuf_data[27]; /* Manufacturer Specific Data */
+
+    /*7E*/ uchar_t intel_freq; /* Intel specification frequency */
+    /*7F*/ uchar_t intel_100MHz; /* Intel spec details for 100MHz support */
+
+} eeprom_spd_t;
+
+
+#define EEPROM_SPD_RECORD_MAXLEN	256
+
+typedef union eeprom_spd_u
+{
+    eeprom_spd_t fields;
+    char         bytes[EEPROM_SPD_RECORD_MAXLEN];
+
+} eeprom_spd_u;
+
+
+/* EEPROM board record
+ */
+typedef struct eeprom_brd_record_t 
+{
+    eeprom_chassis_ia_t		*chassis_ia;
+    eeprom_board_ia_t		*board_ia;
+    eeprom_spd_u		*spd;
+
+} eeprom_brd_record_t;
+
+
+/* End-of-fields marker
+ */
+#define EEPROM_EOF	        0xc1
+
+
+/* masks for dissecting the type/length bytes
+ */
+#define FIELD_FORMAT_MASK       0xc0
+#define FIELD_LENGTH_MASK       0x3f
+
+
+/* field format codes (used in type/length bytes)
+ */
+#define FIELD_FORMAT_BINARY     0x00 /* binary format */
+#define FIELD_FORMAT_BCD        0x40 /* BCD */
+#define FIELD_FORMAT_PACKED     0x80 /* packed 6-bit ASCII */
+#define FIELD_FORMAT_ASCII      0xC0 /* 8-bit ASCII */
+
+
+
+
+/* codes specifying brick and board type
+ */
+#define C_BRICK		0x100
+
+#define C_PIMM		(C_BRICK | 0x10)
+#define C_PIMM_0	(C_PIMM) /* | 0x0 */
+#define C_PIMM_1	(C_PIMM | 0x1)
+
+#define C_DIMM		(C_BRICK | 0x20)
+#define C_DIMM_0	(C_DIMM) /* | 0x0 */
+#define C_DIMM_1	(C_DIMM | 0x1)
+#define C_DIMM_2	(C_DIMM | 0x2)
+#define C_DIMM_3	(C_DIMM | 0x3)
+#define C_DIMM_4	(C_DIMM | 0x4)
+#define C_DIMM_5	(C_DIMM | 0x5)
+#define C_DIMM_6	(C_DIMM | 0x6)
+#define C_DIMM_7	(C_DIMM | 0x7)
+
+#define R_BRICK		0x200
+#define R_POWER		(R_BRICK | 0x10)
+
+#define VECTOR		0x300 /* used in vector ops when the destination
+			       * could be a cbrick or an rbrick */
+
+#define IO_BRICK	0x400
+#define IO_POWER	(IO_BRICK | 0x10)
+
+#define BRICK_MASK	0xf00
+#define SUBORD_MASK	0xf0  /* AND with component specification; if the
+			         the result is non-zero, then the component
+			         is a subordinate board of some kind */
+#define COMPT_MASK	0xf   /* if there's more than one instance of a
+				 particular type of subordinate board, this 
+				 masks out which one we're talking about */
+
+
+
+/* functions & macros for obtaining "NIC-like" strings from EEPROMs
+ */
+
+int eeprom_str( char *nic_str, nasid_t nasid, int component );
+int vector_eeprom_str( char *nic_str, nasid_t nasid,
+		       int component, net_vec_t path );
+
+#define CBRICK_EEPROM_STR(s,n)	eeprom_str((s),(n),C_BRICK)
+#define IOBRICK_EEPROM_STR(s,n)	eeprom_str((s),(n),IO_BRICK)
+#define RBRICK_EEPROM_STR(s,n,p)  vector_eeprom_str((s),(n),R_BRICK,p)
+#define VECTOR_EEPROM_STR(s,n,p)  vector_eeprom_str((s),(n),VECTOR,p)
+
+
+
+/* functions for obtaining formatted records from EEPROMs
+ */
+
+int cbrick_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid,
+			int component );
+int iobrick_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid,
+			 int component );
+int vector_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid,
+			net_vec_t path, int component );
+
+
+/* functions providing unique id's for duplonet and i/o discovery
+ */
+
+int cbrick_uid_get( nasid_t nasid, uint64_t *uid );
+int rbrick_uid_get( nasid_t nasid, net_vec_t path, uint64_t *uid );
+int iobrick_uid_get( nasid_t nasid, uint64_t *uid );
+
+
+/* retrieve the ethernet MAC address for an I-brick
+ */
+
+int ibrick_mac_addr_get( nasid_t nasid, char *eaddr );
+
+
+/* error codes
+ */
+
+#define EEP_OK			0
+#define EEP_L1			1
+#define EEP_FAIL		2
+#define EEP_BAD_CHECKSUM	3
+#define EEP_NICIFY		4
+#define EEP_PARAM		6
+#define EEP_NOMEM		7
+
+
+
+/* given a hardware graph vertex and an indication of the brick type,
+ * brick and board to be read, this functions reads the eeprom and
+ * attaches a "NIC"-format string of manufacturing information to the 
+ * vertex.  If the vertex already has the string, just returns the
+ * string.  If component is not VECTOR or R_BRICK, the path parameter
+ * is ignored.
+ */
+
+#ifdef IRIX
+char *eeprom_vertex_info_set( int component, int nasid, devfs_handle_t v,
+			      net_vec_t path );
+#endif
+
+
+
+/* We may need to differentiate between an XBridge and other types of
+ * bridges during discovery to tell whether the bridge in question
+ * is part of an IO brick.  The following function reads the WIDGET_ID
+ * register of the bridge under examination and returns a positive value
+ * if the part and mfg numbers stored there indicate that this widget
+ * is an XBridge (and so must be part of a brick).
+ */
+#ifdef IRIX
+int is_iobrick( int nasid, int widget_num );
+#endif
+
+/* the following macro derives the widget number from the register
+ * address passed to it and uses is_iobrick to determine whether
+ * the widget in question is part of an SN1 IO brick.
+ */
+#ifdef IRIX
+#define IS_IOBRICK(rg)	is_iobrick( NASID_GET((rg)), SWIN_WIDGETNUM((rg)) )
+#else
+#define IS_IOBRICK(rg)	1
+#endif
+
+
+
+/* macros for NIC compatability */
+/* always invoked on "this" cbrick */
+#define HUB_VERTEX_MFG_INFO(v) \
+    eeprom_vertex_info_set( C_BRICK, get_nasid(), (v), 0 )
+
+#define BRIDGE_VERTEX_MFG_INFO(v, r) \
+    ( IS_IOBRICK((r)) ? eeprom_vertex_info_set \
+		          ( IO_BRICK, NASID_GET((r)), (v), 0 ) \
+		      : nic_bridge_vertex_info((v), (r)) )
+
+#ifdef BRINGUP /* will we read mfg info from IOC3's that aren't
+		* part of IO7 cards, or aren't in I/O bricks? */
+#define IOC3_VERTEX_MFG_INFO(v, r, e) \
+    eeprom_vertex_info_set( IO_IO7, NASID_GET((r)), (v), 0 )
+#endif /* BRINGUP */
+
+#define HUB_UID_GET(n,v,p)	cbrick_uid_get((n),(p))
+#define ROUTER_UID_GET(d,p)	rbrick_uid_get(get_nasid(),(d),(p))
+#define XBOW_UID_GET(n,p)	iobrick_uid_get((n),(p))
+
+#endif /* _ASM_SN_EEPROM_H */
diff --git a/include/asm-ia64/sn/gda.h b/include/asm-ia64/sn/gda.h
new file mode 100644
index 000000000..385aeb265
--- /dev/null
+++ b/include/asm-ia64/sn/gda.h
@@ -0,0 +1,108 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/gda.h>.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ *
+ * gda.h -- Contains the data structure for the global data area,
+ * 	The GDA contains information communicated between the
+ *	PROM, SYMMON, and the kernel. 
+ */
+#ifndef _ASM_SN_GDA_H
+#define _ASM_SN_GDA_H
+
+#include <asm/sn/addrs.h>
+
+#define GDA_MAGIC	0x58464552
+
+/*
+ * GDA Version History
+ *
+ * Version #	| Change
+ * -------------+-------------------------------------------------------
+ * 	1	| Initial IP27 version 
+ * 	2	| Prom sets g_partid field to the partition number. 0 IS
+ *		| a valid partition #. 
+ */
+
+#define GDA_VERSION	2	/* Current GDA version # */
+
+#define G_MAGICOFF	0
+#define G_VERSIONOFF	4
+#define G_PROMOPOFF	6
+#define G_MASTEROFF	8
+#define G_VDSOFF	12
+#define G_HKDNORMOFF	16
+#define G_HKDUTLBOFF	24
+#define G_HKDXUTLBOFF	32
+#define G_PARTIDOFF	40
+#define G_TABLEOFF	128
+
+#ifdef _LANGUAGE_C
+
+typedef struct gda {
+	u32	g_magic;	/* GDA magic number */
+	u16	g_version;	/* Version of this structure */
+	u16	g_masterid;	/* The NASID:CPUNUM of the master cpu */
+	u32	g_promop;	/* Passes requests from the kernel to prom */
+	u32	g_vds;		/* Store the virtual dipswitches here */
+	void	**g_hooked_norm;/* ptr to pda loc for norm hndlr */
+	void	**g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
+	void	**g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
+	int	g_partid;	/* partition id */
+	int	g_symmax;	/* Max symbols in name table. */
+	void	*g_dbstab;	/* Address of idbg symbol table */
+	char	*g_nametab;	/* Address of idbg name table */
+	void	*g_ktext_repmask;
+				/* Pointer to a mask of nodes with copies
+				 * of the kernel. */
+	char	g_padding[56];	/* pad out to 128 bytes */
+	nasid_t	g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
+						  * indexed by cnodeid.
+						  */
+} gda_t;
+
+#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
+
+#endif /* __LANGUAGE_C */
+/*
+ * Define:	PART_GDA_VERSION
+ * Purpose:	Define the minimum version of the GDA required, lower 
+ *		revisions assume GDA is NOT set up, and read partition
+ *		information from the board info.
+ */
+#define	PART_GDA_VERSION	2
+
+/*
+ * The following requests can be sent to the PROM during startup.
+ */
+
+#define PROMOP_MAGIC		0x0ead0000
+#define PROMOP_MAGIC_MASK	0x0fff0000
+
+#define PROMOP_BIST_SHIFT       11
+#define PROMOP_BIST_MASK        (0x3 << 11)
+
+#define PROMOP_REG		PI_ERR_STACK_ADDR_A
+
+#define PROMOP_INVALID		(PROMOP_MAGIC | 0x00)
+#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
+#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
+#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
+#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
+#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
+
+#define PROMOP_CMD_MASK		0x00f0
+#define PROMOP_OPTIONS_MASK	0xfff0
+
+#define PROMOP_SKIP_DIAGS	0x0100		/* don't bother running diags */
+#define PROMOP_SKIP_MEMINIT	0x0200		/* don't bother initing memory */
+#define PROMOP_SKIP_DEVINIT	0x0400		/* don't bother initing devices */
+#define PROMOP_BIST1		0x0800		/* keep track of which BIST ran */
+#define PROMOP_BIST2		0x1000		/* keep track of which BIST ran */
+
+#endif /* _ASM_SN_GDA_H */
diff --git a/include/asm-ia64/sn/hack.h b/include/asm-ia64/sn/hack.h
new file mode 100644
index 000000000..0f1006656
--- /dev/null
+++ b/include/asm-ia64/sn/hack.h
@@ -0,0 +1,92 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ */
+
+
+#ifndef _ASM_SN_HACK_H
+#define _ASM_SN_HACK_H
+
+#include <asm/sn/types.h>
+#include <asm/uaccess.h>		/* for copy_??_user */
+
+/******************************************
+ * Definitions that do not exist in linux *
+ ******************************************/
+
+typedef int cred_t;	/* This is for compilation reasons */
+struct cred { int x; };
+
+/*
+ * Hardware Graph routines that are currently stubbed!
+ */
+#include <linux/devfs_fs_kernel.h>
+
+#define DELAY(a)
+#define cpuid() 0
+
+/************************************************
+ * Routines redefined to use linux equivalents. *
+ ************************************************/
+
+#define FIXME(s) printk("FIXME: [ %s ] in %s at %s:%d\n", s, __FUNCTION__, __FILE__, __LINE__)
+
+#define sv_init(a,b,c)          FIXME("Fixme: sv_init : no-op")
+#define sv_wait(a,b,c,d)        FIXME("Fixme: sv_wait : no-op")
+#define sv_broadcast(a)  	FIXME("Fixme: sv_broadcast : no-op")
+#define sv_destroy(a)		FIXME("Fixme: sv_destroy : no-op")
+
+extern devfs_handle_t dummy_vrtx;
+#define cpuid_to_vertex(cpuid) dummy_vrtx /* (pdaindr[cpuid].pda->p_vertex) */
+
+#define PUTBUF_LOCK(a) { FIXME("PUTBUF_LOCK"); }
+#define PUTBUF_UNLOCK(a) { FIXME("PUTBUF_UNLOCK"); }
+static inline int sv_signal(sv_t *a) {FIXME("sv_signal : return 0"); return (0); }
+
+#define cmn_err(x,y...)         { FIXME("cmn_err : use printk"); printk(x y); }
+
+typedef int (*splfunc_t)(void);
+extern int badaddr_val(volatile void *, int , volatile void *);
+
+extern int cap_able_cred(uint64_t a, uint64_t b);
+
+#define _CAP_CRABLE(cr,c)	(cap_able_cred(cr,c))
+#define CAP_MEMORY_MGT          (0x01LL << 25)
+#define CAP_DEVICE_MGT          (0x01LL << 37)
+
+#define io_splock(l) l
+#define io_spunlock(l,s)
+
+/* move to stubs.c yet */
+#define spinlock_destroy(a)     /* needed by pcibr_detach() */
+#define mutex_spinlock(a) 0
+#define mutex_spinunlock(a,b)
+#define mutex_spinlock_spl(x,y) y
+#define mutex_init(a,b,c)               ;
+#define mutex_lock(a,b)                 ;
+#define mutex_unlock(a)                 ;
+#define dev_to_vhdl(dev) 0
+#define get_timestamp() 0
+#define us_delay(a)
+#define v_mapphys(a,b,c) printk("Fixme: v_mapphys - soft->base 0x%p\n", b);
+#define splhi()  0
+#define spl7	splhi()
+#define splx(s)
+#define spinlock_init(x,name) mutex_init(x, MUTEX_DEFAULT, name);
+
+extern void * kmem_alloc_node(register size_t, register int, cnodeid_t);
+extern void * kmem_zalloc(size_t, int);
+extern void * kmem_zalloc_node(register size_t, register int, cnodeid_t );
+extern void * kmem_zone_alloc(register zone_t *, int);
+extern zone_t * kmem_zone_init(register int , char *);
+extern void kmem_zone_free(register zone_t *, void *);
+extern int is_specified(char *);
+extern int cap_able(uint64_t);
+extern int compare_and_swap_ptr(void **, void *, void *);
+
+#endif	/* _ASM_SN_HACK_H */
diff --git a/include/asm-ia64/sn/hcl.h b/include/asm-ia64/sn/hcl.h
new file mode 100644
index 000000000..b3117aad5
--- /dev/null
+++ b/include/asm-ia64/sn/hcl.h
@@ -0,0 +1,114 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_HCL_H
+#define _ASM_SN_HCL_H
+
+extern spinlock_t hcl_spinlock;
+extern devfs_handle_t hcl_handle; /* HCL driver */
+extern devfs_handle_t hwgraph_root;
+
+
+typedef long            labelcl_info_place_t;
+typedef long            arbitrary_info_t;
+typedef long            arb_info_desc_t;
+
+/* Support for INVENTORY */
+struct inventory_s;
+struct invplace_s;
+extern struct invplace_s invplace_none;
+
+
+/* 
+ * Reserve room in every vertex for 2 pieces of fast access indexed information 
+ * Note that we do not save a pointer to the bdevsw or cdevsw[] tables anymore.
+ */
+#define HWGRAPH_NUM_INDEX_INFO	2	/* MAX Entries */
+#define HWGRAPH_CONNECTPT	0	/* connect point (aprent) */
+#define HWGRAPH_FASTINFO	1	/* callee's private handle */
+
+/*
+ * Reserved edge_place_t values, used as the "place" parameter to edge_get_next.
+ * Every vertex in the hwgraph has up to 2 *implicit* edges.  There is an implicit
+ * edge called "." that points to the current vertex.  There is an implicit edge
+ * called ".." that points to the vertex' connect point.
+ */
+#define EDGE_PLACE_WANT_CURRENT 0	/* "." */
+#define EDGE_PLACE_WANT_CONNECTPT 1	/* ".." */
+#define EDGE_PLACE_WANT_REAL_EDGES 2	/* Get the first real edge */
+#define HWGRAPH_RESERVED_PLACES 2
+
+
+/*
+ * Special pre-defined edge labels.
+ */
+#define HWGRAPH_EDGELBL_HW 	"hw"
+#define HWGRAPH_EDGELBL_DOT 	"."
+#define HWGRAPH_EDGELBL_DOTDOT 	".."
+#define graph_edge_place_t uint
+
+/*
+ * External declarations of EXPORTED SYMBOLS in hcl.c
+ */
+extern devfs_handle_t hwgraph_register(devfs_handle_t, const char *,
+	unsigned int, unsigned int, unsigned int, unsigned int,
+	umode_t, uid_t, gid_t, struct file_operations *, void *);
+
+extern int hwgraph_mk_symlink(devfs_handle_t, const char *, unsigned int,
+	unsigned int, const char *, unsigned int, devfs_handle_t *, void *);
+
+extern int hwgraph_vertex_destroy(devfs_handle_t);
+
+extern int hwgraph_edge_add(devfs_handle_t, devfs_handle_t, char *);
+extern int hwgraph_edge_get(devfs_handle_t, char *, devfs_handle_t *);
+
+extern arbitrary_info_t hwgraph_fastinfo_get(devfs_handle_t);
+extern void hwgraph_fastinfo_set(devfs_handle_t, arbitrary_info_t );
+extern devfs_handle_t hwgraph_mk_dir(devfs_handle_t, const char *, unsigned int, void *);
+
+extern int hwgraph_connectpt_set(devfs_handle_t, devfs_handle_t);
+extern devfs_handle_t hwgraph_connectpt_get(devfs_handle_t);
+extern int hwgraph_edge_get_next(devfs_handle_t, char *, devfs_handle_t *, uint *);
+extern graph_error_t hwgraph_edge_remove(devfs_handle_t, char *, devfs_handle_t *);
+
+extern graph_error_t hwgraph_traverse(devfs_handle_t, char *, devfs_handle_t *);
+
+extern int hwgraph_vertex_get_next(devfs_handle_t *, devfs_handle_t *);
+extern int hwgraph_inventory_get_next(devfs_handle_t, invplace_t *, 
+				      inventory_t **);
+extern int hwgraph_inventory_add(devfs_handle_t, int, int, major_t, minor_t, int);
+extern int hwgraph_inventory_remove(devfs_handle_t, int, int, major_t, minor_t, int);
+extern int hwgraph_controller_num_get(devfs_handle_t);
+extern void hwgraph_controller_num_set(devfs_handle_t, int);
+extern int hwgraph_path_ad(devfs_handle_t, char *, devfs_handle_t *);
+extern devfs_handle_t hwgraph_path_to_vertex(char *);
+extern devfs_handle_t hwgraph_path_to_dev(char *);
+extern devfs_handle_t hwgraph_block_device_get(devfs_handle_t);
+extern devfs_handle_t hwgraph_char_device_get(devfs_handle_t);
+extern graph_error_t hwgraph_char_device_add(devfs_handle_t, char *, char *, devfs_handle_t *);
+extern int hwgraph_path_add(devfs_handle_t, char *, devfs_handle_t *);
+extern struct file_operations * hwgraph_bdevsw_get(devfs_handle_t);
+extern int hwgraph_info_add_LBL(devfs_handle_t, char *, arbitrary_info_t);
+extern int hwgraph_info_get_LBL(devfs_handle_t, char *, arbitrary_info_t *);
+extern int hwgraph_info_replace_LBL(devfs_handle_t, char *, arbitrary_info_t,
+				    arbitrary_info_t *);
+extern int hwgraph_info_get_exported_LBL(devfs_handle_t, char *, int *, arbitrary_info_t *);
+extern int hwgraph_info_get_next_LBL(devfs_handle_t, char *, arbitrary_info_t *,
+                                labelcl_info_place_t *);
+
+extern int hwgraph_path_lookup(devfs_handle_t, char *, devfs_handle_t *, char **);
+extern int hwgraph_info_export_LBL(devfs_handle_t, char *, int);
+extern int hwgraph_info_unexport_LBL(devfs_handle_t, char *);
+extern int hwgraph_info_remove_LBL(devfs_handle_t, char *, arbitrary_info_t *);
+extern char * vertex_to_name(devfs_handle_t, char *, uint);
+extern graph_error_t hwgraph_vertex_unref(devfs_handle_t);
+
+
+
+#endif /* _ASM_SN_HCL_H */
diff --git a/include/asm-ia64/sn/hcl_util.h b/include/asm-ia64/sn/hcl_util.h
new file mode 100644
index 000000000..2c7794d2f
--- /dev/null
+++ b/include/asm-ia64/sn/hcl_util.h
@@ -0,0 +1,24 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_HCL_UTIL_H
+#define _ASM_SN_HCL_UTIL_H
+
+extern char * dev_to_name(devfs_handle_t, char *, uint);
+extern int device_master_set(devfs_handle_t, devfs_handle_t);
+extern devfs_handle_t device_master_get(devfs_handle_t);
+extern cnodeid_t master_node_get(devfs_handle_t);
+extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t);
+extern void mark_nodevertex_as_node(devfs_handle_t, cnodeid_t);
+extern void device_info_set(devfs_handle_t, void *);
+extern void *device_info_get(devfs_handle_t);
+
+
+#endif _ASM_SN_HCL_UTIL_H
diff --git a/include/asm-ia64/sn/hubspc.h b/include/asm-ia64/sn/hubspc.h
new file mode 100644
index 000000000..9241ab516
--- /dev/null
+++ b/include/asm-ia64/sn/hubspc.h
@@ -0,0 +1,25 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_HUBSPC_H
+#define _ASM_SN_HUBSPC_H
+
+typedef enum {
+        HUBSPC_REFCOUNTERS,
+	HUBSPC_PROM
+} hubspc_subdevice_t;
+
+
+/*
+ * Reference Counters
+ */
+
+extern int refcounters_attach(devfs_handle_t hub);
+
+#endif /* _ASM_SN_HUBSPC_H */        
diff --git a/include/asm-ia64/sn/hwcntrs.h b/include/asm-ia64/sn/hwcntrs.h
new file mode 100644
index 000000000..a3e35561d
--- /dev/null
+++ b/include/asm-ia64/sn/hwcntrs.h
@@ -0,0 +1,98 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_HWCNTRS_H
+#define _ASM_SN_HWCNTRS_H
+
+
+typedef  uint64_t refcnt_t;
+
+#define SN0_REFCNT_MAX_COUNTERS 64
+
+typedef struct sn0_refcnt_set {
+	refcnt_t    refcnt[SN0_REFCNT_MAX_COUNTERS];
+        uint64_t  flags;
+        uint64_t  reserved[4];
+} sn0_refcnt_set_t;
+
+typedef struct sn0_refcnt_buf {
+	sn0_refcnt_set_t   refcnt_set;
+	uint64_t         paddr;
+        uint64_t         page_size;
+        cnodeid_t          cnodeid;         /* cnodeid + pad[3] use 64 bits */
+        uint16_t           pad[3];
+        uint64_t         reserved[4];
+} sn0_refcnt_buf_t;
+
+typedef struct sn0_refcnt_args {
+	uint64_t          vaddr;
+	uint64_t          len;
+	sn0_refcnt_buf_t*   buf;
+        uint64_t          reserved[4];
+} sn0_refcnt_args_t;
+
+/*
+ * Info needed by the user level program
+ * to mmap the refcnt buffer
+ */
+
+#define RCB_INFO_GET  1
+#define RCB_SLOT_GET  2
+
+typedef struct rcb_info {
+        uint64_t  rcb_len;                  /* total refcnt buffer len in bytes */
+
+        int         rcb_sw_sets;              /* number of sw counter sets in buffer */
+        int         rcb_sw_counters_per_set;  /* sw counters per set -- numnodes */
+        int         rcb_sw_counter_size;      /* sizeof(refcnt_t) -- size of sw cntr */
+
+        int         rcb_base_pages;           /* number of base pages in node */
+        int         rcb_base_page_size;       /* sw base page size */        
+        uint64_t  rcb_base_paddr;           /* base physical address for this node */
+
+        int         rcb_cnodeid;              /* cnodeid for this node */
+        int         rcb_granularity;          /* hw page size used for counter sets */
+        uint        rcb_hw_counter_max;       /* max hwcounter count (width mask) */
+        int         rcb_diff_threshold;       /* current node differential threshold */
+        int         rcb_abs_threshold;        /* current node absolute threshold */
+        int         rcb_num_slots;            /* physmem slots */
+        
+        int         rcb_reserved[512];
+        
+} rcb_info_t;
+
+typedef struct rcb_slot {
+        uint64_t  base;
+        uint64_t  size;
+} rcb_slot_t;
+
+#if defined(__KERNEL__)
+// #include <sys/immu.h>
+typedef struct sn0_refcnt_args_32 {
+	uint64_t    vaddr;
+	uint64_t    len;
+	app32_ptr_t   buf;
+        uint64_t    reserved[4];
+} sn0_refcnt_args_32_t;
+
+/* Defines and Macros  */
+/* A set of reference counts are for 4k bytes of physical memory */
+#define	NBPREFCNTP	0x1000	
+#define	BPREFCNTPSHIFT	12
+#define bytes_to_refcntpages(x)	(((__psunsigned_t)(x)+(NBPREFCNTP-1))>>BPREFCNTPSHIFT)
+#define refcntpage_offset(x)	((__psunsigned_t)(x)&((NBPP-1)&~(NBPREFCNTP-1)))
+#define align_to_refcntpage(x)	((__psunsigned_t)(x)&(~(NBPREFCNTP-1)))
+
+extern void migr_refcnt_read(sn0_refcnt_buf_t*);
+extern void migr_refcnt_read_extended(sn0_refcnt_buf_t*);
+extern int migr_refcnt_enabled(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SN_HWCNTRS_H */
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
new file mode 100644
index 000000000..f08594321
--- /dev/null
+++ b/include/asm-ia64/sn/intr.h
@@ -0,0 +1,251 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_INTR_H
+#define _ASM_SN_INTR_H
+
+/* Number of interrupt levels associated with each interrupt register. */
+#define N_INTPEND_BITS		64
+
+#define INT_PEND0_BASELVL	0
+#define INT_PEND1_BASELVL	64
+
+#define	N_INTPENDJUNK_BITS	8
+#define	INTPENDJUNK_CLRBIT	0x80
+
+#include <linux/config.h>
+#include <asm/sn/intr_public.h>
+
+#if LANGUAGE_C
+
+#if defined(CONFIG_IA64_SGI_IO)
+
+#define II_NAMELEN	24
+
+/*
+ * Dispatch table entry - contains information needed to call an interrupt
+ * routine.
+ */
+typedef struct intr_vector_s {
+	intr_func_t	iv_func;	/* Interrupt handler function */
+	intr_func_t	iv_prefunc;	/* Interrupt handler prologue func */
+	void		*iv_arg;	/* Argument to pass to handler */
+#ifdef IRIX
+	thd_int_t		iv_tinfo;	/* Thread info */
+#endif
+	cpuid_t			iv_mustruncpu;	/* Where we must run. */
+} intr_vector_t;
+
+/* Interrupt information table. */
+typedef struct intr_info_s {
+	xtalk_intr_setfunc_t	ii_setfunc;	/* Function to set the interrupt
+						 * destination and level register.
+						 * It returns 0 (success) or an
+						 * error code.
+						 */
+	void			*ii_cookie;	/* arg passed to setfunc */
+	devfs_handle_t		ii_owner_dev;	/* device that owns this intr */
+	char			ii_name[II_NAMELEN];	/* Name of this intr. */
+	int			ii_flags;	/* informational flags */
+} intr_info_t;
+
+#define iv_tflags	iv_tinfo.thd_flags
+#define iv_isync	iv_tinfo.thd_isync
+#define iv_lat		iv_tinfo.thd_latstats
+#define iv_thread	iv_tinfo.thd_ithread
+#define iv_pri		iv_tinfo.thd_pri
+
+#define THD_CREATED	0x00000001	/*
+					 * We've created a thread for this
+					 * interrupt.
+					 */
+
+/*
+ * Bits for ii_flags:
+ */
+#define II_UNRESERVE	0
+#define II_RESERVE	1		/* Interrupt reserved. 			*/
+#define II_INUSE	2		/* Interrupt connected 			*/
+#define II_ERRORINT	4		/* INterrupt is an error condition 	*/
+#define II_THREADED	8		/* Interrupt handler is threaded.	*/
+
+/*
+ * Interrupt level wildcard
+ */
+#define INTRCONNECT_ANYBIT	-1
+
+/*
+ * This structure holds information needed both to call and to maintain
+ * interrupts.  The two are in separate arrays for the locality benefits.
+ * Since there's only one set of vectors per hub chip (but more than one
+ * CPU, the lock to change the vector tables must be here rather than in
+ * the PDA.
+ */
+
+typedef struct intr_vecblk_s {
+	intr_vector_t	vectors[N_INTPEND_BITS];  /* information needed to
+						     call an intr routine. */
+	intr_info_t	info[N_INTPEND_BITS];	  /* information needed only
+						     to maintain interrupts. */
+	lock_t		vector_lock;		  /* Lock for this and the
+						     masks in the PDA. */
+	splfunc_t	vector_spl;		  /* vector_lock req'd spl */
+	int		vector_state;		  /* Initialized to zero.
+						     Set to INTR_INITED
+						     by hubintr_init.
+						   */
+	int		vector_count;		  /* Number of vectors
+						   * reserved.
+						   */
+	int		cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are
+						   * connected to each CPU
+						   */
+	int		ithreads_enabled;	  /* Are interrupt threads
+						   * initialized on this node.
+						   * and block?
+						   */
+} intr_vecblk_t;
+
+/* Possible values for vector_state: */
+#define VECTOR_UNINITED	0
+#define VECTOR_INITED	1
+#define VECTOR_SET	2
+
+#define hub_intrvect0	private.p_intmasks.dispatch0->vectors
+#define hub_intrvect1	private.p_intmasks.dispatch1->vectors
+#define hub_intrinfo0	private.p_intmasks.dispatch0->info
+#define hub_intrinfo1	private.p_intmasks.dispatch1->info
+
+#endif	/* CONFIG_IA64_SGI_IO */
+
+/*
+ * Macros to manipulate the interrupt register on the calling hub chip.
+ */
+
+#define LOCAL_HUB_SEND_INTR(_level)	LOCAL_HUB_S(PI_INT_PEND_MOD, \
+						    (0x100|(_level)))
+#if defined(CONFIG_IA64_SGI_IO)
+#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \
+		REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level)))
+
+#define REMOTE_CPU_SEND_INTR(_cpuid, _level) 					\
+		REMOTE_HUB_PI_S(cputonasid(_cpuid),				\
+			SUBNODE(cputoslice(_cpuid)),				\
+			PI_INT_PEND_MOD, (0x100|(_level)))
+#endif	/* CONFIG_IA64_SGI_IO*/
+
+/*
+ * When clearing the interrupt, make sure this clear does make it 
+ * to the hub. Otherwise we could end up losing interrupts.
+ * We do an uncached load of the int_pend0 register to ensure this.
+ */
+
+#define LOCAL_HUB_CLR_INTR(_level)	  \
+                LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)),	\
+                LOCAL_HUB_L(PI_INT_PEND0)
+#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \
+		REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)),	\
+                REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0)
+
+#if defined(CONFIG_IA64_SGI_IO)
+/* Special support for use by gfx driver only.  Supports special gfx hub interrupt. */
+extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg);
+
+void setrtvector(intr_func_t func);
+
+/*
+ * Interrupt blocking
+ */
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+#endif	/* CONFIG_IA64_SGI_IO */
+
+#endif /* LANGUAGE_C */
+
+/*
+ * Hard-coded interrupt levels:
+ */
+
+/*
+ *	L0 = SW1
+ *	L1 = SW2
+ *	L2 = INT_PEND0
+ *	L3 = INT_PEND1
+ *	L4 = RTC
+ *	L5 = Profiling Timer
+ *	L6 = Hub Errors
+ *	L7 = Count/Compare (T5 counters)
+ */
+
+
+/* INT_PEND0 hard-coded bits. */
+#ifdef DEBUG_INTR_TSTAMP
+/* hard coded interrupt level for interrupt latency test interrupt */
+#define	CPU_INTRLAT_B	62
+#define	CPU_INTRLAT_A	61
+#endif
+
+/* Hardcoded bits required by software. */
+#define MSC_MESG_INTR	9
+#define CPU_ACTION_B	8
+#define CPU_ACTION_A	7
+
+/* These are determined by hardware: */
+#define CC_PEND_B	6
+#define CC_PEND_A	5
+#define UART_INTR	4
+#define PG_MIG_INTR	3
+#define GFX_INTR_B	2
+#define GFX_INTR_A	1
+#define RESERVED_INTR	0
+
+/* INT_PEND1 hard-coded bits: */
+#define MSC_PANIC_INTR	63
+#define NI_ERROR_INTR	62
+#define MD_COR_ERR_INTR	61
+#define COR_ERR_INTR_B	60
+#define COR_ERR_INTR_A	59
+#define CLK_ERR_INTR	58
+
+#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+# define NACK_INT_B	57
+# define NACK_INT_A	56
+# define LB_ERROR	55
+# define XB_ERROR	54
+#else
+	<< BOMB! >>  Must define IP27 or IP35 or IP37
+#endif
+
+#define BRIDGE_ERROR_INTR 53	/* Setup by PROM to catch Bridge Errors */
+
+#define IP27_INTR_0	52	/* Reserved for PROM use */
+#define IP27_INTR_1	51	/*   (do not use in Kernel) */
+#define IP27_INTR_2	50
+#define IP27_INTR_3	49
+#define IP27_INTR_4	48
+#define IP27_INTR_5	47
+#define IP27_INTR_6	46
+#define IP27_INTR_7	45
+
+#define	TLB_INTR_B	44	/* used for tlb flush random */
+#define	TLB_INTR_A	43
+
+#define LLP_PFAIL_INTR_B 42	/* see ml/SN/SN0/sysctlr.c */
+#define LLP_PFAIL_INTR_A 41
+
+#define NI_BRDCAST_ERR_B 40
+#define NI_BRDCAST_ERR_A 39
+
+#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+# define IO_ERROR_INTR	38	/* set up by prom */
+# define DEBUG_INTR_B	37	/* used by symmon to stop all cpus */
+# define DEBUG_INTR_A	36
+#endif
+
+#endif /* _ASM_SN_INTR_H */
diff --git a/include/asm-ia64/sn/intr_public.h b/include/asm-ia64/sn/intr_public.h
new file mode 100644
index 000000000..7ae569d10
--- /dev/null
+++ b/include/asm-ia64/sn/intr_public.h
@@ -0,0 +1,60 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef __SYS_SN_INTR_PUBLIC_H__
+#define __SYS_SN_INTR_PUBLIC_H__
+
+
+/* REMEMBER: If you change these, the whole world needs to be recompiled.
+ * It would also require changing the hubspl.s code and SN0/intr.c
+ * Currently, the spl code has no support for multiple INTPEND1 masks.
+ */
+
+#define	N_INTPEND0_MASKS	1
+#define	N_INTPEND1_MASKS	1
+
+#define INTPEND0_MAXMASK	(N_INTPEND0_MASKS - 1)
+#define INTPEND1_MAXMASK	(N_INTPEND1_MASKS - 1)
+
+#include <linux/config.h>
+#if _LANGUAGE_C
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/arch.h>
+#endif
+#include <asm/sn/arch.h>
+
+struct intr_vecblk_s;	/* defined in asm/sn/intr.h */
+
+/*
+ * The following are necessary to create the illusion of a CEL
+ * on the IP27 hub.  We'll add more priority levels soon, but for
+ * now, any interrupt in a particular band effectively does an spl.
+ * These must be in the PDA since they're different for each processor.
+ * Users of this structure must hold the vector_lock in the appropriate vector
+ * block before modifying the mask arrays.  There's only one vector block
+ * for each Hub so a lock in the PDA wouldn't be adequate.
+ */
+typedef struct hub_intmasks_s {
+	/*
+	 * The masks are stored with the lowest-priority (most inclusive)
+	 * in the lowest-numbered masks (i.e., 0, 1, 2...).
+	 */
+	/* INT_PEND0: */
+	hubreg_t		intpend0_masks[N_INTPEND0_MASKS]; 
+	/* INT_PEND1: */
+	hubreg_t		intpend1_masks[N_INTPEND1_MASKS];
+	/* INT_PEND0: */
+	struct intr_vecblk_s	*dispatch0;	
+	/* INT_PEND1: */
+	struct intr_vecblk_s	*dispatch1;
+} hub_intmasks_t;
+
+#endif /* _LANGUAGE_C */
+#endif /* __SYS_SN_INTR_PUBLIC_H__ */
+
diff --git a/include/asm-ia64/sn/invent.h b/include/asm-ia64/sn/invent.h
new file mode 100644
index 000000000..b5708da8e
--- /dev/null
+++ b/include/asm-ia64/sn/invent.h
@@ -0,0 +1,684 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_INVENT_H
+#define _ASM_SN_INVENT_H
+
+/*
+ * sys/sn/invent.h --  Kernel Hardware Inventory
+ *
+ * As the system boots, a list of recognized devices is assembled.
+ * This list can then be accessed through syssgi() by user-level programs
+ * so that they can learn about available peripherals and the system's
+ * hardware configuration.
+ *
+ * The data is organized into a linked list of structures that are composed
+ * of an inventory item class and a class-specific type.  Each instance may
+ * also specify a 32-bit "state" which might be size, readiness, or
+ * anything else that's relevant.
+ *
+ */
+
+#define major_t int
+#define minor_t int
+#define app32_ptr_t unsigned long
+#define graph_vertex_place_t long
+#define GRAPH_VERTEX_NONE ((devfs_handle_t)-1)
+
+typedef struct inventory_s {
+	struct	inventory_s *inv_next;	/* next inventory record in list */
+	int	inv_class;		/* class of object */
+	int	inv_type;		/* class sub-type of object */
+	major_t	inv_controller;		/* object major identifier */
+	minor_t	inv_unit;		/* object minor identifier */
+	int	inv_state;		/* information specific to object or
+					   class */
+} inventory_t;
+
+typedef struct cpu_inv_s {
+	int	cpuflavor;	/* differentiate processor */
+	int	cpufq;		/* cpu frequency */
+	int	sdsize;		/* secondary data cache size */
+	int	sdfreq;		/* speed of the secondary cache */
+} cpu_inv_t;
+
+
+typedef struct diag_inv_s{
+         char name[80];
+         int  diagval;
+         int  physid;
+         int  virtid;
+} diag_inv_t;
+
+
+typedef struct router_inv_s{
+  char portmap[80];             /* String indicating which ports int/ext */
+  char type[40];                /* String name: e.g. "star", "meta", etc. */
+  int  freq;                    /* From hub */
+  int  rev;                     /* From hub */
+} router_inv_t;
+
+
+/*
+ * NOTE: This file is a central registry for inventory IDs for each
+ *       class of inventory object.  It is important to keep the central copy
+ *       of this file up-to-date with the work going on in various engineering
+ *       projects.  When making changes to this file in an engineering project
+ *       tree, please make those changes separately from any others and then
+ *       merge the changes to this file into the main line trees in order to
+ *       prevent other engineering projects from conflicting with your ID
+ *       allocations.
+ */
+
+
+/* Inventory Classes */
+/* when adding a new class, add also to classes[] in hinv.c */
+#define INV_PROCESSOR	1
+#define INV_DISK	2
+#define INV_MEMORY	3
+#define INV_SERIAL	4
+#define INV_PARALLEL	5
+#define INV_TAPE	6
+#define INV_GRAPHICS	7
+#define INV_NETWORK	8
+#define INV_SCSI	9	/* SCSI devices other than disk and tape */
+#define INV_AUDIO	10
+#define	INV_IOBD	11
+#define	INV_VIDEO	12
+#define	INV_BUS		13
+#define	INV_MISC	14	/* miscellaneous: a catchall */
+/*** add post-5.2 classes here for backward compatibility ***/
+#define	INV_COMPRESSION	15
+#define	INV_VSCSI	16	/* SCSI devices on jag other than disk and tape */
+#define	INV_DISPLAY     17
+#define	INV_UNC_SCSILUN	18	/* Unconnected SCSI lun */
+#define	INV_PCI		19	/* PCI Bus */
+#define	INV_PCI_NO_DRV	20	/* PCI Bus without any driver */
+#define	INV_PROM	21	/* Different proms in the system */
+#define INV_IEEE1394	22	/* IEEE1394 devices */
+#define INV_RPS		23      /* redundant power source */
+#define INV_TPU		24	/* Tensor Processing Unit */
+#define INV_FCNODE	25	/* Helper class for SCSI classes, not in classes[] */
+
+/* types for class processor */
+#define INV_CPUBOARD	1
+#define INV_CPUCHIP	2
+#define INV_FPUCHIP	3
+#define INV_CCSYNC	4	/* CC Rev 2+ sync join counter */
+
+/* states for cpu and fpu chips are revision numbers */
+
+/* cpuboard states */
+#define INV_IP20BOARD   10
+#define INV_IP19BOARD   11
+#define INV_IP22BOARD   12
+#define INV_IP21BOARD	13
+#define INV_IP26BOARD	14
+#define INV_IP25BOARD	15
+#define INV_IP30BOARD	16
+#define INV_IP28BOARD	17
+#define INV_IP32BOARD	18
+#define INV_IP27BOARD	19
+#define INV_IPMHSIMBOARD 20
+#define INV_IP33BOARD	21
+#define INV_IP35BOARD	22
+
+/* types for class INV_IOBD */
+#define INV_EVIO	2	/* EVEREST I/O board */
+#define INV_O200IO	3	/* Origin 200 base I/O */
+
+/* IO board types for origin2000  for class INV_IOBD*/
+
+#define INV_O2000BASEIO	0x21	
+#define INV_O2000MSCSI	0x22	
+#define INV_O2000MENET	0x23
+#define INV_O2000HIPPI	0x24
+#define INV_O2000GFX	0x25	
+#define INV_O2000HAROLD 0x26
+#define INV_O2000VME	0x27
+#define INV_O2000MIO	0x28
+#define INV_O2000FC	0x29
+#define INV_O2000LINC	0x2a
+
+#define INV_PCIADAP	4
+/* states for class INV_IOBD type INV_EVERESTIO -- value of eb_type field */
+#define INV_IO4_REV1	0x21	
+
+/* types for class disk */
+/* NB: types MUST be unique within a class.
+   Please check this if adding new types. */
+
+#define INV_SCSICONTROL	1
+#define INV_SCSIDRIVE	2
+#define INV_SCSIFLOPPY	5	/* also cdroms, optical disks, etc. */
+#define INV_JAGUAR	16	/* Interphase Jaguar */
+#define INV_VSCSIDRIVE	17	/* Disk connected to Jaguar */
+#define INV_GIO_SCSICONTROL 18	/* optional GIO SCSI controller */
+#define INV_SCSIRAID	19	/* SCSI attached RAID */
+#define INV_XLVGEN      20	/* Generic XLV disk device */
+#define INV_PCCARD	21	/* PC-card (PCMCIA) devices */
+#define INV_PCI_SCSICONTROL	22   /* optional PCI SCSI controller */
+
+/* states for INV_SCSICONTROL disk type; indicate which chip rev;
+ * for 93A and B, unit field has microcode rev. */
+#define INV_WD93	0	/* WD 33C93  */
+#define INV_WD93A	1	/* WD 33C93A */
+#define INV_WD93B	2	/* WD 33C93B */
+#define INV_WD95A	3	/* WD 33C95A */
+#define INV_SCIP95	4       /* SCIP with a WD 33C95A */
+#define INV_ADP7880	5	/* Adaptec 7880 (single channel) */
+#define INV_QL_REV1     6       /* qlogic 1040  */
+#define INV_QL_REV2     7       /* qlogic 1040A */
+#define INV_QL_REV2_4   8       /* qlogic 1040A rev 4 */
+#define INV_QL_REV3     9       /* qlogic 1040B */
+#define INV_FCADP	10	/* Adaptec Emerald Fibrechannel */
+#define INV_QL_REV4     11      /* qlogic 1040B rev 2 */
+#define INV_QL		12	/* Unknown QL version */	
+#define INV_QL_1240     13      /* qlogic 1240 */
+#define INV_QL_1080     14      /* qlogic 1080 */
+#define INV_QL_1280     15      /* qlogic 1280 */
+#define INV_QL_10160    16      /* qlogic 10160 */
+#define INV_QL_12160    17      /* qlogic 12160 */
+#define INV_QL_2100	18	/* qLogic 2100 Fibrechannel */
+#define INV_QL_2200	19	/* qLogic 2200 Fibrechannel */
+#define INV_SBP2	20	/* SBP2 protocol over OHCI on 1394 */
+
+
+
+/* states for INV_SCSIDRIVE type of class disk */
+#define INV_RAID5_LUN	0x100
+#define INV_PRIMARY	0x200	/* primary path */
+#define INV_ALTERNATE	0x400	/* alternate path */
+#define INV_FAILED	0x800	/* path has failed */
+#define INV_XVMVOL	0x1000	/* disk is managed by XVM */
+
+/* states for INV_SCSIFLOPPY type of class disk */
+#define INV_TEAC_FLOPPY 1       /* TEAC 3 1/2 inch floppy drive */
+#define INV_INSITE_FLOPPY 2     /* INSITE, IOMEGA  Io20S, SyQuest floppy drives */
+
+/* END OF CLASS DISK TYPES */
+
+/* types for class memory */
+/* NB. the states for class memory are sizes in bytes */
+#define INV_MAIN	1
+#define INV_DCACHE	3
+#define INV_ICACHE	4
+#define INV_WBUFFER	5
+#define INV_SDCACHE	6
+#define INV_SICACHE	7
+#define INV_SIDCACHE	8
+#define INV_MAIN_MB	9
+#define INV_HUBSPC      10      /* HUBSPC */
+
+/* types for class serial */
+#define INV_CDSIO	1	/* Central Data serial board */
+#define INV_T3270	2	/* T3270 emulation */
+#define INV_GSE		3	/* SpectraGraphics Gerbil coax cable */
+#define INV_SI		4	/* SNA SDLC controller */
+#define	INV_M333X25 	6	/* X.25 controller */
+#define INV_CDSIO_E	7	/* Central Data serial board on E space */
+#define INV_ONBOARD	8	/* Serial ports per CPU board */
+#define INV_EPC_SERIAL	9	/* EVEREST I/O EPC serial port */
+#define INV_ICA		10	/* IRIS (IBM) Channel Adapter card */
+#define INV_VSC		11	/* SBE VME Synch Comm board */
+#define INV_ISC		12	/* SBE ISA Synch Comm board */
+#define INV_GSC		13	/* SGI GIO Synch Comm board */
+#define INV_ASO_SERIAL	14	/* serial portion of SGI ASO board */
+#define INV_PSC		15	/* SBE PCI Synch Comm board */
+#define INV_IOC3_DMA	16	/* DMA mode IOC3 serial */
+#define INV_IOC3_PIO	17	/* PIO mode IOC3 serial */
+#define INV_INVISIBLE	18	/* invisible inventory entry for kernel use */
+#define INV_ISA_DMA	19	/* DMA mode ISA serial -- O2 */
+
+/* types for class parallel */
+#define INV_GPIB	2	/* National Instrument GPIB board */
+#define INV_GPIB_E	3	/* National Instrument GPIB board on E space*/
+#define INV_EPC_PLP	4	/* EVEREST I/O EPC Parallel Port */
+#define INV_ONBOARD_PLP	5	/* Integral parallel port,
+				      state = 0 -> output only
+				      state = 1 -> bi-directional */
+#define INV_EPP_ECP_PLP	6	/* Integral EPP/ECP parallel port */
+#define INV_EPP_PFD	7	/* External EPP parallel peripheral */
+
+/* types for class tape */
+#define INV_SCSIQIC	1	/* Any SCSI tape, not just QIC{24,150}... */
+#define INV_VSCSITAPE	4	/* SCSI tape connected to Jaguar */
+
+/* sub types for type INV_SCSIQIC and INV_VSCSITAPE (in state) */
+#define TPUNKNOWN	0	/* type not known */
+#define TPQIC24		1	/* QIC24 1/4" cartridge */
+#define TPDAT		2	/* 4mm Digital Audio Tape cartridge */
+#define TPQIC150	3	/* QIC150 1/4" cartridge */
+#define TP9TRACK	4	/* 9 track reel */
+#define TP8MM_8200	5	/* 8 mm video tape cartridge */
+#define TP8MM_8500	6	/* 8 mm video tape cartridge */
+#define TPQIC1000	7	/* QIC1000 1/4" cartridge */
+#define TPQIC1350	8	/* QIC1350 1/4" cartridge */
+#define TP3480		9	/* 3480 compatible cartridge */
+#define TPDLT		10	/* DEC Digital Linear Tape cartridge */
+#define TPD2		11	/* D2 tape cartridge */
+#define TPDLTSTACKER	12	/* DEC Digital Linear Tape stacker */
+#define TPNTP		13	/* IBM Magstar 3590 Tape Device cartridge */
+#define TPNTPSTACKER	14	/* IBM Magstar 3590 Tape Device stacker */
+#define TPSTK9490       15      /* StorageTeK 9490 */
+#define TPSTKSD3        16      /* StorageTeK SD3 */
+#define TPGY10	        17      /* Sony GY-10  */
+#define TP8MM_8900	18	/* 8 mm (AME) tape cartridge */
+#define TPMGSTRMP       19      /* IBM Magster MP 3570 cartridge */
+#define TPMGSTRMPSTCKR  20      /* IBM Magstar MP stacker */
+#define TPSTK4791       21      /* StorageTek 4791 */
+#define TPSTK4781       22      /* StorageTek 4781 */
+#define TPFUJDIANA1     23      /* Fujitsu Diana-1 (M1016/M1017) */
+#define TPFUJDIANA2     24      /* Fujitsu Diana-2 (M2483) */
+#define TPFUJDIANA3     25      /* Fujitsu Diana-3 (M2488) */
+#define TP8MM_AIT	26	/* Sony AIT format tape */
+#define TPTD3600        27      /* Philips TD3600  */
+#define TPTD3600STCKR   28      /* Philips TD3600  stacker */
+#define TPNCTP          29      /* Philips NCTP */
+#define TPGY2120        30      /* Sony GY-2120 (replaces GY-10)  */
+#define TPOVL490E       31      /* Overland Data L490E (3490E compatible) */
+#define TPSTK9840       32      /* StorageTeK 9840 (aka Eagle) */
+
+/* Diagnostics inventory */
+#define INV_CPUDIAGVAL  70
+
+
+/*
+ *  GFX invent is a subset of gfxinfo
+ */
+
+/* types for class graphics */
+#define INV_GR1BOARD	1	/* GR1 (Eclipse) graphics */
+#define INV_GR1BP	2	/* OBSOLETE - use INV_GR1BIT24 instead */
+#define INV_GR1ZBUFFER	3	/* OBSOLETE - use INV_GR1ZBUF24 instead */
+#define INV_GRODEV	4	/* Clover1 graphics */
+#define INV_GMDEV	5	/* GT graphics */
+#define INV_CG2		6	/* CG2 composite video/genlock board */
+#define INV_VMUXBOARD	7	/* VMUX video mux board */
+#define	INV_VGX		8	/* VGX (PowerVision) graphics */
+#define	INV_VGXT	9	/* VGXT (PowerVision) graphics with IMP5s. */
+#define	INV_LIGHT	10	/* LIGHT graphics */
+#define INV_GR2		11	/* EXPRESS graphics */
+#define INV_RE		12	/* RealityEngine graphics */
+#define INV_VTX		13	/* RealityEngine graphics - VTX variant */
+#define INV_NEWPORT	14	/* Newport graphics */
+#define INV_MGRAS	15	/* Mardigras graphics */
+#define INV_IR		16	/* InfiniteReality graphics */
+#define INV_CRIME	17	/* Moosehead on board CRIME graphics */
+#define INV_IR2		18	/* InfiniteReality2 graphics */
+#define INV_IR2LITE	19	/* Reality graphics */
+#define INV_IR2E	20	/* InfiniteReality2e graphics */
+#define INV_ODSY        21      /* Odyssey graphics */
+#define INV_IR3		22	/* InfiniteReality3 graphics */
+
+/* states for graphics class GR1 */
+#define INV_GR1REMASK	0x7	/* RE version */
+#define INV_GR1REUNK	0x0	/* RE version unknown */
+#define INV_GR1RE1	0x1	/* RE1 */
+#define INV_GR1RE2	0x2	/* RE2 */
+#define INV_GR1BUSMASK	0x38	/* GR1 bus architecture */
+#define INV_GR1PB	0x00	/* Eclipse private bus */
+#define INV_GR1PBVME	0x08	/* VGR2 board VME and private bus interfaces */
+#define INV_GR1TURBO	0x40	/* has turbo option */
+#define INV_GR1BIT24  	0x80    /* has bitplane option */
+#define INV_GR1ZBUF24 	0x100   /* has z-buffer option */
+#define INV_GR1SMALLMON 0x200   /* using 14" monitor */
+#define INV_GR1SMALLMAP 0x400   /* has 256 entry color map */
+#define INV_GR1AUX4 	0x800   /* has AUX/WID plane option */
+
+/* states for graphics class GR2 */
+		/* bitmasks */
+#define INV_GR2_Z	0x1	/* has z-buffer option */
+#define INV_GR2_24	0x2	/* has bitplane option */
+#define INV_GR2_4GE     0x4     /* has 4 GEs */
+#define INV_GR2_1GE	0x8	/* has 1 GEs */
+#define INV_GR2_2GE	0x10	/* has 2 GEs */
+#define INV_GR2_8GE	0x20	/* has 8 GEs */
+#define INV_GR2_GR3	0x40	/* board GR3 */
+#define INV_GR2_GU1	0x80	/* board GU1 */
+#define INV_GR2_INDY    0x100   /* board GR3 on Indy*/
+#define INV_GR2_GR5	0x200	/* board GR3 with 4 GEs, hinv prints GR5-XZ */
+
+		/* supported configurations */
+#define INV_GR2_XS	0x0     /* GR2-XS */
+#define INV_GR2_XSZ	0x1     /* GR2-XS with z-buffer */
+#define INV_GR2_XS24	0x2     /* GR2-XS24 */
+#define INV_GR2_XS24Z	0x3     /* GR2-XS24 with z-buffer */
+#define INV_GR2_XSM	0x4     /* GR2-XSM */
+#define INV_GR2_ELAN	0x7	/* GR2-Elan */
+#define	INV_GR2_XZ	0x13	/* GR2-XZ */
+#define	INV_GR3_XSM	0x44	/* GR3-XSM */
+#define	INV_GR3_ELAN	0x47	/* GR3-Elan */
+#define	INV_GU1_EXTREME	0xa3	/* GU1-Extreme */
+
+/* States for graphics class NEWPORT */
+#define	INV_NEWPORT_XL	0x01	/* Indigo2 XL model */
+#define INV_NEWPORT_24	0x02	/* board has 24 bitplanes */
+#define INV_NEWTON      0x04    /* Triton SUBGR tagging */
+
+/* States for graphics class MGRAS */
+#define INV_MGRAS_ARCHS 0xff000000      /* architectures */
+#define INV_MGRAS_HQ3   0x00000000   /*impact*/
+#define INV_MGRAS_HQ4	0x01000000   /*gamera*/
+#define INV_MGRAS_MOT   0x02000000   /*mothra*/
+#define INV_MGRAS_GES	0x00ff0000	/* number of GEs */
+#define INV_MGRAS_1GE	0x00010000
+#define INV_MGRAS_2GE	0x00020000
+#define INV_MGRAS_RES	0x0000ff00	/* number of REs */
+#define INV_MGRAS_1RE	0x00000100
+#define INV_MGRAS_2RE	0x00000200
+#define INV_MGRAS_TRS	0x000000ff	/* number of TRAMs */
+#define INV_MGRAS_0TR	0x00000000
+#define INV_MGRAS_1TR	0x00000001
+#define INV_MGRAS_2TR	0x00000002
+
+/* States for graphics class CRIME */
+#define INV_CRM_BASE    0x01            /* Moosehead basic model */
+
+/* States for graphics class ODSY */
+#define INV_ODSY_ARCHS      0xff000000 /* architectures */
+#define INV_ODSY_REVA_ARCH  0x01000000 /* Buzz Rev A */
+#define INV_ODSY_REVB_ARCH  0x02000000 /* Buzz Rev B */
+#define INV_ODSY_MEMCFG     0x00ff0000 /* memory configs */
+#define INV_ODSY_MEMCFG_32  0x00010000 /* 32MB memory */
+#define INV_ODSY_MEMCFG_64  0x00020000 /* 64MB memory */
+#define INV_ODSY_MEMCFG_128 0x00030000 /* 128MB memory */
+#define INV_ODSY_MEMCFG_256 0x00040000 /* 256MB memory */
+#define INV_ODSY_MEMCFG_512 0x00050000 /* 512MB memory */
+
+
+/* types for class network */
+#define INV_NET_ETHER		0	/* 10Mb Ethernet */
+#define INV_NET_HYPER		1	/* HyperNet */
+#define	INV_NET_CRAYIOS		2	/* Cray Input/Ouput Subsystem */
+#define	INV_NET_FDDI		3	/* FDDI */
+#define INV_NET_TOKEN		4	/* 16/4 Token Ring */
+#define INV_NET_HIPPI		5	/* HIPPI */
+#define INV_NET_ATM		6	/* ATM */
+#define INV_NET_ISDN_BRI	7	/* ISDN */
+#define INV_NET_ISDN_PRI	8	/* PRI ISDN */
+#define INV_NET_HIPPIS		9	/* HIPPI-Serial */
+#define	INV_NET_GSN		10	/* GSN (aka HIPPI-6400) */
+
+/* controllers for network types, unique within class network */
+#define INV_ETHER_EC	0	/* IP6 integral controller */
+#define INV_ETHER_ENP	1	/* CMC board */
+#define INV_ETHER_ET	2	/* IP5 integral controller */
+#define INV_HYPER_HY	3	/* HyperNet controller */
+#define	INV_CRAYIOS_CFEI3 4	/* Cray Front End Interface, v3 */
+#define	INV_FDDI_IMF	5	/* Interphase/Martin 3211 FDDI */
+#define INV_ETHER_EGL	6	/* Interphase V/4207 Eagle */
+#define INV_ETHER_FXP	7	/* CMC C/130 FXP */
+#define INV_FDDI_IPG	8	/* Interphase/SGI 4211 Peregrine FDDI */
+#define INV_TOKEN_FV	9	/* Formation fv1600 Token-Ring board */
+#define INV_FDDI_XPI	10	/* XPI GIO bus FDDI */
+#define INV_TOKEN_GTR	11	/* GTR GIO bus TokenRing */
+#define INV_ETHER_GIO	12	/* IP12/20 optional GIO ethernet controller */
+#define INV_ETHER_EE	13	/* Everest IO4 EPC SEEQ/EDLC */
+#define INV_HIO_HIPPI	14	/* HIO HIPPI for Challenge/Onyx */
+#define INV_ATM_GIO64	15	/* ATM OC-3c Mez card */
+#define INV_ETHER_EP	16	/* 8-port E-Plex Ethernet */
+#define INV_ISDN_SM	17	/* Siemens PEB 2085 */
+#define INV_TOKEN_MTR	18	/* EISA TokenRing */
+#define INV_ETHER_EF	19	/* IOC3 Fast Ethernet */
+#define INV_ISDN_48XP	20	/* Xircom PRI-48XP */
+#define INV_FDDI_RNS	21	/* Rockwell Network Systems FDDI */
+#define INV_HIPPIS_XTK	22	/* Xtalk HIPPI-Serial */
+#define INV_ATM_QUADOC3	23	/* Xtalk Quad OC-3c ATM interface */
+#define INV_TOKEN_MTRPCI 24     /* PCI TokenRing */
+#define INV_ETHER_ECF	25	/* PCI Fast Ethernet */
+#define INV_GFE		26	/* GIO Fast Ethernet */
+#define INV_VFE		27	/* VME Fast Ethernet */
+#define	INV_ETHER_GE	28	/* Gigabit Ethernet */
+#define	INV_ETHER_EFP	INV_ETHER_EF	/* unused (same as IOC3 Fast Ethernet) */
+#define INV_GSN_XTK1	29	/* single xtalk version of GSN */
+#define INV_GSN_XTK2	30	/* dual xtalk version of GSN */
+#define INV_FORE_HE	31	/* FORE HE ATM Card */
+#define INV_FORE_PCA	32	/* FORE PCA ATM Card */
+#define INV_FORE_VMA    33      /* FORE VMA ATM Card */
+#define INV_FORE_ESA    34      /* FORE ESA ATM Card */
+#define INV_FORE_GIA    35      /* FORE GIA ATM Card */
+
+/* Types for class INV_SCSI and INV_VSCSI; The type code is the same as
+ * the device type code returned by the Inquiry command, iff the Inquiry
+ * command defines a type code for the device in question.  If it doesn't,
+ * values over 31 will be used for the device type.
+ * Note: the lun is encoded in bits 8-15 of the state.  The
+ * state field low 3 bits contains the information from the inquiry
+ * cmd that indicates ANSI SCSI 1,2, etc. compliance, and bit 7
+ * contains the inquiry info that indicates whether the media is
+ * removable.
+ */
+#define INV_PRINTER	2	/* SCSI printer */
+#define INV_CPU		3	/* SCSI CPU device */
+#define INV_WORM	4	/* write-once-read-many (e.g. optical disks) */
+#define INV_CDROM	5	/* CD-ROM  */
+#define INV_SCANNER	6	/* scanners */
+#define INV_OPTICAL	7	/* optical disks (read-write) */
+#define INV_CHANGER	8	/* jukebox's for CDROMS, for example */
+#define INV_COMM	9	/* Communications device */
+#define INV_RAIDCTLR	32	/* RAID ctlr actually gives type 0 */
+
+/* bit definitions for state field for class INV_SCSI */
+#define INV_REMOVE	0x80	/* has removable media */
+#define INV_SCSI_MASK	7	/* to which ANSI SCSI standard device conforms*/
+
+/* types for class INV_AUDIO */
+
+#define INV_AUDIO_HDSP		0	/* Indigo DSP system */
+#define INV_AUDIO_VIGRA110	1	/* ViGRA 110 audio board */
+#define INV_AUDIO_VIGRA210	2	/* ViGRA 210 audio board */
+#define INV_AUDIO_A2		3	/* HAL2 / Audio Module for Indigo 2 */
+#define INV_AUDIO_A3		4	/* Moosehead (IP32) AD1843 codec */
+#define INV_AUDIO_RAD		5	/* RAD PCI chip */
+
+/* types for class INV_VIDEO */
+
+#define	INV_VIDEO_LIGHT		0
+#define	INV_VIDEO_VS2		1	/* MultiChannel Option */
+#define	INV_VIDEO_EXPRESS	2	/* kaleidecope video */
+#define	INV_VIDEO_VINO		3
+#define	INV_VIDEO_VO2		4	/* Sirius Video */
+#define	INV_VIDEO_INDY		5	/* Indy Video - kal vid on Newport
+					  gfx on Indy */
+#define	INV_VIDEO_MVP		6	/* Moosehead Video Ports */
+#define	INV_VIDEO_INDY_601	7	/* Indy Video 601 */
+#define	INV_VIDEO_PMUX		8	/* PALMUX video w/ PGR gfx */
+#define	INV_VIDEO_MGRAS		9	/* Galileo 1.5 video */
+#define	INV_VIDEO_DIVO		10	/* DIVO video */
+#define	INV_VIDEO_RACER		11	/* SpeedRacer Pro Video */
+#define	INV_VIDEO_EVO		12	/* EVO Personal Video */
+#define INV_VIDEO_XTHD		13	/* XIO XT-HDTV video */
+
+/* states for video class INV_VIDEO_EXPRESS */
+
+#define INV_GALILEO_REV		0xF
+#define INV_GALILEO_JUNIOR	0x10
+#define INV_GALILEO_INDY_CAM	0x20
+#define INV_GALILEO_DBOB	0x40
+#define INV_GALILEO_ELANTEC	0x80
+
+/* states for video class VINO */
+
+#define INV_VINO_REV		0xF
+#define INV_VINO_INDY_CAM	0x10
+#define INV_VINO_INDY_NOSW	0x20	/* nebulous - means s/w not installed */
+
+/* states for video class MVP */
+
+#define INV_MVP_REV(x)		(((x)&0x0000000f))
+#define INV_MVP_REV_SW(x)	(((x)&0x000000f0)>>4)
+#define INV_MVP_AV_BOARD(x)	(((x)&0x00000f00)>>8)
+#define	INV_MVP_AV_REV(x)	(((x)&0x0000f000)>>12)
+#define	INV_MVP_CAMERA(x)	(((x)&0x000f0000)>>16)
+#define	INV_MVP_CAM_REV(x)	(((x)&0x00f00000)>>20)
+#define INV_MVP_SDIINF(x)       (((x)&0x0f000000)>>24)
+#define INV_MVP_SDI_REV(x)      (((x)&0xf0000000)>>28)
+
+/* types for class INV_BUS */
+
+#define INV_BUS_VME	0
+#define INV_BUS_EISA	1
+#define INV_BUS_GIO	2
+#define INV_BUS_BT3_PCI	3
+
+/* types for class INV_MISC */
+#define INV_MISC_EPC_EINT	0	/* EPC external interrupts */
+#define INV_MISC_PCKM		1	/* pc keyboard or mouse */
+#define INV_MISC_IOC3_EINT	2	/* IOC3 external interrupts */
+#define INV_MISC_OTHER		3	/* non-specific type */
+
+/*
+ * The four components below do not actually have inventory information
+ * associated with the vertex. These symbols are used by grio at the 
+ * moment to figure out the device type from the vertex. If these get
+ * inventory structures in the future, either the type values must
+ * remain the same or grio code needs to change.
+ */
+
+#define INV_XBOW        	3	/* cross bow */
+#define INV_HUB         	4	/* hub */
+#define INV_PCI_BRIDGE  	5	/* pci bridge */
+#define INV_ROUTER		6	/* router */
+
+/*  types for class INV_PROM */
+#define INV_IO6PROM	0
+#define INV_IP27PROM	1
+#define INV_IP35PROM	2
+
+/* types for class INV_COMPRESSION */
+
+#define	INV_COSMO		0
+#define	INV_INDYCOMP		1
+#define	INV_IMPACTCOMP		2	/* cosmo2, aka impact compression */
+#define	INV_VICE		3 	/* Video imaging & compression engine */
+
+/* types for class INV_DISPLAY */
+#define INV_PRESENTER_BOARD	0       /* Indy Presenter adapter board */
+#define INV_PRESENTER_PANEL	1       /* Indy Presenter board and panel */
+#define INV_ICO_BOARD		2	/* IMPACT channel option board */
+#define INV_DCD_BOARD		3	/* O2 dual channel option board */
+#define INV_7of9_BOARD          4       /* 7of9 flatpanel adapter board */
+#define INV_7of9_PANEL          5       /* 7of9 flatpanel board and panel */
+
+/* types for class INV_IEEE1394 */
+#define INV_OHCI		0	/* Ohci IEEE1394 pci card */
+#define INV_RAWISO1394   	10	/* Raw Isochronous IEEE 1394 protocol driver */
+#define INV_RAWASYNC1394 	11	/* Raw Asynchronous IEEE 1394 protocol driver */
+#define INV_AVC1394     	12	/* Audio, Video & Control (AV/C) IEEE 1394 protocol driver */
+
+/* state for class INV_IEEE1394 & type INV_OHCI */
+#define INV_IEEE1394_STATE_TI_REV_1 0
+
+/* O2 DVLink 1.1 controller static info */
+#define INV_IEEE1394_CTLR_O2_DVLINK_11 0x8009104c
+
+/* types for class INV_TPU */
+#define	INV_TPU_EXT		0	/* External XIO Tensor Processing Unit */
+#define	INV_TPU_XIO		1	/* Internal XIO Tensor Processing Unit */
+
+typedef struct invent_generic_s {
+	unsigned short	ig_module;
+	unsigned short	ig_slot;
+	unsigned char	ig_flag;
+	int	ig_invclass;
+} invent_generic_t;
+
+#define INVENT_ENABLED	0x1
+
+typedef struct invent_membnkinfo {
+	unsigned short	imb_size;	/* bank size in MB */
+	unsigned short	imb_attr;	/* Mem attributes */
+	unsigned int	imb_flag;	/* bank flags */
+} invent_membnkinfo_t;
+
+
+typedef struct invent_meminfo {
+	invent_generic_t 	im_gen;
+	unsigned short	im_size;	/* memory size     */
+	unsigned short	im_banks;	/* number of banks */
+	/*
+	 * declare an array with one element. Each platform is expected to
+	 * allocate the size required based on the number of banks and set
+	 * the im_banks correctly for this array traversal.
+	 */
+	invent_membnkinfo_t im_bank_info[1]; 
+} invent_meminfo_t;
+
+#define INV_MEM_PREMIUM	 0x01
+
+typedef struct invent_cpuinfo {
+	invent_generic_t ic_gen;
+	cpu_inv_t     ic_cpu_info;
+	unsigned short	ic_cpuid;
+	unsigned short	ic_slice;
+} invent_cpuinfo_t;
+
+typedef struct invent_rpsinfo {
+	invent_generic_t ir_gen;
+	int 		 ir_xbox;	/* is RPS connected to an xbox */
+} invent_rpsinfo_t;
+
+typedef struct invent_miscinfo {
+	invent_generic_t im_gen;
+	int       	 im_rev;
+	int		 im_version;
+	int	         im_type;
+	uint64_t	 im_speed;
+} invent_miscinfo_t;
+
+
+typedef struct invent_routerinfo{
+         invent_generic_t im_gen;
+         router_inv_t     rip;
+} invent_routerinfo_t;
+
+
+
+#ifdef __KERNEL__
+
+typedef struct irix5_inventory_s {
+	app32_ptr_t	inv_next;	/* next inventory record in list */
+	int	inv_class;		/* class of object */
+	int	inv_type;		/* class sub-type of object */
+	major_t	inv_controller;		/* object major identifier */
+	minor_t	inv_unit;		/* object minor identifier */
+	int	inv_state;		/* information specific to object or
+					   class */
+} irix5_inventory_t;
+
+typedef struct invplace_s {
+	devfs_handle_t		invplace_vhdl;		/* current vertex */
+	devfs_handle_t		invplace_vplace;	/* place in vertex list */
+	inventory_t		*invplace_inv;		/* place in inv list on vertex */
+} invplace_t; /* Magic cookie placeholder in inventory list */
+
+extern void	    add_to_inventory(int, int, int, int, int);
+extern void	    replace_in_inventory(inventory_t *, int, int, int, int, int);
+extern inventory_t  *get_next_inventory(invplace_t *);
+extern inventory_t  *find_inventory(inventory_t *, int, int, int, int, int);
+extern int	    scaninvent(int (*)(inventory_t *, void *), void *);
+extern int	    get_sizeof_inventory(int);
+
+extern void device_inventory_add(	devfs_handle_t device, 
+					int class, 
+					int type, 
+					major_t ctlr, 
+					minor_t unit, 
+					int state);
+
+
+extern inventory_t *device_inventory_get_next(	devfs_handle_t device,
+						invplace_t *);
+
+extern void device_controller_num_set(	devfs_handle_t,
+					int);
+extern int device_controller_num_get(	devfs_handle_t);
+#endif /* __KERNEL__ */
+#endif /* _ASM_SN_INVENT_H */
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
new file mode 100644
index 000000000..1523351ec
--- /dev/null
+++ b/include/asm-ia64/sn/io.h
@@ -0,0 +1,77 @@
+
+/* $Id: io.h,v 1.2 2000/02/02 16:35:57 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+
+#include <linux/config.h>
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/addrs.h>
+#endif
+
+#define IO_SPACE_BASE IO_BASE
+
+/* Because we only have PCI I/O ports.  */
+#if !defined(CONFIG_IA64_SGI_IO)
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* No isa_* versions, the Origin doesn't have ISA / EISA bridges.  */
+
+#else	/* CONFIG_IA64_SGI_IO */
+
+#define IIO_ITTE_BASE	0x400160	/* base of translation table entries */
+#define IIO_ITTE(bigwin)	(IIO_ITTE_BASE + 8*(bigwin))
+
+#define IIO_ITTE_OFFSET_BITS	5	/* size of offset field */
+#define IIO_ITTE_OFFSET_MASK	((1<<IIO_ITTE_OFFSET_BITS)-1)
+#define IIO_ITTE_OFFSET_SHIFT	0
+
+#define IIO_ITTE_WIDGET_BITS	4	/* size of widget field */
+#define IIO_ITTE_WIDGET_MASK	((1<<IIO_ITTE_WIDGET_BITS)-1)
+#define IIO_ITTE_WIDGET_SHIFT	8
+
+#define IIO_ITTE_IOSP		1	/* I/O Space bit */
+#define IIO_ITTE_IOSP_MASK	1
+#define IIO_ITTE_IOSP_SHIFT	12
+#define HUB_PIO_MAP_TO_MEM	0
+#define HUB_PIO_MAP_TO_IO	1
+
+#define IIO_ITTE_INVALID_WIDGET	3	/* an invalid widget  */
+
+#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
+	REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
+		(((((addr) >> BWIN_SIZE_BITS) & \
+		   IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
+		(io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
+		(((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
+
+#define IIO_ITTE_DISABLE(nasid, bigwin) \
+	IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
+		     (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
+
+#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
+
+/*
+ * Macro which takes the widget number, and returns the 
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range 
+ * 0, 8 - 0xF
+ */
+#define	IIO_IOPRB(_x)	(IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+			(_x) : \
+			(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/hubio.h>
+#endif
+
+#endif	/* CONFIG_IA64_SGI_IO */
+
+#endif /* _ASM_SN_IO_H */
diff --git a/include/asm-ia64/sn/iobus.h b/include/asm-ia64/sn/iobus.h
new file mode 100644
index 000000000..d710578cc
--- /dev/null
+++ b/include/asm-ia64/sn/iobus.h
@@ -0,0 +1,185 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_IOBUS_H
+#define _ASM_SN_IOBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct eframe_s;
+struct piomap;
+struct dmamap;
+
+
+/* for ilvl_t interrupt level, for use with intr_block_level.  Can't
+ * typedef twice without causing warnings, and some users of this header
+ * file do not already include driver.h, but expect ilvl_t to be defined,
+ * while others include both, leading to the warning ...
+ */
+
+#include <asm/types.h>
+#include <asm/sn/driver.h>
+
+
+typedef __psunsigned_t iobush_t;
+
+#if __KERNEL__
+/* adapter handle */
+typedef devfs_handle_t adap_t;
+#endif
+
+
+/* interrupt function */
+typedef void	       *intr_arg_t;
+typedef void		intr_func_f(intr_arg_t);
+typedef intr_func_f    *intr_func_t;
+
+#define	INTR_ARG(n)	((intr_arg_t)(__psunsigned_t)(n))
+
+/* system interrupt resource handle -- returned from intr_alloc */
+typedef struct intr_s *intr_t;
+#define INTR_HANDLE_NONE ((intr_t)0)
+
+/*
+ * restore interrupt level value, returned from intr_block_level
+ * for use with intr_unblock_level.
+ */
+typedef void *rlvl_t;
+
+
+/* 
+ * A basic, platform-independent description of I/O requirements for
+ * a device. This structure is usually formed by lboot based on information 
+ * in configuration files.  It contains information about PIO, DMA, and
+ * interrupt requirements for a specific instance of a device.
+ *
+ * The pio description is currently unused.
+ *
+ * The dma description describes bandwidth characteristics and bandwidth
+ * allocation requirements. (TBD)
+ *
+ * The Interrupt information describes the priority of interrupt, desired 
+ * destination, policy (TBD), whether this is an error interrupt, etc.  
+ * For now, interrupts are targeted to specific CPUs.
+ */
+
+typedef struct device_desc_s {
+	/* pio description (currently none) */
+
+	/* dma description */
+	/* TBD: allocated badwidth requirements */
+
+	/* interrupt description */
+	devfs_handle_t	intr_target;	/* Hardware locator string */
+	int 		intr_policy;	/* TBD */
+	ilvl_t		intr_swlevel;	/* software level for blocking intr */
+	char		*intr_name;	/* name of interrupt, if any */
+
+	int		flags;
+} *device_desc_t;
+
+/* flag values */
+#define	D_INTR_ISERR	0x1		/* interrupt is for error handling */
+#define D_IS_ASSOC	0x2		/* descriptor is associated with a dev */
+#define D_INTR_NOTHREAD	0x4		/* Interrupt handler isn't threaded. */
+
+#define INTR_SWLEVEL_NOTHREAD_DEFAULT 	0	/* Default
+						 * Interrupt level in case of
+						 * non-threaded interrupt 
+						 * handlers
+						 */
+/* 
+ * Drivers use these interfaces to manage device descriptors.
+ *
+ * To examine defaults:
+ *	desc = device_desc_default_get(dev);
+ *	device_desc_*_get(desc);
+ *
+ * To modify defaults:
+ *	desc = device_desc_default_get(dev);
+ *	device_desc_*_set(desc);
+ *
+ * To eliminate defaults:
+ *	device_desc_default_set(dev, NULL);
+ *
+ * To override defaults:
+ *	desc = device_desc_dup(dev);
+ *	device_desc_*_set(desc,...);
+ *	use device_desc in calls
+ *	device_desc_free(desc);
+ *
+ * Software must not set or eliminate default device descriptors for a device while
+ * concurrently get'ing, dup'ing or using them.  Default device descriptors can be 
+ * changed only for a device that is quiescent.  In general, device drivers have no
+ * need to permanently change defaults anyway -- they just override defaults, when
+ * necessary.
+ */
+extern device_desc_t	device_desc_dup(devfs_handle_t dev);
+extern void		device_desc_free(device_desc_t device_desc);
+extern device_desc_t	device_desc_default_get(devfs_handle_t dev);
+extern void		device_desc_default_set(devfs_handle_t dev, device_desc_t device_desc);
+
+extern devfs_handle_t	device_desc_intr_target_get(device_desc_t device_desc);
+extern int		device_desc_intr_policy_get(device_desc_t device_desc);
+extern ilvl_t		device_desc_intr_swlevel_get(device_desc_t device_desc);
+extern char *		device_desc_intr_name_get(device_desc_t device_desc);
+extern int		device_desc_flags_get(device_desc_t device_desc);
+
+extern void		device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target);
+extern void		device_desc_intr_policy_set(device_desc_t device_desc, int policy);
+extern void		device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel);
+extern void		device_desc_intr_name_set(device_desc_t device_desc, char *name);
+extern void		device_desc_flags_set(device_desc_t device_desc, int flags);
+
+
+/* IO state */
+#ifdef COMMENT
+#define IO_STATE_EMPTY			0x01	/* non-existent */
+#define IO_STATE_INITIALIZING		0x02	/* being initialized */
+#define IO_STATE_ATTACHING   		0x04    /* becoming active */
+#define IO_STATE_ACTIVE      		0x08    /* active */
+#define IO_STATE_DETACHING   		0x10    /* becoming inactive */
+#define IO_STATE_INACTIVE    		0x20    /* not in use */
+#define IO_STATE_ERROR			0x40    /* problems */
+#define IO_STATE_BAD_HARDWARE		0x80	/* broken hardware */
+#endif
+
+struct edt;
+
+
+/* return codes */
+#define RC_OK				0	
+#define RC_ERROR			1
+
+/* bus configuration management op code */
+#define IOBUS_CONFIG_ATTACH		0	/* vary on */
+#define IOBUS_CONFIG_DETACH		1	/* vary off */
+#define IOBUS_CONFIG_RECOVER		2	/* clear error then vary on */
+
+/* get low-level PIO handle */
+extern int pio_geth(struct piomap*, int bus, int bus_id, int subtype, 
+	iopaddr_t addr, int size);	
+
+/* get low-level DMA handle */
+extern int dma_geth(struct dmamap*, int bus_type, int bus_id, int dma_type, 
+	int npages, int page_size, int flags);	
+
+#ifdef __cplusplus
+}
+#endif
+
+/*
+ * Macros for page number and page offsets, using ps as page size
+ */
+#define x_pnum(addr, ps) ((__psunsigned_t)(addr) / (__psunsigned_t)(ps))
+#define x_poff(addr, ps) ((__psunsigned_t)(addr) & ((__psunsigned_t)(ps) - 1))
+
+#endif /* _ASM_SN_IOBUS_H */
diff --git a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h
new file mode 100644
index 000000000..e407a3f7a
--- /dev/null
+++ b/include/asm-ia64/sn/ioc3.h
@@ -0,0 +1,671 @@
+/* $Id: ioc3.h,v 1.2 2000/11/16 19:49:17 pfg Exp $
+ *
+ * Copyright (C) 1999 Ralf Baechle
+ * This file is part of the Linux driver for the SGI IOC3.
+ */
+#ifndef IOC3_H
+#define IOC3_H
+
+/* SUPERIO uart register map */
+typedef volatile struct ioc3_uartregs {
+	union {
+		volatile u8	rbr;	/* read only, DLAB == 0 */
+		volatile u8	thr;	/* write only, DLAB == 0 */
+		volatile u8	dll;	/* DLAB == 1 */
+	} u1;
+	union {
+		volatile u8	ier;	/* DLAB == 0 */
+		volatile u8	dlm;	/* DLAB == 1 */
+	} u2;
+	union {
+		volatile u8	iir;	/* read only */
+		volatile u8	fcr;	/* write only */
+	} u3;
+	volatile u8	    iu_lcr;
+	volatile u8	    iu_mcr;
+	volatile u8	    iu_lsr;
+	volatile u8	    iu_msr;
+	volatile u8	    iu_scr;
+} ioc3_uregs_t;
+
+#define iu_rbr u1.rbr
+#define iu_thr u1.thr
+#define iu_dll u1.dll
+#define iu_ier u2.ier
+#define iu_dlm u2.dlm
+#define iu_iir u3.iir
+#define iu_fcr u3.fcr
+
+struct ioc3_sioregs {
+	volatile u8		fill[0x141];	/* starts at 0x141 */
+
+	volatile u8		uartc;
+	volatile u8		kbdcg;
+
+	volatile u8		fill0[0x150 - 0x142 - 1];
+
+	volatile u8		pp_data;
+	volatile u8		pp_dsr;
+	volatile u8		pp_dcr;
+
+	volatile u8		fill1[0x158 - 0x152 - 1];
+
+	volatile u8		pp_fifa;
+	volatile u8		pp_cfgb;
+	volatile u8		pp_ecr;
+
+	volatile u8		fill2[0x168 - 0x15a - 1];
+
+	volatile u8		rtcad;
+	volatile u8		rtcdat;
+
+	volatile u8		fill3[0x170 - 0x169 - 1];
+
+	struct ioc3_uartregs    uartb;	/* 0x20170  */
+	struct ioc3_uartregs    uarta;	/* 0x20178  */
+};
+
+/* Register layout of IOC3 in configuration space.  */
+struct ioc3 {
+	volatile u32	pad0[7];	/* 0x00000  */
+	volatile u32	sio_ir;		/* 0x0001c  */
+	volatile u32	sio_ies;	/* 0x00020  */
+	volatile u32	sio_iec;	/* 0x00024  */
+	volatile u32	sio_cr;		/* 0x00028  */
+	volatile u32	int_out;	/* 0x0002c  */
+	volatile u32	mcr;		/* 0x00030  */
+
+	/* General Purpose I/O registers  */
+	volatile u32	gpcr_s;		/* 0x00034  */
+	volatile u32	gpcr_c;		/* 0x00038  */
+	volatile u32	gpdr;		/* 0x0003c  */
+	volatile u32	gppr_0;		/* 0x00040  */
+	volatile u32	gppr_1;		/* 0x00044  */
+	volatile u32	gppr_2;		/* 0x00048  */
+	volatile u32	gppr_3;		/* 0x0004c  */
+	volatile u32	gppr_4;		/* 0x00050  */
+	volatile u32	gppr_5;		/* 0x00054  */
+	volatile u32	gppr_6;		/* 0x00058  */
+	volatile u32	gppr_7;		/* 0x0005c  */
+	volatile u32	gppr_8;		/* 0x00060  */
+	volatile u32	gppr_9;		/* 0x00064  */
+	volatile u32	gppr_10;	/* 0x00068  */
+	volatile u32	gppr_11;	/* 0x0006c  */
+	volatile u32	gppr_12;	/* 0x00070  */
+	volatile u32	gppr_13;	/* 0x00074  */
+	volatile u32	gppr_14;	/* 0x00078  */
+	volatile u32	gppr_15;	/* 0x0007c  */
+
+	/* Parallel Port Registers  */
+	volatile u32	ppbr_h_a;	/* 0x00080  */
+	volatile u32	ppbr_l_a;	/* 0x00084  */
+	volatile u32	ppcr_a;		/* 0x00088  */
+	volatile u32	ppcr;		/* 0x0008c  */
+	volatile u32	ppbr_h_b;	/* 0x00090  */
+	volatile u32	ppbr_l_b;	/* 0x00094  */
+	volatile u32	ppcr_b;		/* 0x00098  */
+
+	/* Keyboard and Mouse Registers  */
+	volatile u32	km_csr;		/* 0x0009c  */
+	volatile u32	k_rd;		/* 0x000a0  */
+	volatile u32	m_rd;		/* 0x000a4  */
+	volatile u32	k_wd;		/* 0x000a8  */
+	volatile u32	m_wd;		/* 0x000ac  */
+
+	/* Serial Port Registers  */
+	volatile u32	sbbr_h;		/* 0x000b0  */
+	volatile u32	sbbr_l;		/* 0x000b4  */
+	volatile u32	sscr_a;		/* 0x000b8  */
+	volatile u32	stpir_a;	/* 0x000bc  */
+	volatile u32	stcir_a;	/* 0x000c0  */
+	volatile u32	srpir_a;	/* 0x000c4  */
+	volatile u32	srcir_a;	/* 0x000c8  */
+	volatile u32	srtr_a;		/* 0x000cc  */
+	volatile u32	shadow_a;	/* 0x000d0  */
+	volatile u32	sscr_b;		/* 0x000d4  */
+	volatile u32	stpir_b;	/* 0x000d8  */
+	volatile u32	stcir_b;	/* 0x000dc  */
+	volatile u32	srpir_b;	/* 0x000e0  */
+	volatile u32	srcir_b;	/* 0x000e4  */
+	volatile u32	srtr_b;		/* 0x000e8  */
+	volatile u32	shadow_b;	/* 0x000ec  */
+
+	/* Ethernet Registers  */
+	volatile u32	emcr;		/* 0x000f0  */
+	volatile u32	eisr;		/* 0x000f4  */
+	volatile u32	eier;		/* 0x000f8  */
+	volatile u32	ercsr;		/* 0x000fc  */
+	volatile u32	erbr_h;		/* 0x00100  */
+	volatile u32	erbr_l;		/* 0x00104  */
+	volatile u32	erbar;		/* 0x00108  */
+	volatile u32	ercir;		/* 0x0010c  */
+	volatile u32	erpir;		/* 0x00110  */
+	volatile u32	ertr;		/* 0x00114  */
+	volatile u32	etcsr;		/* 0x00118  */
+	volatile u32	ersr;		/* 0x0011c  */
+	volatile u32	etcdc;		/* 0x00120  */
+	volatile u32	ebir;		/* 0x00124  */
+	volatile u32	etbr_h;		/* 0x00128  */
+	volatile u32	etbr_l;		/* 0x0012c  */
+	volatile u32	etcir;		/* 0x00130  */
+	volatile u32	etpir;		/* 0x00134  */
+	volatile u32	emar_h;		/* 0x00138  */
+	volatile u32	emar_l;		/* 0x0013c  */
+	volatile u32	ehar_h;		/* 0x00140  */
+	volatile u32	ehar_l;		/* 0x00144  */
+	volatile u32	micr;		/* 0x00148  */
+	volatile u32	midr_r;		/* 0x0014c  */
+	volatile u32    midr_w;           /* 0x00150  */
+	volatile u32	pad1[(0x20000 - 0x00154) / 4];
+
+	/* SuperIO Registers  XXX */
+	struct ioc3_sioregs	sregs;	/* 0x20000 */
+	volatile u32	pad2[(0x40000 - 0x20180) / 4];
+
+	/* SSRAM Diagnostic Access */
+	volatile u32	ssram[(0x80000 - 0x40000) / 4];
+
+	/* Bytebus device offsets
+	   0x80000 -   Access to the generic devices selected with   DEV0
+	   0x9FFFF     bytebus DEV_SEL_0
+	   0xA0000 -   Access to the generic devices selected with   DEV1
+	   0xBFFFF     bytebus DEV_SEL_1
+	   0xC0000 -   Access to the generic devices selected with   DEV2
+	   0xDFFFF     bytebus DEV_SEL_2
+	   0xE0000 -   Access to the generic devices selected with   DEV3
+	   0xFFFFF     bytebus DEV_SEL_3  */
+};
+
+/*
+ * Ethernet RX Buffer
+ */
+struct ioc3_erxbuf {
+	u32	w0;			/* first word (valid,bcnt,cksum) */
+	u32	err;			/* second word various errors */
+	/* next comes n bytes of padding */
+	/* then the received ethernet frame itself */
+};
+
+#define ERXBUF_IPCKSUM_MASK	0x0000ffff
+#define ERXBUF_BYTECNT_MASK	0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT	16
+#define ERXBUF_V		0x80000000
+
+#define ERXBUF_CRCERR		0x00000001	/* aka RSV15 */
+#define ERXBUF_FRAMERR		0x00000002	/* aka RSV14 */
+#define ERXBUF_CODERR		0x00000004	/* aka RSV13 */
+#define ERXBUF_INVPREAMB	0x00000008	/* aka RSV18 */
+#define ERXBUF_LOLEN		0x00007000	/* aka RSV2_0 */
+#define ERXBUF_HILEN		0x03ff0000	/* aka RSV12_3 */
+#define ERXBUF_MULTICAST	0x04000000	/* aka RSV16 */
+#define ERXBUF_BROADCAST	0x08000000	/* aka RSV17 */
+#define ERXBUF_LONGEVENT	0x10000000	/* aka RSV19 */
+#define ERXBUF_BADPKT		0x20000000	/* aka RSV20 */
+#define ERXBUF_GOODPKT		0x40000000	/* aka RSV21 */
+#define ERXBUF_CARRIER		0x80000000	/* aka RSV22 */
+
+/*
+ * Ethernet TX Descriptor
+ */
+#define ETXD_DATALEN    104
+struct ioc3_etxd {
+	u32	cmd;				/* command field */
+	u32	bufcnt;				/* buffer counts field */
+	u64	p1;				/* buffer pointer 1 */
+	u64	p2;				/* buffer pointer 2 */
+	u8	data[ETXD_DATALEN];		/* opt. tx data */
+};
+
+#define ETXD_BYTECNT_MASK	0x000007ff	/* total byte count */
+#define ETXD_INTWHENDONE	0x00001000	/* intr when done */
+#define ETXD_D0V		0x00010000	/* data 0 valid */
+#define ETXD_B1V		0x00020000	/* buf 1 valid */
+#define ETXD_B2V		0x00040000	/* buf 2 valid */
+#define ETXD_DOCHECKSUM		0x00080000	/* insert ip cksum */
+#define ETXD_CHKOFF_MASK	0x07f00000	/* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT	20
+
+#define ETXD_D0CNT_MASK		0x0000007f
+#define ETXD_B1CNT_MASK		0x0007ff00
+#define ETXD_B1CNT_SHIFT	8
+#define ETXD_B2CNT_MASK		0x7ff00000
+#define ETXD_B2CNT_SHIFT	20
+
+/*
+ * Bytebus device space
+ */
+#define IOC3_BYTEBUS_DEV0	0x80000L
+#define IOC3_BYTEBUS_DEV1	0xa0000L
+#define IOC3_BYTEBUS_DEV2	0xc0000L
+#define IOC3_BYTEBUS_DEV3	0xe0000L
+
+/* ------------------------------------------------------------------------- */
+
+/* Superio Registers (PIO Access) */
+#define IOC3_SIO_BASE		0x20000
+#define IOC3_SIO_UARTC		(IOC3_SIO_BASE+0x141)	/* UART Config */
+#define IOC3_SIO_KBDCG		(IOC3_SIO_BASE+0x142)	/* KBD Config */
+#define IOC3_SIO_PP_BASE	(IOC3_SIO_BASE+PP_BASE)		/* Parallel Port */
+#define IOC3_SIO_RTC_BASE	(IOC3_SIO_BASE+0x168)	/* Real Time Clock */
+#define IOC3_SIO_UB_BASE	(IOC3_SIO_BASE+UARTB_BASE)	/* UART B */
+#define IOC3_SIO_UA_BASE	(IOC3_SIO_BASE+UARTA_BASE)	/* UART A */
+
+/* SSRAM Diagnostic Access */
+#define IOC3_SSRAM	IOC3_RAM_OFF	/* base of SSRAM diagnostic access */
+#define IOC3_SSRAM_LEN	0x40000 /* 256kb (address space size, may not be fully populated) */
+#define IOC3_SSRAM_DM	0x0000ffff	/* data mask */
+#define IOC3_SSRAM_PM	0x00010000	/* parity mask */
+
+/* bitmasks for PCI_SCR */
+#define PCI_SCR_PAR_RESP_EN	0x00000040	/* enb PCI parity checking */
+#define PCI_SCR_SERR_EN		0x00000100	/* enable the SERR# driver */
+#define PCI_SCR_DROP_MODE_EN	0x00008000	/* drop pios on parity err */
+#define PCI_SCR_RX_SERR		(0x1 << 16)
+#define PCI_SCR_DROP_MODE	(0x1 << 17)
+#define PCI_SCR_SIG_PAR_ERR	(0x1 << 24)
+#define PCI_SCR_SIG_TAR_ABRT	(0x1 << 27)
+#define PCI_SCR_RX_TAR_ABRT	(0x1 << 28)
+#define PCI_SCR_SIG_MST_ABRT	(0x1 << 29)
+#define PCI_SCR_SIG_SERR	(0x1 << 30)
+#define PCI_SCR_PAR_ERR		(0x1 << 31)
+
+/* bitmasks for IOC3_KM_CSR */
+#define KM_CSR_K_WRT_PEND 0x00000001	/* kbd port xmitting or resetting */
+#define KM_CSR_M_WRT_PEND 0x00000002	/* mouse port xmitting or resetting */
+#define KM_CSR_K_LCB	  0x00000004	/* Line Cntrl Bit for last KBD write */
+#define KM_CSR_M_LCB	  0x00000008	/* same for mouse */
+#define KM_CSR_K_DATA	  0x00000010	/* state of kbd data line */
+#define KM_CSR_K_CLK	  0x00000020	/* state of kbd clock line */
+#define KM_CSR_K_PULL_DATA 0x00000040	/* pull kbd data line low */
+#define KM_CSR_K_PULL_CLK 0x00000080	/* pull kbd clock line low */
+#define KM_CSR_M_DATA	  0x00000100	/* state of ms data line */
+#define KM_CSR_M_CLK	  0x00000200	/* state of ms clock line */
+#define KM_CSR_M_PULL_DATA 0x00000400	/* pull ms data line low */
+#define KM_CSR_M_PULL_CLK 0x00000800	/* pull ms clock line low */
+#define KM_CSR_EMM_MODE	  0x00001000	/* emulation mode */
+#define KM_CSR_SIM_MODE	  0x00002000	/* clock X8 */
+#define KM_CSR_K_SM_IDLE  0x00004000	/* Keyboard is idle */
+#define KM_CSR_M_SM_IDLE  0x00008000	/* Mouse is idle */
+#define KM_CSR_K_TO	  0x00010000	/* Keyboard trying to send/receive */
+#define KM_CSR_M_TO	  0x00020000	/* Mouse trying to send/receive */
+#define KM_CSR_K_TO_EN	  0x00040000	/* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
+					   SIO_IR to assert */
+#define KM_CSR_M_TO_EN	  0x00080000	/* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
+					   SIO_IR to assert */
+#define KM_CSR_K_CLAMP_ONE	0x00100000	/* Pull K_CLK low after rec. one char */
+#define KM_CSR_M_CLAMP_ONE	0x00200000	/* Pull M_CLK low after rec. one char */
+#define KM_CSR_K_CLAMP_THREE	0x00400000	/* Pull K_CLK low after rec. three chars */
+#define KM_CSR_M_CLAMP_THREE	0x00800000	/* Pull M_CLK low after rec. three char */
+
+/* bitmasks for IOC3_K_RD and IOC3_M_RD */
+#define KM_RD_DATA_2	0x000000ff	/* 3rd char recvd since last read */
+#define KM_RD_DATA_2_SHIFT 0
+#define KM_RD_DATA_1	0x0000ff00	/* 2nd char recvd since last read */
+#define KM_RD_DATA_1_SHIFT 8
+#define KM_RD_DATA_0	0x00ff0000	/* 1st char recvd since last read */
+#define KM_RD_DATA_0_SHIFT 16
+#define KM_RD_FRAME_ERR_2 0x01000000	/*  framing or parity error in byte 2 */
+#define KM_RD_FRAME_ERR_1 0x02000000	/* same for byte 1 */
+#define KM_RD_FRAME_ERR_0 0x04000000	/* same for byte 0 */
+
+#define KM_RD_KBD_MSE	0x08000000	/* 0 if from kbd, 1 if from mouse */
+#define KM_RD_OFLO	0x10000000	/* 4th char recvd before this read */
+#define KM_RD_VALID_2	0x20000000	/* DATA_2 valid */
+#define KM_RD_VALID_1	0x40000000	/* DATA_1 valid */
+#define KM_RD_VALID_0	0x80000000	/* DATA_0 valid */
+#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
+
+/* bitmasks for IOC3_K_WD & IOC3_M_WD */
+#define KM_WD_WRT_DATA	0x000000ff	/* write to keyboard/mouse port */
+#define KM_WD_WRT_DATA_SHIFT 0
+
+/* bitmasks for serial RX status byte */
+#define RXSB_OVERRUN	0x01	/* char(s) lost */
+#define RXSB_PAR_ERR	0x02	/* parity error */
+#define RXSB_FRAME_ERR	0x04	/* framing error */
+#define RXSB_BREAK	0x08	/* break character */
+#define RXSB_CTS	0x10	/* state of CTS */
+#define RXSB_DCD	0x20	/* state of DCD */
+#define RXSB_MODEM_VALID 0x40	/* DCD, CTS and OVERRUN are valid */
+#define RXSB_DATA_VALID 0x80	/* data byte, FRAME_ERR PAR_ERR & BREAK valid */
+
+/* bitmasks for serial TX control byte */
+#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
+#define TXCB_INVALID	0x00	/* byte is invalid */
+#define TXCB_VALID	0x40	/* byte is valid */
+#define TXCB_MCR	0x80	/* data<7:0> to modem control register */
+#define TXCB_DELAY	0xc0	/* delay data<7:0> mSec */
+
+/* bitmasks for IOC3_SBBR_L */
+#define SBBR_L_SIZE	0x00000001	/* 0 == 1KB rings, 1 == 4KB rings */
+#define SBBR_L_BASE	0xfffff000	/* lower serial ring base addr */
+
+/* bitmasks for IOC3_SSCR_<A:B> */
+#define SSCR_RX_THRESHOLD 0x000001ff	/* hiwater mark */
+#define SSCR_TX_TIMER_BUSY 0x00010000	/* TX timer in progress */
+#define SSCR_HFC_EN	0x00020000	/* hardware flow control enabled */
+#define SSCR_RX_RING_DCD 0x00040000	/* post RX record on delta-DCD */
+#define SSCR_RX_RING_CTS 0x00080000	/* post RX record on delta-CTS */
+#define SSCR_HIGH_SPD	0x00100000	/* 4X speed */
+#define SSCR_DIAG	0x00200000	/* bypass clock divider for sim */
+#define SSCR_RX_DRAIN	0x08000000	/* drain RX buffer to memory */
+#define SSCR_DMA_EN	0x10000000	/* enable ring buffer DMA */
+#define SSCR_DMA_PAUSE	0x20000000	/* pause DMA */
+#define SSCR_PAUSE_STATE 0x40000000	/* sets when PAUSE takes effect */
+#define SSCR_RESET	0x80000000	/* reset DMA channels */
+
+/* all producer/comsumer pointers are the same bitfield */
+#define PROD_CONS_PTR_4K 0x00000ff8	/* for 4K buffers */
+#define PROD_CONS_PTR_1K 0x000003f8	/* for 1K buffers */
+#define PROD_CONS_PTR_OFF 3
+
+/* bitmasks for IOC3_SRCIR_<A:B> */
+#define SRCIR_ARM	0x80000000	/* arm RX timer */
+
+/* bitmasks for IOC3_SRPIR_<A:B> */
+#define SRPIR_BYTE_CNT	0x07000000	/* bytes in packer */
+#define SRPIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_STCIR_<A:B> */
+#define STCIR_BYTE_CNT	0x0f000000	/* bytes in unpacker */
+#define STCIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_SHADOW_<A:B> */
+#define SHADOW_DR	0x00000001	/* data ready */
+#define SHADOW_OE	0x00000002	/* overrun error */
+#define SHADOW_PE	0x00000004	/* parity error */
+#define SHADOW_FE	0x00000008	/* framing error */
+#define SHADOW_BI	0x00000010	/* break interrupt */
+#define SHADOW_THRE	0x00000020	/* transmit holding register empty */
+#define SHADOW_TEMT	0x00000040	/* transmit shift register empty */
+#define SHADOW_RFCE	0x00000080	/* char in RX fifo has an error */
+#define SHADOW_DCTS	0x00010000	/* delta clear to send */
+#define SHADOW_DDCD	0x00080000	/* delta data carrier detect */
+#define SHADOW_CTS	0x00100000	/* clear to send */
+#define SHADOW_DCD	0x00800000	/* data carrier detect */
+#define SHADOW_DTR	0x01000000	/* data terminal ready */
+#define SHADOW_RTS	0x02000000	/* request to send */
+#define SHADOW_OUT1	0x04000000	/* 16550 OUT1 bit */
+#define SHADOW_OUT2	0x08000000	/* 16550 OUT2 bit */
+#define SHADOW_LOOP	0x10000000	/* loopback enabled */
+
+/* bitmasks for IOC3_SRTR_<A:B> */
+#define SRTR_CNT	0x00000fff	/* reload value for RX timer */
+#define SRTR_CNT_VAL	0x0fff0000	/* current value of RX timer */
+#define SRTR_CNT_VAL_SHIFT 16
+#define SRTR_HZ		16000	/* SRTR clock frequency */
+
+/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
+#define SIO_IR_SA_TX_MT		0x00000001	/* Serial port A TX empty */
+#define SIO_IR_SA_RX_FULL	0x00000002	/* port A RX buf full */
+#define SIO_IR_SA_RX_HIGH	0x00000004	/* port A RX hiwat */
+#define SIO_IR_SA_RX_TIMER	0x00000008	/* port A RX timeout */
+#define SIO_IR_SA_DELTA_DCD	0x00000010	/* port A delta DCD */
+#define SIO_IR_SA_DELTA_CTS	0x00000020	/* port A delta CTS */
+#define SIO_IR_SA_INT		0x00000040	/* port A pass-thru intr */
+#define SIO_IR_SA_TX_EXPLICIT	0x00000080	/* port A explicit TX thru */
+#define SIO_IR_SA_MEMERR	0x00000100	/* port A PCI error */
+#define SIO_IR_SB_TX_MT		0x00000200	/* */
+#define SIO_IR_SB_RX_FULL	0x00000400	/* */
+#define SIO_IR_SB_RX_HIGH	0x00000800	/* */
+#define SIO_IR_SB_RX_TIMER	0x00001000	/* */
+#define SIO_IR_SB_DELTA_DCD	0x00002000	/* */
+#define SIO_IR_SB_DELTA_CTS	0x00004000	/* */
+#define SIO_IR_SB_INT		0x00008000	/* */
+#define SIO_IR_SB_TX_EXPLICIT	0x00010000	/* */
+#define SIO_IR_SB_MEMERR	0x00020000	/* */
+#define SIO_IR_PP_INT		0x00040000	/* P port pass-thru intr */
+#define SIO_IR_PP_INTA		0x00080000	/* PP context A thru */
+#define SIO_IR_PP_INTB		0x00100000	/* PP context B thru */
+#define SIO_IR_PP_MEMERR	0x00200000	/* PP PCI error */
+#define SIO_IR_KBD_INT		0x00400000	/* kbd/mouse intr */
+#define SIO_IR_RT_INT		0x08000000	/* RT output pulse */
+#define SIO_IR_GEN_INT1		0x10000000	/* RT input pulse */
+#define SIO_IR_GEN_INT_SHIFT	28
+
+/* per device interrupt masks */
+#define SIO_IR_SA		(SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
+				 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
+				 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
+				 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
+				 SIO_IR_SA_MEMERR)
+#define SIO_IR_SB		(SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
+				 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
+				 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
+				 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
+				 SIO_IR_SB_MEMERR)
+#define SIO_IR_PP		(SIO_IR_PP_INT | SIO_IR_PP_INTA | \
+				 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
+#define SIO_IR_RT		(SIO_IR_RT_INT | SIO_IR_GEN_INT1)
+
+/* macro to load pending interrupts */
+#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
+				 PCI_INW(&((mem)->sio_ies_ro)))
+
+/* bitmasks for SIO_CR */
+#define SIO_CR_SIO_RESET	0x00000001	/* reset the SIO */
+#define SIO_CR_SER_A_BASE	0x000000fe	/* DMA poll addr port A */
+#define SIO_CR_SER_A_BASE_SHIFT 1
+#define SIO_CR_SER_B_BASE	0x00007f00	/* DMA poll addr port B */
+#define SIO_CR_SER_B_BASE_SHIFT 8
+#define SIO_SR_CMD_PULSE	0x00078000	/* byte bus strobe length */
+#define SIO_CR_CMD_PULSE_SHIFT	15
+#define SIO_CR_ARB_DIAG		0x00380000	/* cur !enet PCI requet (ro) */
+#define SIO_CR_ARB_DIAG_TXA	0x00000000
+#define SIO_CR_ARB_DIAG_RXA	0x00080000
+#define SIO_CR_ARB_DIAG_TXB	0x00100000
+#define SIO_CR_ARB_DIAG_RXB	0x00180000
+#define SIO_CR_ARB_DIAG_PP	0x00200000
+#define SIO_CR_ARB_DIAG_IDLE	0x00400000	/* 0 -> active request (ro) */
+
+/* bitmasks for INT_OUT */
+#define INT_OUT_COUNT	0x0000ffff	/* pulse interval timer */
+#define INT_OUT_MODE	0x00070000	/* mode mask */
+#define INT_OUT_MODE_0	0x00000000	/* set output to 0 */
+#define INT_OUT_MODE_1	0x00040000	/* set output to 1 */
+#define INT_OUT_MODE_1PULSE 0x00050000	/* send 1 pulse */
+#define INT_OUT_MODE_PULSES 0x00060000	/* send 1 pulse every interval */
+#define INT_OUT_MODE_SQW 0x00070000	/* toggle output every interval */
+#define INT_OUT_DIAG	0x40000000	/* diag mode */
+#define INT_OUT_INT_OUT 0x80000000	/* current state of INT_OUT */
+
+/* time constants for INT_OUT */
+#define INT_OUT_NS_PER_TICK (30 * 260)	/* 30 ns PCI clock, divisor=260 */
+#define INT_OUT_TICKS_PER_PULSE 3	/* outgoing pulse lasts 3 ticks */
+#define INT_OUT_US_TO_COUNT(x)		/* convert uS to a count value */ \
+	(((x) * 10 + INT_OUT_NS_PER_TICK / 200) *	\
+	 100 / INT_OUT_NS_PER_TICK - 1)
+#define INT_OUT_COUNT_TO_US(x)		/* convert count value to uS */ \
+	(((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
+#define INT_OUT_MIN_TICKS 3	/* min period is width of pulse in "ticks" */
+#define INT_OUT_MAX_TICKS INT_OUT_COUNT		/* largest possible count */
+
+/* bitmasks for GPCR */
+#define GPCR_DIR	0x000000ff	/* tristate pin input or output */
+#define GPCR_DIR_PIN(x) (1<<(x))	/* access one of the DIR bits */
+#define GPCR_EDGE	0x000f0000	/* extint edge or level sensitive */
+#define GPCR_EDGE_PIN(x) (1<<((x)+15))	/* access one of the EDGE bits */
+
+/* values for GPCR */
+#define GPCR_INT_OUT_EN 0x00100000	/* enable INT_OUT to pin 0 */
+#define GPCR_MLAN_EN	0x00200000	/* enable MCR to pin 8 */
+#define GPCR_DIR_SERA_XCVR 0x00000080	/* Port A Transceiver select enable */
+#define GPCR_DIR_SERB_XCVR 0x00000040	/* Port B Transceiver select enable */
+#define GPCR_DIR_PHY_RST   0x00000020	/* ethernet PHY reset enable */
+
+/* defs for some of the generic I/O pins */
+#define GPCR_PHY_RESET		0x20	/* pin is output to PHY reset */
+#define GPCR_UARTB_MODESEL	0x40	/* pin is output to port B mode sel */
+#define GPCR_UARTA_MODESEL	0x80	/* pin is output to port A mode sel */
+
+#define GPPR_PHY_RESET_PIN	5	/* GIO pin controlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN	6	/* GIO pin controlling uart b mode select */
+#define GPPR_UARTA_MODESEL_PIN	7	/* GIO pin controlling uart a mode select */
+
+#define EMCR_DUPLEX		0x00000001
+#define EMCR_PROMISC		0x00000002
+#define EMCR_PADEN		0x00000004
+#define EMCR_RXOFF_MASK		0x000001f8
+#define EMCR_RXOFF_SHIFT	3
+#define EMCR_RAMPAR		0x00000200
+#define EMCR_BADPAR		0x00000800
+#define EMCR_BUFSIZ		0x00001000
+#define EMCR_TXDMAEN		0x00002000
+#define EMCR_TXEN		0x00004000
+#define EMCR_RXDMAEN		0x00008000
+#define EMCR_RXEN		0x00010000
+#define EMCR_LOOPBACK		0x00020000
+#define EMCR_ARB_DIAG		0x001c0000
+#define EMCR_ARB_DIAG_IDLE	0x00200000
+#define EMCR_RST		0x80000000
+
+#define EISR_RXTIMERINT		0x00000001
+#define EISR_RXTHRESHINT	0x00000002
+#define EISR_RXOFLO		0x00000004
+#define EISR_RXBUFOFLO		0x00000008
+#define EISR_RXMEMERR		0x00000010
+#define EISR_RXPARERR		0x00000020
+#define EISR_TXEMPTY		0x00010000
+#define EISR_TXRTRY		0x00020000
+#define EISR_TXEXDEF		0x00040000
+#define EISR_TXLCOL		0x00080000
+#define EISR_TXGIANT		0x00100000
+#define EISR_TXBUFUFLO		0x00200000
+#define EISR_TXEXPLICIT		0x00400000
+#define EISR_TXCOLLWRAP		0x00800000
+#define EISR_TXDEFERWRAP	0x01000000
+#define EISR_TXMEMERR		0x02000000
+#define EISR_TXPARERR		0x04000000
+
+#define ERCSR_THRESH_MASK	0x000001ff	/* enet RX threshold */
+#define ERCSR_RX_TMR		0x40000000	/* simulation only */
+#define ERCSR_DIAG_OFLO		0x80000000	/* simulation only */
+
+#define ERBR_ALIGNMENT		4096
+#define ERBR_L_RXRINGBASE_MASK	0xfffff000
+
+#define ERBAR_BARRIER_BIT	0x0100
+#define ERBAR_RXBARR_MASK	0xffff0000
+#define ERBAR_RXBARR_SHIFT	16
+
+#define ERCIR_RXCONSUME_MASK	0x00000fff
+
+#define ERPIR_RXPRODUCE_MASK	0x00000fff
+#define ERPIR_ARM		0x80000000
+
+#define ERTR_CNT_MASK		0x000007ff
+
+#define ETCSR_IPGT_MASK		0x0000007f
+#define ETCSR_IPGR1_MASK	0x00007f00
+#define ETCSR_IPGR1_SHIFT	8
+#define ETCSR_IPGR2_MASK	0x007f0000
+#define ETCSR_IPGR2_SHIFT	16
+#define ETCSR_NOTXCLK		0x80000000
+
+#define ETCDC_COLLCNT_MASK	0x0000ffff
+#define ETCDC_DEFERCNT_MASK	0xffff0000
+#define ETCDC_DEFERCNT_SHIFT	16
+
+#define ETBR_ALIGNMENT		(64*1024)
+#define ETBR_L_RINGSZ_MASK	0x00000001
+#define ETBR_L_RINGSZ128	0
+#define ETBR_L_RINGSZ512	1
+#define ETBR_L_TXRINGBASE_MASK	0xffffc000
+
+#define ETCIR_TXCONSUME_MASK	0x0000ffff
+#define ETCIR_IDLE		0x80000000
+
+#define ETPIR_TXPRODUCE_MASK	0x0000ffff
+
+#define EBIR_TXBUFPROD_MASK	0x0000001f
+#define EBIR_TXBUFCONS_MASK	0x00001f00
+#define EBIR_TXBUFCONS_SHIFT	8
+#define EBIR_RXBUFPROD_MASK	0x007fc000
+#define EBIR_RXBUFPROD_SHIFT	14
+#define EBIR_RXBUFCONS_MASK	0xff800000
+#define EBIR_RXBUFCONS_SHIFT	23
+
+#define MICR_REGADDR_MASK	0x0000001f
+#define MICR_PHYADDR_MASK	0x000003e0
+#define MICR_PHYADDR_SHIFT	5
+#define MICR_READTRIG		0x00000400
+#define MICR_BUSY		0x00000800
+
+#define MIDR_DATA_MASK		0x0000ffff
+
+#define ERXBUF_IPCKSUM_MASK	0x0000ffff
+#define ERXBUF_BYTECNT_MASK	0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT	16
+#define ERXBUF_V		0x80000000
+
+#define ERXBUF_CRCERR		0x00000001	/* aka RSV15 */
+#define ERXBUF_FRAMERR		0x00000002	/* aka RSV14 */
+#define ERXBUF_CODERR		0x00000004	/* aka RSV13 */
+#define ERXBUF_INVPREAMB	0x00000008	/* aka RSV18 */
+#define ERXBUF_LOLEN		0x00007000	/* aka RSV2_0 */
+#define ERXBUF_HILEN		0x03ff0000	/* aka RSV12_3 */
+#define ERXBUF_MULTICAST	0x04000000	/* aka RSV16 */
+#define ERXBUF_BROADCAST	0x08000000	/* aka RSV17 */
+#define ERXBUF_LONGEVENT	0x10000000	/* aka RSV19 */
+#define ERXBUF_BADPKT		0x20000000	/* aka RSV20 */
+#define ERXBUF_GOODPKT		0x40000000	/* aka RSV21 */
+#define ERXBUF_CARRIER		0x80000000	/* aka RSV22 */
+
+#define ETXD_BYTECNT_MASK	0x000007ff	/* total byte count */
+#define ETXD_INTWHENDONE	0x00001000	/* intr when done */
+#define ETXD_D0V		0x00010000	/* data 0 valid */
+#define ETXD_B1V		0x00020000	/* buf 1 valid */
+#define ETXD_B2V		0x00040000	/* buf 2 valid */
+#define ETXD_DOCHECKSUM		0x00080000	/* insert ip cksum */
+#define ETXD_CHKOFF_MASK	0x07f00000	/* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT	20
+
+#define ETXD_D0CNT_MASK		0x0000007f
+#define ETXD_B1CNT_MASK		0x0007ff00
+#define ETXD_B1CNT_SHIFT	8
+#define ETXD_B2CNT_MASK		0x7ff00000
+#define ETXD_B2CNT_SHIFT	20
+
+typedef enum ioc3_subdevs_e {
+    ioc3_subdev_ether,
+    ioc3_subdev_generic,
+    ioc3_subdev_nic,
+    ioc3_subdev_kbms,
+    ioc3_subdev_ttya,
+    ioc3_subdev_ttyb,
+    ioc3_subdev_ecpp,
+    ioc3_subdev_rt,
+    ioc3_nsubdevs
+} ioc3_subdev_t;
+
+/* subdevice disable bits,
+ * from the standard INFO_LBL_SUBDEVS
+ */
+#define IOC3_SDB_ETHER		(1<<ioc3_subdev_ether)
+#define IOC3_SDB_GENERIC	(1<<ioc3_subdev_generic)
+#define IOC3_SDB_NIC		(1<<ioc3_subdev_nic)
+#define IOC3_SDB_KBMS		(1<<ioc3_subdev_kbms)
+#define IOC3_SDB_TTYA		(1<<ioc3_subdev_ttya)
+#define IOC3_SDB_TTYB		(1<<ioc3_subdev_ttyb)
+#define IOC3_SDB_ECPP		(1<<ioc3_subdev_ecpp)
+#define IOC3_SDB_RT		(1<<ioc3_subdev_rt)
+
+#define IOC3_ALL_SUBDEVS	((1<<ioc3_nsubdevs)-1)
+
+#define IOC3_SDB_SERIAL		(IOC3_SDB_TTYA|IOC3_SDB_TTYB)
+
+#define IOC3_STD_SUBDEVS	IOC3_ALL_SUBDEVS
+
+#define IOC3_INTA_SUBDEVS	IOC3_SDB_ETHER
+#define IOC3_INTB_SUBDEVS	(IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
+
+/*
+ * PCI Configuration Space Register Address Map, use offset from IOC3 PCI
+ * configuration base such that this can be used for multiple IOC3s
+ */
+#define IOC3_PCI_ID		0x0	/* ID */
+
+#define IOC3_VENDOR_ID_NUM	0x10A9
+#define IOC3_DEVICE_ID_NUM	0x0003
+
+#endif /* IOC3_H */
diff --git a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h
new file mode 100644
index 000000000..05edeb08a
--- /dev/null
+++ b/include/asm-ia64/sn/ioerror.h
@@ -0,0 +1,194 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_IOERROR_H
+#define _ASM_SN_IOERROR_H
+
+
+/*
+ * Macros defining the various Errors to be handled as part of
+ * IO Error handling.
+ */
+
+/*
+ * List of errors to be handled by each subsystem.
+ * "error_code" field will take one of these values.
+ * The error code is built up of single bits expressing
+ * our confidence that the error was that type; note
+ * that it is possible to have a PIO or DMA error where
+ * we don't know whether it was a READ or a WRITE, or
+ * even a READ or WRITE error that we're not sure whether
+ * to call a PIO or DMA.
+ *
+ * It is also possible to set both PIO and DMA, and possible
+ * to set both READ and WRITE; the first may be nonsensical
+ * but the second *could* be used to designate an access
+ * that is known to be a read-modify-write cycle. It is
+ * quite possible that nobody will ever use PIO|DMA or
+ * READ|WRITE ... but being flexible is good.
+ */
+#define	IOECODE_UNSPEC		0
+#define	IOECODE_READ		1
+#define	IOECODE_WRITE		2
+#define	IOECODE_PIO		4
+#define	IOECODE_DMA		8
+
+#define	IOECODE_PIO_READ	(IOECODE_PIO|IOECODE_READ)
+#define	IOECODE_PIO_WRITE	(IOECODE_PIO|IOECODE_WRITE)
+#define	IOECODE_DMA_READ	(IOECODE_DMA|IOECODE_READ)
+#define	IOECODE_DMA_WRITE	(IOECODE_DMA|IOECODE_WRITE)
+
+/* support older names, but try to move everything
+ * to using new names that identify which package
+ * controls their values ...
+ */
+#define	PIO_READ_ERROR		IOECODE_PIO_READ
+#define	PIO_WRITE_ERROR		IOECODE_PIO_WRITE
+#define	DMA_READ_ERROR		IOECODE_DMA_READ
+#define	DMA_WRITE_ERROR		IOECODE_DMA_WRITE
+
+/*
+ * List of error numbers returned by error handling sub-system.
+ */
+
+#define	IOERROR_HANDLED		0	/* Error Properly handled.        */
+#define	IOERROR_NODEV		0x1	/* No such device attached        */
+#define	IOERROR_BADHANDLE	0x2	/* Received bad handle            */
+#define	IOERROR_BADWIDGETNUM	0x3	/* Bad widget number              */
+#define	IOERROR_BADERRORCODE	0x4	/* Bad error code passed in       */
+#define	IOERROR_INVALIDADDR	0x5	/* Invalid address specified      */
+
+#define	IOERROR_WIDGETLEVEL	0x6	/* Some failure at widget level    */
+#define	IOERROR_XTALKLEVEL	0x7
+
+#define	IOERROR_HWGRAPH_LOOKUP	0x8	/* hwgraph lookup failed for path  */
+#define	IOERROR_UNHANDLED	0x9	/* handler rejected error          */
+
+#define	IOERROR_PANIC		0xA	/* subsidiary handler has already
+					 * started decode: continue error
+					 * data dump, and panic from top
+					 * caller in error chain.
+					 */
+
+/*
+ * IO errors at the bus/device driver level
+ */
+
+#define	IOERROR_DEV_NOTFOUND	0x10	/* Device matching bus addr not found */
+#define	IOERROR_DEV_SHUTDOWN	0x11	/* Device has been shutdown        */
+
+/*
+ * Type of address.
+ * Indicates the direction of transfer that caused the error.
+ */
+#define	IOERROR_ADDR_PIO	1	/* Error Address generated due to PIO */
+#define	IOERROR_ADDR_DMA	2	/* Error address generated due to DMA */
+
+/*
+ * IO error structure.
+ *
+ * This structure would expand to hold the information retrieved from
+ * all IO related error registers.
+ *
+ * This structure is defined to hold all system specific
+ * information related to a single error.
+ *
+ * This serves a couple of purpose.
+ *      - Error handling often involves translating one form of address to other
+ *        form. So, instead of having different data structures at each level,
+ *        we have a single structure, and the appropriate fields get filled in
+ *        at each layer.
+ *      - This provides a way to dump all error related information in any layer
+ *        of erorr handling (debugging aid).
+ *
+ * A second possibility is to allow each layer to define its own error
+ * data structure, and fill in the proper fields. This has the advantage
+ * of isolating the layers.
+ * A big concern is the potential stack usage (and overflow), if each layer
+ * defines these structures on stack (assuming we don't want to do kmalloc.
+ *
+ * Any layer wishing to pass extra information to a layer next to it in
+ * error handling hierarchy, can do so as a separate parameter.
+ */
+
+typedef struct io_error_s {
+    /* Bit fields indicating which sturcture fields are valid */
+    union {
+	struct {
+	    unsigned                ievb_errortype:1;
+	    unsigned                ievb_widgetnum:1;
+	    unsigned                ievb_widgetdev:1;
+	    unsigned                ievb_srccpu:1;
+	    unsigned                ievb_srcnode:1;
+	    unsigned                ievb_errnode:1;
+	    unsigned                ievb_sysioaddr:1;
+	    unsigned                ievb_xtalkaddr:1;
+	    unsigned                ievb_busspace:1;
+	    unsigned                ievb_busaddr:1;
+	    unsigned                ievb_vaddr:1;
+	    unsigned                ievb_memaddr:1;
+	    unsigned		    ievb_epc:1;
+	    unsigned		    ievb_ef:1;
+	} iev_b;
+	unsigned                iev_a;
+    } ie_v;
+
+    short                   ie_errortype;	/* error type: extra info about error */
+    short                   ie_widgetnum;	/* Widget number that's in error */
+    short                   ie_widgetdev;	/* Device within widget in error */
+    cpuid_t                 ie_srccpu;	/* CPU on srcnode generating error */
+    cnodeid_t               ie_srcnode;		/* Node which caused the error   */
+    cnodeid_t               ie_errnode;		/* Node where error was noticed  */
+    iopaddr_t               ie_sysioaddr;	/* Sys specific IO address       */
+    iopaddr_t               ie_xtalkaddr;	/* Xtalk (48bit) addr of Error   */
+    iopaddr_t               ie_busspace;	/* Bus specific address space    */
+    iopaddr_t               ie_busaddr;		/* Bus specific address          */
+    caddr_t                 ie_vaddr;	/* Virtual address of error      */
+    paddr_t                 ie_memaddr;		/* Physical memory address       */
+    caddr_t		    ie_epc;		/* pc when error reported	 */
+    caddr_t		    ie_ef;		/* eframe when error reported	 */
+
+} ioerror_t;
+
+#define	IOERROR_INIT(e)		do { (e)->ie_v.iev_a = 0; } while (0)
+#define	IOERROR_SETVALUE(e,f,v)	do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0)
+#define	IOERROR_FIELDVALID(e,f)	(((e)->ie_v.iev_b.ievb_ ## f) != 0)
+#define	IOERROR_GETVALUE(e,f)	(ASSERT(IOERROR_FIELDVALID(e,f)),((e)->ie_ ## f))
+
+#if	IP27 || IP35
+/* hub code likes to call the SysAD address "hubaddr" ... */
+#define	ie_hubaddr	ie_sysioaddr
+#define	ievb_hubaddr	ievb_sysioaddr
+#endif
+
+/*
+ * Error handling Modes.
+ */
+typedef enum {
+    MODE_DEVPROBE,		/* Probing mode. Errors not fatal */
+    MODE_DEVERROR,		/* Error while system is running */
+    MODE_DEVUSERERROR,		/* Device Error created due to user mode access */
+    MODE_DEVREENABLE		/* Reenable pass                */
+} ioerror_mode_t;
+
+
+typedef int             error_handler_f(void *, int, ioerror_mode_t, ioerror_t *);
+typedef void           *error_handler_arg_t;
+
+extern void             ioerror_dump(char *, int, int, ioerror_t *);
+
+#ifdef	ERROR_DEBUG
+#define	IOERROR_DUMP(x, y, z, t)	ioerror_dump((x), (y), (z), (t))
+#define	IOERR_PRINTF(x)	(x)
+#else
+#define	IOERROR_DUMP(x, y, z, t)
+#define	IOERR_PRINTF(x)
+#endif				/* ERROR_DEBUG */
+
+#endif				/* _ASM_SN_IOERROR_H */
diff --git a/include/asm-ia64/sn/ioerror_handling.h b/include/asm-ia64/sn/ioerror_handling.h
new file mode 100644
index 000000000..08186d183
--- /dev/null
+++ b/include/asm-ia64/sn/ioerror_handling.h
@@ -0,0 +1,319 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_IOERROR_HANDLING_H
+#define _ASM_SN_IOERROR_HANDLING_H
+
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+
+/*
+ * Basic types required for io error handling interfaces.
+ */
+
+/*
+ * Return code from the io error handling interfaces.
+ */
+
+enum error_return_code_e {
+	/* Success */
+	ERROR_RETURN_CODE_SUCCESS,
+
+	/* Unknown failure */
+	ERROR_RETURN_CODE_GENERAL_FAILURE,
+
+	/* Nth error noticed while handling the first error */
+	ERROR_RETURN_CODE_NESTED_CALL,
+
+	/* State of the vertex is invalid */
+	ERROR_RETURN_CODE_INVALID_STATE,
+
+	/* Invalid action */
+	ERROR_RETURN_CODE_INVALID_ACTION,
+
+	/* Valid action but not cannot set it */
+	ERROR_RETURN_CODE_CANNOT_SET_ACTION,
+
+	/* Valid action but not possible for the current state */
+	ERROR_RETURN_CODE_CANNOT_PERFORM_ACTION,
+
+	/* Valid state but cannot change the state of the vertex to it */
+	ERROR_RETURN_CODE_CANNOT_SET_STATE,
+
+	/* ??? */
+	ERROR_RETURN_CODE_DUPLICATE,
+
+	/* Reached the root of the system critical graph */
+	ERROR_RETURN_CODE_SYS_CRITICAL_GRAPH_BEGIN,
+
+	/* Reached the leaf of the system critical graph */
+	ERROR_RETURN_CODE_SYS_CRITICAL_GRAPH_ADD,
+
+	/* Cannot shutdown the device in hw/sw */
+	ERROR_RETURN_CODE_SHUTDOWN_FAILED,
+
+	/* Cannot restart the device in hw/sw */
+	ERROR_RETURN_CODE_RESET_FAILED,
+
+	/* Cannot failover the io subsystem */
+	ERROR_RETURN_CODE_FAILOVER_FAILED,
+
+	/* No Jump Buffer exists */
+	ERROR_RETURN_CODE_NO_JUMP_BUFFER
+};
+
+typedef uint64_t  error_return_code_t;
+
+/*
+ * State of the vertex during error handling.
+ */
+enum error_state_e {
+	/* Ignore state */
+	ERROR_STATE_IGNORE,
+
+	/* Invalid state */
+	ERROR_STATE_NONE,
+
+	/* Trying to decipher the error bits */
+	ERROR_STATE_LOOKUP,
+
+	/* Trying to carryout the action decided upon after
+	 * looking at the error bits 
+	 */
+	ERROR_STATE_ACTION,
+
+	/* Donot allow any other operations to this vertex from
+	 * other parts of the kernel. This is also used to indicate
+	 * that the device has been software shutdown.
+	 */
+	ERROR_STATE_SHUTDOWN,
+
+	/* This is a transitory state when no new requests are accepted
+	 * on behalf of the device. This is usually used when trying to
+	 * quiesce all the outstanding operations and preparing the
+	 * device for a failover / shutdown etc.
+	 */
+	ERROR_STATE_SHUTDOWN_IN_PROGRESS,
+
+	/* This is the state when there is absolutely no activity going
+	 * on wrt device.
+	 */
+	ERROR_STATE_SHUTDOWN_COMPLETE,
+	
+	/* This is the state when the device has issued a retry. */
+	ERROR_STATE_RETRY,
+
+	/* This is the normal state. This can also be used to indicate
+	 * that the device has been software-enabled after software-
+	 * shutting down previously.
+	 */
+	ERROR_STATE_NORMAL
+	
+};
+
+typedef uint64_t  error_state_t;
+
+/*
+ * Generic error classes. This is used to classify errors after looking
+ * at the error bits and helpful in deciding on the action.
+ */
+enum error_class_e {
+	/* Unclassified error */
+	ERROR_CLASS_UNKNOWN,
+
+	/* LLP transmit error */
+	ERROR_CLASS_LLP_XMIT,
+
+	/* LLP receive error */
+	ERROR_CLASS_LLP_RECV,
+
+	/* Credit error */
+	ERROR_CLASS_CREDIT,
+
+	/* Timeout error */
+	ERROR_CLASS_TIMEOUT,
+
+	/* Access error */
+	ERROR_CLASS_ACCESS,
+
+	/* System coherency error */
+	ERROR_CLASS_SYS_COHERENCY,
+
+	/* Bad data error (ecc / parity etc) */
+	ERROR_CLASS_BAD_DATA,
+
+	/* Illegal request packet */
+	ERROR_CLASS_BAD_REQ_PKT,
+	
+	/* Illegal response packet */
+	ERROR_CLASS_BAD_RESP_PKT
+};
+
+typedef uint64_t  error_class_t;
+
+
+/* 
+ * Error context which the error action can use.
+ */
+typedef void			*error_context_t;
+#define ERROR_CONTEXT_IGNORE	((error_context_t)-1ll)
+
+
+/* 
+ * Error action type.
+ */
+typedef error_return_code_t 	(*error_action_f)( error_context_t);
+#define ERROR_ACTION_IGNORE	((error_action_f)-1ll)
+
+/* Typical set of error actions */
+typedef struct error_action_set_s {
+	error_action_f		eas_panic;
+	error_action_f		eas_shutdown;
+	error_action_f		eas_abort;
+	error_action_f		eas_retry;
+	error_action_f		eas_failover;
+	error_action_f		eas_log_n_ignore;
+	error_action_f		eas_reset;
+} error_action_set_t;
+
+
+/* Set of priorites for in case mutliple error actions/states
+ * are trying to be prescribed for a device.
+ * NOTE : The ordering below encapsulates the priorities. Highest value
+ * corresponds to highest priority.
+ */
+enum error_priority_e {
+	ERROR_PRIORITY_IGNORE,
+	ERROR_PRIORITY_NONE,
+	ERROR_PRIORITY_NORMAL,
+	ERROR_PRIORITY_LOG,
+	ERROR_PRIORITY_FAILOVER,
+	ERROR_PRIORITY_RETRY,
+	ERROR_PRIORITY_ABORT,
+	ERROR_PRIORITY_SHUTDOWN,
+	ERROR_PRIORITY_RESTART,
+	ERROR_PRIORITY_PANIC
+};
+
+typedef uint64_t  error_priority_t;
+
+/* Error state interfaces */
+#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
+extern error_return_code_t	error_state_set(devfs_handle_t,error_state_t);
+extern error_state_t		error_state_get(devfs_handle_t);
+#endif
+
+/* System critical graph interfaces */
+
+extern boolean_t		is_sys_critical_vertex(devfs_handle_t);
+extern devfs_handle_t		sys_critical_first_child_get(devfs_handle_t);
+extern devfs_handle_t		sys_critical_next_child_get(devfs_handle_t);
+extern devfs_handle_t		sys_critical_parent_get(devfs_handle_t);
+extern error_return_code_t	sys_critical_graph_vertex_add(devfs_handle_t,
+							     devfs_handle_t new);
+
+/* Error action interfaces */
+
+extern error_return_code_t	error_action_set(devfs_handle_t,
+						 error_action_f,
+						 error_context_t,
+						 error_priority_t);
+extern error_return_code_t	error_action_perform(devfs_handle_t);
+
+
+#define INFO_LBL_ERROR_SKIP_ENV	"error_skip_env"
+
+#define v_error_skip_env_get(v, l)		\
+hwgraph_info_get_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t *)&l)
+
+#define v_error_skip_env_set(v, l, r)		\
+(r ? 						\
+ hwgraph_info_replace_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t)l,0) :\
+ hwgraph_info_add_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t)l))
+
+#define v_error_skip_env_clear(v)		\
+hwgraph_info_remove_LBL(v, INFO_LBL_ERROR_SKIP_ENV, 0)
+
+/* Skip point interfaces */
+extern error_return_code_t	error_skip_point_jump(devfs_handle_t, boolean_t);
+extern error_return_code_t	error_skip_point_clear(devfs_handle_t);
+
+/* REFERENCED */
+#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
+
+inline static int
+error_skip_point_mark(devfs_handle_t  v)  			 
+{									
+	label_t		*error_env = NULL;	 			
+	int		code = 0;		
+
+	/* Check if we have a valid hwgraph vertex */
+#ifdef IRIX
+	if (!dev_is_vertex(v))
+		return(code);
+#endif
+				
+	/* There is no error jump buffer for this device vertex. Allocate
+	 * one.								 
+	 */								 
+	if (v_error_skip_env_get(v, error_env) != GRAPH_SUCCESS) {	 
+		error_env = kmem_zalloc(sizeof(label_t), KM_NOSLEEP);	 
+		/* Unable to allocate memory for jum buffer. This should 
+		 * be a very rare occurrence.				 
+		 */							 
+		if (!error_env)						 
+			return(-1);					 
+		/* Store the jump buffer information on the vertex.*/	 
+		if (v_error_skip_env_set(v, error_env, 0) != GRAPH_SUCCESS)
+			return(-2);					   
+	}								   
+	ASSERT(v_error_skip_env_get(v, error_env) == GRAPH_SUCCESS);
+	code = setjmp(*error_env);					   
+#ifdef IRIX
+	/* NOTE: It might be OK to leave the allocated jump buffer on the
+	 * vertex. This can be used for later purposes.
+	 */
+	if (code) {							   
+		/* This is the case where a long jump has been taken from one
+		 * one of the error handling interfaces.		     
+		 */							     
+		if (v_error_skip_env_clear(v, error_env) == GRAPH_SUCCESS)   
+			kfree(error_env);
+	}								     
+#endif
+	return(code);							     
+}
+#endif	/* CONFIG_SGI_IO_ERROR_HANDLING */
+
+typedef uint64_t		counter_t;
+
+extern counter_t		error_retry_count_get(devfs_handle_t);
+extern error_return_code_t	error_retry_count_set(devfs_handle_t,counter_t);
+extern counter_t		error_retry_count_increment(devfs_handle_t);
+extern counter_t		error_retry_count_decrement(devfs_handle_t);
+
+/* Except for the PIO Read error typically the other errors are handled in
+ * the context of an asynchronous error interrupt.
+ */
+#define	IS_ERROR_INTR_CONTEXT(_ec)	((_ec & IOECODE_DMA) 		|| \
+					 (_ec == IOECODE_PIO_WRITE))
+
+/* Some convenience macros on device state. This state is accessed only 
+ * thru the calls the io error handling layer.
+ */
+#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
+#define IS_DEVICE_SHUTDOWN(_d) 	(error_state_get(_d) == ERROR_STATE_SHUTDOWN)
+#else
+extern boolean_t		is_device_shutdown(devfs_handle_t);
+#define IS_DEVICE_SHUTDOWN(_d) 	(is_device_shutdown(_d))
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_SN_IOERROR_HANDLING_H */
diff --git a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h
new file mode 100644
index 000000000..bce1129a8
--- /dev/null
+++ b/include/asm-ia64/sn/iograph.h
@@ -0,0 +1,200 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_IOGRAPH_H
+#define _ASM_SN_IOGRAPH_H
+
+/*
+ * During initialization, platform-dependent kernel code establishes some
+ * basic elements of the hardware graph.  This file contains edge and
+ * info labels that are used across various platforms -- it serves as an
+ * ad-hoc registry.
+ */
+
+/* edges names */
+#define EDGE_LBL_BUS			"bus"
+#define EDGE_LBL_CONN			".connection"
+#define EDGE_LBL_ECP			"ecp"		/* EPP/ECP plp */
+#define EDGE_LBL_ECPP			"ecpp"
+#define EDGE_LBL_GUEST			".guest"	/* For IOC3 */
+#define EDGE_LBL_HOST			".host"		/* For IOC3 */
+#define EDGE_LBL_PERFMON		"mon"
+#define EDGE_LBL_USRPCI			"usrpci"
+#define EDGE_LBL_VME			"vmebus"
+#define EDGE_LBL_BLOCK			"block"
+#define EDGE_LBL_BOARD			"board"
+#define EDGE_LBL_CHAR			"char"
+#define EDGE_LBL_CONTROLLER		"controller"
+#define EDGE_LBL_CPU			"cpu"
+#define EDGE_LBL_CPUNUM			"cpunum"
+#define EDGE_LBL_DISABLED		"disabled"
+#define EDGE_LBL_DISK			"disk"
+#define EDGE_LBL_DMA_ENGINE             "dma_engine"    /* Only available on
+							   VMEbus now        */
+#define EDGE_LBL_NET			"net"		/* all nw. devs */
+#define EDGE_LBL_EF			"ef"		/* For if_ef ethernet */
+#define EDGE_LBL_ET			"et"		/* For if_ee ethernet */
+#define EDGE_LBL_EC			"ec"		/* For if_ec2 ether */
+#define EDGE_LBL_ECF			"ec"		/* For if_ecf enet */
+#define EDGE_LBL_EM			"ec"		/* For O2 ether */
+#define EDGE_LBL_IPG			"ipg"		/* For IPG FDDI */
+#define EDGE_LBL_XPI			"xpi"		/* For IPG FDDI */
+#define EDGE_LBL_HIP			"hip"		/* For HIPPI */
+#define EDGE_LBL_GSN                    "gsn"           /* For GSN */
+#define EDGE_LBL_ATM			"atm"		/* For ATM */
+#define EDGE_LBL_FXP			"fxp"		/* For FXP ether */
+#define EDGE_LBL_EP			"ep"		/* For eplex ether */
+#define EDGE_LBL_VFE			"vfe"		/* For VFE ether */
+#define EDGE_LBL_GFE			"gfe"		/* For GFE ether */
+#define EDGE_LBL_RNS			"rns"		/* RNS PCI FDDI card */
+#define EDGE_LBL_MTR			"mtr"		/* MTR PCI 802.5 card */
+#define EDGE_LBL_FV			"fv"		/* FV VME 802.5 card */
+#define EDGE_LBL_GTR			"gtr"		/* GTR GIO 802.5 card */
+#define EDGE_LBL_ISDN                   "isdn"		/* Digi PCI ISDN-BRI card */
+
+#define EDGE_LBL_EISA			"eisa"
+#define EDGE_LBL_ENET			"ethernet"
+#define EDGE_LBL_FLOPPY			"floppy"
+#define EDGE_LBL_PFD			"pfd"		/* For O2 pfd floppy */
+#define EDGE_LBL_FOP                    "fop"           /* Fetchop pseudo device */
+#define EDGE_LBL_GIO			"gio"
+#define EDGE_LBL_HEART			"heart"		/* For RACER */
+#define EDGE_LBL_HPC			"hpc"
+#define EDGE_LBL_GFX			"gfx"
+#define EDGE_LBL_HUB			"hub"		/* For SN0 */
+#define EDGE_LBL_IBUS			"ibus"		/* For EVEREST */
+#define EDGE_LBL_INTERCONNECT		"link"
+#define EDGE_LBL_IO			"io"
+#define EDGE_LBL_IO4			"io4"		/* For EVEREST */
+#define EDGE_LBL_IOC3			"ioc3"
+#define EDGE_LBL_LUN                    "lun"
+#define EDGE_LBL_MACE                   "mace" 		/* O2 mace */
+#define EDGE_LBL_MACHDEP                "machdep"       /* Platform depedent devices */
+#define EDGE_LBL_MASTER			".master"
+#define EDGE_LBL_MEMORY			"memory"
+#define EDGE_LBL_META_ROUTER		"metarouter"
+#define EDGE_LBL_MIDPLANE		"midplane"
+#define EDGE_LBL_MODULE			"module"
+#define EDGE_LBL_NODE			"node"
+#define EDGE_LBL_NODENUM		"nodenum"
+#define EDGE_LBL_NVRAM			"nvram"
+#define EDGE_LBL_PARTITION		"partition"
+#define EDGE_LBL_PCI			"pci"
+#define EDGE_LBL_PORT			"port"
+#define EDGE_LBL_PROM			"prom"
+#define EDGE_LBL_RACK			"rack"
+#define EDGE_LBL_RDISK			"rdisk"
+#define EDGE_LBL_ROUTER			"router"
+#define EDGE_LBL_RPOS			"bay"		/* Position in rack */
+#define EDGE_LBL_SCSI			"scsi"
+#define EDGE_LBL_SCSI_CTLR		"scsi_ctlr"
+#define EDGE_LBL_SLOT			"slot"
+#define EDGE_LBL_TAPE			"tape"
+#define EDGE_LBL_TARGET                 "target"
+#define EDGE_LBL_UNKNOWN		"unknown"
+#define EDGE_LBL_VOLUME			"volume"
+#define EDGE_LBL_VOLUME_HEADER		"volume_header"
+#define EDGE_LBL_XBOW			"xbow"
+#define	EDGE_LBL_XIO			"xio"
+#define EDGE_LBL_XSWITCH		".xswitch"
+#define EDGE_LBL_XTALK			"xtalk"
+#define EDGE_LBL_XWIDGET		"xwidget"
+#define EDGE_LBL_ELSC			"elsc"
+#define EDGE_LBL_L1			"L1"
+#define EDGE_LBL_MADGE_TR               "Madge-tokenring"
+#define EDGE_LBL_XPLINK			"xplink" 	/* Cross partition */
+#define	EDGE_LBL_XPLINK_NET		"net" 		/* XP network devs */
+#define	EDGE_LBL_XPLINK_RAW		"raw"		/* XP Raw devs */
+#define	EDGE_LBL_XPLINK_KERNEL		"kernel"	/* XP kernel devs */
+#define	EDGE_LBL_XPLINK_ADMIN		"admin"	   	/* Partition admin */
+#define	EDGE_LBL_KAIO			"kaio"	   	/* Kernel async i/o poll */
+#define EDGE_LBL_RPS                    "rps"           /* redundant power supply */ 
+#define EDGE_LBL_XBOX_RPS               "xbox_rps"      /* redundant power supply for xbox unit */ 
+#define EDGE_LBL_IOBRICK		"iobrick"
+#define EDGE_LBL_PBRICK			"pbrick"
+#define EDGE_LBL_IBRICK			"ibrick"
+#define EDGE_LBL_XBRICK			"xbrick"
+#define EDGE_LBL_CPUBUS			"cpubus"	/* CPU Interfaces (SysAd) */
+
+/* vertex info labels in hwgraph */
+#define INFO_LBL_CNODEID		"_cnodeid"
+#define INFO_LBL_CONTROLLER_NAME	"_controller_name"
+#define INFO_LBL_CPUBUS			"_cpubus"
+#define INFO_LBL_CPUID			"_cpuid"
+#define INFO_LBL_CPU_INFO		"_cpu"
+#define INFO_LBL_DETAIL_INVENT		"_detail_invent" /* inventory data*/
+#define INFO_LBL_DEVICE_DESC		"_device_desc"
+#define INFO_LBL_DIAGVAL                "_diag_reason"   /* Reason disabled */
+#define INFO_LBL_DKIOTIME		"_dkiotime"
+#define INFO_LBL_DRIVER			"_driver"	/* points to attached device_driver_t */
+#define INFO_LBL_ELSC			"_elsc"
+#define INFO_LBL_FC_PORTNAME		"_fc_portname"
+#define INFO_LBL_GIOIO			"_gioio"
+#define INFO_LBL_GFUNCS			"_gioio_ops"	/* ops vector for gio providers */
+#define INFO_LBL_HUB_INFO		"_hubinfo"
+#define INFO_LBL_HWGFSLIST		"_hwgfs_list"
+#define INFO_LBL_TRAVERSE		"_hwg_traverse" /* hwgraph traverse function */
+#define INFO_LBL_INVENT 		"_invent"	/* inventory data */
+#define INFO_LBL_MLRESET		"_mlreset"	/* present if device preinitialized */
+#define INFO_LBL_MODULE_INFO		"_module"	/* module data ptr */
+#define INFO_LBL_MONDATA		"_mon"		/* monitor data ptr */
+#define INFO_LBL_MDPERF_DATA		"_mdperf"	/* mdperf monitoring*/
+#define INFO_LBL_NIC			"_nic"
+#define INFO_LBL_NODE_INFO		"_node"
+#define	INFO_LBL_PCIBR_HINTS		"_pcibr_hints"
+#define INFO_LBL_PCIIO			"_pciio"
+#define INFO_LBL_PFUNCS			"_pciio_ops"	/* ops vector for gio providers */
+#define INFO_LBL_PERMISSIONS		"_permissions"	/* owner, uid, gid */
+#define INFO_LBL_ROUTER_INFO		"_router"
+#define INFO_LBL_SUBDEVS		"_subdevs"	/* subdevice enable bits */
+#define INFO_LBL_VME_FUNCS		"_vmeio_ops"	/* ops vector for VME providers */
+#define INFO_LBL_XSWITCH		"_xswitch"
+#define INFO_LBL_XSWITCH_ID		"_xswitch_id"
+#define INFO_LBL_XSWITCH_VOL		"_xswitch_volunteer"
+#define INFO_LBL_XFUNCS			"_xtalk_ops"	/* ops vector for gio providers */
+#define INFO_LBL_XWIDGET		"_xwidget"
+#define INFO_LBL_GRIO_DSK		"_grio_disk"	/* guaranteed rate I/O */
+#define INFO_LBL_ASYNC_ATTACH           "_async_attach"	/* parallel attachment */
+#define INFO_LBL_GFXID			"_gfxid"	/* gfx pipe ID #s */
+/* Device/Driver  Admin directive labels  */
+#define ADMIN_LBL_INTR_TARGET		"INTR_TARGET"	/* Target cpu for device interrupts*/
+#define ADMIN_LBL_INTR_SWLEVEL		"INTR_SWLEVEL"	/* Priority level of the ithread */
+
+#define	ADMIN_LBL_DMATRANS_NODE		"PCIBUS_DMATRANS_NODE" /* Node used for
+								* 32-bit Direct
+								* Mapping I/O
+								*/
+#define ADMIN_LBL_DISABLED		"DISABLE"	/* Device has been disabled */
+#define ADMIN_LBL_DETACH		"DETACH"	/* Device has been detached */
+
+#define ADMIN_LBL_THREAD_PRI		"thread_priority" 
+							/* Driver adminstrator
+							 * hint parameter for 
+							 * thread priority
+							 */
+#define ADMIN_LBL_THREAD_CLASS		"thread_class" 
+							/* Driver adminstrator
+							 * hint parameter for 
+							 * thread priority
+							 * default class
+							 */
+/* Special reserved info labels (also hwgfs attributes) */
+#define _DEVNAME_ATTR		"_devname"	/* device name */
+#define _DRIVERNAME_ATTR	"_drivername"	/* driver name */
+#define _INVENT_ATTR		"_inventory"	/* device inventory data */
+#define _MASTERNODE_ATTR	"_masternode"	/* node that "controls" device */
+
+/* Info labels that begin with '_' cannot be overwritten by an attr_set call */
+#define INFO_LBL_RESERVED(name) ((name)[0] == '_')
+
+#if defined(__KERNEL__)
+void init_all_devices(void);
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SN_IOGRAPH_H */
diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
new file mode 100644
index 000000000..17819151a
--- /dev/null
+++ b/include/asm-ia64/sn/klconfig.h
@@ -0,0 +1,961 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef	_ASM_SN_KLCONFIG_H
+#define	_ASM_SN_KLCONFIG_H
+
+/*
+ * klconfig.h
+ */
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+/*
+ * WARNING:
+ *	Certain assembly language routines (notably xxxxx.s) in the IP27PROM 
+ *	will depend on the format of the data structures in this file.  In 
+ *      most cases, rearranging the fields can seriously break things.   
+ *      Adding fields in the beginning or middle can also break things.
+ *      Add fields if necessary, to the end of a struct in such a way
+ *      that offsets of existing fields do not change.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sn/types.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/router.h>
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn1/addrs.h>
+#include <asm/sn/vector.h>
+#include <asm/sn/agent.h>
+// #include <sys/graph.h>
+// #include <asm/sn/arc/types.h>
+#include <asm/sn/arc/hinv.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/kldir.h>
+#include <asm/sn/sn_fru.h>
+
+#endif  /* CONFIG_SGI_IP35 ... */
+
+#define KLCFGINFO_MAGIC	0xbeedbabe
+
+typedef s32 klconf_off_t;
+
+#define	MAX_MODULE_ID		255
+#define SIZE_PAD		4096 /* 4k padding for structures */
+#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP) /* MAX_SLOTS_PER_NODE??? */
+/* 
+ * 1 NODE brick, 2 Router bricks (1 local, 1 meta), 6 XIO Widgets, 
+ * 1 Midplane (midplane will likely become IO brick when Bruce cleans
+ * up IP35 klconfig)
+ */
+#define MAX_SLOTS_PER_NODE	(1 + 2 + 6 + 1) 
+#else
+/* 
+ * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets, 
+ * 2 Midplanes assuming no pci card cages 
+ */
+#define MAX_SLOTS_PER_NODE	(1 + 2 + 6 + 2) 
+#endif
+
+/* XXX if each node is guranteed to have some memory */
+
+#define MAX_PCI_DEVS		8
+
+/* lboard_t->brd_flags fields */
+/* All bits in this field are currently used. Try the pad fields if
+   you need more flag bits */
+
+#define ENABLE_BOARD 		0x01
+#define FAILED_BOARD  		0x02
+#define DUPLICATE_BOARD 	0x04    /* Boards like midplanes/routers which
+                                   	   are discovered twice. Use one of them */
+#define VISITED_BOARD		0x08	/* Used for compact hub numbering. */
+#define LOCAL_MASTER_IO6	0x10 	/* master io6 for that node */
+#define GLOBAL_MASTER_IO6	0x20
+#define THIRD_NIC_PRESENT 	0x40  	/* for future use */
+#define SECOND_NIC_PRESENT 	0x80 	/* addons like MIO are present */
+
+/* klinfo->flags fields */
+
+#define KLINFO_ENABLE 		0x01    /* This component is enabled */
+#define KLINFO_FAILED   	0x02 	/* This component failed */
+#define KLINFO_DEVICE   	0x04 	/* This component is a device */
+#define KLINFO_VISITED  	0x08 	/* This component has been visited */
+#define KLINFO_CONTROLLER   	0x10 	/* This component is a device controller */
+#define KLINFO_INSTALL   	0x20  	/* Install a driver */
+#define	KLINFO_HEADLESS		0x40	/* Headless (or hubless) component */
+#define IS_CONSOLE_IOC3(i)	((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
+
+#define GB2		0x80000000
+
+#define MAX_RSV_PTRS	32
+
+/* Structures to manage various data storage areas */
+/* The numbers must be contiguous since the array index i
+   is used in the code to allocate various areas. 
+*/
+
+#define BOARD_STRUCT 		0
+#define COMPONENT_STRUCT 	1
+#define ERRINFO_STRUCT 		2
+#define KLMALLOC_TYPE_MAX 	(ERRINFO_STRUCT + 1)
+#define DEVICE_STRUCT 		3
+
+
+typedef struct console_s {
+#if defined(CONFIG_IA64_SGI_IO)	/* FIXME */
+	__psunsigned_t 	uart_base;
+	__psunsigned_t 	config_base;
+	__psunsigned_t 	memory_base;
+#else
+	unsigned long 	uart_base;
+	unsigned long 	config_base;
+	unsigned long 	memory_base;
+#endif
+	short		baud;
+	short		flag;
+	int		type;
+	nasid_t		nasid;
+	char		wid;
+	char 		npci;
+	nic_t		baseio_nic;
+} console_t;
+
+typedef struct klc_malloc_hdr {
+        klconf_off_t km_base;
+        klconf_off_t km_limit;
+        klconf_off_t km_current;
+} klc_malloc_hdr_t;
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+	u64		ch_magic;	/* set this to KLCFGINFO_MAGIC */
+	u32		ch_version;    /* structure version number */
+	klconf_off_t	ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
+	klconf_off_t	ch_cons_off;       /* offset of ch_cons */
+	klconf_off_t	ch_board_info;	/* the link list of boards */
+	console_t	ch_cons_info;	/* address info of the console */
+	klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
+	confidence_t	ch_sw_belief;	/* confidence that software is bad*/
+	confidence_t	ch_sn0net_belief; /* confidence that sn0net is bad */
+} kl_config_hdr_t;
+
+
+#define KL_CONFIG_HDR(_nasid) 	((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+#define KL_CONFIG_INFO_OFFSET(_nasid)					\
+        (KL_CONFIG_HDR(_nasid)->ch_board_info)
+#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)				\
+        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
+
+#if !defined(SIMULATED_KLGRAPH)
+#define KL_CONFIG_INFO(_nasid) 						\
+        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?		\
+	 NODE_OFFSET_TO_K0((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
+	 0)
+#else
+/*
+ * For Fake klgraph info.
+ */
+extern kl_config_hdr_t *linux_klcfg;
+#define KL_CONFIG_INFO(_nasid) (lboard_t *)((ulong)linux_klcfg->ch_board_info | 0xe000000000000000)
+#endif	/* CONFIG_IA64_SGI_IO */
+
+#define KL_CONFIG_MAGIC(_nasid)		(KL_CONFIG_HDR(_nasid)->ch_magic)
+
+#define KL_CONFIG_CHECK_MAGIC(_nasid)					\
+        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
+
+#define KL_CONFIG_HDR_INIT_MAGIC(_nasid)	\
+                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
+
+/* --- New Macros for the changed kl_config_hdr_t structure --- */
+
+#if defined(CONFIG_IA64_SGI_IO)
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+			((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
+#else
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+			(unsigned long)_k + (_k->ch_malloc_hdr_off)))
+#endif
+
+#define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
+
+#if defined(CONFIG_IA64_SGI_IO)
+#define PTR_CH_CONS_INFO(_k)	((console_t *)\
+			((__psunsigned_t)_k + (_k->ch_cons_off)))
+#else
+#define PTR_CH_CONS_INFO(_k)	((console_t *)\
+			((unsigned long)_k + (_k->ch_cons_off)))
+#endif
+
+#define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
+
+/* ------------------------------------------------------------- */
+
+#define KL_CONFIG_INFO_START(_nasid)	\
+        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
+
+#define KL_CONFIG_BOARD_NASID(_brd)	((_brd)->brd_nasid)
+#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)	((_brd)->brd_next = (_off))
+
+#define KL_CONFIG_DUPLICATE_BOARD(_brd)	((_brd)->brd_flags & DUPLICATE_BOARD)
+
+#define XBOW_PORT_TYPE_HUB(_xbowp, _link) 	\
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
+#define XBOW_PORT_TYPE_IO(_xbowp, _link) 	\
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
+
+#define XBOW_PORT_IS_ENABLED(_xbowp, _link) 	\
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
+#define XBOW_PORT_NASID(_xbowp, _link) 	\
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
+
+#define XBOW_PORT_IO     0x1
+#define XBOW_PORT_HUB    0x2
+#define XBOW_PORT_ENABLE 0x4
+
+#define	SN0_PORT_FENCE_SHFT	0
+#define	SN0_PORT_FENCE_MASK	(1 << SN0_PORT_FENCE_SHFT)
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to 
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to 
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and 
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the 
+ * First board info on the remote node. The remote node list is 
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ * 
+ KLCONFIG
+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
+
+
+ +------------+
+ | board info |
+ +------------+       +--------------------------------+
+ | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
+ +------------+       +--------------------------------+
+ | compt 2    |--+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
+ | errinfo    |--+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has 
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accomodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error 
+ * information specific to the COMPONENT is present in the respective 
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the 
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is 
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where 
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info 
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes 
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR. 
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ * 
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+/*
+ * Values for CPU types
+ */
+#define KL_CPU_R4000		0x1	/* Standard R4000 */
+#define KL_CPU_TFP		0x2	/* TFP processor */
+#define	KL_CPU_R10000		0x3	/* R10000 (T5) */
+#define KL_CPU_NONE		(-1)	/* no cpu present in slot */
+
+/*
+ * IP27 BOARD classes
+ */
+
+#define KLCLASS_MASK	0xf0   
+#define KLCLASS_NONE	0x00
+#define KLCLASS_NODE	0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_CPU	KLCLASS_NODE	
+#define KLCLASS_IO	0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI 
+					    and the non-graphics widget boards */
+#define KLCLASS_ROUTER	0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
+#define KLCLASS_GFX	0x50		/* graphics boards */
+
+#define KLCLASS_PSEUDO_GFX	0x60	/* HDTV type cards that use a gfx
+					 * hw ifc to xtalk and are not gfx
+					 * class for sw purposes */
+
+#define KLCLASS_IOBRICK	0x70		/* IP35 iobrick */
+
+#define KLCLASS_MAX	7		/* Bump this if a new CLASS is added */
+#define KLTYPE_MAX	10		/* Bump this if a new CLASS is added */
+
+#define KLCLASS_UNKNOWN	0xf0
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+/*
+ * IP27 board types
+ */
+
+#define KLTYPE_MASK	0x0f
+#define KLTYPE_NONE	0x00
+#define KLTYPE_EMPTY	0x00
+
+#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
+#define KLTYPE_IP27	(KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define KLTYPE_IP35	KLTYPE_IP27
+#endif
+
+#define KLTYPE_WEIRDIO	(KLCLASS_IO  | 0x0)
+#define KLTYPE_BASEIO	(KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
+#define KLTYPE_IO6	KLTYPE_BASEIO       /* Additional name */
+#define KLTYPE_4CHSCSI	(KLCLASS_IO  | 0x2)
+#define KLTYPE_MSCSI	KLTYPE_4CHSCSI      /* Additional name */
+#define KLTYPE_ETHERNET	(KLCLASS_IO  | 0x3)
+#define KLTYPE_MENET	KLTYPE_ETHERNET     /* Additional name */
+#define KLTYPE_FDDI  	(KLCLASS_IO  | 0x4)
+#define KLTYPE_UNUSED	(KLCLASS_IO  | 0x5) /* XXX UNUSED */
+#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
+#define KLTYPE_PCI	KLTYPE_HAROLD
+#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
+#define KLTYPE_MIO   	(KLCLASS_IO  | 0x8)
+#define KLTYPE_FC    	(KLCLASS_IO  | 0x9)
+#define KLTYPE_LINC    	(KLCLASS_IO  | 0xA)
+#define KLTYPE_TPU    	(KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
+#define KLTYPE_GSN_A   	(KLCLASS_IO  | 0xC) /* Main GSN board */
+#define KLTYPE_GSN_B   	(KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
+
+#define KLTYPE_GFX	(KLCLASS_GFX | 0x0) /* unknown graphics type */
+#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
+#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
+
+#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_ROUTER2    KLTYPE_ROUTER		/* Obsolete! */
+#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+
+#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
+#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
+#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
+#define KLTYPE_PBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK		(KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_IBRICK		(KLCLASS_IOBRICK | 0x1)
+#define KLTYPE_PBRICK		(KLCLASS_IOBRICK | 0x2)
+#define KLTYPE_XBRICK		(KLCLASS_IOBRICK | 0x3)
+
+#define KLTYPE_PBRICK_BRIDGE	KLTYPE_PBRICK
+
+/* The value of type should be more than 8 so that hinv prints
+ * out the board name from the NIC string. For values less than
+ * 8 the name of the board needs to be hard coded in a few places.
+ * When bringup started nic names had not standardized and so we
+ * had to hard code. (For people interested in history.) 
+ */
+#define KLTYPE_XTHD   	(KLCLASS_PSEUDO_GFX | 0x9)
+
+#define KLTYPE_UNKNOWN	(KLCLASS_UNKNOWN | 0xf)
+
+#define KLTYPE(_x) 	((_x) & KLTYPE_MASK)
+#define IS_MIO_PRESENT(l)	((l->brd_type == KLTYPE_BASEIO) && \
+				 (l->brd_flags & SECOND_NIC_PRESENT))
+#define IS_MIO_IOC3(l,n)	(IS_MIO_PRESENT(l) && (n > 2))
+
+/* 
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+#define LOCAL_BOARD 1
+#define REMOTE_BOARD 2
+
+#define LBOARD_STRUCT_VERSION 	2
+
+typedef struct lboard_s {
+	klconf_off_t 	brd_next;         /* Next BOARD */
+	unsigned char 	struct_type;      /* type of structure, local or remote */
+	unsigned char 	brd_type;         /* type+class */
+	unsigned char 	brd_sversion;     /* version of this structure */
+        unsigned char 	brd_brevision;    /* board revision */
+        unsigned char 	brd_promver;      /* board prom version, if any */
+ 	unsigned char 	brd_flags;        /* Enabled, Disabled etc */
+	unsigned char 	brd_slot;         /* slot number */
+	unsigned short	brd_debugsw;      /* Debug switches */
+	moduleid_t	brd_module;       /* module to which it belongs */
+	partid_t 	brd_partition;    /* Partition number */
+        unsigned short 	brd_diagval;      /* diagnostic value */
+        unsigned short 	brd_diagparm;     /* diagnostic parameter */
+        unsigned char 	brd_inventory;    /* inventory history */
+        unsigned char 	brd_numcompts;    /* Number of components */
+        nic_t         	brd_nic;          /* Number in CAN */
+	nasid_t		brd_nasid;        /* passed parameter */
+	klconf_off_t 	brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+	klconf_off_t 	brd_errinfo;      /* Board's error information */
+	struct lboard_s *brd_parent;	  /* Logical parent for this brd */
+	devfs_handle_t	brd_graph_link;   /* vertex hdl to connect extern compts */
+	confidence_t	brd_confidence;	  /* confidence that the board is bad */
+	nasid_t		brd_owner;        /* who owns this board */
+	unsigned char 	brd_nic_flags;    /* To handle 8 more NICs */
+	char		brd_name[32];
+} lboard_t;
+
+
+/*
+ *	Make sure we pass back the calias space address for local boards.
+ *	klconfig board traversal and error structure extraction defines.
+ */
+
+#define BOARD_SLOT(_brd)	((_brd)->brd_slot)
+
+#define KLCF_CLASS(_brd)	KLCLASS((_brd)->brd_type)
+#define KLCF_TYPE(_brd)		KLTYPE((_brd)->brd_type)
+#define KLCF_REMOTE(_brd)  	(((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
+#define KLCF_NUM_COMPS(_brd)	((_brd)->brd_numcompts)
+#define KLCF_MODULE_ID(_brd)	((_brd)->brd_module)
+
+#ifndef SIMULATED_KLGRAPH
+#define KLCF_NEXT(_brd) 		((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next):  NULL)
+#define KLCF_COMP(_brd, _ndx)   \
+		(klinfo_t *)(NODE_OFFSET_TO_K0(NASID_GET(_brd), \
+						(_brd)->brd_compts[(_ndx)]))
+#define KLCF_COMP_ERROR(_brd, _comp)    \
+		(NODE_OFFSET_TO_K0(NASID_GET(_brd), (_comp)->errinfo))
+
+#else
+/*
+ * For fake klgraph info.
+ */
+#define KLCF_COMP(_brd, _ndx)           (klinfo_t *)((ulong) 0xe000000000000000 |((_brd)->brd_compts[(_ndx)]))
+#define KLCF_NEXT(_brd)	((_brd)->brd_next ? (lboard_t *)((ulong) 0xe000000000000000 | (_brd->brd_next)) : NULL)
+#define KLCF_COMP_ERROR(_brd, _comp)    (_brd = _brd , (_comp)->errinfo)
+
+#endif	/* SIMULATED_KLGRAPH */
+
+#define KLCF_COMP_TYPE(_comp)	((_comp)->struct_type)
+#define KLCF_BRIDGE_W_ID(_comp)	((_comp)->physid)	/* Widget ID */
+
+
+
+/*
+ * Generic info structure. This stores common info about a 
+ * component.
+ */
+ 
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        unsigned short  partid;		   /* widget part number */
+	nic_t 		nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+	unsigned char	widid;	          /* Widget id - if applicable */
+	nasid_t		nasid;            /* node number - from parent */
+	char		pad1;		  /* pad out structure. */
+	char		pad2;		  /* pad out structure. */
+	COMPONENT	*arcs_compt;      /* ptr to the arcs struct for ease*/
+        klconf_off_t	errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
+} klinfo_t ;
+
+#define KLCONFIG_INFO_ENABLED(_i)	((_i)->flags & KLINFO_ENABLE)
+/*
+ * Component structures.
+ * Following are the currently identified components:
+ * 	CPU, HUB, MEM_BANK, 
+ * 	XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
+ * 	BRIDGE, IOC3, SuperIO, SCSI, FDDI 
+ * 	ROUTER
+ * 	GRAPHICS
+ */
+#define KLSTRUCT_UNKNOWN	0
+#define KLSTRUCT_CPU  		1
+#define KLSTRUCT_HUB  		2
+#define KLSTRUCT_MEMBNK 	3
+#define KLSTRUCT_XBOW 		4
+#define KLSTRUCT_BRI 		5
+#define KLSTRUCT_IOC3 		6
+#define KLSTRUCT_PCI 		7
+#define KLSTRUCT_VME 		8
+#define KLSTRUCT_ROU		9
+#define KLSTRUCT_GFX 		10
+#define KLSTRUCT_SCSI 		11
+#define KLSTRUCT_FDDI 		12
+#define KLSTRUCT_MIO 		13
+#define KLSTRUCT_DISK 		14
+#define KLSTRUCT_TAPE 		15
+#define KLSTRUCT_CDROM 		16
+#define KLSTRUCT_HUB_UART 	17
+#define KLSTRUCT_IOC3ENET 	18
+#define KLSTRUCT_IOC3UART 	19
+#define KLSTRUCT_UNUSED		20 /* XXX UNUSED */
+#define KLSTRUCT_IOC3PCKM       21
+#define KLSTRUCT_RAD        	22
+#define KLSTRUCT_HUB_TTY        23
+#define KLSTRUCT_IOC3_TTY 	24
+
+/* Early Access IO proms are compatible
+   only with KLSTRUCT values upto 24. */
+
+#define KLSTRUCT_FIBERCHANNEL 	25
+#define KLSTRUCT_MOD_SERIAL_NUM 26
+#define KLSTRUCT_IOC3MS         27
+#define KLSTRUCT_TPU            28
+#define KLSTRUCT_GSN_A          29
+#define KLSTRUCT_GSN_B          30
+#define KLSTRUCT_XTHD           31
+
+/*
+ * These are the indices of various components within a lboard structure.
+ */
+
+#define IP27_CPU0_INDEX 0
+#define IP27_CPU1_INDEX 1
+#define IP27_HUB_INDEX 2
+#define IP27_MEM_INDEX 3
+
+#define BASEIO_BRIDGE_INDEX 0
+#define BASEIO_IOC3_INDEX 1
+#define BASEIO_SCSI1_INDEX 2
+#define BASEIO_SCSI2_INDEX 3
+
+#define MIDPLANE_XBOW_INDEX 0
+#define ROUTER_COMPONENT_INDEX 0
+
+#define CH4SCSI_BRIDGE_INDEX 0
+
+/* Info holders for various hardware components */
+
+typedef u64 *pci_t;
+typedef u64 *vmeb_t;
+typedef u64 *vmed_t;
+typedef u64 *fddi_t;
+typedef u64 *scsi_t;
+typedef u64 *mio_t;
+typedef u64 *graphics_t;
+typedef u64 *router_t;
+
+/*
+ * The port info in ip27_cfg area translates to a lboart_t in the 
+ * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
+ * is stored in terms of a nasid and a offset from start of KLCONFIG 
+ * area  on that nasid.
+ */
+typedef struct klport_s {
+	nasid_t		port_nasid;
+	unsigned char	port_flag;
+	klconf_off_t	port_offset;
+} klport_t;
+
+typedef struct klcpu_s {                          /* CPU */
+	klinfo_t 	cpu_info;
+	unsigned short 	cpu_prid;	/* Processor PRID value */
+	unsigned short 	cpu_fpirr;	/* FPU IRR value */
+    	unsigned short 	cpu_speed;	/* Speed in MHZ */
+    	unsigned short 	cpu_scachesz;	/* secondary cache size in MB */
+    	unsigned short 	cpu_scachespeed;/* secondary cache speed in MHz */
+} klcpu_t ;
+
+#define CPU_STRUCT_VERSION   2
+
+typedef struct klhub_s {			/* HUB */
+	klinfo_t 	hub_info;
+	uint 		hub_flags;		/* PCFG_HUB_xxx flags */
+	klport_t	hub_port;		/* hub is connected to this */
+	nic_t		hub_box_nic;		/* nic of containing box */
+	klconf_off_t	hub_mfg_nic;		/* MFG NIC string */
+	u64		hub_speed;		/* Speed of hub in HZ */
+} klhub_t ;
+
+typedef struct klhub_uart_s {			/* HUB */
+	klinfo_t 	hubuart_info;
+	uint 		hubuart_flags;		/* PCFG_HUB_xxx flags */
+	nic_t		hubuart_box_nic;	/* nic of containing box */
+} klhub_uart_t ;
+
+#define MEMORY_STRUCT_VERSION   2
+
+typedef struct klmembnk_s {			/* MEMORY BANK */
+	klinfo_t 	membnk_info;
+    	short 		membnk_memsz;		/* Total memory in megabytes */
+	short		membnk_dimm_select; /* bank to physical addr mapping*/
+	short		membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
+	short		membnk_attr;
+} klmembnk_t ;
+
+#define KLCONFIG_MEMBNK_SIZE(_info, _bank)	\
+                            ((_info)->membnk_bnksz[(_bank)])
+
+
+#define MEMBNK_PREMIUM 1
+#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)	\
+                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
+
+#define MAX_SERIAL_NUM_SIZE 10
+
+typedef struct klmod_serial_num_s {
+      klinfo_t        snum_info;
+      union {
+              char snum_str[MAX_SERIAL_NUM_SIZE];
+              unsigned long long       snum_int;
+      } snum;
+} klmod_serial_num_t;
+
+/* Macros needed to access serial number structure in lboard_t.
+   Hard coded values are necessary since we cannot treat 
+   serial number struct as a component without losing compatibility
+   between prom versions. */
+
+#define GET_SNUM_COMP(_l) 	((klmod_serial_num_t *)\
+				KLCF_COMP(_l, _l->brd_numcompts))
+
+#define MAX_XBOW_LINKS 16
+
+typedef struct klxbow_s {                          /* XBOW */
+	klinfo_t 	xbow_info ;
+    	klport_t	xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
+        int		xbow_master_hub_link;
+        /* type of brd connected+component struct ptr+flags */
+} klxbow_t ;
+
+#define MAX_PCI_SLOTS 8
+
+typedef struct klpci_device_s {
+	s32	pci_device_id;	/* 32 bits of vendor/device ID. */
+	s32	pci_device_pad;	/* 32 bits of padding. */
+} klpci_device_t;
+
+#define BRIDGE_STRUCT_VERSION	2
+
+typedef struct klbri_s {                          /* BRIDGE */
+	klinfo_t 	bri_info ;
+    	unsigned char	bri_eprominfo ;    /* IO6prom connected to bridge */
+    	unsigned char	bri_bustype ;      /* PCI/VME BUS bridge/GIO */
+    	pci_t    	pci_specific  ;    /* PCI Board config info */
+	klpci_device_t	bri_devices[MAX_PCI_DEVS] ;	/* PCI IDs */
+	klconf_off_t	bri_mfg_nic ;
+} klbri_t ;
+
+#define MAX_IOC3_TTY	2
+
+typedef struct klioc3_s {                          /* IOC3 */
+	klinfo_t 	ioc3_info ;
+    	unsigned char	ioc3_ssram ;        /* Info about ssram */
+    	unsigned char	ioc3_nvram ;        /* Info about nvram */
+    	klinfo_t	ioc3_superio ;      /* Info about superio */
+	klconf_off_t	ioc3_tty_off ;
+	klinfo_t	ioc3_enet ;
+	klconf_off_t	ioc3_enet_off ;
+	klconf_off_t	ioc3_kbd_off ;
+} klioc3_t ;
+
+#define MAX_VME_SLOTS 8
+
+typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
+	klinfo_t 	vmeb_info ;
+	vmeb_t		vmeb_specific ;
+    	klconf_off_t   	vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmeb_t ;
+
+typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
+	klinfo_t	vmed_info ;
+	vmed_t		vmed_specific ;
+    	klconf_off_t   	vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmed_t ;
+
+#define ROUTER_VECTOR_VERS	2
+
+/* XXX - Don't we need the number of ports here?!? */
+typedef struct klrou_s {                          /* ROUTER */
+	klinfo_t 	rou_info ;
+	uint		rou_flags ;           /* PCFG_ROUTER_xxx flags */
+	nic_t		rou_box_nic ;         /* nic of the containing module */
+    	klport_t 	rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
+	klconf_off_t	rou_mfg_nic ;     /* MFG NIC string */
+	u64	rou_vector;	  /* vector from master node */
+} klrou_t ;
+
+/*
+ *  Graphics Controller/Device
+ *
+ *  (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
+ *  used a couple different structures to store graphics information.
+ *  For compatibility reasons, the newer data structure preserves some
+ *  of the layout so that fields that are used in the old versions remain
+ *  in the same place (with the same info).  Determination of what version
+ *  of this structure we have is done by checking the cookie field.
+ */
+#define KLGFX_COOKIE	0x0c0de000
+
+typedef struct klgfx_s {		/* GRAPHICS Device */
+	klinfo_t 	gfx_info;
+	klconf_off_t    old_gndevs;	/* for compatibility with older proms */
+	klconf_off_t    old_gdoff0;	/* for compatibility with older proms */
+	uint		cookie;		/* for compatibility with older proms */
+	uint		moduleslot;
+	struct klgfx_s	*gfx_next_pipe;
+	graphics_t	gfx_specific;
+	klconf_off_t    pad0;		/* for compatibility with older proms */
+	klconf_off_t    gfx_mfg_nic;
+} klgfx_t;
+
+typedef struct klxthd_s {   
+	klinfo_t 	xthd_info ;
+	klconf_off_t	xthd_mfg_nic ;        /* MFG NIC string */
+} klxthd_t ;
+
+typedef struct kltpu_s {                     /* TPU board */
+	klinfo_t 	tpu_info ;
+	klconf_off_t	tpu_mfg_nic ;        /* MFG NIC string */
+} kltpu_t ;
+
+typedef struct klgsn_s {                     /* GSN board */
+	klinfo_t 	gsn_info ;
+	klconf_off_t	gsn_mfg_nic ;        /* MFG NIC string */
+} klgsn_t ;
+
+#define MAX_SCSI_DEVS 16
+
+/*
+ * NOTE: THis is the max sized kl* structure and is used in klmalloc.c
+ * to allocate space of type COMPONENT. Make sure that if the size of
+ * any other component struct becomes more than this, then redefine
+ * that as the size to be klmalloced.
+ */
+
+typedef struct klscsi_s {                          /* SCSI Controller */
+	klinfo_t 	scsi_info ;
+    	scsi_t       	scsi_specific   ; 
+	unsigned char 	scsi_numdevs ;
+	klconf_off_t	scsi_devinfo[MAX_SCSI_DEVS] ; 
+} klscsi_t ;
+
+typedef struct klscdev_s {                          /* SCSI device */
+	klinfo_t 	scdev_info ;
+	struct scsidisk_data *scdev_cfg ; /* driver fills up this */
+} klscdev_t ;
+
+typedef struct klttydev_s {                          /* TTY device */
+	klinfo_t 	ttydev_info ;
+	struct terminal_data *ttydev_cfg ; /* driver fills up this */
+} klttydev_t ;
+
+typedef struct klenetdev_s {                          /* ENET device */
+	klinfo_t 	enetdev_info ;
+	struct net_data *enetdev_cfg ; /* driver fills up this */
+} klenetdev_t ;
+
+typedef struct klkbddev_s {                          /* KBD device */
+	klinfo_t 	kbddev_info ;
+	struct keyboard_data *kbddev_cfg ; /* driver fills up this */
+} klkbddev_t ;
+
+typedef struct klmsdev_s {                          /* mouse device */
+        klinfo_t        msdev_info ;
+        void 		*msdev_cfg ; 
+} klmsdev_t ;
+
+#define MAX_FDDI_DEVS 10 /* XXX Is this true */
+
+typedef struct klfddi_s {                          /* FDDI */
+	klinfo_t 	fddi_info ;
+    	fddi_t        	fddi_specific ;       
+	klconf_off_t	fddi_devinfo[MAX_FDDI_DEVS] ;
+} klfddi_t ;
+
+typedef struct klmio_s {                          /* MIO */
+	klinfo_t 	mio_info ;
+    	mio_t       	mio_specific   ; 
+} klmio_t ;
+
+
+typedef union klcomp_s {
+	klcpu_t		kc_cpu;
+	klhub_t		kc_hub;
+	klmembnk_t 	kc_mem;
+	klxbow_t  	kc_xbow;
+	klbri_t		kc_bri;
+	klioc3_t	kc_ioc3;
+	klvmeb_t	kc_vmeb;
+	klvmed_t	kc_vmed;
+	klrou_t		kc_rou;
+	klgfx_t		kc_gfx;
+	klscsi_t	kc_scsi;
+	klscdev_t	kc_scsi_dev;
+	klfddi_t	kc_fddi;
+	klmio_t		kc_mio;
+	klmod_serial_num_t kc_snum ;
+} klcomp_t;
+
+typedef union kldev_s {      /* for device structure allocation */
+	klscdev_t	kc_scsi_dev ;
+	klttydev_t	kc_tty_dev ;
+	klenetdev_t	kc_enet_dev ;
+	klkbddev_t 	kc_kbd_dev ;
+} kldev_t ;
+
+/* Data structure interface routines. TBD */
+
+/* Include launch info in this file itself? TBD */
+
+/*
+ * TBD - Can the ARCS and device driver related info also be included in the
+ * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t 
+ * structure, viz private to the IO4prom.
+ */
+
+/* 
+ * TBD - Allocation issues. 
+ *
+ * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component, 
+ * errinfo and allocate from them, or have a single heap and allocate all 
+ * structures from it. Debug is easier in the former method since we can
+ * dump all similar structs in one command, but there will be lots of holes, 
+ * in memory and max limits are needed for number of structures.
+ * Another way to make it organized, is to have a union of all components
+ * and allocate a aligned chunk of memory greater than the biggest
+ * component.
+ */
+
+typedef union {
+	lboard_t *lbinfo ;
+} biptr_t ;
+
+
+#define BRI_PER_XBOW 6
+#define PCI_PER_BRI  8
+#define DEV_PER_PCI  16
+
+
+/* Virtual dipswitch values (starting from switch "7"): */
+
+#define VDS_NOGFX		0x8000	/* Don't enable gfx and autoboot */
+#define VDS_NOMP		0x100	/* Don't start slave processors */
+#define VDS_MANUMODE		0x80	/* Manufacturing mode */
+#define VDS_NOARB		0x40	/* No bootmaster arbitration */
+#define VDS_PODMODE		0x20	/* Go straight to POD mode */
+#define VDS_NO_DIAGS		0x10	/* Don't run any diags after BM arb */
+#define VDS_DEFAULTS		0x08	/* Use default environment values */
+#define VDS_NOMEMCLEAR		0x04	/* Don't run mem cfg code */
+#define VDS_2ND_IO4		0x02	/* Boot from the second IO4 */
+#define VDS_DEBUG_PROM		0x01	/* Print PROM debugging messages */
+
+/* external declarations of Linux kernel functions. */
+
+extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
+extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
+extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
+extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
+
+
+#if defined(CONFIG_IA64_SGI_IO)
+extern xwidgetnum_t nodevertex_widgetnum_get(devfs_handle_t node_vtx);
+extern devfs_handle_t nodevertex_xbow_peer_get(devfs_handle_t node_vtx);
+extern lboard_t *find_gfxpipe(int pipenum);
+extern void setup_gfxpipe_link(devfs_handle_t vhdl,int pipenum);
+extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
+extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
+                                               unsigned char brd_class);
+extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
+extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
+extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
+extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
+extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
+extern int	config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
+extern int	config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
+extern int	config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
+extern klcpu_t *get_cpuinfo(cpuid_t cpu);
+extern int 	update_klcfg_cpuinfo(nasid_t, int);
+extern void 	board_to_path(lboard_t *brd, char *path);
+extern moduleid_t get_module_id(nasid_t nasid);
+extern void 	nic_name_convert(char *old_name, char *new_name);
+extern int 	module_brds(nasid_t nasid, lboard_t **module_brds, int n);
+extern lboard_t *brd_from_key(uint64_t key);
+extern void 	device_component_canonical_name_get(lboard_t *,klinfo_t *,
+						    char *);
+extern int	board_serial_number_get(lboard_t *,char *);
+extern int	is_master_baseio(nasid_t,moduleid_t,slotid_t);
+extern nasid_t	get_actual_nasid(lboard_t *brd) ;
+extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
+#else	/* CONFIG_IA64_SGI_IO */
+extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
+#endif	/* CONFIG_IA64_SGI_IO */
+
+#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/include/asm-ia64/sn/kldir.h b/include/asm-ia64/sn/kldir.h
new file mode 100644
index 000000000..64db62f85
--- /dev/null
+++ b/include/asm-ia64/sn/kldir.h
@@ -0,0 +1,246 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_KLDIR_H
+#define _ASM_SN_KLDIR_H
+
+#include <linux/config.h>
+#if defined(CONFIG_IA64_SGI_IO)
+#include <asm/sn/sgi.h>
+#endif
+
+/*
+ * The kldir memory area resides at a fixed place in each node's memory and
+ * provides pointers to most other IP27 memory areas.  This allows us to
+ * resize and/or relocate memory areas at a later time without breaking all
+ * firmware and kernels that use them.  Indices in the array are
+ * permanently dedicated to areas listed below.  Some memory areas (marked
+ * below) reside at a permanently fixed location, but are included in the
+ * directory for completeness.
+ */
+
+#define KLDIR_MAGIC		0x434d5f53505f5357
+
+/*
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      IO6 TEXT/DATA/BSS/stack            |
+ * 0x1C00000 (30M)         +-----------------------------------------+
+ *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
+ * 0x0800000 (28M)         +-----------------------------------------+
+ *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
+ * 0x1B00000 (27M)         +-----------------------------------------+
+ *                         |      IP27 CFG                           |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Graphics PROM                      |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      3rd Party PROM drivers             |
+ * 0x1600000 (22M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x190000 (2M--)         +-----------------------------------------+
+ *                         |      SYMMON                             |
+ *                         |      (For UNIX Debug only)              |
+ * 0x34000 (208K)          +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x25000 (148K)          +-----------------------------------------+
+ *                         |      KLCONFIG - II (temp)               |
+ *                         |                                         |
+ *                         |    ----------------------------         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP27PROM, IO6PROM and IRIX.
+ *
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (32K)              |
+ *                         |                                         |
+ * 0x12000 (72K)           +-----------------------------------------+
+ *                         |      Unused                             |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Eframe area       	     |
+ * 0x11a00 (70.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Eframe area       	     |
+ * 0x11800 (70K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Register save area       |
+ * 0x11600 (69.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Register save area       |
+ * 0x11400 (69K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x11000 (68K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *			   |      kernel/io6prom nmi registers	     |
+ * 0x10800  (66k)	   +-----------------------------------------+
+ *			   |      cache error eframe   	 	     |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (UALIAS copy)   |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      KLCONFIG - I (permanent) (48K)     |
+ *                         |                                         |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x4000 (16K)            +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x3000 (12K)            +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x2c00 (11K)            +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x2800 (10K)            +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x2400 (9K)             +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x2000 (8K)             +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x1000 (4K)             +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *			   |      kernel/io6prom nmi registers	     |
+ * 0x800  (2k)	           +-----------------------------------------+
+ *			   |      cache error eframe   	 	     |
+ * 0x400 (1K)              +-----------------------------------------+
+ *                         |      Exception Handlers                 |
+ * 0x0   (0K)              +-----------------------------------------+
+ */
+
+#ifdef LANGUAGE_ASSEMBLY
+#define KLDIR_OFF_MAGIC			0x00
+#define KLDIR_OFF_OFFSET		0x08
+#define KLDIR_OFF_POINTER		0x10
+#define KLDIR_OFF_SIZE			0x18
+#define KLDIR_OFF_COUNT			0x20
+#define KLDIR_OFF_STRIDE		0x28
+#endif /* LANGUAGE_ASSEMBLY */
+
+#if !defined(CONFIG_IA64_SGI_IO)
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE		0x8000
+
+#if defined (PROM) || defined (SABLE)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP27
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET		0x2400
+#define IP27_LAUNCH_SIZE		0x400
+#define IP27_LAUNCH_COUNT		2
+#define IP27_LAUNCH_STRIDE		0x200
+
+#define IP27_KLCONFIG_OFFSET		0x4000
+#define IP27_KLCONFIG_SIZE		0xc000
+#define IP27_KLCONFIG_COUNT		1
+#define IP27_KLCONFIG_STRIDE		0
+
+#define IP27_NMI_OFFSET			0x3000
+#define IP27_NMI_SIZE			0x40
+#define IP27_NMI_COUNT			2
+#define IP27_NMI_STRIDE			0x40
+
+#define IP27_PI_ERROR_OFFSET		0x12000
+#define IP27_PI_ERROR_SIZE		0x4000
+#define IP27_PI_ERROR_COUNT		1
+#define IP27_PI_ERROR_STRIDE		0
+
+#define IP27_SYMMON_STK_OFFSET		0x25000
+#define IP27_SYMMON_STK_SIZE		0xe000
+#define IP27_SYMMON_STK_COUNT		2
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE		0x7000
+
+#define IP27_FREEMEM_OFFSET		0x19000
+#define IP27_FREEMEM_SIZE		-1
+#define IP27_FREEMEM_COUNT		1
+#define IP27_FREEMEM_STRIDE		0
+
+#endif /* PROM || SABLE*/
+/*
+ * There will be only one of these in a partition so the IO6 must set it up.
+ */
+#define IO6_GDA_OFFSET			0x11000
+#define IO6_GDA_SIZE			0x400
+#define IO6_GDA_COUNT			1
+#define IO6_GDA_STRIDE			0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET		0x11400
+#define IP27_NMI_KREGS_CPU_SIZE		0x200
+/*
+ * save area of kernel nmi regs in eframe format 
+ */
+#define IP27_NMI_EFRAME_OFFSET		0x11800
+#define IP27_NMI_EFRAME_SIZE		0x200
+
+#define KLDIR_ENT_SIZE			0x40
+#define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
+
+#endif	/* !CONFIG_IA64_SGI_IO */
+
+#ifdef _LANGUAGE_C
+typedef struct kldir_ent_s {
+	u64		magic;		/* Indicates validity of entry      */
+	off_t		offset;		/* Offset from start of node space  */
+#if defined(CONFIG_IA64_SGI_IO)	/* FIXME */
+	__psunsigned_t	pointer;	/* Pointer to area in some cases    */
+#else
+	unsigned long	pointer;	/* Pointer to area in some cases    */
+#endif
+	size_t		size;		/* Size in bytes 		    */
+	u64		count;		/* Repeat count if array, 1 if not  */
+	size_t		stride;		/* Stride if array, 0 if not        */
+	char		rsvd[16];	/* Pad entry to 0x40 bytes          */
+	/* NOTE: These 16 bytes are used in the Partition KLDIR
+	   entry to store partition info. Refer to klpart.h for this. */
+} kldir_ent_t;
+#endif /* _LANGUAGE_C */
+
+#if defined(CONFIG_IA64_SGI_IO)
+
+#define KLDIR_ENT_SIZE			0x40
+#define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
+
+/*
+ * The actual offsets of each memory area are machine-dependent
+ */
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/kldir.h>
+#else
+#error "kldir.h is currently defined for IP27 and IP35 platforms only"
+#endif
+
+#endif	/* CONFIG_IA64_SGI_IO */
+
+#endif /* _ASM_SN_KLDIR_H */
diff --git a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h
new file mode 100644
index 000000000..5d553e63a
--- /dev/null
+++ b/include/asm-ia64/sn/ksys/elsc.h
@@ -0,0 +1,163 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_KSYS_ELSC_H
+#define _ASM_SN_KSYS_ELSC_H
+
+#include <linux/config.h>
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/ksys/l1.h>
+#endif
+
+// #include <asm/sn/ksys/i2c.h>
+
+#define ELSC_I2C_ADDR		0x08
+#define ELSC_I2C_HUB0		0x09
+#define ELSC_I2C_HUB1		0x0a
+#define ELSC_I2C_HUB2		0x0b
+#define ELSC_I2C_HUB3		0x0c
+
+#define ELSC_PACKET_MAX		96
+#define ELSC_ACP_MAX		86		/* 84+cr+lf */
+#define ELSC_LINE_MAX		(ELSC_ACP_MAX - 2)
+
+/*
+ * ELSC character queue type for I/O
+ */
+
+#define ELSC_QSIZE	128		/* Power of 2 is more efficient */
+
+typedef sc_cq_t elsc_cq_t;
+
+/*
+ * ELSC structure passed around as handle
+ */
+
+typedef l1sc_t elsc_t;
+
+void	elsc_init(elsc_t *e, nasid_t nasid);
+
+int	elsc_process(elsc_t *e);
+int	elsc_msg_check(elsc_t *e, char *msg, int msg_max);
+int	elsc_msg_callback(elsc_t *e,
+			  void (*callback)(void *callback_data, char *msg),
+			  void *callback_data);
+#if 0
+char   *elsc_errmsg(int code);
+
+int	elsc_nvram_write(elsc_t *e, int addr, char *buf, int len);
+int	elsc_nvram_read(elsc_t *e, int addr, char *buf, int len);
+int	elsc_nvram_magic(elsc_t *e);
+#endif
+
+int	elsc_command(elsc_t *e, int only_if_message);
+int	elsc_parse(elsc_t *e, char *p1, char *p2, char *p3);
+int	elsc_ust_write(elsc_t *e, uchar_t c);
+int 	elsc_ust_read(elsc_t *e, char *c);
+
+
+
+/*
+ * System controller commands
+ */
+
+int	elsc_version(elsc_t *e, char *result);
+#if 0
+int	elsc_debug_set(elsc_t *e, u_char byte1, u_char byte2);
+int	elsc_debug_get(elsc_t *e, u_char *byte1, u_char *byte2);
+#endif
+int	elsc_module_set(elsc_t *e, int module);
+int	elsc_module_get(elsc_t *e);
+int	elsc_partition_set(elsc_t *e, int partition);
+int	elsc_partition_get(elsc_t *e);
+int	elsc_domain_set(elsc_t *e, int domain);
+int	elsc_domain_get(elsc_t *e);
+int	elsc_cluster_set(elsc_t *e, int cluster);
+int	elsc_cluster_get(elsc_t *e);
+int	elsc_cell_set(elsc_t *e, int cell);
+int	elsc_cell_get(elsc_t *e);
+int	elsc_bist_set(elsc_t *e, char bist_status);
+char	elsc_bist_get(elsc_t *e);
+int	elsc_lock(elsc_t *e,
+		  int retry_interval_usec,
+		  int timeout_usec, u_char lock_val);
+int	elsc_unlock(elsc_t *e);
+int	elsc_display_char(elsc_t *e, int led, int chr);
+int	elsc_display_digit(elsc_t *e, int led, int num, int l_case);
+#if 0
+int	elsc_display_mesg(elsc_t *e, char *chr);	/* 8-char input */
+int	elsc_password_set(elsc_t *e, char *password);	/* 4-char input */
+int	elsc_password_get(elsc_t *e, char *password);	/* 4-char output */
+int	elsc_rpwr_query(elsc_t *e, int is_master);
+int	elsc_power_query(elsc_t *e);
+int	elsc_power_down(elsc_t *e, int sec);
+int	elsc_power_cycle(elsc_t *e);
+int	elsc_system_reset(elsc_t *e);
+int	elsc_dip_switches(elsc_t *e);
+int	elsc_nic_get(elsc_t *e, uint64_t *nic, int verbose);
+#endif
+
+int	_elsc_hbt(elsc_t *e, int ival, int rdly);
+
+#define	elsc_hbt_enable(e, ival, rdly)	_elsc_hbt(e, ival, rdly)
+#define	elsc_hbt_disable(e)		_elsc_hbt(e, 0, 0)
+#define	elsc_hbt_send(e)		_elsc_hbt(e, 0, 1)
+
+/*
+ * Routines for using the ELSC as a UART.  There's a version of each
+ * routine that takes a pointer to an elsc_t, and another version that
+ * gets the pointer by calling a user-supplied global routine "get_elsc".
+ * The latter version is useful when the elsc is employed for stdio.
+ */
+
+#define ELSCUART_FLASH		0x3c			/* LED pattern */
+
+elsc_t	       *get_elsc(void);
+
+int	elscuart_probe(void);
+void	elscuart_init(void *);
+int	elscuart_poll(void);
+int	elscuart_readc(void);
+int	elscuart_getc(void);
+int	elscuart_putc(int);
+int	elscuart_puts(char *);
+char   *elscuart_gets(char *, int);
+int	elscuart_flush(void);
+
+
+
+/*
+ * Error codes
+ *
+ *   The possible ELSC error codes are a superset of the I2C error codes,
+ *   so ELSC error codes begin at -100.
+ */
+
+#define ELSC_ERROR_NONE			0
+
+#define ELSC_ERROR_CMD_SEND	       -100	/* Error sending command    */
+#define ELSC_ERROR_CMD_CHECKSUM	       -101	/* Command checksum bad     */
+#define ELSC_ERROR_CMD_UNKNOWN	       -102	/* Unknown command          */
+#define ELSC_ERROR_CMD_ARGS	       -103	/* Invalid argument(s)      */
+#define ELSC_ERROR_CMD_PERM	       -104	/* Permission denied	    */
+#define ELSC_ERROR_CMD_STATE	       -105	/* not allowed in this state*/
+
+#define ELSC_ERROR_RESP_TIMEOUT	       -110	/* ELSC response timeout    */
+#define ELSC_ERROR_RESP_CHECKSUM       -111	/* Response checksum bad    */
+#define ELSC_ERROR_RESP_FORMAT	       -112	/* Response format error    */
+#define ELSC_ERROR_RESP_DIR	       -113	/* Response direction error */
+
+#define ELSC_ERROR_MSG_LOST	       -120	/* Queue full; msg. lost    */
+#define ELSC_ERROR_LOCK_TIMEOUT	       -121	/* ELSC response timeout    */
+#define ELSC_ERROR_DATA_SEND	       -122	/* Error sending data       */
+#define ELSC_ERROR_NIC		       -123	/* NIC processing error     */
+#define ELSC_ERROR_NVMAGIC	       -124	/* Bad magic no. in NVRAM   */
+#define ELSC_ERROR_MODULE	       -125	/* Moduleid processing err  */
+
+#endif /* _ASM_SN_KSYS_ELSC_H */
diff --git a/include/asm-ia64/sn/ksys/i2c.h b/include/asm-ia64/sn/ksys/i2c.h
new file mode 100644
index 000000000..f350d2186
--- /dev/null
+++ b/include/asm-ia64/sn/ksys/i2c.h
@@ -0,0 +1,77 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_KSYS_I2C_H
+#define _ASM_SN_KSYS_I2C_H
+
+#if _STANDALONE
+# include "rtc.h"
+#else
+# define rtc_time()	(GET_LOCAL_RTC * NSEC_PER_CYCLE / 1000)
+# define rtc_sleep	us_delay
+# define rtc_time_t	uint64_t
+#endif
+
+typedef u_char			i2c_addr_t;	/* 7-bit address            */
+
+int		i2c_init(nasid_t);
+
+int		i2c_probe(nasid_t nasid, rtc_time_t timeout);
+
+int		i2c_arb(nasid_t, rtc_time_t timeout, rtc_time_t *token_start);
+
+int		i2c_master_xmit(nasid_t,
+				i2c_addr_t addr,
+				u_char *buf,
+				int len_max,
+				int *len_ptr,
+				rtc_time_t timeout,
+				int only_if_message);
+
+int		i2c_master_recv(nasid_t,
+				i2c_addr_t addr,
+				u_char *buf,
+				int len_max,
+				int *len_ptr,
+				int emblen,
+				rtc_time_t timeout,
+				int only_if_message);
+
+int		i2c_master_xmit_recv(nasid_t,
+				     i2c_addr_t addr,
+				     u_char *xbuf,
+				     int xlen_max,
+				     int *xlen_ptr,
+				     u_char *rbuf,
+				     int rlen_max,
+				     int *rlen_ptr,
+				     int emblen,
+				     rtc_time_t timeout,
+				     int only_if_message);
+
+char	       *i2c_errmsg(int code);
+
+/*
+ * Error codes
+ */
+
+#define I2C_ERROR_NONE		 0
+#define I2C_ERROR_INIT		-1	/* Initialization error             */
+#define I2C_ERROR_STATE		-2	/* Unexpected chip state	    */
+#define I2C_ERROR_NAK		-3	/* Addressed slave not responding   */
+#define I2C_ERROR_TO_ARB	-4	/* Timeout waiting for sysctlr arb  */
+#define I2C_ERROR_TO_BUSY	-5	/* Timeout waiting for busy bus     */
+#define I2C_ERROR_TO_SENDA	-6	/* Timeout sending address byte     */
+#define I2C_ERROR_TO_SENDD	-7	/* Timeout sending data byte        */
+#define I2C_ERROR_TO_RECVA	-8	/* Timeout receiving address byte   */
+#define I2C_ERROR_TO_RECVD	-9	/* Timeout receiving data byte      */
+#define I2C_ERROR_NO_MESSAGE	-10	/* No message was waiting	    */
+#define I2C_ERROR_NO_ELSC	-11	/* ELSC is disabled for access 	    */ 	
+
+#endif /* _ASM_SN_KSYS_I2C_H */
diff --git a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h
new file mode 100644
index 000000000..773459cde
--- /dev/null
+++ b/include/asm-ia64/sn/ksys/l1.h
@@ -0,0 +1,375 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_KSYS_L1_H
+#define _ASM_SN_KSYS_L1_H
+
+#include <asm/sn/vector.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn1/bedrock.h>
+
+#define BRL1_QSIZE	128	/* power of 2 is more efficient */
+#define BRL1_BUFSZ	264	/* needs to be large enough
+				 * to hold 2 flags, escaped
+				 * CRC, type/subchannel byte,
+				 * and escaped payload
+				 */
+
+#define BRL1_IQS          32
+#define BRL1_OQS          4
+
+
+typedef struct sc_cq_s {
+    u_char              buf[BRL1_QSIZE];
+    int                 ipos, opos, tent_next;
+} sc_cq_t;
+
+/* An l1sc_t struct can be associated with the local (C-brick) L1 or an L1
+ * on an R-brick.  In the R-brick case, the l1sc_t records a vector path
+ * to the R-brick's junk bus UART.  In the C-brick case, we just use the
+ * following flag to denote the local uart.
+ *
+ * This value can't be confused with a network vector because the least-
+ * significant nibble of a network vector cannot be greater than 8.
+ */
+#define BRL1_LOCALUART	((net_vec_t)0xf)
+
+/* L1<->Bedrock reserved subchannels */
+
+/* console channels */
+#define SC_CONS_CPU0    0x00
+#define SC_CONS_CPU1    0x01
+#define SC_CONS_CPU2    0x02
+#define SC_CONS_CPU3    0x03
+
+#define L1_ELSCUART_SUBCH(p)	(p)
+#define L1_ELSCUART_CPU(ch)	(ch)
+
+#define SC_CONS_SYSTEM  CPUS_PER_NODE
+
+/* mapping subchannels to queues */
+#define MAP_IQ(s)       (s)
+#define MAP_OQ(s)       (s)
+     
+#define BRL1_NUM_SUBCHANS 32
+#define BRL1_CMD_SUBCH	  16
+#define BRL1_EVENT_SUBCH  (BRL1_NUM_SUBCHANS - 1)
+#define BRL1_SUBCH_RSVD   0
+#define BRL1_SUBCH_FREE   (-1)
+
+/* constants for L1 hwgraph vertex info */
+#define CBRICK_L1	(__psint_t)1
+#define IOBRICK_L1	(__psint_t)2
+#define RBRICK_L1	(__psint_t)3
+
+
+struct l1sc_s;     
+typedef void (*brl1_notif_t)(struct l1sc_s *, int);
+typedef int  (*brl1_uartf_t)(struct l1sc_s *);
+
+/* structure for controlling a subchannel */
+typedef struct brl1_sch_s {
+    int		use;		/* if this subchannel is free,
+				 * use == BRL1_SUBCH_FREE */
+    uint	target;		/* type, rack and slot of component to
+				 * which this subchannel is directed */
+    int		packet_arrived; /* true if packet arrived on
+				 * this subchannel */
+    sc_cq_t *	iqp;		/* input queue for this subchannel */
+    sv_t	arrive_sv;	/* used to wait for a packet */
+    lock_t	data_lock;	/* synchronize access to input queues and
+				 * other fields of the brl1_sch_s struct */
+    brl1_notif_t tx_notify;     /* notify higher layer that transmission may 
+				 * continue */
+    brl1_notif_t rx_notify;	/* notify higher layer that a packet has been
+				 * received */
+} brl1_sch_t;
+
+/* br<->l1 protocol states */
+#define BRL1_IDLE	0
+#define BRL1_FLAG	1
+#define BRL1_HDR	2
+#define BRL1_BODY	3
+#define BRL1_ESC	4
+#define BRL1_RESET	7
+
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/*
+ * l1sc_t structure-- tracks protocol state, open subchannels, etc.
+ */
+typedef struct l1sc_s {
+    nasid_t	 nasid;		/* nasid with which this instance
+				 * of the structure is associated */
+    moduleid_t	 modid;         /* module id of this brick */
+    u_char	 verbose;	/* non-zero if elscuart routines should
+				 * prefix output */
+    net_vec_t    uart;		/* vector path to UART, or BRL1_LOCALUART */
+    int		 sent;		/* number of characters sent */
+    int		 send_len;	/* number of characters in send buf */
+    brl1_uartf_t putc_f;	/* pointer to UART putc function */
+    brl1_uartf_t getc_f;	/* pointer to UART getc function */
+
+    lock_t	 send_lock;	/* arbitrates send synchronization */
+    lock_t	 recv_lock;	/* arbitrates uart receive access */
+    lock_t	 subch_lock;	/* arbitrates subchannel allocation */
+    cpuid_t	 intr_cpu;	/* cpu that receives L1 interrupts */
+
+    u_char	 send_in_use;	/* non-zero if send buffer contains an
+				 * unsent or partially-sent  packet */
+    u_char	 fifo_space;	/* current depth of UART send FIFO */
+
+    u_char	 brl1_state;	/* current state of the receive side */
+    u_char	 brl1_last_hdr;	/* last header byte received */
+
+    char	 send[BRL1_BUFSZ]; /* send buffer */
+
+    int		 sol;		/* "start of line" (see elscuart routines) */
+    int		 cons_listen;	/* non-zero if the elscuart interface should
+				 * also check the system console subchannel */
+    brl1_sch_t	 subch[BRL1_NUM_SUBCHANS];
+    				/* subchannels provided by link */
+
+    sc_cq_t	 garbage_q;	/* a place to put unsolicited packets */
+    sc_cq_t	 oq[BRL1_OQS];	/* elscuart output queues */
+
+} l1sc_t;
+
+
+/* error codes */
+#define BRL1_VALID	  0
+#define BRL1_FULL_Q	(-1)
+#define BRL1_CRC	(-2)
+#define BRL1_PROTOCOL	(-3)
+#define BRL1_NO_MESSAGE	(-4)
+#define BRL1_LINK	(-5)
+#define BRL1_BUSY	(-6)
+
+#define SC_SUCCESS      BRL1_VALID
+#define SC_NMSG         BRL1_NO_MESSAGE
+#define SC_BUSY         BRL1_BUSY
+#define SC_NOPEN        (-7)
+#define SC_BADSUBCH     (-8)
+#define SC_TIMEDOUT	(-9)
+#define SC_NSUBCH	(-10)
+
+
+/* L1 Target Addresses */
+/*
+ * L1 commands and responses use source/target addresses that are
+ * 32 bits long.  These are broken up into multiple bitfields that
+ * specify the type of the target controller (could actually be L2
+ * L3, not just L1), the rack and bay of the target, and the task
+ * id (L1 functionality is divided into several independent "tasks"
+ * that can each receive command requests and transmit responses)
+ */
+#define L1_ADDR_TYPE_SHFT	28
+#define L1_ADDR_TYPE_MASK	0xF0000000
+#define L1_ADDR_TYPE_L1		0x00	/* L1 system controller */
+#define L1_ADDR_TYPE_L2		0x01	/* L2 system controller */
+#define L1_ADDR_TYPE_L3		0x02	/* L3 system controller */
+#define L1_ADDR_TYPE_CBRICK	0x03	/* attached C brick	*/
+#define L1_ADDR_TYPE_IOBRICK	0x04	/* attached I/O brick	*/
+
+#define L1_ADDR_RACK_SHFT	18
+#define L1_ADDR_RACK_MASK	0x0FFC0000
+#define	L1_ADDR_RACK_LOCAL	0x3ff	/* local brick's rack	*/
+
+#define L1_ADDR_BAY_SHFT	12
+#define L1_ADDR_BAY_MASK	0x0003F000
+#define	L1_ADDR_BAY_LOCAL	0x3f	/* local brick's bay	*/
+
+#define L1_ADDR_TASK_SHFT	0
+#define L1_ADDR_TASK_MASK	0x0000001F
+#define L1_ADDR_TASK_INVALID	0x00	/* invalid task 	*/
+#define	L1_ADDR_TASK_IROUTER	0x01	/* iRouter		*/
+#define L1_ADDR_TASK_SYS_MGMT	0x02	/* system management port */
+#define L1_ADDR_TASK_CMD	0x03	/* command interpreter	*/
+#define L1_ADDR_TASK_ENV	0x04	/* environmental monitor */
+#define L1_ADDR_TASK_BEDROCK	0x05	/* bedrock		*/
+#define L1_ADDR_TASK_GENERAL	0x06	/* general requests	*/
+
+#define L1_ADDR_LOCAL				\
+    (L1_ADDR_TYPE_L1 << L1_ADDR_TYPE_SHFT) |	\
+    (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) |	\
+    (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT)
+
+#define L1_ADDR_LOCALIO					\
+    (L1_ADDR_TYPE_IOBRICK << L1_ADDR_TYPE_SHFT) |	\
+    (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) |		\
+    (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT)
+
+#define L1_ADDR_LOCAL_SHFT	L1_ADDR_BAY_SHFT
+
+/* response argument types */
+#define L1_ARG_INT		0x00	/* 4-byte integer (big-endian)	*/
+#define L1_ARG_ASCII		0x01	/* null-terminated ASCII string */
+#define L1_ARG_UNKNOWN		0x80	/* unknown data type.  The low
+					 * 7 bits will contain the data
+					 * length.			*/
+
+/* response codes */
+#define L1_RESP_OK	    0	/* no problems encountered      */
+#define L1_RESP_IROUTER	(-  1)	/* iRouter error	        */
+#define L1_RESP_ARGC	(-100)	/* arg count mismatch	        */
+#define L1_RESP_REQC	(-101)	/* bad request code	        */
+#define L1_RESP_NAVAIL	(-104)	/* requested data not available */
+#define L1_RESP_ARGVAL	(-105)  /* arg value out of range       */
+
+/* L1 general requests */
+
+/* request codes */
+#define	L1_REQ_RDBG		0x0001	/* read debug switches	*/
+#define L1_REQ_RRACK		0x0002	/* read brick rack & bay */
+#define L1_REQ_RRBT		0x0003  /* read brick rack, bay & type */
+#define L1_REQ_SER_NUM		0x0004  /* read brick serial number */
+#define L1_REQ_FW_REV		0x0005  /* read L1 firmware revision */
+#define L1_REQ_EEPROM		0x0006  /* read EEPROM info */
+#define L1_REQ_EEPROM_FMT	0x0007  /* get EEPROM data format & size */
+#define L1_REQ_SYS_SERIAL	0x0008	/* read system serial number */
+#define L1_REQ_PARTITION_GET	0x0009	/* read partition id */
+#define L1_REQ_PORTSPEED	0x000a	/* get ioport speed */
+
+#define L1_REQ_CONS_SUBCH	0x1002  /* select this node's console 
+					 * subchannel */
+#define L1_REQ_CONS_NODE	0x1003  /* volunteer to be the master 
+					 * (console-hosting) node */
+#define L1_REQ_DISP1		0x1004  /* write line 1 of L1 display */
+#define L1_REQ_DISP2		0x1005  /* write line 2 of L1 display */
+#define L1_REQ_PARTITION_SET	0x1006	/* set partition id */
+#define L1_REQ_EVENT_SUBCH	0x1007	/* set the subchannel for system
+					   controller event transmission */
+
+#define L1_REQ_RESET		0x2001	/* request a full system reset */
+
+/* L1 command interpreter requests */
+
+/* request codes */
+#define L1_REQ_EXEC_CMD		0x0000	/* interpret and execute an ASCII
+					   command string */
+
+
+/* brick type response codes */
+#define L1_BRICKTYPE_C	0x43
+#define L1_BRICKTYPE_I	0x49
+#define L1_BRICKTYPE_P	0x50
+#define L1_BRICKTYPE_R  0x52
+#define L1_BRICKTYPE_X  0x58
+
+/* EEPROM codes (for the "read EEPROM" request) */
+/* c brick */
+#define L1_EEP_NODE		0x00	/* node board */
+#define L1_EEP_PIMM0		0x01
+#define L1_EEP_PIMM(x)		(L1_EEP_PIMM0+(x))
+#define L1_EEP_DIMM0		0x03
+#define L1_EEP_DIMM(x)		(L1_EEP_DIMM0+(x))
+
+/* other brick types */
+#define L1_EEP_POWER		0x00	/* power board */
+#define L1_EEP_LOGIC		0x01	/* logic board */
+
+/* info area types */
+#define L1_EEP_CHASSIS		1	/* chassis info area */
+#define L1_EEP_BOARD		2	/* board info area */
+#define L1_EEP_IUSE		3	/* internal use area */
+#define L1_EEP_SPD		4	/* serial presence detect record */
+
+typedef uint32_t l1addr_t;
+
+#define L1_BUILD_ADDR(addr,at,r,s,t)					\
+    (*(l1addr_t *)(addr) = ((l1addr_t)(at) << L1_ADDR_TYPE_SHFT) |	\
+			     ((l1addr_t)(r)  << L1_ADDR_RACK_SHFT) |	\
+			     ((l1addr_t)(s)  << L1_ADDR_BAY_SHFT) |	\
+			     ((l1addr_t)(t)  << L1_ADDR_TASK_SHFT))
+
+#define L1_ADDRESS_TO_TASK(addr,trb,tsk)				\
+    (*(l1addr_t *)(addr) = (l1addr_t)(trb) |				\
+    			     ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT))
+
+
+#define L1_DISPLAY_LINE_LENGTH	12	/* L1 display characters/line */
+
+#ifdef L1_DISP_2LINES
+#define L1_DISPLAY_LINES	2	/* number of L1 display lines */
+#else
+#define L1_DISPLAY_LINES	1	/* number of L1 display lines available
+					 * to system software */
+#endif
+
+#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00)
+
+#define bzero(d, n)	memset((d), 0, (n))
+
+/* public interfaces to L1 system controller */
+
+int	sc_open( l1sc_t *sc, uint target );
+int	sc_close( l1sc_t *sc, int ch );
+int	sc_construct_msg( l1sc_t *sc, int ch, 
+			  char *msg, int msg_len,
+			  uint addr_task, short req_code,
+			  int req_nargs, ... );
+int	sc_interpret_resp( char *resp, int resp_nargs, ... );
+int	sc_send( l1sc_t *sc, int ch, char *msg, int len, int wait );
+int	sc_recv( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block );
+int	sc_command( l1sc_t *sc, int ch, char *cmd, char *resp, int *len );
+int	sc_command_kern( l1sc_t *sc, int ch, char *cmd, char *resp, int *len );
+int	sc_poll( l1sc_t *sc, int ch );
+void	sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart );
+void	sc_intr_enable( l1sc_t *sc );
+
+#if 0
+int	sc_portspeed_get( l1sc_t *sc );
+#endif
+
+int	l1_cons_poll( l1sc_t *sc );
+int	l1_cons_getc( l1sc_t *sc );
+void	l1_cons_init( l1sc_t *sc );
+int	l1_cons_read( l1sc_t *sc, char *buf, int avail );
+int	l1_cons_write( l1sc_t *sc, char *msg, int len, int wait );
+void	l1_cons_tx_notif( l1sc_t *sc, brl1_notif_t func );
+void	l1_cons_rx_notif( l1sc_t *sc, brl1_notif_t func );
+
+int	_elscuart_putc( l1sc_t *sc, int c );
+int	_elscuart_getc( l1sc_t *sc );
+int	_elscuart_poll( l1sc_t *sc );
+int	_elscuart_readc( l1sc_t *sc );
+int	_elscuart_flush( l1sc_t *sc );
+int	_elscuart_probe( l1sc_t *sc );
+void	_elscuart_init( l1sc_t *sc );
+void	elscuart_syscon_listen( l1sc_t *sc );
+
+int	elsc_rack_bay_get(l1sc_t *e, uint *rack, uint *bay);
+int	elsc_rack_bay_type_get(l1sc_t *e, uint *rack, 
+			       uint *bay, uint *brick_type);
+int	elsc_cons_subch(l1sc_t *e, uint ch);
+int	elsc_cons_node(l1sc_t *e);
+int	elsc_display_line(l1sc_t *e, char *line, int lnum);
+
+extern l1sc_t *get_elsc( void );
+extern void    set_elsc( l1sc_t *e );
+
+#define get_l1sc	get_elsc
+#define set_l1sc(e)	set_elsc(e)
+
+#define get_master_l1sc get_l1sc
+
+int	router_module_get( nasid_t nasid, net_vec_t path );
+
+int	iobrick_rack_bay_type_get( l1sc_t *sc, uint *rack,
+				   uint *bay, uint *brick_type );
+int	iobrick_module_get( l1sc_t *sc );
+int	iobrick_pci_slot_pwr( l1sc_t *sc, int bus, int slot, int up );
+int	iobrick_pci_bus_pwr( l1sc_t *sc, int bus, int up );
+int	iobrick_sc_version( l1sc_t *sc, char *result );
+
+
+#endif /* !_LANGUAGE_ASSEMBLY */
+#endif /* _ASM_SN_KSYS_L1_H */
diff --git a/include/asm-ia64/sn/labelcl.h b/include/asm-ia64/sn/labelcl.h
new file mode 100644
index 000000000..902ae2203
--- /dev/null
+++ b/include/asm-ia64/sn/labelcl.h
@@ -0,0 +1,93 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_LABELCL_H
+#define _ASM_SN_LABELCL_H
+
+#define LABELCL_MAGIC 0x4857434c	/* 'HWLC' */
+#define LABEL_LENGTH_MAX 256		/* Includes NULL char */
+#define INFO_DESC_PRIVATE -1      	/* default */
+#define INFO_DESC_EXPORT  0       	/* export info itself */
+
+/*
+ * Internal Error codes.
+ */
+typedef enum labelcl_error_e {  LABELCL_SUCCESS,          /* 0 */
+                                LABELCL_DUP,              /* 1 */
+                                LABELCL_NOT_FOUND,        /* 2 */
+                                LABELCL_BAD_PARAM,        /* 3 */
+                                LABELCL_HIT_LIMIT,        /* 4 */
+                                LABELCL_CANNOT_ALLOC,     /* 5 */
+                                LABELCL_ILLEGAL_REQUEST,  /* 6 */
+                                LABELCL_IN_USE            /* 7 */
+                                } labelcl_error_t;
+
+
+/*
+ * Description of a label entry.
+ */
+typedef struct label_info_s {
+        char			*name;
+        arb_info_desc_t		desc;
+        arbitrary_info_t	info;
+} label_info_t;
+
+/*
+ * Definition of the data structure that provides the link to 
+ * the hwgraph fastinfo and the label entries associated with a 
+ * particular devfs entry.
+ */
+typedef struct labelcl_info_s {
+	unsigned long	hwcl_magic;
+	unsigned long	num_labels;
+	void		*label_list;
+	arbitrary_info_t IDX_list[HWGRAPH_NUM_INDEX_INFO];
+} labelcl_info_t;
+
+/*
+ * Definitions for the string table that holds the actual names 
+ * of the labels.
+ */
+struct string_table_item {
+        struct string_table_item        *next;
+        char                            string[1];
+};
+
+struct string_table {
+        struct string_table_item        *string_table_head;
+        long                            string_table_generation;
+};
+
+
+#define STRTBL_BASIC_SIZE ((size_t)(((struct string_table_item *)0)->string))
+#define STRTBL_ITEM_SIZE(str_length) (STRTBL_BASIC_SIZE + (str_length) + 1)
+
+#define STRTBL_ALLOC(str_length) \
+        ((struct string_table_item *)kmalloc(STRTBL_ITEM_SIZE(str_length), GFP_KERNEL))
+
+#define STRTBL_FREE(ptr) kfree(ptr)
+
+
+extern labelcl_info_t *labelcl_info_create(void);
+extern int labelcl_info_destroy(labelcl_info_t *);
+extern int labelcl_info_add_LBL(struct devfs_entry *, char *, arb_info_desc_t, arbitrary_info_t);
+extern int labelcl_info_remove_LBL(struct devfs_entry *, char *, arb_info_desc_t *, arbitrary_info_t *);
+extern int labelcl_info_replace_LBL(struct devfs_entry *, char *, arb_info_desc_t,
+                        arbitrary_info_t, arb_info_desc_t *, arbitrary_info_t *);
+extern int labelcl_info_get_LBL(struct devfs_entry *, char *, arb_info_desc_t *,
+                      arbitrary_info_t *);
+extern int labelcl_info_get_next_LBL(struct devfs_entry *, char *, arb_info_desc_t *,
+                           arbitrary_info_t *, labelcl_info_place_t *);
+extern int labelcl_info_replace_IDX(struct devfs_entry *, int, arbitrary_info_t, 
+			arbitrary_info_t *);
+extern int labelcl_info_connectpt_set(struct devfs_entry *, struct devfs_entry *);
+extern int labelcl_info_get_IDX(struct devfs_entry *, int, arbitrary_info_t *);
+extern struct devfs_entry *device_info_connectpt_get(struct devfs_entry *);
+
+#endif /* _ASM_SN_LABELCL_H */
diff --git a/include/asm-ia64/sn/mem_refcnt.h b/include/asm-ia64/sn/mem_refcnt.h
new file mode 100644
index 000000000..e75986fde
--- /dev/null
+++ b/include/asm-ia64/sn/mem_refcnt.h
@@ -0,0 +1,26 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_MEM_REFCNT_H
+#define _ASM_SN_MEM_REFCNT_H
+
+extern int mem_refcnt_attach(devfs_handle_t hub);
+extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp);
+extern int mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp);
+extern int mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot);
+extern int mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt);
+extern int mem_refcnt_ioctl(devfs_handle_t dev,
+                 int cmd,
+                 void *arg,
+                 int mode,
+                 cred_t *cred_p,
+                 int *rvalp);
+        
+
+#endif /* _ASM_SN_MEM_REFCNT_H */
diff --git a/include/asm-ia64/sn/mmzone.h b/include/asm-ia64/sn/mmzone.h
new file mode 100644
index 000000000..e44f16f14
--- /dev/null
+++ b/include/asm-ia64/sn/mmzone.h
@@ -0,0 +1,112 @@
+/*
+ * Written by Kanoj Sarcar (kanoj@sgi.com) Jan 2000
+ * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
+ */
+#ifndef _LINUX_ASM_SN_MMZONE_H
+#define _LINUX_ASM_SN_MMZONE_H
+
+#include <linux/config.h>
+#include <asm/sn/mmzone_sn1.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * Memory is conceptually divided into chunks. A chunk is either
+ * completely present, or else the kernel assumes it is completely
+ * absent. Each node consists of a number of contiguous chunks.
+ */
+
+#define CHUNKMASK       	(~(CHUNKSZ - 1))
+#define CHUNKNUM(vaddr)        	(__pa(vaddr) >> CHUNKSHIFT)
+#define PCHUNKNUM(paddr)        ((paddr) >> CHUNKSHIFT)
+
+#define MAXCHUNKS      		(MAXNODES * MAX_CHUNKS_PER_NODE)
+
+extern int chunktonid[];
+#define CHUNKTONID(cnum)       (chunktonid[cnum])
+
+typedef struct plat_pglist_data {
+       pg_data_t       gendata;		/* try to keep this first. */
+       unsigned long   virtstart;
+       unsigned long   size;
+} plat_pg_data_t;
+
+extern plat_pg_data_t plat_node_data[];
+
+extern int numa_debug(void);
+
+/*
+ * The foll two will move into linux/mmzone.h RSN.
+ */
+#define NODE_START(n)  plat_node_data[(n)].virtstart
+#define NODE_SIZE(n)   plat_node_data[(n)].size
+
+#define KVADDR_TO_NID(kaddr) \
+       ((CHUNKTONID(CHUNKNUM((kaddr))) != -1) ? (CHUNKTONID(CHUNKNUM((kaddr)))) : \
+       (printk("DISCONTIGBUG: %s line %d addr 0x%lx", __FILE__, __LINE__, \
+       (unsigned long)(kaddr)), numa_debug()))
+#if 0
+#define KVADDR_TO_NID(kaddr) CHUNKTONID(CHUNKNUM((kaddr)))
+#endif
+
+/* These 2 macros should never be used if KVADDR_TO_NID(kaddr) is -1 */
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr) \
+                       NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
+
+/*
+ * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory
+ * and returns the kaddr corresponding to first physical page in the
+ * node's mem_map.
+ */
+#define LOCAL_BASE_ADDR(kaddr) NODE_START(KVADDR_TO_NID(kaddr))
+
+#ifdef CONFIG_DISCONTIGMEM
+
+/*
+ * Return a pointer to the node data for node n.
+ * Assume that n is the compact node id.
+ */
+#define NODE_DATA(n)   (&((plat_node_data + (n))->gendata))
+
+/*
+ * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
+ */
+#define NODE_MEM_MAP(nid)      (NODE_DATA((nid))->node_mem_map)
+
+/* This macro should never be used if KVADDR_TO_NID(kaddr) is -1 */
+#define LOCAL_MAP_NR(kvaddr) \
+        (((unsigned long)(kvaddr)-LOCAL_BASE_ADDR((kvaddr))) >> PAGE_SHIFT)
+#define MAP_NR_SN1(kaddr)   (LOCAL_MAP_NR((kaddr)) + \
+                (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
+                sizeof(mem_map_t)))
+#if 0
+#define MAP_NR_VALID(kaddr)   (LOCAL_MAP_NR((kaddr)) + \
+                (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
+                sizeof(mem_map_t)))
+#define MAP_NR_SN1(kaddr)	((KVADDR_TO_NID(kaddr) == -1) ? (max_mapnr + 1) :\
+				MAP_NR_VALID(kaddr))
+#endif
+
+/* FIXME */
+#define sn1_pte_pagenr(x)		MAP_NR_SN1(PAGE_OFFSET + (unsigned long)((pte_val(x)&_PFN_MASK) & PAGE_MASK))
+#define pte_page(pte)			(mem_map + sn1_pte_pagenr(pte))
+/* FIXME */
+
+#define kern_addr_valid(addr)   ((KVADDR_TO_NID((unsigned long)addr) >= \
+        numnodes) ? 0 : (test_bit(LOCAL_MAP_NR((addr)), \
+        NODE_DATA(KVADDR_TO_NID((unsigned long)addr))->valid_addr_bitmap)))
+
+#define virt_to_page(kaddr)	(mem_map + MAP_NR_SN1(kaddr))
+
+#else /* CONFIG_DISCONTIGMEM */
+
+#define MAP_NR_SN1(addr)	(((unsigned long) (addr) - PAGE_OFFSET) >> PAGE_SHIFT)
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#define numa_node_id()		cpuid_to_cnodeid(smp_processor_id())
+
+#endif /* !_LINUX_ASM_SN_MMZONE_H */
diff --git a/include/asm-ia64/sn/mmzone_default.h b/include/asm-ia64/sn/mmzone_default.h
new file mode 100644
index 000000000..084c33d7a
--- /dev/null
+++ b/include/asm-ia64/sn/mmzone_default.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
+ */
+
+#define MAXNODES                16
+#define MAXNASIDS               16
+
+#define CHUNKSZ                (8*1024*1024)
+#define CHUNKSHIFT              23      /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
+
+#define CNODEID_TO_NASID(n)	n
+#define NASID_TO_CNODEID(n)     n
+
+#define MAX_CHUNKS_PER_NODE     8
+
diff --git a/include/asm-ia64/sn/mmzone_sn1.h b/include/asm-ia64/sn/mmzone_sn1.h
new file mode 100644
index 000000000..170fdfc3c
--- /dev/null
+++ b/include/asm-ia64/sn/mmzone_sn1.h
@@ -0,0 +1,106 @@
+#ifndef _ASM_IA64_MMZONE_SN1_H
+#define _ASM_IA64_MMZONE_SN1_H
+
+/*
+ * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
+ */
+
+#include <linux/config.h>
+
+/* Maximum configuration supported by SNIA hardware. There are other
+ * restrictions that may limit us to a smaller max configuration.
+ */
+#define MAXNODES                128
+#define MAXNASIDS		128
+
+#define CHUNKSZ                (64*1024*1024)
+#define CHUNKSHIFT              26      /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
+
+extern int 	cnodeid_map[] ;
+extern int	nasid_map[] ;
+
+#define CNODEID_TO_NASID(n)	(cnodeid_map[(n)])
+#define NASID_TO_CNODEID(n)     (nasid_map[(n)])
+
+#define MAX_CHUNKS_PER_NODE     128
+
+
+/*
+ * These are a bunch of sn1 hw specific defines. For now, keep it 
+ * in this file. If it gets too diverse we may want to create a 
+ * mmhwdefs_sn1.h
+ */
+
+/*
+ * Structure of the mem config of the node as a SN1 MI reg
+ * Medusa supports this reg config.
+ */
+
+typedef struct node_memmap_s
+{
+        unsigned int    b0      :1,     /* 0 bank 0 present */
+                        b1      :1,     /* 1 bank 1 present */
+                        r01     :2,     /* 2-3 reserved */
+                        b01size :4,     /* 4-7 Size of bank 0 and 1 */
+                        b2      :1,     /* 8 bank 2 present */
+                        b3      :1,     /* 9 bank 3 present */
+                        r23     :2,     /* 10-11 reserved */
+                        b23size :4,     /* 12-15 Size of bank 2 and 3 */
+                        b4      :1,     /* 16 bank 4 present */
+                        b5      :1,     /* 17 bank 5 present */
+                        r45     :2,     /* 18-19 reserved */
+                        b45size :4,     /* 20-23 Size of bank 4 and 5 */
+                        b6      :1,     /* 24 bank 6 present */
+                        b7      :1,     /* 25 bank 7 present */
+                        r67     :2,     /* 26-27 reserved */
+                        b67size :4;     /* 28-31 Size of bank 6 and 7 */
+} node_memmap_t ;
+
+#define GBSHIFT                 30
+#define MBSHIFT                 20
+
+/*
+ * SN1 Arch defined values
+ */
+#define SN1_MAX_BANK_PER_NODE   8
+#define SN1_BANK_PER_NODE_SHIFT 3       /* derived from SN1_MAX_BANK_PER_NODE */
+#define SN1_NODE_ADDR_SHIFT     (GBSHIFT+3)             /* 8GB */
+#define SN1_BANK_ADDR_SHIFT     (SN1_NODE_ADDR_SHIFT-SN1_BANK_PER_NODE_SHIFT)
+
+#define SN1_BANK_SIZE_SHIFT     (MBSHIFT+6)     /* 64 MB */
+#define SN1_MIN_BANK_SIZE_SHIFT SN1_BANK_SIZE_SHIFT
+
+/*
+ * BankSize nibble to bank size mapping
+ *
+ *      1 - 64 MB
+ *      2 - 128 MB
+ *      3 - 256 MB
+ *      4 - 512 MB
+ *      5 - 1024 MB (1GB)
+ */
+
+/* fixme - this macro breaks for bsize 6-8 and 0 */
+
+#ifdef CONFIG_IA64_SGI_SN1_SIM
+/* Support the medusa hack for 8M/16M/32M nodes */
+#define BankSizeBytes(bsize)            ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
+					 (1<<((bsize-9)+MBSHIFT)))
+#else
+#define BankSizeBytes(bsize)            (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT))
+#endif
+
+#define BankSizeToEFIPages(bsize)       ((BankSizeBytes(bsize)) >> 12)
+
+#define GetPhysAddr(n,b)                (((u64)n<<SN1_NODE_ADDR_SHIFT) | \
+                                                ((u64)b<<SN1_BANK_ADDR_SHIFT))
+
+#define GetNasId(paddr)			((u64)(paddr) >> SN1_NODE_ADDR_SHIFT)
+
+#define GetBankId(paddr)						\
+				(((u64)(paddr) >> SN1_BANK_ADDR_SHIFT) & 7)
+
+#define SN1_MAX_BANK_SIZE		((u64)BankSizeBytes(5))
+#define SN1_BANK_SIZE_MASK		(~(SN1_MAX_BANK_SIZE-1))
+
+#endif /* _ASM_IA64_MMZONE_SN1_H */
diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h
new file mode 100644
index 000000000..ea00d5af6
--- /dev/null
+++ b/include/asm-ia64/sn/module.h
@@ -0,0 +1,205 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_MODULE_H
+#define _ASM_SN_MODULE_H
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <linux/config.h>
+#include <asm/sn/systeminfo.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/ksys/elsc.h>
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#ifdef BRINGUP /* max. number of modules?  Should be about 300.*/
+#define MODULE_MAX			56
+#endif /* BRINGUP */
+#define MODULE_MAX_NODES		1
+#endif /* CONFIG_SGI_IP35 */
+#define MODULE_HIST_CNT			16
+#define MAX_MODULE_LEN			16
+
+/* Well-known module IDs */
+#define MODULE_UNKNOWN		(-2) /* initial value of klconfig brd_module */
+/* #define INVALID_MODULE	(-1) ** generic invalid moduleid_t (arch.h) */
+#define MODULE_NOT_SET		0    /* module ID not set in sys ctlrs. */
+
+/* parameter for format_module_id() */
+#define MODULE_FORMAT_BRIEF	1
+#define MODULE_FORMAT_LONG	2
+
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+
+/*
+ *	Module id format
+ *
+ *	  15-12 Brick type (enumerated)
+ *	   11-6	Rack ID	(encoded class, group, number)
+ *	    5-0 Brick position in rack (0-63)
+ */
+/*
+ * Macros for getting the brick type
+ */
+#define MODULE_BTYPE_MASK	0xf000
+#define MODULE_BTYPE_SHFT	12
+#define MODULE_GET_BTYPE(_m)	(((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
+#define MODULE_BT_TO_CHAR(_b)	(brick_types[(_b)])
+#define MODULE_GET_BTCHAR(_m)	(MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
+
+/*
+ * Macros for getting the rack ID.
+ */
+#define MODULE_RACK_MASK	0x0fc0
+#define MODULE_RACK_SHFT	6
+#define MODULE_GET_RACK(_m)	(((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
+
+/*
+ * Macros for getting the brick position
+ */
+#define MODULE_BPOS_MASK	0x003f
+#define MODULE_BPOS_SHFT	0
+#define MODULE_GET_BPOS(_m)	(((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
+
+/*
+ * Macros for constructing moduleid_t's
+ */
+#define RBT_TO_MODULE(_r, _b, _t) ((_r) << MODULE_RACK_SHFT | \
+				   (_b) << MODULE_BPOS_SHFT | \
+				   (_t) << MODULE_BTYPE_SHFT)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ *   class	1 bit, 0==CPU/mixed, 1==I/O
+ *   group	2 bits for CPU/mixed, 3 bits for I/O
+ *   number	3 bits for CPU/mixed, 2 bits for I/O (1 based)
+ */
+#define RACK_GROUP_BITS(_r)	(RACK_GET_CLASS(_r) ? 3 : 2)
+#define RACK_NUM_BITS(_r)	(RACK_GET_CLASS(_r) ? 2 : 3)
+
+#define RACK_CLASS_MASK(_r)	0x20
+#define RACK_CLASS_SHFT(_r)	5
+#define RACK_GET_CLASS(_r)	\
+	(((_r) & RACK_CLASS_MASK(_r)) >> RACK_CLASS_SHFT(_r))
+#define RACK_ADD_CLASS(_r, _c)	\
+	((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
+
+#define RACK_GROUP_SHFT(_r)	RACK_NUM_BITS(_r)
+#define RACK_GROUP_MASK(_r)	\
+	( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
+#define RACK_GET_GROUP(_r)	\
+	(((_r) & RACK_GROUP_MASK(_r)) >> RACK_GROUP_SHFT(_r))
+#define RACK_ADD_GROUP(_r, _g)	\
+	((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
+
+#define RACK_NUM_SHFT(_r)	0
+#define RACK_NUM_MASK(_r)	\
+	( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
+#define RACK_GET_NUM(_r)	\
+	( (((_r) & RACK_NUM_MASK(_r)) >> RACK_NUM_SHFT(_r)) + 1 )
+#define RACK_ADD_NUM(_r, _n)	\
+	((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
+
+/*
+ * Brick type definitions
+ */
+#define MAX_BRICK_TYPES		16 /* 1 << (MODULE_RACK_SHFT - MODULE_BTYPE_SHFT */
+
+extern char brick_types[];
+
+#define MODULE_CBRICK		0
+#define MODULE_RBRICK		1
+#define MODULE_IBRICK		2
+#define MODULE_KBRICK		3
+#define MODULE_XBRICK		4
+#define MODULE_DBRICK		5
+#define MODULE_PBRICK		6
+
+/*
+ * Moduleid_t comparison macros
+ */
+/* Don't compare the brick type:  only the position is significant */
+#define MODULE_CMP(_m1, _m2)	(((_m1)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)) -\
+				 ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)))
+#define MODULE_MATCH(_m1, _m2)	(MODULE_CMP((_m1),(_m2)) == 0)
+
+#else
+
+/*
+ * Some code that uses this macro will not be conditionally compiled.
+ */
+#define MODULE_GET_BTCHAR(_m)	('?')
+#define MODULE_CMP(_m1, _m2)	((_m1) - (_m2))
+#define MODULE_MATCH(_m1, _m2)	(MODULE_CMP((_m1),(_m2)) == 0)
+
+#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+
+typedef struct module_s module_t;
+
+struct module_s {
+    moduleid_t		id;		/* Module ID of this module        */
+
+    spinlock_t		lock;		/* Lock for this structure	   */
+
+    /* List of nodes in this module */
+    cnodeid_t		nodes[MODULE_MAX_NODES];
+    int			nodecnt;	/* Number of nodes in array        */
+
+    /* Fields for Module System Controller */
+    int			mesgpend;	/* Message pending                 */
+    int			shutdown;	/* Shutdown in progress            */
+    struct semaphore	thdcnt;		/* Threads finished counter        */
+
+    elsc_t		elsc;
+    spinlock_t		elsclock;
+
+    time_t		intrhist[MODULE_HIST_CNT];
+    int			histptr;
+
+    int			hbt_active;	/* MSC heartbeat monitor active    */
+    uint64_t		hbt_last;	/* RTC when last heartbeat sent    */
+
+    /* Module serial number info */
+    union {
+	char		snum_str[MAX_SERIAL_NUM_SIZE];	 /* used by CONFIG_SGI_IP27    */
+	uint64_t	snum_int;			 /* used by speedo */
+    } snum;
+    int			snum_valid;
+
+    int			disable_alert;
+    int			count_down;
+};
+
+/* module.c */
+extern module_t	       *modules[MODULE_MAX];	/* Indexed by cmoduleid_t   */
+extern int		nummodules;
+
+#ifndef CONFIG_IA64_SGI_IO
+/* Clashes with LINUX stuff */
+extern void		module_init(void);
+#endif
+extern module_t	       *module_lookup(moduleid_t id);
+
+extern elsc_t	       *get_elsc(void);
+
+extern int		get_kmod_info(cmoduleid_t cmod,
+				      module_info_t *mod_info);
+
+extern void		format_module_id(char *buffer, moduleid_t m, int fmt);
+extern int		parse_module_id(char *buffer);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _ASM_SN_MODULE_H */
diff --git a/include/asm-ia64/sn/nic.h b/include/asm-ia64/sn/nic.h
new file mode 100644
index 000000000..09370cb94
--- /dev/null
+++ b/include/asm-ia64/sn/nic.h
@@ -0,0 +1,128 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_NIC_H
+#define _ASM_SN_NIC_H
+
+#include <asm/types.h>
+
+#define MCR_DATA(x)			((int) ((x) & 1))
+#define MCR_DONE(x)			((x) & 2)
+#define MCR_PACK(pulse, sample)		((pulse) << 10 | (sample) << 2)
+
+typedef __psunsigned_t	nic_data_t;
+
+typedef int		
+nic_access_f(nic_data_t data,
+	     int pulse, int sample, int delay);
+
+typedef nic_access_f   *nic_access_t;
+
+typedef struct nic_vmce_s      *nic_vmce_t;
+typedef void			nic_vmc_func(devfs_handle_t v);
+
+/*
+ * PRIVATE data for Dallas NIC
+ */
+
+typedef struct nic_state_t {
+    nic_access_t	access;
+    nic_data_t		data;
+    int			last_disc;
+    int			done;
+    int			bit_index;
+    int			disc_marker;
+    uchar_t		bits[64];
+} nic_state_t;
+
+/*
+ * Public interface for Dallas NIC
+ *
+ *
+ *   Access Routine
+ *
+ *   nic_setup requires an access routine that pulses the NIC line for a
+ *   specified duration, samples the NIC line after a specified duration,
+ *   then delays for a third specified duration (for precharge).
+ *
+ *   This general scheme allows us to access NICs through any medium
+ *   (e.g. hub regs, bridge regs, vector writes, system ctlr commands).
+ *
+ *   The access routine should return the sample value 0 or 1, or if an
+ *   error occurs, return a negative error code.  Negative error codes from
+ *   the access routine will abort the NIC operation and be propagated
+ *   through out of the top-level NIC call.
+ */
+
+#define NIC_OK			0
+#define NIC_DONE		1
+#define NIC_FAIL		2
+#define NIC_BAD_CRC		3
+#define NIC_NOT_PRESENT		4
+#define NIC_REDIR_LOOP		5
+#define NIC_PARAM		6
+#define NIC_NOMEM		7
+
+uint64_t nic_get_phase_bits(void);
+
+extern int nic_setup(nic_state_t *ns,
+		     nic_access_t access,
+		     nic_data_t data);
+
+extern int nic_next(nic_state_t *ns,
+		    char *serial,
+		    char *family,
+		    char *crc);
+
+extern int nic_read_one_page(nic_state_t *ns,
+			     char *family,
+			     char *serial,
+			     char *crc,
+			     int start,
+			     uchar_t *redirect,
+			     uchar_t *byte);
+
+extern int nic_read_mfg(nic_state_t *ns,
+			char *family,
+			char *serial,
+			char *crc,
+			uchar_t *pageA,
+			uchar_t *pageB);
+
+extern int nic_info_get(nic_access_t access,
+			nic_data_t data,
+			char *info);
+
+extern int nic_item_info_get(char *buf, char *item, char **item_info);
+
+nic_access_f	nic_access_mcr32;
+
+extern char *nic_vertex_info_get(devfs_handle_t v);
+
+extern char *nic_vertex_info_set(nic_access_t access,
+				 nic_data_t data, 
+				 devfs_handle_t v);
+
+extern int nic_vertex_info_match(devfs_handle_t vertex,
+				 char *name);
+
+extern char *nic_bridge_vertex_info(devfs_handle_t vertex,
+				    nic_data_t	data);
+extern char *nic_hq4_vertex_info(devfs_handle_t vertex,
+				 nic_data_t data);
+extern char *nic_ioc3_vertex_info(devfs_handle_t vertex,
+				    nic_data_t	data,
+				    int32_t *gpcr_s);
+
+extern char *nic_hub_vertex_info(devfs_handle_t vertex);
+
+extern nic_vmce_t	nic_vmc_add(char *, nic_vmc_func *);
+extern void		nic_vmc_del(nic_vmce_t);
+
+#endif /* _ASM_SN_NIC_H */
diff --git a/include/asm-ia64/sn/nodemask.h b/include/asm-ia64/sn/nodemask.h
new file mode 100644
index 000000000..97ce56755
--- /dev/null
+++ b/include/asm-ia64/sn/nodemask.h
@@ -0,0 +1,329 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_NODEMASK_H
+#define _ASM_SN_NODEMASK_H
+
+#if defined(__KERNEL__) || defined(_KMEMUSER)
+
+#include <linux/config.h>
+#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#include <asm/sn/sn1/arch.h>    /* needed for MAX_COMPACT_NODES */
+#endif
+
+#define CNODEMASK_BOOTED_MASK		boot_cnodemask
+#define CNODEMASK_BIPW    64
+
+#if !defined(SN0XXL) && !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
+			/* MAXCPUS 128p (64 nodes) or less */
+
+#define CNODEMASK_SIZE    1
+typedef uint64_t cnodemask_t;
+
+#define CNODEMASK_WORD(p,w)     (p)
+#define CNODEMASK_SET_WORD(p,w,val)     (p) = val
+#define CNODEMASK_CLRALL(p)     (p) = 0
+#define CNODEMASK_SETALL(p)     (p) = ~((cnodemask_t)0)
+#define CNODEMASK_IS_ZERO(p)	((p) == 0)
+#define CNODEMASK_IS_NONZERO(p)	((p) != 0)
+#define CNODEMASK_NOTEQ(p, q)	((p) != (q))
+#define CNODEMASK_EQ(p, q)      ((p) == (q))
+#define CNODEMASK_LSB_ISONE(p)  ((p) & 0x1ULL)
+
+#define CNODEMASK_ZERO()        ((cnodemask_t)0)
+#define CNODEMASK_CVTB(bit)     (1ULL << (bit))
+#define CNODEMASK_SETB(p, bit)	((p) |= 1ULL << (bit))
+#define CNODEMASK_CLRB(p, bit)	((p) &= ~(1ULL << (bit)))
+#define CNODEMASK_TSTB(p, bit)	((p) & (1ULL << (bit)))
+
+#define CNODEMASK_SETM(p, q)	((p) |= (q))
+#define CNODEMASK_CLRM(p, q)	((p) &= ~(q))
+#define CNODEMASK_ANDM(p, q)	((p) &= (q))
+#define CNODEMASK_TSTM(p, q)	((p) & (q))
+
+#define CNODEMASK_CPYNOTM(p, q)	((p) = ~(q))
+#define CNODEMASK_CPY(p, q)     ((p) = (q))
+#define CNODEMASK_ORNOTM(p, q)	((p) |= ~(q))
+#define CNODEMASK_SHIFTL(p)     ((p) <<= 1)
+#define CNODEMASK_SHIFTR(p)     ((p) >>= 1)
+#define CNODEMASK_SHIFTL_PTR(p)     (*(p) <<= 1)
+#define CNODEMASK_SHIFTR_PTR(p)     (*(p) >>= 1)
+
+/* Atomically set or clear a particular bit */
+#define CNODEMASK_ATOMSET_BIT(p, bit) atomicSetUlong((cnodemask_t *)&(p), (1ULL<<(bit))) 
+#define CNODEMASK_ATOMCLR_BIT(p, bit) atomicClearUlong((cnodemask_t *)&(p), (1ULL<<(bit)))
+
+/* Atomically set or clear a collection of bits */
+#define CNODEMASK_ATOMSET(p, q)  atomicSetUlong((cnodemask_t *)&(p), q)
+#define CNODEMASK_ATOMCLR(p, q)  atomicClearUlong((cnodemask_t *)&(p), q)
+
+/* Atomically set or clear a collection of bits, returning the old value */
+#define CNODEMASK_ATOMSET_MASK(__old, p, q)	{ \
+		(__old) = atomicSetUlong((cnodemask_t *)&(p), q); \
+}
+#define CNODEMASK_ATOMCLR_MASK(__old, p, q)	{ \
+		(__old) = atomicClearUlong((cnodemask_t *)&(p),q); \
+}
+
+#define CNODEMASK_FROM_NUMNODES(n)	((~(cnodemask_t)0)>>(CNODEMASK_BIPW-(n)))
+
+#else  /* SN0XXL || SN1 - MAXCPUS > 128 */
+
+#define CNODEMASK_SIZE    (MAX_COMPACT_NODES / CNODEMASK_BIPW)
+
+typedef struct {
+        uint64_t _bits[CNODEMASK_SIZE];
+} cnodemask_t;
+
+#define CNODEMASK_WORD(p,w)  \
+	((w >= 0 && w < CNODEMASK_SIZE) ? (p)._bits[(w)] : 0)
+#define CNODEMASK_SET_WORD(p,w,val)  { 				\
+	if (w >= 0 && w < CNODEMASK_SIZE) 			\
+		(p)._bits[(w)] = val;				\
+}
+
+#define CNODEMASK_CLRALL(p)       {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] = 0;                               \
+}
+
+#define CNODEMASK_SETALL(p)       {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] = ~(0);                            \
+}
+
+#define CNODEMASK_LSB_ISONE(p)  ((p)._bits[0] & 0x1ULL)
+
+
+#define CNODEMASK_SETM(p,q)       {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] |= ((q)._bits[i]);                 \
+}
+
+#define CNODEMASK_CLRM(p,q)       {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] &= ~((q)._bits[i]);                \
+}
+
+#define CNODEMASK_ANDM(p,q)       {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] &= ((q)._bits[i]);                 \
+}
+
+#define CNODEMASK_CPY(p, q)  {					\
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] = (q)._bits[i];	                \
+}
+
+#define CNODEMASK_CPYNOTM(p,q)    {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] = ~((q)._bits[i]);                 \
+}
+
+#define CNODEMASK_ORNOTM(p,q)     {                             \
+        int i;                                                  \
+                                                                \
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
+                (p)._bits[i] |= ~((q)._bits[i]);                \
+}
+
+#define CNODEMASK_INDEX(bit)      ((bit) >> 6)
+#define CNODEMASK_SHFT(bit)       ((bit) & 0x3f)
+
+
+#define CNODEMASK_SETB(p, bit)	 				\
+	(p)._bits[CNODEMASK_INDEX(bit)] |= (1ULL << CNODEMASK_SHFT(bit))
+
+
+#define CNODEMASK_CLRB(p, bit)					\
+	(p)._bits[CNODEMASK_INDEX(bit)] &= ~(1ULL << CNODEMASK_SHFT(bit)) 
+
+
+#define CNODEMASK_TSTB(p, bit)		\
+	((p)._bits[CNODEMASK_INDEX(bit)] & (1ULL << CNODEMASK_SHFT(bit))) 
+
+/** Probably should add atomic update for entire cnodemask_t struct **/
+
+/* Atomically set or clear a particular bit */
+#define CNODEMASK_ATOMSET_BIT(p, bit) \
+        (atomicSetUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit))));
+#define CNODEMASK_ATOMCLR_BIT(__old, p, bit) \
+        (atomicClearUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit))));
+
+/* Atomically set or clear a collection of bits */
+#define CNODEMASK_ATOMSET(p, q) { \
+        int i;				\
+					\
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \
+	      atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]);  \
+        }				\
+}
+#define CNODEMASK_ATOMCLR(p, q) { \
+        int i;				\
+                        		\
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++) {	\
+	      atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \
+        }				\
+}
+
+/* Atomically set or clear a collection of bits, returning the old value */
+#define CNODEMASK_ATOMSET_MASK(__old, p, q)  { \
+        int i;				\
+					\
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \
+           (__old)._bits[i] =	 \
+	      atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]);  \
+        }				\
+}
+#define CNODEMASK_ATOMCLR_MASK(__old, p, q) {					\
+        int i;				\
+                        		\
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++) {	\
+           (__old)._bits[i] =				\
+	      atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \
+        }				\
+}
+
+__inline static cnodemask_t CNODEMASK_CVTB(int bit) 
+{
+	cnodemask_t __tmp;
+	CNODEMASK_CLRALL(__tmp);
+	CNODEMASK_SETB(__tmp,bit);
+	return(__tmp);
+}
+
+
+__inline static cnodemask_t CNODEMASK_ZERO(void)
+{
+	cnodemask_t __tmp;
+	CNODEMASK_CLRALL(__tmp);
+	return(__tmp);
+}
+
+__inline static int CNODEMASK_IS_ZERO (cnodemask_t p)
+{
+        int i;
+
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
+                if (p._bits[i] != 0)
+                        return 0;
+        return 1;
+}
+
+__inline static int CNODEMASK_IS_NONZERO (cnodemask_t p)
+{
+        int i;
+
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
+                if (p._bits[i] != 0)
+                        return 1;
+        return 0;
+}
+
+__inline static int CNODEMASK_NOTEQ (cnodemask_t p, cnodemask_t q)
+{
+        int i;
+
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
+                if (p._bits[i] != q._bits[i])
+                        return 1;
+        return 0;
+}
+
+__inline static int CNODEMASK_EQ (cnodemask_t p, cnodemask_t q)
+{
+        int i;
+
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
+                if (p._bits[i] != q._bits[i])
+                        return 0;
+        return 1;
+}
+
+
+__inline static int CNODEMASK_TSTM (cnodemask_t p, cnodemask_t q)
+{
+        int i;
+
+        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
+                if (p._bits[i] & q._bits[i])
+                        return 1;
+        return 0;
+}
+
+__inline static void CNODEMASK_SHIFTL_PTR (cnodemask_t *p)
+{
+        int i;
+        uint64_t upper;
+
+        /*
+         * shift words starting with the last word
+         * of the vector and work backward to the first
+         * word updating the low order bits with the
+         * high order bit of the prev word.
+         */
+        for (i=(CNODEMASK_SIZE-1); i > 0; --i) {
+	   upper = (p->_bits[i-1] & (1ULL<<(CNODEMASK_BIPW-1))) ? 1 : 0;
+           p->_bits[i] <<= 1;
+           p->_bits[i] |= upper;
+        }
+        p->_bits[i] <<= 1;
+}
+
+__inline static void CNODEMASK_SHIFTR_PTR (cnodemask_t *p)
+{
+        int i;
+        uint64_t lower;
+
+        /*
+         * shift words starting with the first word
+         * of the vector and work forward to the last
+         * word updating the high order bit with the
+         * low order bit of the next word.
+         */
+        for (i=0; i < (CNODEMASK_SIZE-2); ++i) {
+	   lower = (p->_bits[i+1] & (0x1)) ? 1 : 0;
+           p->_bits[i] >>= 1;
+           p->_bits[i] |= (lower<<((CNODEMASK_BIPW-1)));
+        }
+        p->_bits[i] >>= 1;
+}
+
+__inline static cnodemask_t CNODEMASK_FROM_NUMNODES(int n)
+{
+	cnodemask_t __tmp;
+	int i;
+	CNODEMASK_CLRALL(__tmp);
+	for (i=0; i<n; i++) {
+		CNODEMASK_SETB(__tmp, i);
+	}
+	return(__tmp);
+}
+
+#endif /* SN0XXL || SN1 */
+
+extern cnodemask_t boot_cnodemask;
+
+#endif /* __KERNEL__ || _KMEMUSER */
+
+#endif /* _ASM_SN_NODEMASK_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
new file mode 100644
index 000000000..ee82656f8
--- /dev/null
+++ b/include/asm-ia64/sn/nodepda.h
@@ -0,0 +1,445 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_NODEPDA_H
+#define _ASM_SN_NODEPDA_H
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <linux/config.h>
+#include <asm/sn/agent.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/router.h>
+/* #include <SN/klkernvars.h> */
+#ifdef IRIX
+typedef struct module_s module_t;       /* Avoids sys/SN/module.h */
+#else
+#include <asm/sn/module.h>
+#endif
+/* #include <SN/slotnum.h> */
+
+/*
+ * NUMA Node-Specific Data structures are defined in this file.
+ * In particular, this is the location of the node PDA.
+ * A pointer to the right node PDA is saved in each CPU PDA.
+ */
+
+/*
+ * Subnode PDA structures. Each node needs a few data structures that 
+ * correspond to the PIs on the HUB chip that supports the node.
+ *
+ * WARNING!!!! 6.5.x compatibility requirements prevent us from
+ * changing or reordering fields in the following structure for IP27.
+ * It is essential that the data mappings not change for IP27 platforms.
+ * It is OK to add fields that are IP35 specific if they are under #ifdef IP35.
+ */
+struct subnodepda_s {
+	intr_vecblk_t	intr_dispatch0;
+	intr_vecblk_t	intr_dispatch1;
+	uint64_t	next_prof_timeout;
+	int		prof_count;
+};
+
+
+typedef struct subnodepda_s subnode_pda_t;
+
+
+struct ptpool_s;
+
+
+/*
+ * Node-specific data structure.
+ *
+ * One of these structures is allocated on each node of a NUMA system.
+ * Non-NUMA systems are considered to be systems with one node, and
+ * hence there will be one of this structure for the entire system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all per-node data structures. 
+ */
+
+
+#ifndef CONFIG_IA64_SGI_IO
+/*
+ * The following structure is contained in the nodepda & contains
+ * a lock & queue-head for sanon pages that belong to the node.
+ * See the anon manager for more details.
+ */
+typedef struct {
+	lock_t  sal_lock;
+	plist_t sal_listhead;
+} sanon_list_head_t;
+#endif
+
+
+
+struct nodepda_s {
+
+#ifdef	NUMA_BASE
+
+	/* 
+	 * Pointer to this node's copy of Nodepdaindr 
+	 */
+	struct nodepda_s	**pernode_pdaindr; 
+
+	/*
+         * Data used for migration control
+         */
+	struct migr_control_data_s *mcd; 
+
+	/*
+         * Data used for replication control
+         */
+	struct repl_control_data_s *rcd;
+
+        /*
+         * Numa statistics
+         */
+	struct numa_stats_s *numa_stats;
+
+        /*
+         * Load distribution
+         */
+        uint memfit_assign;
+
+        /*
+         * New extended memory reference counters
+         */
+        void *migr_refcnt_counterbase;
+        void *migr_refcnt_counterbuffer;
+        size_t migr_refcnt_cbsize;
+        int  migr_refcnt_numsets;
+
+        /*
+         * mem_tick quiescing lock
+         */
+        uint mem_tick_lock;
+
+        /*
+         * Migration candidate set
+         * by migration prologue intr handler
+         */
+        uint64_t migr_candidate;
+
+	/*
+	 * Each node gets its own syswait counter to remove contention
+	 * on the global one.
+	 */
+#ifndef CONFIG_IA64_SGI_IO
+	struct syswait syswait;
+#endif
+
+#endif	/* NUMA_BASE */
+	/*
+	 * Node-specific Zone structures.
+	 */
+#ifndef CONFIG_IA64_SGI_IO
+	zoneset_element_t	node_zones;
+	pg_data_t	node_pg_data;	/* VM page data structures */ 
+	plist_t	error_discard_plist;
+#endif
+	uint		error_discard_count;
+	uint		error_page_count;
+	uint		error_cleaned_count;
+	spinlock_t	error_discard_lock;
+
+	/* Information needed for SN Hub chip interrupt handling. */
+	subnode_pda_t	snpda[NUM_SUBNODES];
+	/* Distributed kernel support */
+#ifndef CONFIG_IA64_SGI_IO
+	kern_vars_t	kern_vars;
+#endif
+	/* Vector operation support */
+	/* Change this to a sleep lock? */
+	spinlock_t	vector_lock;
+	/* State of the vector unit for this node */
+	char		vector_unit_busy;
+	cpuid_t         node_first_cpu; /* Starting cpu number for node */
+	ushort          node_num_cpus;  /* Number of cpus present       */
+
+	/* node utlbmiss info */
+  	spinlock_t		node_utlbswitchlock;
+	volatile cpumask_t	node_utlbmiss_flush;
+	volatile signed char	node_need_utlbmiss_patch;
+	volatile char		node_utlbmiss_patched;
+	nodepda_router_info_t	*npda_rip_first;
+	nodepda_router_info_t	**npda_rip_last;
+	int		dependent_routers;
+	devfs_handle_t 	xbow_vhdl;
+	nasid_t		xbow_peer;	/* NASID of our peer hub on xbow */
+	struct semaphore xbow_sema;	/* Sema for xbow synchronization */
+	slotid_t	slotdesc;
+	moduleid_t	module_id;	/* Module ID (redundant local copy) */
+	module_t	*module;	/* Pointer to containing module */
+	int		hub_chip_rev;	/* Rev of my Hub chip */
+	char		nasid_mask[NASID_MASK_BYTES];
+					/* Need a copy of the nasid mask
+					 * on every node */
+	xwidgetnum_t 	basew_id;
+	devfs_handle_t 	basew_xc;
+	spinlock_t	fprom_lock;
+	char		ni_error_print; /* For printing ni error state
+					 * only once during system panic
+					 */
+#ifndef CONFIG_IA64_SGI_IO
+	md_perf_monitor_t node_md_perfmon;
+	hubstat_t	hubstats;
+	int		hubticks;
+	int		huberror_ticks;
+	sbe_info_t	*sbe_info;	/* ECC single-bit error statistics */
+#endif	/* !CONFIG_IA64_SGI_IO */
+
+	router_queue_t  *visited_router_q;
+	router_queue_t	*bfs_router_q; 
+					/* Used for router traversal */
+#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+	router_map_ent_t router_map[MAX_RTR_BREADTH];
+#endif
+	int		num_routers;	/* Total routers in the system */
+
+        char		membank_flavor;
+	                                /* Indicates what sort of memory 
+					 * banks are present on this node
+					 */
+	
+	char		*hwg_node_name;	/* hwgraph node name */
+
+	struct widget_info_t *widget_info;	/* Node as xtalk widget */
+	devfs_handle_t	node_vertex;	/* Hwgraph vertex for this node */
+
+	void 		*pdinfo;	/* Platform-dependent per-node info */
+	uint64_t	*dump_stack;	/* Dump stack during nmi handling */
+	int		dump_count;	/* To allow only one cpu-per-node */
+#if defined BRINGUP
+#ifndef CONFIG_IA64_SGI_IO
+	io_perf_monitor_t node_io_perfmon;
+#endif
+#endif
+
+	/*
+	 * Each node gets its own pdcount counter to remove contention
+	 * on the global one.
+	 */
+
+	int pdcount;			/* count of pdinserted pages */
+
+#ifdef	NUMA_BASE
+	void		*cached_global_pool;	/* pointer to cached vmpool */
+#endif /* NUMA_BASE */
+
+#ifndef CONFIG_IA64_SGI_IO
+	sanon_list_head_t sanon_list_head;	/* head for sanon pages */	
+#endif
+#ifdef	NUMA_BASE
+	struct ptpool_s	*ptpool;	/* ptpool for this node */
+#endif /* NUMA_BASE */
+
+	/*
+	 * The BTEs on this node are shared by the local cpus
+	 */
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#ifndef CONFIG_IA64_SGI_IO
+	bteinfo_t	*node_bte_info[BTES_PER_NODE];
+#endif
+#endif
+};
+
+typedef struct nodepda_s nodepda_t;
+
+
+#define NODE_MODULEID(_node)	(NODEPDA(_node)->module_id)
+#define NODE_SLOTID(_node)	(NODEPDA(_node)->slotdesc)
+
+#ifdef	NUMA_BASE
+/*
+ * Access Functions for node PDA.
+ * Since there is one nodepda for each node, we need a convenient mechanism
+ * to access these nodepdas without cluttering code with #ifdefs.
+ * The next set of definitions provides this.
+ * Routines are expected to use 
+ *
+ *	nodepda		-> to access PDA for the node on which code is running
+ *	subnodepda	-> to access subnode PDA for the node on which code is running
+ *
+ *	NODEPDA(x)	-> to access node PDA for cnodeid 'x'
+ *	SUBNODEPDA(x,s)	-> to access subnode PDA for cnodeid/slice 'x'
+ */
+
+#ifndef CONFIG_IA64_SGI_IO
+#define	nodepda		private.p_nodepda	/* Ptr to this node's PDA */
+#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#define subnodepda	private.p_subnodepda	/* Ptr to this node's subnode PDA */
+#endif
+
+#else
+/*
+ * Until we have a shared node local area defined, do it this way ..
+ * like in Caliase space.  See above.
+ */
+extern nodepda_t        *nodepda;
+extern subnode_pda_t	*subnodepda;
+#endif
+
+/* 
+ * Nodepdaindr[]
+ * This is a private data structure for use only in early initialization.
+ * All users of nodepda should use the macro NODEPDA(nodenum) to get
+ * the suitable nodepda structure.
+ * This macro has the advantage of not requiring #ifdefs for NUMA and
+ * non-NUMA code.
+ */
+extern nodepda_t	*Nodepdaindr[]; 
+/*
+ * NODEPDA_GLOBAL(x) macro should ONLY be used during early initialization.
+ * Once meminit is complete, NODEPDA(x) is ready to use.
+ * During early init, the system fills up Nodepdaindr.  By the time we
+ * are in meminit(), all nodepdas are initialized, and hence
+ * we can fill up the node_pdaindr array in each nodepda structure.
+ */
+#define	NODEPDA_GLOBAL(x)	Nodepdaindr[x]
+
+/*
+ * Returns a pointer to a given node's nodepda.
+ */
+#define	NODEPDA(x)		(nodepda->pernode_pdaindr[x])
+
+/*
+ * Returns a pointer to a given node/slice's subnodepda.
+ *	SUBNODEPDA(cnode, subnode) - uses cnode as first arg
+ *	SNPDA(npda, subnode)	   - uses pointer to nodepda as first arg
+ */
+#define	SUBNODEPDA(x,sn)	(&nodepda->pernode_pdaindr[x]->snpda[sn])
+#define	SNPDA(npda,sn)		(&(npda)->snpda[sn])
+
+#define NODEPDA_ERROR_FOOTPRINT(node, cpu) \
+                   (&(NODEPDA(node)->error_stamp[cpu]))
+#define NODEPDA_MDP_MON(node)	(&(NODEPDA(node)->node_md_perfmon))
+#define NODEPDA_IOP_MON(node)	(&(NODEPDA(node)->node_io_perfmon))
+
+/*
+ * Macros to access data structures inside nodepda 
+ */
+#if NUMA_MIGR_CONTROL
+#define NODEPDA_MCD(node) (NODEPDA(node)->mcd)
+#endif /* NUMA_MIGR_CONTROL */
+
+#if NUMA_REPL_CONTROL
+#define NODEPDA_RCD(node) (NODEPDA(node)->rcd)
+#endif /* NUMA_REPL_CONTROL */
+
+#if (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL)
+#define NODEPDA_LRS(node) (NODEPDA(node)->lrs)
+#endif /* (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL) */
+
+/* 
+ * Exported functions
+ */
+extern nodepda_t *nodepda_alloc(void);
+
+#else	/* !NUMA_BASE */
+/*
+ * For a single-node system we will just have one global nodepda pointer
+ * allocated at startup.  The global nodepda will point to this nodepda 
+ * structure.
+ */
+extern nodepda_t	*Nodepdaindr; 
+
+/*
+ * On non-NUMA systems, NODEPDA_GLOBAL and NODEPDA macros collapse to
+ * be the same.
+ */
+#define	NODEPDA_GLOBAL(x)	Nodepdaindr
+
+/*
+ * Returns a pointer to a given node's nodepda.
+ */
+#define	NODEPDA(x)	Nodepdaindr
+
+/*
+ * nodepda can also be defined as private.p_nodepda.
+ * But on non-NUMA systems, there is only one nodepda, and there is
+ * no reason to go through the PDA to access this pointer.
+ * Hence nodepda aliases to the global nodepda directly.
+ *
+ * Routines should use nodepda to access the local node's PDA.
+ */
+#define	nodepda		(Nodepdaindr)
+
+#endif	/* NUMA_BASE */
+
+/* Quickly convert a compact node ID into a hwgraph vertex */
+#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex)
+
+
+/* Check if given a compact node id the corresponding node has all the
+ * cpus disabled. 
+ */
+#define is_headless_node(_cnode)	((_cnode == CNODEID_NONE) || \
+					 (CNODE_NUM_CPUS(_cnode) == 0))
+/* Check if given a node vertex handle the corresponding node has all the
+ * cpus disabled. 
+ */
+#define is_headless_node_vertex(_nodevhdl) \
+			is_headless_node(nodevertex_to_cnodeid(_nodevhdl))
+
+#ifdef	__cplusplus
+}
+#endif
+
+#ifdef NUMA_BASE
+/*
+ * To remove contention on the global syswait counter each node will have
+ * its own.  Each clock tick the clock cpu will re-calculate the global
+ * syswait counter by summing from each of the nodes.  The other cpus will
+ * continue to read the global one during their clock ticks.   This does 
+ * present a problem when a thread increments the count on one node and wakes
+ * up on a different node and decrements it there.  Eventually the count could
+ * overflow if this happens continually for a long period.  To prevent this
+ * second_thread() periodically preserves the current syswait state and
+ * resets the counters.
+ */
+#define ADD_SYSWAIT(_field)	atomicAddInt(&nodepda->syswait._field, 1)
+#define SUB_SYSWAIT(_field)	atomicAddInt(&nodepda->syswait._field, -1)
+#else
+#define ADD_SYSWAIT(_field)				\
+{							\
+	ASSERT(syswait._field >= 0);			\
+	atomicAddInt(&syswait._field, 1);		\
+}
+#define SUB_SYSWAIT(_field)				\
+{							\
+	ASSERT(syswait._field > 0);			\
+	atomicAddInt(&syswait._field, -1);		\
+}
+#endif /* NUMA_BASE */
+
+#ifdef NUMA_BASE
+/*
+ * Another global variable to remove contention from: pdcount.
+ * See above comments for SYSWAIT.
+ */
+#define ADD_PDCOUNT(_n)					\
+{							\
+	atomicAddInt(&nodepda->pdcount, _n);		\
+	if (_n > 0 && !pdflag)				\
+		pdflag = 1;				\
+}
+#else
+#define ADD_PDCOUNT(_n)					\
+{							\
+	ASSERT(&pdcount >= 0);				\
+	atomicAddInt(&pdcount, _n);			\
+	if (_n > 0 && !pdflag)				\
+		pdflag = 1;				\
+}
+#endif /* NUMA_BASE */
+
+#endif /* _ASM_SN_NODEPDA_H */
diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h
new file mode 100644
index 000000000..f070d6d2c
--- /dev/null
+++ b/include/asm-ia64/sn/pci/bridge.h
@@ -0,0 +1,1729 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_BRIDGE_H
+#define _ASM_SN_PCI_BRIDGE_H
+
+
+/*
+ * bridge.h - header file for bridge chip and bridge portion of xbridge chip
+ */
+
+#include <asm/sn/xtalk/xwidget.h>
+
+/* I/O page size */
+
+#if _PAGESZ == 4096
+#define IOPFNSHIFT		12	/* 4K per mapped page */
+#else
+#define IOPFNSHIFT		14	/* 16K per mapped page */
+#endif				/* _PAGESZ */
+
+#define IOPGSIZE		(1 << IOPFNSHIFT)
+#define IOPG(x)			((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)		((x) & (IOPGSIZE-1))
+
+/* Bridge RAM sizes */
+
+#define BRIDGE_INTERNAL_ATES	128
+#define XBRIDGE_INTERNAL_ATES	1024
+
+#define BRIDGE_ATE_RAM_SIZE     (BRIDGE_INTERNAL_ATES<<3)	/* 1kB ATE */
+#define XBRIDGE_ATE_RAM_SIZE    (XBRIDGE_INTERNAL_ATES<<3)	/* 8kB ATE */
+
+#define BRIDGE_CONFIG_BASE	0x20000		/* start of bridge's */
+						/* map to each device's */
+						/* config space */
+#define BRIDGE_CONFIG1_BASE	0x28000		/* type 1 device config space */
+#define BRIDGE_CONFIG_END	0x30000
+#define BRIDGE_CONFIG_SLOT_SIZE 0x1000		/* each map == 4k */
+
+#define BRIDGE_SSRAM_512K	0x00080000	/* 512kB */
+#define BRIDGE_SSRAM_128K	0x00020000	/* 128kB */
+#define BRIDGE_SSRAM_64K	0x00010000	/* 64kB */
+#define BRIDGE_SSRAM_0K		0x00000000	/* 0kB */
+
+/* ========================================================================
+ *    Bridge address map
+ */
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * All accesses to bridge hardware registers must be done
+ * using 32-bit loads and stores.
+ */
+typedef uint32_t	bridgereg_t;
+
+typedef uint64_t	bridge_ate_t;
+
+/* pointers to bridge ATEs
+ * are always "pointer to volatile"
+ */
+typedef volatile bridge_ate_t  *bridge_ate_p;
+
+/*
+ * It is generally preferred that hardware registers on the bridge
+ * are located from C code via this structure.
+ *
+ * Generated from Bridge spec dated 04oct95
+ */
+
+#ifdef LITTLE_ENDIAN
+
+typedef volatile struct bridge_s {
+
+    /* Local Registers				       0x000000-0x00FFFF */
+
+    /* standard widget configuration		       0x000000-0x000057 */
+    widget_cfg_t	    b_widget;		    /* 0x000000 */
+
+    /* helper fieldnames for accessing bridge widget */
+
+#define b_wid_id			b_widget.w_id
+#define b_wid_stat			b_widget.w_status
+#define b_wid_err_upper			b_widget.w_err_upper_addr
+#define b_wid_err_lower			b_widget.w_err_lower_addr
+#define b_wid_control			b_widget.w_control
+#define b_wid_req_timeout		b_widget.w_req_timeout
+#define b_wid_int_upper			b_widget.w_intdest_upper_addr
+#define b_wid_int_lower			b_widget.w_intdest_lower_addr
+#define b_wid_err_cmdword		b_widget.w_err_cmd_word
+#define b_wid_llp			b_widget.w_llp_cfg
+#define b_wid_tflush			b_widget.w_tflush
+
+    /*
+     * we access these through synergy unswizzled space, so the address
+     * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
+     * That's why we put the register first and filler second.
+     */
+    /* bridge-specific widget configuration	       0x000058-0x00007F */
+    bridgereg_t             b_wid_aux_err;          /* 0x00005C */
+    bridgereg_t		    _pad_000058;
+
+    bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
+    bridgereg_t             _pad_000060;
+
+    bridgereg_t             b_wid_resp_lower;       /* 0x00006C */
+    bridgereg_t             _pad_000068;
+
+    bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
+    bridgereg_t             _pad_000070;
+
+    bridgereg_t		    _pad_000078[2];
+
+    /* PMU & Map				       0x000080-0x00008F */
+    bridgereg_t             b_dir_map;              /* 0x000084 */
+    bridgereg_t             _pad_000080;
+    bridgereg_t		    _pad_000088[2];
+
+    /* SSRAM					       0x000090-0x00009F */
+    bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
+    bridgereg_t             _pad_000090;
+#define b_ram_perr  b_ram_perr_or_map_fault	/* Bridge */
+#define b_map_fault b_ram_perr_or_map_fault	/* Xbridge */
+    bridgereg_t		    _pad_000098[2];
+
+    /* Arbitration				       0x0000A0-0x0000AF */
+    bridgereg_t             b_arb;                  /* 0x0000A4 */
+    bridgereg_t             _pad_0000A0;
+    bridgereg_t		    _pad_0000A8[2];
+
+    /* Number In A Can				       0x0000B0-0x0000BF */
+    bridgereg_t             b_nic;                  /* 0x0000B4 */
+    bridgereg_t             _pad_0000B0;
+    bridgereg_t		    _pad_0000B8[2];
+
+    /* PCI/GIO					       0x0000C0-0x0000FF */
+    bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
+    bridgereg_t             _pad_0000C0;
+#define b_pci_bus_timeout b_bus_timeout
+
+    bridgereg_t             b_pci_cfg;              /* 0x0000CC */
+    bridgereg_t             _pad_0000C8;
+
+    bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
+    bridgereg_t             _pad_0000D0;
+
+    bridgereg_t             b_pci_err_lower;        /* 0x0000DC */
+    bridgereg_t             _pad_0000D8;
+    bridgereg_t		    _pad_0000E0[8];
+#define b_gio_err_lower b_pci_err_lower
+#define b_gio_err_upper b_pci_err_upper
+
+    /* Interrupt				       0x000100-0x0001FF */
+    bridgereg_t             b_int_status;           /* 0x000104 */
+    bridgereg_t             _pad_000100;
+
+    bridgereg_t             b_int_enable;           /* 0x00010C */
+    bridgereg_t             _pad_000108;
+
+    bridgereg_t             b_int_rst_stat;         /* 0x000114 */
+    bridgereg_t             _pad_000110;
+
+    bridgereg_t             b_int_mode;             /* 0x00011C */
+    bridgereg_t             _pad_000118;
+
+    bridgereg_t             b_int_device;           /* 0x000124 */
+    bridgereg_t             _pad_000120;
+
+    bridgereg_t             b_int_host_err;         /* 0x00012C */
+    bridgereg_t             _pad_000128;
+
+    struct {
+        bridgereg_t             addr;               /* 0x0001{34,,,6C} */
+        bridgereg_t             __pad;              /* 0x0001{30,,,68} */
+    } b_int_addr[8];				    /* 0x000130 */
+
+    bridgereg_t             b_err_int_view;         /* 0x000174 */
+    bridgereg_t             _pad_000170;
+
+    bridgereg_t             b_mult_int;             /* 0x00017c */
+    bridgereg_t             _pad_000178;
+
+    struct {
+        bridgereg_t             intr;               /* 0x0001{84,,,BC} */
+        bridgereg_t             __pad;              /* 0x0001{80,,,B8} */
+    } b_force_always[8];			    /* 0x000180 */
+
+    struct {
+        bridgereg_t             intr;               /* 0x0001{C4,,,FC} */
+        bridgereg_t             __pad;              /* 0x0001{C0,,,F8} */
+    } b_force_pin[8];			    	    /* 0x0001C0 */
+
+    /* Device					       0x000200-0x0003FF */
+    struct {
+        bridgereg_t             reg;                /* 0x0002{04,,,3C} */
+        bridgereg_t             __pad;              /* 0x0002{00,,,38} */
+    } b_device[8];				    /* 0x000200 */
+
+    struct {
+        bridgereg_t             reg;                /* 0x0002{44,,,7C} */
+        bridgereg_t             __pad;              /* 0x0002{40,,,78} */
+    } b_wr_req_buf[8];				    /* 0x000240 */
+
+    struct {
+        bridgereg_t             reg;                /* 0x0002{84,,,8C} */
+        bridgereg_t             __pad;              /* 0x0002{80,,,88} */
+    } b_rrb_map[2];				    /* 0x000280 */
+#define	b_even_resp	b_rrb_map[0].reg	    /* 0x000284 */
+#define	b_odd_resp	b_rrb_map[1].reg	    /* 0x00028C */
+
+    bridgereg_t             b_resp_status;          /* 0x000294 */
+    bridgereg_t             _pad_000290;
+
+    bridgereg_t             b_resp_clear;           /* 0x00029C */
+    bridgereg_t             _pad_000298;
+
+    bridgereg_t		    _pad_0002A0[24];
+
+    /* Xbridge only */
+    struct {
+	bridgereg_t	        upper;              /* 0x0003{04,,,F4} */
+	bridgereg_t             __pad1;		    /* 0x0003{00,,,F0} */
+	bridgereg_t             lower;              /* 0x0003{0C,,,FC} */
+	bridgereg_t             __pad2;             /* 0x0003{08,,,F8} */
+    } b_buf_addr_match[16];
+
+    /* Performance Monitor Registers (even only) */
+    struct {
+        bridgereg_t             flush_w_touch;      /* 0x000404,,,5C4 */
+        bridgereg_t             __pad1;             /* 0x000400,,,5C0 */
+
+        bridgereg_t             flush_wo_touch;     /* 0x00040C,,,5CC */
+        bridgereg_t             __pad2;             /* 0x000408,,,5C8 */
+
+        bridgereg_t             inflight;           /* 0x000414,,,5D4 */
+        bridgereg_t             __pad3;             /* 0x000410,,,5D0 */
+
+        bridgereg_t             prefetch;           /* 0x00041C,,,5DC */
+        bridgereg_t             __pad4;             /* 0x000418,,,5D8 */
+
+        bridgereg_t             total_pci_retry;    /* 0x000424,,,5E4 */
+        bridgereg_t             __pad5;             /* 0x000420,,,5E0 */
+
+        bridgereg_t             max_pci_retry;      /* 0x00042C,,,5EC */
+        bridgereg_t             __pad6;             /* 0x000428,,,5E8 */
+
+        bridgereg_t             max_latency;        /* 0x000434,,,5F4 */
+        bridgereg_t             __pad7;             /* 0x000430,,,5F0 */
+
+        bridgereg_t             clear_all;          /* 0x00043C,,,5FC */
+        bridgereg_t             __pad8;             /* 0x000438,,,5F8 */
+    } b_buf_count[8];
+
+    char                    _pad_000600[0x010000 - 0x000600];
+
+    /*
+     * The Xbridge has 1024 internal ATE's and the Bridge has 128.
+     * Make enough room for the Xbridge ATE's and depend on runtime
+     * checks to limit access to bridge ATE's.
+     */
+
+    /* Internal Address Translation Entry RAM	       0x010000-0x011fff */
+    union {
+	bridge_ate_t		wr;		/* write-only */
+	struct {
+	    bridgereg_t             rd;         /* read-only */
+            bridgereg_t             _p_pad;
+	}			hi;
+    }			    b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
+
+#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
+
+    /* the xbridge read path for internal ates starts at 0x12000.
+     * I don't believe we ever try to read the ates.
+     */
+    /* Internal Address Translation Entry RAM LOW       0x012000-0x013fff */
+    struct {
+	bridgereg_t             rd; 
+        bridgereg_t             _p_pad;
+    }			    xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
+
+    char		    _pad_014000[0x20000 - 0x014000];
+
+    /* PCI Device Configuration Spaces		       0x020000-0x027FFF */
+    union {				/* make all access sizes available. */
+	uchar_t			c[0x1000 / 1];
+	uint16_t		s[0x1000 / 2];
+	uint32_t		l[0x1000 / 4];
+	uint64_t		d[0x1000 / 8];
+	union {
+	    uchar_t		c[0x100 / 1];
+	    uint16_t		s[0x100 / 2];
+	    uint32_t		l[0x100 / 4];
+	    uint64_t		d[0x100 / 8];
+	}			f[8];
+    } b_type0_cfg_dev[8];			    /* 0x020000 */
+
+    /* PCI Type 1 Configuration Space		       0x028000-0x028FFF */
+    union {				/* make all access sizes available. */
+	uchar_t			c[0x1000 / 1];
+	uint16_t		s[0x1000 / 2];
+	uint32_t		l[0x1000 / 4];
+	uint64_t		d[0x1000 / 8];
+    } b_type1_cfg;				    /* 0x028000-0x029000 */
+
+    char		    _pad_029000[0x007000];  /* 0x029000-0x030000 */
+
+    /* PCI Interrupt Acknowledge Cycle		       0x030000 */
+    union {
+	uchar_t			c[8 / 1];
+	uint16_t		s[8 / 2];
+	uint32_t		l[8 / 4];
+	uint64_t		d[8 / 8];
+    } b_pci_iack;				    /* 0x030000 */
+
+    uchar_t		    _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */
+
+    /* External Address Translation Entry RAM	       0x080000-0x0FFFFF */
+    bridge_ate_t	    b_ext_ate_ram[0x10000];
+
+    /* Reserved					       0x100000-0x1FFFFF */
+    char		    _pad_100000[0x200000-0x100000];
+
+    /* PCI/GIO Device Spaces			       0x200000-0xBFFFFF */
+    union {				/* make all access sizes available. */
+	uchar_t			c[0x100000 / 1];
+	uint16_t		s[0x100000 / 2];
+	uint32_t		l[0x100000 / 4];
+	uint64_t		d[0x100000 / 8];
+    } b_devio_raw[10];			/* 0x200000 */
+
+    /* b_devio macro is a bit strange; it reflects the
+     * fact that the Bridge ASIC provides 2M for the
+     * first two DevIO windows and 1M for the other six.
+     */
+#define b_devio(n)	b_devio_raw[((n)<2)?(n*2):(n+2)]
+
+    /* External Flash Proms 1,0			       0xC00000-0xFFFFFF */
+    union {				/* make all access sizes available. */
+	uchar_t			c[0x400000 / 1];	/* read-only */
+	uint16_t		s[0x400000 / 2];	/* read-write */
+	uint32_t		l[0x400000 / 4];	/* read-only */
+	uint64_t		d[0x400000 / 8];	/* read-only */
+    } b_external_flash;			/* 0xC00000 */
+} bridge_t;
+
+#else
+
+/*
+ * Field formats for Error Command Word and Auxillary Error Command Word
+ * of bridge.
+ */
+typedef struct bridge_err_cmdword_s {
+    union {
+	uint32_t		cmd_word;
+	struct {
+	    uint32_t		    didn:4,	/* Destination ID */
+				    sidn:4,	/* SOurce ID	  */
+				    pactyp:4,	/* Packet type	  */
+				    tnum:5,	/* Trans Number	  */
+				    coh:1,	/* Coh Transacti  */
+				    ds:2,	/* Data size	  */
+				    gbr:1,	/* GBR enable	  */
+				    vbpm:1,	/* VBPM message	  */
+				    error:1,	/* Error occured  */
+				    barr:1,	/* Barrier op	  */
+				    rsvd:8;
+	} berr_st;
+    } berr_un;
+} bridge_err_cmdword_t;
+
+typedef volatile struct bridge_s {
+
+    /* Local Registers                                 0x000000-0x00FFFF */
+
+    /* standard widget configuration                   0x000000-0x000057 */
+    widget_cfg_t            b_widget;               /* 0x000000 */
+
+    /* helper fieldnames for accessing bridge widget */
+
+#define b_wid_id                        b_widget.w_id
+#define b_wid_stat                      b_widget.w_status
+#define b_wid_err_upper                 b_widget.w_err_upper_addr
+#define b_wid_err_lower                 b_widget.w_err_lower_addr
+#define b_wid_control                   b_widget.w_control
+#define b_wid_req_timeout               b_widget.w_req_timeout
+#define b_wid_int_upper                 b_widget.w_intdest_upper_addr
+#define b_wid_int_lower                 b_widget.w_intdest_lower_addr
+#define b_wid_err_cmdword               b_widget.w_err_cmd_word
+#define b_wid_llp                       b_widget.w_llp_cfg
+#define b_wid_tflush                    b_widget.w_tflush
+
+    /* bridge-specific widget configuration            0x000058-0x00007F */
+    bridgereg_t             _pad_000058;
+    bridgereg_t             b_wid_aux_err;          /* 0x00005C */
+    bridgereg_t             _pad_000060;
+    bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
+    bridgereg_t             _pad_000068;
+    bridgereg_t             b_wid_resp_lower;       /* 0x00006C */
+    bridgereg_t             _pad_000070;
+    bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
+    bridgereg_t             _pad_000078[2];
+
+    /* PMU & Map                                       0x000080-0x00008F */
+    bridgereg_t             _pad_000080;
+    bridgereg_t             b_dir_map;              /* 0x000084 */
+    bridgereg_t             _pad_000088[2];
+
+    /* SSRAM                                           0x000090-0x00009F */
+    bridgereg_t             _pad_000090;
+    bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
+#define b_ram_perr  b_ram_perr_or_map_fault     /* Bridge */
+#define b_map_fault b_ram_perr_or_map_fault     /* Xbridge */
+    bridgereg_t             _pad_000098[2];
+
+    /* Arbitration                                     0x0000A0-0x0000AF */
+    bridgereg_t             _pad_0000A0;
+    bridgereg_t             b_arb;                  /* 0x0000A4 */
+    bridgereg_t             _pad_0000A8[2];
+
+    /* Number In A Can                                 0x0000B0-0x0000BF */
+    bridgereg_t             _pad_0000B0;
+    bridgereg_t             b_nic;                  /* 0x0000B4 */
+    bridgereg_t             _pad_0000B8[2];
+
+    /* PCI/GIO                                         0x0000C0-0x0000FF */
+    bridgereg_t             _pad_0000C0;
+    bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
+#define b_pci_bus_timeout b_bus_timeout
+
+    bridgereg_t             _pad_0000C8;
+    bridgereg_t             b_pci_cfg;              /* 0x0000CC */
+    bridgereg_t             _pad_0000D0;
+    bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
+    bridgereg_t             _pad_0000D8;
+    bridgereg_t             b_pci_err_lower;        /* 0x0000DC */
+    bridgereg_t             _pad_0000E0[8];
+#define b_gio_err_lower b_pci_err_lower
+#define b_gio_err_upper b_pci_err_upper
+
+    /* Interrupt                                       0x000100-0x0001FF */
+    bridgereg_t             _pad_000100;
+    bridgereg_t             b_int_status;           /* 0x000104 */
+    bridgereg_t             _pad_000108;
+    bridgereg_t             b_int_enable;           /* 0x00010C */
+    bridgereg_t             _pad_000110;
+    bridgereg_t             b_int_rst_stat;         /* 0x000114 */
+    bridgereg_t             _pad_000118;
+    bridgereg_t             b_int_mode;             /* 0x00011C */
+    bridgereg_t             _pad_000120;
+    bridgereg_t             b_int_device;           /* 0x000124 */
+    bridgereg_t             _pad_000128;
+    bridgereg_t             b_int_host_err;         /* 0x00012C */
+
+    struct {
+        bridgereg_t             __pad;              /* 0x0001{30,,,68} */
+        bridgereg_t             addr;               /* 0x0001{34,,,6C} */
+    } b_int_addr[8];                                /* 0x000130 */
+
+    bridgereg_t             _pad_000170;
+    bridgereg_t             b_err_int_view;         /* 0x000174 */
+    bridgereg_t             _pad_000178;
+    bridgereg_t             b_mult_int;             /* 0x00017c */
+
+    struct {
+        bridgereg_t             __pad;              /* 0x0001{80,,,B8} */
+        bridgereg_t             intr;               /* 0x0001{84,,,BC} */
+    } b_force_always[8];                            /* 0x000180 */
+
+    struct {
+        bridgereg_t             __pad;              /* 0x0001{C0,,,F8} */
+        bridgereg_t             intr;               /* 0x0001{C4,,,FC} */
+    } b_force_pin[8];                               /* 0x0001C0 */
+
+    /* Device                                          0x000200-0x0003FF */
+    struct {
+        bridgereg_t             __pad;              /* 0x0002{00,,,38} */
+        bridgereg_t             reg;                /* 0x0002{04,,,3C} */
+    } b_device[8];                                  /* 0x000200 */
+
+    struct {
+        bridgereg_t             __pad;              /* 0x0002{40,,,78} */
+        bridgereg_t             reg;                /* 0x0002{44,,,7C} */
+    } b_wr_req_buf[8];                              /* 0x000240 */
+
+    struct {
+        bridgereg_t             __pad;              /* 0x0002{80,,,88} */
+        bridgereg_t             reg;                /* 0x0002{84,,,8C} */
+    } b_rrb_map[2];                                 /* 0x000280 */
+#define b_even_resp     b_rrb_map[0].reg            /* 0x000284 */
+#define b_odd_resp      b_rrb_map[1].reg            /* 0x00028C */
+
+    bridgereg_t             _pad_000290;
+    bridgereg_t             b_resp_status;          /* 0x000294 */
+    bridgereg_t             _pad_000298;
+    bridgereg_t             b_resp_clear;           /* 0x00029C */
+
+    bridgereg_t             _pad_0002A0[24];
+
+    /* Xbridge only */
+    struct {
+        bridgereg_t             __pad1;             /* 0x0003{00,,,F0} */
+        bridgereg_t             upper;              /* 0x0003{04,,,F4} */
+        bridgereg_t             __pad2;             /* 0x0003{08,,,F8} */
+        bridgereg_t             lower;              /* 0x0003{0C,,,FC} */
+    } b_buf_addr_match[16];
+
+    /* Performance Monitor Registers (even only) */
+    struct {
+        bridgereg_t             __pad1;             /* 0x000400,,,5C0 */
+        bridgereg_t             flush_w_touch;      /* 0x000404,,,5C4 */
+        bridgereg_t             __pad2;             /* 0x000408,,,5C8 */
+        bridgereg_t             flush_wo_touch;     /* 0x00040C,,,5CC */
+        bridgereg_t             __pad3;             /* 0x000410,,,5D0 */
+        bridgereg_t             inflight;           /* 0x000414,,,5D4 */
+        bridgereg_t             __pad4;             /* 0x000418,,,5D8 */
+        bridgereg_t             prefetch;           /* 0x00041C,,,5DC */
+        bridgereg_t             __pad5;             /* 0x000420,,,5E0 */
+        bridgereg_t             total_pci_retry;    /* 0x000424,,,5E4 */
+        bridgereg_t             __pad6;             /* 0x000428,,,5E8 */
+        bridgereg_t             max_pci_retry;      /* 0x00042C,,,5EC */
+        bridgereg_t             __pad7;             /* 0x000430,,,5F0 */
+        bridgereg_t             max_latency;        /* 0x000434,,,5F4 */
+        bridgereg_t             __pad8;             /* 0x000438,,,5F8 */
+        bridgereg_t             clear_all;          /* 0x00043C,,,5FC */
+    } b_buf_count[8];
+
+    char                    _pad_000600[0x010000 - 0x000600];
+
+    /*
+     * The Xbridge has 1024 internal ATE's and the Bridge has 128.
+     * Make enough room for the Xbridge ATE's and depend on runtime
+     * checks to limit access to bridge ATE's.
+     */
+
+    /* Internal Address Translation Entry RAM          0x010000-0x011fff */
+    union {
+        bridge_ate_t            wr;             /* write-only */
+        struct {
+            bridgereg_t             _p_pad;
+            bridgereg_t             rd;         /* read-only */
+        }                       hi;
+    }                       b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
+
+#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
+
+    /* the xbridge read path for internal ates starts at 0x12000.
+     * I don't believe we ever try to read the ates.
+     */
+    /* Internal Address Translation Entry RAM LOW       0x012000-0x013fff */
+    struct {
+        bridgereg_t             _p_pad;
+        bridgereg_t             rd;             /* read-only */
+    }                       xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
+
+    char                    _pad_014000[0x20000 - 0x014000];
+
+    /* PCI Device Configuration Spaces                 0x020000-0x027FFF */
+    union {                             /* make all access sizes available. */
+        uchar_t                 c[0x1000 / 1];
+        uint16_t                s[0x1000 / 2];
+        uint32_t              l[0x1000 / 4];
+        uint64_t              d[0x1000 / 8];
+        union {
+            uchar_t             c[0x100 / 1];
+            uint16_t            s[0x100 / 2];
+            uint32_t          l[0x100 / 4];
+            uint64_t          d[0x100 / 8];
+        }                       f[8];
+    } b_type0_cfg_dev[8];                           /* 0x020000 */
+
+
+    /* PCI Type 1 Configuration Space                  0x028000-0x028FFF */
+    union {                             /* make all access sizes available. */
+        uchar_t                 c[0x1000 / 1];
+        uint16_t                s[0x1000 / 2];
+        uint32_t              l[0x1000 / 4];
+        uint64_t              d[0x1000 / 8];
+    } b_type1_cfg;                                  /* 0x028000-0x029000 */
+
+    char                    _pad_029000[0x007000];  /* 0x029000-0x030000 */
+
+    /* PCI Interrupt Acknowledge Cycle                 0x030000 */
+    union {
+        uchar_t                 c[8 / 1];
+        uint16_t                s[8 / 2];
+        uint32_t              l[8 / 4];
+        uint64_t              d[8 / 8];
+    } b_pci_iack;                                   /* 0x030000 */
+
+    uchar_t                 _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */
+
+    /* External Address Translation Entry RAM          0x080000-0x0FFFFF */
+    bridge_ate_t            b_ext_ate_ram[0x10000];
+
+    /* Reserved                                        0x100000-0x1FFFFF */
+    char                    _pad_100000[0x200000-0x100000];
+
+    /* PCI/GIO Device Spaces                           0x200000-0xBFFFFF */
+    union {                             /* make all access sizes available. */
+        uchar_t                 c[0x100000 / 1];
+        uint16_t                s[0x100000 / 2];
+        uint32_t              l[0x100000 / 4];
+        uint64_t              d[0x100000 / 8];
+    } b_devio_raw[10];                  /* 0x200000 */
+
+    /* b_devio macro is a bit strange; it reflects the
+     * fact that the Bridge ASIC provides 2M for the
+     * first two DevIO windows and 1M for the other six.
+     */
+#define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
+
+    /* External Flash Proms 1,0                        0xC00000-0xFFFFFF */
+    union {                             /* make all access sizes available. */
+        uchar_t                 c[0x400000 / 1];        /* read-only */
+        uint16_t                s[0x400000 / 2];        /* read-write */
+        uint32_t              l[0x400000 / 4];        /* read-only */
+        uint64_t              d[0x400000 / 8];        /* read-only */
+    } b_external_flash;                 /* 0xC00000 */
+} bridge_t;
+
+#endif
+
+
+
+
+
+
+#define berr_field	berr_un.berr_st
+#endif				/* LANGUAGE_C */
+
+/*
+ * The values of these macros can and should be crosschecked
+ * regularly against the offsets of the like-named fields
+ * within the "bridge_t" structure above.
+ */
+
+/* Byte offset macros for Bridge internal registers */
+
+#define BRIDGE_WID_ID		WIDGET_ID
+#define BRIDGE_WID_STAT		WIDGET_STATUS
+#define BRIDGE_WID_ERR_UPPER	WIDGET_ERR_UPPER_ADDR
+#define BRIDGE_WID_ERR_LOWER	WIDGET_ERR_LOWER_ADDR
+#define BRIDGE_WID_CONTROL	WIDGET_CONTROL
+#define BRIDGE_WID_REQ_TIMEOUT	WIDGET_REQ_TIMEOUT
+#define BRIDGE_WID_INT_UPPER	WIDGET_INTDEST_UPPER_ADDR
+#define BRIDGE_WID_INT_LOWER	WIDGET_INTDEST_LOWER_ADDR
+#define BRIDGE_WID_ERR_CMDWORD	WIDGET_ERR_CMD_WORD
+#define BRIDGE_WID_LLP		WIDGET_LLP_CFG
+#define BRIDGE_WID_TFLUSH	WIDGET_TFLUSH
+
+#define BRIDGE_WID_AUX_ERR	0x00005C	/* Aux Error Command Word */
+#define BRIDGE_WID_RESP_UPPER	0x000064	/* Response Buf Upper Addr */
+#define BRIDGE_WID_RESP_LOWER	0x00006C	/* Response Buf Lower Addr */
+#define BRIDGE_WID_TST_PIN_CTRL 0x000074	/* Test pin control */
+
+#define BRIDGE_DIR_MAP		0x000084	/* Direct Map reg */
+
+/* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */
+#define BRIDGE_RAM_PERR 	0x000094	/* SSRAM Parity Error */
+#define BRIDGE_MAP_FAULT	0x000094	/* Map Fault */
+
+#define BRIDGE_ARB		0x0000A4	/* Arbitration Priority reg */
+
+#define BRIDGE_NIC		0x0000B4	/* Number In A Can */
+
+#define BRIDGE_BUS_TIMEOUT	0x0000C4	/* Bus Timeout Register */
+#define BRIDGE_PCI_BUS_TIMEOUT	BRIDGE_BUS_TIMEOUT
+#define BRIDGE_PCI_CFG		0x0000CC	/* PCI Type 1 Config reg */
+#define BRIDGE_PCI_ERR_UPPER	0x0000D4	/* PCI error Upper Addr */
+#define BRIDGE_PCI_ERR_LOWER	0x0000DC	/* PCI error Lower Addr */
+
+#define BRIDGE_INT_STATUS	0x000104	/* Interrupt Status */
+#define BRIDGE_INT_ENABLE	0x00010C	/* Interrupt Enables */
+#define BRIDGE_INT_RST_STAT	0x000114	/* Reset Intr Status */
+#define BRIDGE_INT_MODE		0x00011C	/* Interrupt Mode */
+#define BRIDGE_INT_DEVICE	0x000124	/* Interrupt Device */
+#define BRIDGE_INT_HOST_ERR	0x00012C	/* Host Error Field */
+
+#define BRIDGE_INT_ADDR0	0x000134	/* Host Address Reg */
+#define BRIDGE_INT_ADDR_OFF	0x000008	/* Host Addr offset (1..7) */
+#define BRIDGE_INT_ADDR(x)	(BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
+
+#define BRIDGE_INT_VIEW		0x000174	/* Interrupt view */
+#define BRIDGE_MULTIPLE_INT	0x00017c	/* Multiple interrupt occured */
+
+#define BRIDGE_FORCE_ALWAYS0	0x000184	/* Force an interrupt (always)*/
+#define BRIDGE_FORCE_ALWAYS_OFF 0x000008	/* Force Always offset */
+#define BRIDGE_FORCE_ALWAYS(x)  (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF)
+
+#define BRIDGE_FORCE_PIN0	0x0001c4	/* Force an interrupt */
+#define BRIDGE_FORCE_PIN_OFF 	0x000008	/* Force Pin offset */
+#define BRIDGE_FORCE_PIN(x)  (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF)
+
+#define BRIDGE_DEVICE0		0x000204	/* Device 0 */
+#define BRIDGE_DEVICE_OFF	0x000008	/* Device offset (1..7) */
+#define BRIDGE_DEVICE(x)	(BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
+
+#define BRIDGE_WR_REQ_BUF0	0x000244	/* Write Request Buffer 0 */
+#define BRIDGE_WR_REQ_BUF_OFF	0x000008	/* Buffer Offset (1..7) */
+#define BRIDGE_WR_REQ_BUF(x)	(BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
+
+#define BRIDGE_EVEN_RESP	0x000284	/* Even Device Response Buf */
+#define BRIDGE_ODD_RESP		0x00028C	/* Odd Device Response Buf */
+
+#define BRIDGE_RESP_STATUS	0x000294	/* Read Response Status reg */
+#define BRIDGE_RESP_CLEAR	0x00029C	/* Read Response Clear reg */
+
+#define BRIDGE_BUF_ADDR_UPPER0	0x000304
+#define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010	/* PCI Buffer Upper Offset */
+#define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF)
+
+#define BRIDGE_BUF_ADDR_LOWER0	0x00030c
+#define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010	/* PCI Buffer Upper Offset */
+#define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF)
+
+/* 
+ * Performance Monitor Registers.
+ *
+ * The Performance registers are those registers which are associated with
+ * monitoring the performance of PCI generated reads to the host environ
+ * ment. Because of the size of the register file only the even registers
+ * were instrumented.
+ */
+
+#define BRIDGE_BUF_OFF 0x40
+#define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF))
+
+/*
+ * Buffer (x) Flush Count with Data Touch Register.
+ *
+ * This counter is incremented each time the corresponding response buffer
+ * is flushed after at least a single data element in the buffer is used.
+ * A word write to this address clears the count.
+ */
+
+#define BRIDGE_BUF_0_FLUSH_TOUCH  0x000404
+#define BRIDGE_BUF_2_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1)
+#define BRIDGE_BUF_4_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2)
+#define BRIDGE_BUF_6_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3)
+#define BRIDGE_BUF_8_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4)
+#define BRIDGE_BUF_10_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5)
+#define BRIDGE_BUF_12_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6)
+#define BRIDGE_BUF_14_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7)
+
+/*
+ * Buffer (x) Flush Count w/o Data Touch Register
+ *
+ * This counter is incremented each time the corresponding response buffer
+ * is flushed without any data element in the buffer being used. A word
+ * write to this address clears the count.
+ */
+
+
+#define BRIDGE_BUF_0_FLUSH_NOTOUCH  0x00040c
+#define BRIDGE_BUF_2_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1)
+#define BRIDGE_BUF_4_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2)
+#define BRIDGE_BUF_6_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3)
+#define BRIDGE_BUF_8_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4)
+#define BRIDGE_BUF_10_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5)
+#define BRIDGE_BUF_12_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6)
+#define BRIDGE_BUF_14_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7)
+
+/*
+ * Buffer (x) Request in Flight Count Register
+ *
+ * This counter is incremented on each bus clock while the request is in
+ * flight. A word write to this address clears the count.
+ */
+
+#define BRIDGE_BUF_0_INFLIGHT	 0x000414
+#define BRIDGE_BUF_2_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1)
+#define BRIDGE_BUF_4_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2)
+#define BRIDGE_BUF_6_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3)
+#define BRIDGE_BUF_8_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4)
+#define BRIDGE_BUF_10_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5)
+#define BRIDGE_BUF_12_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6)
+#define BRIDGE_BUF_14_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7)
+
+/*
+ * Buffer (x) Prefetch Request Count Register
+ *
+ * This counter is incremented each time the request using this buffer was
+ * generated from the prefetcher. A word write to this address clears the
+ * count.
+ */
+
+#define BRIDGE_BUF_0_PREFETCH	 0x00041C
+#define BRIDGE_BUF_2_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1)
+#define BRIDGE_BUF_4_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2)
+#define BRIDGE_BUF_6_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3)
+#define BRIDGE_BUF_8_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4)
+#define BRIDGE_BUF_10_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5)
+#define BRIDGE_BUF_12_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6)
+#define BRIDGE_BUF_14_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7)
+
+/*
+ * Buffer (x) Total PCI Retry Count Register
+ *
+ * This counter is incremented each time a PCI bus retry occurs and the ad
+ * dress matches the tag for the selected buffer. The buffer must also has
+ * this request in-flight. A word write to this address clears the count.
+ */
+
+#define BRIDGE_BUF_0_PCI_RETRY	 0x000424
+#define BRIDGE_BUF_2_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1)
+#define BRIDGE_BUF_4_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2)
+#define BRIDGE_BUF_6_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3)
+#define BRIDGE_BUF_8_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4)
+#define BRIDGE_BUF_10_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5)
+#define BRIDGE_BUF_12_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6)
+#define BRIDGE_BUF_14_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7)
+
+/*
+ * Buffer (x) Max PCI Retry Count Register
+ *
+ * This counter is contains the maximum retry count for a single request
+ * which was in-flight for this buffer. A word write to this address
+ * clears the count.
+ */
+
+#define BRIDGE_BUF_0_MAX_PCI_RETRY	 0x00042C
+#define BRIDGE_BUF_2_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1)
+#define BRIDGE_BUF_4_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2)
+#define BRIDGE_BUF_6_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3)
+#define BRIDGE_BUF_8_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4)
+#define BRIDGE_BUF_10_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5)
+#define BRIDGE_BUF_12_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6)
+#define BRIDGE_BUF_14_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7)
+
+/*
+ * Buffer (x) Max Latency Count Register
+ *
+ * This counter is contains the maximum count (in bus clocks) for a single
+ * request which was in-flight for this buffer. A word write to this
+ * address clears the count.
+ */
+
+#define BRIDGE_BUF_0_MAX_LATENCY	 0x000434
+#define BRIDGE_BUF_2_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1)
+#define BRIDGE_BUF_4_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2)
+#define BRIDGE_BUF_6_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3)
+#define BRIDGE_BUF_8_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4)
+#define BRIDGE_BUF_10_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5)
+#define BRIDGE_BUF_12_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6)
+#define BRIDGE_BUF_14_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7)
+
+/*
+ * Buffer (x) Clear All Register
+ *
+ * Any access to this register clears all the count values for the (x)
+ * registers.
+ */
+
+#define BRIDGE_BUF_0_CLEAR_ALL	 0x00043C
+#define BRIDGE_BUF_2_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1)
+#define BRIDGE_BUF_4_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2)
+#define BRIDGE_BUF_6_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3)
+#define BRIDGE_BUF_8_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4)
+#define BRIDGE_BUF_10_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5)
+#define BRIDGE_BUF_12_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6)
+#define BRIDGE_BUF_14_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7)
+
+/* end of Performance Monitor Registers */
+
+/* Byte offset macros for Bridge I/O space */
+
+#define BRIDGE_ATE_RAM		0x00010000	/* Internal Addr Xlat Ram */
+
+#define BRIDGE_TYPE0_CFG_DEV0	0x00020000	/* Type 0 Cfg, Device 0 */
+#define BRIDGE_TYPE0_CFG_SLOT_OFF	0x00001000	/* Type 0 Cfg Slot Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_FUNC_OFF	0x00000100	/* Type 0 Cfg Func Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_DEV(s)		(BRIDGE_TYPE0_CFG_DEV0+\
+					 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
+#define BRIDGE_TYPE0_CFG_DEVF(s,f)	(BRIDGE_TYPE0_CFG_DEV0+\
+					 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
+					 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
+
+#define BRIDGE_TYPE1_CFG	0x00028000	/* Type 1 Cfg space */
+
+#define BRIDGE_PCI_IACK		0x00030000	/* PCI Interrupt Ack */
+#define BRIDGE_EXT_SSRAM	0x00080000	/* Extern SSRAM (ATE) */
+
+/* Byte offset macros for Bridge device IO spaces */
+
+#define BRIDGE_DEV_CNT		8	/* Up to 8 devices per bridge */
+#define BRIDGE_DEVIO0		0x00200000	/* Device IO 0 Addr */
+#define BRIDGE_DEVIO1		0x00400000	/* Device IO 1 Addr */
+#define BRIDGE_DEVIO2		0x00600000	/* Device IO 2 Addr */
+#define BRIDGE_DEVIO_OFF	0x00100000	/* Device IO Offset (3..7) */
+
+#define BRIDGE_DEVIO_2MB	0x00200000	/* Device IO Offset (0..1) */
+#define BRIDGE_DEVIO_1MB	0x00100000	/* Device IO Offset (2..7) */
+
+#if	LANGUAGE_C
+
+#define BRIDGE_DEVIO(x)		((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
+#endif				/* LANGUAGE_C */
+
+#define BRIDGE_EXTERNAL_FLASH	0x00C00000	/* External Flash PROMS */
+
+/* ========================================================================
+ *    Bridge register bit field definitions
+ */
+
+/* Widget part number of bridge */
+#define BRIDGE_WIDGET_PART_NUM		0xc002
+#define XBRIDGE_WIDGET_PART_NUM		0xd002
+
+/* Manufacturer of bridge */
+#define BRIDGE_WIDGET_MFGR_NUM		0x036
+#define XBRIDGE_WIDGET_MFGR_NUM		0x024
+
+/* Revision numbers for known [X]Bridge revisions */
+#define BRIDGE_REV_A			0x1
+#define BRIDGE_REV_B			0x2
+#define BRIDGE_REV_C			0x3
+#define	BRIDGE_REV_D			0x4
+#define XBRIDGE_REV_A			0x1
+#define XBRIDGE_REV_B			0x2
+
+/* Part + Rev numbers allows distinction and acscending sequence */
+#define BRIDGE_PART_REV_A	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A)
+#define BRIDGE_PART_REV_B	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B)
+#define BRIDGE_PART_REV_C	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C)
+#define	BRIDGE_PART_REV_D	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D)
+#define XBRIDGE_PART_REV_A	(XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A)
+#define XBRIDGE_PART_REV_B	(XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B)
+
+/* Bridge widget status register bits definition */
+
+#define BRIDGE_STAT_LLP_REC_CNT		(0xFFu << 24)
+#define BRIDGE_STAT_LLP_TX_CNT		(0xFF << 16)
+#define BRIDGE_STAT_FLASH_SELECT	(0x1 << 6)
+#define BRIDGE_STAT_PCI_GIO_N		(0x1 << 5)
+#define BRIDGE_STAT_PENDING		(0x1F << 0)
+
+/* Bridge widget control register bits definition */
+#define BRIDGE_CTRL_FLASH_WR_EN		(0x1ul << 31)
+#define BRIDGE_CTRL_EN_CLK50		(0x1 << 30)
+#define BRIDGE_CTRL_EN_CLK40		(0x1 << 29)
+#define BRIDGE_CTRL_EN_CLK33		(0x1 << 28)
+#define BRIDGE_CTRL_RST(n)		((n) << 24)
+#define BRIDGE_CTRL_RST_MASK		(BRIDGE_CTRL_RST(0xF))
+#define BRIDGE_CTRL_RST_PIN(x)		(BRIDGE_CTRL_RST(0x1 << (x)))
+#define BRIDGE_CTRL_IO_SWAP		(0x1 << 23)
+#define BRIDGE_CTRL_MEM_SWAP		(0x1 << 22)
+#define BRIDGE_CTRL_PAGE_SIZE		(0x1 << 21)
+#define BRIDGE_CTRL_SS_PAR_BAD		(0x1 << 20)
+#define BRIDGE_CTRL_SS_PAR_EN		(0x1 << 19)
+#define BRIDGE_CTRL_SSRAM_SIZE(n)	((n) << 17)
+#define BRIDGE_CTRL_SSRAM_SIZE_MASK	(BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_512K		(BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_128K		(BRIDGE_CTRL_SSRAM_SIZE(0x2))
+#define BRIDGE_CTRL_SSRAM_64K		(BRIDGE_CTRL_SSRAM_SIZE(0x1))
+#define BRIDGE_CTRL_SSRAM_1K		(BRIDGE_CTRL_SSRAM_SIZE(0x0))
+#define BRIDGE_CTRL_F_BAD_PKT		(0x1 << 16)
+#define BRIDGE_CTRL_LLP_XBAR_CRD(n)	((n) << 12)
+#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK	(BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
+#define BRIDGE_CTRL_CLR_RLLP_CNT	(0x1 << 11)
+#define BRIDGE_CTRL_CLR_TLLP_CNT	(0x1 << 10)
+#define BRIDGE_CTRL_SYS_END		(0x1 << 9)
+#define BRIDGE_CTRL_MAX_TRANS(n)	((n) << 4)
+#define BRIDGE_CTRL_MAX_TRANS_MASK	(BRIDGE_CTRL_MAX_TRANS(0x1f))
+#define BRIDGE_CTRL_WIDGET_ID(n)	((n) << 0)
+#define BRIDGE_CTRL_WIDGET_ID_MASK	(BRIDGE_CTRL_WIDGET_ID(0xf))
+
+/* Bridge Response buffer Error Upper Register bit fields definition */
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+#define BRIDGE_RESP_ERRRUPPR_BUFMASK	(0xFFFF)
+
+#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)	\
+			(((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
+				BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+
+#define BRIDGE_RESP_ERRUPPR_DEVICE(x)	\
+			(((x) &	 BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
+				 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+
+/* Bridge direct mapping register bits definition */
+#define BRIDGE_DIRMAP_W_ID_SHFT		20
+#define BRIDGE_DIRMAP_W_ID		(0xf << BRIDGE_DIRMAP_W_ID_SHFT)
+#define BRIDGE_DIRMAP_RMF_64		(0x1 << 18)
+#define BRIDGE_DIRMAP_ADD512		(0x1 << 17)
+#define BRIDGE_DIRMAP_OFF		(0x1ffff << 0)
+#define BRIDGE_DIRMAP_OFF_ADDRSHFT	(31)	/* lsbit of DIRMAP_OFF is xtalk address bit 31 */
+
+/* Bridge Arbitration register bits definition */
+#define BRIDGE_ARB_REQ_WAIT_TICK(x)	((x) << 16)
+#define BRIDGE_ARB_REQ_WAIT_TICK_MASK	BRIDGE_ARB_REQ_WAIT_TICK(0x3)
+#define BRIDGE_ARB_REQ_WAIT_EN(x)	((x) << 8)
+#define BRIDGE_ARB_REQ_WAIT_EN_MASK	BRIDGE_ARB_REQ_WAIT_EN(0xff)
+#define BRIDGE_ARB_FREEZE_GNT		(1 << 6)
+#define BRIDGE_ARB_HPRI_RING_B2		(1 << 5)
+#define BRIDGE_ARB_HPRI_RING_B1		(1 << 4)
+#define BRIDGE_ARB_HPRI_RING_B0		(1 << 3)
+#define BRIDGE_ARB_LPRI_RING_B2		(1 << 2)
+#define BRIDGE_ARB_LPRI_RING_B1		(1 << 1)
+#define BRIDGE_ARB_LPRI_RING_B0		(1 << 0)
+
+/* Bridge Bus time-out register bits definition */
+#define BRIDGE_BUS_PCI_RETRY_HLD(x)	((x) << 16)
+#define BRIDGE_BUS_PCI_RETRY_HLD_MASK	BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
+#define BRIDGE_BUS_GIO_TIMEOUT		(1 << 12)
+#define BRIDGE_BUS_PCI_RETRY_CNT(x)	((x) << 0)
+#define BRIDGE_BUS_PCI_RETRY_MASK	BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
+
+/* Bridge interrupt status register bits definition */
+#define BRIDGE_ISR_MULTI_ERR		(0x1u << 31)	/* bridge only */
+#define BRIDGE_ISR_PMU_ESIZE_FAULT	(0x1 << 30)	/* bridge only */
+#define BRIDGE_ISR_PAGE_FAULT		(0x1 << 30)	/* xbridge only */
+#define BRIDGE_ISR_UNEXP_RESP		(0x1 << 29)
+#define BRIDGE_ISR_BAD_XRESP_PKT	(0x1 << 28)
+#define BRIDGE_ISR_BAD_XREQ_PKT		(0x1 << 27)
+#define BRIDGE_ISR_RESP_XTLK_ERR	(0x1 << 26)
+#define BRIDGE_ISR_REQ_XTLK_ERR		(0x1 << 25)
+#define BRIDGE_ISR_INVLD_ADDR		(0x1 << 24)
+#define BRIDGE_ISR_UNSUPPORTED_XOP	(0x1 << 23)
+#define BRIDGE_ISR_XREQ_FIFO_OFLOW	(0x1 << 22)
+#define BRIDGE_ISR_LLP_REC_SNERR	(0x1 << 21)
+#define BRIDGE_ISR_LLP_REC_CBERR	(0x1 << 20)
+#define BRIDGE_ISR_LLP_RCTY		(0x1 << 19)
+#define BRIDGE_ISR_LLP_TX_RETRY		(0x1 << 18)
+#define BRIDGE_ISR_LLP_TCTY		(0x1 << 17)
+#define BRIDGE_ISR_SSRAM_PERR		(0x1 << 16)
+#define BRIDGE_ISR_PCI_ABORT		(0x1 << 15)
+#define BRIDGE_ISR_PCI_PARITY		(0x1 << 14)
+#define BRIDGE_ISR_PCI_SERR		(0x1 << 13)
+#define BRIDGE_ISR_PCI_PERR		(0x1 << 12)
+#define BRIDGE_ISR_PCI_MST_TIMEOUT	(0x1 << 11)
+#define BRIDGE_ISR_GIO_MST_TIMEOUT	BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_ISR_PCI_RETRY_CNT	(0x1 << 10)
+#define BRIDGE_ISR_XREAD_REQ_TIMEOUT	(0x1 << 9)
+#define BRIDGE_ISR_GIO_B_ENBL_ERR	(0x1 << 8)
+#define BRIDGE_ISR_INT_MSK		(0xff << 0)
+#define BRIDGE_ISR_INT(x)		(0x1 << (x))
+
+#define BRIDGE_ISR_LINK_ERROR		\
+		(BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|	\
+		 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|		\
+		 BRIDGE_ISR_LLP_TCTY)
+
+#define BRIDGE_ISR_PCIBUS_PIOERR	\
+		(BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
+
+#define BRIDGE_ISR_PCIBUS_ERROR		\
+		(BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|		\
+		 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|		\
+		 BRIDGE_ISR_PCI_PARITY)
+
+#define BRIDGE_ISR_XTALK_ERROR		\
+		(BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
+		 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|	\
+		 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|	\
+		 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|	\
+		 BRIDGE_ISR_UNEXP_RESP)
+
+#define BRIDGE_ISR_ERRORS		\
+		(BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|		\
+		 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|		\
+		 BRIDGE_ISR_PMU_ESIZE_FAULT)
+
+/*
+ * List of Errors which are fatal and kill the sytem
+ */
+#define BRIDGE_ISR_ERROR_FATAL		\
+		((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
+		 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
+
+#define BRIDGE_ISR_ERROR_DUMP		\
+		(BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|	\
+		 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
+
+/* Bridge interrupt enable register bits definition */
+#define BRIDGE_IMR_UNEXP_RESP		BRIDGE_ISR_UNEXP_RESP
+#define BRIDGE_IMR_PMU_ESIZE_FAULT	BRIDGE_ISR_PMU_ESIZE_FAULT
+#define BRIDGE_IMR_BAD_XRESP_PKT	BRIDGE_ISR_BAD_XRESP_PKT
+#define BRIDGE_IMR_BAD_XREQ_PKT		BRIDGE_ISR_BAD_XREQ_PKT
+#define BRIDGE_IMR_RESP_XTLK_ERR	BRIDGE_ISR_RESP_XTLK_ERR
+#define BRIDGE_IMR_REQ_XTLK_ERR		BRIDGE_ISR_REQ_XTLK_ERR
+#define BRIDGE_IMR_INVLD_ADDR		BRIDGE_ISR_INVLD_ADDR
+#define BRIDGE_IMR_UNSUPPORTED_XOP	BRIDGE_ISR_UNSUPPORTED_XOP
+#define BRIDGE_IMR_XREQ_FIFO_OFLOW	BRIDGE_ISR_XREQ_FIFO_OFLOW
+#define BRIDGE_IMR_LLP_REC_SNERR	BRIDGE_ISR_LLP_REC_SNERR
+#define BRIDGE_IMR_LLP_REC_CBERR	BRIDGE_ISR_LLP_REC_CBERR
+#define BRIDGE_IMR_LLP_RCTY		BRIDGE_ISR_LLP_RCTY
+#define BRIDGE_IMR_LLP_TX_RETRY		BRIDGE_ISR_LLP_TX_RETRY
+#define BRIDGE_IMR_LLP_TCTY		BRIDGE_ISR_LLP_TCTY
+#define BRIDGE_IMR_SSRAM_PERR		BRIDGE_ISR_SSRAM_PERR
+#define BRIDGE_IMR_PCI_ABORT		BRIDGE_ISR_PCI_ABORT
+#define BRIDGE_IMR_PCI_PARITY		BRIDGE_ISR_PCI_PARITY
+#define BRIDGE_IMR_PCI_SERR		BRIDGE_ISR_PCI_SERR
+#define BRIDGE_IMR_PCI_PERR		BRIDGE_ISR_PCI_PERR
+#define BRIDGE_IMR_PCI_MST_TIMEOUT	BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_IMR_GIO_MST_TIMEOUT	BRIDGE_ISR_GIO_MST_TIMEOUT
+#define BRIDGE_IMR_PCI_RETRY_CNT	BRIDGE_ISR_PCI_RETRY_CNT
+#define BRIDGE_IMR_XREAD_REQ_TIMEOUT	BRIDGE_ISR_XREAD_REQ_TIMEOUT
+#define BRIDGE_IMR_GIO_B_ENBL_ERR	BRIDGE_ISR_GIO_B_ENBL_ERR
+#define BRIDGE_IMR_INT_MSK		BRIDGE_ISR_INT_MSK
+#define BRIDGE_IMR_INT(x)		BRIDGE_ISR_INT(x)
+
+/* Bridge interrupt reset register bits definition */
+#define BRIDGE_IRR_MULTI_CLR		(0x1 << 6)
+#define BRIDGE_IRR_CRP_GRP_CLR		(0x1 << 5)
+#define BRIDGE_IRR_RESP_BUF_GRP_CLR	(0x1 << 4)
+#define BRIDGE_IRR_REQ_DSP_GRP_CLR	(0x1 << 3)
+#define BRIDGE_IRR_LLP_GRP_CLR		(0x1 << 2)
+#define BRIDGE_IRR_SSRAM_GRP_CLR	(0x1 << 1)
+#define BRIDGE_IRR_PCI_GRP_CLR		(0x1 << 0)
+#define BRIDGE_IRR_GIO_GRP_CLR		(0x1 << 0)
+#define BRIDGE_IRR_ALL_CLR		0x7f
+
+#define BRIDGE_IRR_CRP_GRP		(BRIDGE_ISR_UNEXP_RESP | \
+					 BRIDGE_ISR_XREQ_FIFO_OFLOW)
+#define BRIDGE_IRR_RESP_BUF_GRP		(BRIDGE_ISR_BAD_XRESP_PKT | \
+					 BRIDGE_ISR_RESP_XTLK_ERR | \
+					 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+#define BRIDGE_IRR_REQ_DSP_GRP		(BRIDGE_ISR_UNSUPPORTED_XOP | \
+					 BRIDGE_ISR_BAD_XREQ_PKT | \
+					 BRIDGE_ISR_REQ_XTLK_ERR | \
+					 BRIDGE_ISR_INVLD_ADDR)
+#define BRIDGE_IRR_LLP_GRP		(BRIDGE_ISR_LLP_REC_SNERR | \
+					 BRIDGE_ISR_LLP_REC_CBERR | \
+					 BRIDGE_ISR_LLP_RCTY | \
+					 BRIDGE_ISR_LLP_TX_RETRY | \
+					 BRIDGE_ISR_LLP_TCTY)
+#define BRIDGE_IRR_SSRAM_GRP		(BRIDGE_ISR_SSRAM_PERR | \
+					 BRIDGE_ISR_PMU_ESIZE_FAULT)
+#define BRIDGE_IRR_PCI_GRP		(BRIDGE_ISR_PCI_ABORT | \
+					 BRIDGE_ISR_PCI_PARITY | \
+					 BRIDGE_ISR_PCI_SERR | \
+					 BRIDGE_ISR_PCI_PERR | \
+					 BRIDGE_ISR_PCI_MST_TIMEOUT | \
+					 BRIDGE_ISR_PCI_RETRY_CNT)
+
+#define BRIDGE_IRR_GIO_GRP		(BRIDGE_ISR_GIO_B_ENBL_ERR | \
+					 BRIDGE_ISR_GIO_MST_TIMEOUT)
+
+/* Bridge INT_DEV register bits definition */
+#define BRIDGE_INT_DEV_SHFT(n)		((n)*3)
+#define BRIDGE_INT_DEV_MASK(n)		(0x7 << BRIDGE_INT_DEV_SHFT(n))
+#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))	
+
+/* Bridge interrupt(x) register bits definition */
+#define BRIDGE_INT_ADDR_HOST		0x0003FF00
+#define BRIDGE_INT_ADDR_FLD		0x000000FF
+
+#define BRIDGE_TMO_PCI_RETRY_HLD_MASK	0x1f0000
+#define BRIDGE_TMO_GIO_TIMEOUT_MASK	0x001000
+#define BRIDGE_TMO_PCI_RETRY_CNT_MASK	0x0003ff
+
+#define BRIDGE_TMO_PCI_RETRY_CNT_MAX	0x3ff
+
+#ifdef SN0
+/*
+ * The NASID should be shifted by this amount and stored into the
+ * interrupt(x) register.
+ */
+#define BRIDGE_INT_ADDR_NASID_SHFT	8
+
+/*
+ * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
+ * memory.
+ */
+#define BRIDGE_INT_ADDR_DEST_IO		(1 << 17)
+#define BRIDGE_INT_ADDR_DEST_MEM	0
+#define BRIDGE_INT_ADDR_MASK		(1 << 17)
+#endif
+
+/* Bridge device(x) register bits definition */
+#define BRIDGE_DEV_ERR_LOCK_EN		(1ull << 28)
+#define BRIDGE_DEV_PAGE_CHK_DIS		(1ull << 27)
+#define BRIDGE_DEV_FORCE_PCI_PAR	(1ull << 26)
+#define BRIDGE_DEV_VIRTUAL_EN		(1ull << 25)
+#define BRIDGE_DEV_PMU_WRGA_EN		(1ull << 24)
+#define BRIDGE_DEV_DIR_WRGA_EN		(1ull << 23)
+#define BRIDGE_DEV_DEV_SIZE		(1ull << 22)
+#define BRIDGE_DEV_RT			(1ull << 21)
+#define BRIDGE_DEV_SWAP_PMU		(1ull << 20)
+#define BRIDGE_DEV_SWAP_DIR		(1ull << 19)
+#define BRIDGE_DEV_PREF			(1ull << 18)
+#define BRIDGE_DEV_PRECISE		(1ull << 17)
+#define BRIDGE_DEV_COH			(1ull << 16)
+#define BRIDGE_DEV_BARRIER		(1ull << 15)
+#define BRIDGE_DEV_GBR			(1ull << 14)
+#define BRIDGE_DEV_DEV_SWAP		(1ull << 13)
+#define BRIDGE_DEV_DEV_IO_MEM		(1ull << 12)
+#define BRIDGE_DEV_OFF_MASK		0x00000fff
+#define BRIDGE_DEV_OFF_ADDR_SHFT	20
+
+#define XBRIDGE_DEV_PMU_BITS		BRIDGE_DEV_PMU_WRGA_EN
+#define BRIDGE_DEV_PMU_BITS		(BRIDGE_DEV_PMU_WRGA_EN		| \
+					 BRIDGE_DEV_SWAP_PMU)
+#define BRIDGE_DEV_D32_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
+					 BRIDGE_DEV_SWAP_DIR		| \
+					 BRIDGE_DEV_PREF		| \
+					 BRIDGE_DEV_PRECISE		| \
+					 BRIDGE_DEV_COH			| \
+					 BRIDGE_DEV_BARRIER)
+#define XBRIDGE_DEV_D64_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
+					 BRIDGE_DEV_COH			| \
+					 BRIDGE_DEV_BARRIER)
+#define BRIDGE_DEV_D64_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
+					 BRIDGE_DEV_SWAP_DIR		| \
+					 BRIDGE_DEV_COH			| \
+					 BRIDGE_DEV_BARRIER)
+
+/* Bridge Error Upper register bit field definition */
+#define BRIDGE_ERRUPPR_DEVMASTER	(0x1 << 20)	/* Device was master */
+#define BRIDGE_ERRUPPR_PCIVDEV		(0x1 << 19)	/* Virtual Req value */
+#define BRIDGE_ERRUPPR_DEVNUM_SHFT	(16)
+#define BRIDGE_ERRUPPR_DEVNUM_MASK	(0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_ERRUPPR_DEVICE(err)	(((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
+#define BRIDGE_ERRUPPR_ADDRMASK		(0xFFFF)
+
+/* Bridge interrupt mode register bits definition */
+#define BRIDGE_INTMODE_CLR_PKT_EN(x)	(0x1 << (x))
+
+/* this should be written to the xbow's link_control(x) register */
+#define BRIDGE_CREDIT	3
+
+/* RRB assignment register */
+#define	BRIDGE_RRB_EN	0x8	/* after shifting down */
+#define	BRIDGE_RRB_DEV	0x7	/* after shifting down */
+#define	BRIDGE_RRB_VDEV	0x4	/* after shifting down */
+#define	BRIDGE_RRB_PDEV	0x3	/* after shifting down */
+
+/* RRB status register */
+#define	BRIDGE_RRB_VALID(r)	(0x00010000<<(r))
+#define	BRIDGE_RRB_INUSE(r)	(0x00000001<<(r))
+
+/* RRB clear register */
+#define	BRIDGE_RRB_CLEAR(r)	(0x00000001<<(r))
+
+/* xbox system controller declarations */
+#define XBOX_BRIDGE_WID         8
+#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
+#define XBOX_RPS_EXISTS		1 << 6	 /* RPS bit in status register */
+#define XBOX_RPS_FAIL		1 << 4	 /* RPS status bit in register */
+
+/* ========================================================================
+ */
+/*
+ * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
+ * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
+ */
+/* XTALK addresses that map into Bridge Bus addr space */
+#define BRIDGE_PIO32_XTALK_ALIAS_BASE	0x000040000000L
+#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT	0x00007FFFFFFFL
+#define BRIDGE_PIO64_XTALK_ALIAS_BASE	0x000080000000L
+#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT	0x0000BFFFFFFFL
+#define BRIDGE_PCIIO_XTALK_ALIAS_BASE	0x000100000000L
+#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT	0x0001FFFFFFFFL
+
+/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
+#define BRIDGE_MIN_PIO_ADDR_MEM		0x00000000	/* 1G PCI memory space */
+#define BRIDGE_MAX_PIO_ADDR_MEM		0x3fffffff
+#define BRIDGE_MIN_PIO_ADDR_IO		0x00000000	/* 4G PCI IO space */
+#define BRIDGE_MAX_PIO_ADDR_IO		0xffffffff
+
+/* XTALK addresses that map into PCI addresses */
+#define BRIDGE_PCI_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_MEM64_BASE		BRIDGE_PIO64_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM64_LIMIT		BRIDGE_PIO64_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_IO_BASE		BRIDGE_PCIIO_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_IO_LIMIT		BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
+
+/*
+ * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
+ */
+/* Bridge Bus DMA addresses */
+#define BRIDGE_LOCAL_BASE		0
+#define BRIDGE_DMA_MAPPED_BASE		0x40000000
+#define BRIDGE_DMA_MAPPED_SIZE		0x40000000	/* 1G Bytes */
+#define BRIDGE_DMA_DIRECT_BASE		0x80000000
+#define BRIDGE_DMA_DIRECT_SIZE		0x80000000	/* 2G Bytes */
+
+#define PCI32_LOCAL_BASE		BRIDGE_LOCAL_BASE
+
+/* PCI addresses of regions decoded by Bridge for DMA */
+#define PCI32_MAPPED_BASE		BRIDGE_DMA_MAPPED_BASE
+#define PCI32_DIRECT_BASE		BRIDGE_DMA_DIRECT_BASE
+
+#if	LANGUAGE_C
+
+#define IS_PCI32_LOCAL(x)	((uint64_t)(x) < PCI32_MAPPED_BASE)
+#define IS_PCI32_MAPPED(x)	((uint64_t)(x) < PCI32_DIRECT_BASE && \
+					(uint64_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)	((uint64_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI64(x)		((uint64_t)(x) >= PCI64_BASE)
+#endif				/* LANGUAGE_C */
+
+/*
+ * The GIO address space.
+ */
+/* Xtalk to GIO PIO */
+#define BRIDGE_GIO_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_GIO_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+
+#define GIO_LOCAL_BASE			BRIDGE_LOCAL_BASE
+
+/* GIO addresses of regions decoded by Bridge for DMA */
+#define GIO_MAPPED_BASE			BRIDGE_DMA_MAPPED_BASE
+#define GIO_DIRECT_BASE			BRIDGE_DMA_DIRECT_BASE
+
+#if	LANGUAGE_C
+
+#define IS_GIO_LOCAL(x)		((uint64_t)(x) < GIO_MAPPED_BASE)
+#define IS_GIO_MAPPED(x)	((uint64_t)(x) < GIO_DIRECT_BASE && \
+					(uint64_t)(x) >= GIO_MAPPED_BASE)
+#define IS_GIO_DIRECT(x)	((uint64_t)(x) >= GIO_MAPPED_BASE)
+#endif				/* LANGUAGE_C */
+
+/* PCI to xtalk mapping */
+
+/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
+ * which xtalk address is accessed
+ */
+#define BRIDGE_DIRECT_32_SEG_SIZE	BRIDGE_DMA_DIRECT_SIZE
+#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)		\
+	((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +	\
+		((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
+
+/* 64-bit address attribute masks */
+#define PCI64_ATTR_TARG_MASK	0xf000000000000000
+#define PCI64_ATTR_TARG_SHFT	60
+#define PCI64_ATTR_PREF		(1ull << 59)
+#define PCI64_ATTR_PREC		(1ull << 58)
+#define PCI64_ATTR_VIRTUAL	(1ull << 57)
+#define PCI64_ATTR_BAR		(1ull << 56)
+#define PCI64_ATTR_SWAP		(1ull << 55)
+#define PCI64_ATTR_RMF_MASK	0x00ff000000000000
+#define PCI64_ATTR_RMF_SHFT	48
+
+#if LANGUAGE_C
+/* Address translation entry for mapped pci32 accesses */
+typedef union ate_u {
+    uint64_t		    ent;
+    struct xb_ate_s {					/* xbridge */
+	uint64_t		:16;
+	uint64_t		addr:36;
+	uint64_t		targ:4;
+	uint64_t		reserved:2;
+        uint64_t		swap:1;
+	uint64_t		barrier:1;
+	uint64_t		prefetch:1;
+	uint64_t		precise:1;
+	uint64_t		coherent:1;
+	uint64_t		valid:1;
+    } xb_field;
+    struct ate_s {					/* bridge */
+	uint64_t		rmf:16;
+	uint64_t		addr:36;
+	uint64_t		targ:4;
+	uint64_t		reserved:3;
+	uint64_t		barrier:1;
+	uint64_t		prefetch:1;
+	uint64_t		precise:1;
+	uint64_t		coherent:1;
+	uint64_t		valid:1;
+    } field;
+} ate_t;
+#endif				/* LANGUAGE_C */
+
+#define ATE_V		(1 << 0)
+#define ATE_CO		(1 << 1)
+#define ATE_PREC	(1 << 2)
+#define ATE_PREF	(1 << 3)
+#define ATE_BAR		(1 << 4)
+#define ATE_SWAP        (1 << 5)
+
+#define ATE_PFNSHIFT		12
+#define ATE_TIDSHIFT		8
+#define ATE_RMFSHIFT		48
+
+#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
+				((xid)<<ATE_TIDSHIFT) | \
+				(attr)
+
+/*
+ * for xbridge, bit 29 of the pci address is the swap bit */
+#define ATE_SWAPSHIFT		29
+#define ATE_SWAP_ON(x)		((x) |= (1 << ATE_SWAPSHIFT))
+#define ATE_SWAP_OFF(x)		((x) &= ~(1 << ATE_SWAPSHIFT))
+
+#define is_xbridge(bridge) \
+        (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM)
+
+#if	LANGUAGE_C
+
+/* ========================================================================
+ */
+
+#ifdef	MACROFIELD_LINE
+/*
+ * This table forms a relation between the byte offset macros normally
+ * used for ASM coding and the calculated byte offsets of the fields
+ * in the C structure.
+ *
+ * See bridge_check.c and bridge_html.c for further details.
+ */
+#ifndef MACROFIELD_LINE_BITFIELD
+#define MACROFIELD_LINE_BITFIELD(m)	/* ignored */
+#endif
+
+struct macrofield_s	bridge_macrofield[] =
+{
+
+    MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id)
+    MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM)
+    MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM)
+    MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM)
+    MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING)
+    MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper)
+    MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower)
+    MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK)
+    MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout)
+    MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper)
+    MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR)
+    MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID)
+    MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR)
+    MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower)
+    MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword)
+    MACROFIELD_LINE_BITFIELD(WIDGET_DIDN)
+    MACROFIELD_LINE_BITFIELD(WIDGET_SIDN)
+    MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP)
+    MACROFIELD_LINE_BITFIELD(WIDGET_TNUM)
+    MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT)
+    MACROFIELD_LINE_BITFIELD(WIDGET_DS)
+    MACROFIELD_LINE_BITFIELD(WIDGET_GBR)
+    MACROFIELD_LINE_BITFIELD(WIDGET_VBPM)
+    MACROFIELD_LINE_BITFIELD(WIDGET_ERROR)
+    MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER)
+    MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp)
+    MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY)
+    MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT)
+    MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST)
+    MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush)
+    MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err)
+    MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper)
+    MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower)
+    MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl)
+    MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF)
+    MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr)
+    MACROFIELD_LINE(BRIDGE_ARB, b_arb)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0)
+    MACROFIELD_LINE(BRIDGE_NIC, b_nic)
+    MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout)
+    MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg)
+    MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper)
+    MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower)
+    MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK)
+    MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK)
+    MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR)
+    MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0))
+    MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1))
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0))
+    MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr)
+    MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr)
+    MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM)
+    MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK)
+    MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg)
+    MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg)
+    MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg)
+    MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp)
+    MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp)
+    MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status)
+    MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear)
+    MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram)
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0])
+
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6])
+    MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7])
+
+    MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg)
+    MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack)
+    MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram)
+    MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0))
+    MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0))
+    MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1))
+    MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2))
+    MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3))
+    MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4))
+    MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5))
+    MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6))
+    MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7))
+    MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash)
+};
+#endif
+
+#ifdef __cplusplus
+};
+#endif
+#endif				/* C or C++ */ 
+
+#endif                          /* _ASM_SN_PCI_BRIDGE_H */
diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h
new file mode 100644
index 000000000..fa5722450
--- /dev/null
+++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h
@@ -0,0 +1,29 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_CVLINK_H
+#define _ASM_SN_PCI_CVLINK_H
+
+#define SET_PCIA64(dev) \
+	(((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1
+#define IS_PCIA64(dev)	(((dev)->dma_mask == 0xffffffffffffffffUL) || \
+		(((struct sn1_device_sysdata *)((dev)->sysdata))->isa64))
+#define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
+#define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
+
+struct sn1_widget_sysdata {
+        devfs_handle_t  vhdl;
+};
+
+struct sn1_device_sysdata {
+        devfs_handle_t  vhdl;
+	int		isa64;
+};
+
+#endif				/* _ASM_SN_PCI_CVLINK_H */
diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h
new file mode 100644
index 000000000..d12ad0d58
--- /dev/null
+++ b/include/asm-ia64/sn/pci/pci_defs.h
@@ -0,0 +1,244 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_PCI_DEFS_H
+#define _ASM_SN_PCI_PCI_DEFS_H
+
+#include <linux/config.h>
+
+/* defines for the PCI bus architecture */
+
+/* Bit layout of address fields for Type-1
+ * Configuration Space cycles.
+ */
+#define	PCI_TYPE0_SLOT_MASK	0xFFFFF800
+#define	PCI_TYPE0_FUNC_MASK	0x00000700
+#define	PCI_TYPE0_REG_MASK	0x000000FF
+
+#define	PCI_TYPE0_SLOT_SHFT	11
+#define	PCI_TYPE0_FUNC_SHFT	8
+#define	PCI_TYPE0_REG_SHFT	0
+
+#define	PCI_TYPE0_FUNC(a)	(((a) & PCI_TYPE0_FUNC_MASK) >> PCI_TYPE0_FUNC_SHFT)
+#define	PCI_TYPE0_REG(a)	(((a) & PCI_TYPE0_REG_MASK) >> PCI_TYPE0_REG_SHFT)
+
+#define	PCI_TYPE0(s,f,r)	((((1<<(s)) << PCI_TYPE0_SLOT_SHFT) & PCI_TYPE0_SLOT_MASK) |\
+				 (((f) << PCI_TYPE0_FUNC_SHFT) & PCI_TYPE0_FUNC_MASK) |\
+				 (((r) << PCI_TYPE0_REG_SHFT) & PCI_TYPE0_REG_MASK))
+
+/* Bit layout of address fields for Type-1
+ * Configuration Space cycles.
+ * NOTE: I'm including the byte offset within
+ * the 32-bit word as part of the register
+ * number as an extension of the layout in
+ * the PCI spec.
+ */
+#define	PCI_TYPE1_BUS_MASK	0x00FF0000
+#define	PCI_TYPE1_SLOT_MASK	0x0000F100
+#define	PCI_TYPE1_FUNC_MASK	0x00000700
+#define	PCI_TYPE1_REG_MASK	0x000000FF
+
+#define	PCI_TYPE1_BUS_SHFT	16
+#define	PCI_TYPE1_SLOT_SHFT	11
+#define	PCI_TYPE1_FUNC_SHFT	8
+#define	PCI_TYPE1_REG_SHFT	0
+
+#define	PCI_TYPE1_BUS(a)	(((a) & PCI_TYPE1_BUS_MASK) >> PCI_TYPE1_BUS_SHFT)
+#define	PCI_TYPE1_SLOT(a)	(((a) & PCI_TYPE1_SLOT_MASK) >> PCI_TYPE1_SLOT_SHFT)
+#define	PCI_TYPE1_FUNC(a)	(((a) & PCI_TYPE1_FUNC_MASK) >> PCI_TYPE1_FUNC_SHFT)
+#define	PCI_TYPE1_REG(a)	(((a) & PCI_TYPE1_REG_MASK) >> PCI_TYPE1_REG_SHFT)
+
+#define	PCI_TYPE1(b,s,f,r)	((((b) << PCI_TYPE1_BUS_SHFT) & PCI_TYPE1_BUS_MASK) |\
+				 (((s) << PCI_TYPE1_SLOT_SHFT) & PCI_TYPE1_SLOT_MASK) |\
+				 (((f) << PCI_TYPE1_FUNC_SHFT) & PCI_TYPE1_FUNC_MASK) |\
+				 (((r) << PCI_TYPE1_REG_SHFT) & PCI_TYPE1_REG_MASK))
+
+/* Byte offsets of registers in CFG space
+ */
+#define	PCI_CFG_VENDOR_ID	0x00		/* Vendor ID (2 bytes) */
+#define	PCI_CFG_DEVICE_ID	0x02		/* Device ID (2 bytes) */
+
+#define	PCI_CFG_COMMAND		0x04		/* Command (2 bytes) */
+#define	PCI_CFG_STATUS		0x06		/* Status (2 bytes) */
+
+/* NOTE: if you are using a C "switch" statement to
+ * differentiate between the Config space registers, be
+ * aware that PCI_CFG_CLASS_CODE and PCI_CFG_BASE_CLASS
+ * are the same offset.
+ */
+#define	PCI_CFG_REV_ID		0x08		/* Revision Id (1 byte) */
+#define	PCI_CFG_CLASS_CODE	0x09		/* Class Code (3 bytes) */
+#define	PCI_CFG_BASE_CLASS	0x09		/* Base Class (1 byte) */
+#define	PCI_CFG_SUB_CLASS	0x0A		/* Sub Class (1 byte) */
+#define	PCI_CFG_PROG_IF		0x0B		/* Prog Interface (1 byte) */
+
+#define	PCI_CFG_CACHE_LINE	0x0C		/* Cache line size (1 byte) */
+#define	PCI_CFG_LATENCY_TIMER	0x0D		/* Latency Timer (1 byte) */
+#define	PCI_CFG_HEADER_TYPE	0x0E		/* Header Type (1 byte) */
+#define	PCI_CFG_BIST		0x0F		/* Built In Self Test */
+
+#define	PCI_CFG_BASE_ADDR_0	0x10		/* Base Address (4 bytes) */
+#define	PCI_CFG_BASE_ADDR_1	0x14		/* Base Address (4 bytes) */
+#define	PCI_CFG_BASE_ADDR_2	0x18		/* Base Address (4 bytes) */
+#define	PCI_CFG_BASE_ADDR_3	0x1C		/* Base Address (4 bytes) */
+#define	PCI_CFG_BASE_ADDR_4	0x20		/* Base Address (4 bytes) */
+#define	PCI_CFG_BASE_ADDR_5	0x24		/* Base Address (4 bytes) */
+
+#define	PCI_CFG_BASE_ADDR_OFF	0x04		/* Base Address Offset (1..5)*/
+#define	PCI_CFG_BASE_ADDR(n)	(PCI_CFG_BASE_ADDR_0 + (n)*PCI_CFG_BASE_ADDR_OFF)
+#define	PCI_CFG_BASE_ADDRS	6		/* up to this many BASE regs */
+
+#define	PCI_CFG_CARDBUS_CIS	0x28		/* Cardbus CIS Pointer (4B) */
+
+#define	PCI_CFG_SUBSYS_VEND_ID	0x2C		/* Subsystem Vendor ID (2B) */
+#define	PCI_CFG_SUBSYS_ID	0x2E		/* Subsystem ID */
+
+#define	PCI_EXPANSION_ROM	0x30		/* Expansion Rom Base (4B) */
+
+#define	PCI_INTR_LINE		0x3C		/* Interrupt Line (1B) */
+#define	PCI_INTR_PIN		0x3D		/* Interrupt Pin (1B) */
+#define	PCI_MIN_GNT		0x3E		/* Minimum Grant (1B) */
+#define	PCI_MAX_LAT		0x3F		/* Maximum Latency (1B) */
+
+#define PCI_CFG_VEND_SPECIFIC	0x40		/* first vendor specific reg */
+
+/* layout for Type 0x01 headers */
+
+#define	PCI_CFG_PPB_BUS_PRI		0x18	/* immediate upstream bus # */
+#define	PCI_CFG_PPB_BUS_SEC		0x19	/* immediate downstream bus # */
+#define	PCI_CFG_PPB_BUS_SUB		0x1A	/* last downstream bus # */
+#define	PCI_CFG_PPB_SEC_LAT		0x1B	/* latency timer for SEC bus */
+#define PCI_CFG_PPB_IOBASE		0x1C	/* IO Base Addr bits 12..15 */
+#define PCI_CFG_PPB_IOLIM		0x1D	/* IO Limit Addr bits 12..15 */
+#define	PCI_CFG_PPB_SEC_STAT		0x1E	/* Secondary Status */
+#define PCI_CFG_PPB_MEMBASE		0x20	/* MEM Base Addr bits 16..31 */
+#define PCI_CFG_PPB_MEMLIM		0x22	/* MEM Limit Addr bits 16..31 */
+#define PCI_CFG_PPB_MEMPFBASE		0x24	/* PfMEM Base Addr bits 16..31 */
+#define PCI_CFG_PPB_MEMPFLIM		0x26	/* PfMEM Limit Addr bits 16..31 */
+#define PCI_CFG_PPB_MEMPFBASEHI		0x28	/* PfMEM Base Addr bits 32..63 */
+#define PCI_CFG_PPB_MEMPFLIMHI		0x2C	/* PfMEM Limit Addr bits 32..63 */
+#define PCI_CFG_PPB_IOBASEHI		0x30	/* IO Base Addr bits 16..31 */
+#define PCI_CFG_PPB_IOLIMHI		0x32	/* IO Limit Addr bits 16..31 */
+#define	PCI_CFG_PPB_SUB_VENDOR		0x34	/* Subsystem Vendor ID */
+#define	PCI_CFG_PPB_SUB_DEVICE		0x36	/* Subsystem Device ID */
+#define	PCI_CFG_PPB_INT_PIN		0x3D	/* Interrupt Pin */
+#define	PCI_CFG_PPB_BRIDGE_CTRL		0x3E	/* Bridge Control */
+     /* XXX- these might be DEC 21152 specific */
+#define	PCI_CFG_PPB_CHIP_CTRL		0x40
+#define	PCI_CFG_PPB_DIAG_CTRL		0x41
+#define	PCI_CFG_PPB_ARB_CTRL		0x42
+#define	PCI_CFG_PPB_SERR_DISABLE	0x64
+#define	PCI_CFG_PPB_CLK2_CTRL		0x68
+#define	PCI_CFG_PPB_SERR_STATUS		0x6A
+
+/* Command Register layout (0x04) */
+#define	PCI_CMD_IO_SPACE	0x001		/* I/O Space device */
+#define	PCI_CMD_MEM_SPACE	0x002		/* Memory Space */
+#define	PCI_CMD_BUS_MASTER	0x004		/* Bus Master */
+#define	PCI_CMD_SPEC_CYCLES	0x008		/* Special Cycles */
+#define	PCI_CMD_MEMW_INV_ENAB	0x010		/* Memory Write Inv Enable */
+#define	PCI_CMD_VGA_PALETTE_SNP	0x020		/* VGA Palette Snoop */
+#define	PCI_CMD_PAR_ERR_RESP	0x040		/* Parity Error Response */
+#define	PCI_CMD_WAIT_CYCLE_CTL	0x080		/* Wait Cycle Control */
+#define	PCI_CMD_SERR_ENABLE	0x100		/* SERR# Enable */
+#define	PCI_CMD_F_BK_BK_ENABLE	0x200		/* Fast Back-to-Back Enable */
+
+/* Status Register Layout (0x06) */
+#define	PCI_STAT_PAR_ERR_DET	0x8000		/* Detected Parity Error */
+#define	PCI_STAT_SYS_ERR	0x4000		/* Signaled System Error */
+#define	PCI_STAT_RCVD_MSTR_ABT	0x2000		/* Received Master Abort */
+#define	PCI_STAT_RCVD_TGT_ABT	0x1000		/* Received Target Abort */
+#define	PCI_STAT_SGNL_TGT_ABT	0x0800		/* Signaled Target Abort */
+
+#define	PCI_STAT_DEVSEL_TIMING	0x0600		/* DEVSEL Timing Mask */
+#define	DEVSEL_TIMING(_x)	(((_x) >> 9) & 3)	/* devsel tim macro */
+#define	DEVSEL_FAST		0		/* Fast timing */
+#define	DEVSEL_MEDIUM		1		/* Medium timing */
+#define	DEVSEL_SLOW		2		/* Slow timing */
+
+#define	PCI_STAT_DATA_PAR_ERR	0x0100		/* Data Parity Err Detected */
+#define	PCI_STAT_F_BK_BK_CAP	0x0080		/* Fast Back-to-Back Capable */
+#define	PCI_STAT_UDF_SUPP	0x0040		/* UDF Supported */
+#define	PCI_STAT_66MHZ_CAP	0x0020		/* 66 MHz Capable */
+
+/* BIST Register Layout (0x0F) */
+#define	PCI_BIST_BIST_CAP	0x80		/* BIST Capable */
+#define	PCI_BIST_START_BIST	0x40		/* Start BIST */
+#define	PCI_BIST_CMPLTION_MASK	0x0F		/* COMPLETION MASK */
+#define	PCI_BIST_CMPL_OK	0x00		/* 0 value is completion OK */
+
+/* Base Address Register 0x10 */
+#define	PCI_BA_IO_SPACE		0x1		/* I/O Space Marker */
+#define	PCI_BA_MEM_LOCATION	0x6		/* 2 bits for location avail */
+#define	PCI_BA_MEM_32BIT	0x0		/* Anywhere in 32bit space */
+#define	PCI_BA_MEM_1MEG		0x2		/* Locate below 1 Meg */
+#define	PCI_BA_MEM_64BIT	0x4		/* Anywhere in 64bit space */
+#define	PCI_BA_PREFETCH		0x8		/* Prefetchable, no side effect */
+
+/* PIO interface macros */
+
+#ifndef IOC3_EMULATION
+
+#define PCI_INB(x)          (*((volatile char*)x))
+#define PCI_INH(x)          (*((volatile short*)x))
+#define PCI_INW(x)          (*((volatile int*)x))
+#define PCI_OUTB(x,y)       (*((volatile char*)x) = y)
+#define PCI_OUTH(x,y)       (*((volatile short*)x) = y)
+#define PCI_OUTW(x,y)       (*((volatile int*)x) = y)
+
+#else
+
+extern uint pci_read(void * address, int type);
+extern void pci_write(void * address, int data, int type);
+
+#define BYTE   1
+#define HALF   2
+#define WORD   4
+
+#define PCI_INB(x)          pci_read((void *)(x),BYTE)
+#define PCI_INH(x)          pci_read((void *)(x),HALF)
+#define PCI_INW(x)          pci_read((void *)(x),WORD)
+#define PCI_OUTB(x,y)       pci_write((void *)(x),(y),BYTE)
+#define PCI_OUTH(x,y)       pci_write((void *)(x),(y),HALF)
+#define PCI_OUTW(x,y)       pci_write((void *)(x),(y),WORD)
+
+#endif /* !IOC3_EMULATION */
+						/* effects on reads, merges */
+
+#ifdef CONFIG_SGI_IP22
+#define BYTECOUNT_W_GIO	    0xbf400000
+#endif
+
+/*
+ * Definition of address layouts for PCI Config mechanism #1
+ * XXX- These largely duplicate PCI_TYPE1 constants at the top
+ * of the file; the two groups should probably be combined.
+ */
+
+#define CFG1_ADDR_REGISTER_MASK		0x000000fc
+#define CFG1_ADDR_FUNCTION_MASK		0x00000700
+#define CFG1_ADDR_DEVICE_MASK		0x0000f800
+#define CFG1_ADDR_BUS_MASK		0x00ff0000
+
+#define CFG1_REGISTER_SHIFT		2
+#define CFG1_FUNCTION_SHIFT		8
+#define CFG1_DEVICE_SHIFT		11
+#define CFG1_BUS_SHIFT			16
+
+#ifdef CONFIG_SGI_IP32
+ /* Definitions related to IP32 PCI Bridge policy
+  * XXX- should probaly be moved to a mace-specific header
+  */
+#define PCI_CONFIG_BITS			0xfe0085ff
+#define	PCI_CONTROL_MRMRA_ENABLE	0x00000800
+#define PCI_FIRST_IO_ADDR		0x1000
+#define PCI_IO_MAP_INCR			0x1000
+#endif /* CONFIG_SGI_IP32 */
+
+#endif /* _ASM_SN_PCI_PCI_DEFS_H */
diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h
new file mode 100644
index 000000000..4159fb07b
--- /dev/null
+++ b/include/asm-ia64/sn/pci/pcibr.h
@@ -0,0 +1,360 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_PCIBR_H
+#define _ASM_SN_PCI_PCIBR_H
+
+#if defined(__KERNEL__)
+
+#include <asm/sn/dmamap.h>
+#include <asm/sn/iobus.h>
+#include <asm/sn/pio.h>
+
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/bridge.h>
+
+/* =====================================================================
+ *    symbolic constants used by pcibr's xtalk bus provider
+ */
+
+#define PCIBR_PIOMAP_BUSY		0x80000000
+
+#define PCIBR_DMAMAP_BUSY		0x80000000
+#define	PCIBR_DMAMAP_SSRAM		0x40000000
+
+#define PCIBR_INTR_BLOCKED		0x40000000
+#define PCIBR_INTR_BUSY			0x80000000
+
+#if LANGUAGE_C
+
+/* =====================================================================
+ *    opaque types used by pcibr's xtalk bus provider
+ */
+
+typedef struct pcibr_piomap_s *pcibr_piomap_t;
+typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
+typedef struct pcibr_intr_s *pcibr_intr_t;
+
+/* =====================================================================
+ *    primary entry points: Bridge (pcibr) device driver
+ *
+ *	These functions are normal device driver entry points
+ *	and are called along with the similar entry points from
+ *	other device drivers. They are included here as documentation
+ *	of their existance and purpose.
+ *
+ *	pcibr_init() is called to inform us that there is a pcibr driver
+ *	configured into the kernel; it is responsible for registering
+ *	as a crosstalk widget and providing a routine to be called
+ *	when a widget with the proper part number is observed.
+ *
+ *	pcibr_attach() is called for each vertex in the hardware graph
+ *	corresponding to a crosstalk widget with the manufacturer
+ *	code and part number registered by pcibr_init().
+ */
+
+extern void		pcibr_init(void);
+
+extern int		pcibr_attach(devfs_handle_t);
+
+/* =====================================================================
+ *    bus provider function table
+ *
+ *	Normally, this table is only handed off explicitly
+ *	during provider initialization, and the PCI generic
+ *	layer will stash a pointer to it in the vertex; however,
+ *	exporting it explicitly enables a performance hack in
+ *	the generic PCI provider where if we know at compile
+ *	time that the only possible PCI provider is a
+ *	pcibr, we can go directly to this ops table.
+ */
+
+extern pciio_provider_t pcibr_provider;
+
+/* =====================================================================
+ *    secondary entry points: pcibr PCI bus provider
+ *
+ *	These functions are normally exported explicitly by
+ *	a direct call from the pcibr initialization routine
+ *	into the generic crosstalk provider; they are included
+ *	here to enable a more aggressive performance hack in
+ *	the generic crosstalk layer, where if we know that the
+ *	only possible crosstalk provider is pcibr, and we can
+ *	guarantee that all entry points are properly named, and
+ *	we can deal with the implicit casting properly, then
+ *	we can turn many of the generic provider routines into
+ *	plain brances, or even eliminate them (given sufficient
+ *	smarts on the part of the compilation system).
+ */
+
+extern pcibr_piomap_t	pcibr_piomap_alloc(devfs_handle_t dev,
+					   device_desc_t dev_desc,
+					   pciio_space_t space,
+					   iopaddr_t pci_addr,
+					   size_t byte_count,
+					   size_t byte_count_max,
+					   unsigned flags);
+
+extern void		pcibr_piomap_free(pcibr_piomap_t piomap);
+
+extern caddr_t		pcibr_piomap_addr(pcibr_piomap_t piomap,
+					  iopaddr_t xtalk_addr,
+					  size_t byte_count);
+
+extern void		pcibr_piomap_done(pcibr_piomap_t piomap);
+
+extern caddr_t		pcibr_piotrans_addr(devfs_handle_t dev,
+					    device_desc_t dev_desc,
+					    pciio_space_t space,
+					    iopaddr_t pci_addr,
+					    size_t byte_count,
+					    unsigned flags);
+
+extern iopaddr_t	pcibr_piospace_alloc(devfs_handle_t dev,
+					     device_desc_t dev_desc,
+					     pciio_space_t space,
+					     size_t byte_count,
+					     size_t alignment);
+extern void		pcibr_piospace_free(devfs_handle_t dev,
+					    pciio_space_t space,
+					    iopaddr_t pciaddr,
+					    size_t byte_count);
+
+extern pcibr_dmamap_t	pcibr_dmamap_alloc(devfs_handle_t dev,
+					   device_desc_t dev_desc,
+					   size_t byte_count_max,
+					   unsigned flags);
+
+extern void		pcibr_dmamap_free(pcibr_dmamap_t dmamap);
+
+extern iopaddr_t	pcibr_dmamap_addr(pcibr_dmamap_t dmamap,
+					  paddr_t paddr,
+					  size_t byte_count);
+
+extern alenlist_t	pcibr_dmamap_list(pcibr_dmamap_t dmamap,
+					  alenlist_t palenlist,
+					  unsigned flags);
+
+extern void		pcibr_dmamap_done(pcibr_dmamap_t dmamap);
+
+extern iopaddr_t	pcibr_dmatrans_addr(devfs_handle_t dev,
+					    device_desc_t dev_desc,
+					    paddr_t paddr,
+					    size_t byte_count,
+					    unsigned flags);
+
+extern alenlist_t	pcibr_dmatrans_list(devfs_handle_t dev,
+					    device_desc_t dev_desc,
+					    alenlist_t palenlist,
+					    unsigned flags);
+
+extern void		pcibr_dmamap_drain(pcibr_dmamap_t map);
+
+extern void		pcibr_dmaaddr_drain(devfs_handle_t vhdl,
+					    paddr_t addr,
+					    size_t bytes);
+
+extern void		pcibr_dmalist_drain(devfs_handle_t vhdl,
+					    alenlist_t list);
+
+typedef unsigned	pcibr_intr_ibit_f(pciio_info_t info,
+					  pciio_intr_line_t lines);
+
+extern void		pcibr_intr_ibit_set(devfs_handle_t, pcibr_intr_ibit_f *);
+
+extern pcibr_intr_t	pcibr_intr_alloc(devfs_handle_t dev,
+					 device_desc_t dev_desc,
+					 pciio_intr_line_t lines,
+					 devfs_handle_t owner_dev);
+
+extern void		pcibr_intr_free(pcibr_intr_t intr);
+
+extern int		pcibr_intr_connect(pcibr_intr_t intr,
+					   intr_func_t intr_func,
+					   intr_arg_t intr_arg,
+					   void *thread);
+
+extern void		pcibr_intr_disconnect(pcibr_intr_t intr);
+
+extern devfs_handle_t	pcibr_intr_cpu_get(pcibr_intr_t intr);
+
+extern void		pcibr_provider_startup(devfs_handle_t pcibr);
+
+extern void		pcibr_provider_shutdown(devfs_handle_t pcibr);
+
+extern int		pcibr_reset(devfs_handle_t dev);
+
+extern int              pcibr_write_gather_flush(devfs_handle_t dev);
+
+extern pciio_endian_t	pcibr_endian_set(devfs_handle_t dev,
+					 pciio_endian_t device_end,
+					 pciio_endian_t desired_end);
+
+extern pciio_priority_t pcibr_priority_set(devfs_handle_t dev,
+					   pciio_priority_t device_prio);
+
+extern uint64_t		pcibr_config_get(devfs_handle_t conn,
+					 unsigned reg,
+					 unsigned size);
+
+extern void		pcibr_config_set(devfs_handle_t conn,
+					 unsigned reg,
+					 unsigned size,
+					 uint64_t value);
+
+extern int		pcibr_error_devenable(devfs_handle_t pconn_vhdl,
+					      int error_code);
+
+extern pciio_slot_t	pcibr_error_extract(devfs_handle_t pcibr_vhdl,
+					    pciio_space_t *spacep,
+					    iopaddr_t *addrp);
+
+extern int		pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+					int *count_vchan0,
+					int *count_vchan1);
+
+extern int		pcibr_wrb_flush(devfs_handle_t pconn_vhdl);
+extern int		pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+					int *count_vchan0,
+					int *count_vchan1,
+					int *count_reserved,
+					int *count_pool);
+
+extern int		pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+					     int dev_1_rrbs, int virt1,
+					     int dev_2_rrbs, int virt2,
+					     int dev_3_rrbs, int virt3,
+					     int dev_4_rrbs, int virt4);
+
+typedef void
+rrb_alloc_funct_f	(devfs_handle_t xconn_vhdl,
+			 int *vendor_list);
+
+typedef rrb_alloc_funct_f      *rrb_alloc_funct_t;
+
+void			pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl,
+					       rrb_alloc_funct_f *func);
+
+extern void		pcibr_device_unregister(devfs_handle_t);
+extern int		pcibr_dma_enabled(devfs_handle_t);
+/*
+ * Bridge-specific flags that can be set via pcibr_device_flags_set
+ * and cleared via pcibr_device_flags_clear.  Other flags are
+ * more generic and are maniuplated through PCI-generic interfaces.
+ *
+ * Note that all PCI implementation-specific flags (Bridge flags, in
+ * this case) are in bits 15-31.  The lower 15 bits are reserved
+ * for PCI-generic flags.
+ *
+ * Some of these flags have been "promoted" to the
+ * generic layer, so they can be used without having
+ * to "know" that the PCI bus is hosted by a Bridge.
+ *
+ * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when 
+ * allocating ATE's. ATE count computation will assume that the
+ * address to be mapped will start on a page boundary.
+ */
+#define PCIBR_NO_ATE_ROUNDUP    0x00008000
+#define PCIBR_WRITE_GATHER	0x00010000	/* please use PCIIO version */
+#define PCIBR_NOWRITE_GATHER	0x00020000	/* please use PCIIO version */
+#define PCIBR_PREFETCH		0x00040000	/* please use PCIIO version */
+#define PCIBR_NOPREFETCH	0x00080000	/* please use PCIIO version */
+#define PCIBR_PRECISE		0x00100000
+#define PCIBR_NOPRECISE		0x00200000
+#define PCIBR_BARRIER		0x00400000
+#define PCIBR_NOBARRIER		0x00800000
+#define PCIBR_VCHAN0		0x01000000
+#define PCIBR_VCHAN1		0x02000000
+#define PCIBR_64BIT		0x04000000
+#define PCIBR_NO64BIT		0x08000000
+#define PCIBR_SWAP		0x10000000
+#define PCIBR_NOSWAP		0x20000000
+
+#define	PCIBR_EXTERNAL_ATES	0x40000000	/* uses external ATEs */
+#define	PCIBR_ACTIVE		0x80000000	/* need a "done" */
+
+/* Flags that have meaning to pcibr_device_flags_{set,clear} */
+#define PCIBR_DEVICE_FLAGS (	\
+	PCIBR_WRITE_GATHER	|\
+	PCIBR_NOWRITE_GATHER	|\
+	PCIBR_PREFETCH		|\
+	PCIBR_NOPREFETCH	|\
+	PCIBR_PRECISE		|\
+	PCIBR_NOPRECISE		|\
+	PCIBR_BARRIER		|\
+	PCIBR_NOBARRIER		\
+)
+
+/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */
+#define PCIBR_DMA_FLAGS (	\
+	PCIBR_PREFETCH		|\
+	PCIBR_NOPREFETCH	|\
+	PCIBR_PRECISE		|\
+	PCIBR_NOPRECISE		|\
+	PCIBR_BARRIER		|\
+	PCIBR_NOBARRIER		|\
+	PCIBR_VCHAN0		|\
+	PCIBR_VCHAN1		\
+)
+
+typedef int		pcibr_device_flags_t;
+
+/*
+ * Set bits in the Bridge Device(x) register for this device.
+ * "flags" are defined above. NOTE: this includes turning
+ * things *OFF* as well as turning them *ON* ...
+ */
+extern int		pcibr_device_flags_set(devfs_handle_t dev,
+					     pcibr_device_flags_t flags);
+
+/*
+ * Allocate Read Response Buffers for use by the specified device.
+ * count_vchan0 is the total number of buffers desired for the
+ * "normal" channel.  count_vchan1 is the total number of buffers
+ * desired for the "virtual" channel.  Returns 0 on success, or
+ * <0 on failure, which occurs when we're unable to allocate any
+ * buffers to a channel that desires at least one buffer.
+ */
+extern int		pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+					int *count_vchan0,
+					int *count_vchan1);
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+extern iopaddr_t	pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+extern xwidget_intr_preset_f pcibr_xintr_preset;
+
+extern void		pcibr_hints_fix_rrbs(devfs_handle_t);
+extern void		pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+extern void		pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+extern void		pcibr_hints_handsoff(devfs_handle_t);
+
+typedef unsigned	pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t);
+extern void		pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+
+extern int		pcibr_asic_rev(devfs_handle_t);
+
+#endif 	/* _LANGUAGE_C */
+#endif	/* #if defined(__KERNEL__) */
+/* 
+ * Some useful ioctls into the pcibr driver
+ */
+#define PCIBR			'p'
+#define _PCIBR(x)		((PCIBR << 8) | (x))
+
+#define PCIBR_SLOT_POWERUP	_PCIBR(1)
+#define PCIBR_SLOT_SHUTDOWN	_PCIBR(2)
+#define PCIBR_SLOT_INQUIRY	_PCIBR(3)
+
+#endif				/* _ASM_SN_PCI_PCIBR_H */
diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h
new file mode 100644
index 000000000..f7f033989
--- /dev/null
+++ b/include/asm-ia64/sn/pci/pcibr_private.h
@@ -0,0 +1,415 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H
+#define _ASM_SN_PCI_PCIBR_PRIVATE_H
+
+/*
+ * pcibr_private.h -- private definitions for pcibr
+ * only the pcibr driver (and its closest friends)
+ * should ever peek into this file.
+ */
+
+#include <asm/sn/pci/pciio_private.h>
+
+/*
+ * convenience typedefs
+ */
+
+typedef uint64_t pcibr_DMattr_t;
+typedef uint32_t pcibr_ATEattr_t;
+
+typedef struct pcibr_info_s *pcibr_info_t, **pcibr_info_h;
+typedef struct pcibr_soft_s *pcibr_soft_t;
+typedef struct pcibr_soft_slot_s *pcibr_soft_slot_t;
+typedef struct pcibr_hints_s *pcibr_hints_t;
+typedef struct pcibr_intr_list_s *pcibr_intr_list_t;
+typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t;
+
+/*
+ * Bridge sets up PIO using this information.
+ */
+struct pcibr_piomap_s {
+    struct pciio_piomap_s   bp_pp;	/* generic stuff */
+
+#define	bp_flags	bp_pp.pp_flags	/* PCIBR_PIOMAP flags */
+#define	bp_dev		bp_pp.pp_dev	/* associated pci card */
+#define	bp_slot		bp_pp.pp_slot	/* which slot the card is in */
+#define	bp_space	bp_pp.pp_space	/* which address space */
+#define	bp_pciaddr	bp_pp.pp_pciaddr	/* starting offset of mapping */
+#define	bp_mapsz	bp_pp.pp_mapsz	/* size of this mapping */
+#define	bp_kvaddr	bp_pp.pp_kvaddr	/* kernel virtual address to use */
+
+    iopaddr_t               bp_xtalk_addr;	/* corresponding xtalk address */
+    xtalk_piomap_t          bp_xtalk_pio;	/* corresponding xtalk resource */
+    pcibr_piomap_t	    bp_next;	/* Next piomap on the list */
+    pcibr_soft_t	    bp_soft;	/* backpointer to bridge soft data */
+    int			    bp_toc[1];	/* PCI timeout counter */
+
+};
+
+/*
+ * Bridge sets up DMA using this information.
+ */
+struct pcibr_dmamap_s {
+    struct pciio_dmamap_s   bd_pd;
+#define	bd_flags	bd_pd.pd_flags	/* PCIBR_DMAMAP flags */
+#define	bd_dev		bd_pd.pd_dev	/* associated pci card */
+#define	bd_slot		bd_pd.pd_slot	/* which slot the card is in */
+    struct pcibr_soft_s    *bd_soft;	/* pcibr soft state backptr */
+    xtalk_dmamap_t          bd_xtalk;	/* associated xtalk resources */
+
+    size_t                  bd_max_size;	/* maximum size of mapping */
+    xwidgetnum_t            bd_xio_port;	/* target XIO port */
+    iopaddr_t               bd_xio_addr;	/* target XIO address */
+    iopaddr_t               bd_pci_addr;	/* via PCI address */
+
+    int                     bd_ate_index;	/* Address Translation Entry Index */
+    int                     bd_ate_count;	/* number of ATE's allocated */
+    bridge_ate_p            bd_ate_ptr;		/* where to write first ATE */
+    bridge_ate_t            bd_ate_proto;	/* prototype ATE (for xioaddr=0) */
+    bridge_ate_t            bd_ate_prime;	/* value of 1st ATE written */
+};
+
+/*
+ * Bridge sets up interrupts using this information.
+ */
+
+struct pcibr_intr_s {
+    struct pciio_intr_s     bi_pi;
+#define	bi_flags	bi_pi.pi_flags	/* PCIBR_INTR flags */
+#define	bi_dev		bi_pi.pi_dev	/* associated pci card */
+#define	bi_lines	bi_pi.pi_lines	/* which PCI interrupt line(s) */
+#define	bi_func		bi_pi.pi_func	/* handler function (when connected) */
+#define	bi_arg		bi_pi.pi_arg	/* handler parameter (when connected) */
+#define bi_tinfo	bi_pi.pi_tinfo	/* Thread info (when connected) */
+#define bi_mustruncpu	bi_pi.pi_mustruncpu /* Where we must run. */
+#define bi_irq		bi_pi.pi_irq	/* IRQ assigned. */
+#define bi_cpu		bi_pi.pi_cpu	/* cpu assigned. */
+    unsigned                bi_ibits;	/* which Bridge interrupt bit(s) */
+    pcibr_soft_t            bi_soft;	/* shortcut to soft info */
+};
+
+/*
+ * per-connect point pcibr data, including
+ * standard pciio data in-line:
+ */
+struct pcibr_info_s {
+    struct pciio_info_s	    f_c;	/* MUST BE FIRST. */
+#define	f_vertex	f_c.c_vertex	/* back pointer to vertex */
+#define	f_bus		f_c.c_bus	/* which bus the card is in */
+#define	f_slot		f_c.c_slot	/* which slot the card is in */
+#define	f_func		f_c.c_func	/* which func (on multi-func cards) */
+#define	f_vendor	f_c.c_vendor	/* PCI card "vendor" code */
+#define	f_device	f_c.c_device	/* PCI card "device" code */
+#define	f_master	f_c.c_master	/* PCI bus provider */
+#define	f_mfast		f_c.c_mfast	/* cached fastinfo from c_master */
+#define	f_pops		f_c.c_pops	/* cached provider from c_master */
+#define	f_efunc		f_c.c_efunc	/* error handling function */
+#define	f_einfo		f_c.c_einfo	/* first parameter for efunc */
+#define	f_window	f_c.c_window	/* state of BASE regs */
+#define	f_rbase		f_c.c_rbase	/* expansion rom base */
+#define	f_rsize		f_c.c_rsize	/* expansion rom size */
+#define	f_piospace	f_c.c_piospace	/* additional I/O spaces allocated */
+
+    /* pcibr-specific connection state */
+    int			    f_ibit[4];	/* Bridge bit for each INTx */
+    pcibr_piomap_t	    f_piomap;
+};
+
+/* =====================================================================
+ *          Shared Interrupt Information
+ */
+
+struct pcibr_intr_list_s {
+    pcibr_intr_list_t       il_next;
+    pcibr_intr_t            il_intr;
+    volatile bridgereg_t   *il_wrbf;	/* ptr to b_wr_req_buf[] */
+};
+
+/* =====================================================================
+ *          Interrupt Wrapper Data
+ */
+struct pcibr_intr_wrap_s {
+    pcibr_soft_t            iw_soft;	/* which bridge */
+    volatile bridgereg_t   *iw_stat;	/* ptr to b_int_status */
+    bridgereg_t             iw_intr;	/* bits in b_int_status */
+    pcibr_intr_list_t       iw_list;	/* ghostbusters! */
+};
+
+#define	PCIBR_ISR_ERR_START	8
+#define PCIBR_ISR_MAX_ERRS 	32
+
+/* =====================================================================
+ *            Bridge Device State structure
+ *
+ *      one instance of this structure is kept for each
+ *      Bridge ASIC in the system.
+ */
+
+struct pcibr_soft_s {
+    devfs_handle_t            bs_conn;	/* xtalk connection point */
+    devfs_handle_t            bs_vhdl;	/* vertex owned by pcibr */
+    int                     bs_int_enable;	/* Mask of enabled intrs */
+    bridge_t               *bs_base;	/* PIO pointer to Bridge chip */
+    char                   *bs_name;	/* hw graph name */
+    xwidgetnum_t            bs_xid;	/* Bridge's xtalk ID number */
+    devfs_handle_t            bs_master;	/* xtalk master vertex */
+    xwidgetnum_t            bs_mxid;	/* master's xtalk ID number */
+
+    iopaddr_t               bs_dir_xbase;	/* xtalk address for 32-bit PCI direct map */
+    xwidgetnum_t	    bs_dir_xport;	/* xtalk port for 32-bit PCI direct map */
+
+    struct map             *bs_int_ate_map;	/* rmalloc map for internal ATEs */
+    struct map             *bs_ext_ate_map;	/* rmalloc map for external ATEs */
+    short		    bs_int_ate_size;	/* number of internal ates */
+    short		    bs_xbridge;		/* if 1 then xbridge */
+
+    int                     bs_rev_num;	/* revision number of Bridge */
+
+    unsigned                bs_dma_flags;	/* revision-implied DMA flags */
+
+    /*
+     * Lock used primarily to get mutual exclusion while managing any
+     * bridge resources..
+     */
+    lock_t                  bs_lock;
+    
+    devfs_handle_t	    bs_noslot_conn;	/* NO-SLOT connection point */
+    pcibr_info_t	    bs_noslot_info;
+    struct pcibr_soft_slot_s {
+	/* information we keep about each CFG slot */
+
+	/* some devices (ioc3 in non-slotted
+	 * configurations, sometimes) make use
+	 * of more than one REQ/GNT/INT* signal
+	 * sets. The slot corresponding to the
+	 * IDSEL that the device responds to is
+	 * called the host slot; the slot
+	 * numbers that the device is stealing
+	 * REQ/GNT/INT bits from are known as
+	 * the guest slots.
+	 */
+	int                     has_host;
+	pciio_slot_t            host_slot;
+	devfs_handle_t		slot_conn;
+	/* Potentially several connection points
+	 * for this slot. bss_ninfo is how many,
+	 * and bss_infos is a pointer to
+	 * an array pcibr_info_t values (which are
+	 * pointers to pcibr_info structs, stored
+	 * as device_info in connection ponts).
+	 */
+	int			bss_ninfo;
+	pcibr_info_h	        bss_infos;
+
+	/* Temporary Compatibility Macros, for
+	 * stuff that has moved out of bs_slot
+	 * and into the info structure. These
+	 * will go away when their users have
+	 * converted over to multifunction-
+	 * friendly use of bss_{ninfo,infos}.
+	 */
+#define	bss_vendor_id	bss_infos[0]->f_vendor
+#define	bss_device_id	bss_infos[0]->f_device
+#define	bss_window	bss_infos[0]->f_window
+#define	bssw_space	w_space
+#define	bssw_base	w_base
+#define	bssw_size	w_size
+
+	/* Where is DevIO(x) pointing? */
+	/* bssd_space is NONE if it is not assigned. */
+	struct {
+	    pciio_space_t           bssd_space;
+	    iopaddr_t               bssd_base;
+	} bss_devio;
+
+	/* Shadow value for Device(x) register,
+	 * so we don't have to go to the chip.
+	 */
+	bridgereg_t             bss_device;
+
+	/* Number of sets on GBR/REALTIME bit outstanding
+	 * Used by Priority I/O for tracking reservations
+	 */
+	int                     bss_pri_uctr;
+
+	/* Number of "uses" of PMU, 32-bit direct,
+	 * and 64-bit direct DMA (0:none, <0: trans,
+	 * >0: how many dmamaps). Device(x) bits
+	 * controlling attribute of each kind of
+	 * channel can't be changed by dmamap_alloc
+	 * or dmatrans if the controlling counter
+	 * is nonzero. dmatrans is forever.
+	 */
+	int                     bss_pmu_uctr;
+	int                     bss_d32_uctr;
+	int                     bss_d64_uctr;
+
+	/* When the contents of mapping configuration
+	 * information is locked down by dmatrans,
+	 * repeated checks of the same flags should
+	 * be shortcircuited for efficiency.
+	 */
+	iopaddr_t		bss_d64_base;
+	unsigned		bss_d64_flags;
+	iopaddr_t		bss_d32_base;
+	unsigned		bss_d32_flags;
+
+	/* Shadow information used for implementing
+	 * Bridge Hardware WAR #484930
+	 */
+	int			bss_ext_ates_active;
+        volatile unsigned      *bss_cmd_pointer;
+	unsigned		bss_cmd_shadow;
+
+    } bs_slot[8];
+
+    pcibr_intr_bits_f	       *bs_intr_bits;
+
+    /* RRB MANAGEMENT
+     * bs_rrb_fixed: bitmap of slots whose RRB
+     *	allocations we should not "automatically" change
+     * bs_rrb_avail: number of RRBs that have not
+     *  been allocated or reserved for {even,odd} slots
+     * bs_rrb_res: number of RRBs reserved for the
+     *	use of the index slot number
+     * bs_rrb_valid: number of RRBs marked valid
+     *	for the indexed slot number; indexes 8-15
+     *	are for the virtual channels for slots 0-7.
+     */
+    int                     bs_rrb_fixed;
+    int			    bs_rrb_avail[2];
+    int			    bs_rrb_res[8];
+    int			    bs_rrb_valid[16];
+
+    struct {
+	/* Each Bridge interrupt bit has a single XIO
+	 * interrupt channel allocated.
+	 */
+	xtalk_intr_t            bsi_xtalk_intr;
+	/*
+	 * We do not like sharing PCI interrrupt lines
+	 * between devices, but the Origin 200 PCI
+	 * layout forces us to do so.
+	 */
+	pcibr_intr_list_t       bsi_pcibr_intr_list;
+	pcibr_intr_wrap_t       bsi_pcibr_intr_wrap;
+	int                     bsi_pcibr_wrap_set;
+
+    } bs_intr[8];
+
+    xtalk_intr_t		bsi_err_intr;
+
+    /*
+     * We stash away some information in this structure on getting
+     * an error interrupt. This information is used during PIO read/
+     * write error handling.
+     *
+     * As it stands now, we do not re-enable the error interrupt
+     * till the error is resolved. Error resolution happens either at
+     * bus error time for PIO Read errors (~100 microseconds), or at
+     * the scheduled timeout time for PIO write errors (~milliseconds).
+     * If this delay causes problems, we may need to move towards
+     * a different scheme..
+     *
+     * Note that there is no locking while looking at this data structure.
+     * There should not be any race between bus error code and
+     * error interrupt code.. will look into this if needed.
+     */
+    struct br_errintr_info {
+	int                     bserr_toutcnt;
+#ifdef IRIX
+	toid_t                  bserr_toutid;	/* Timeout started by errintr */
+#endif
+	iopaddr_t               bserr_addr;	/* Address where error occured */
+	bridgereg_t             bserr_intstat;	/* interrupts active at error time */
+    } bs_errinfo;
+
+    /*
+     * PCI Bus Space allocation data structure.
+     * This info is used to satisfy the callers of pcibr_piospace_alloc
+     * interface. Most of these users need "large" amounts of PIO
+     * space (typically in Megabytes), and they generally tend to
+     * take once and never release..
+     * For Now use a simple algorithm to manage it. On allocation,
+     * Update the _base field to reflect next free address.
+     *
+     * Freeing does nothing.. So, once allocated, it's gone for good.
+     */
+    struct br_pcisp_info {
+	iopaddr_t               pci_io_base;
+	iopaddr_t               pci_io_last;
+	iopaddr_t               pci_swin_base;
+	iopaddr_t               pci_swin_last;
+	iopaddr_t               pci_mem_base;
+	iopaddr_t               pci_mem_last;
+    } bs_spinfo;
+
+    struct bs_errintr_stat_s {
+	uint32_t              bs_errcount_total;
+	uint32_t              bs_lasterr_timestamp;
+	uint32_t              bs_lasterr_snapshot;
+    } bs_errintr_stat[PCIBR_ISR_MAX_ERRS];
+
+    /*
+     * Bridge-wide endianness control for
+     * large-window PIO mappings
+     *
+     * These fields are set to PCIIO_BYTE_SWAP
+     * or PCIIO_WORD_VALUES once the swapper
+     * has been configured, one way or the other,
+     * for the direct windows. If they are zero,
+     * nobody has a PIO mapping through that window,
+     * and the swapper can be set either way.
+     */
+    unsigned		bs_pio_end_io;
+    unsigned		bs_pio_end_mem;
+};
+
+#define	PCIBR_ERRTIME_THRESHOLD		(100)
+#define	PCIBR_ERRRATE_THRESHOLD		(100)
+
+/*
+ * pcibr will respond to hints dropped in its vertex
+ * using the following structure.
+ */
+struct pcibr_hints_s {
+    /* ph_host_slot is actually +1 so "0" means "no host" */
+    pciio_slot_t            ph_host_slot[8];	/* REQ/GNT/INT in use by ... */
+    unsigned                ph_rrb_fixed;	/* do not change RRB allocations */
+    unsigned                ph_hands_off;	/* prevent further pcibr operations */
+    rrb_alloc_funct_t       rrb_alloc_funct;	/* do dynamic rrb allocation */
+    pcibr_intr_bits_f	   *ph_intr_bits;	/* map PCI INT[ABCD] to Bridge Int(n) */
+};
+
+extern int              pcibr_prefetch_enable_rev, pcibr_wg_enable_rev;
+
+/*
+ * Number of bridge non-fatal error interrupts we can see before
+ * we decide to disable that interrupt.
+ */
+#define	PCIBR_ERRINTR_DISABLE_LEVEL	10000
+
+/* =====================================================================
+ *    Bridge (pcibr) state management functions
+ *
+ *      pcibr_soft_get is here because we do it in a lot
+ *      of places and I want to make sure they all stay
+ *      in step with each other.
+ *
+ *      pcibr_soft_set is here because I want it to be
+ *      closely associated with pcibr_soft_get, even
+ *      though it is only called in one place.
+ */
+
+#define pcibr_soft_get(v)       ((pcibr_soft_t)hwgraph_fastinfo_get((v)))
+#define pcibr_soft_set(v,i)     (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i)))
+
+#endif				/* _ASM_SN_PCI_PCIBR_PRIVATE_H */
diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h
new file mode 100644
index 000000000..304d4410b
--- /dev/null
+++ b/include/asm-ia64/sn/pci/pciio.h
@@ -0,0 +1,717 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_PCIIO_H
+#define _ASM_SN_PCI_PCIIO_H
+
+/*
+ * pciio.h -- platform-independent PCI interface
+ */
+
+#include <asm/sn/ioerror.h>
+#include <asm/sn/iobus.h>
+
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+
+#include <asm/sn/dmamap.h>
+#include <asm/sn/alenlist.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int pciio_vendor_id_t;
+
+#define PCIIO_VENDOR_ID_NONE	-1
+
+typedef int pciio_device_id_t;
+
+#define PCIIO_DEVICE_ID_NONE	-1
+
+#ifdef colin
+typedef char pciio_bus_t;	/* PCI bus number (0..255) */
+typedef char pciio_slot_t;	/* PCI slot number (0..31, 255) */
+typedef char pciio_function_t;	/* PCI func number (0..7, 255) */
+#else
+typedef uint8_t pciio_bus_t;       /* PCI bus number (0..255) */
+typedef uint8_t pciio_slot_t;      /* PCI slot number (0..31, 255) */
+typedef uint8_t pciio_function_t;  /* PCI func number (0..7, 255) */
+#endif
+
+#define	PCIIO_SLOTS		((pciio_slot_t)32)
+#define	PCIIO_FUNCS		((pciio_function_t)8)
+
+#define	PCIIO_SLOT_NONE		((pciio_slot_t)255)
+#define	PCIIO_FUNC_NONE		((pciio_function_t)255)
+
+typedef int pciio_intr_line_t;		/* PCI interrupt line(s) */
+
+#define PCIIO_INTR_LINE(n)      (0x1 << (n))
+#define PCIIO_INTR_LINE_A	(0x1)
+#define PCIIO_INTR_LINE_B	(0x2)
+#define PCIIO_INTR_LINE_C	(0x4)
+#define PCIIO_INTR_LINE_D	(0x8)
+
+typedef int pciio_space_t;		/* PCI address space designation */
+
+#define PCIIO_SPACE_NONE	(0)
+#define	PCIIO_SPACE_ROM		(1)
+#define PCIIO_SPACE_IO		(2)
+/*	PCIIO_SPACE_		(3) */
+#define PCIIO_SPACE_MEM		(4)
+#define PCIIO_SPACE_MEM32	(5)
+#define PCIIO_SPACE_MEM64	(6)
+#define PCIIO_SPACE_CFG		(7)
+#define PCIIO_SPACE_WIN0	(8)
+#define PCIIO_SPACE_WIN(n)	(PCIIO_SPACE_WIN0+(n))	/* 8..13 */
+/*	PCIIO_SPACE_		(14) */
+#define PCIIO_SPACE_BAD		(15)
+
+#if 1	/* does anyone really use these? */
+#define PCIIO_SPACE_USER0	(20)
+#define PCIIO_SPACE_USER(n)	(PCIIO_SPACE_USER0+(n))	/* 20 .. ? */
+#endif
+
+/*
+ * PCI_NOWHERE is the error value returned in
+ * place of a PCI address when there is no
+ * corresponding address.
+ */
+#define	PCI_NOWHERE		(0)
+
+/*
+ *    Acceptable flag bits for pciio service calls
+ *
+ * PCIIO_FIXED: require that mappings be established
+ *	using fixed sharable resources; address
+ *	translation results will be permanently
+ *	available. (PIOMAP_FIXED and DMAMAP_FIXED are
+ *	the same numeric value and are acceptable).
+ * PCIIO_NOSLEEP: if any part of the operation would
+ *	sleep waiting for resoruces, return an error
+ *	instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are
+ *	the same numeric value and are acceptable).
+ * PCIIO_INPLACE: when operating on alenlist structures,
+ *	reuse the source alenlist rather than creating a
+ *	new one. (PIOMAP_INPLACE and DMAMAP_INPLACE are
+ *	the same numeric value and are acceptable).
+ *
+ * PCIIO_DMA_CMD: configure this stream as a
+ *	generic "command" stream. Generally this
+ *	means turn off prefetchers and write
+ *	gatherers, and whatever else might be
+ *	necessary to make command ring DMAs
+ *	work as expected.
+ * PCIIO_DMA_DATA: configure this stream as a
+ *	generic "data" stream. Generally, this
+ *	means turning on prefetchers and write
+ *	gatherers, and anything else that might
+ *	increase the DMA throughput (short of
+ *	using "high priority" or "real time"
+ *	resources that may lower overall system
+ *	performance).
+ * PCIIO_DMA_A64: this device is capable of
+ *	using 64-bit DMA addresses. Unless this
+ *	flag is specified, it is assumed that
+ *	the DMA address must be in the low 4G
+ *	of PCI space.
+ * PCIIO_PREFETCH: if there are prefetchers
+ *	available, they can be turned on.
+ * PCIIO_NOPREFETCH: any prefetchers along
+ *	the dma path should be turned off.
+ * PCIIO_WRITE_GATHER: if there are write gatherers
+ *	available, they can be turned on.
+ * PCIIO_NOWRITE_GATHER: any write gatherers along
+ *	the dma path should be turned off.
+ *
+ * PCIIO_BYTE_STREAM: the DMA stream represents a group
+ *	of ordered bytes. Arrange all byte swapping
+ *	hardware so that the bytes land in the correct
+ *	order. This is a common setting for data
+ *	channels, but is NOT implied by PCIIO_DMA_DATA.
+ * PCIIO_WORD_VALUES: the DMA stream is used to
+ *	communicate quantities stored in multiple bytes,
+ *	and the device doing the DMA is little-endian;
+ *	arrange any swapping hardware so that
+ *	32-bit-wide values are maintained. This is a
+ *	common setting for command rings that contain
+ *	DMA addresses and counts, but is NOT implied by
+ *	PCIIO_DMA_CMD. CPU Accesses to 16-bit fields
+ *	must have their address xor-ed with 2, and
+ *	accesses to individual bytes must have their
+ *	addresses xor-ed with 3 relative to what the
+ *	device expects.
+ *
+ * NOTE: any "provider specific" flags that
+ * conflict with the generic flags will
+ * override the generic flags, locally
+ * at that provider.
+ *
+ * Also, note that PCI-generic flags (PCIIO_) are
+ * in bits 0-14. The upper bits, 15-31, are reserved
+ * for PCI implementation-specific flags.
+ */
+
+#define	PCIIO_FIXED		DMAMAP_FIXED
+#define	PCIIO_NOSLEEP		DMAMAP_NOSLEEP
+#define	PCIIO_INPLACE		DMAMAP_INPLACE
+
+#define PCIIO_DMA_CMD		0x0010
+#define PCIIO_DMA_DATA		0x0020
+#define PCIIO_DMA_A64		0x0040
+
+#define PCIIO_WRITE_GATHER	0x0100
+#define PCIIO_NOWRITE_GATHER	0x0200
+#define PCIIO_PREFETCH		0x0400
+#define PCIIO_NOPREFETCH	0x0800
+
+/* Requesting an endianness setting that the
+ * underlieing hardware can not support
+ * WILL result in a failure to allocate
+ * dmamaps or complete a dmatrans.
+ */
+#define	PCIIO_BYTE_STREAM	0x1000	/* set BYTE SWAP for "byte stream" */
+#define	PCIIO_WORD_VALUES	0x2000	/* set BYTE SWAP for "word values" */
+
+/*
+ * Interface to deal with PCI endianness.
+ * The driver calls pciio_endian_set once, supplying the actual endianness of
+ * the device and the desired endianness.  On SGI systems, only use LITTLE if
+ * dealing with a driver that does software swizzling.  Most of the time,
+ * it's preferable to request BIG.  The return value indicates the endianness
+ * that is actually achieved.  On systems that support hardware swizzling,
+ * the achieved endianness will be the desired endianness.  On systems without
+ * swizzle hardware, the achieved endianness will be the device's endianness.
+ */
+typedef enum pciio_endian_e {
+    PCIDMA_ENDIAN_BIG,
+    PCIDMA_ENDIAN_LITTLE
+} pciio_endian_t;
+
+/*
+ * Interface to set PCI arbitration priority for devices that require
+ * realtime characteristics.  pciio_priority_set is used to switch a
+ * device between the PCI high-priority arbitration ring and the low
+ * priority arbitration ring.
+ *
+ * (Note: this is strictly for the PCI arbitrary priority.  It has
+ * no direct relationship to GBR.)
+ */
+typedef enum pciio_priority_e {
+    PCI_PRIO_LOW,
+    PCI_PRIO_HIGH
+} pciio_priority_t;
+
+/*
+ * handles of various sorts
+ */
+typedef struct pciio_piomap_s *pciio_piomap_t;
+typedef struct pciio_dmamap_s *pciio_dmamap_t;
+typedef struct pciio_intr_s *pciio_intr_t;
+typedef struct pciio_info_s *pciio_info_t;
+typedef struct pciio_piospace_s *pciio_piospace_t;
+
+/* PIO MANAGEMENT */
+
+/*
+ *    A NOTE ON PCI PIO ADDRESSES
+ *
+ *      PCI supports three different address spaces: CFG
+ *      space, MEM space and I/O space. Further, each
+ *      card always accepts CFG accesses at an address
+ *      based on which slot it is attached to, but can
+ *      decode up to six address ranges.
+ *
+ *      Assignment of the base address registers for all
+ *      PCI devices is handled centrally; most commonly,
+ *      device drivers will want to talk to offsets
+ *      within one or another of the address ranges. In
+ *      order to do this, which of these "address
+ *      spaces" the PIO is directed into must be encoded
+ *      in the flag word.
+ *
+ *      We reserve the right to defer allocation of PCI
+ *      address space for a device window until the
+ *      driver makes a piomap_alloc or piotrans_addr
+ *      request.
+ *
+ *      If a device driver mucks with its device's base
+ *      registers through a PIO mapping to CFG space,
+ *      results of further PIO through the corresponding
+ *      window are UNDEFINED.
+ *
+ *      Windows are named by the index in the base
+ *      address register set for the device of the
+ *      desired register; IN THE CASE OF 64 BIT base
+ *      registers, the index should be to the word of
+ *      the register that contains the mapping type
+ *      bits; since the PCI CFG space is natively
+ *      organized little-endian fashion, this is the
+ *      first of the two words.
+ *
+ *      AT THE MOMENT, any required corrections for
+ *      endianness are the responsibility of the device
+ *      driver; not all platforms support control in
+ *      hardware of byteswapping hardware. We anticipate
+ *      providing flag bits to the PIO and DMA
+ *      management interfaces to request different
+ *      configurations of byteswapping hardware.
+ *
+ *      PIO Accesses to CFG space via the "Bridge" ASIC
+ *      used in IP30 platforms preserve the native byte
+ *      significance within the 32-bit word; byte
+ *      addresses for single byte accesses need to be
+ *      XORed with 3, and addresses for 16-bit accesses
+ *      need to be XORed with 2.
+ *
+ *      The IOC3 used on IP30, and other SGI PCI devices
+ *      as well, require use of 32-bit accesses to their
+ *      configuration space registers. Any potential PCI
+ *      bus providers need to be aware of this requirement.
+ */
+
+#define PCIIO_PIOMAP_CFG	(0x1)
+#define PCIIO_PIOMAP_MEM	(0x2)
+#define PCIIO_PIOMAP_IO		(0x4)
+#define PCIIO_PIOMAP_WIN(n)	(0x8+(n))
+
+typedef pciio_piomap_t
+pciio_piomap_alloc_f    (devfs_handle_t dev,	/* set up mapping for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 pciio_space_t space,	/* which address space */
+			 iopaddr_t pcipio_addr,		/* starting address */
+			 size_t byte_count,
+			 size_t byte_count_max,		/* maximum size of a mapping */
+			 unsigned flags);	/* defined in sys/pio.h */
+
+typedef void
+pciio_piomap_free_f     (pciio_piomap_t pciio_piomap);
+
+typedef caddr_t
+pciio_piomap_addr_f     (pciio_piomap_t pciio_piomap,	/* mapping resources */
+			 iopaddr_t pciio_addr,	/* map for this pcipio address */
+			 size_t byte_count);	/* map this many bytes */
+
+typedef void
+pciio_piomap_done_f     (pciio_piomap_t pciio_piomap);
+
+typedef caddr_t
+pciio_piotrans_addr_f   (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 pciio_space_t space,	/* which address space */
+			 iopaddr_t pciio_addr,	/* starting address */
+			 size_t byte_count,	/* map this many bytes */
+			 unsigned flags);
+
+typedef caddr_t
+pciio_pio_addr_f        (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 pciio_space_t space,	/* which address space */
+			 iopaddr_t pciio_addr,	/* starting address */
+			 size_t byte_count,	/* map this many bytes */
+			 pciio_piomap_t *mapp,	/* in case a piomap was needed */
+			 unsigned flags);
+
+typedef iopaddr_t
+pciio_piospace_alloc_f  (devfs_handle_t dev,	/* PIO space for this device */
+			 device_desc_t dev_desc,	/* Device descriptor   */
+			 pciio_space_t space,	/* which address space  */
+			 size_t byte_count,	/* Number of bytes of space */
+			 size_t alignment);	/* Alignment of allocation  */
+
+typedef void
+pciio_piospace_free_f   (devfs_handle_t dev,	/* Device freeing space */
+			 pciio_space_t space,	/* Which space is freed */
+			 iopaddr_t pci_addr,	/* Address being freed */
+			 size_t size);	/* Size freed           */
+
+/* DMA MANAGEMENT */
+
+typedef pciio_dmamap_t
+pciio_dmamap_alloc_f    (devfs_handle_t dev,	/* set up mappings for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 size_t byte_count_max,		/* max size of a mapping */
+			 unsigned flags);	/* defined in dma.h */
+
+typedef void
+pciio_dmamap_free_f     (pciio_dmamap_t dmamap);
+
+typedef iopaddr_t
+pciio_dmamap_addr_f     (pciio_dmamap_t dmamap,		/* use these mapping resources */
+			 paddr_t paddr,	/* map for this address */
+			 size_t byte_count);	/* map this many bytes */
+
+typedef alenlist_t
+pciio_dmamap_list_f     (pciio_dmamap_t dmamap,		/* use these mapping resources */
+			 alenlist_t alenlist,	/* map this address/length list */
+			 unsigned flags);
+
+typedef void
+pciio_dmamap_done_f     (pciio_dmamap_t dmamap);
+
+typedef iopaddr_t
+pciio_dmatrans_addr_f   (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 paddr_t paddr,	/* system physical address */
+			 size_t byte_count,	/* length */
+			 unsigned flags);	/* defined in dma.h */
+
+typedef alenlist_t
+pciio_dmatrans_list_f   (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 alenlist_t palenlist,	/* system address/length list */
+			 unsigned flags);	/* defined in dma.h */
+
+typedef void
+pciio_dmamap_drain_f	(pciio_dmamap_t map);
+
+typedef void
+pciio_dmaaddr_drain_f	(devfs_handle_t vhdl,
+			 paddr_t addr,
+			 size_t bytes);
+
+typedef void
+pciio_dmalist_drain_f	(devfs_handle_t vhdl,
+			 alenlist_t list);
+
+/* INTERRUPT MANAGEMENT */
+
+typedef pciio_intr_t
+pciio_intr_alloc_f      (devfs_handle_t dev,	/* which PCI device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 pciio_intr_line_t lines,	/* which line(s) will be used */
+			 devfs_handle_t owner_dev);	/* owner of this intr */
+
+typedef void
+pciio_intr_free_f       (pciio_intr_t intr_hdl);
+
+typedef int
+pciio_intr_connect_f    (pciio_intr_t intr_hdl,		/* pciio intr resource handle */
+			 intr_func_t intr_func,		/* pciio intr handler */
+			 intr_arg_t intr_arg,	/* arg to intr handler */
+			 void *thread);	/* intr thread to use */
+
+typedef void
+pciio_intr_disconnect_f (pciio_intr_t intr_hdl);
+
+typedef devfs_handle_t
+pciio_intr_cpu_get_f    (pciio_intr_t intr_hdl);	/* pciio intr resource handle */
+
+/* CONFIGURATION MANAGEMENT */
+
+typedef void
+pciio_provider_startup_f (devfs_handle_t pciio_provider);
+
+typedef void
+pciio_provider_shutdown_f (devfs_handle_t pciio_provider);
+
+typedef int	
+pciio_reset_f		(devfs_handle_t conn);	/* pci connection point */
+
+typedef int
+pciio_write_gather_flush_f (devfs_handle_t dev);    /* Device flushing buffers */
+
+typedef pciio_endian_t			/* actual endianness */
+pciio_endian_set_f      (devfs_handle_t dev,	/* specify endianness for this device */
+			 pciio_endian_t device_end,	/* endianness of device */
+			 pciio_endian_t desired_end);	/* desired endianness */
+
+typedef pciio_priority_t
+pciio_priority_set_f    (devfs_handle_t pcicard,
+			 pciio_priority_t device_prio);
+
+typedef uint64_t
+pciio_config_get_f	(devfs_handle_t conn,	/* pci connection point */
+			 unsigned reg,		/* register byte offset */
+			 unsigned size);	/* width in bytes (1..4) */
+
+typedef void
+pciio_config_set_f	(devfs_handle_t conn,	/* pci connection point */
+			 unsigned reg,		/* register byte offset */
+			 unsigned size,		/* width in bytes (1..4) */
+			 uint64_t value);	/* value to store */
+
+typedef int
+pciio_error_devenable_f (devfs_handle_t pconn_vhdl, int error_code);
+
+typedef pciio_slot_t
+pciio_error_extract_f	(devfs_handle_t vhdl,
+			 pciio_space_t *spacep,
+			 iopaddr_t *addrp);
+
+/*
+ * Adapters that provide a PCI interface adhere to this software interface.
+ */
+typedef struct pciio_provider_s {
+    /* PIO MANAGEMENT */
+    pciio_piomap_alloc_f   *piomap_alloc;
+    pciio_piomap_free_f    *piomap_free;
+    pciio_piomap_addr_f    *piomap_addr;
+    pciio_piomap_done_f    *piomap_done;
+    pciio_piotrans_addr_f  *piotrans_addr;
+    pciio_piospace_alloc_f *piospace_alloc;
+    pciio_piospace_free_f  *piospace_free;
+
+    /* DMA MANAGEMENT */
+    pciio_dmamap_alloc_f   *dmamap_alloc;
+    pciio_dmamap_free_f    *dmamap_free;
+    pciio_dmamap_addr_f    *dmamap_addr;
+    pciio_dmamap_list_f    *dmamap_list;
+    pciio_dmamap_done_f    *dmamap_done;
+    pciio_dmatrans_addr_f  *dmatrans_addr;
+    pciio_dmatrans_list_f  *dmatrans_list;
+    pciio_dmamap_drain_f   *dmamap_drain;
+    pciio_dmaaddr_drain_f  *dmaaddr_drain;
+    pciio_dmalist_drain_f  *dmalist_drain;
+
+    /* INTERRUPT MANAGEMENT */
+    pciio_intr_alloc_f     *intr_alloc;
+    pciio_intr_free_f      *intr_free;
+    pciio_intr_connect_f   *intr_connect;
+    pciio_intr_disconnect_f *intr_disconnect;
+    pciio_intr_cpu_get_f   *intr_cpu_get;
+
+    /* CONFIGURATION MANAGEMENT */
+    pciio_provider_startup_f *provider_startup;
+    pciio_provider_shutdown_f *provider_shutdown;
+    pciio_reset_f	   *reset;
+    pciio_write_gather_flush_f *write_gather_flush;
+    pciio_endian_set_f     *endian_set;
+    pciio_priority_set_f   *priority_set;
+    pciio_config_get_f	   *config_get;
+    pciio_config_set_f	   *config_set;
+
+    /* Error handling interface */
+    pciio_error_devenable_f *error_devenable;
+    pciio_error_extract_f *error_extract;
+} pciio_provider_t;
+
+/* PCI devices use these standard PCI provider interfaces */
+extern pciio_piomap_alloc_f pciio_piomap_alloc;
+extern pciio_piomap_free_f pciio_piomap_free;
+extern pciio_piomap_addr_f pciio_piomap_addr;
+extern pciio_piomap_done_f pciio_piomap_done;
+extern pciio_piotrans_addr_f pciio_piotrans_addr;
+extern pciio_pio_addr_f pciio_pio_addr;
+extern pciio_piospace_alloc_f pciio_piospace_alloc;
+extern pciio_piospace_free_f pciio_piospace_free;
+extern pciio_dmamap_alloc_f pciio_dmamap_alloc;
+extern pciio_dmamap_free_f pciio_dmamap_free;
+extern pciio_dmamap_addr_f pciio_dmamap_addr;
+extern pciio_dmamap_list_f pciio_dmamap_list;
+extern pciio_dmamap_done_f pciio_dmamap_done;
+extern pciio_dmatrans_addr_f pciio_dmatrans_addr;
+extern pciio_dmatrans_list_f pciio_dmatrans_list;
+extern pciio_dmamap_drain_f pciio_dmamap_drain;
+extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain;
+extern pciio_dmalist_drain_f pciio_dmalist_drain;
+extern pciio_intr_alloc_f pciio_intr_alloc;
+extern pciio_intr_free_f pciio_intr_free;
+extern pciio_intr_connect_f pciio_intr_connect;
+extern pciio_intr_disconnect_f pciio_intr_disconnect;
+extern pciio_intr_cpu_get_f pciio_intr_cpu_get;
+extern pciio_provider_startup_f pciio_provider_startup;
+extern pciio_provider_shutdown_f pciio_provider_shutdown;
+extern pciio_reset_f pciio_reset;
+extern pciio_write_gather_flush_f pciio_write_gather_flush;
+extern pciio_endian_set_f pciio_endian_set;
+extern pciio_priority_set_f pciio_priority_set;
+extern pciio_config_get_f pciio_config_get;
+extern pciio_config_set_f pciio_config_set;
+extern pciio_error_devenable_f pciio_error_devenable;
+extern pciio_error_extract_f pciio_error_extract;
+
+/* Widgetdev in the IOERROR structure is encoded as follows.
+ *	+---------------------------+
+ *	| slot (7:3) | function(2:0)|
+ *	+---------------------------+
+ * Following are the convenience interfaces to get at form
+ * a widgetdev or to break it into its constituents.
+ */
+
+#define PCIIO_WIDGETDEV_SLOT_SHFT		3
+#define PCIIO_WIDGETDEV_SLOT_MASK		0x1f
+#define PCIIO_WIDGETDEV_FUNC_MASK		0x7
+
+#ifdef IRIX
+#define pciio_widgetdev_create(slot,func)	\
+	((slot) << PCIIO_WIDGETDEV_SLOT_SHFT + (func))
+#else
+#define pciio_widgetdev_create(slot,func)       \
+        (((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func))
+#endif
+
+#define pciio_widgetdev_slot_get(wdev)		\
+	(((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK)
+
+#define pciio_widgetdev_func_get(wdev)		\
+	((wdev) & PCIIO_WIDGETDEV_FUNC_MASK)
+
+
+/* Generic PCI card initialization interface
+ */
+
+extern int
+pciio_driver_register  (pciio_vendor_id_t vendor_id,	/* card's vendor number */
+			pciio_device_id_t device_id,	/* card's device number */
+			char *driver_prefix,	/* driver prefix */
+			unsigned flags);
+
+extern void
+pciio_error_register   (devfs_handle_t pconn,	/* which slot */
+			error_handler_f *efunc,	/* function to call */
+			error_handler_arg_t einfo);	/* first parameter */
+
+extern void             pciio_driver_unregister(char *driver_prefix);
+
+typedef void		pciio_iter_f(devfs_handle_t pconn);	/* a connect point */
+
+extern void             pciio_iterate(char *driver_prefix,
+				      pciio_iter_f *func);
+
+/* Interfaces used by PCI Bus Providers to talk to
+ * the Generic PCI layer.
+ */
+extern devfs_handle_t
+pciio_device_register  (devfs_handle_t connectpt,	/* vertex at center of bus */
+			devfs_handle_t master,	/* card's master ASIC (pci provider) */
+			pciio_slot_t slot,	/* card's slot (0..?) */
+			pciio_function_t func,	/* card's func (0..?) */
+			pciio_vendor_id_t vendor,	/* card's vendor number */
+			pciio_device_id_t device);	/* card's device number */
+
+extern void
+pciio_device_unregister(devfs_handle_t connectpt);
+
+extern pciio_info_t
+pciio_device_info_new  (pciio_info_t pciio_info,	/* preallocated info struct */
+			devfs_handle_t master,	/* card's master ASIC (pci provider) */
+			pciio_slot_t slot,	/* card's slot (0..?) */
+			pciio_function_t func,	/* card's func (0..?) */
+			pciio_vendor_id_t vendor,	/* card's vendor number */
+			pciio_device_id_t device);	/* card's device number */
+
+extern void
+pciio_device_info_free(pciio_info_t pciio_info);
+
+extern devfs_handle_t
+pciio_device_info_register(
+			devfs_handle_t connectpt,	/* vertex at center of bus */
+			pciio_info_t pciio_info);	/* details about conn point */
+
+extern void
+pciio_device_info_unregister(
+			devfs_handle_t connectpt,	/* vertex at center of bus */
+			pciio_info_t pciio_info);	/* details about conn point */
+
+
+extern int              pciio_device_attach(devfs_handle_t pcicard);	/* vertex created by pciio_device_register */
+extern int             pciio_device_detach(devfs_handle_t pcicard);	/* vertex created by pciio_device_register */
+
+/*
+ * Generic PCI interface, for use with all PCI providers
+ * and all PCI devices.
+ */
+
+/* Generic PCI interrupt interfaces */
+extern devfs_handle_t     pciio_intr_dev_get(pciio_intr_t pciio_intr);
+extern devfs_handle_t     pciio_intr_cpu_get(pciio_intr_t pciio_intr);
+
+/* Generic PCI pio interfaces */
+extern devfs_handle_t     pciio_pio_dev_get(pciio_piomap_t pciio_piomap);
+extern pciio_slot_t     pciio_pio_slot_get(pciio_piomap_t pciio_piomap);
+extern pciio_space_t    pciio_pio_space_get(pciio_piomap_t pciio_piomap);
+extern iopaddr_t        pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap);
+extern ulong            pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap);
+extern caddr_t          pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap);
+
+#ifdef IRIX
+#ifdef USE_PCI_PIO
+extern uint8_t 		pciio_pio_read8(volatile uint8_t *addr);
+extern uint16_t 	pciio_pio_read16(volatile uint16_t *addr);
+extern uint32_t 	pciio_pio_read32(volatile uint32_t *addr);
+extern uint64_t 	pciio_pio_read64(volatile uint64_t *addr);
+extern void 		pciio_pio_write8(uint8_t val, volatile uint8_t *addr);
+extern void 		pciio_pio_write16(uint16_t val, volatile uint16_t *addr);
+extern void 		pciio_pio_write32(uint32_t val, volatile uint32_t *addr);
+extern void 		pciio_pio_write64(uint64_t val, volatile uint64_t *addr);
+#else /* !USE_PCI_PIO */
+__inline uint8_t pciio_pio_read8(volatile uint8_t *addr)
+{ 
+	return *addr; 
+}
+__inline uint16_t pciio_pio_read16(volatile uint16_t *addr)
+{
+	return *addr; 
+}
+__inline uint32_t pciio_pio_read32(volatile uint32_t *addr)
+{
+	return *addr; 
+}
+__inline uint64_t pciio_pio_read64(volatile uint64_t *addr)
+{
+	return *addr;
+}
+__inline void pciio_pio_write8(uint8_t val, volatile uint8_t *addr)
+{
+	*addr = val;
+}
+__inline void pciio_pio_write16(uint16_t val, volatile uint16_t *addr)
+{
+	*addr = val;
+}
+__inline void pciio_pio_write32(uint32_t val, volatile uint32_t *addr)
+{
+	*addr = val;
+}
+__inline void pciio_pio_write64(uint64_t val, volatile uint64_t *addr)
+{
+	*addr = val;
+}
+#endif /* USE_PCI_PIO */
+#endif
+
+/* Generic PCI dma interfaces */
+extern devfs_handle_t     pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap);
+
+/* Register/unregister PCI providers and get implementation handle */
+extern void             pciio_provider_register(devfs_handle_t provider, pciio_provider_t *pciio_fns);
+extern void             pciio_provider_unregister(devfs_handle_t provider);
+extern pciio_provider_t *pciio_provider_fns_get(devfs_handle_t provider);
+
+/* Generic pci slot information access interface */
+extern pciio_info_t     pciio_info_chk(devfs_handle_t vhdl);
+extern pciio_info_t     pciio_info_get(devfs_handle_t vhdl);
+extern void             pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info);
+extern devfs_handle_t     pciio_info_dev_get(pciio_info_t pciio_info);
+extern pciio_bus_t	pciio_info_bus_get(pciio_info_t pciio_info);
+extern pciio_slot_t     pciio_info_slot_get(pciio_info_t pciio_info);
+extern pciio_function_t	pciio_info_function_get(pciio_info_t pciio_info);
+extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info);
+extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info);
+extern devfs_handle_t     pciio_info_master_get(pciio_info_t pciio_info);
+extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info);
+extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info);
+extern error_handler_f *pciio_info_efunc_get(pciio_info_t);
+extern error_handler_arg_t *pciio_info_einfo_get(pciio_info_t);
+extern pciio_space_t	pciio_info_bar_space_get(pciio_info_t, int);
+extern iopaddr_t	pciio_info_bar_base_get(pciio_info_t, int);
+extern size_t		pciio_info_bar_size_get(pciio_info_t, int);
+extern iopaddr_t	pciio_info_rom_base_get(pciio_info_t);
+extern size_t		pciio_info_rom_size_get(pciio_info_t);
+
+extern int              pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
+extern int		pciio_dma_enabled(devfs_handle_t);
+
+#ifdef __cplusplus
+};
+#endif
+#endif				/* C or C++ */
+#endif				/* _ASM_SN_PCI_PCIIO_H */
diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h
new file mode 100644
index 000000000..00daf01d8
--- /dev/null
+++ b/include/asm-ia64/sn/pci/pciio_private.h
@@ -0,0 +1,100 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H
+#define _ASM_SN_PCI_PCIIO_PRIVATE_H
+
+#ifdef colin
+#include <ksys/xthread.h>
+#endif
+
+/*
+ * pciio_private.h -- private definitions for pciio
+ * PCI drivers should NOT include this file.
+ */
+
+#ident "sys/PCI/pciio_private: $Revision: 1.13 $"
+
+/*
+ * All PCI providers set up PIO using this information.
+ */
+struct pciio_piomap_s {
+    unsigned                pp_flags;	/* PCIIO_PIOMAP flags */
+    devfs_handle_t            pp_dev;	/* associated pci card */
+    pciio_slot_t            pp_slot;	/* which slot the card is in */
+    pciio_space_t           pp_space;	/* which address space */
+    iopaddr_t               pp_pciaddr;		/* starting offset of mapping */
+    size_t                  pp_mapsz;	/* size of this mapping */
+    caddr_t                 pp_kvaddr;	/* kernel virtual address to use */
+};
+
+/*
+ * All PCI providers set up DMA using this information.
+ */
+struct pciio_dmamap_s {
+    unsigned                pd_flags;	/* PCIIO_DMAMAP flags */
+    devfs_handle_t            pd_dev;	/* associated pci card */
+    pciio_slot_t            pd_slot;	/* which slot the card is in */
+};
+
+/*
+ * All PCI providers set up interrupts using this information.
+ */
+
+struct pciio_intr_s {
+    unsigned                pi_flags;	/* PCIIO_INTR flags */
+    devfs_handle_t            pi_dev;	/* associated pci card */
+    device_desc_t	    pi_dev_desc;	/* override device descriptor */
+    pciio_intr_line_t       pi_lines;	/* which interrupt line(s) */
+    intr_func_t             pi_func;	/* handler function (when connected) */
+    intr_arg_t              pi_arg;	/* handler parameter (when connected) */
+#ifdef IRIX
+    thd_int_t               pi_tinfo;	/* Thread info (when connected) */
+#endif
+    cpuid_t                 pi_mustruncpu; /* Where we must run. */
+    int			    pi_irq;	/* IRQ assigned */
+    int			    pi_cpu;	/* cpu assigned */
+};
+
+/* PCIIO_INTR (pi_flags) flags */
+#define PCIIO_INTR_CONNECTED	1	/* interrupt handler/thread has been connected */
+#define PCIIO_INTR_NOTHREAD	2	/* interrupt handler wants to be called at interrupt level */
+
+/*
+ * Each PCI Card has one of these.
+ */
+
+struct pciio_info_s {
+    char                   *c_fingerprint;
+    devfs_handle_t            c_vertex;	/* back pointer to vertex */
+    pciio_bus_t             c_bus;	/* which bus the card is in */
+    pciio_slot_t            c_slot;	/* which slot the card is in */
+    pciio_function_t        c_func;	/* which func (on multi-func cards) */
+    pciio_vendor_id_t       c_vendor;	/* PCI card "vendor" code */
+    pciio_device_id_t       c_device;	/* PCI card "device" code */
+    devfs_handle_t            c_master;	/* PCI bus provider */
+    arbitrary_info_t        c_mfast;	/* cached fastinfo from c_master */
+    pciio_provider_t       *c_pops;	/* cached provider from c_master */
+    error_handler_f        *c_efunc;	/* error handling function */
+    error_handler_arg_t     c_einfo;	/* first parameter for efunc */
+
+    struct {				/* state of BASE regs */
+	pciio_space_t		w_space;
+	iopaddr_t		w_base;
+	size_t			w_size;
+    }			    c_window[6];
+
+    unsigned		    c_rbase;	/* EXPANSION ROM base addr */
+    unsigned		    c_rsize;	/* EXPANSION ROM size (bytes) */
+
+    pciio_piospace_t	    c_piospace;	/* additional I/O spaces allocated */
+};
+
+extern char             pciio_info_fingerprint[];
+#endif				/* _ASM_SN_PCI_PCIIO_PRIVATE_H */
diff --git a/include/asm-ia64/sn/pio.h b/include/asm-ia64/sn/pio.h
new file mode 100644
index 000000000..72e2615d6
--- /dev/null
+++ b/include/asm-ia64/sn/pio.h
@@ -0,0 +1,155 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PIO_H
+#define _ASM_SN_PIO_H
+
+#include <linux/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iobus.h>
+
+/*
+ * pioaddr_t	- The kernel virtual address that a PIO can be done upon.
+ *		  Should probably be (volatile void*) but EVEREST would do PIO
+ *		  to long mostly, just cast for other sizes.
+ */
+
+typedef volatile ulong*	pioaddr_t;
+
+/*
+ * iopaddr_t	- the physical io space relative address (e.g. VME A16S 0x0800).
+ * iosapce_t	- specifies the io address space to be mapped/accessed.
+ * piomap_t	- the handle returned by pio_alloc() and used with all the pio
+ *		  access functions.
+ */
+
+
+typedef struct piomap {
+	uint		pio_bus;
+	uint		pio_adap;
+#ifdef IRIX
+	iospace_t	pio_iospace;
+#endif
+	int		pio_flag;
+	int		pio_reg;
+	char		pio_name[7];	/* to identify the mapped device */
+	struct piomap	*pio_next;	/* dlist to link active piomap's */
+	struct piomap	*pio_prev;	/* for debug and error reporting */
+#ifdef IRIX
+	void		(*pio_errfunc)(); /* Pointer to an error function */
+					  /* Used only for piomaps allocated
+					   * in user level vme driver     */
+#endif
+	iopaddr_t	pio_iopmask;	/* valid iop address bit mask */
+	iobush_t	pio_bushandle;	/* bus-level handle */
+} piomap_t;
+
+
+/* Macro to get/set PIO error function */
+#define	pio_seterrf(p,f)	(p)->pio_errfunc = (f)
+#define	pio_geterrf(p)		(p)->pio_errfunc
+
+
+/*
+ * pio_mapalloc() - allocates a handle that specifies a mapping from kernel
+ *		    virtual to io space. The returned handle piomap is used
+ *		    with the access functions to make sure that the mapping
+ *		    to the iospace exists.
+ * pio_mapfree()  - frees the mapping as specified in the piomap handle.
+ * pio_mapaddr()  - returns the kv address that maps to piomap'ed io address.
+ */
+#ifdef IRIX
+extern piomap_t	*pio_mapalloc(uint,uint,iospace_t*,int,char*);
+extern void	 pio_mapfree(piomap_t*);
+extern caddr_t	 pio_mapaddr(piomap_t*,iopaddr_t);
+extern piomap_t *pio_ioaddr(int, iobush_t, iopaddr_t, piomap_t *);
+
+/*
+ * PIO access functions.
+ */
+extern int  pio_badaddr(piomap_t*,iopaddr_t,int);
+extern int  pio_badaddr_val(piomap_t*,iopaddr_t,int,void*);
+extern int  pio_wbadaddr(piomap_t*,iopaddr_t,int);
+extern int  pio_wbadaddr_val(piomap_t*,iopaddr_t,int,int);
+extern int  pio_bcopyin(piomap_t*,iopaddr_t,void *,int, int, int);
+extern int  pio_bcopyout(piomap_t*,iopaddr_t,void *,int, int, int);
+
+
+/*
+ * PIO RMW functions using piomap.
+ */
+extern void pio_orb_rmw(piomap_t*, iopaddr_t, unsigned char);
+extern void pio_orh_rmw(piomap_t*, iopaddr_t, unsigned short);
+extern void pio_orw_rmw(piomap_t*, iopaddr_t, unsigned long);
+extern void pio_andb_rmw(piomap_t*, iopaddr_t, unsigned char);
+extern void pio_andh_rmw(piomap_t*, iopaddr_t, unsigned short); 
+extern void pio_andw_rmw(piomap_t*, iopaddr_t, unsigned long); 
+
+
+/*
+ * Old RMW function interface
+ */
+extern void orb_rmw(volatile void*, unsigned int);
+extern void orh_rmw(volatile void*, unsigned int);
+extern void orw_rmw(volatile void*, unsigned int);
+extern void andb_rmw(volatile void*, unsigned int);
+extern void andh_rmw(volatile void*, unsigned int);
+extern void andw_rmw(volatile void*, unsigned int);
+#endif	/* IRIX */
+
+
+/*
+ * piomap_t type defines
+ */
+
+#define PIOMAP_NTYPES	7
+
+#define PIOMAP_A16N	VME_A16NP
+#define PIOMAP_A16S	VME_A16S
+#define PIOMAP_A24N	VME_A24NP
+#define PIOMAP_A24S	VME_A24S
+#define PIOMAP_A32N	VME_A32NP
+#define PIOMAP_A32S	VME_A32S
+#define PIOMAP_A64	6
+
+#define PIOMAP_EISA_IO	0
+#define PIOMAP_EISA_MEM	1
+
+#define PIOMAP_PCI_IO	0
+#define PIOMAP_PCI_MEM	1
+#define PIOMAP_PCI_CFG	2
+#define PIOMAP_PCI_ID	3
+
+/* IBUS piomap types */
+#define PIOMAP_FCI	0
+
+/* dang gio piomap types */
+
+#define	PIOMAP_GIO32	0
+#define	PIOMAP_GIO64	1
+
+#define ET_MEM         	0
+#define ET_IO          	1
+#define LAN_RAM         2
+#define LAN_IO          3
+
+#define PIOREG_NULL	-1
+
+/* standard flags values for pio_map routines,
+ * including {xtalk,pciio}_piomap calls.
+ * NOTE: try to keep these in step with DMAMAP flags.
+ */
+#define PIOMAP_UNFIXED	0x0
+#define PIOMAP_FIXED	0x1
+#define PIOMAP_NOSLEEP	0x2
+#define	PIOMAP_INPLACE	0x4
+
+#define	PIOMAP_FLAGS	0x7
+
+#endif	/* _ASM_SN_PIO_H */
diff --git a/include/asm-ia64/sn/prio.h b/include/asm-ia64/sn/prio.h
new file mode 100644
index 000000000..1651390e0
--- /dev/null
+++ b/include/asm-ia64/sn/prio.h
@@ -0,0 +1,38 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PRIO_H
+#define _ASM_SN_PRIO_H
+
+/*
+ * Priority I/O function prototypes and macro definitions
+ */
+
+typedef long long bandwidth_t;
+
+/* These should be the same as FREAD/FWRITE */
+#define PRIO_READ_ALLOCATE	0x1
+#define PRIO_WRITE_ALLOCATE	0x2
+#define PRIO_READWRITE_ALLOCATE	(PRIO_READ_ALLOCATE | PRIO_WRITE_ALLOCATE)
+
+extern int prioSetBandwidth (int		/* fd */,
+                             int		/* alloc_type */,
+                             bandwidth_t	/* bytes_per_sec */,
+                             pid_t *		/* pid */);
+extern int prioGetBandwidth (int		/* fd */,
+                             bandwidth_t *	/* read_bw */,
+                             bandwidth_t *	/* write_bw */);
+extern int prioLock (pid_t *);
+extern int prioUnlock (void);
+
+/* Error returns */
+#define PRIO_SUCCESS     0
+#define PRIO_FAIL       -1 
+
+#endif /* _ASM_SN_PRIO_H */
diff --git a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h
new file mode 100644
index 000000000..fb9d0e192
--- /dev/null
+++ b/include/asm-ia64/sn/router.h
@@ -0,0 +1,18 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_ROUTER_H
+#define _ASM_SN_ROUTER_H
+
+#include <linux/config.h>
+#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#include <asm/sn/sn1/router.h>
+#endif
+
+#endif /* _ASM_SN_ROUTER_H */
diff --git a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h
new file mode 100644
index 000000000..b76cc1a67
--- /dev/null
+++ b/include/asm-ia64/sn/sgi.h
@@ -0,0 +1,238 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ */
+
+
+#ifndef _ASM_SN_SGI_H
+#define _ASM_SN_SGI_H
+
+#include <linux/config.h>
+#include <asm/sn/types.h>
+#include <asm/uaccess.h>		/* for copy_??_user */
+#include <linux/mm.h>
+#include <linux/devfs_fs_kernel.h>
+
+// This devfs stuff needs a better home .....
+
+struct directory_type
+{
+    struct devfs_entry *first;
+    struct devfs_entry *last;
+    unsigned int num_removable;
+};
+
+struct file_type
+{
+    unsigned long size;
+};
+
+struct device_type
+{
+    unsigned short major;
+    unsigned short minor;
+};
+
+struct fcb_type  /*  File, char, block type  */
+{
+    uid_t default_uid;
+    gid_t default_gid;
+    void *ops;
+    union 
+    {
+	struct file_type file;
+	struct device_type device;
+    }
+    u;
+    unsigned char auto_owner:1;
+    unsigned char aopen_notify:1;
+    unsigned char removable:1;  /*  Belongs in device_type, but save space   */
+    unsigned char open:1;       /*  Not entirely correct                     */
+};
+
+struct symlink_type
+{
+    unsigned int length;  /*  Not including the NULL-termimator  */
+    char *linkname;       /*  This is NULL-terminated            */
+};
+
+struct fifo_type
+{
+    uid_t uid;
+    gid_t gid;
+};
+
+struct devfs_entry
+{
+    void *info;
+    union 
+    {
+	struct directory_type dir;
+	struct fcb_type fcb;
+	struct symlink_type symlink;
+	struct fifo_type fifo;
+    }
+    u;
+    struct devfs_entry *prev;    /*  Previous entry in the parent directory  */
+    struct devfs_entry *next;    /*  Next entry in the parent directory      */
+    struct devfs_entry *parent;  /*  The parent directory                    */
+    struct devfs_entry *slave;   /*  Another entry to unregister             */
+    struct devfs_inode *first_inode;
+    struct devfs_inode *last_inode;
+    umode_t mode;
+    unsigned short namelen;  /*  I think 64k+ filenames are a way off...  */
+    unsigned char registered:1;
+    unsigned char show_unreg:1;
+    unsigned char hide:1;
+    unsigned char no_persistence /*:1*/;
+    char name[1];            /*  This is just a dummy: the allocated array is
+				 bigger. This is NULL-terminated  */
+};
+
+#define MIN(_a,_b)		((_a)<(_b)?(_a):(_b))
+
+typedef uint32_t app32_ptr_t;	/* needed by edt.h */
+typedef int64_t  __psint_t;	/* needed by klgraph.c */
+
+typedef enum { B_FALSE, B_TRUE } boolean_t;
+
+#define ctob(x)			((uint64_t)(x)*NBPC)
+#define btoc(x)			(((uint64_t)(x)+(NBPC-1))/NBPC)
+
+typedef __psunsigned_t nic_data_t;
+
+
+/*
+** Possible return values from graph routines.
+*/
+typedef enum graph_error_e {
+	GRAPH_SUCCESS,		/* 0 */
+	GRAPH_DUP,		/* 1 */
+	GRAPH_NOT_FOUND,	/* 2 */
+	GRAPH_BAD_PARAM,	/* 3 */
+	GRAPH_HIT_LIMIT,	/* 4 */
+	GRAPH_CANNOT_ALLOC,	/* 5 */
+	GRAPH_ILLEGAL_REQUEST,	/* 6 */
+	GRAPH_IN_USE		/* 7 */
+} graph_error_t;
+
+#define SV_FIFO         0x0             /* sv_t is FIFO type */
+#define SV_LIFO         0x2             /* sv_t is LIFO type */
+#define SV_PRIO         0x4             /* sv_t is PRIO type */
+#define SV_KEYED        0x6             /* sv_t is KEYED type */
+#define SV_DEFAULT      SV_FIFO
+
+
+#define MUTEX_DEFAULT	0x0		/* needed by mutex_init() calls */
+#define PZERO		25		/* needed by mutex_lock(), sv_wait()
+					 * psema() calls */
+
+#define sema_t  uint64_t		/* FIXME */
+#define KM_SLEEP   0x0000
+#define KM_NOSLEEP 0x0001		/* needed by kmem_alloc_node(), kmem_zalloc()
+					 * calls */
+#define VM_NOSLEEP 0x0001		/* needed kmem_alloc_node(), kmem_zalloc_node
+					 * calls */
+#define XG_WIDGET_PART_NUM      0xC102          /* KONA/xt_regs.h     XG_XT_PART_NUM_VALUE */
+
+#ifndef K1BASE
+#define K1BASE 0xA0000000
+#endif
+
+#ifndef TO_PHYS_MASK
+#define TO_PHYS_MASK 0x0000000fffffffff
+#endif
+
+typedef uint64_t vhandl_t;
+
+
+#ifndef NBPP
+#define NBPP 4096
+#endif
+
+#ifndef D_MP
+#define D_MP 1
+#endif
+
+#ifndef MAXDEVNAME
+#define MAXDEVNAME 256
+#endif
+
+#ifndef NBPC
+#define NBPC 0
+#endif
+
+#ifndef _PAGESZ
+#define _PAGESZ 4096
+#endif
+
+typedef uint64_t k_machreg_t;	/* needed by cmn_err.h */
+
+typedef uint64_t mrlock_t;	/* needed by devsupport.c */
+
+#define HUB_PIO_CONVEYOR 0x1
+#define CNODEID_NONE (cnodeid_t)-1
+#define XTALK_PCI_PART_NUM "030-1275-"
+#define kdebug 0
+
+
+#define COPYIN(a, b, c)		copy_from_user(b,a,c)
+#define COPYOUT(a, b, c)	copy_to_user(b,a,c)
+
+#define kvtophys(x)		(alenaddr_t) (x)
+#define POFFMASK		(NBPP - 1)
+#define poff(X)			((__psunsigned_t)(X) & POFFMASK)
+
+#define initnsema(a,b,c) 	sema_init(a,b)
+
+#define BZERO(a,b)		memset(a, 0, b)
+
+#define kern_malloc(x)	kmalloc(x, GFP_KERNEL)
+#define kern_free(x)	kfree(x)
+
+typedef cpuid_t cpu_cookie_t;
+#define CPU_NONE		-1
+
+
+#if defined(DISABLE_ASSERT)
+#define ASSERT(expr)
+#define ASSERT_ALWAYS(expr)
+#else
+#define ASSERT(expr)	\
+        if(!(expr)) { \
+		printk( "Assertion [%s] failed! %s:%s(line=%d)\n",\
+			#expr,__FILE__,__FUNCTION__,__LINE__); \
+		panic("Assertion panic\n"); 	\
+        }
+
+#define ASSERT_ALWAYS(expr)	\
+        if(!(expr)) { \
+		printk( "Assertion [%s] failed! %s:%s(line=%d)\n",\
+			#expr,__FILE__,__FUNCTION__,__LINE__); \
+		panic("Assertion always panic\n"); 	\
+        }
+#endif	/* DISABLE_ASSERT */
+
+/* These are defined as cmn_err() replacements */
+#define PRINT_WARNING(x...)	{ printk("WARNING : "); printk(x); }
+#define PRINT_NOTICE(x...)	{ printk("NOTICE : "); printk(x); }
+#define PRINT_ALERT(x...)	{ printk("ALERT : "); printk(x); }
+#define PRINT_PANIC		panic
+
+#define mutex_t int
+#define spinlock_init(x,name) mutex_init(x, MUTEX_DEFAULT, name);
+
+#ifdef CONFIG_SMP
+#define cpu_enabled(cpu)        (test_bit(cpu, &cpu_online_map))
+#else
+#define cpu_enabled(cpu)	(1)
+#endif
+
+#include <asm/sn/hack.h>	/* for now */
+
+#endif	/* _ASM_SN_SGI_H */
diff --git a/include/asm-ia64/sn/slotnum.h b/include/asm-ia64/sn/slotnum.h
new file mode 100644
index 000000000..9d48072c3
--- /dev/null
+++ b/include/asm-ia64/sn/slotnum.h
@@ -0,0 +1,24 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SLOTNUM_H
+#define _ASM_SN_SLOTNUM_H
+
+typedef	unsigned char slotid_t;
+
+#include <linux/config.h>
+#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/slotnum.h>
+#else
+
+#error <<BOMB! slotnum defined only for SN0 and SN1 >>
+
+#endif /* !CONFIG_SGI_IP35 && !CONFIG_IA64_SGI_SN1 */
+
+#endif /* _ASM_SN_SLOTNUM_H */
diff --git a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h
new file mode 100644
index 000000000..d5f6f7f93
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/addrs.h
@@ -0,0 +1,311 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_SN1_ADDRS_H
+#define _ASM_SN_SN1_ADDRS_H
+
+/*
+ * IP35 (on a TRex) Address map
+ *
+ * This file contains a set of definitions and macros which are used
+ * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
+ * and UNCAC) used by the IP35 architecture.  It also contains addresses
+ * for "major" statically locatable PROM/Kernel data structures, such as
+ * the partition table, the configuration data structure, etc.
+ * We make an implicit assumption that the processor using this file
+ * follows the R12K's provisions for specifying uncached attributes;
+ * should this change, the base registers may very well become processor-
+ * dependent.
+ *
+ * For more information on the address spaces, see the "Local Resources"
+ * chapter of the Hub specification.
+ *
+ * NOTE: This header file is included both by C and by assembler source
+ *	 files.  Please bracket any language-dependent definitions
+ *	 appropriately.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Some of the macros here need to be casted to appropriate types when used
+ * from C.  They definitely must not be casted from assembly language so we
+ * use some new ANSI preprocessor stuff to paste these on where needed.
+ */
+
+#if defined(_RUN_UNCACHED)
+#define CAC_BASE		0x9600000000000000
+#else
+#define CAC_BASE		0xa800000000000000
+#endif
+
+#ifdef Colin
+#define HSPEC_BASE		0x9000000000000000
+#define IO_BASE			0x9200000000000000
+#define MSPEC_BASE		0x9400000000000000
+#define UNCAC_BASE		0x9600000000000000
+#else
+#define HSPEC_BASE              0xc0000b0000000000
+#define HSPEC_SWIZ_BASE         0xc000030000000000
+#define IO_BASE                 0xc0000a0000000000
+#define IO_SWIZ_BASE            0xc000020000000000
+#define MSPEC_BASE              0xc000000000000000
+#define UNCAC_BASE              0xc000000000000000
+#endif
+
+#define TO_PHYS(x)		(	      ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)		(CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)		(UNCAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_MSPEC(x)		(MSPEC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_HSPEC(x)		(HSPEC_BASE | ((x) & TO_PHYS_MASK))
+
+
+/*
+ * The following couple of definitions will eventually need to be variables,
+ * since the amount of address space assigned to each node depends on
+ * whether the system is running in N-mode (more nodes with less memory)
+ * or M-mode (fewer nodes with more memory).  We expect that it will
+ * be a while before we need to make this decision dynamically, though,
+ * so for now we just use defines bracketed by an ifdef.
+ */
+
+#if defined(N_MODE)
+
+#define NODE_SIZE_BITS		32
+#define BWIN_SIZE_BITS		28
+
+#define NASID_BITS		8
+#define NASID_BITMASK		(0xffLL)
+#define NASID_SHFT		32
+#define NASID_META_BITS		1
+#define NASID_LOCAL_BITS	7
+
+#define BDDIR_UPPER_MASK	(UINT64_CAST 0x1ffffff << 4)
+#define BDECC_UPPER_MASK	(UINT64_CAST 0x1fffffff )
+
+#else /* !defined(N_MODE), assume that M-mode is desired */
+
+#define NODE_SIZE_BITS		33
+#define BWIN_SIZE_BITS		29
+
+#define NASID_BITMASK		(0x7fLL)
+#define NASID_BITS		7
+#define NASID_SHFT		33
+#define NASID_META_BITS		0
+#define NASID_LOCAL_BITS	7
+
+#define BDDIR_UPPER_MASK	(UINT64_CAST 0x3ffffff << 4)
+#define BDECC_UPPER_MASK	(UINT64_CAST 0x3fffffff)
+
+#endif /* defined(N_MODE) */
+
+#define NODE_ADDRSPACE_SIZE	(UINT64_CAST 1 << NODE_SIZE_BITS)
+
+#define NASID_MASK		(UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)		(int) ((UINT64_CAST (_pa) >>		\
+					NASID_SHFT) & NASID_BITMASK)
+
+#if _LANGUAGE_C && !defined(_STANDALONE)
+#ifndef REAL_HARDWARE
+#define NODE_SWIN_BASE(nasid, widget) RAW_NODE_SWIN_BASE(nasid, widget)
+#else
+#define NODE_SWIN_BASE(nasid, widget)					\
+	((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)		\
+	: RAW_NODE_SWIN_BASE(nasid, widget))
+#endif
+#else
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+#endif /* _LANGUAGE_C */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS		3
+#define BWIN_SIZE		(UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define	BWIN_SIZEMASK		(BWIN_SIZE - 1)
+#define	BWIN_WIDGET_MASK	0x7
+#define NODE_BWIN_BASE0(nasid)	(NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)	(NODE_BWIN_BASE0(nasid) + 	\
+			(UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
+
+#define	BWIN_WIDGETADDR(addr)	((addr) & BWIN_SIZEMASK)
+#define	BWIN_WINDOWNUM(addr)	(((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define	NODE_BWIN_ADDR(nasid, addr)	\
+		(((addr) >= NODE_BWIN_BASE0(nasid)) && \
+		 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+				BWIN_SIZE)))
+
+/*
+ * The following define the major position-independent aliases used
+ * in IP27.
+ *	CALIAS -- Varies in size, points to the first n bytes of memory
+ *		  	on the reader's node.
+ */
+
+#define CALIAS_BASE		CAC_BASE
+
+
+
+#define BRIDGE_REG_PTR(_base, _off)	((volatile bridgereg_t *) \
+	((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define SN0_WIDGET_BASE(_nasid, _wid)	(NODE_SWIN_BASE((_nasid), (_wid)))
+
+#if _LANGUAGE_C
+#define KERN_NMI_ADDR(nasid, slice)					\
+                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + 	\
+				  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
+#endif /* _LANGUAGE_C */
+
+
+/*
+ * needed by symmon so it needs to be outside #if PROM
+ * (see also POD_ELSCSIZE)
+ */
+#define IP27PROM_ELSC_BASE_A	PHYS_TO_K0(0x020e0000)
+#define IP27PROM_ELSC_BASE_B	PHYS_TO_K0(0x020e0800)
+#define IP27PROM_ELSC_BASE_C	PHYS_TO_K0(0x020e1000)
+#define IP27PROM_ELSC_BASE_D	PHYS_TO_K0(0x020e1800)
+#define IP27PROM_ELSC_SHFT	11
+#define IP27PROM_ELSC_SIZE	(1 << IP27PROM_ELSC_SHFT)
+
+#define FREEMEM_BASE		PHYS_TO_K0(0x4000000)
+
+#define IO6PROM_STACK_SHFT	14	/* stack per cpu */
+#define IO6PROM_STACK_SIZE	(1 << IO6PROM_STACK_SHFT)
+
+
+#define KL_UART_BASE	LOCAL_HSPEC(HSPEC_UART_0)	/* base of UART regs */
+#define KL_UART_CMD	LOCAL_HSPEC(HSPEC_UART_0)	/* UART command reg */
+#define KL_UART_DATA	LOCAL_HSPEC(HSPEC_UART_1)	/* UART data reg */
+
+#if !_LANGUAGE_ASSEMBLY
+/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
+ * CACHE_ERR_SP_PTR could either contain an address to the stack, or
+ * the stack could start at CACHE_ERR_SP_PTR
+ */
+#define CACHE_ERR_EFRAME	0x400
+
+#define CACHE_ERR_ECCFRAME	(CACHE_ERR_EFRAME + EF_SIZE)
+#define CACHE_ERR_SP_PTR	(0x1000 - 32)	/* why -32? TBD */
+#define CACHE_ERR_IBASE_PTR	(0x1000 - 40)
+#define CACHE_ERR_SP		(CACHE_ERR_SP_PTR - 16)
+#define CACHE_ERR_AREA_SIZE	(ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
+
+#endif	/* !_LANGUAGE_ASSEMBLY */
+
+/* Each CPU accesses UALIAS at a different physaddr, on 32k boundaries
+ * This determines the locations of the exception vectors
+ */
+#define UALIAS_FLIP_BASE	UALIAS_BASE
+#define UALIAS_FLIP_SHIFT	15
+#define UALIAS_FLIP_ADDR(_x)	((_x) ^ (cputoslice(getcpuid())<<UALIAS_FLIP_SHIFT))
+
+#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
+#define EX_HANDLER_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT)
+#endif
+#define EX_HANDLER_ADDR(nasid, slice)					\
+	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
+#define EX_HANDLER_SIZE		0x0400
+
+#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
+#define EX_FRAME_OFFSET(slice)	((slice) << UALIAS_FLIP_SHIFT | 0x400)
+#endif
+#define EX_FRAME_ADDR(nasid, slice)					\
+	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
+#define EX_FRAME_SIZE		0x0c00
+
+#define _ARCSPROM
+
+#ifdef _STANDALONE
+
+/*
+ * The PROM needs to pass the device base address and the
+ * device pci cfg space address to the device drivers during
+ * install. The COMPONENT->Key field is used for this purpose.
+ * Macros needed by IP27 device drivers to convert the
+ * COMPONENT->Key field to the respective base address.
+ * Key field looks as follows:
+ *
+ *  +----------------------------------------------------+
+ *  |devnasid | widget  |pciid |hubwidid|hstnasid | adap |
+ *  |   2     |   1     |  1   |   1    |    2    |   1  |
+ *  +----------------------------------------------------+
+ *  |         |         |      |        |         |      |
+ *  64        48        40     32       24        8      0
+ *
+ * These are used by standalone drivers till the io infrastructure
+ * is in place.
+ */
+
+#if _LANGUAGE_C
+
+#define uchar unsigned char
+
+#define KEY_DEVNASID_SHFT  48
+#define KEY_WIDID_SHFT	   40
+#define KEY_PCIID_SHFT	   32
+#define KEY_HUBWID_SHFT	   24
+#define KEY_HSTNASID_SHFT  8
+
+#define MK_SN0_KEY(nasid, widid, pciid) \
+			((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
+				((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
+				((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
+
+#define ADD_HUBWID_KEY(key,hubwid)\
+			(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
+
+#define ADD_HSTNASID_KEY(key,hstnasid)\
+			(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
+
+#define GET_DEVNASID_FROM_KEY(key)	((short)(key >> KEY_DEVNASID_SHFT))
+#define GET_WIDID_FROM_KEY(key)		((uchar)(key >> KEY_WIDID_SHFT))
+#define GET_PCIID_FROM_KEY(key)		((uchar)(key >> KEY_PCIID_SHFT))
+#define GET_HUBWID_FROM_KEY(key)	((uchar)(key >> KEY_HUBWID_SHFT))
+#define GET_HSTNASID_FROM_KEY(key)	((short)(key >> KEY_HSTNASID_SHFT))
+
+#define PCI_64_TARGID_SHFT		60
+
+#define GET_PCIBASE_FROM_KEY(key)  (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+					GET_WIDID_FROM_KEY(key))\
+					| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
+
+#define GET_PCICFGBASE_FROM_KEY(key) \
+			(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+			      GET_WIDID_FROM_KEY(key))\
+			| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
+
+#define GET_WIDBASE_FROM_KEY(key) \
+                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                              GET_WIDID_FROM_KEY(key)))
+
+#define PUT_INSTALL_STATUS(c,s)		c->Revision = s
+#define GET_INSTALL_STATUS(c)		c->Revision
+
+#endif /* LANGUAGE_C */
+
+#endif /* _STANDALONE */
+
+#endif /* _ASM_SN_SN1_ADDRS_H */
diff --git a/include/asm-ia64/sn/sn1/arch.h b/include/asm-ia64/sn/sn1/arch.h
new file mode 100644
index 000000000..94458112d
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/arch.h
@@ -0,0 +1,79 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_ARCH_H
+#define _ASM_SN_SN1_ARCH_H
+
+#if defined(N_MODE)
+#error "ERROR constants defined only for M-mode"
+#endif
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              128
+
+/*
+ * MAXCPUS refers to the maximum number of CPUs in a single kernel.
+ * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
+ */
+#define MAXCPUS                 512
+
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ * This is not necessarily the same as MAX_NASIDS.
+ */
+#define MAX_COMPACT_NODES       128
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define	MAX_REGIONS		64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined 
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS		MAX_REGIONS
+
+
+#define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
+
+/*
+ * Slot constants for IP35
+ */
+
+#define MAX_MEM_SLOTS    8                     /* max slots per node */
+
+#if defined(N_MODE)
+#error "N-mode not supported"
+#endif
+
+#define SLOT_SHIFT      	(30)
+#define SLOT_MIN_MEM_SIZE	(64*1024*1024)
+
+/*
+ * two PIs per bedrock, two CPUs per PI
+ */
+#define NUM_SUBNODES	2
+#define SUBNODE_SHFT	1
+#define SUBNODE_MASK	(0x1 << SUBNODE_SHFT)
+#define LOCALCPU_SHFT	0
+#define LOCALCPU_MASK	(0x1 << LOCALCPU_SHFT)
+#define SUBNODE(slice)	(((slice) & SUBNODE_MASK) >> SUBNODE_SHFT)
+#define LOCALCPU(slice)	(((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT)
+#define TO_SLICE(subn, local)	(((subn) << SUBNODE_SHFT) | \
+				 ((local) << LOCALCPU_SHFT))
+
+#endif /* _ASM_SN_SN1_ARCH_H */
diff --git a/include/asm-ia64/sn/sn1/bedrock.h b/include/asm-ia64/sn/sn1/bedrock.h
new file mode 100644
index 000000000..fa98dfd68
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/bedrock.h
@@ -0,0 +1,82 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_SN1_BEDROCK_H
+#define _ASM_SN_SN1_BEDROCK_H
+
+/* The secret password; used to release protection */
+#define HUB_PASSWORD		0x53474972756c6573ull
+
+#define CHIPID_HUB		0x3012
+#define CHIPID_ROUTER		0x3017
+
+#define BEDROCK_REV_1_0		1
+#define BEDROCK_REV_1_1		2
+
+#define MAX_HUB_PATH		80
+
+#include <linux/config.h>
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/arch.h>
+#include <asm/sn/sn1/addrs.h>
+#include <asm/sn/sn1/hubpi.h>
+#include <asm/sn/sn1/hubmd.h>
+#include <asm/sn/sn1/hubio.h>
+#include <asm/sn/sn1/hubni.h>
+#include <asm/sn/sn1/hublb.h>
+#include <asm/sn/sn1/hubxb.h>
+#include <asm/sn/sn1/hubpi_next.h>
+#include <asm/sn/sn1/hubmd_next.h>
+#include <asm/sn/sn1/hubio_next.h>
+#include <asm/sn/sn1/hubni_next.h>
+#include <asm/sn/sn1/hublb_next.h>
+#include <asm/sn/sn1/hubxb_next.h>
+
+#else /* ! CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+
+<< BOMB! CONFIG_SGI_IP35 is only defined for IP35 >>
+
+#endif /* defined(CONFIG_SGI_IP35) */
+
+/* Translation of uncached attributes */
+#define	UATTR_HSPEC	0
+#define	UATTR_IO	1
+#define	UATTR_MSPEC	2
+#define	UATTR_UNCAC	3
+
+#if _LANGUAGE_ASSEMBLY
+
+/*
+ * Get nasid into register, r (uses at)
+ */
+#define GET_NASID_ASM(r)				\
+	dli	r, LOCAL_HUB_ADDR(LB_REV_ID);	\
+	ld	r, (r);					\
+	and	r, LRI_NODEID_MASK;			\
+	dsrl	r, LRI_NODEID_SHFT
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
+#if _LANGUAGE_C
+
+#include <asm/sn/xtalk/xwidget.h>
+
+/* hub-as-widget iograph info, labelled by INFO_LBL_XWIDGET */
+typedef struct v_hub_s *v_hub_t;
+typedef uint64_t      rtc_time_t;
+
+struct nodepda_s;
+int hub_check_pci_equiv(void *addra, void *addrb);
+void capture_hub_stats(cnodeid_t, struct nodepda_s *);
+void init_hub_stats(cnodeid_t, struct nodepda_s *);
+
+#endif /* _LANGUAGE_C */
+
+#endif /* _ASM_SN_SN1_BEDROCK_H */
diff --git a/include/asm-ia64/sn/sn1/hubdev.h b/include/asm-ia64/sn/sn1/hubdev.h
new file mode 100644
index 000000000..63aecadf9
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubdev.h
@@ -0,0 +1,22 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_SN1_HUBDEV_H
+#define _ASM_SN_SN1_HUBDEV_H
+
+extern void hubdev_init(void);
+extern void hubdev_register(int (*attach_method)(devfs_handle_t));
+extern int hubdev_unregister(int (*attach_method)(devfs_handle_t));
+extern int hubdev_docallouts(devfs_handle_t hub);
+
+extern caddr_t hubdev_prombase_get(devfs_handle_t hub);
+extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub);
+
+#endif /* _ASM_SN_SN1_HUBDEV_H */
diff --git a/include/asm-ia64/sn/sn1/hubio.h b/include/asm-ia64/sn/sn1/hubio.h
new file mode 100644
index 000000000..523741108
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubio.h
@@ -0,0 +1,5017 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+/************************************************************************
+ *                                                                      *
+ *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
+ *                                                                      *
+ * This file is created by an automated script. Any (minimal) changes   *
+ * made manually to this  file should be made with care.                *
+ *                                                                      *
+ *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
+ *                                                                      *
+ ************************************************************************/
+
+
+#ifndef _ASM_SN_SN1_HUBIO_H
+#define _ASM_SN_SN1_HUBIO_H
+
+
+#define    IIO_WID                   0x00400000    /*
+                                                    * Crosstalk Widget
+                                                    * Identification This
+                                                    * register is also
+                                                    * accessible from
+                                                    * Crosstalk at
+                                                    * address 0x0.
+                                                    */
+
+
+
+#define    IIO_WSTAT                 0x00400008    /*
+                                                    * Crosstalk Widget
+                                                    * Status
+                                                    */
+
+
+
+#define    IIO_WCR                   0x00400020    /*
+                                                    * Crosstalk Widget
+                                                    * Control Register
+                                                    */
+
+
+
+#define    IIO_ILAPR                 0x00400100    /*
+                                                    * IO Local Access
+                                                    * Protection Register
+                                                    */
+
+
+
+#define    IIO_ILAPO                 0x00400108    /*
+                                                    * IO Local Access
+                                                    * Protection Override
+                                                    */
+
+
+
+#define    IIO_IOWA                  0x00400110    /*
+                                                    * IO Outbound Widget
+                                                    * Access
+                                                    */
+
+
+
+#define    IIO_IIWA                  0x00400118    /*
+                                                    * IO Inbound Widget
+                                                    * Access
+                                                    */
+
+
+
+#define    IIO_IIDEM                 0x00400120    /*
+                                                    * IO Inbound Device
+                                                    * Error Mask
+                                                    */
+
+
+
+#define    IIO_ILCSR                 0x00400128    /*
+                                                    * IO LLP Control and
+                                                    * Status Register
+                                                    */
+
+
+
+#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
+
+
+
+#define    IIO_IIDSR                 0x00400138    /*
+                                                    * IO Interrupt
+                                                    * Destination
+                                                    */
+
+
+
+#define    IIO_IGFX0                 0x00400140    /*
+                                                    * IO Graphics
+                                                    * Node-Widget Map 0
+                                                    */
+
+
+
+#define    IIO_IGFX1                 0x00400148    /*
+                                                    * IO Graphics
+                                                    * Node-Widget Map 1
+                                                    */
+
+
+
+#define    IIO_ISCR0                 0x00400150    /*
+                                                    * IO Scratch Register
+                                                    * 0
+                                                    */
+
+
+
+#define    IIO_ISCR1                 0x00400158    /*
+                                                    * IO Scratch Register
+                                                    * 1
+                                                    */
+
+
+
+#define    IIO_ITTE1                 0x00400160    /*
+                                                    * IO Translation
+                                                    * Table Entry 1
+                                                    */
+
+
+
+#define    IIO_ITTE2                 0x00400168    /*
+                                                    * IO Translation
+                                                    * Table Entry 2
+                                                    */
+
+
+
+#define    IIO_ITTE3                 0x00400170    /*
+                                                    * IO Translation
+                                                    * Table Entry 3
+                                                    */
+
+
+
+#define    IIO_ITTE4                 0x00400178    /*
+                                                    * IO Translation
+                                                    * Table Entry 4
+                                                    */
+
+
+
+#define    IIO_ITTE5                 0x00400180    /*
+                                                    * IO Translation
+                                                    * Table Entry 5
+                                                    */
+
+
+
+#define    IIO_ITTE6                 0x00400188    /*
+                                                    * IO Translation
+                                                    * Table Entry 6
+                                                    */
+
+
+
+#define    IIO_ITTE7                 0x00400190    /*
+                                                    * IO Translation
+                                                    * Table Entry 7
+                                                    */
+
+
+
+#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
+
+
+
+#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
+
+
+
+#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
+
+
+
+#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
+
+
+
+#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
+
+
+
+#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
+
+
+
+#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
+
+
+
+#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
+
+
+
+#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
+
+
+
+#define    IIO_IXCC                  0x004001E0    /*
+                                                    * IO Crosstalk Credit
+                                                    * Count Timeout
+                                                    */
+
+
+
+#define    IIO_IMEM                  0x004001E8    /*
+                                                    * IO Miscellaneous
+                                                    * Error Mask
+                                                    */
+
+
+
+#define    IIO_IXTT                  0x004001F0    /*
+                                                    * IO Crosstalk
+                                                    * Timeout Threshold
+                                                    */
+
+
+
+#define    IIO_IECLR                 0x004001F8    /*
+                                                    * IO Error Clear
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_IBCR                  0x00400200    /*
+                                                    * IO BTE Control
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_IXSM                  0x00400208    /*
+                                                    * IO Crosstalk
+                                                    * Spurious Message
+                                                    */
+
+
+
+#define    IIO_IXSS                  0x00400210    /*
+                                                    * IO Crosstalk
+                                                    * Spurious Sideband
+                                                    */
+
+
+
+#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
+
+
+
+#define    IIO_IIEPH1                0x00400220    /*
+                                                    * IO Incoming Error
+                                                    * Packet Header, Part
+                                                    * 1
+                                                    */
+
+
+
+#define    IIO_IIEPH2                0x00400228    /*
+                                                    * IO Incoming Error
+                                                    * Packet Header, Part
+                                                    * 2
+                                                    */
+
+
+
+#define    IIO_IPCA                  0x00400300    /*
+                                                    * IO PRB Counter
+                                                    * Adjust
+                                                    */
+
+
+
+#define    IIO_IPRTE0                0x00400308    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 0
+                                                    */
+
+
+
+#define    IIO_IPRTE1                0x00400310    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 1
+                                                    */
+
+
+
+#define    IIO_IPRTE2                0x00400318    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 2
+                                                    */
+
+
+
+#define    IIO_IPRTE3                0x00400320    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 3
+                                                    */
+
+
+
+#define    IIO_IPRTE4                0x00400328    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 4
+                                                    */
+
+
+
+#define    IIO_IPRTE5                0x00400330    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 5
+                                                    */
+
+
+
+#define    IIO_IPRTE6                0x00400338    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 6
+                                                    */
+
+
+
+#define    IIO_IPRTE7                0x00400340    /*
+                                                    * IO PIO Read Address
+                                                    * Table Entry 7
+                                                    */
+
+
+
+#define    IIO_IPDR                  0x00400388    /*
+                                                    * IO PIO Deallocation
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_ICDR                  0x00400390    /*
+                                                    * IO CRB Entry
+                                                    * Deallocation
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_IFDR                  0x00400398    /*
+                                                    * IO IOQ FIFO Depth
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_IIAP                  0x004003A0    /*
+                                                    * IO IIQ Arbitration
+                                                    * Parameters
+                                                    */
+
+
+
+#define    IIO_ICMR                  0x004003A8    /*
+                                                    * IO CRB Management
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_ICCR                  0x004003B0    /*
+                                                    * IO CRB Control
+                                                    * Register
+                                                    */
+
+
+
+#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
+
+
+
+#define    IIO_ICTP                  0x004003C0    /*
+                                                    * IO CRB Timeout
+                                                    * Prescalar
+                                                    */
+
+
+
+#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
+
+
+
+#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
+
+
+
+#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
+
+
+
+#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
+
+
+
+#define    IIO_ICRB1_A               0x00400420    /* IO CRB Entry 1_A       */
+
+
+
+#define    IIO_ICRB1_B               0x00400428    /* IO CRB Entry 1_B       */
+
+
+
+#define    IIO_ICRB1_C               0x00400430    /* IO CRB Entry 1_C       */
+
+
+
+#define    IIO_ICRB1_D               0x00400438    /* IO CRB Entry 1_D       */
+
+
+
+#define    IIO_ICRB2_A               0x00400440    /* IO CRB Entry 2_A       */
+
+
+
+#define    IIO_ICRB2_B               0x00400448    /* IO CRB Entry 2_B       */
+
+
+
+#define    IIO_ICRB2_C               0x00400450    /* IO CRB Entry 2_C       */
+
+
+
+#define    IIO_ICRB2_D               0x00400458    /* IO CRB Entry 2_D       */
+
+
+
+#define    IIO_ICRB3_A               0x00400460    /* IO CRB Entry 3_A       */
+
+
+
+#define    IIO_ICRB3_B               0x00400468    /* IO CRB Entry 3_B       */
+
+
+
+#define    IIO_ICRB3_C               0x00400470    /* IO CRB Entry 3_C       */
+
+
+
+#define    IIO_ICRB3_D               0x00400478    /* IO CRB Entry 3_D       */
+
+
+
+#define    IIO_ICRB4_A               0x00400480    /* IO CRB Entry 4_A       */
+
+
+
+#define    IIO_ICRB4_B               0x00400488    /* IO CRB Entry 4_B       */
+
+
+
+#define    IIO_ICRB4_C               0x00400490    /* IO CRB Entry 4_C       */
+
+
+
+#define    IIO_ICRB4_D               0x00400498    /* IO CRB Entry 4_D       */
+
+
+
+#define    IIO_ICRB5_A               0x004004A0    /* IO CRB Entry 5_A       */
+
+
+
+#define    IIO_ICRB5_B               0x004004A8    /* IO CRB Entry 5_B       */
+
+
+
+#define    IIO_ICRB5_C               0x004004B0    /* IO CRB Entry 5_C       */
+
+
+
+#define    IIO_ICRB5_D               0x004004B8    /* IO CRB Entry 5_D       */
+
+
+
+#define    IIO_ICRB6_A               0x004004C0    /* IO CRB Entry 6_A       */
+
+
+
+#define    IIO_ICRB6_B               0x004004C8    /* IO CRB Entry 6_B       */
+
+
+
+#define    IIO_ICRB6_C               0x004004D0    /* IO CRB Entry 6_C       */
+
+
+
+#define    IIO_ICRB6_D               0x004004D8    /* IO CRB Entry 6_D       */
+
+
+
+#define    IIO_ICRB7_A               0x004004E0    /* IO CRB Entry 7_A       */
+
+
+
+#define    IIO_ICRB7_B               0x004004E8    /* IO CRB Entry 7_B       */
+
+
+
+#define    IIO_ICRB7_C               0x004004F0    /* IO CRB Entry 7_C       */
+
+
+
+#define    IIO_ICRB7_D               0x004004F8    /* IO CRB Entry 7_D       */
+
+
+
+#define    IIO_ICRB8_A               0x00400500    /* IO CRB Entry 8_A       */
+
+
+
+#define    IIO_ICRB8_B               0x00400508    /* IO CRB Entry 8_B       */
+
+
+
+#define    IIO_ICRB8_C               0x00400510    /* IO CRB Entry 8_C       */
+
+
+
+#define    IIO_ICRB8_D               0x00400518    /* IO CRB Entry 8_D       */
+
+
+
+#define    IIO_ICRB9_A               0x00400520    /* IO CRB Entry 9_A       */
+
+
+
+#define    IIO_ICRB9_B               0x00400528    /* IO CRB Entry 9_B       */
+
+
+
+#define    IIO_ICRB9_C               0x00400530    /* IO CRB Entry 9_C       */
+
+
+
+#define    IIO_ICRB9_D               0x00400538    /* IO CRB Entry 9_D       */
+
+
+
+#define    IIO_ICRBA_A               0x00400540    /* IO CRB Entry A_A       */
+
+
+
+#define    IIO_ICRBA_B               0x00400548    /* IO CRB Entry A_B       */
+
+
+
+#define    IIO_ICRBA_C               0x00400550    /* IO CRB Entry A_C       */
+
+
+
+#define    IIO_ICRBA_D               0x00400558    /* IO CRB Entry A_D       */
+
+
+
+#define    IIO_ICRBB_A               0x00400560    /* IO CRB Entry B_A       */
+
+
+
+#define    IIO_ICRBB_B               0x00400568    /* IO CRB Entry B_B       */
+
+
+
+#define    IIO_ICRBB_C               0x00400570    /* IO CRB Entry B_C       */
+
+
+
+#define    IIO_ICRBB_D               0x00400578    /* IO CRB Entry B_D       */
+
+
+
+#define    IIO_ICRBC_A               0x00400580    /* IO CRB Entry C_A       */
+
+
+
+#define    IIO_ICRBC_B               0x00400588    /* IO CRB Entry C_B       */
+
+
+
+#define    IIO_ICRBC_C               0x00400590    /* IO CRB Entry C_C       */
+
+
+
+#define    IIO_ICRBC_D               0x00400598    /* IO CRB Entry C_D       */
+
+
+
+#define    IIO_ICRBD_A               0x004005A0    /* IO CRB Entry D_A       */
+
+
+
+#define    IIO_ICRBD_B               0x004005A8    /* IO CRB Entry D_B       */
+
+
+
+#define    IIO_ICRBD_C               0x004005B0    /* IO CRB Entry D_C       */
+
+
+
+#define    IIO_ICRBD_D               0x004005B8    /* IO CRB Entry D_D       */
+
+
+
+#define    IIO_ICRBE_A               0x004005C0    /* IO CRB Entry E_A       */
+
+
+
+#define    IIO_ICRBE_B               0x004005C8    /* IO CRB Entry E_B       */
+
+
+
+#define    IIO_ICRBE_C               0x004005D0    /* IO CRB Entry E_C       */
+
+
+
+#define    IIO_ICRBE_D               0x004005D8    /* IO CRB Entry E_D       */
+
+
+
+#define    IIO_ICSML                 0x00400600    /*
+                                                    * IO CRB Spurious
+                                                    * Message Low
+                                                    */
+
+
+
+#define    IIO_ICSMH                 0x00400608    /*
+                                                    * IO CRB Spurious
+                                                    * Message High
+                                                    */
+
+
+
+#define    IIO_IDBSS                 0x00400610    /*
+                                                    * IO Debug Submenu
+                                                    * Select
+                                                    */
+
+
+
+#define    IIO_IBLS0                 0x00410000    /*
+                                                    * IO BTE Length
+                                                    * Status 0
+                                                    */
+
+
+
+#define    IIO_IBSA0                 0x00410008    /*
+                                                    * IO BTE Source
+                                                    * Address 0
+                                                    */
+
+
+
+#define    IIO_IBDA0                 0x00410010    /*
+                                                    * IO BTE Destination
+                                                    * Address 0
+                                                    */
+
+
+
+#define    IIO_IBCT0                 0x00410018    /*
+                                                    * IO BTE Control
+                                                    * Terminate 0
+                                                    */
+
+
+
+#define    IIO_IBNA0                 0x00410020    /*
+                                                    * IO BTE Notification
+                                                    * Address 0
+                                                    */
+
+
+
+#define    IIO_IBIA0                 0x00410028    /*
+                                                    * IO BTE Interrupt
+                                                    * Address 0
+                                                    */
+
+
+
+#define    IIO_IBLS1                 0x00420000    /*
+                                                    * IO BTE Length
+                                                    * Status 1
+                                                    */
+
+
+
+#define    IIO_IBSA1                 0x00420008    /*
+                                                    * IO BTE Source
+                                                    * Address 1
+                                                    */
+
+
+
+#define    IIO_IBDA1                 0x00420010    /*
+                                                    * IO BTE Destination
+                                                    * Address 1
+                                                    */
+
+
+
+#define    IIO_IBCT1                 0x00420018    /*
+                                                    * IO BTE Control
+                                                    * Terminate 1
+                                                    */
+
+
+
+#define    IIO_IBNA1                 0x00420020    /*
+                                                    * IO BTE Notification
+                                                    * Address 1
+                                                    */
+
+
+
+#define    IIO_IBIA1                 0x00420028    /*
+                                                    * IO BTE Interrupt
+                                                    * Address 1
+                                                    */
+
+
+
+#define    IIO_IPCR                  0x00430000    /*
+                                                    * IO Performance
+                                                    * Control
+                                                    */
+
+
+
+#define    IIO_IPPR                  0x00430008    /*
+                                                    * IO Performance
+                                                    * Profiling
+                                                    */
+
+
+
+
+
+#ifdef _LANGUAGE_C
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register echoes some information from the         *
+ * LB_REV_ID register. It is available through Crosstalk as described   *
+ * above. The REV_NUM and MFG_NUM fields receive their values from      *
+ * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
+ * The PART_NUM field's value is the Crosstalk device ID number that    *
+ * Steve Miller assigned to the Bedrock chip.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_wid_u {
+	bdrkreg_t	ii_wid_regval;
+	struct	{
+		bdrkreg_t	w_rsvd_1		  :	 1;
+		bdrkreg_t	w_mfg_num		  :	11;
+		bdrkreg_t	w_part_num		  :	16;
+		bdrkreg_t	w_rev_num		  :	 4;
+		bdrkreg_t	w_rsvd			  :	32;
+	} ii_wid_fld_s;
+} ii_wid_u_t;
+
+#else
+
+typedef union ii_wid_u {
+	bdrkreg_t	ii_wid_regval;
+	struct  {
+		bdrkreg_t	w_rsvd                    :	32;
+		bdrkreg_t	w_rev_num                 :	 4;
+		bdrkreg_t	w_part_num                :	16;
+		bdrkreg_t	w_mfg_num                 :	11;
+		bdrkreg_t	w_rsvd_1                  :	 1;
+	} ii_wid_fld_s;
+} ii_wid_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  The fields in this register are set upon detection of an error      *
+ * and cleared by various mechanisms, as explained in the               *
+ * description.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_wstat_u {
+	bdrkreg_t	ii_wstat_regval;
+	struct	{
+		bdrkreg_t	w_pending		  :	 4;
+		bdrkreg_t	w_xt_crd_to		  :	 1;
+		bdrkreg_t	w_xt_tail_to		  :	 1;
+		bdrkreg_t	w_rsvd_3		  :	 3;
+		bdrkreg_t       w_tx_mx_rty               :      1;
+		bdrkreg_t	w_rsvd_2		  :	 6;
+		bdrkreg_t	w_llp_tx_cnt		  :	 8;
+		bdrkreg_t	w_rsvd_1		  :	 8;
+		bdrkreg_t	w_crazy			  :	 1;
+		bdrkreg_t	w_rsvd			  :	31;
+	} ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+#else
+
+typedef union ii_wstat_u {
+	bdrkreg_t	ii_wstat_regval;
+	struct  {
+		bdrkreg_t	w_rsvd                    :	31;
+		bdrkreg_t	w_crazy                   :	 1;
+		bdrkreg_t	w_rsvd_1                  :	 8;
+		bdrkreg_t	w_llp_tx_cnt              :	 8;
+		bdrkreg_t	w_rsvd_2                  :	 6;
+		bdrkreg_t	w_tx_mx_rty               :	 1;
+		bdrkreg_t	w_rsvd_3                  :	 3;
+		bdrkreg_t	w_xt_tail_to              :	 1;
+		bdrkreg_t	w_xt_crd_to               :	 1;
+		bdrkreg_t	w_pending                 :	 4;
+	} ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This is a read-write enabled register. It controls     *
+ * various aspects of the Crosstalk flow control.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_wcr_u {
+	bdrkreg_t	ii_wcr_regval;
+	struct	{
+		bdrkreg_t	w_wid			  :	 4;
+		bdrkreg_t	w_tag			  :	 1;
+		bdrkreg_t	w_rsvd_1		  :	 8;
+		bdrkreg_t	w_dst_crd		  :	 3;
+		bdrkreg_t	w_f_bad_pkt		  :	 1;
+		bdrkreg_t	w_dir_con		  :	 1;
+		bdrkreg_t	w_e_thresh		  :	 5;
+		bdrkreg_t	w_rsvd			  :	41;
+	} ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+#else
+
+typedef union ii_wcr_u {
+	bdrkreg_t	ii_wcr_regval;
+	struct  {
+		bdrkreg_t	w_rsvd                    :	41;
+		bdrkreg_t	w_e_thresh                :	 5;
+		bdrkreg_t	w_dir_con                 :	 1;
+		bdrkreg_t	w_f_bad_pkt               :	 1;
+		bdrkreg_t	w_dst_crd                 :	 3;
+		bdrkreg_t	w_rsvd_1                  :	 8;
+		bdrkreg_t	w_tag                     :	 1;
+		bdrkreg_t	w_wid                     :	 4;
+	} ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register's value is a bit vector that guards      *
+ * access to local registers within the II as well as to external       *
+ * Crosstalk widgets. Each bit in the register corresponds to a         *
+ * particular region in the system; a region consists of one, two or    *
+ * four nodes (depending on the value of the REGION_SIZE field in the   *
+ * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
+ * protection provided by this register applies to PIO read             *
+ * operations as well as PIO write operations. The II will perform a    *
+ * PIO read or write request only if the bit for the requestor's        *
+ * region is set; otherwise, the II will not perform the requested      *
+ * operation and will return an error response. When a PIO read or      *
+ * write request targets an external Crosstalk widget, then not only    *
+ * must the bit for the requestor's region be set in the ILAPR, but     *
+ * also the target widget's bit in the IOWA register must be set in     *
+ * order for the II to perform the requested operation; otherwise,      *
+ * the II will return an error response. Hence, the protection          *
+ * provided by the IOWA register supplements the protection provided    *
+ * by the ILAPR for requests that target external Crosstalk widgets.    *
+ * This register itself can be accessed only by the nodes whose         *
+ * region ID bits are enabled in this same register. It can also be     *
+ * accessed through the IAlias space by the local processors.           *
+ * The reset value of this register allows access by all nodes.         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union ii_ilapr_u {
+	bdrkreg_t	ii_ilapr_regval;
+	struct  {
+		bdrkreg_t	i_region                  :	64;
+	} ii_ilapr_fld_s;
+} ii_ilapr_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A write to this register of the 64-bit value           *
+ * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
+ * corresponding to the region of the requestor to be set (allow        *
+ * access). A write of any other value will be ignored. Access          *
+ * protection for this register is "SGIrules".                          *
+ * This register can also be accessed through the IAlias space.         *
+ * However, this access will not change the access permissions in the   *
+ * ILAPR.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ilapo_u {
+	bdrkreg_t	ii_ilapo_regval;
+	struct	{
+		bdrkreg_t	i_io_ovrride		  :	 9;
+		bdrkreg_t	i_rsvd			  :	55;
+	} ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+#else
+
+typedef union ii_ilapo_u {
+	bdrkreg_t	ii_ilapo_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	55;
+		bdrkreg_t	i_io_ovrride              :	 9;
+	} ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register qualifies all the PIO and Graphics writes launched    *
+ * from the Bedrock towards a widget.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iowa_u {
+	bdrkreg_t	ii_iowa_regval;
+	struct	{
+		bdrkreg_t	i_w0_oac		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+                bdrkreg_t       i_wx_oac                  :      8;
+		bdrkreg_t	i_rsvd			  :	48;
+	} ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+#else
+
+typedef union ii_iowa_u {
+	bdrkreg_t	ii_iowa_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	48;
+		bdrkreg_t	i_wx_oac                  :	 8;
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_w0_oac                  :	 1;
+	} ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the requests launched      *
+ * from a widget towards the Bedrock. This register is intended to be   *
+ * used by software in case of misbehaving widgets.                     *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iiwa_u {
+	bdrkreg_t	ii_iiwa_regval;
+	struct  {
+		bdrkreg_t	i_w0_iac                  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+		bdrkreg_t	i_wx_iac		  :	 8;
+		bdrkreg_t	i_rsvd			  :	48;
+	} ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+#else
+
+typedef union ii_iiwa_u {
+	bdrkreg_t	ii_iiwa_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	48;
+		bdrkreg_t	i_wx_iac		  :	 8;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+		bdrkreg_t	i_w0_iac		  :	 1;
+	} ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the operations launched    *
+ * from a widget towards the Bedrock. It allows individual access       *
+ * control for up to 8 devices per widget. A device refers to           *
+ * individual DMA master hosted by a widget.                            *
+ * The bits in each field of this register are cleared by the Bedrock   *
+ * upon detection of an error which requires the device to be           *
+ * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
+ * Crosstalk). Whether or not a device has access rights to this        *
+ * Bedrock is determined by an AND of the device enable bit in the      *
+ * appropriate field of this register and the corresponding bit in      *
+ * the Wx_IAC field (for the widget which this device belongs to).      *
+ * The bits in this field are set by writing a 1 to them. Incoming      *
+ * replies from Crosstalk are not subject to this access control        *
+ * mechanism.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iidem_u {
+	bdrkreg_t	ii_iidem_regval;
+	struct	{
+		bdrkreg_t	i_w8_dxs		  :	 8;
+		bdrkreg_t	i_w9_dxs		  :	 8;
+		bdrkreg_t	i_wa_dxs		  :	 8;
+		bdrkreg_t	i_wb_dxs		  :	 8;
+		bdrkreg_t	i_wc_dxs		  :	 8;
+		bdrkreg_t	i_wd_dxs		  :	 8;
+		bdrkreg_t	i_we_dxs		  :	 8;
+		bdrkreg_t	i_wf_dxs		  :	 8;
+	} ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+#else
+
+typedef union ii_iidem_u {
+	bdrkreg_t	ii_iidem_regval;
+	struct  {
+		bdrkreg_t	i_wf_dxs                  :	 8;
+		bdrkreg_t	i_we_dxs                  :	 8;
+		bdrkreg_t	i_wd_dxs                  :	 8;
+		bdrkreg_t	i_wc_dxs                  :	 8;
+		bdrkreg_t	i_wb_dxs                  :	 8;
+		bdrkreg_t	i_wa_dxs                  :	 8;
+		bdrkreg_t	i_w9_dxs                  :	 8;
+		bdrkreg_t	i_w8_dxs                  :	 8;
+	} ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the various programmable fields necessary    *
+ * for controlling and observing the LLP signals.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ilcsr_u {
+	bdrkreg_t	ii_ilcsr_regval;
+	struct  {
+		bdrkreg_t	i_nullto                  :	 6;
+		bdrkreg_t	i_rsvd_4		  :	 2;
+		bdrkreg_t	i_wrmrst		  :	 1;
+		bdrkreg_t	i_rsvd_3		  :	 1;
+		bdrkreg_t	i_llp_en		  :	 1;
+		bdrkreg_t	i_bm8			  :	 1;
+		bdrkreg_t	i_llp_stat		  :	 2;
+		bdrkreg_t	i_remote_power		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 1;
+		bdrkreg_t	i_maxrtry		  :	10;
+		bdrkreg_t	i_d_avail_sel		  :	 2;
+		bdrkreg_t	i_rsvd_1		  :	 4;
+		bdrkreg_t	i_maxbrst		  :	10;
+                bdrkreg_t       i_rsvd                    :     22;
+
+	} ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+#else
+
+typedef union ii_ilcsr_u {
+	bdrkreg_t	ii_ilcsr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	22;
+		bdrkreg_t	i_maxbrst		  :	10;
+		bdrkreg_t	i_rsvd_1		  :	 4;
+		bdrkreg_t	i_d_avail_sel		  :	 2;
+		bdrkreg_t	i_maxrtry		  :	10;
+		bdrkreg_t	i_rsvd_2		  :	 1;
+		bdrkreg_t	i_remote_power		  :	 1;
+		bdrkreg_t	i_llp_stat		  :	 2;
+		bdrkreg_t	i_bm8			  :	 1;
+		bdrkreg_t	i_llp_en		  :	 1;
+		bdrkreg_t	i_rsvd_3		  :	 1;
+		bdrkreg_t	i_wrmrst		  :	 1;
+		bdrkreg_t	i_rsvd_4		  :	 2;
+		bdrkreg_t	i_nullto		  :	 6;
+	} ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This is simply a status registers that monitors the LLP error       *
+ * rate.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_illr_u {
+	bdrkreg_t	ii_illr_regval;
+	struct	{
+		bdrkreg_t	i_sn_cnt		  :	16;
+		bdrkreg_t	i_cb_cnt		  :	16;
+		bdrkreg_t	i_rsvd			  :	32;
+	} ii_illr_fld_s;
+} ii_illr_u_t;
+
+#else
+
+typedef union ii_illr_u {
+	bdrkreg_t	ii_illr_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	32;
+		bdrkreg_t	i_cb_cnt                  :	16;
+		bdrkreg_t	i_sn_cnt                  :	16;
+	} ii_illr_fld_s;
+} ii_illr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  All II-detected non-BTE error interrupts are           *
+ * specified via this register.                                         *
+ * NOTE: The PI interrupt register address is hardcoded in the II. If   *
+ * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
+ * packet) to address offset 0x0180_0090 within the local register      *
+ * address space of PI0 on the node specified by the NODE field. If     *
+ * PI_ID==1, then the II sends the interrupt request to address         *
+ * offset 0x01A0_0090 within the local register address space of PI1    *
+ * on the node specified by the NODE field.                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iidsr_u {
+	bdrkreg_t	ii_iidsr_regval;
+	struct  {
+		bdrkreg_t	i_level                   :	 7;
+		bdrkreg_t	i_rsvd_4		  :	 1;
+		bdrkreg_t       i_pi_id                   :      1;
+		bdrkreg_t	i_node			  :	 8;
+		bdrkreg_t       i_rsvd_3                  :      7;
+		bdrkreg_t	i_enable		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_int_sent		  :	 1;
+		bdrkreg_t       i_rsvd_1                  :      3;
+		bdrkreg_t	i_pi0_forward_int	  :	 1;
+		bdrkreg_t	i_pi1_forward_int	  :	 1;
+		bdrkreg_t	i_rsvd			  :	30;
+	} ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+#else
+
+typedef union ii_iidsr_u {
+	bdrkreg_t	ii_iidsr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	30;
+		bdrkreg_t	i_pi1_forward_int	  :	 1;
+		bdrkreg_t	i_pi0_forward_int	  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_int_sent		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_enable		  :	 1;
+		bdrkreg_t	i_rsvd_3		  :	 7;
+		bdrkreg_t	i_node			  :	 8;
+		bdrkreg_t	i_pi_id			  :	 1;
+		bdrkreg_t	i_rsvd_4		  :	 1;
+		bdrkreg_t	i_level			  :	 7;
+	} ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_igfx0_u {
+	bdrkreg_t	ii_igfx0_regval;
+	struct	{
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t       i_pi_id                   :      1;
+		bdrkreg_t	i_n_num			  :	 8;
+		bdrkreg_t       i_rsvd_1                  :      3;
+		bdrkreg_t       i_p_num                   :      1;
+		bdrkreg_t       i_rsvd                    :     47;
+	} ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+#else
+
+typedef union ii_igfx0_u {
+	bdrkreg_t	ii_igfx0_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	47;
+		bdrkreg_t	i_p_num                   :	 1;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_n_num                   :	 8;
+		bdrkreg_t	i_pi_id                   :	 1;
+		bdrkreg_t	i_w_num                   :	 4;
+	} ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_igfx1_u {
+	bdrkreg_t	ii_igfx1_regval;
+	struct  {
+		bdrkreg_t	i_w_num                   :	 4;
+		bdrkreg_t	i_pi_id			  :	 1;
+		bdrkreg_t	i_n_num			  :	 8;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_p_num			  :	 1;
+		bdrkreg_t	i_rsvd			  :	47;
+	} ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+#else
+
+typedef union ii_igfx1_u {
+	bdrkreg_t	ii_igfx1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	47;
+		bdrkreg_t	i_p_num			  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_n_num			  :	 8;
+		bdrkreg_t	i_pi_id			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+	} ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union ii_iscr0_u {
+	bdrkreg_t	ii_iscr0_regval;
+	struct  {
+		bdrkreg_t	i_scratch                 :	64;
+	} ii_iscr0_fld_s;
+} ii_iscr0_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union ii_iscr1_u {
+	bdrkreg_t	ii_iscr1_regval;
+	struct  {
+		bdrkreg_t	i_scratch                 :	64;
+	} ii_iscr1_fld_s;
+} ii_iscr1_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte1_u {
+	bdrkreg_t	ii_itte1_regval;
+	struct  {
+		bdrkreg_t	i_offset                  :	 5;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_rsvd			  :	51;
+	} ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+#else
+
+typedef union ii_itte1_u {
+	bdrkreg_t	ii_itte1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_offset		  :	 5;
+	} ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte2_u {
+	bdrkreg_t	ii_itte2_regval;
+	struct	{
+		bdrkreg_t	i_offset		  :	 5;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+#else
+typedef union ii_itte2_u {
+	bdrkreg_t	ii_itte2_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	51;
+		bdrkreg_t	i_iosp                    :	 1;
+		bdrkreg_t	i_w_num                   :	 4;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_offset                  :	 5;
+	} ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte3_u {
+	bdrkreg_t	ii_itte3_regval;
+	struct  {
+		bdrkreg_t	i_offset                  :	 5;
+		bdrkreg_t       i_rsvd_1                  :      3;
+		bdrkreg_t       i_w_num                   :      4;
+		bdrkreg_t       i_iosp                    :      1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+#else
+
+typedef union ii_itte3_u {
+	bdrkreg_t	ii_itte3_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_offset		  :	 5;
+	} ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte4_u {
+	bdrkreg_t	ii_itte4_regval;
+	struct  {
+		bdrkreg_t	i_offset                  :	 5;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t       i_w_num                   :      4;
+		bdrkreg_t       i_iosp                    :      1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+#else
+
+typedef union ii_itte4_u {
+	bdrkreg_t	ii_itte4_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_offset		  :	 5;
+	} ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte5_u {
+	bdrkreg_t	ii_itte5_regval;
+	struct  {
+		bdrkreg_t	i_offset                  :	 5;
+		bdrkreg_t       i_rsvd_1                  :      3;
+		bdrkreg_t       i_w_num                   :      4;
+		bdrkreg_t       i_iosp                    :      1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+#else
+
+typedef union ii_itte5_u {
+	bdrkreg_t	ii_itte5_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_offset		  :	 5;
+	} ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte6_u {
+	bdrkreg_t	ii_itte6_regval;
+	struct  {
+		bdrkreg_t	i_offset                  :	 5;
+		bdrkreg_t       i_rsvd_1                  :      3;
+		bdrkreg_t       i_w_num                   :      4;
+		bdrkreg_t       i_iosp                    :      1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+#else
+
+typedef union ii_itte6_u {
+	bdrkreg_t	ii_itte6_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_offset		  :	 5;
+	} ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Bedrock Big Window to a 48-bit       *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Bedrock is thus the lower         *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_itte7_u {
+	bdrkreg_t	ii_itte7_regval;
+	struct  {
+		bdrkreg_t	i_offset                  :	 5;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t       i_w_num                   :      4;
+		bdrkreg_t       i_iosp                    :      1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+#else
+
+typedef union ii_itte7_u {
+	bdrkreg_t	ii_itte7_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_iosp			  :	 1;
+		bdrkreg_t	i_w_num			  :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_offset		  :	 5;
+	} ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprb0_u {
+	bdrkreg_t	ii_iprb0_regval;
+	struct  {
+		bdrkreg_t	i_c                       :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t       i_rsvd_2                  :      2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+#else
+
+typedef union ii_iprb0_u {
+	bdrkreg_t	ii_iprb0_regval;
+	struct	{
+		bdrkreg_t	i_mult_err		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_c			  :	 8;
+	} ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprb8_u {
+	bdrkreg_t	ii_iprb8_regval;
+	struct  {
+		bdrkreg_t	i_c                       :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t       i_rsvd_2                  :      2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t       i_rsvd_1                  :      2;
+		bdrkreg_t       i_m                       :      2;
+		bdrkreg_t       i_f                       :      1;
+		bdrkreg_t       i_of_cnt                  :      5;
+		bdrkreg_t       i_error                   :      1;
+		bdrkreg_t       i_rd_to                   :      1;
+		bdrkreg_t       i_spur_wr                 :      1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t       i_rsvd                    :     11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+#else
+
+
+typedef union ii_iprb8_u {
+	bdrkreg_t	ii_iprb8_regval;
+	struct	{
+		bdrkreg_t	i_mult_err		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_c			  :	 8;
+	} ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprb9_u {
+	bdrkreg_t	ii_iprb9_regval;
+	struct	{
+		bdrkreg_t	i_c			  :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+#else
+
+typedef union ii_iprb9_u {
+	bdrkreg_t	ii_iprb9_regval;
+	struct  {
+		bdrkreg_t	i_mult_err                :	 1;
+		bdrkreg_t	i_rsvd                    :	11;
+		bdrkreg_t	i_spur_rd                 :	 1;
+		bdrkreg_t	i_spur_wr                 :	 1;
+		bdrkreg_t	i_rd_to                   :	 1;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_of_cnt                  :	 5;
+		bdrkreg_t	i_f                       :	 1;
+		bdrkreg_t	i_m                       :	 2;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_nb                      :	14;
+		bdrkreg_t	i_rsvd_2                  :	 2;
+		bdrkreg_t	i_na                      :	14;
+		bdrkreg_t	i_c                       :	 8;
+	} ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprba_u {
+	bdrkreg_t	ii_iprba_regval;
+	struct  {
+		bdrkreg_t	i_c                       :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t       i_rsvd_2                  :      2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+#else
+
+typedef union ii_iprba_u {
+	bdrkreg_t	ii_iprba_regval;
+	struct	{
+		bdrkreg_t	i_mult_err		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_c			  :	 8;
+	} ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprbb_u {
+	bdrkreg_t	ii_iprbb_regval;
+	struct	{
+		bdrkreg_t	i_c			  :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+#else
+
+typedef union ii_iprbb_u {
+	bdrkreg_t	ii_iprbb_regval;
+	struct  {
+		bdrkreg_t	i_mult_err                :	 1;
+		bdrkreg_t	i_rsvd                    :	11;
+		bdrkreg_t	i_spur_rd                 :	 1;
+		bdrkreg_t	i_spur_wr                 :	 1;
+		bdrkreg_t	i_rd_to                   :	 1;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_of_cnt                  :	 5;
+		bdrkreg_t	i_f                       :	 1;
+		bdrkreg_t	i_m                       :	 2;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_nb                      :	14;
+		bdrkreg_t	i_rsvd_2                  :	 2;
+		bdrkreg_t	i_na                      :	14;
+		bdrkreg_t	i_c                       :	 8;
+	} ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprbc_u {
+	bdrkreg_t	ii_iprbc_regval;
+	struct	{
+		bdrkreg_t	i_c			  :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+#else
+
+typedef union ii_iprbc_u {
+	bdrkreg_t	ii_iprbc_regval;
+	struct  {
+		bdrkreg_t	i_mult_err                :	 1;
+		bdrkreg_t	i_rsvd                    :	11;
+		bdrkreg_t	i_spur_rd                 :	 1;
+		bdrkreg_t	i_spur_wr                 :	 1;
+		bdrkreg_t	i_rd_to                   :	 1;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_of_cnt                  :	 5;
+		bdrkreg_t	i_f                       :	 1;
+		bdrkreg_t	i_m                       :	 2;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_nb                      :	14;
+		bdrkreg_t	i_rsvd_2                  :	 2;
+		bdrkreg_t	i_na                      :	14;
+		bdrkreg_t	i_c                       :	 8;
+	} ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprbd_u {
+	bdrkreg_t	ii_iprbd_regval;
+	struct	{
+		bdrkreg_t	i_c			  :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+#else
+
+typedef union ii_iprbd_u {
+	bdrkreg_t	ii_iprbd_regval;
+	struct  {
+		bdrkreg_t	i_mult_err                :	 1;
+		bdrkreg_t	i_rsvd                    :	11;
+		bdrkreg_t	i_spur_rd                 :	 1;
+		bdrkreg_t	i_spur_wr                 :	 1;
+		bdrkreg_t	i_rd_to                   :	 1;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_of_cnt                  :	 5;
+		bdrkreg_t	i_f                       :	 1;
+		bdrkreg_t	i_m                       :	 2;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_nb                      :	14;
+		bdrkreg_t	i_rsvd_2                  :	 2;
+		bdrkreg_t	i_na                      :	14;
+		bdrkreg_t	i_c                       :	 8;
+	} ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprbe_u {
+	bdrkreg_t	ii_iprbe_regval;
+	struct	{
+		bdrkreg_t	i_c			  :	 8;
+		bdrkreg_t	i_na			  :	14;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_nb			  :	14;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_m			  :	 2;
+		bdrkreg_t	i_f			  :	 1;
+		bdrkreg_t	i_of_cnt		  :	 5;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rd_to			  :	 1;
+		bdrkreg_t	i_spur_wr		  :	 1;
+		bdrkreg_t	i_spur_rd		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_mult_err		  :	 1;
+	} ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+#else
+
+typedef union ii_iprbe_u {
+	bdrkreg_t	ii_iprbe_regval;
+	struct  {
+		bdrkreg_t	i_mult_err                :	 1;
+		bdrkreg_t	i_rsvd                    :	11;
+		bdrkreg_t	i_spur_rd                 :	 1;
+		bdrkreg_t	i_spur_wr                 :	 1;
+		bdrkreg_t	i_rd_to                   :	 1;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_of_cnt                  :	 5;
+		bdrkreg_t	i_f                       :	 1;
+		bdrkreg_t	i_m                       :	 2;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_nb                      :	14;
+		bdrkreg_t	i_rsvd_2                  :	 2;
+		bdrkreg_t	i_na                      :	14;
+		bdrkreg_t	i_c                       :	 8;
+	} ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Bedrock and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprbf_u {
+        bdrkreg_t       ii_iprbf_regval;
+        struct  {
+                bdrkreg_t       i_c                       :      8;
+                bdrkreg_t       i_na                      :     14;
+                bdrkreg_t       i_rsvd_2                  :      2;
+                bdrkreg_t       i_nb                      :     14;
+                bdrkreg_t       i_rsvd_1                  :      2;
+                bdrkreg_t       i_m                       :      2;
+                bdrkreg_t       i_f                       :      1;
+                bdrkreg_t       i_of_cnt                  :      5;
+                bdrkreg_t       i_error                   :      1;
+                bdrkreg_t       i_rd_to                   :      1;
+                bdrkreg_t       i_spur_wr                 :      1;
+                bdrkreg_t       i_spur_rd                 :      1;
+                bdrkreg_t       i_rsvd                    :     11;
+                bdrkreg_t       i_mult_err                :      1;
+        } ii_iprbe_fld_s;
+} ii_iprbf_u_t;
+
+#else
+
+typedef union ii_iprbf_u {
+	bdrkreg_t	ii_iprbf_regval;
+	struct  {
+		bdrkreg_t	i_mult_err                :	 1;
+		bdrkreg_t	i_rsvd                    :	11;
+		bdrkreg_t	i_spur_rd                 :	 1;
+		bdrkreg_t	i_spur_wr                 :	 1;
+		bdrkreg_t	i_rd_to                   :	 1;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_of_cnt                  :	 5;
+		bdrkreg_t	i_f                       :	 1;
+		bdrkreg_t	i_m                       :	 2;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_nb                      :	14;
+		bdrkreg_t	i_rsvd_2                  :	 2;
+		bdrkreg_t	i_na                      :	14;
+		bdrkreg_t	i_c                       :	 8;
+	} ii_iprbf_fld_s;
+} ii_iprbf_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register specifies the timeout value to use for monitoring     *
+ * Crosstalk credits which are used outbound to Crosstalk. An           *
+ * internal counter called the Crosstalk Credit Timeout Counter         *
+ * increments every 128 II clocks. The counter starts counting          *
+ * anytime the credit count drops below a threshold, and resets to      *
+ * zero (stops counting) anytime the credit count is at or above the    *
+ * threshold. The threshold is 1 credit in direct connect mode and 2    *
+ * in Crossbow connect mode. When the internal Crosstalk Credit         *
+ * Timeout Counter reaches the value programmed in this register, a     *
+ * Crosstalk Credit Timeout has occurred. The internal counter is not   *
+ * readable from software, and stops counting at its maximum value,     *
+ * so it cannot cause more than one interrupt.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ixcc_u {
+	bdrkreg_t	ii_ixcc_regval;
+	struct  {
+		bdrkreg_t	i_time_out                :	26;
+		bdrkreg_t	i_rsvd			  :	38;
+	} ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+#else
+
+typedef union ii_ixcc_u {
+	bdrkreg_t	ii_ixcc_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	38;
+		bdrkreg_t	i_time_out		  :	26;
+	} ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the PIO and DMA            *
+ * operations launched from widget 0 towards the Bedrock. In            *
+ * addition, it also qualifies accesses by the BTE streams.             *
+ * The bits in each field of this register are cleared by the Bedrock   *
+ * upon detection of an error which requires widget 0 or the BTE        *
+ * streams to be terminated. Whether or not widget x has access         *
+ * rights to this Bedrock is determined by an AND of the device         *
+ * enable bit in the appropriate field of this register and bit 0 in    *
+ * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
+ * them. Incoming replies from Crosstalk are not subject to this        *
+ * access control mechanism.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_imem_u {
+	bdrkreg_t	ii_imem_regval;
+	struct  {
+		bdrkreg_t	i_w0_esd                  :	 1;
+		bdrkreg_t	i_rsvd_3		  :	 3;
+		bdrkreg_t	i_b0_esd		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_b1_esd		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_clr_precise		  :	 1;
+		bdrkreg_t       i_rsvd                    :     51;
+	} ii_imem_fld_s;
+} ii_imem_u_t;
+
+#else
+
+typedef union ii_imem_u {
+	bdrkreg_t	ii_imem_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	51;
+		bdrkreg_t	i_clr_precise		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_b1_esd		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_b0_esd		  :	 1;
+		bdrkreg_t	i_rsvd_3		  :	 3;
+		bdrkreg_t	i_w0_esd		  :	 1;
+	} ii_imem_fld_s;
+} ii_imem_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register specifies the timeout value to use for   *
+ * monitoring Crosstalk tail flits coming into the Bedrock in the       *
+ * TAIL_TO field. An internal counter associated with this register     *
+ * is incremented every 128 II internal clocks (7 bits). The counter    *
+ * starts counting anytime a header micropacket is received and stops   *
+ * counting (and resets to zero) any time a micropacket with a Tail     *
+ * bit is received. Once the counter reaches the threshold value        *
+ * programmed in this register, it generates an interrupt to the        *
+ * processor that is programmed into the IIDSR. The counter saturates   *
+ * (does not roll over) at its maximum value, so it cannot cause        *
+ * another interrupt until after it is cleared.                         *
+ * The register also contains the Read Response Timeout values. The     *
+ * Prescalar is 23 bits, and counts II clocks. An internal counter      *
+ * increments on every II clock and when it reaches the value in the    *
+ * Prescalar field, all IPRTE registers with their valid bits set       *
+ * have their Read Response timers bumped. Whenever any of them match   *
+ * the value in the RRSP_TO field, a Read Response Timeout has          *
+ * occurred, and error handling occurs as described in the Error        *
+ * Handling section of this document.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ixtt_u {
+	bdrkreg_t	ii_ixtt_regval;
+	struct  {
+		bdrkreg_t	i_tail_to                 :	26;
+		bdrkreg_t	i_rsvd_1		  :	 6;
+		bdrkreg_t	i_rrsp_ps		  :	23;
+		bdrkreg_t	i_rrsp_to		  :	 5;
+		bdrkreg_t	i_rsvd			  :	 4;
+	} ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+#else
+
+typedef union ii_ixtt_u {
+	bdrkreg_t	ii_ixtt_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	 4;
+		bdrkreg_t	i_rrsp_to		  :	 5;
+		bdrkreg_t	i_rrsp_ps		  :	23;
+		bdrkreg_t	i_rsvd_1		  :	 6;
+		bdrkreg_t	i_tail_to		  :	26;
+	} ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing a 1 to the fields of this register clears the appropriate   *
+ * error bits in other areas of Bedrock_II. Note that when the          *
+ * E_PRB_x bits are used to clear error bits in PRB registers,          *
+ * SPUR_RD and SPUR_WR may persist, because they require additional     *
+ * action to clear them. See the IPRBx and IXSS Register                *
+ * specifications.                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ieclr_u {
+	bdrkreg_t	ii_ieclr_regval;
+	struct  {
+		bdrkreg_t	i_e_prb_0                 :	 1;
+		bdrkreg_t	i_rsvd			  :	 7;
+		bdrkreg_t	i_e_prb_8		  :	 1;
+		bdrkreg_t	i_e_prb_9		  :	 1;
+		bdrkreg_t	i_e_prb_a		  :	 1;
+		bdrkreg_t	i_e_prb_b		  :	 1;
+		bdrkreg_t	i_e_prb_c		  :	 1;
+		bdrkreg_t	i_e_prb_d		  :	 1;
+		bdrkreg_t	i_e_prb_e		  :	 1;
+		bdrkreg_t	i_e_prb_f		  :	 1;
+		bdrkreg_t	i_e_crazy		  :	 1;
+		bdrkreg_t	i_e_bte_0		  :	 1;
+		bdrkreg_t	i_e_bte_1		  :	 1;
+		bdrkreg_t	i_reserved_1		  :	 9;
+		bdrkreg_t	i_ii_internal		  :	 1;
+		bdrkreg_t	i_spur_rd_hdr		  :	 1;
+		bdrkreg_t	i_pi0_forward_int	  :	 1;
+		bdrkreg_t	i_pi1_forward_int	  :	 1;
+		bdrkreg_t       i_reserved                :     32;
+	} ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+#else
+
+typedef union ii_ieclr_u {
+	bdrkreg_t	ii_ieclr_regval;
+	struct	{
+		bdrkreg_t	i_reserved		  :	32;
+		bdrkreg_t	i_pi1_forward_int	  :	 1;
+		bdrkreg_t	i_pi0_forward_int	  :	 1;
+		bdrkreg_t	i_spur_rd_hdr		  :	 1;
+		bdrkreg_t	i_ii_internal		  :	 1;
+		bdrkreg_t	i_reserved_1		  :	 9;
+		bdrkreg_t	i_e_bte_1		  :	 1;
+		bdrkreg_t	i_e_bte_0		  :	 1;
+		bdrkreg_t	i_e_crazy		  :	 1;
+		bdrkreg_t	i_e_prb_f		  :	 1;
+		bdrkreg_t	i_e_prb_e		  :	 1;
+		bdrkreg_t	i_e_prb_d		  :	 1;
+		bdrkreg_t	i_e_prb_c		  :	 1;
+		bdrkreg_t	i_e_prb_b		  :	 1;
+		bdrkreg_t	i_e_prb_a		  :	 1;
+		bdrkreg_t	i_e_prb_9		  :	 1;
+		bdrkreg_t	i_e_prb_8		  :	 1;
+		bdrkreg_t	i_rsvd			  :	 7;
+		bdrkreg_t	i_e_prb_0		  :	 1;
+	} ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+#endif
+
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls both BTEs. SOFT_RESET is intended for        *
+ * recovery after an error. COUNT controls the total number of CRBs     *
+ * that both BTEs (combined) can use, which affects total BTE           *
+ * bandwidth.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibcr_u {
+	bdrkreg_t	ii_ibcr_regval;
+	struct  {
+		bdrkreg_t	i_count                   :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 4;
+		bdrkreg_t	i_soft_reset		  :	 1;
+		bdrkreg_t	i_rsvd			  :	55;
+	} ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+#else
+
+typedef union ii_ibcr_u {
+	bdrkreg_t	ii_ibcr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	55;
+		bdrkreg_t	i_soft_reset		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 4;
+		bdrkreg_t	i_count			  :	 4;
+	} ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the header of a spurious read response       *
+ * received from Crosstalk. A spurious read response is defined as a    *
+ * read response received by II from a widget for which (1) the SIDN    *
+ * has a value between 1 and 7, inclusive (II never sends requests to   *
+ * these widgets (2) there is no valid IPRTE register which             *
+ * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
+ * not the same as the widget recorded in the IPRTE register            *
+ * referenced by the TNUM. If this condition is true, and if the        *
+ * IXSS[VALID] bit is clear, then the header of the spurious read       *
+ * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
+ * errant header is thereby captured, and no further spurious read      *
+ * respones are captured until IXSS[VALID] is cleared by setting the    *
+ * appropriate bit in IECLR.Everytime a spurious read response is       *
+ * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
+ * message's SIDN field is set. This always happens, regarless of       *
+ * whether a header is captured. The programmer should check            *
+ * IXSM[SIDN] to determine which widget sent the spurious response,     *
+ * because there may be more than one SPUR_RD bit set in the PRB        *
+ * registers. The widget indicated by IXSM[SIDN] was the first          *
+ * spurious read response to be received since the last time            *
+ * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
+ * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
+ * spurious messages from other widets which were detected after the    *
+ * header was captured..                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ixsm_u {
+	bdrkreg_t	ii_ixsm_regval;
+	struct  {
+		bdrkreg_t	i_byte_en                 :	32;
+		bdrkreg_t	i_reserved		  :	 1;
+		bdrkreg_t	i_tag			  :	 3;
+		bdrkreg_t	i_alt_pactyp		  :	 4;
+		bdrkreg_t	i_bo			  :	 1;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_vbpm			  :	 1;
+		bdrkreg_t	i_gbr			  :	 1;
+		bdrkreg_t	i_ds			  :	 2;
+		bdrkreg_t	i_ct			  :	 1;
+		bdrkreg_t	i_tnum			  :	 5;
+		bdrkreg_t	i_pactyp		  :	 4;
+		bdrkreg_t	i_sidn			  :	 4;
+		bdrkreg_t	i_didn			  :	 4;
+	} ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+#else
+
+typedef union ii_ixsm_u {
+	bdrkreg_t	ii_ixsm_regval;
+	struct	{
+		bdrkreg_t	i_didn			  :	 4;
+		bdrkreg_t	i_sidn			  :	 4;
+		bdrkreg_t	i_pactyp		  :	 4;
+		bdrkreg_t	i_tnum			  :	 5;
+		bdrkreg_t	i_ct			  :	 1;
+		bdrkreg_t	i_ds			  :	 2;
+		bdrkreg_t	i_gbr			  :	 1;
+		bdrkreg_t	i_vbpm			  :	 1;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_bo			  :	 1;
+		bdrkreg_t	i_alt_pactyp		  :	 4;
+		bdrkreg_t	i_tag			  :	 3;
+		bdrkreg_t	i_reserved		  :	 1;
+		bdrkreg_t	i_byte_en		  :	32;
+	} ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the sideband bits of a spurious read         *
+ * response received from Crosstalk.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ixss_u {
+	bdrkreg_t	ii_ixss_regval;
+	struct  {
+		bdrkreg_t	i_sideband                :	 8;
+		bdrkreg_t	i_rsvd			  :	55;
+		bdrkreg_t	i_valid			  :	 1;
+	} ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+#else
+
+typedef union ii_ixss_u {
+	bdrkreg_t	ii_ixss_regval;
+	struct	{
+		bdrkreg_t	i_valid			  :	 1;
+		bdrkreg_t	i_rsvd			  :	55;
+		bdrkreg_t	i_sideband		  :	 8;
+	} ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register enables software to access the II LLP's test port.    *
+ * Refer to the LLP 2.5 documentation for an explanation of the test    *
+ * port. Software can write to this register to program the values      *
+ * for the control fields (TestErrCapture, TestClear, TestFlit,         *
+ * TestMask and TestSeed). Similarly, software can read from this       *
+ * register to obtain the values of the test port's status outputs      *
+ * (TestCBerr, TestValid and TestData).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ilct_u {
+	bdrkreg_t	ii_ilct_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	 9;
+		bdrkreg_t	i_test_err_capture        :	 1;
+		bdrkreg_t	i_test_clear              :	 1;
+		bdrkreg_t	i_test_flit               :	 3;
+		bdrkreg_t	i_test_cberr              :	 1;
+		bdrkreg_t	i_test_valid              :	 1;
+		bdrkreg_t	i_test_data               :	20;
+		bdrkreg_t	i_test_mask               :	 8;
+		bdrkreg_t	i_test_seed               :	20;
+	} ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+#else
+
+typedef union ii_ilct_u {
+	bdrkreg_t	ii_ilct_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	 9;
+		bdrkreg_t	i_test_err_capture	  :	 1;
+		bdrkreg_t	i_test_clear		  :	 1;
+		bdrkreg_t	i_test_flit		  :	 3;
+		bdrkreg_t	i_test_cberr		  :	 1;
+		bdrkreg_t	i_test_valid		  :	 1;
+		bdrkreg_t	i_test_data		  :	20;
+		bdrkreg_t	i_test_mask		  :	 8;
+		bdrkreg_t	i_test_seed		  :	20;
+	} ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  If the II detects an illegal incoming Duplonet packet (request or   *
+ * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
+ * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
+ * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
+ * and assigns a value to the ERR_TYPE field which indicates the        *
+ * specific nature of the error. The II recognizes four different       *
+ * types of errors: short request packets (ERR_TYPE==2), short reply    *
+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
+ * reply packets (ERR_TYPE==5). The encodings for these types of        *
+ * errors were chosen to be consistent with the same types of errors    *
+ * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
+ * the LB unit). If the II detects an illegal incoming Duplonet         *
+ * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
+ * the OVERRUN bit to indicate that a subsequent error has happened,    *
+ * and does nothing further.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iieph1_u {
+	bdrkreg_t	ii_iieph1_regval;
+	struct	{
+		bdrkreg_t	i_command		  :	 7;
+		bdrkreg_t	i_rsvd_5		  :	 1;
+		bdrkreg_t	i_suppl			  :	11;
+		bdrkreg_t	i_rsvd_4		  :	 1;
+		bdrkreg_t	i_source		  :	11;
+		bdrkreg_t	i_rsvd_3		  :	 1;
+		bdrkreg_t	i_err_type		  :	 4;
+		bdrkreg_t	i_rsvd_2		  :	 4;
+		bdrkreg_t	i_overrun		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_valid			  :	 1;
+		bdrkreg_t	i_rsvd			  :	19;
+	} ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+#else
+
+typedef union ii_iieph1_u {
+	bdrkreg_t	ii_iieph1_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	19;
+		bdrkreg_t	i_valid                   :	 1;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_overrun                 :	 1;
+		bdrkreg_t	i_rsvd_2                  :	 4;
+		bdrkreg_t	i_err_type                :	 4;
+		bdrkreg_t	i_rsvd_3                  :	 1;
+		bdrkreg_t	i_source                  :	11;
+		bdrkreg_t	i_rsvd_4                  :	 1;
+		bdrkreg_t	i_suppl                   :	11;
+		bdrkreg_t	i_rsvd_5                  :	 1;
+		bdrkreg_t	i_command                 :	 7;
+	} ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register holds the Address field from the header flit of an    *
+ * incoming erroneous Duplonet packet, along with the tail bit which    *
+ * accompanied this header flit. This register is essentially an        *
+ * extension of IIEPH1. Two registers were necessary because the 64     *
+ * bits available in only a single register were insufficient to        *
+ * capture the entire header flit of an erroneous packet.               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iieph2_u {
+	bdrkreg_t	ii_iieph2_regval;
+	struct  {
+		bdrkreg_t	i_address                 :	38;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_tail			  :	 1;
+		bdrkreg_t	i_rsvd			  :	23;
+	} ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+#else
+
+typedef union ii_iieph2_u {
+	bdrkreg_t	ii_iieph2_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	23;
+		bdrkreg_t	i_tail			  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_address		  :	38;
+	} ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a particular field in the           *
+ * corresponding widget's PRB entry to be adjusted up or down by 1.     *
+ * This counter should be used when recovering from error and reset     *
+ * conditions. Note that software would be capable of causing           *
+ * inadvertent overflow or underflow of these counters.                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ipca_u {
+	bdrkreg_t	ii_ipca_regval;
+	struct  {
+		bdrkreg_t	i_wid                     :	 4;
+		bdrkreg_t	i_adjust		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_field			  :	 2;
+		bdrkreg_t	i_rsvd			  :	54;
+	} ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+#else
+
+typedef union ii_ipca_u {
+	bdrkreg_t	ii_ipca_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	54;
+		bdrkreg_t	i_field			  :	 2;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_adjust		  :	 1;
+		bdrkreg_t	i_wid			  :	 4;
+	} ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte0_u {
+	bdrkreg_t	ii_iprte0_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t       i_vld                     :      1;
+	} ii_iprte0_fld_s;
+} ii_iprte0_u_t;
+
+#else
+
+typedef union ii_iprte0_u {
+	bdrkreg_t	ii_iprte0_regval;
+	struct	{
+		bdrkreg_t	i_vld			  :	 1;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+	} ii_iprte0_fld_s;
+} ii_iprte0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte1_u {
+	bdrkreg_t	ii_iprte1_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t       i_vld                     :      1;
+	} ii_iprte1_fld_s;
+} ii_iprte1_u_t;
+
+#else
+
+typedef union ii_iprte1_u {
+	bdrkreg_t	ii_iprte1_regval;
+	struct	{
+		bdrkreg_t	i_vld			  :	 1;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+	} ii_iprte1_fld_s;
+} ii_iprte1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte2_u {
+	bdrkreg_t	ii_iprte2_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t       i_vld                     :      1;
+	} ii_iprte2_fld_s;
+} ii_iprte2_u_t;
+
+#else
+
+typedef union ii_iprte2_u {
+	bdrkreg_t	ii_iprte2_regval;
+	struct	{
+		bdrkreg_t	i_vld			  :	 1;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+	} ii_iprte2_fld_s;
+} ii_iprte2_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte3_u {
+	bdrkreg_t	ii_iprte3_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_vld			  :	 1;
+	} ii_iprte3_fld_s;
+} ii_iprte3_u_t;
+
+#else
+
+typedef union ii_iprte3_u {
+	bdrkreg_t	ii_iprte3_regval;
+	struct	{
+		bdrkreg_t	i_vld			  :	 1;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+	} ii_iprte3_fld_s;
+} ii_iprte3_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte4_u {
+	bdrkreg_t	ii_iprte4_regval;
+	struct	{
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_vld			  :	 1;
+	} ii_iprte4_fld_s;
+} ii_iprte4_u_t;
+
+#else
+
+typedef union ii_iprte4_u {
+	bdrkreg_t	ii_iprte4_regval;
+	struct  {
+		bdrkreg_t	i_vld                     :	 1;
+		bdrkreg_t	i_to_cnt                  :	 5;
+		bdrkreg_t	i_widget                  :	 4;
+		bdrkreg_t	i_rsvd                    :	 2;
+		bdrkreg_t	i_source                  :	 8;
+		bdrkreg_t	i_init                    :	 3;
+		bdrkreg_t	i_addr                    :	38;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+	} ii_iprte4_fld_s;
+} ii_iprte4_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte5_u {
+	bdrkreg_t	ii_iprte5_regval;
+	struct	{
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_vld			  :	 1;
+	} ii_iprte5_fld_s;
+} ii_iprte5_u_t;
+
+#else
+
+typedef union ii_iprte5_u {
+	bdrkreg_t	ii_iprte5_regval;
+	struct  {
+		bdrkreg_t	i_vld                     :	 1;
+		bdrkreg_t	i_to_cnt                  :	 5;
+		bdrkreg_t	i_widget                  :	 4;
+		bdrkreg_t	i_rsvd                    :	 2;
+		bdrkreg_t	i_source                  :	 8;
+		bdrkreg_t	i_init                    :	 3;
+		bdrkreg_t	i_addr                    :	38;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+	} ii_iprte5_fld_s;
+} ii_iprte5_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte6_u {
+	bdrkreg_t	ii_iprte6_regval;
+	struct	{
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_vld			  :	 1;
+	} ii_iprte6_fld_s;
+} ii_iprte6_u_t;
+
+#else
+
+typedef union ii_iprte6_u {
+	bdrkreg_t	ii_iprte6_regval;
+	struct  {
+		bdrkreg_t	i_vld                     :	 1;
+		bdrkreg_t	i_to_cnt                  :	 5;
+		bdrkreg_t	i_widget                  :	 4;
+		bdrkreg_t	i_rsvd                    :	 2;
+		bdrkreg_t	i_source                  :	 8;
+		bdrkreg_t	i_init                    :	 3;
+		bdrkreg_t	i_addr                    :	38;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+	} ii_iprte6_fld_s;
+} ii_iprte6_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iprte7_u {
+        bdrkreg_t       ii_iprte7_regval;
+        struct  {
+                bdrkreg_t       i_rsvd_1                  :      3;
+                bdrkreg_t       i_addr                    :     38;
+                bdrkreg_t       i_init                    :      3;
+                bdrkreg_t       i_source                  :      8;
+                bdrkreg_t       i_rsvd                    :      2;
+                bdrkreg_t       i_widget                  :      4;
+                bdrkreg_t       i_to_cnt                  :      5;
+                bdrkreg_t       i_vld                     :      1;
+        } ii_iprte7_fld_s;
+} ii_iprte7_u_t;
+
+#else
+
+typedef union ii_iprte7_u {
+	bdrkreg_t	ii_iprte7_regval;
+	struct  {
+		bdrkreg_t	i_vld                     :	 1;
+		bdrkreg_t	i_to_cnt                  :	 5;
+		bdrkreg_t	i_widget                  :	 4;
+		bdrkreg_t	i_rsvd                    :	 2;
+		bdrkreg_t	i_source                  :	 8;
+		bdrkreg_t	i_init                    :	 3;
+		bdrkreg_t	i_addr                    :	38;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+	} ii_iprte7_fld_s;
+} ii_iprte7_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Bedrock_II contains a feature which did not exist in   *
+ * the Hub which automatically cleans up after a Read Response          *
+ * timeout, including deallocation of the IPRTE and recovery of IBuf    *
+ * space. The inclusion of this register in Bedrock is for backward     *
+ * compatibility                                                        *
+ * A write to this register causes an entry from the table of           *
+ * outstanding PIO Read Requests to be freed and returned to the        *
+ * stack of free entries. This register is used in handling the         *
+ * timeout errors that result in a PIO Reply never returning from       *
+ * Crosstalk.                                                           *
+ * Note that this register does not affect the contents of the IPRTE    *
+ * registers. The Valid bits in those registers have to be              *
+ * specifically turned off by software.                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ipdr_u {
+	bdrkreg_t	ii_ipdr_regval;
+	struct  {
+		bdrkreg_t	i_te                      :	 3;
+		bdrkreg_t	i_rsvd_1		  :	 1;
+		bdrkreg_t	i_pnd			  :	 1;
+		bdrkreg_t	i_init_rpcnt		  :	 1;
+		bdrkreg_t	i_rsvd			  :	58;
+	} ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+#else
+
+typedef union ii_ipdr_u {
+	bdrkreg_t	ii_ipdr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	58;
+		bdrkreg_t	i_init_rpcnt		  :	 1;
+		bdrkreg_t	i_pnd			  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 1;
+		bdrkreg_t	i_te			  :	 3;
+	} ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a CRB entry to be returned to the   *
+ * queue of free CRBs. The entry should have previously been cleared    *
+ * (mark bit) via backdoor access to the pertinent CRB entry. This      *
+ * register is used in the last step of handling the errors that are    *
+ * captured and marked in CRB entries.  Briefly: 1) first error for     *
+ * DMA write from a particular device, and first error for a            *
+ * particular BTE stream, lead to a marked CRB entry, and processor     *
+ * interrupt, 2) software reads the error information captured in the   *
+ * CRB entry, and presumably takes some corrective action, 3)           *
+ * software clears the mark bit, and finally 4) software writes to      *
+ * the ICDR register to return the CRB entry to the list of free CRB    *
+ * entries.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icdr_u {
+	bdrkreg_t	ii_icdr_regval;
+	struct  {
+		bdrkreg_t	i_crb_num                 :	 4;
+		bdrkreg_t	i_pnd			  :	 1;
+		bdrkreg_t       i_rsvd                    :     59;
+	} ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+#else
+
+typedef union ii_icdr_u {
+	bdrkreg_t	ii_icdr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	59;
+		bdrkreg_t	i_pnd			  :	 1;
+		bdrkreg_t	i_crb_num		  :	 4;
+	} ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides debug access to two FIFOs inside of II.      *
+ * Both IOQ_MAX* fields of this register contain the instantaneous      *
+ * depth (in units of the number of available entries) of the           *
+ * associated IOQ FIFO.  A read of this register will return the        *
+ * number of free entries on each FIFO at the time of the read.  So     *
+ * when a FIFO is idle, the associated field contains the maximum       *
+ * depth of the FIFO.  This register is writable for debug reasons      *
+ * and is intended to be written with the maximum desired FIFO depth    *
+ * while the FIFO is idle. Software must assure that II is idle when    *
+ * this register is written. If there are any active entries in any     *
+ * of these FIFOs when this register is written, the results are        *
+ * undefined.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ifdr_u {
+	bdrkreg_t	ii_ifdr_regval;
+	struct  {
+		bdrkreg_t	i_ioq_max_rq              :	 7;
+		bdrkreg_t	i_set_ioq_rq		  :	 1;
+		bdrkreg_t	i_ioq_max_rp		  :	 7;
+		bdrkreg_t	i_set_ioq_rp		  :	 1;
+		bdrkreg_t	i_rsvd			  :	48;
+	} ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+#else
+
+typedef union ii_ifdr_u {
+	bdrkreg_t	ii_ifdr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	48;
+		bdrkreg_t	i_set_ioq_rp		  :	 1;
+		bdrkreg_t	i_ioq_max_rp		  :	 7;
+		bdrkreg_t	i_set_ioq_rq		  :	 1;
+		bdrkreg_t	i_ioq_max_rq		  :	 7;
+	} ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the II to become sluggish in removing          *
+ * messages from its inbound queue (IIQ). This will cause messages to   *
+ * back up in either virtual channel. Disabling the "molasses" mode     *
+ * subsequently allows the II to be tested under stress. In the         *
+ * sluggish ("Molasses") mode, the localized effects of congestion      *
+ * can be observed.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iiap_u {
+        bdrkreg_t       ii_iiap_regval;
+        struct  {
+                bdrkreg_t       i_rq_mls                  :      6;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_rp_mls		  :	 6;
+		bdrkreg_t       i_rsvd                    :     50;
+        } ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+#else
+
+typedef union ii_iiap_u {
+	bdrkreg_t	ii_iiap_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	50;
+		bdrkreg_t	i_rp_mls                  :	 6;
+		bdrkreg_t	i_rsvd_1                  :	 2;
+		bdrkreg_t	i_rq_mls                  :	 6;
+	} ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows several parameters of CRB operation to be      *
+ * set. Note that writing to this register can have catastrophic side   *
+ * effects, if the CRB is not quiescent, i.e. if the CRB is             *
+ * processing protocol messages when the write occurs.                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icmr_u {
+	bdrkreg_t	ii_icmr_regval;
+	struct  {
+		bdrkreg_t	i_sp_msg                  :	 1;
+		bdrkreg_t	i_rd_hdr		  :	 1;
+		bdrkreg_t	i_rsvd_4		  :	 2;
+		bdrkreg_t	i_c_cnt			  :	 4;
+		bdrkreg_t	i_rsvd_3		  :	 4;
+		bdrkreg_t	i_clr_rqpd		  :	 1;
+		bdrkreg_t	i_clr_rppd		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_fc_cnt		  :	 4;
+		bdrkreg_t	i_crb_vld		  :	15;
+		bdrkreg_t	i_crb_mark		  :	15;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_precise		  :	 1;
+		bdrkreg_t	i_rsvd			  :	11;
+	} ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+#else
+
+typedef union ii_icmr_u {
+	bdrkreg_t	ii_icmr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	11;
+		bdrkreg_t	i_precise		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 2;
+		bdrkreg_t	i_crb_mark		  :	15;
+		bdrkreg_t	i_crb_vld		  :	15;
+		bdrkreg_t	i_fc_cnt		  :	 4;
+		bdrkreg_t	i_rsvd_2		  :	 2;
+		bdrkreg_t	i_clr_rppd		  :	 1;
+		bdrkreg_t	i_clr_rqpd		  :	 1;
+		bdrkreg_t	i_rsvd_3		  :	 4;
+		bdrkreg_t	i_c_cnt			  :	 4;
+		bdrkreg_t	i_rsvd_4		  :	 2;
+		bdrkreg_t	i_rd_hdr		  :	 1;
+		bdrkreg_t	i_sp_msg		  :	 1;
+	} ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows control of the table portion of the CRB        *
+ * logic via software. Control operations from this register have       *
+ * priority over all incoming Crosstalk or BTE requests.                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_iccr_u {
+	bdrkreg_t	ii_iccr_regval;
+	struct  {
+		bdrkreg_t	i_crb_num                 :	 4;
+		bdrkreg_t	i_rsvd_1		  :	 4;
+		bdrkreg_t	i_cmd			  :	 8;
+		bdrkreg_t	i_pending		  :	 1;
+		bdrkreg_t	i_rsvd			  :	47;
+	} ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+#else
+
+typedef union ii_iccr_u {
+	bdrkreg_t	ii_iccr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	47;
+		bdrkreg_t	i_pending		  :	 1;
+		bdrkreg_t	i_cmd			  :	 8;
+		bdrkreg_t	i_rsvd_1		  :	 4;
+		bdrkreg_t	i_crb_num		  :	 4;
+	} ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the maximum timeout value to be programmed.    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icto_u {
+	bdrkreg_t	ii_icto_regval;
+	struct  {
+		bdrkreg_t	i_timeout                 :	 8;
+		bdrkreg_t	i_rsvd			  :	56;
+	} ii_icto_fld_s;
+} ii_icto_u_t;
+
+#else
+
+typedef union ii_icto_u {
+	bdrkreg_t	ii_icto_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	56;
+		bdrkreg_t	i_timeout		  :	 8;
+	} ii_icto_fld_s;
+} ii_icto_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the timeout prescalar to be programmed. An     *
+ * internal counter is associated with this register. When the          *
+ * internal counter reaches the value of the PRESCALE field, the        *
+ * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
+ * field). The internal counter resets to zero, and then continues      *
+ * counting.                                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ictp_u {
+	bdrkreg_t	ii_ictp_regval;
+	struct  {
+		bdrkreg_t	i_prescale                :	24;
+		bdrkreg_t	i_rsvd			  :	40;
+	} ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+#else
+
+typedef union ii_ictp_u {
+	bdrkreg_t	ii_ictp_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	40;
+		bdrkreg_t	i_prescale		  :	24;
+	} ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, four   *
+ * registers (_A to _D) are required to read and write each entry.      *
+ * The CRB Entry registers can be conceptualized as rows and columns    *
+ * (illustrated in the table above). Each row contains the 4            *
+ * registers required for a single CRB Entry. The first doubleword      *
+ * (column) for each entry is labeled A, and the second doubleword      *
+ * (higher address) is labeled B, the third doubleword is labeled C,    *
+ * and the fourth doubleword is labeled D. All CRB entries have their   *
+ * addresses on a quarter cacheline aligned boundary.                   *
+ * Upon reset, only the following fields are initialized: valid         *
+ * (VLD), priority count, timeout, timeout valid, and context valid.    *
+ * All other bits should be cleared by software before use (after       *
+ * recovering any potential error state from before the reset).         *
+ * The following four tables summarize the format for the four          *
+ * registers that are used for each ICRB# Entry.                        *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icrb0_a_u {
+	bdrkreg_t	ii_icrb0_a_regval;
+	struct  {
+		bdrkreg_t	ia_iow                    :	 1;
+		bdrkreg_t	ia_vld			  :	 1;
+		bdrkreg_t	ia_addr			  :	38;
+		bdrkreg_t	ia_tnum			  :	 5;
+		bdrkreg_t	ia_sidn			  :	 4;
+		bdrkreg_t	ia_xt_err		  :	 1;
+		bdrkreg_t	ia_mark			  :	 1;
+		bdrkreg_t	ia_ln_uce		  :	 1;
+		bdrkreg_t	ia_errcode		  :	 3;
+		bdrkreg_t	ia_error		  :	 1;
+		bdrkreg_t	ia_stall__bte_1		  :	 1;
+		bdrkreg_t	ia_stall__bte_0		  :	 1;
+		bdrkreg_t       ia_rsvd                   :      6;
+	} ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+#else
+
+typedef union ii_icrb0_a_u {
+	bdrkreg_t	ii_icrb0_a_regval;
+	struct	{
+		bdrkreg_t	ia_rsvd			  :	 6;
+		bdrkreg_t	ia_stall__bte_0		  :	 1;
+		bdrkreg_t	ia_stall__bte_1		  :	 1;
+		bdrkreg_t	ia_error		  :	 1;
+		bdrkreg_t	ia_errcode		  :	 3;
+		bdrkreg_t	ia_ln_uce		  :	 1;
+		bdrkreg_t	ia_mark			  :	 1;
+		bdrkreg_t	ia_xt_err		  :	 1;
+		bdrkreg_t	ia_sidn			  :	 4;
+		bdrkreg_t	ia_tnum			  :	 5;
+		bdrkreg_t	ia_addr			  :	38;
+		bdrkreg_t	ia_vld			  :	 1;
+		bdrkreg_t	ia_iow			  :	 1;
+	} ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, four   *
+ * registers (_A to _D) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icrb0_b_u {
+	bdrkreg_t	ii_icrb0_b_regval;
+	struct	{
+		bdrkreg_t	ib_stall__intr		  :	 1;
+		bdrkreg_t	ib_stall_ib		  :	 1;
+		bdrkreg_t	ib_intvn		  :	 1;
+		bdrkreg_t	ib_wb			  :	 1;
+		bdrkreg_t	ib_hold			  :	 1;
+		bdrkreg_t	ib_ack			  :	 1;
+		bdrkreg_t	ib_resp			  :	 1;
+		bdrkreg_t	ib_ack_cnt		  :	11;
+		bdrkreg_t	ib_rsvd_1		  :	 7;
+		bdrkreg_t	ib_exc			  :	 5;
+		bdrkreg_t	ib_init			  :	 3;
+		bdrkreg_t	ib_imsg			  :	 8;
+		bdrkreg_t	ib_imsgtype		  :	 2;
+		bdrkreg_t	ib_use_old		  :	 1;
+		bdrkreg_t	ib_source		  :	12;
+		bdrkreg_t	ib_size			  :	 2;
+		bdrkreg_t	ib_ct			  :	 1;
+		bdrkreg_t	ib_bte_num		  :	 1;
+		bdrkreg_t	ib_rsvd			  :	 4;
+	} ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+#else
+
+typedef union ii_icrb0_b_u {
+	bdrkreg_t	ii_icrb0_b_regval;
+	struct  {
+		bdrkreg_t	ib_rsvd                   :	 4;
+		bdrkreg_t	ib_bte_num                :	 1;
+		bdrkreg_t	ib_ct                     :	 1;
+		bdrkreg_t	ib_size                   :	 2;
+		bdrkreg_t	ib_source                 :	12;
+		bdrkreg_t	ib_use_old                :	 1;
+		bdrkreg_t	ib_imsgtype               :	 2;
+		bdrkreg_t	ib_imsg                   :	 8;
+		bdrkreg_t	ib_init                   :	 3;
+		bdrkreg_t	ib_exc                    :	 5;
+		bdrkreg_t	ib_rsvd_1                 :	 7;
+		bdrkreg_t	ib_ack_cnt                :	11;
+		bdrkreg_t	ib_resp                   :	 1;
+		bdrkreg_t	ib_ack                    :	 1;
+		bdrkreg_t	ib_hold                   :	 1;
+		bdrkreg_t	ib_wb                     :	 1;
+		bdrkreg_t	ib_intvn                  :	 1;
+		bdrkreg_t	ib_stall_ib               :	 1;
+		bdrkreg_t	ib_stall__intr            :	 1;
+	} ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, four   *
+ * registers (_A to _D) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icrb0_c_u {
+	bdrkreg_t	ii_icrb0_c_regval;
+	struct	{
+		bdrkreg_t	ic_gbr			  :	 1;
+		bdrkreg_t	ic_resprqd		  :	 1;
+		bdrkreg_t	ic_bo			  :	 1;
+		bdrkreg_t	ic_suppl		  :	12;
+		bdrkreg_t	ic_pa_be		  :	34;
+		bdrkreg_t	ic_bte_op		  :	 1;
+		bdrkreg_t	ic_pr_psc		  :	 4;
+		bdrkreg_t	ic_pr_cnt		  :	 4;
+		bdrkreg_t	ic_sleep		  :	 1;
+		bdrkreg_t	ic_rsvd			  :	 5;
+	} ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+#else
+
+typedef union ii_icrb0_c_u {
+	bdrkreg_t	ii_icrb0_c_regval;
+	struct  {
+		bdrkreg_t	ic_rsvd                   :	 5;
+		bdrkreg_t	ic_sleep                  :	 1;
+		bdrkreg_t	ic_pr_cnt                 :	 4;
+		bdrkreg_t	ic_pr_psc                 :	 4;
+		bdrkreg_t	ic_bte_op                 :	 1;
+		bdrkreg_t	ic_pa_be                  :	34;
+		bdrkreg_t	ic_suppl                  :	12;
+		bdrkreg_t	ic_bo                     :	 1;
+		bdrkreg_t	ic_resprqd                :	 1;
+		bdrkreg_t	ic_gbr                    :	 1;
+	} ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, four   *
+ * registers (_A to _D) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icrb0_d_u {
+	bdrkreg_t	ii_icrb0_d_regval;
+	struct  {
+		bdrkreg_t	id_timeout                :	 8;
+		bdrkreg_t	id_context		  :	15;
+		bdrkreg_t	id_rsvd_1		  :	 1;
+		bdrkreg_t	id_tvld			  :	 1;
+		bdrkreg_t	id_cvld			  :	 1;
+		bdrkreg_t	id_rsvd			  :	38;
+	} ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+#else
+
+typedef union ii_icrb0_d_u {
+	bdrkreg_t	ii_icrb0_d_regval;
+	struct	{
+		bdrkreg_t	id_rsvd			  :	38;
+		bdrkreg_t	id_cvld			  :	 1;
+		bdrkreg_t	id_tvld			  :	 1;
+		bdrkreg_t	id_rsvd_1		  :	 1;
+		bdrkreg_t	id_context		  :	15;
+		bdrkreg_t	id_timeout		  :	 8;
+	} ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the lower 64 bits of the header of the       *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icsml_u {
+	bdrkreg_t	ii_icsml_regval;
+	struct  {
+		bdrkreg_t	i_tt_addr                 :	38;
+		bdrkreg_t	i_tt_ack_cnt		  :	11;
+		bdrkreg_t	i_newsuppl_ex		  :	11;
+		bdrkreg_t	i_reserved		  :	 3;
+		bdrkreg_t       i_overflow                :      1;
+	} ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+#else
+
+typedef union ii_icsml_u {
+	bdrkreg_t	ii_icsml_regval;
+	struct	{
+		bdrkreg_t	i_overflow		  :	 1;
+		bdrkreg_t	i_reserved		  :	 3;
+		bdrkreg_t	i_newsuppl_ex		  :	11;
+		bdrkreg_t	i_tt_ack_cnt		  :	11;
+		bdrkreg_t	i_tt_addr		  :	38;
+	} ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the microscopic state, all the inputs to     *
+ * the protocol table, captured with the spurious message. Valid when   *
+ * the SP_MSG bit in the ICMR register is set.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_icsmh_u {
+	bdrkreg_t	ii_icsmh_regval;
+	struct  {
+		bdrkreg_t	i_tt_vld                  :	 1;
+		bdrkreg_t	i_xerr			  :	 1;
+		bdrkreg_t	i_ft_cwact_o		  :	 1;
+		bdrkreg_t	i_ft_wact_o		  :	 1;
+		bdrkreg_t       i_ft_active_o             :      1;
+		bdrkreg_t	i_sync			  :	 1;
+		bdrkreg_t	i_mnusg			  :	 1;
+		bdrkreg_t	i_mnusz			  :	 1;
+		bdrkreg_t	i_plusz			  :	 1;
+		bdrkreg_t	i_plusg			  :	 1;
+		bdrkreg_t	i_tt_exc		  :	 5;
+		bdrkreg_t	i_tt_wb			  :	 1;
+		bdrkreg_t	i_tt_hold		  :	 1;
+		bdrkreg_t	i_tt_ack		  :	 1;
+		bdrkreg_t	i_tt_resp		  :	 1;
+		bdrkreg_t	i_tt_intvn		  :	 1;
+		bdrkreg_t	i_g_stall_bte1		  :	 1;
+		bdrkreg_t	i_g_stall_bte0		  :	 1;
+		bdrkreg_t	i_g_stall_il		  :	 1;
+		bdrkreg_t	i_g_stall_ib		  :	 1;
+		bdrkreg_t	i_tt_imsg		  :	 8;
+		bdrkreg_t	i_tt_imsgtype		  :	 2;
+		bdrkreg_t	i_tt_use_old		  :	 1;
+		bdrkreg_t	i_tt_respreqd		  :	 1;
+		bdrkreg_t	i_tt_bte_num		  :	 1;
+		bdrkreg_t	i_cbn			  :	 1;
+		bdrkreg_t	i_match			  :	 1;
+		bdrkreg_t	i_rpcnt_lt_34		  :	 1;
+		bdrkreg_t	i_rpcnt_ge_34		  :	 1;
+		bdrkreg_t	i_rpcnt_lt_18		  :	 1;
+		bdrkreg_t	i_rpcnt_ge_18		  :	 1;
+		bdrkreg_t       i_rpcnt_lt_2              :      1;
+		bdrkreg_t	i_rpcnt_ge_2		  :	 1;
+		bdrkreg_t	i_rqcnt_lt_18		  :	 1;
+		bdrkreg_t	i_rqcnt_ge_18		  :	 1;
+		bdrkreg_t	i_rqcnt_lt_2		  :	 1;
+		bdrkreg_t	i_rqcnt_ge_2		  :	 1;
+		bdrkreg_t	i_tt_device		  :	 7;
+		bdrkreg_t	i_tt_init		  :	 3;
+		bdrkreg_t	i_reserved		  :	 5;
+	} ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+#else
+
+typedef union ii_icsmh_u {
+	bdrkreg_t	ii_icsmh_regval;
+	struct	{
+		bdrkreg_t	i_reserved		  :	 5;
+		bdrkreg_t	i_tt_init		  :	 3;
+		bdrkreg_t	i_tt_device		  :	 7;
+		bdrkreg_t	i_rqcnt_ge_2		  :	 1;
+		bdrkreg_t	i_rqcnt_lt_2		  :	 1;
+		bdrkreg_t	i_rqcnt_ge_18		  :	 1;
+		bdrkreg_t	i_rqcnt_lt_18		  :	 1;
+		bdrkreg_t	i_rpcnt_ge_2		  :	 1;
+		bdrkreg_t	i_rpcnt_lt_2		  :	 1;
+		bdrkreg_t	i_rpcnt_ge_18		  :	 1;
+		bdrkreg_t	i_rpcnt_lt_18		  :	 1;
+		bdrkreg_t	i_rpcnt_ge_34		  :	 1;
+		bdrkreg_t	i_rpcnt_lt_34		  :	 1;
+		bdrkreg_t	i_match			  :	 1;
+		bdrkreg_t	i_cbn			  :	 1;
+		bdrkreg_t	i_tt_bte_num		  :	 1;
+		bdrkreg_t	i_tt_respreqd		  :	 1;
+		bdrkreg_t	i_tt_use_old		  :	 1;
+		bdrkreg_t	i_tt_imsgtype		  :	 2;
+		bdrkreg_t	i_tt_imsg		  :	 8;
+		bdrkreg_t	i_g_stall_ib		  :	 1;
+		bdrkreg_t	i_g_stall_il		  :	 1;
+		bdrkreg_t	i_g_stall_bte0		  :	 1;
+		bdrkreg_t	i_g_stall_bte1		  :	 1;
+		bdrkreg_t	i_tt_intvn		  :	 1;
+		bdrkreg_t	i_tt_resp		  :	 1;
+		bdrkreg_t	i_tt_ack		  :	 1;
+		bdrkreg_t	i_tt_hold		  :	 1;
+		bdrkreg_t	i_tt_wb			  :	 1;
+		bdrkreg_t	i_tt_exc		  :	 5;
+		bdrkreg_t	i_plusg			  :	 1;
+		bdrkreg_t	i_plusz			  :	 1;
+		bdrkreg_t	i_mnusz			  :	 1;
+		bdrkreg_t	i_mnusg			  :	 1;
+		bdrkreg_t	i_sync			  :	 1;
+		bdrkreg_t	i_ft_active_o		  :	 1;
+		bdrkreg_t	i_ft_wact_o		  :	 1;
+		bdrkreg_t	i_ft_cwact_o		  :	 1;
+		bdrkreg_t	i_xerr			  :	 1;
+		bdrkreg_t	i_tt_vld		  :	 1;
+	} ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+#endif
+
+
+/************************************************************************
+ *                                                                      *
+ *  The Bedrock DEBUG unit provides a 3-bit selection signal to the     *
+ * II unit, thus allowing a choice of one set of debug signal outputs   *
+ * from a menu of 8 options. Each option is limited to 32 bits in       *
+ * size. There are more signals of interest than can be accommodated    *
+ * in this 8*32 framework, so the IDBSS register has been defined to    *
+ * extend the range of choices available. For each menu option          *
+ * available to the DEBUG unit, the II provides a "submenu" of          *
+ * several options. The value of the SUBMENU field in the IDBSS         *
+ * register selects the desired submenu. Hence, the particular debug    *
+ * signals provided by the II are determined by the 3-bit selection     *
+ * signal from the DEBUG unit and the value of the SUBMENU field        *
+ * within the IDBSS register. For a detailed description of the         *
+ * available menus and submenus for II debug signals, refer to the      *
+ * documentation in ii_interface.doc..                                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LIITLE_ENDIAN
+
+typedef union ii_idbss_u {
+	bdrkreg_t	ii_idbss_regval;
+	struct  {
+		bdrkreg_t	i_submenu                 :	 3;
+		bdrkreg_t	i_rsvd			  :	61;
+	} ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+#else
+
+typedef union ii_idbss_u {
+	bdrkreg_t	ii_idbss_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	61;
+		bdrkreg_t	i_submenu		  :	 3;
+	} ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LIITLE_ENDIAN
+
+typedef union ii_ibls0_u {
+	bdrkreg_t	ii_ibls0_regval;
+	struct	{
+		bdrkreg_t	i_length		  :	16;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_busy			  :	 1;
+		bdrkreg_t       i_rsvd                    :     43;
+	} ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+#else
+
+typedef union ii_ibls0_u {
+	bdrkreg_t	ii_ibls0_regval;
+	struct  {
+		bdrkreg_t	i_rsvd                    :	43;
+		bdrkreg_t	i_busy                    :	 1;
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_error                   :	 1;
+		bdrkreg_t	i_length                  :	16;
+	} ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibsa0_u {
+	bdrkreg_t	ii_ibsa0_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t       i_rsvd                    :     24;
+	} ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+#else
+
+typedef union ii_ibsa0_u {
+	bdrkreg_t	ii_ibsa0_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	24;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+	} ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibda0_u {
+	bdrkreg_t	ii_ibda0_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd			  :	24;
+	} ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+#else
+
+typedef union ii_ibda0_u {
+	bdrkreg_t	ii_ibda0_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	24;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+	} ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibct0_u {
+	bdrkreg_t	ii_ibct0_regval;
+	struct  {
+		bdrkreg_t	i_zerofill                :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_notify		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t       i_poison                  :      1;
+		bdrkreg_t       i_rsvd                    :     55;
+	} ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+#else
+
+typedef union ii_ibct0_u {
+	bdrkreg_t	ii_ibct0_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	55;
+		bdrkreg_t	i_poison		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_notify		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_zerofill		  :	 1;
+	} ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibna0_u {
+	bdrkreg_t	ii_ibna0_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd			  :	24;
+	} ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+#else
+
+typedef union ii_ibna0_u {
+	bdrkreg_t	ii_ibna0_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	24;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+	} ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibia0_u {
+	bdrkreg_t	ii_ibia0_regval;
+	struct  {
+		bdrkreg_t	i_pi_id                   :	 1;
+		bdrkreg_t	i_node_id		  :	 8;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+		bdrkreg_t	i_level			  :	 7;
+		bdrkreg_t       i_rsvd                    :     41;
+	} ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+#else
+
+typedef union ii_ibia0_u {
+	bdrkreg_t	ii_ibia0_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	41;
+		bdrkreg_t	i_level			  :	 7;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+		bdrkreg_t	i_node_id		  :	 8;
+		bdrkreg_t	i_pi_id			  :	 1;
+	} ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibls1_u {
+	bdrkreg_t	ii_ibls1_regval;
+	struct  {
+		bdrkreg_t	i_length                  :	16;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_busy			  :	 1;
+		bdrkreg_t       i_rsvd                    :     43;
+	} ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+#else
+
+typedef union ii_ibls1_u {
+	bdrkreg_t	ii_ibls1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	43;
+		bdrkreg_t	i_busy			  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_error			  :	 1;
+		bdrkreg_t	i_length		  :	16;
+	} ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibsa1_u {
+	bdrkreg_t	ii_ibsa1_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd			  :	24;
+	} ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+#else
+
+typedef union ii_ibsa1_u {
+	bdrkreg_t	ii_ibsa1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	24;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+	} ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibda1_u {
+	bdrkreg_t	ii_ibda1_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd			  :	24;
+	} ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+#else
+
+typedef union ii_ibda1_u {
+	bdrkreg_t	ii_ibda1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	24;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+	} ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibct1_u {
+	bdrkreg_t	ii_ibct1_regval;
+	struct  {
+		bdrkreg_t	i_zerofill                :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_notify		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_poison		  :	 1;
+		bdrkreg_t	i_rsvd			  :	55;
+	} ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+#else
+
+typedef union ii_ibct1_u {
+	bdrkreg_t	ii_ibct1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	55;
+		bdrkreg_t	i_poison		  :	 1;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+		bdrkreg_t	i_notify		  :	 1;
+		bdrkreg_t	i_rsvd_2		  :	 3;
+		bdrkreg_t	i_zerofill		  :	 1;
+	} ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibna1_u {
+	bdrkreg_t	ii_ibna1_regval;
+	struct  {
+		bdrkreg_t	i_rsvd_1                  :	 7;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t       i_rsvd                    :     24;
+	} ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+#else
+
+typedef union ii_ibna1_u {
+	bdrkreg_t	ii_ibna1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	24;
+		bdrkreg_t	i_addr			  :	33;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+	} ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ibia1_u {
+	bdrkreg_t	ii_ibia1_regval;
+	struct  {
+		bdrkreg_t	i_pi_id                   :	 1;
+		bdrkreg_t	i_node_id		  :	 8;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+		bdrkreg_t	i_level			  :	 7;
+		bdrkreg_t	i_rsvd			  :	41;
+	} ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+#else
+
+typedef union ii_ibia1_u {
+	bdrkreg_t	ii_ibia1_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	41;
+		bdrkreg_t	i_level			  :	 7;
+		bdrkreg_t	i_rsvd_1		  :	 7;
+		bdrkreg_t	i_node_id		  :	 8;
+		bdrkreg_t	i_pi_id			  :	 1;
+	} ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register defines the resources that feed information into      *
+ * the two performance counters located in the IO Performance           *
+ * Profiling Register. There are 17 different quantities that can be    *
+ * measured. Given these 17 different options, the two performance      *
+ * counters have 15 of them in common; menu selections 0 through 0xE    *
+ * are identical for each performance counter. As for the other two     *
+ * options, one is available from one performance counter and the       *
+ * other is available from the other performance counter. Hence, the    *
+ * II supports all 17*16=272 possible combinations of quantities to     *
+ * measure.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ipcr_u {
+	bdrkreg_t	ii_ipcr_regval;
+	struct  {
+		bdrkreg_t	i_ippr0_c                 :	 4;
+		bdrkreg_t	i_ippr1_c		  :	 4;
+		bdrkreg_t	i_icct			  :	 8;
+		bdrkreg_t       i_rsvd                    :     48;
+	} ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+#else
+
+typedef union ii_ipcr_u {
+	bdrkreg_t	ii_ipcr_regval;
+	struct	{
+		bdrkreg_t	i_rsvd			  :	48;
+		bdrkreg_t	i_icct			  :	 8;
+		bdrkreg_t	i_ippr1_c		  :	 4;
+		bdrkreg_t	i_ippr0_c		  :	 4;
+	} ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ii_ippr_u {
+	bdrkreg_t	ii_ippr_regval;
+	struct  {
+		bdrkreg_t	i_ippr0                   :	32;
+		bdrkreg_t	i_ippr1			  :	32;
+	} ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+#else
+
+typedef union ii_ippr_u {
+	bdrkreg_t	ii_ippr_regval;
+	struct	{
+		bdrkreg_t	i_ippr1			  :	32;
+		bdrkreg_t	i_ippr0			  :	32;
+	} ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+#endif
+
+
+
+
+
+
+#endif /* _LANGUAGE_C */
+
+/************************************************************************
+ *                                                                      *
+ * The following defines which were not formed into structures are      *
+ * probably indentical to another register, and the name of the         *
+ * register is provided against each of these registers. This           *
+ * information needs to be checked carefully                            *
+ *                                                                      *
+ *           IIO_ICRB1_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB1_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB1_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB1_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB2_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB2_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB2_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB2_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB3_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB3_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB3_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB3_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB4_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB4_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB4_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB4_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB5_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB5_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB5_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB5_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB6_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB6_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB6_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB6_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB7_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB7_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB7_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB7_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB8_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB8_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB8_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB8_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB9_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB9_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB9_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB9_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBA_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBA_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBA_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBA_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBB_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBB_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBB_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBB_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBC_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBC_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBC_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBC_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBD_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBD_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBD_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBD_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBE_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBE_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBE_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBE_D                IIO_ICRB0_D                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+/************************************************************************
+ *                                                                      *
+ *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+
+#endif /* _ASM_SN_SN1_HUBIO_H */
diff --git a/include/asm-ia64/sn/sn1/hubio_next.h b/include/asm-ia64/sn/sn1/hubio_next.h
new file mode 100644
index 000000000..52c0eab54
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubio_next.h
@@ -0,0 +1,714 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBIO_NEXT_H
+#define _ASM_SN_SN1_HUBIO_NEXT_H
+
+/*
+ * Slightly friendlier names for some common registers.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_IGFX_0 		IIO_IGFX0
+#define IIO_IGFX_1 		IIO_IGFX1
+#define IIO_IBCT_0		IIO_IBCT0
+#define IIO_IBCT_1		IIO_IBCT1
+#define IIO_IBLS_0		IIO_IBLS0
+#define IIO_IBLS_1		IIO_IBLS1
+#define IIO_IBSA_0		IIO_IBSA0
+#define IIO_IBSA_1		IIO_IBSA1
+#define IIO_IBDA_0		IIO_IBDA0
+#define IIO_IBDA_1		IIO_IBDA1
+#define IIO_IBNA_0		IIO_IBNA0
+#define IIO_IBNA_1		IIO_IBNA1
+#define IIO_IBIA_0		IIO_IBIA0
+#define IIO_IBIA_1		IIO_IBIA1
+#define IIO_IOPRB_0		IIO_IPRB0
+#define IIO_PRTE_0      	IIO_IPRTE0        /* PIO Read address table entry 0 */
+#define IIO_PRTE(_x)    	(IIO_PRTE_0 + (8 * (_x)))
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+#define IIO_LLP_CB_MAX  0xffff	/* in ILLR CB_CNT, Max Check Bit errors */
+#define IIO_LLP_SN_MAX  0xffff	/* in ILLR SN_CNT, Max Sequence Number errors */
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/* names used in hub_diags.c; carried over from SN0 */
+#define IIO_BASE_BTE0   IIO_IBLS_0		
+#define IIO_BASE_BTE1   IIO_IBLS_1		
+#if 0
+#define IIO_BASE        IIO_WID
+#define IIO_BASE_PERF   IIO_IPCR   /* IO Performance Control */
+#define IIO_PERF_CNT    IIO_IPPR   /* IO Performance Profiling */
+#endif
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_W_NUM_BITS	4	/* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK	((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT	0
+#define IIO_IGFX_PI_NUM_BITS	1	/* size of PI num field */
+#define IIO_IGFX_PI_NUM_MASK	((1<<IIO_IGFX_PI_NUM_BITS)-1)
+#define IIO_IGFX_PI_NUM_SHIFT	4
+#define IIO_IGFX_N_NUM_BITS	8	/* size of node num field */
+#define IIO_IGFX_N_NUM_MASK	((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT	5
+#define IIO_IGFX_P_NUM_BITS	1	/* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK	((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT	16
+#define IIO_IGFX_INIT(widget, pi, node, cpu)				(\
+	(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |	 \
+	(((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|	 \
+	(((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |	 \
+	(((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
+
+
+/* Scratch registers (all bits available) */
+#define IIO_SCRATCH_REG0        IIO_ISCR0
+#define IIO_SCRATCH_REG1        IIO_ISCR1
+#define IIO_SCRATCH_MASK        0xffffffffffffffff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000000000001
+#define IIO_SCRATCH_BIT0_1      0x0000000000000002
+#define IIO_SCRATCH_BIT0_2      0x0000000000000004
+#define IIO_SCRATCH_BIT0_3      0x0000000000000008
+#define IIO_SCRATCH_BIT0_4      0x0000000000000010
+#define IIO_SCRATCH_BIT0_5      0x0000000000000020
+#define IIO_SCRATCH_BIT0_6      0x0000000000000040
+#define IIO_SCRATCH_BIT0_7      0x0000000000000080
+#define IIO_SCRATCH_BIT0_8      0x0000000000000100
+#define IIO_SCRATCH_BIT0_9      0x0000000000000200
+#define IIO_SCRATCH_BIT0_A      0x0000000000000400
+
+#define IIO_SCRATCH_BIT1_0      0x0000000000000001
+#define IIO_SCRATCH_BIT1_1      0x0000000000000002
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the hub, we've
+ * redefined big window 7 as small window 0.
+ XXX does this still apply for SN1??
+ */
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
+
+#define ILCSR_WARM_RESET        0x100
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              IIO_ICRB0_A
+#define IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+
+#define TNUM_TO_WIDGET_DEV(_tnum)	(_tnum & 0x7)
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+/*************************************************************************
+
+ Some of the IIO field masks and shifts are defined here.
+ This is in order to maintain compatibility in SN0 and SN1 code
+ 
+**************************************************************************/
+
+/*
+ * ICMR register fields
+ * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
+ * present in Bedrock)
+ */
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ XXX present but not needed in bedrock?  See the manual.
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/* 
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY		(0x1 << 20)
+#define IBLS_ERROR_SHFT		16
+#define IBLS_ERROR		(0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK	0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON		(0x1 << 8)
+#define IBCT_NOTIFY		(0x1 << 4)
+#define IBCT_ZFIL_MODE		(0x1 << 0)
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_PI1_FWD_INT	(1 << 31)  /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT	(1 << 30)  /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR	(1 << 29)  /* clear valid bit in ixss reg */
+#define IECLR_BTE1		(1 << 18)  /* clear bte error 1 */
+#define IECLR_BTE0		(1 << 17)  /* clear bte error 0 */
+#define IECLR_CRAZY		(1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F		(1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E		(1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D		(1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C		(1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B		(1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A		(1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9		(1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8		(1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0		(1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR 
+ */
+#define	IIO_ICCR_PENDING	(0x10000)
+#define	IIO_ICCR_CMD_MASK	(0xFF)
+#define	IIO_ICCR_CMD_SHFT	(7)
+#define	IIO_ICCR_CMD_NOP	(0x0)	/* No Op */
+#define	IIO_ICCR_CMD_WAKE	(0x100) /* Reactivate CRB entry and process */
+#define	IIO_ICCR_CMD_TIMEOUT	(0x200)	/* Make CRB timeout & mark invalid */
+#define	IIO_ICCR_CMD_EJECT	(0x400)	/* Contents of entry written to memory 
+					 * via a WB
+					 */
+#define	IIO_ICCR_CMD_FLUSH	(0x800)
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to hub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+#ifdef _LANGUAGE_C
+
+/*
+ * Easy access macros for CRBs, all 4 registers (A-D)
+ */
+typedef ii_icrb0_a_u_t icrba_t;	/* what it was called on SN0/hub */
+#define a_error         ii_icrb0_a_fld_s.ia_error
+#define a_ecode         ii_icrb0_a_fld_s.ia_errcode
+#define a_lnetuce       ii_icrb0_a_fld_s.ia_ln_uce
+#define a_mark          ii_icrb0_a_fld_s.ia_mark
+#define a_xerr          ii_icrb0_a_fld_s.ia_xt_err
+#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_addr          ii_icrb0_a_fld_s.ia_addr
+#define a_valid         ii_icrb0_a_fld_s.ia_vld
+#define a_iow           ii_icrb0_a_fld_s.ia_iow
+#define a_regvalue	ii_icrb0_a_regval
+
+typedef ii_icrb0_b_u_t icrbb_t;
+#define b_btenum        ii_icrb0_b_fld_s.ib_bte_num
+#define b_cohtrans      ii_icrb0_b_fld_s.ib_ct
+#define b_xtsize        ii_icrb0_b_fld_s.ib_size
+#define b_source        ii_icrb0_b_fld_s.ib_source
+#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
+#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
+#define b_initiator     ii_icrb0_b_fld_s.ib_init
+#define b_regvalue	ii_icrb0_b_regval
+
+typedef ii_icrb0_c_u_t icrbc_t;
+#define c_pricnt        ii_icrb0_c_fld_s.ic_pr_cnt
+#define c_pripsc        ii_icrb0_c_fld_s.ic_pr_psc
+#define c_bteop         ii_icrb0_c_fld_s.ic_bte_op
+#define c_bteaddr       ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
+#define c_benable       ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
+#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
+#define c_barrop        ii_icrb0_c_fld_s.ic_bo
+#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
+#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
+#define c_regvalue	ii_icrb0_c_regval
+
+typedef ii_icrb0_d_u_t icrbd_t;
+#define icrbd_ctxtvld   ii_icrb0_d_fld_s.id_cvld
+#define icrbd_toutvld   ii_icrb0_d_fld_s.id_tvld
+#define icrbd_context   ii_icrb0_d_fld_s.id_context
+#define d_regvalue	ii_icrb0_d_regval
+
+#endif /* LANGUAGE_C */
+
+/* Number of widgets supported by hub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc110
+#define MAX_HUBS_PER_XBOW       2
+
+#ifdef _LANGUAGE_C
+/* A few more #defines for backwards compatibility */
+#define iprb_t          ii_iprb0_u_t
+#define iprb_regval     ii_iprb0_regval
+#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
+#define iprb_error      ii_iprb0_fld_s.i_error
+#define iprb_ff         ii_iprb0_fld_s.i_f
+#define iprb_mode       ii_iprb0_fld_s.i_m
+#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
+#define iprb_anakctr    ii_iprb0_fld_s.i_na
+#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
+#endif
+
+#define LNK_STAT_WORKING        0x2
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+/* Number of II perf. counters we can multiplex at once */
+
+#define IO_PERF_SETS	32
+
+#ifdef BRINGUP
+#if __KERNEL__
+#if _LANGUAGE_C
+/* XXX moved over from SN/SN0/hubio.h -- each should be checked for SN1 */
+#include <asm/sn/alenlist.h>
+#include <asm/sn/dmamap.h>
+#include <asm/sn/iobus.h>
+#include <asm/sn/xtalk/xtalk.h>
+
+/* Bit for the widget in inbound access register */
+#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+/* Bit for the widget in outbound access register */
+#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+
+/* NOTE: The following define assumes that we are going to get
+ * widget numbers from 8 thru F and the device numbers within
+ * widget from 0 thru 7.
+ */
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_PI_ID_SHIFT   8
+#define IIO_IIDSR_PI_ID_MASK    0x00000010
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000007f
+
+/* Xtalk timeout threshhold register (IIO_IXTT) */
+#define IXTT_RRSP_TO_SHFT	55	   /* read response timeout */
+#define IXTT_RRSP_TO_MASK	(0x1FULL << IXTT_RRSP_TO_SHFT)
+#define IXTT_RRSP_PS_SHFT	32	   /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_MASK	(0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
+#define IXTT_TAIL_TO_SHFT	0	   /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_MASK	(0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
+
+/*
+ * The IO LLP control status register and widget control register
+ */
+
+#ifdef LITTLE_ENDIAN
+
+typedef union hubii_wcr_u {
+        uint64_t      wcr_reg_value;
+        struct {
+	  uint64_t	wcr_widget_id:   4,     /* LLP crossbar credit */
+			wcr_tag_mode:	 1,	/* Tag mode */
+			wcr_rsvd1:	 8,	/* Reserved */
+			wcr_xbar_crd:	 3,	/* LLP crossbar credit */
+			wcr_f_bad_pkt:	 1,	/* Force bad llp pkt enable */
+			wcr_dir_con:	 1,	/* widget direct connect */
+			wcr_e_thresh:	 5,	/* elasticity threshold */
+			wcr_rsvd:	41;	/* unused */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#else
+
+typedef union hubii_wcr_u {
+	uint64_t	wcr_reg_value;
+	struct {
+	    uint64_t	wcr_rsvd:	41,	/* unused */
+			wcr_e_thresh:	 5,	/* elasticity threshold */
+			wcr_dir_con:	 1,	/* widget direct connect */
+			wcr_f_bad_pkt:	 1,	/* Force bad llp pkt enable */
+			wcr_xbar_crd:	 3,	/* LLP crossbar credit */
+			wcr_rsvd1:	 8,	/* Reserved */
+			wcr_tag_mode:	 1,	/* Tag mode */
+			wcr_widget_id:	 4;	/* LLP crossbar credit */
+	} wcr_fields_s;
+} hubii_wcr_t;
+
+#endif
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+#ifdef LITTLE_ENDIAN
+
+typedef union io_perf_sel {
+        uint64_t perf_sel_reg;
+        struct {
+               uint64_t	perf_ippr0 :  4,
+				perf_ippr1 :  4,
+				perf_icct  :  8,
+				perf_rsvd  : 48;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+#else
+
+typedef union io_perf_sel {
+	uint64_t perf_sel_reg;
+	struct {
+		uint64_t	perf_rsvd  : 48,
+				perf_icct  :  8,
+				perf_ippr1 :  4,
+				perf_ippr0 :  4;
+	} perf_sel_bits;
+} io_perf_sel_t;
+
+#endif
+
+/* io_perf_cnt is to extract the count from the hub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+#ifdef LITTLE_ENDIAN
+
+typedef union io_perf_cnt {
+        uint64_t      perf_cnt;
+        struct {
+               uint64_t	perf_cnt   : 20,
+				perf_rsvd2 : 12,
+				perf_rsvd1 : 32;
+        } perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+#else
+
+typedef union io_perf_cnt {
+	uint64_t	perf_cnt;
+	struct {
+		uint64_t	perf_rsvd1 : 32,
+				perf_rsvd2 : 12,
+				perf_cnt   : 20;
+	} perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+typedef union iprte_a {
+	bdrkreg_t	entry;
+	struct {
+		bdrkreg_t	i_rsvd_1                  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t       i_vld                     :      1;
+	} iprte_fields;
+} iprte_a_t;
+
+#else
+
+typedef union iprte_a {
+	bdrkreg_t	entry;
+	struct {
+		bdrkreg_t	i_vld			  :	 1;
+		bdrkreg_t	i_to_cnt		  :	 5;
+		bdrkreg_t	i_widget		  :	 4;
+		bdrkreg_t	i_rsvd			  :	 2;
+		bdrkreg_t	i_source		  :	 8;
+		bdrkreg_t	i_init			  :	 3;
+		bdrkreg_t	i_addr			  :	38;
+		bdrkreg_t	i_rsvd_1		  :	 3;
+	} iprte_fields;
+} iprte_a_t;
+
+#endif
+
+/* PIO MANAGEMENT */
+typedef struct hub_piomap_s *hub_piomap_t;
+
+extern hub_piomap_t
+hub_piomap_alloc(devfs_handle_t dev,      /* set up mapping for this device */
+                device_desc_t dev_desc, /* device descriptor */
+                iopaddr_t xtalk_addr,   /* map for this xtalk_addr range */
+                size_t byte_count,
+                size_t byte_count_max,  /* maximum size of a mapping */
+                unsigned flags);                /* defined in sys/pio.h */
+
+extern void hub_piomap_free(hub_piomap_t hub_piomap);
+
+extern caddr_t
+hub_piomap_addr(hub_piomap_t hub_piomap,        /* mapping resources */
+                iopaddr_t xtalk_addr,           /* map for this xtalk addr */
+                size_t byte_count);             /* map this many bytes */
+
+extern void
+hub_piomap_done(hub_piomap_t hub_piomap);
+
+extern caddr_t
+hub_piotrans_addr(      devfs_handle_t dev,       /* translate to this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        iopaddr_t xtalk_addr,   /* Crosstalk address */
+                        size_t byte_count,      /* map this many bytes */
+                        unsigned flags);        /* (currently unused) */
+
+/* DMA MANAGEMENT */
+typedef struct hub_dmamap_s *hub_dmamap_t;
+
+extern hub_dmamap_t
+hub_dmamap_alloc(       devfs_handle_t dev,       /* set up mappings for dev */
+                        device_desc_t dev_desc, /* device descriptor */
+                        size_t byte_count_max,  /* max size of a mapping */
+                        unsigned flags);        /* defined in dma.h */
+
+extern void
+hub_dmamap_free(hub_dmamap_t dmamap);
+
+extern iopaddr_t
+hub_dmamap_addr(        hub_dmamap_t dmamap,    /* use mapping resources */
+                        paddr_t paddr,          /* map for this address */
+                        size_t byte_count);     /* map this many bytes */
+
+extern alenlist_t
+hub_dmamap_list(        hub_dmamap_t dmamap,    /* use mapping resources */
+                        alenlist_t alenlist,    /* map this Addr/Length List */
+                        unsigned flags);
+
+extern void
+hub_dmamap_done(        hub_dmamap_t dmamap);   /* done w/ mapping resources */
+
+extern iopaddr_t
+hub_dmatrans_addr(      devfs_handle_t dev,       /* translate for this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        paddr_t paddr,          /* system physical address */
+                        size_t byte_count,      /* length */
+                        unsigned flags);                /* defined in dma.h */
+
+extern alenlist_t
+hub_dmatrans_list(      devfs_handle_t dev,       /* translate for this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        alenlist_t palenlist,   /* system addr/length list */
+                        unsigned flags);                /* defined in dma.h */
+
+extern void
+hub_dmamap_drain(       hub_dmamap_t map);
+
+extern void
+hub_dmaaddr_drain(      devfs_handle_t vhdl,
+                        paddr_t addr,
+                        size_t bytes);
+
+extern void
+hub_dmalist_drain(      devfs_handle_t vhdl,
+                        alenlist_t list);
+
+
+/* INTERRUPT MANAGEMENT */
+typedef struct hub_intr_s *hub_intr_t;
+
+extern hub_intr_t
+hub_intr_alloc( devfs_handle_t dev,               /* which device */
+                device_desc_t dev_desc,         /* device descriptor */
+                devfs_handle_t owner_dev);        /* owner of this interrupt */
+
+extern void
+hub_intr_free(hub_intr_t intr_hdl);
+
+extern int
+hub_intr_connect(       hub_intr_t intr_hdl,    /* xtalk intr resource hndl */
+                        intr_func_t intr_func,  /* xtalk intr handler */
+                        void *intr_arg,         /* arg to intr handler */
+                        xtalk_intr_setfunc_t setfunc,
+                                                /* func to set intr hw */
+                        void *setfunc_arg,      /* arg to setfunc */
+                        void *thread);          /* intr thread to use */
+
+extern void
+hub_intr_disconnect(hub_intr_t intr_hdl);
+
+extern devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl);
+
+/* CONFIGURATION MANAGEMENT */
+
+extern void
+hub_provider_startup(devfs_handle_t hub);
+
+extern void
+hub_provider_shutdown(devfs_handle_t hub);
+
+#define HUB_PIO_CONVEYOR        0x1     /* PIO in conveyor belt mode */
+#define HUB_PIO_FIRE_N_FORGET   0x2     /* PIO in fire-and-forget mode */
+
+/* Flags that make sense to hub_widget_flags_set */
+#define HUB_WIDGET_FLAGS        (                               \
+				 HUB_PIO_CONVEYOR       |       \
+				 HUB_PIO_FIRE_N_FORGET          \
+				)
+
+
+typedef int     hub_widget_flags_t;
+
+/* Set the PIO mode for a widget.  These two functions perform the
+ * same operation, but hub_device_flags_set() takes a hardware graph
+ * vertex while hub_widget_flags_set() takes a nasid and widget
+ * number.  In most cases, hub_device_flags_set() should be used.
+ */
+extern int      hub_widget_flags_set(nasid_t            nasid,
+                                     xwidgetnum_t       widget_num,
+                                     hub_widget_flags_t flags);
+
+/* Depending on the flags set take the appropriate actions */
+extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
+                                     hub_widget_flags_t flags);
+                                                    
+
+/* Error Handling. */
+extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *);
+extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t,
+                              int, paddr_t, caddr_t, ioerror_mode_t);
+extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t);
+extern int hub_error_devenable(devfs_handle_t, int, int);
+extern void hub_widgetdev_enable(devfs_handle_t, int);
+extern void hub_widgetdev_shutdown(devfs_handle_t, int);
+extern int  hub_dma_enabled(devfs_handle_t);
+
+#endif /* _LANGUAGE_C */
+#endif /* _KERNEL */
+#endif /* BRINGUP */
+#endif  /* _ASM_SN_SN1_HUBIO_NEXT_H */
diff --git a/include/asm-ia64/sn/sn1/hublb.h b/include/asm-ia64/sn/sn1/hublb.h
new file mode 100644
index 000000000..692eeab44
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hublb.h
@@ -0,0 +1,1608 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+/************************************************************************
+ *                                                                      *
+ *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
+ *                                                                      *
+ * This file is created by an automated script. Any (minimal) changes   *
+ * made manually to this  file should be made with care.                *
+ *                                                                      *
+ *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
+ *                                                                      *
+ ************************************************************************/
+
+
+#ifndef _ASM_SN_SN1_HUBLB_H
+#define _ASM_SN_SN1_HUBLB_H
+
+
+#define    LB_REV_ID                 0x00600000    /*
+                                                    * Bedrock Revision
+                                                    * and ID
+                                                    */
+
+
+
+#define    LB_CPU_PERMISSION         0x00604000    /*
+                                                    * CPU PIO access
+                                                    * permission bits
+                                                    */
+
+
+
+#define    LB_CPU_PERM_OVRRD         0x00604008    /*
+                                                    * CPU PIO access
+                                                    * permission bit
+                                                    * override
+                                                    */
+
+
+
+#define    LB_IO_PERMISSION          0x00604010    /*
+                                                    * IO PIO access
+                                                    * permission bits
+                                                    */
+
+
+
+#define    LB_SOFT_RESET             0x00604018    /*
+                                                    * Soft reset the
+                                                    * Bedrock chip
+                                                    */
+
+
+
+#define    LB_REGION_PRESENT         0x00604020    /*
+                                                    * Regions Present for
+                                                    * Invalidates
+                                                    */
+
+
+
+#define    LB_NODES_ABSENT           0x00604028    /*
+                                                    * Nodes Absent for
+                                                    * Invalidates
+                                                    */
+
+
+
+#define    LB_MICROLAN_CTL           0x00604030    /*
+                                                    * Microlan Control
+                                                    * (NIC)
+                                                    */
+
+
+
+#define    LB_ERROR_BITS             0x00604040    /*
+                                                    * Local Block error
+                                                    * bits
+                                                    */
+
+
+
+#define    LB_ERROR_MASK_CLR         0x00604048    /*
+                                                    * Bit mask write to
+                                                    * clear error bits
+                                                    */
+
+
+
+#define    LB_ERROR_HDR1             0x00604050    /*
+                                                    * Source, Suppl and
+                                                    * Cmd fields
+                                                    */
+
+
+
+#define    LB_ERROR_HDR2             0x00604058    /*
+                                                    * Address field from
+                                                    * first error
+                                                    */
+
+
+
+#define    LB_ERROR_DATA             0x00604060    /*
+                                                    * Data flit (if any)
+                                                    * from first error
+                                                    */
+
+
+
+#define    LB_DEBUG_SELECT           0x00604100    /*
+                                                    * Choice of debug
+                                                    * signals from chip
+                                                    */
+
+
+
+#define    LB_DEBUG_PINS             0x00604108    /*
+                                                    * Value on the chip's
+                                                    * debug pins
+                                                    */
+
+
+
+#define    LB_RT_LOCAL_CTRL          0x00604200    /*
+                                                    * Local generation of
+                                                    * real-time clock
+                                                    */
+
+
+
+#define    LB_RT_FILTER_CTRL         0x00604208    /*
+                                                    * Control of
+                                                    * filtering of global
+                                                    * clock
+                                                    */
+
+
+
+#define    LB_SCRATCH_REG0           0x00608000    /* Scratch Register 0     */
+
+
+
+#define    LB_SCRATCH_REG1           0x00608008    /* Scratch Register 1     */
+
+
+
+#define    LB_SCRATCH_REG2           0x00608010    /* Scratch Register 2     */
+
+
+
+#define    LB_SCRATCH_REG3           0x00608018    /* Scratch Register 3     */
+
+
+
+#define    LB_SCRATCH_REG4           0x00608020    /* Scratch Register 4     */
+
+
+
+#define    LB_SCRATCH_REG0_WZ        0x00608040    /*
+                                                    * Scratch Register 0
+                                                    * (WZ alias)
+                                                    */
+
+
+
+#define    LB_SCRATCH_REG1_WZ        0x00608048    /*
+                                                    * Scratch Register 1
+                                                    * (WZ alias)
+                                                    */
+
+
+
+#define    LB_SCRATCH_REG2_WZ        0x00608050    /*
+                                                    * Scratch Register 2
+                                                    * (WZ alias)
+                                                    */
+
+
+
+#define    LB_SCRATCH_REG3_RZ        0x00608058    /*
+                                                    * Scratch Register 3
+                                                    * (RZ alias)
+                                                    */
+
+
+
+#define    LB_SCRATCH_REG4_RZ        0x00608060    /*
+                                                    * Scratch Register 4
+                                                    * (RZ alias)
+                                                    */
+
+
+
+#define    LB_VECTOR_PARMS           0x0060C000    /*
+                                                    * Vector PIO
+                                                    * parameters
+                                                    */
+
+
+
+#define    LB_VECTOR_ROUTE           0x0060C008    /*
+                                                    * Vector PIO Vector
+                                                    * Route
+                                                    */
+
+
+
+#define    LB_VECTOR_DATA            0x0060C010    /*
+                                                    * Vector PIO Write
+                                                    * Data
+                                                    */
+
+
+
+#define    LB_VECTOR_STATUS          0x0060C020    /*
+                                                    * Vector PIO Return
+                                                    * Status
+                                                    */
+
+
+
+#define    LB_VECTOR_RETURN          0x0060C028    /*
+                                                    * Vector PIO Return
+                                                    * Route
+                                                    */
+
+
+
+#define    LB_VECTOR_READ_DATA       0x0060C030    /*
+                                                    * Vector PIO Read
+                                                    * Data
+                                                    */
+
+
+
+#define    LB_VECTOR_STATUS_CLEAR    0x0060C038    /*
+                                                    * Clear Vector PIO
+                                                    * Return Status
+                                                    */
+
+
+
+
+
+#ifdef _LANGUAGE_C
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains information that allows         *
+ * exploratory software to probe for chip type. This is also the        *
+ * register that sets this node's ID and the size of each region        *
+ * (which affects the maximum possible system size). IBM assigns the    *
+ * values for the REVISION, PART_NUMBER and MANUFACTURER fields, in     *
+ * accordance with the IEEE 1149.1 standard; SGI is not at liberty to   *
+ * unilaterally change the values of these fields.                      *
+ *  .                                                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_rev_id_u {
+	bdrkreg_t	lb_rev_id_regval;
+	struct  {
+		bdrkreg_t	ri_reserved_2             :	 1;
+		bdrkreg_t       ri_manufacturer           :     11;
+		bdrkreg_t       ri_part_number            :     16;
+		bdrkreg_t       ri_revision               :      4;
+		bdrkreg_t       ri_node_id                :      8;
+		bdrkreg_t       ri_reserved_1             :      6;
+		bdrkreg_t       ri_region_size            :      2;
+		bdrkreg_t       ri_reserved               :     16;
+	} lb_rev_id_fld_s;
+} lb_rev_id_u_t;
+
+#else
+
+typedef union lb_rev_id_u {
+        bdrkreg_t       lb_rev_id_regval;
+	struct	{
+		bdrkreg_t	ri_reserved		  :	16;
+		bdrkreg_t	ri_region_size		  :	 2;
+		bdrkreg_t	ri_reserved_1		  :	 6;
+		bdrkreg_t	ri_node_id		  :	 8;
+		bdrkreg_t	ri_revision		  :	 4;
+		bdrkreg_t	ri_part_number		  :	16;
+		bdrkreg_t	ri_manufacturer		  :	11;
+		bdrkreg_t	ri_reserved_2		  :	 1;
+	} lb_rev_id_fld_s;
+} lb_rev_id_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the PI-access-rights bit-vector for the      *
+ * LB, NI, XB and MD portions of the Bedrock local register space. If   *
+ * a bit in the bit-vector is set, the region corresponding to that     *
+ * bit has read/write permission on the LB, NI, XB and MD local         *
+ * registers. If the bit is clear, that region has no write access to   *
+ * the local registers and no read access if the read will cause any    *
+ * state change. If a write or a read with side effects is attempted    *
+ * by a PI in a region for which access is restricted, the LB will      *
+ * not perform the operation and will send back a reply which           *
+ * indicates an error.                                                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_cpu_permission_u {
+	bdrkreg_t	lb_cpu_permission_regval;
+	struct  {
+		bdrkreg_t	cp_cpu_access             :	64;
+	} lb_cpu_permission_fld_s;
+} lb_cpu_permission_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register of the 64-bit value "SGIrules" will        *
+ * cause the bit in the LB_CPU_PROTECT register corresponding to the    *
+ * region of the requester to be set.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_cpu_perm_ovrrd_u {
+	bdrkreg_t	lb_cpu_perm_ovrrd_regval;
+	struct  {
+		bdrkreg_t	cpo_cpu_perm_ovr          :	64;
+	} lb_cpu_perm_ovrrd_fld_s;
+} lb_cpu_perm_ovrrd_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the II-access-rights bit-vector for the      *
+ * LB, NI, XB and MD portions of the Bedrock local register space. If   *
+ * a bit in the bit-vector is set, the region corresponding to that     *
+ * bit has read/write permission on the LB, NI, XB and MD local         *
+ * registers. If the bit is clear, then that region has no write        *
+ * access to the local registers and no read access if the read         *
+ * results in any state change. If a write or a read with side          *
+ * effects is attempted by an II in a region for which access is        *
+ * restricted, the LB will not perform the operation and will send      *
+ * back a reply which indicates an error.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_io_permission_u {
+	bdrkreg_t	lb_io_permission_regval;
+	struct  {
+		bdrkreg_t	ip_io_permission          :	64;
+	} lb_io_permission_fld_s;
+} lb_io_permission_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this bit resets the Bedrock chip with a soft reset.      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_soft_reset_u {
+	bdrkreg_t	lb_soft_reset_regval;
+	struct  {
+		bdrkreg_t	sr_soft_reset             :	 1;
+		bdrkreg_t	sr_reserved		  :	63;
+	} lb_soft_reset_fld_s;
+} lb_soft_reset_u_t;
+
+#else
+
+typedef union lb_soft_reset_u {
+	bdrkreg_t	lb_soft_reset_regval;
+	struct	{
+		bdrkreg_t	sr_reserved		  :	63;
+		bdrkreg_t	sr_soft_reset		  :	 1;
+	} lb_soft_reset_fld_s;
+} lb_soft_reset_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register indicates which regions are present and capable of    *
+ * receiving an invalidate (INVAL) request. The LB samples this         *
+ * register at the start of processing each LINVAL. When an LINVAL      *
+ * indicates that a particular PI unit might hold a shared copy of a    *
+ * cache block but this PI is in a region which is not present (i.e.,   *
+ * its bit in LB_REGION_PRESENT is clear), then the LB sends an IVACK   *
+ * reply packet on behalf of this PI. The REGION_SIZE field in the      *
+ * LB_REV_ID register determines the number of nodes per region (and    *
+ * hence, the number of PI units which share a common bit in the        *
+ * LB_REGION_PRESENT register).                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_region_present_u {
+	bdrkreg_t	lb_region_present_regval;
+	struct  {
+		bdrkreg_t	rp_present_bits           :	64;
+	} lb_region_present_fld_s;
+} lb_region_present_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register indicates which nodes are absent and     *
+ * not capable of receiving an invalidate (INVAL) request. The LB       *
+ * samples this register at the start of processing each LINVAL. When   *
+ * an LINVAL indicates that a particular PI unit might hold a shared    *
+ * copy of a cache block but this PI unit's node is not present         *
+ * (i.e., its node ID is listed in the LB_NODES_ABSENT register),       *
+ * then the LB sends an IVACK reply packet on behalf of this PI.        *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_nodes_absent_u {
+	bdrkreg_t	lb_nodes_absent_regval;
+	struct  {
+		bdrkreg_t	na_node_0                 :	 8;
+		bdrkreg_t       na_reserved_3             :      7;
+		bdrkreg_t       na_node_0_valid           :      1;
+		bdrkreg_t       na_node_1                 :      8;
+		bdrkreg_t       na_reserved_2             :      7;
+		bdrkreg_t       na_node_1_valid           :      1;
+		bdrkreg_t       na_node_2                 :      8;
+		bdrkreg_t       na_reserved_1             :      7;
+		bdrkreg_t       na_node_2_valid           :      1;
+		bdrkreg_t       na_node_3                 :      8;
+		bdrkreg_t       na_reserved               :      7;
+		bdrkreg_t       na_node_3_valid           :      1;
+	} lb_nodes_absent_fld_s;
+} lb_nodes_absent_u_t;
+
+#else
+
+typedef union lb_nodes_absent_u {
+	bdrkreg_t	lb_nodes_absent_regval;
+	struct	{
+		bdrkreg_t	na_node_3_valid		  :	 1;
+		bdrkreg_t	na_reserved		  :	 7;
+		bdrkreg_t	na_node_3		  :	 8;
+		bdrkreg_t	na_node_2_valid		  :	 1;
+		bdrkreg_t	na_reserved_1		  :	 7;
+		bdrkreg_t	na_node_2		  :	 8;
+		bdrkreg_t	na_node_1_valid		  :	 1;
+		bdrkreg_t	na_reserved_2		  :	 7;
+		bdrkreg_t	na_node_1		  :	 8;
+		bdrkreg_t	na_node_0_valid		  :	 1;
+		bdrkreg_t	na_reserved_3		  :	 7;
+		bdrkreg_t	na_node_0		  :	 8;
+	} lb_nodes_absent_fld_s;
+} lb_nodes_absent_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides access to the Number-In-a-Can add-only       *
+ * serial PROM that is used to store node board serial number and       *
+ * configuration information. (Refer to NIC datasheet Dallas 1990A      *
+ * that is viewable at                                                  *
+ * URL::http://www.dalsemi.com/DocControl/PDFs/pdfindex.html). Data     *
+ * comes from this interface LSB first.                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_microlan_ctl_u {
+	bdrkreg_t	lb_microlan_ctl_regval;
+	struct  {
+		bdrkreg_t	mc_rd_data                :	 1;
+		bdrkreg_t       mc_done                   :      1;
+		bdrkreg_t       mc_sample                 :      8;
+		bdrkreg_t       mc_pulse                  :     10;
+		bdrkreg_t       mc_clkdiv_phi0            :      7;
+		bdrkreg_t       mc_clkdiv_phi1            :      7;
+		bdrkreg_t       mc_reserved               :     30;
+	} lb_microlan_ctl_fld_s;
+} lb_microlan_ctl_u_t;
+
+#else
+
+typedef union lb_microlan_ctl_u {
+        bdrkreg_t       lb_microlan_ctl_regval;
+        struct  {
+                bdrkreg_t       mc_reserved               :     30;
+                bdrkreg_t       mc_clkdiv_phi1            :      7;
+                bdrkreg_t       mc_clkdiv_phi0            :      7;
+                bdrkreg_t       mc_pulse                  :     10;
+                bdrkreg_t       mc_sample                 :      8;
+                bdrkreg_t       mc_done                   :      1;
+                bdrkreg_t       mc_rd_data                :      1;
+        } lb_microlan_ctl_fld_s;
+} lb_microlan_ctl_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains the LB error status bits.       *
+ * Whenever a particular type of error occurs, the LB sets its bit in   *
+ * this register so that software will be aware that such an event      *
+ * has happened. Reads from this register are non-destructive and the   *
+ * contents of this register remain intact across reset operations.     *
+ * Whenever any of these bits is set, the LB will assert its            *
+ * interrupt request output signals that go to the PI units.            *
+ *  Software can simulate the occurrence of an error by first writing   *
+ * appropriate values into the LB_ERROR_HDR1, LB_ERROR_HDR2 and         *
+ * LB_ERROR_DATA registers, and then writing to the LB_ERROR_BITS       *
+ * register to set the error bits in a particular way. Setting one or   *
+ * more error bits will cause the LB to interrupt a processor and       *
+ * invoke error-handling software.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_error_bits_u {
+	bdrkreg_t	lb_error_bits_regval;
+	struct  {
+		bdrkreg_t	eb_rq_bad_cmd             :	 1;
+		bdrkreg_t       eb_rp_bad_cmd             :      1;
+		bdrkreg_t       eb_rq_short               :      1;
+		bdrkreg_t       eb_rp_short               :      1;
+		bdrkreg_t       eb_rq_long                :      1;
+		bdrkreg_t       eb_rp_long                :      1;
+		bdrkreg_t       eb_rq_bad_data            :      1;
+		bdrkreg_t       eb_rp_bad_data            :      1;
+		bdrkreg_t       eb_rq_bad_addr            :      1;
+		bdrkreg_t       eb_rq_bad_linval          :      1;
+		bdrkreg_t       eb_gclk_drop              :      1;
+		bdrkreg_t       eb_reserved               :     53;
+	} lb_error_bits_fld_s;
+} lb_error_bits_u_t;
+
+#else
+
+typedef union lb_error_bits_u {
+	bdrkreg_t	lb_error_bits_regval;
+	struct	{
+		bdrkreg_t	eb_reserved		  :	53;
+		bdrkreg_t	eb_gclk_drop		  :	 1;
+		bdrkreg_t	eb_rq_bad_linval	  :	 1;
+		bdrkreg_t	eb_rq_bad_addr		  :	 1;
+		bdrkreg_t	eb_rp_bad_data		  :	 1;
+		bdrkreg_t	eb_rq_bad_data		  :	 1;
+		bdrkreg_t	eb_rp_long		  :	 1;
+		bdrkreg_t	eb_rq_long		  :	 1;
+		bdrkreg_t	eb_rp_short		  :	 1;
+		bdrkreg_t	eb_rq_short		  :	 1;
+		bdrkreg_t	eb_rp_bad_cmd		  :	 1;
+		bdrkreg_t	eb_rq_bad_cmd		  :	 1;
+	} lb_error_bits_fld_s;
+} lb_error_bits_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register lets software clear some of the bits in the           *
+ * LB_ERROR_BITS register without affecting other bits.  Essentially,   *
+ * it provides bit mask functionality. When software writes to the      *
+ * LB_ERROR_MASK_CLR register, the bits which are set in the data       *
+ * value indicate which bits are to be cleared in LB_ERROR_BITS. If a   *
+ * bit is clear in the data value written to the LB_ERROR_MASK_CLR      *
+ * register, then its corresponding bit in the LB_ERROR_BITS register   *
+ * is not affected. Hence, software can atomically clear any subset     *
+ * of the error bits in the LB_ERROR_BITS register.                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_error_mask_clr_u {
+	bdrkreg_t	lb_error_mask_clr_regval;
+	struct  {
+		bdrkreg_t	emc_clr_rq_bad_cmd        :	 1;
+		bdrkreg_t       emc_clr_rp_bad_cmd        :      1;
+		bdrkreg_t       emc_clr_rq_short          :      1;
+		bdrkreg_t       emc_clr_rp_short          :      1;
+		bdrkreg_t       emc_clr_rq_long           :      1;
+		bdrkreg_t       emc_clr_rp_long           :      1;
+		bdrkreg_t       emc_clr_rq_bad_data       :      1;
+		bdrkreg_t       emc_clr_rp_bad_data       :      1;
+		bdrkreg_t       emc_clr_rq_bad_addr       :      1;
+		bdrkreg_t       emc_clr_rq_bad_linval     :      1;
+		bdrkreg_t       emc_clr_gclk_drop         :      1;
+		bdrkreg_t       emc_reserved              :     53;
+	} lb_error_mask_clr_fld_s;
+} lb_error_mask_clr_u_t;
+
+#else
+
+typedef union lb_error_mask_clr_u {
+	bdrkreg_t	lb_error_mask_clr_regval;
+	struct	{
+		bdrkreg_t	emc_reserved		  :	53;
+		bdrkreg_t	emc_clr_gclk_drop	  :	 1;
+		bdrkreg_t	emc_clr_rq_bad_linval	  :	 1;
+		bdrkreg_t	emc_clr_rq_bad_addr	  :	 1;
+		bdrkreg_t	emc_clr_rp_bad_data	  :	 1;
+		bdrkreg_t	emc_clr_rq_bad_data	  :	 1;
+		bdrkreg_t	emc_clr_rp_long		  :	 1;
+		bdrkreg_t	emc_clr_rq_long		  :	 1;
+		bdrkreg_t	emc_clr_rp_short	  :	 1;
+		bdrkreg_t	emc_clr_rq_short	  :	 1;
+		bdrkreg_t	emc_clr_rp_bad_cmd	  :	 1;
+		bdrkreg_t	emc_clr_rq_bad_cmd	  :	 1;
+	} lb_error_mask_clr_fld_s;
+} lb_error_mask_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  If the LB detects an error when VALID==0 in the LB_ERROR_HDR1       *
+ * register, then it saves the contents of the offending packet's       *
+ * header flit in the LB_ERROR_HDR1 and LB_ERROR_HDR2 registers, sets   *
+ * the VALID bit in LB_ERROR_HDR1 and clears the OVERRUN bit in         *
+ * LB_ERROR_HDR1 (and it will also set the corresponding bit in the     *
+ * LB_ERROR_BITS register). The ERR_TYPE field indicates specifically   *
+ * what kind of error occurred.  Its encoding corresponds to the bit    *
+ * positions in the LB_ERROR_BITS register (e.g., ERR_TYPE==5           *
+ * indicates a RP_LONG error).  If an error (of any type except         *
+ * GCLK_DROP) subsequently happens while VALID==1, then the LB sets     *
+ * the OVERRUN bit in LB_ERROR_HDR1. This register is not relevant      *
+ * when a GCLK_DROP error occurs; the LB does not even attempt to       *
+ * change the ERR_TYPE, VALID or OVERRUN field when a GCLK_DROP error   *
+ * happens.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_error_hdr1_u {
+	bdrkreg_t	lb_error_hdr1_regval;
+	struct  {
+		bdrkreg_t	eh_command                :	 7;
+		bdrkreg_t       eh_reserved_5             :      1;
+		bdrkreg_t       eh_suppl                  :     11;
+		bdrkreg_t       eh_reserved_4             :      1;
+		bdrkreg_t       eh_source                 :     11;
+		bdrkreg_t       eh_reserved_3             :      1;
+		bdrkreg_t       eh_err_type               :      4;
+		bdrkreg_t       eh_reserved_2             :      4;
+		bdrkreg_t       eh_overrun                :      1;
+		bdrkreg_t       eh_reserved_1             :      3;
+		bdrkreg_t       eh_valid                  :      1;
+		bdrkreg_t       eh_reserved               :     19;
+	} lb_error_hdr1_fld_s;
+} lb_error_hdr1_u_t;
+
+#else
+
+typedef union lb_error_hdr1_u {
+	bdrkreg_t	lb_error_hdr1_regval;
+	struct	{
+		bdrkreg_t	eh_reserved		  :	19;
+		bdrkreg_t	eh_valid		  :	 1;
+		bdrkreg_t	eh_reserved_1		  :	 3;
+		bdrkreg_t	eh_overrun		  :	 1;
+		bdrkreg_t	eh_reserved_2		  :	 4;
+		bdrkreg_t	eh_err_type		  :	 4;
+		bdrkreg_t	eh_reserved_3		  :	 1;
+		bdrkreg_t	eh_source		  :	11;
+		bdrkreg_t	eh_reserved_4		  :	 1;
+		bdrkreg_t	eh_suppl		  :	11;
+		bdrkreg_t	eh_reserved_5		  :	 1;
+		bdrkreg_t	eh_command		  :	 7;
+	} lb_error_hdr1_fld_s;
+} lb_error_hdr1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contents of the Address field from header flit of first packet      *
+ * that causes an error. This register is not relevant when a           *
+ * GCLK_DROP error occurs.                                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_error_hdr2_u {
+	bdrkreg_t	lb_error_hdr2_regval;
+	struct  {
+		bdrkreg_t	eh_address                :	38;
+		bdrkreg_t       eh_reserved               :     26;
+	} lb_error_hdr2_fld_s;
+} lb_error_hdr2_u_t;
+
+#else
+
+typedef union lb_error_hdr2_u {
+	bdrkreg_t	lb_error_hdr2_regval;
+	struct	{
+		bdrkreg_t	eh_reserved		  :	26;
+		bdrkreg_t	eh_address		  :	38;
+	} lb_error_hdr2_fld_s;
+} lb_error_hdr2_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register accompanies the LB_ERROR_HDR1 and        *
+ * LB_ERROR_HDR2 registers.  The LB updates the value in this           *
+ * register when an incoming packet with a data flit causes an error    *
+ * while VALID==0 in the LB_ERROR_HDR1 register.  This register         *
+ * retains the contents of the data flit from the incoming packet       *
+ * that caused the error. This register is relevant for the following   *
+ * types of errors:                                                     *
+ * <UL >                                                                *
+ * <UL >                                                                *
+ * <UL >                                                                *
+ * <UL >                                                                *
+ * <UL >                                                                *
+ * <LI >RQ_BAD_LINVAL for a LINVAL request.                             *
+ * <LI >RQ_BAD_ADDR for a normal or vector PIO request.                 *
+ * <LI >RP_BAD_DATA for a vector PIO reply.                             *
+ * <LI >RQ_BAD DATA for an incoming request with data.                  *
+ * <LI >RP_LONG for a vector PIO reply.                                 *
+ * <LI >RQ_LONG for an incoming request with expected data.             *
+ * <BLOCKQUOTE >                                                        *
+ * In the case of RQ_BAD_LINVAL, the register retains the 64-bit data   *
+ * value that followed the header flit.  In the case of RQ_BAD_ADDR     *
+ * or RQ_BAD_DATA, the register retains the incoming packet's 64-bit    *
+ * data value (i.e., 2nd flit in the packet for a normal PIO write or   *
+ * an LINVAL, 3rd flit for a vector PIO read or write). In the case     *
+ * of RP_BAD_DATA, the register retains the 64-bit data value in the    *
+ * 3rd flit of the packet. When a RP_LONG or RQ_LONG error occurs,      *
+ * the LB loads the LB_ERROR_DATA register with the contents of the     *
+ * expected data flit (i.e., the 3rd flit in the packet for a vector    *
+ * PIO request or reply, the 2nd flit for other packets), if any. The   *
+ * contents of the LB_ERROR_DATA register are undefined after a         *
+ * RP_SHORT, RQ_SHORT, RP_BAD_CMD or RQ_BAD_CMD error. The contents     *
+ * of the LB_ERROR_DATA register are also undefined after an incoming   *
+ * normal PIO read request which encounters a RQ_LONG error.            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_error_data_u {
+	bdrkreg_t	lb_error_data_regval;
+	struct  {
+		bdrkreg_t	ed_data                   :	64;
+	} lb_error_data_fld_s;
+} lb_error_data_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register enables software to control what internal Bedrock     *
+ * signals are visible on the chip's debug pins. The LB provides the    *
+ * 6-bit value in this register to Bedrock's DEBUG unit. The JTAG       *
+ * unit provides a similar 6-bit selection input to the DEBUG unit,     *
+ * along with another signal that tells the DEBUG unit whether to use   *
+ * the selection signal from the LB or the JTAG unit. For a             *
+ * description of the menu of choices for debug signals, refer to the   *
+ * documentation for the DEBUG unit.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_debug_select_u {
+	bdrkreg_t	lb_debug_select_regval;
+	struct  {
+		bdrkreg_t	ds_debug_sel              :	 6;
+		bdrkreg_t       ds_reserved               :     58;
+	} lb_debug_select_fld_s;
+} lb_debug_select_u_t;
+
+#else
+
+typedef union lb_debug_select_u {
+	bdrkreg_t	lb_debug_select_regval;
+	struct	{
+		bdrkreg_t	ds_reserved		  :	58;
+		bdrkreg_t	ds_debug_sel		  :	 6;
+	} lb_debug_select_fld_s;
+} lb_debug_select_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A PIO read from this register returns the 32-bit value that is      *
+ * currently on the Bedrock chip's debug pins. This register allows     *
+ * software to observe debug pin output values which do not change      *
+ * frequently (i.e., they remain constant over a period of many         *
+ * cycles).                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_debug_pins_u {
+	bdrkreg_t	lb_debug_pins_regval;
+	struct  {
+		bdrkreg_t	dp_debug_pins             :	32;
+		bdrkreg_t       dp_reserved               :     32;
+	} lb_debug_pins_fld_s;
+} lb_debug_pins_u_t;
+
+#else
+
+typedef union lb_debug_pins_u {
+	bdrkreg_t	lb_debug_pins_regval;
+	struct	{
+		bdrkreg_t	dp_reserved		  :	32;
+		bdrkreg_t	dp_debug_pins		  :	32;
+	} lb_debug_pins_fld_s;
+} lb_debug_pins_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  The LB unit provides the PI0 and PI1 units with a real-time clock   *
+ * signal. The LB can generate this signal itself, based on the         *
+ * Bedrock chip's system clock which the LB receives as an input.       *
+ * Alternatively, the LB can filter a global clock signal which it      *
+ * receives as an input and provide the filtered version to PI0 and     *
+ * PI1. The user can program the LB_RT_LOCAL_CTRL register to choose    *
+ * the source of the real-time clock. If the user chooses to generate   *
+ * the real-time clock internally within the LB, then the user can      *
+ * specify the period for the real-time clock signal.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_rt_local_ctrl_u {
+	bdrkreg_t	lb_rt_local_ctrl_regval;
+	struct  {
+		bdrkreg_t	rlc_gclk_enable           :	 1;
+		bdrkreg_t       rlc_reserved_4            :      3;
+		bdrkreg_t       rlc_max_count             :     10;
+		bdrkreg_t       rlc_reserved_3            :      2;
+		bdrkreg_t       rlc_gclk_counter          :     10;
+		bdrkreg_t       rlc_reserved_2            :      2;
+		bdrkreg_t       rlc_gclk                  :      1;
+		bdrkreg_t       rlc_reserved_1            :      3;
+		bdrkreg_t       rlc_use_internal          :      1;
+		bdrkreg_t       rlc_reserved              :     31;
+	} lb_rt_local_ctrl_fld_s;
+} lb_rt_local_ctrl_u_t;
+
+#else
+
+typedef union lb_rt_local_ctrl_u {
+        bdrkreg_t       lb_rt_local_ctrl_regval;
+        struct  {
+                bdrkreg_t       rlc_reserved              :     31;
+                bdrkreg_t       rlc_use_internal          :      1;
+                bdrkreg_t       rlc_reserved_1            :      3;
+                bdrkreg_t       rlc_gclk                  :      1;
+                bdrkreg_t       rlc_reserved_2            :      2;
+                bdrkreg_t       rlc_gclk_counter          :     10;
+                bdrkreg_t       rlc_reserved_3            :      2;
+                bdrkreg_t       rlc_max_count             :     10;
+                bdrkreg_t       rlc_reserved_4            :      3;
+                bdrkreg_t       rlc_gclk_enable           :      1;
+        } lb_rt_local_ctrl_fld_s;
+} lb_rt_local_ctrl_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  When the value of the USE_INTERNAL field in the LB_RT_LOCAL_CTRL    *
+ * register is 0, the LB filters an incoming global clock signal and    *
+ * provides the result to PI0 and PI1 for their real-time clock         *
+ * inputs. The LB can perform either simple filtering or complex        *
+ * filtering, depending on the value of the MASK_ENABLE bit. For the    *
+ * simple filtering option, the LB merely removes glitches from the     *
+ * incoming global clock; if the global clock goes high (or low) for    *
+ * only a single cycle, the LB considers it to be a glitch and does     *
+ * not pass it through to PI0 and PI1. For the complex filtering        *
+ * option, the LB expects positive edges on the incoming global clock   *
+ * to be spaced at fairly regular intervals and it looks for them at    *
+ * these times; the LB keeps track of unexpected or missing positive    *
+ * edges, and it generates an edge itself whenever the incoming         *
+ * global clock apparently misses an edge. For each filtering option,   *
+ * the real-time clock which the LB provides to PI0 and PI1 is not      *
+ * necessarily a square wave; when a positive edge happens, the         *
+ * real-time clock stays high for (2*MAX_COUNT+1-OFFSET)/2 cycles of    *
+ * the LB's system clock, and then is low until the next positive       *
+ * edge.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_rt_filter_ctrl_u {
+	bdrkreg_t	lb_rt_filter_ctrl_regval;
+	struct  {
+		bdrkreg_t       rfc_offset                :      5;
+		bdrkreg_t       rfc_reserved_4            :      3;
+		bdrkreg_t       rfc_mask_counter          :     12;
+		bdrkreg_t       rfc_mask_enable           :      1;
+		bdrkreg_t       rfc_reserved_3            :      3;
+		bdrkreg_t       rfc_dropout_counter       :     10;
+		bdrkreg_t       rfc_reserved_2            :      2;
+		bdrkreg_t       rfc_dropout_thresh        :     10;
+		bdrkreg_t       rfc_reserved_1            :      2;
+		bdrkreg_t       rfc_error_counter         :     10;
+		bdrkreg_t       rfc_reserved              :      6;
+	} lb_rt_filter_ctrl_fld_s;
+} lb_rt_filter_ctrl_u_t;
+
+#else
+
+typedef union lb_rt_filter_ctrl_u {
+        bdrkreg_t       lb_rt_filter_ctrl_regval;
+        struct  {
+                bdrkreg_t       rfc_reserved              :      6;
+                bdrkreg_t       rfc_error_counter         :     10;
+                bdrkreg_t       rfc_reserved_1            :      2;
+                bdrkreg_t       rfc_dropout_thresh        :     10;
+                bdrkreg_t       rfc_reserved_2            :      2;
+                bdrkreg_t       rfc_dropout_counter       :     10;
+                bdrkreg_t       rfc_reserved_3            :      3;
+                bdrkreg_t       rfc_mask_enable           :      1;
+                bdrkreg_t       rfc_mask_counter          :     12;
+                bdrkreg_t       rfc_reserved_4            :      3;
+                bdrkreg_t       rfc_offset                :      5;
+        } lb_rt_filter_ctrl_fld_s;
+} lb_rt_filter_ctrl_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is a scratch register that is reset to 0x0. At the    *
+ * normal address, the register is a simple storage location. At the    *
+ * Write-If-Zero address, the register accepts a new value from a       *
+ * write operation only if the current value is zero.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_scratch_reg0_u {
+	bdrkreg_t	lb_scratch_reg0_regval;
+	struct  {
+		bdrkreg_t	sr_scratch_bits           :	64;
+	} lb_scratch_reg0_fld_s;
+} lb_scratch_reg0_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These registers are scratch registers that are not reset. At a      *
+ * register's normal address, it is a simple storage location. At a     *
+ * register's Write-If-Zero address, it accepts a new value from a      *
+ * write operation only if the current value is zero.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_scratch_reg1_u {
+	bdrkreg_t	lb_scratch_reg1_regval;
+	struct  {
+		bdrkreg_t	sr_scratch_bits           :	64;
+	} lb_scratch_reg1_fld_s;
+} lb_scratch_reg1_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These registers are scratch registers that are not reset. At a      *
+ * register's normal address, it is a simple storage location. At a     *
+ * register's Write-If-Zero address, it accepts a new value from a      *
+ * write operation only if the current value is zero.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_scratch_reg2_u {
+	bdrkreg_t	lb_scratch_reg2_regval;
+	struct  {
+		bdrkreg_t	sr_scratch_bits           :	64;
+	} lb_scratch_reg2_fld_s;
+} lb_scratch_reg2_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These one-bit registers are scratch registers. At a register's      *
+ * normal address, it is a simple storage location. At a register's     *
+ * Read-Set-If-Zero address, it returns the original contents and       *
+ * sets the bit if the original value is zero.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_scratch_reg3_u {
+	bdrkreg_t	lb_scratch_reg3_regval;
+	struct  {
+		bdrkreg_t	sr_scratch_bit            :	 1;
+		bdrkreg_t	sr_reserved		  :	63;
+	} lb_scratch_reg3_fld_s;
+} lb_scratch_reg3_u_t;
+
+#else
+
+typedef union lb_scratch_reg3_u {
+	bdrkreg_t	lb_scratch_reg3_regval;
+	struct	{
+		bdrkreg_t	sr_reserved		  :	63;
+		bdrkreg_t	sr_scratch_bit		  :	 1;
+	} lb_scratch_reg3_fld_s;
+} lb_scratch_reg3_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These one-bit registers are scratch registers. At a register's      *
+ * normal address, it is a simple storage location. At a register's     *
+ * Read-Set-If-Zero address, it returns the original contents and       *
+ * sets the bit if the original value is zero.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_scratch_reg4_u {
+	bdrkreg_t	lb_scratch_reg4_regval;
+	struct  {
+		bdrkreg_t	sr_scratch_bit            :	 1;
+		bdrkreg_t       sr_reserved               :     63;
+	} lb_scratch_reg4_fld_s;
+} lb_scratch_reg4_u_t;
+
+#else
+
+typedef union lb_scratch_reg4_u {
+	bdrkreg_t	lb_scratch_reg4_regval;
+	struct	{
+		bdrkreg_t	sr_reserved		  :	63;
+		bdrkreg_t	sr_scratch_bit		  :	 1;
+	} lb_scratch_reg4_fld_s;
+} lb_scratch_reg4_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is a scratch register that is reset to 0x0. At the    *
+ * normal address, the register is a simple storage location. At the    *
+ * Write-If-Zero address, the register accepts a new value from a       *
+ * write operation only if the current value is zero.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_scratch_reg0_wz_u {
+	bdrkreg_t	lb_scratch_reg0_wz_regval;
+	struct  {
+		bdrkreg_t	srw_scratch_bits          :	64;
+	} lb_scratch_reg0_wz_fld_s;
+} lb_scratch_reg0_wz_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These registers are scratch registers that are not reset. At a      *
+ * register's normal address, it is a simple storage location. At a     *
+ * register's Write-If-Zero address, it accepts a new value from a      *
+ * write operation only if the current value is zero.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_scratch_reg1_wz_u {
+	bdrkreg_t	lb_scratch_reg1_wz_regval;
+	struct  {
+		bdrkreg_t	srw_scratch_bits          :	64;
+	} lb_scratch_reg1_wz_fld_s;
+} lb_scratch_reg1_wz_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These registers are scratch registers that are not reset. At a      *
+ * register's normal address, it is a simple storage location. At a     *
+ * register's Write-If-Zero address, it accepts a new value from a      *
+ * write operation only if the current value is zero.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_scratch_reg2_wz_u {
+	bdrkreg_t	lb_scratch_reg2_wz_regval;
+	struct  {
+		bdrkreg_t	srw_scratch_bits          :	64;
+	} lb_scratch_reg2_wz_fld_s;
+} lb_scratch_reg2_wz_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These one-bit registers are scratch registers. At a register's      *
+ * normal address, it is a simple storage location. At a register's     *
+ * Read-Set-If-Zero address, it returns the original contents and       *
+ * sets the bit if the original value is zero.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_scratch_reg3_rz_u {
+	bdrkreg_t	lb_scratch_reg3_rz_regval;
+	struct  {
+		bdrkreg_t	srr_scratch_bit           :	 1;
+		bdrkreg_t       srr_reserved              :     63;
+	} lb_scratch_reg3_rz_fld_s;
+} lb_scratch_reg3_rz_u_t;
+
+#else
+
+typedef union lb_scratch_reg3_rz_u {
+	bdrkreg_t	lb_scratch_reg3_rz_regval;
+	struct	{
+		bdrkreg_t	srr_reserved		  :	63;
+		bdrkreg_t	srr_scratch_bit		  :	 1;
+	} lb_scratch_reg3_rz_fld_s;
+} lb_scratch_reg3_rz_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  These one-bit registers are scratch registers. At a register's      *
+ * normal address, it is a simple storage location. At a register's     *
+ * Read-Set-If-Zero address, it returns the original contents and       *
+ * sets the bit if the original value is zero.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_scratch_reg4_rz_u {
+	bdrkreg_t	lb_scratch_reg4_rz_regval;
+	struct  {
+		bdrkreg_t	srr_scratch_bit           :	 1;
+		bdrkreg_t       srr_reserved              :     63;
+	} lb_scratch_reg4_rz_fld_s;
+} lb_scratch_reg4_rz_u_t;
+
+#else
+
+typedef union lb_scratch_reg4_rz_u {
+	bdrkreg_t	lb_scratch_reg4_rz_regval;
+	struct	{
+		bdrkreg_t	srr_reserved		  :	63;
+		bdrkreg_t	srr_scratch_bit		  :	 1;
+	} lb_scratch_reg4_rz_fld_s;
+} lb_scratch_reg4_rz_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains vector PIO parameters. A        *
+ * write to this register triggers the LB to send out a vector PIO      *
+ * request packet. Immediately after servicing a write request to the   *
+ * LB_VECTOR_PARMS register, the LB sends back a reply (i.e., the LB    *
+ * doesn't wait for the vector PIO operation to finish first). Three    *
+ * LB registers provide the contents for an outgoing vector PIO         *
+ * request packet. Software should wait until the BUSY bit in           *
+ * LB_VECTOR_PARMS is clear and then initialize all three of these      *
+ * registers before initiating a vector PIO operation. The three        *
+ * vector PIO registers are:                                            *
+ * LB_VECTOR_ROUTE                                                      *
+ * LB_VECTOR_DATA                                                       *
+ * LB_VECTOR_PARMS (should be written last)                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_vector_parms_u {
+	bdrkreg_t	lb_vector_parms_regval;
+	struct  {
+		bdrkreg_t	vp_type                   :	 1;
+		bdrkreg_t       vp_reserved_2             :      2;
+		bdrkreg_t       vp_address                :     21;
+		bdrkreg_t       vp_reserved_1             :      8;
+		bdrkreg_t       vp_write_id               :      8;
+		bdrkreg_t       vp_pio_id                 :     11;
+		bdrkreg_t       vp_reserved               :     12;
+		bdrkreg_t       vp_busy                   :      1;
+	} lb_vector_parms_fld_s;
+} lb_vector_parms_u_t;
+
+#else
+
+typedef union lb_vector_parms_u {
+	bdrkreg_t	lb_vector_parms_regval;
+	struct	{
+		bdrkreg_t	vp_busy			  :	 1;
+		bdrkreg_t	vp_reserved		  :	12;
+		bdrkreg_t	vp_pio_id		  :	11;
+		bdrkreg_t	vp_write_id		  :	 8;
+		bdrkreg_t	vp_reserved_1		  :	 8;
+		bdrkreg_t	vp_address		  :	21;
+		bdrkreg_t	vp_reserved_2		  :	 2;
+		bdrkreg_t	vp_type			  :	 1;
+	} lb_vector_parms_fld_s;
+} lb_vector_parms_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the vector PIO route. This is one of the 3   *
+ * vector PIO control registers.                                        *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_vector_route_u {
+	bdrkreg_t	lb_vector_route_regval;
+	struct  {
+		bdrkreg_t	vr_vector                 :	64;
+	} lb_vector_route_fld_s;
+} lb_vector_route_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the vector PIO write data. This is one of    *
+ * the 3 vector PIO control registers. The contents of this register    *
+ * also provide the data value to be sent in outgoing vector PIO read   *
+ * requests and vector PIO write replies.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_vector_data_u {
+	bdrkreg_t	lb_vector_data_regval;
+	struct  {
+		bdrkreg_t	vd_write_data             :	64;
+	} lb_vector_data_fld_s;
+} lb_vector_data_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains the vector PIO return status.   *
+ * Software should clear this register before launching a vector PIO    *
+ * request from the LB. The LB will not modify this register's value    *
+ * if an incoming reply packet encounters any kind of error. If an      *
+ * incoming reply packet does not encounter an error but the            *
+ * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit    *
+ * and leaves the other fields unchanged. The LB updates the values     *
+ * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if     *
+ * an incoming vector PIO reply packet does not encounter an error      *
+ * and the STATUS_VALID bit is clear; at the same time, the LB sets     *
+ * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and   *
+ * LB_VECTOR_READ_DATA registers.                                       *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_vector_status_u {
+	bdrkreg_t	lb_vector_status_regval;
+	struct  {
+		bdrkreg_t	vs_type                   :	 3;
+		bdrkreg_t       vs_address                :     21;
+		bdrkreg_t       vs_reserved               :      8;
+		bdrkreg_t       vs_write_id               :      8;
+		bdrkreg_t       vs_pio_id                 :     11;
+		bdrkreg_t       vs_source                 :     11;
+		bdrkreg_t       vs_overrun                :      1;
+		bdrkreg_t       vs_status_valid           :      1;
+	} lb_vector_status_fld_s;
+} lb_vector_status_u_t;
+
+#else
+
+typedef union lb_vector_status_u {
+	bdrkreg_t	lb_vector_status_regval;
+	struct	{
+		bdrkreg_t	vs_status_valid		  :	 1;
+		bdrkreg_t	vs_overrun		  :	 1;
+		bdrkreg_t	vs_source		  :	11;
+		bdrkreg_t	vs_pio_id		  :	11;
+		bdrkreg_t	vs_write_id		  :	 8;
+		bdrkreg_t	vs_reserved		  :	 8;
+		bdrkreg_t	vs_address		  :	21;
+		bdrkreg_t	vs_type			  :	 3;
+	} lb_vector_status_fld_s;
+} lb_vector_status_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the return vector PIO route. The LB will     *
+ * not modify this register's value if an incoming reply packet         *
+ * encounters any kind of error. The LB also will not modify this       *
+ * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS     *
+ * register is set when it receives an incoming vector PIO reply. The   *
+ * LB stores an incoming vector PIO reply packet's vector route flit    *
+ * in this register only if the packet does not encounter an error      *
+ * and the STATUS_VALID bit is clear.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_vector_return_u {
+	bdrkreg_t	lb_vector_return_regval;
+	struct  {
+		bdrkreg_t	vr_return_vector          :	64;
+	} lb_vector_return_fld_s;
+} lb_vector_return_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the vector PIO read data, if any. The LB     *
+ * will not modify this register's value if an incoming reply packet    *
+ * encounters any kind of error. The LB also will not modify this       *
+ * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS     *
+ * register is set when it receives an incoming vector PIO reply. The   *
+ * LB stores an incoming vector PIO reply packet's data flit in this    *
+ * register only if the packet does not encounter an error and the      *
+ * STATUS_VALID bit is clear.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union lb_vector_read_data_u {
+	bdrkreg_t	lb_vector_read_data_regval;
+	struct  {
+		bdrkreg_t	vrd_read_data             :	64;
+	} lb_vector_read_data_fld_s;
+} lb_vector_read_data_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains the vector PIO return status.   *
+ * Software should clear this register before launching a vector PIO    *
+ * request from the LB. The LB will not modify this register's value    *
+ * if an incoming reply packet encounters any kind of error. If an      *
+ * incoming reply packet does not encounter an error but the            *
+ * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit    *
+ * and leaves the other fields unchanged. The LB updates the values     *
+ * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if     *
+ * an incoming vector PIO reply packet does not encounter an error      *
+ * and the STATUS_VALID bit is clear; at the same time, the LB sets     *
+ * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and   *
+ * LB_VECTOR_READ_DATA registers.                                       *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union lb_vector_status_clear_u {
+	bdrkreg_t	lb_vector_status_clear_regval;
+	struct  {
+		bdrkreg_t	vsc_type                  :	 3;
+		bdrkreg_t       vsc_address               :     21;
+		bdrkreg_t       vsc_reserved              :      8;
+		bdrkreg_t       vsc_write_id              :      8;
+		bdrkreg_t       vsc_pio_id                :     11;
+		bdrkreg_t       vsc_source                :     11;
+		bdrkreg_t       vsc_overrun               :      1;
+		bdrkreg_t       vsc_status_valid          :      1;
+	} lb_vector_status_clear_fld_s;
+} lb_vector_status_clear_u_t;
+
+#else
+
+typedef union lb_vector_status_clear_u {
+	bdrkreg_t	lb_vector_status_clear_regval;
+	struct	{
+		bdrkreg_t	vsc_status_valid	  :	 1;
+		bdrkreg_t	vsc_overrun		  :	 1;
+		bdrkreg_t	vsc_source		  :	11;
+		bdrkreg_t	vsc_pio_id		  :	11;
+		bdrkreg_t	vsc_write_id		  :	 8;
+		bdrkreg_t	vsc_reserved		  :	 8;
+		bdrkreg_t	vsc_address		  :	21;
+		bdrkreg_t	vsc_type		  :	 3;
+	} lb_vector_status_clear_fld_s;
+} lb_vector_status_clear_u_t;
+
+#endif
+
+
+
+
+
+
+#endif /* _LANGUAGE_C */
+
+/************************************************************************
+ *                                                                      *
+ *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+
+#endif /* _ASM_SN_SN1_HUBLB_H */
diff --git a/include/asm-ia64/sn/sn1/hublb_next.h b/include/asm-ia64/sn/sn1/hublb_next.h
new file mode 100644
index 000000000..a0c8430f1
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hublb_next.h
@@ -0,0 +1,110 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBLB_NEXT_H
+#define _ASM_SN_SN1_HUBLB_NEXT_H
+
+/**********************************************************************
+
+ This contains some mask and shift values for LB defined as required
+ for compatibility.
+
+ **********************************************************************/
+
+#define LRI_SYSTEM_SIZE_SHFT        46
+#define LRI_SYSTEM_SIZE_MASK        (UINT64_CAST 0x3 << LRI_SYSTEM_SIZE_SHFT)
+#define LRI_NODEID_SHFT        32
+#define LRI_NODEID_MASK        (UINT64_CAST 0xff << LRI_NODEID_SHFT)/* Node ID    */
+#define LRI_CHIPID_SHFT		12
+#define LRI_CHIPID_MASK		(UINT64_CAST 0xffff << LRI_CHIPID_SHFT) /* should be 0x3012 */
+#define LRI_REV_SHFT        28
+#define LRI_REV_MASK        (UINT64_CAST 0xf << LRI_REV_SHFT)/* Chip revision    */
+
+/* Values for LRI_SYSTEM_SIZE */
+#define SYSTEM_SIZE_INVALID	0x3
+#define SYSTEM_SIZE_NMODE	0x2
+#define SYSTEM_SIZE_COARSE 	0x1
+#define SYSTEM_SIZE_SMALL	0x0
+
+/* In fine mode, each node is a region.  In coarse mode, there are
+ * 2 nodes per region.  In N-mode, there are 4 nodes per region. */
+#define NASID_TO_FINEREG_SHFT   0
+#define NASID_TO_COARSEREG_SHFT 1
+#define NASID_TO_NMODEREG_SHFT  2
+
+#define LR_LOCALRESET               (UINT64_CAST 1)
+/*
+ * LB_VECTOR_PARMS mask and shift definitions.
+ * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
+ */
+
+#define LVP_BUSY		(UINT64_CAST 1 << 63)
+#define LVP_PIOID_SHFT          40
+#define LVP_PIOID_MASK          (UINT64_CAST 0x7ff << 40)
+#define LVP_WRITEID_SHFT        32
+#define LVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define LVP_ADDRESS_MASK        (UINT64_CAST 0xfffff8)   /* Bits 23:3        */
+#define LVP_TYPE_SHFT           0
+#define LVP_TYPE_MASK           (UINT64_CAST 0x3)
+
+/* LB_VECTOR_STATUS mask and shift definitions */
+
+#define LVS_VALID               (UINT64_CAST 1 << 63)
+#define LVS_OVERRUN             (UINT64_CAST 1 << 62)
+#define LVS_TARGET_SHFT         51
+#define LVS_TARGET_MASK         (UINT64_CAST 0x7ff << 51)
+#define LVS_PIOID_SHFT          40
+#define LVS_PIOID_MASK          (UINT64_CAST 0x7ff << 40)
+#define LVS_WRITEID_SHFT        32
+#define LVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define LVS_ADDRESS_MASK        (UINT64_CAST 0xfffff8)   /* Bits 23:3     */
+#define LVS_TYPE_SHFT           0
+#define LVS_TYPE_MASK           (UINT64_CAST 0x7)
+#define LVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
+
+/* LB_RT_LOCAL_CTRL mask and shift definitions */
+
+#define LRLC_USE_INT_SHFT       32
+#define LRLC_USE_INT_MASK       (UINT64_CAST 1 << 32)
+#define LRLC_USE_INT            (UINT64_CAST 1 << 32)
+#define LRLC_GCLK_SHFT          28
+#define LRLC_GCLK_MASK          (UINT64_CAST 1 << 28)
+#define LRLC_GCLK               (UINT64_CAST 1 << 28)
+#define LRLC_GCLK_COUNT_SHFT    16
+#define LRLC_GCLK_COUNT_MASK    (UINT64_CAST 0x3ff << 16)
+#define LRLC_MAX_COUNT_SHFT     4
+#define LRLC_MAX_COUNT_MASK     (UINT64_CAST 0x3ff << 4)
+#define LRLC_GCLK_EN_SHFT       0
+#define LRLC_GCLK_EN_MASK       (UINT64_CAST 1)
+#define LRLC_GCLK_EN            (UINT64_CAST 1)
+
+/* LB_NODES_ABSENT mask and shift definitions */
+#define LNA_VALID_SHFT		15
+#define LNA_VALID_MASK		(UINT64_CAST 1 << LNA_VALID_SHFT)
+#define LNA_VALID		(UINT64_CAST 1 << LNA_VALID_SHFT)
+#define LNA_NODE_SHFT		0
+#define LNA_NODE_MASK		(UINT64_CAST 0xff << LNA_NODE_SHFT)
+
+/* LB_NODES_ABSENT has 4 identical sub-registers, on 16-bit boundaries */
+#define LNA_ENTRY_SHFT		16
+#define LNA_MAX_ENTRIES		4
+#define LNA_ADD(_reg, _n)	((_reg) = (_reg) << LNA_ENTRY_SHFT | \
+				 	LNA_VALID | (_n) << LNA_NODE_SHFT)
+
+#define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
+/* XXX IP35 doesn't support vector exchange:  scr. regs. do locks directly */
+#define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+
+#endif	/* _ASM_SN_SN1_HUBLB_NEXT_H */
diff --git a/include/asm-ia64/sn/sn1/hubmd.h b/include/asm-ia64/sn/sn1/hubmd.h
new file mode 100644
index 000000000..0f5bada86
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubmd.h
@@ -0,0 +1,2477 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBMD_H
+#define _ASM_SN_SN1_HUBMD_H
+
+
+/************************************************************************
+ *                                                                      *
+ *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
+ *                                                                      *
+ * This file is created by an automated script. Any (minimal) changes   *
+ * made manually to this  file should be made with care.                *
+ *                                                                      *
+ *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
+ *                                                                      *
+ ************************************************************************/
+
+
+#define    MD_CURRENT_CELL           0x00780000    /*
+                                                    * BDDIR, LREG, LBOOT,
+                                                    * RREG, RBOOT
+                                                    * protection and mask
+                                                    * for using Local
+                                                    * Access protection.
+                                                    */
+
+
+
+#define    MD_MEMORY_CONFIG          0x00780008    /*
+                                                    * Memory/Directory
+                                                    * DIMM control
+                                                    */
+
+
+
+#define    MD_ARBITRATION_CONTROL    0x00780010    /*
+                                                    * Arbitration
+                                                    * Parameters
+                                                    */
+
+
+
+#define    MD_MIG_CONFIG             0x00780018    /*
+                                                    * Page Migration
+                                                    * control
+                                                    */
+
+
+
+#define    MD_FANDOP_CAC_STAT0       0x00780020    /*
+                                                    * Fetch-and-op cache
+                                                    * 0 status
+                                                    */
+
+
+
+#define    MD_FANDOP_CAC_STAT1       0x00780028    /*
+                                                    * Fetch-and-op cache
+                                                    * 1 status
+                                                    */
+
+
+
+#define    MD_MISC0_ERROR            0x00780040    /*
+                                                    * Miscellaneous MD
+                                                    * error
+                                                    */
+
+
+
+#define    MD_MISC1_ERROR            0x00780048    /*
+                                                    * Miscellaneous MD
+                                                    * error
+                                                    */
+
+
+
+#define    MD_MISC1_ERROR_CLR        0x00780058    /*
+                                                    * Miscellaneous MD
+                                                    * error clear
+                                                    */
+
+
+
+#define    MD_OUTGOING_RP_QUEUE_SIZE 0x00780060    /*
+                                                    * MD outgoing reply
+                                                    * queues sizing
+                                                    */
+
+
+
+#define    MD_PERF_SEL0              0x00790000    /*
+                                                    * Selects events
+                                                    * monitored by
+                                                    * MD_PERF_CNT0
+                                                    */
+
+
+
+#define    MD_PERF_SEL1              0x00790008    /*
+                                                    * Selects events
+                                                    * monitored by
+                                                    * MD_PERF_CNT1
+                                                    */
+
+
+
+#define    MD_PERF_CNT0              0x00790010    /*
+                                                    * Performance counter
+                                                    * 0
+                                                    */
+
+
+
+#define    MD_PERF_CNT1              0x00790018    /*
+                                                    * Performance counter
+                                                    * 1
+                                                    */
+
+
+
+#define    MD_REFRESH_CONTROL        0x007A0000    /*
+                                                    * Memory/Directory
+                                                    * refresh control
+                                                    */
+
+
+
+#define    MD_JUNK_BUS_TIMING        0x007A0008    /* Junk Bus Timing        */
+
+
+
+#define    MD_LED0                   0x007A0010    /* Reads of 8-bit LED0    */
+
+
+
+#define    MD_LED1                   0x007A0018    /* Reads of 8-bit LED1    */
+
+
+
+#define    MD_LED2                   0x007A0020    /* Reads of 8-bit LED2    */
+
+
+
+#define    MD_LED3                   0x007A0028    /* Reads of 8-bit LED3    */
+
+
+
+#define    MD_BIST_CTL               0x007A0030    /*
+                                                    * BIST general
+                                                    * control
+                                                    */
+
+
+
+#define    MD_BIST_DATA              0x007A0038    /*
+                                                    * BIST initial data
+                                                    * pattern and
+                                                    * variation control
+                                                    */
+
+
+
+#define    MD_BIST_AB_ERR_ADDR       0x007A0040    /* BIST error address     */
+
+
+
+#define    MD_BIST_STATUS            0x007A0048    /* BIST status            */
+
+
+
+#define    MD_IB_DEBUG               0x007A0060    /* IB debug select        */
+
+
+
+#define    MD_DIR_CONFIG             0x007C0000    /*
+                                                    * Directory mode
+                                                    * control
+                                                    */
+
+
+
+#define    MD_DIR_ERROR              0x007C0010    /*
+                                                    * Directory DIMM
+                                                    * error
+                                                    */
+
+
+
+#define    MD_DIR_ERROR_CLR          0x007C0018    /*
+                                                    * Directory DIMM
+                                                    * error clear
+                                                    */
+
+
+
+#define    MD_PROTOCOL_ERROR         0x007C0020    /*
+                                                    * Directory protocol
+                                                    * error
+                                                    */
+
+
+
+#define    MD_PROTOCOL_ERR_CLR       0x007C0028    /*
+                                                    * Directory protocol
+                                                    * error clear
+                                                    */
+
+
+
+#define    MD_MIG_CANDIDATE          0x007C0030    /*
+                                                    * Page migration
+                                                    * candidate
+                                                    */
+
+
+
+#define    MD_MIG_CANDIDATE_CLR      0x007C0038    /*
+                                                    * Page migration
+                                                    * candidate clear
+                                                    */
+
+
+
+#define    MD_MIG_DIFF_THRESH        0x007C0040    /*
+                                                    * Page migration
+                                                    * count difference
+                                                    * threshold
+                                                    */
+
+
+
+#define    MD_MIG_VALUE_THRESH       0x007C0048    /*
+                                                    * Page migration
+                                                    * count absolute
+                                                    * threshold
+                                                    */
+
+
+
+#define    MD_OUTGOING_RQ_QUEUE_SIZE 0x007C0050    /*
+                                                    * MD outgoing request
+                                                    * queues sizing
+                                                    */
+
+
+
+#define    MD_BIST_DB_ERR_DATA       0x007C0058    /*
+                                                    * BIST directory
+                                                    * error data
+                                                    */
+
+
+
+#define    MD_DB_DEBUG               0x007C0060    /* DB debug select        */
+
+
+
+#define    MD_MB_ECC_CONFIG          0x007E0000    /*
+                                                    * Data ECC
+                                                    * Configuration
+                                                    */
+
+
+
+#define    MD_MEM_ERROR              0x007E0010    /* Memory DIMM error      */
+
+
+
+#define    MD_MEM_ERROR_CLR          0x007E0018    /*
+                                                    * Memory DIMM error
+                                                    * clear
+                                                    */
+
+
+
+#define    MD_BIST_MB_ERR_DATA_0     0x007E0020    /*
+                                                    * BIST memory error
+                                                    * data
+                                                    */
+
+
+
+#define    MD_BIST_MB_ERR_DATA_1     0x007E0028    /*
+                                                    * BIST memory error
+                                                    * data
+                                                    */
+
+
+
+#define    MD_BIST_MB_ERR_DATA_2     0x007E0030    /*
+                                                    * BIST memory error
+                                                    * data
+                                                    */
+
+
+
+#define    MD_BIST_MB_ERR_DATA_3     0x007E0038    /*
+                                                    * BIST memory error
+                                                    * data
+                                                    */
+
+
+
+#define    MD_MB_DEBUG               0x007E0040    /* MB debug select        */
+
+
+
+
+
+#ifdef _LANGUAGE_C
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register shows which regions are in the current   *
+ * cell. If a region has its bit set in this register, then it uses     *
+ * the Local Access protection in the directory instead of the          *
+ * separate per-region protection (which would cause a small            *
+ * performance penalty). In addition, writeback and write reply         *
+ * commands from outside the current cell will always check the         *
+ * directory protection before writing data to memory. Writeback and    *
+ * write reply commands from inside the current cell will write         *
+ * memory regardless of the protection value.                           *
+ * This register is also used as the access-rights bit-vector for       *
+ * most of the ASIC-special (HSpec) portion of the address space. It    *
+ * covers the BDDIR, LREG, LBOOT, RREG, and RBOOT spaces. It does not   *
+ * cover the UALIAS and BDECC spaces, as they are covered by the        *
+ * protection in the directory. If a bit in the bit-vector is set,      *
+ * the region corresponding to that bit has read/write permission on    *
+ * these spaces. If the bit is clear, then that region has read-only    *
+ * access to these spaces (except for LREG/RREG which have no access    *
+ * when the bit is clear).                                              *
+ * The granularity of a region is set by the REGION_SIZE register in    *
+ * the NI local register space.                                         *
+ * NOTE: This means that no processor outside the current cell can      *
+ * write into the BDDIR, LREG, LBOOT, RREG, or RBOOT spaces.            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union md_current_cell_u {
+	bdrkreg_t	md_current_cell_regval;
+	struct  {
+		bdrkreg_t	cc_hspec_prot             :	64;
+	} md_current_cell_fld_s;
+} md_current_cell_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains three sets of information.      *
+ * The first set describes the size and configuration of DIMMs that     *
+ * are plugged into a system, the second set controls which set of      *
+ * protection checks are performed on each access and the third set     *
+ * controls various DDR SDRAM timing parameters.                        *
+ * In order to config a DIMM bank, three fields must be initialized:    *
+ * BANK_SIZE, DRAM_WIDTH, and BANK_ENABLE. The BANK_SIZE field sets     *
+ * the address range that the MD unit will accept for that DIMM bank.   *
+ * All addresses larger than the specified size will return errors on   *
+ * access. In order to read from a DIMM bank, Bedrock must know         *
+ * whether or not the bank contains x4 or x8/x16 DRAM. The operating    *
+ * system must query the System Controller for this information and     *
+ * then set the DRAM_WIDTH field accordingly. The BANK_ENABLE field     *
+ * can be used to individually enable the two physical banks located    *
+ * on each DIMM bank.                                                   *
+ * The contents of this register are preserved through soft-resets.     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_memory_config_u {
+	bdrkreg_t	md_memory_config_regval;
+	struct  {
+		bdrkreg_t	mc_dimm0_bank_enable      :	 2;
+		bdrkreg_t       mc_reserved_7             :      1;
+		bdrkreg_t       mc_dimm0_dram_width       :      1;
+		bdrkreg_t       mc_dimm0_bank_size        :      4;
+		bdrkreg_t       mc_dimm1_bank_enable      :      2;
+		bdrkreg_t       mc_reserved_6             :      1;
+		bdrkreg_t       mc_dimm1_dram_width       :      1;
+		bdrkreg_t       mc_dimm1_bank_size        :      4;
+                bdrkreg_t       mc_dimm2_bank_enable      :      2;
+                bdrkreg_t       mc_reserved_5             :      1;
+                bdrkreg_t       mc_dimm2_dram_width       :      1;
+                bdrkreg_t       mc_dimm2_bank_size        :      4;
+                bdrkreg_t       mc_dimm3_bank_enable      :      2;
+                bdrkreg_t       mc_reserved_4             :      1;
+                bdrkreg_t       mc_dimm3_dram_width       :      1;
+                bdrkreg_t       mc_dimm3_bank_size        :      4;
+                bdrkreg_t       mc_dimm0_sel              :      2;
+                bdrkreg_t       mc_reserved_3             :     10;
+                bdrkreg_t       mc_cc_enable              :      1;
+                bdrkreg_t       mc_io_prot_en             :      1;
+                bdrkreg_t       mc_io_prot_ignore         :      1;
+                bdrkreg_t       mc_cpu_prot_ignore        :      1;
+                bdrkreg_t       mc_db_neg_edge            :      1;
+                bdrkreg_t       mc_phase_delay            :      1;
+                bdrkreg_t       mc_delay_mux_sel          :      2;
+                bdrkreg_t       mc_sample_time            :      2;
+                bdrkreg_t       mc_reserved_2             :      2;
+                bdrkreg_t       mc_mb_neg_edge            :      3;
+                bdrkreg_t       mc_reserved_1             :      1;
+                bdrkreg_t       mc_rcd_config             :      1;
+                bdrkreg_t       mc_rp_config              :      1;
+                bdrkreg_t       mc_reserved               :      2;
+	} md_memory_config_fld_s;
+} md_memory_config_u_t;
+
+#else
+
+typedef union md_memory_config_u {
+	bdrkreg_t	md_memory_config_regval;
+	struct	{
+		bdrkreg_t	mc_reserved		  :	 2;
+		bdrkreg_t	mc_rp_config		  :	 1;
+		bdrkreg_t	mc_rcd_config		  :	 1;
+		bdrkreg_t	mc_reserved_1		  :	 1;
+		bdrkreg_t	mc_mb_neg_edge		  :	 3;
+		bdrkreg_t	mc_reserved_2		  :	 2;
+		bdrkreg_t	mc_sample_time		  :	 2;
+		bdrkreg_t	mc_delay_mux_sel	  :	 2;
+		bdrkreg_t	mc_phase_delay		  :	 1;
+		bdrkreg_t	mc_db_neg_edge		  :	 1;
+		bdrkreg_t	mc_cpu_prot_ignore	  :	 1;
+		bdrkreg_t	mc_io_prot_ignore	  :	 1;
+		bdrkreg_t	mc_io_prot_en		  :	 1;
+		bdrkreg_t	mc_cc_enable		  :	 1;
+		bdrkreg_t	mc_reserved_3		  :	10;
+		bdrkreg_t	mc_dimm0_sel		  :	 2;
+		bdrkreg_t	mc_dimm3_bank_size	  :	 4;
+		bdrkreg_t	mc_dimm3_dram_width	  :	 1;
+		bdrkreg_t	mc_reserved_4		  :	 1;
+		bdrkreg_t	mc_dimm3_bank_enable	  :	 2;
+		bdrkreg_t	mc_dimm2_bank_size	  :	 4;
+		bdrkreg_t	mc_dimm2_dram_width	  :	 1;
+		bdrkreg_t	mc_reserved_5		  :	 1;
+		bdrkreg_t	mc_dimm2_bank_enable	  :	 2;
+		bdrkreg_t	mc_dimm1_bank_size	  :	 4;
+		bdrkreg_t	mc_dimm1_dram_width	  :	 1;
+		bdrkreg_t	mc_reserved_6		  :	 1;
+		bdrkreg_t	mc_dimm1_bank_enable	  :	 2;
+		bdrkreg_t	mc_dimm0_bank_size	  :	 4;
+		bdrkreg_t	mc_dimm0_dram_width	  :	 1;
+		bdrkreg_t	mc_reserved_7		  :	 1;
+		bdrkreg_t	mc_dimm0_bank_enable	  :	 2;
+	} md_memory_config_fld_s;
+} md_memory_config_u_t;
+
+#endif
+
+
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_arbitration_control_u {
+	bdrkreg_t	md_arbitration_control_regval;
+	struct  {
+		bdrkreg_t	ac_reply_guar             :	 4;
+		bdrkreg_t       ac_write_guar             :      4;
+		bdrkreg_t       ac_reserved               :     56;
+	} md_arbitration_control_fld_s;
+} md_arbitration_control_u_t;
+
+#else
+
+typedef union md_arbitration_control_u {
+	bdrkreg_t	md_arbitration_control_regval;
+	struct	{
+		bdrkreg_t	ac_reserved		  :	56;
+		bdrkreg_t	ac_write_guar		  :	 4;
+		bdrkreg_t	ac_reply_guar		  :	 4;
+	} md_arbitration_control_fld_s;
+} md_arbitration_control_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains page migration control fields.                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mig_config_u {
+	bdrkreg_t	md_mig_config_regval;
+	struct  {
+		bdrkreg_t	mc_mig_interval           :	10;
+		bdrkreg_t       mc_reserved_2             :      6;
+		bdrkreg_t       mc_mig_node_mask          :      8;
+		bdrkreg_t       mc_reserved_1             :      8;
+		bdrkreg_t       mc_mig_enable             :      1;
+		bdrkreg_t       mc_reserved               :     31;
+	} md_mig_config_fld_s;
+} md_mig_config_u_t;
+
+#else
+
+typedef union md_mig_config_u {
+	bdrkreg_t	md_mig_config_regval;
+	struct	{
+		bdrkreg_t	mc_reserved		  :	31;
+		bdrkreg_t	mc_mig_enable		  :	 1;
+		bdrkreg_t	mc_reserved_1		  :	 8;
+		bdrkreg_t	mc_mig_node_mask	  :	 8;
+		bdrkreg_t	mc_reserved_2		  :	 6;
+		bdrkreg_t	mc_mig_interval		  :	10;
+	} md_mig_config_fld_s;
+} md_mig_config_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Each register contains the valid bit and address of the entry in    *
+ * the fetch-and-op for cache 0 (or 1).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_fandop_cac_stat0_u {
+	bdrkreg_t	md_fandop_cac_stat0_regval;
+	struct  {
+		bdrkreg_t	fcs_reserved_1            :	 6;
+		bdrkreg_t       fcs_addr                  :     27;
+		bdrkreg_t       fcs_reserved              :     30;
+		bdrkreg_t       fcs_valid                 :      1;
+	} md_fandop_cac_stat0_fld_s;
+} md_fandop_cac_stat0_u_t;
+
+#else
+
+typedef union md_fandop_cac_stat0_u {
+	bdrkreg_t	md_fandop_cac_stat0_regval;
+	struct	{
+		bdrkreg_t	fcs_valid		  :	 1;
+		bdrkreg_t	fcs_reserved		  :	30;
+		bdrkreg_t	fcs_addr		  :	27;
+		bdrkreg_t	fcs_reserved_1		  :	 6;
+	} md_fandop_cac_stat0_fld_s;
+} md_fandop_cac_stat0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Each register contains the valid bit and address of the entry in    *
+ * the fetch-and-op for cache 0 (or 1).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_fandop_cac_stat1_u {
+	bdrkreg_t	md_fandop_cac_stat1_regval;
+	struct  {
+		bdrkreg_t	fcs_reserved_1            :	 6;
+		bdrkreg_t       fcs_addr                  :     27;
+		bdrkreg_t       fcs_reserved              :     30;
+		bdrkreg_t       fcs_valid                 :      1;
+	} md_fandop_cac_stat1_fld_s;
+} md_fandop_cac_stat1_u_t;
+
+#else
+
+typedef union md_fandop_cac_stat1_u {
+	bdrkreg_t	md_fandop_cac_stat1_regval;
+	struct	{
+		bdrkreg_t	fcs_valid		  :	 1;
+		bdrkreg_t	fcs_reserved		  :	30;
+		bdrkreg_t	fcs_addr		  :	27;
+		bdrkreg_t	fcs_reserved_1		  :	 6;
+	} md_fandop_cac_stat1_fld_s;
+} md_fandop_cac_stat1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Contains a number of fields to capture various         *
+ * random memory/directory errors. For each 2-bit field, the LSB        *
+ * indicates that additional information has been captured for the      *
+ * error and the MSB indicates overrun, thus:                           *
+ *  x1: bits 51...0 of this register contain additional information     *
+ * for the message that caused this error                               *
+ *  1x: overrun occurred                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_misc0_error_u {
+	bdrkreg_t	md_misc0_error_regval;
+	struct	{
+		bdrkreg_t	me_command		  :	 7;
+                bdrkreg_t       me_reserved_4             :      1;
+                bdrkreg_t       me_source                 :     11;
+                bdrkreg_t       me_reserved_3             :      1;
+                bdrkreg_t       me_suppl                  :     11;
+                bdrkreg_t       me_reserved_2             :      1;
+                bdrkreg_t       me_virtual_channel        :      2;
+                bdrkreg_t       me_reserved_1             :      2;
+                bdrkreg_t       me_tail                   :      1;
+                bdrkreg_t       me_reserved               :     11;
+                bdrkreg_t       me_xb_error               :      4;
+                bdrkreg_t       me_bad_partial_data       :      2;
+                bdrkreg_t       me_missing_dv             :      2;
+                bdrkreg_t       me_short_pack             :      2;
+                bdrkreg_t       me_long_pack              :      2;
+                bdrkreg_t       me_ill_msg                :      2;
+                bdrkreg_t       me_ill_revision           :      2;
+	} md_misc0_error_fld_s;
+} md_misc0_error_u_t;
+
+#else
+
+typedef union md_misc0_error_u {
+	bdrkreg_t	md_misc0_error_regval;
+	struct  {
+		bdrkreg_t	me_ill_revision           :	 2;
+		bdrkreg_t	me_ill_msg                :	 2;
+		bdrkreg_t	me_long_pack              :	 2;
+		bdrkreg_t	me_short_pack             :	 2;
+		bdrkreg_t	me_missing_dv             :	 2;
+		bdrkreg_t	me_bad_partial_data       :	 2;
+		bdrkreg_t	me_xb_error               :	 4;
+		bdrkreg_t	me_reserved               :	11;
+		bdrkreg_t	me_tail                   :	 1;
+		bdrkreg_t	me_reserved_1             :	 2;
+		bdrkreg_t	me_virtual_channel        :	 2;
+		bdrkreg_t	me_reserved_2             :	 1;
+		bdrkreg_t	me_suppl                  :	11;
+		bdrkreg_t	me_reserved_3             :	 1;
+		bdrkreg_t	me_source                 :	11;
+		bdrkreg_t	me_reserved_4             :	 1;
+		bdrkreg_t	me_command                :	 7;
+	} md_misc0_error_fld_s;
+} md_misc0_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Address for error captured in MISC0_ERROR. Error valid bits are     *
+ * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be    *
+ * read sequentially without missing any errors).                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_misc1_error_u {
+	bdrkreg_t	md_misc1_error_regval;
+	struct  {
+		bdrkreg_t	me_reserved_1             :	 3;
+		bdrkreg_t       me_address                :     38;
+		bdrkreg_t       me_reserved               :      7;
+		bdrkreg_t       me_xb_error               :      4;
+		bdrkreg_t       me_bad_partial_data       :      2;
+		bdrkreg_t       me_missing_dv             :      2;
+		bdrkreg_t       me_short_pack             :      2;
+		bdrkreg_t       me_long_pack              :      2;
+		bdrkreg_t       me_ill_msg                :      2;
+		bdrkreg_t       me_ill_revision           :      2;
+	} md_misc1_error_fld_s;
+} md_misc1_error_u_t;
+
+#else
+
+typedef union md_misc1_error_u {
+	bdrkreg_t	md_misc1_error_regval;
+	struct	{
+		bdrkreg_t	me_ill_revision		  :	 2;
+		bdrkreg_t	me_ill_msg		  :	 2;
+		bdrkreg_t	me_long_pack		  :	 2;
+		bdrkreg_t	me_short_pack		  :	 2;
+		bdrkreg_t	me_missing_dv		  :	 2;
+		bdrkreg_t	me_bad_partial_data	  :	 2;
+		bdrkreg_t	me_xb_error		  :	 4;
+		bdrkreg_t	me_reserved		  :	 7;
+		bdrkreg_t	me_address		  :	38;
+		bdrkreg_t	me_reserved_1		  :	 3;
+	} md_misc1_error_fld_s;
+} md_misc1_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Address for error captured in MISC0_ERROR. Error valid bits are     *
+ * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be    *
+ * read sequentially without missing any errors).                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_misc1_error_clr_u {
+	bdrkreg_t	md_misc1_error_clr_regval;
+	struct  {
+		bdrkreg_t	mec_reserved_1            :	 3;
+		bdrkreg_t       mec_address               :     38;
+		bdrkreg_t       mec_reserved              :      7;
+		bdrkreg_t       mec_xb_error              :      4;
+		bdrkreg_t       mec_bad_partial_data      :      2;
+		bdrkreg_t       mec_missing_dv            :      2;
+		bdrkreg_t       mec_short_pack            :      2;
+		bdrkreg_t       mec_long_pack             :      2;
+		bdrkreg_t       mec_ill_msg               :      2;
+		bdrkreg_t       mec_ill_revision          :      2;
+	} md_misc1_error_clr_fld_s;
+} md_misc1_error_clr_u_t;
+
+#else
+
+typedef union md_misc1_error_clr_u {
+	bdrkreg_t	md_misc1_error_clr_regval;
+	struct	{
+		bdrkreg_t	mec_ill_revision	  :	 2;
+		bdrkreg_t	mec_ill_msg		  :	 2;
+		bdrkreg_t	mec_long_pack		  :	 2;
+		bdrkreg_t	mec_short_pack		  :	 2;
+		bdrkreg_t	mec_missing_dv		  :	 2;
+		bdrkreg_t	mec_bad_partial_data	  :	 2;
+		bdrkreg_t	mec_xb_error		  :	 4;
+		bdrkreg_t	mec_reserved		  :	 7;
+		bdrkreg_t	mec_address		  :	38;
+		bdrkreg_t	mec_reserved_1		  :	 3;
+	} md_misc1_error_clr_fld_s;
+} md_misc1_error_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  The MD no longer allows for arbitrarily sizing the     *
+ * reply queues, so all of the fields in this register are read-only    *
+ * and contain the reset default value of 12 for the MOQHs (for         *
+ * headers) and 24 for the MOQDs (for data).                            *
+ * Reading from this register returns the values currently held in      *
+ * the MD's credit counters. Writing to the register resets the         *
+ * counters to the default reset values specified in the table below.   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_outgoing_rp_queue_size_u {
+	bdrkreg_t	md_outgoing_rp_queue_size_regval;
+	struct  {
+		bdrkreg_t	orqs_reserved_6           :	 8;
+		bdrkreg_t       orqs_moqh_p0_rp_size      :      4;
+		bdrkreg_t       orqs_reserved_5           :      4;
+		bdrkreg_t       orqs_moqh_p1_rp_size      :      4;
+		bdrkreg_t       orqs_reserved_4           :      4;
+		bdrkreg_t       orqs_moqh_np_rp_size      :      4;
+		bdrkreg_t       orqs_reserved_3           :      4;
+		bdrkreg_t       orqs_moqd_pi0_rp_size     :      5;
+		bdrkreg_t       orqs_reserved_2           :      3;
+		bdrkreg_t       orqs_moqd_pi1_rp_size     :      5;
+		bdrkreg_t       orqs_reserved_1           :      3;
+		bdrkreg_t       orqs_moqd_np_rp_size      :      5;
+		bdrkreg_t       orqs_reserved             :     11;
+	} md_outgoing_rp_queue_size_fld_s;
+} md_outgoing_rp_queue_size_u_t;
+
+#else
+
+typedef union md_outgoing_rp_queue_size_u {
+	bdrkreg_t	md_outgoing_rp_queue_size_regval;
+	struct	{
+		bdrkreg_t	orqs_reserved		  :	11;
+		bdrkreg_t	orqs_moqd_np_rp_size	  :	 5;
+		bdrkreg_t	orqs_reserved_1		  :	 3;
+		bdrkreg_t	orqs_moqd_pi1_rp_size	  :	 5;
+		bdrkreg_t	orqs_reserved_2		  :	 3;
+		bdrkreg_t	orqs_moqd_pi0_rp_size	  :	 5;
+		bdrkreg_t	orqs_reserved_3		  :	 4;
+		bdrkreg_t	orqs_moqh_np_rp_size	  :	 4;
+		bdrkreg_t	orqs_reserved_4		  :	 4;
+		bdrkreg_t	orqs_moqh_p1_rp_size	  :	 4;
+		bdrkreg_t	orqs_reserved_5		  :	 4;
+		bdrkreg_t	orqs_moqh_p0_rp_size	  :	 4;
+		bdrkreg_t	orqs_reserved_6		  :	 8;
+	} md_outgoing_rp_queue_size_fld_s;
+} md_outgoing_rp_queue_size_u_t;
+
+#endif
+
+
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_perf_sel0_u {
+	bdrkreg_t	md_perf_sel0_regval;
+	struct  {
+		bdrkreg_t	ps_cnt_mode               :	 2;
+		bdrkreg_t       ps_reserved_2             :      2;
+		bdrkreg_t       ps_activity               :      4;
+		bdrkreg_t       ps_source                 :      7;
+		bdrkreg_t       ps_reserved_1             :      1;
+		bdrkreg_t       ps_channel                :      4;
+		bdrkreg_t       ps_command                :     40;
+		bdrkreg_t       ps_reserved               :      3;
+		bdrkreg_t       ps_interrupt              :      1;
+	} md_perf_sel0_fld_s;
+} md_perf_sel0_u_t;
+
+#else
+
+typedef union md_perf_sel0_u {
+	bdrkreg_t	md_perf_sel0_regval;
+	struct	{
+		bdrkreg_t	ps_interrupt		  :	 1;
+		bdrkreg_t	ps_reserved		  :	 3;
+		bdrkreg_t	ps_command		  :	40;
+		bdrkreg_t	ps_channel		  :	 4;
+		bdrkreg_t	ps_reserved_1		  :	 1;
+		bdrkreg_t	ps_source		  :	 7;
+		bdrkreg_t	ps_activity		  :	 4;
+		bdrkreg_t	ps_reserved_2		  :	 2;
+		bdrkreg_t	ps_cnt_mode		  :	 2;
+	} md_perf_sel0_fld_s;
+} md_perf_sel0_u_t;
+
+#endif
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_perf_sel1_u {
+	bdrkreg_t	md_perf_sel1_regval;
+	struct  {
+		bdrkreg_t	ps_cnt_mode               :	 2;
+		bdrkreg_t       ps_reserved_2             :      2;
+		bdrkreg_t       ps_activity               :      4;
+		bdrkreg_t       ps_source                 :      7;
+		bdrkreg_t       ps_reserved_1             :      1;
+		bdrkreg_t       ps_channel                :      4;
+		bdrkreg_t       ps_command                :     40;
+		bdrkreg_t       ps_reserved               :      3;
+		bdrkreg_t       ps_interrupt              :      1;
+	} md_perf_sel1_fld_s;
+} md_perf_sel1_u_t;
+
+#else
+
+typedef union md_perf_sel1_u {
+	bdrkreg_t	md_perf_sel1_regval;
+	struct	{
+		bdrkreg_t	ps_interrupt		  :	 1;
+		bdrkreg_t	ps_reserved		  :	 3;
+		bdrkreg_t	ps_command		  :	40;
+		bdrkreg_t	ps_channel		  :	 4;
+		bdrkreg_t	ps_reserved_1		  :	 1;
+		bdrkreg_t	ps_source		  :	 7;
+		bdrkreg_t	ps_activity		  :	 4;
+		bdrkreg_t	ps_reserved_2		  :	 2;
+		bdrkreg_t	ps_cnt_mode		  :	 2;
+	} md_perf_sel1_fld_s;
+} md_perf_sel1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Performance counter.                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_perf_cnt0_u {
+	bdrkreg_t	md_perf_cnt0_regval;
+	struct  {
+		bdrkreg_t	pc_perf_cnt               :	41;
+		bdrkreg_t	pc_reserved		  :	23;
+	} md_perf_cnt0_fld_s;
+} md_perf_cnt0_u_t;
+
+#else
+
+typedef union md_perf_cnt0_u {
+	bdrkreg_t	md_perf_cnt0_regval;
+	struct	{
+		bdrkreg_t	pc_reserved		  :	23;
+		bdrkreg_t	pc_perf_cnt		  :	41;
+	} md_perf_cnt0_fld_s;
+} md_perf_cnt0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Performance counter.                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_perf_cnt1_u {
+	bdrkreg_t	md_perf_cnt1_regval;
+	struct  {
+		bdrkreg_t	pc_perf_cnt               :	41;
+		bdrkreg_t	pc_reserved		  :	23;
+	} md_perf_cnt1_fld_s;
+} md_perf_cnt1_u_t;
+
+#else
+
+typedef union md_perf_cnt1_u {
+	bdrkreg_t	md_perf_cnt1_regval;
+	struct	{
+		bdrkreg_t	pc_reserved		  :	23;
+		bdrkreg_t	pc_perf_cnt		  :	41;
+	} md_perf_cnt1_fld_s;
+} md_perf_cnt1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register contains the control for                 *
+ * memory/directory refresh. Once the MEMORY_CONFIG register contains   *
+ * the correct DIMM information, the hardware takes care of             *
+ * refreshing all the banks in the system. Therefore, the value in      *
+ * the counter threshold is corresponds exactly to the refresh value    *
+ * required by the SDRAM parts (expressed in Bedrock clock cycles).     *
+ * The refresh will execute whenever there is a free cycle and there    *
+ * are still banks that have not been refreshed in the current          *
+ * window. If the window expires with banks still waiting to be         *
+ * refreshed, all other transactions are halted until the banks are     *
+ * refreshed.                                                           *
+ * The upper order bit contains an enable, which may be needed for      *
+ * correct initialization of the DIMMs (according to the specs, the     *
+ * first operation to the DIMMs should be a mode register write, not    *
+ * a refresh, so this bit is cleared on reset) and is also useful for   *
+ * diagnostic purposes.                                                 *
+ * For the SDRAM parts used by Bedrock, 4096 refreshes need to be       *
+ * issued during every 64 ms window, resulting in a refresh threshold   *
+ * of 3125 Bedrock cycles.                                              *
+ * The ENABLE and CNT_THRESH fields of this register are preserved      *
+ * through soft-resets.                                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_refresh_control_u {
+	bdrkreg_t	md_refresh_control_regval;
+	struct  {
+		bdrkreg_t	rc_cnt_thresh             :	12;
+		bdrkreg_t       rc_counter                :     12;
+		bdrkreg_t       rc_reserved               :     39;
+		bdrkreg_t       rc_enable                 :      1;
+	} md_refresh_control_fld_s;
+} md_refresh_control_u_t;
+
+#else
+
+typedef union md_refresh_control_u {
+	bdrkreg_t	md_refresh_control_regval;
+	struct	{
+		bdrkreg_t	rc_enable		  :	 1;
+		bdrkreg_t	rc_reserved		  :	39;
+		bdrkreg_t	rc_counter		  :	12;
+		bdrkreg_t	rc_cnt_thresh		  :	12;
+	} md_refresh_control_fld_s;
+} md_refresh_control_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls the read and write timing for Flash PROM,    *
+ * UART and Synergy junk bus devices.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_junk_bus_timing_u {
+	bdrkreg_t	md_junk_bus_timing_regval;
+	struct  {
+		bdrkreg_t	jbt_fprom_setup_hold      :	 8;
+		bdrkreg_t       jbt_fprom_enable          :      8;
+		bdrkreg_t       jbt_uart_setup_hold       :      8;
+		bdrkreg_t       jbt_uart_enable           :      8;
+		bdrkreg_t       jbt_synergy_setup_hold    :      8;
+		bdrkreg_t       jbt_synergy_enable        :      8;
+		bdrkreg_t       jbt_reserved              :     16;
+	} md_junk_bus_timing_fld_s;
+} md_junk_bus_timing_u_t;
+
+#else
+
+typedef union md_junk_bus_timing_u {
+	bdrkreg_t	md_junk_bus_timing_regval;
+	struct	{
+		bdrkreg_t	jbt_reserved		  :	16;
+		bdrkreg_t	jbt_synergy_enable	  :	 8;
+		bdrkreg_t	jbt_synergy_setup_hold	  :	 8;
+		bdrkreg_t	jbt_uart_enable		  :	 8;
+		bdrkreg_t	jbt_uart_setup_hold	  :	 8;
+		bdrkreg_t	jbt_fprom_enable	  :	 8;
+		bdrkreg_t	jbt_fprom_setup_hold	  :	 8;
+	} md_junk_bus_timing_fld_s;
+} md_junk_bus_timing_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Each of these addresses allows the value on one 8-bit bank of       *
+ * LEDs to be read.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_led0_u {
+	bdrkreg_t	md_led0_regval;
+	struct  {
+		bdrkreg_t	l_data                    :	 8;
+		bdrkreg_t       l_reserved                :     56;
+	} md_led0_fld_s;
+} md_led0_u_t;
+
+#else
+
+typedef union md_led0_u {
+	bdrkreg_t	md_led0_regval;
+	struct	{
+		bdrkreg_t	l_reserved		  :	56;
+		bdrkreg_t	l_data			  :	 8;
+	} md_led0_fld_s;
+} md_led0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Each of these addresses allows the value on one 8-bit bank of       *
+ * LEDs to be read.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_led1_u {
+	bdrkreg_t	md_led1_regval;
+	struct  {
+		bdrkreg_t	l_data                    :	 8;
+		bdrkreg_t       l_reserved                :     56;
+	} md_led1_fld_s;
+} md_led1_u_t;
+
+#else
+
+typedef union md_led1_u {
+	bdrkreg_t	md_led1_regval;
+	struct	{
+		bdrkreg_t	l_reserved		  :	56;
+		bdrkreg_t	l_data			  :	 8;
+	} md_led1_fld_s;
+} md_led1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Each of these addresses allows the value on one 8-bit bank of       *
+ * LEDs to be read.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_led2_u {
+	bdrkreg_t	md_led2_regval;
+	struct  {
+		bdrkreg_t	l_data                    :	 8;
+		bdrkreg_t       l_reserved                :     56;
+	} md_led2_fld_s;
+} md_led2_u_t;
+
+#else
+
+typedef union md_led2_u {
+	bdrkreg_t	md_led2_regval;
+	struct	{
+		bdrkreg_t	l_reserved		  :	56;
+		bdrkreg_t	l_data			  :	 8;
+	} md_led2_fld_s;
+} md_led2_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Each of these addresses allows the value on one 8-bit bank of       *
+ * LEDs to be read.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_led3_u {
+	bdrkreg_t	md_led3_regval;
+	struct  {
+		bdrkreg_t	l_data                    :	 8;
+		bdrkreg_t       l_reserved                :     56;
+	} md_led3_fld_s;
+} md_led3_u_t;
+
+#else
+
+typedef union md_led3_u {
+	bdrkreg_t	md_led3_regval;
+	struct	{
+		bdrkreg_t	l_reserved		  :	56;
+		bdrkreg_t	l_data			  :	 8;
+	} md_led3_fld_s;
+} md_led3_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Core control for the BIST function. Start and stop BIST at any      *
+ * time.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_ctl_u {
+	bdrkreg_t	md_bist_ctl_regval;
+	struct  {
+		bdrkreg_t	bc_bist_start             :	 1;
+		bdrkreg_t       bc_bist_stop              :      1;
+		bdrkreg_t       bc_bist_reset             :      1;
+		bdrkreg_t       bc_reserved_1             :      1;
+		bdrkreg_t       bc_bank_num               :      1;
+		bdrkreg_t       bc_dimm_num               :      2;
+		bdrkreg_t       bc_reserved               :     57;
+	} md_bist_ctl_fld_s;
+} md_bist_ctl_u_t;
+
+#else
+
+typedef union md_bist_ctl_u {
+	bdrkreg_t	md_bist_ctl_regval;
+	struct	{
+		bdrkreg_t	bc_reserved		  :	57;
+		bdrkreg_t	bc_dimm_num		  :	 2;
+		bdrkreg_t	bc_bank_num		  :	 1;
+		bdrkreg_t	bc_reserved_1		  :	 1;
+		bdrkreg_t	bc_bist_reset		  :	 1;
+		bdrkreg_t	bc_bist_stop		  :	 1;
+		bdrkreg_t	bc_bist_start		  :	 1;
+	} md_bist_ctl_fld_s;
+} md_bist_ctl_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contain the initial BIST data nibble and the 4-bit data control     *
+ * field..                                                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_data_u {
+	bdrkreg_t	md_bist_data_regval;
+	struct  {
+		bdrkreg_t	bd_bist_data              :	 4;
+		bdrkreg_t	bd_bist_nibble		  :	 1;
+		bdrkreg_t       bd_bist_byte              :      1;
+		bdrkreg_t       bd_bist_cycle             :      1;
+		bdrkreg_t       bd_bist_write             :      1;
+		bdrkreg_t       bd_reserved               :     56;
+	} md_bist_data_fld_s;
+} md_bist_data_u_t;
+
+#else
+
+typedef union md_bist_data_u {
+	bdrkreg_t	md_bist_data_regval;
+	struct	{
+		bdrkreg_t	bd_reserved		  :	56;
+		bdrkreg_t	bd_bist_write		  :	 1;
+		bdrkreg_t	bd_bist_cycle		  :	 1;
+		bdrkreg_t	bd_bist_byte		  :	 1;
+		bdrkreg_t	bd_bist_nibble		  :	 1;
+		bdrkreg_t	bd_bist_data		  :	 4;
+	} md_bist_data_fld_s;
+} md_bist_data_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Captures the BIST error address and indicates whether it is an MB   *
+ * error or DB error.                                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_ab_err_addr_u {
+	bdrkreg_t	md_bist_ab_err_addr_regval;
+	struct  {
+		bdrkreg_t	baea_be_db_cas_addr       :	15;
+		bdrkreg_t       baea_reserved_3           :      1;
+		bdrkreg_t       baea_be_mb_cas_addr       :     15;
+		bdrkreg_t       baea_reserved_2           :      1;
+		bdrkreg_t       baea_be_ras_addr          :     15;
+		bdrkreg_t       baea_reserved_1           :      1;
+		bdrkreg_t       baea_bist_mb_error        :      1;
+		bdrkreg_t       baea_bist_db_error        :      1;
+		bdrkreg_t       baea_reserved             :     14;
+	} md_bist_ab_err_addr_fld_s;
+} md_bist_ab_err_addr_u_t;
+
+#else
+
+typedef union md_bist_ab_err_addr_u {
+	bdrkreg_t	md_bist_ab_err_addr_regval;
+	struct	{
+		bdrkreg_t	baea_reserved		  :	14;
+		bdrkreg_t	baea_bist_db_error	  :	 1;
+		bdrkreg_t	baea_bist_mb_error	  :	 1;
+		bdrkreg_t	baea_reserved_1		  :	 1;
+		bdrkreg_t	baea_be_ras_addr	  :	15;
+		bdrkreg_t	baea_reserved_2		  :	 1;
+		bdrkreg_t	baea_be_mb_cas_addr	  :	15;
+		bdrkreg_t	baea_reserved_3		  :	 1;
+		bdrkreg_t	baea_be_db_cas_addr	  :	15;
+	} md_bist_ab_err_addr_fld_s;
+} md_bist_ab_err_addr_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains information on BIST progress and memory bank currently     *
+ * under BIST.                                                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_status_u {
+	bdrkreg_t	md_bist_status_regval;
+	struct  {
+		bdrkreg_t	bs_bist_passed            :	 1;
+		bdrkreg_t       bs_bist_done              :      1;
+		bdrkreg_t       bs_reserved               :     62;
+	} md_bist_status_fld_s;
+} md_bist_status_u_t;
+
+#else
+
+typedef union md_bist_status_u {
+	bdrkreg_t	md_bist_status_regval;
+	struct	{
+		bdrkreg_t	bs_reserved		  :	62;
+		bdrkreg_t	bs_bist_done		  :	 1;
+		bdrkreg_t	bs_bist_passed		  :	 1;
+	} md_bist_status_fld_s;
+} md_bist_status_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains 3 bits that allow the selection of IB debug information    *
+ * at the debug port (see design specification for available debug      *
+ * information).                                                        *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_ib_debug_u {
+	bdrkreg_t	md_ib_debug_regval;
+	struct  {
+		bdrkreg_t	id_ib_debug_sel           :	 2;
+		bdrkreg_t       id_reserved               :     62;
+	} md_ib_debug_fld_s;
+} md_ib_debug_u_t;
+
+#else
+
+typedef union md_ib_debug_u {
+	bdrkreg_t	md_ib_debug_regval;
+	struct	{
+		bdrkreg_t	id_reserved		  :	62;
+		bdrkreg_t	id_ib_debug_sel		  :	 2;
+	} md_ib_debug_fld_s;
+} md_ib_debug_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains the directory specific mode bits. The contents of this     *
+ * register are preserved through soft-resets.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_dir_config_u {
+	bdrkreg_t	md_dir_config_regval;
+	struct  {
+		bdrkreg_t	dc_dir_flavor             :	 1;
+		bdrkreg_t       dc_ignore_dir_ecc         :      1;
+		bdrkreg_t       dc_reserved               :     62;
+	} md_dir_config_fld_s;
+} md_dir_config_u_t;
+
+#else
+
+typedef union md_dir_config_u {
+	bdrkreg_t	md_dir_config_regval;
+	struct	{
+		bdrkreg_t	dc_reserved		  :	62;
+		bdrkreg_t	dc_ignore_dir_ecc	  :	 1;
+		bdrkreg_t	dc_dir_flavor		  :	 1;
+	} md_dir_config_fld_s;
+} md_dir_config_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Contains information on uncorrectable and              *
+ * correctable directory ECC errors, along with protection ECC          *
+ * errors. The priority of ECC errors latched is: uncorrectable         *
+ * directory, protection error, correctable directory. Thus the valid   *
+ * bits signal:                                                         *
+ * 1xxx: uncorrectable directory ECC error (UCE)                        *
+ * 01xx: access protection double bit error (AE)                        *
+ * 001x: correctable directory ECC error (CE)                           *
+ * 0001: access protection correctable error (ACE)                      *
+ * If the UCE valid bit is set, the address field contains a pointer    *
+ * to the Hspec address of the offending directory entry, the           *
+ * syndrome field contains the bad syndrome, and the UCE overrun bit    *
+ * indicates whether multiple double-bit errors were received.          *
+ * If the UCE valid bit is clear but the AE valid bit is set, the       *
+ * address field contains a pointer to the Hspec address of the         *
+ * offending protection entry, the Bad Protection field contains the    *
+ * 4-bit bad protection value, the PROT_INDEX field shows which of      *
+ * the 8 protection values in the word was bad and the AE overrun bit   *
+ * indicates whether multiple AE errors were received.                  *
+ * If the UCE and AE valid bits are clear, but the CE valid bit is      *
+ * set, the address field contains a pointer to the Hspec address of    *
+ * the offending directory entry, the syndrome field contains the bad   *
+ * syndrome, and the CE overrun bit indicates whether multiple          *
+ * single-bit errors were received.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_dir_error_u {
+	bdrkreg_t	md_dir_error_regval;
+	struct  {
+		bdrkreg_t	de_reserved_3             :	 3;
+		bdrkreg_t       de_hspec_addr             :     30;
+		bdrkreg_t       de_reserved_2             :      7;
+		bdrkreg_t       de_bad_syn                :      7;
+		bdrkreg_t       de_reserved_1             :      1;
+                bdrkreg_t       de_bad_protect            :      4;
+                bdrkreg_t       de_prot_index             :      3;
+                bdrkreg_t       de_reserved               :      1;
+                bdrkreg_t       de_ace_overrun            :      1;
+                bdrkreg_t       de_ce_overrun             :      1;
+                bdrkreg_t       de_ae_overrun             :      1;
+                bdrkreg_t       de_uce_overrun            :      1;
+                bdrkreg_t       de_ace_valid              :      1;
+                bdrkreg_t       de_ce_valid               :      1;
+                bdrkreg_t       de_ae_valid               :      1;
+                bdrkreg_t       de_uce_valid              :      1;
+	} md_dir_error_fld_s;
+} md_dir_error_u_t;
+
+#else
+
+typedef union md_dir_error_u {
+	bdrkreg_t	md_dir_error_regval;
+	struct	{
+		bdrkreg_t	de_uce_valid		  :	 1;
+		bdrkreg_t	de_ae_valid		  :	 1;
+		bdrkreg_t	de_ce_valid		  :	 1;
+		bdrkreg_t	de_ace_valid		  :	 1;
+		bdrkreg_t	de_uce_overrun		  :	 1;
+		bdrkreg_t	de_ae_overrun		  :	 1;
+		bdrkreg_t	de_ce_overrun		  :	 1;
+		bdrkreg_t	de_ace_overrun		  :	 1;
+		bdrkreg_t	de_reserved		  :	 1;
+		bdrkreg_t	de_prot_index		  :	 3;
+		bdrkreg_t	de_bad_protect		  :	 4;
+		bdrkreg_t	de_reserved_1		  :	 1;
+		bdrkreg_t	de_bad_syn		  :	 7;
+		bdrkreg_t	de_reserved_2		  :	 7;
+		bdrkreg_t	de_hspec_addr		  :	30;
+		bdrkreg_t	de_reserved_3		  :	 3;
+	} md_dir_error_fld_s;
+} md_dir_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Contains information on uncorrectable and              *
+ * correctable directory ECC errors, along with protection ECC          *
+ * errors. The priority of ECC errors latched is: uncorrectable         *
+ * directory, protection error, correctable directory. Thus the valid   *
+ * bits signal:                                                         *
+ * 1xxx: uncorrectable directory ECC error (UCE)                        *
+ * 01xx: access protection double bit error (AE)                        *
+ * 001x: correctable directory ECC error (CE)                           *
+ * 0001: access protection correctable error (ACE)                      *
+ * If the UCE valid bit is set, the address field contains a pointer    *
+ * to the Hspec address of the offending directory entry, the           *
+ * syndrome field contains the bad syndrome, and the UCE overrun bit    *
+ * indicates whether multiple double-bit errors were received.          *
+ * If the UCE valid bit is clear but the AE valid bit is set, the       *
+ * address field contains a pointer to the Hspec address of the         *
+ * offending protection entry, the Bad Protection field contains the    *
+ * 4-bit bad protection value, the PROT_INDEX field shows which of      *
+ * the 8 protection values in the word was bad and the AE overrun bit   *
+ * indicates whether multiple AE errors were received.                  *
+ * If the UCE and AE valid bits are clear, but the CE valid bit is      *
+ * set, the address field contains a pointer to the Hspec address of    *
+ * the offending directory entry, the syndrome field contains the bad   *
+ * syndrome, and the CE overrun bit indicates whether multiple          *
+ * single-bit errors were received.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_dir_error_clr_u {
+	bdrkreg_t	md_dir_error_clr_regval;
+	struct  {
+		bdrkreg_t	dec_reserved_3            :	 3;
+                bdrkreg_t       dec_hspec_addr            :     30;
+                bdrkreg_t       dec_reserved_2            :      7;
+                bdrkreg_t       dec_bad_syn               :      7;
+                bdrkreg_t       dec_reserved_1            :      1;
+                bdrkreg_t       dec_bad_protect           :      4;
+                bdrkreg_t       dec_prot_index            :      3;
+                bdrkreg_t       dec_reserved              :      1;
+                bdrkreg_t       dec_ace_overrun           :      1;
+                bdrkreg_t       dec_ce_overrun            :      1;
+                bdrkreg_t       dec_ae_overrun            :      1;
+                bdrkreg_t       dec_uce_overrun           :      1;
+                bdrkreg_t       dec_ace_valid             :      1;
+                bdrkreg_t       dec_ce_valid              :      1;
+                bdrkreg_t       dec_ae_valid              :      1;
+                bdrkreg_t       dec_uce_valid             :      1;
+	} md_dir_error_clr_fld_s;
+} md_dir_error_clr_u_t;
+
+#else
+
+typedef union md_dir_error_clr_u {
+	bdrkreg_t	md_dir_error_clr_regval;
+	struct	{
+		bdrkreg_t	dec_uce_valid		  :	 1;
+		bdrkreg_t	dec_ae_valid		  :	 1;
+		bdrkreg_t	dec_ce_valid		  :	 1;
+		bdrkreg_t	dec_ace_valid		  :	 1;
+		bdrkreg_t	dec_uce_overrun		  :	 1;
+		bdrkreg_t	dec_ae_overrun		  :	 1;
+		bdrkreg_t	dec_ce_overrun		  :	 1;
+		bdrkreg_t	dec_ace_overrun		  :	 1;
+		bdrkreg_t	dec_reserved		  :	 1;
+		bdrkreg_t	dec_prot_index		  :	 3;
+		bdrkreg_t	dec_bad_protect		  :	 4;
+		bdrkreg_t	dec_reserved_1		  :	 1;
+		bdrkreg_t	dec_bad_syn		  :	 7;
+		bdrkreg_t	dec_reserved_2		  :	 7;
+		bdrkreg_t	dec_hspec_addr		  :	30;
+		bdrkreg_t	dec_reserved_3		  :	 3;
+	} md_dir_error_clr_fld_s;
+} md_dir_error_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains information on requests that encounter no valid protocol   *
+ * table entry.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_protocol_error_u {
+	bdrkreg_t	md_protocol_error_regval;
+	struct  {
+		bdrkreg_t	pe_overrun                :	 1;
+                bdrkreg_t       pe_pointer_me             :      1;
+                bdrkreg_t       pe_reserved_1             :      1;
+                bdrkreg_t       pe_address                :     30;
+                bdrkreg_t       pe_reserved               :      1;
+                bdrkreg_t       pe_ptr1_btmbits           :      3;
+                bdrkreg_t       pe_dir_format             :      2;
+                bdrkreg_t       pe_dir_state              :      3;
+                bdrkreg_t       pe_priority               :      1;
+                bdrkreg_t       pe_access                 :      1;
+                bdrkreg_t       pe_msg_type               :      8;
+                bdrkreg_t       pe_initiator              :     11;
+                bdrkreg_t       pe_valid                  :      1;
+	} md_protocol_error_fld_s;
+} md_protocol_error_u_t;
+
+#else
+
+typedef union md_protocol_error_u {
+	bdrkreg_t	md_protocol_error_regval;
+	struct	{
+		bdrkreg_t	pe_valid		  :	 1;
+		bdrkreg_t	pe_initiator		  :	11;
+		bdrkreg_t	pe_msg_type		  :	 8;
+		bdrkreg_t	pe_access		  :	 1;
+		bdrkreg_t	pe_priority		  :	 1;
+		bdrkreg_t	pe_dir_state		  :	 3;
+		bdrkreg_t	pe_dir_format		  :	 2;
+		bdrkreg_t	pe_ptr1_btmbits		  :	 3;
+		bdrkreg_t	pe_reserved		  :	 1;
+		bdrkreg_t	pe_address		  :	30;
+		bdrkreg_t	pe_reserved_1		  :	 1;
+		bdrkreg_t	pe_pointer_me		  :	 1;
+		bdrkreg_t	pe_overrun		  :	 1;
+	} md_protocol_error_fld_s;
+} md_protocol_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains information on requests that encounter no valid protocol   *
+ * table entry.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_protocol_err_clr_u {
+	bdrkreg_t	md_protocol_err_clr_regval;
+	struct  {
+		bdrkreg_t	pec_overrun               :	 1;
+                bdrkreg_t       pec_pointer_me            :      1;
+                bdrkreg_t       pec_reserved_1            :      1;
+                bdrkreg_t       pec_address               :     30;
+                bdrkreg_t       pec_reserved              :      1;
+                bdrkreg_t       pec_ptr1_btmbits          :      3;
+                bdrkreg_t       pec_dir_format            :      2;
+                bdrkreg_t       pec_dir_state             :      3;
+                bdrkreg_t       pec_priority              :      1;
+                bdrkreg_t       pec_access                :      1;
+                bdrkreg_t       pec_msg_type              :      8;
+                bdrkreg_t       pec_initiator             :     11;
+                bdrkreg_t       pec_valid                 :      1;
+	} md_protocol_err_clr_fld_s;
+} md_protocol_err_clr_u_t;
+
+#else
+
+typedef union md_protocol_err_clr_u {
+	bdrkreg_t	md_protocol_err_clr_regval;
+	struct	{
+		bdrkreg_t	pec_valid		  :	 1;
+		bdrkreg_t	pec_initiator		  :	11;
+		bdrkreg_t	pec_msg_type		  :	 8;
+		bdrkreg_t	pec_access		  :	 1;
+		bdrkreg_t	pec_priority		  :	 1;
+		bdrkreg_t	pec_dir_state		  :	 3;
+		bdrkreg_t	pec_dir_format		  :	 2;
+		bdrkreg_t	pec_ptr1_btmbits	  :	 3;
+		bdrkreg_t	pec_reserved		  :	 1;
+		bdrkreg_t	pec_address		  :	30;
+		bdrkreg_t	pec_reserved_1		  :	 1;
+		bdrkreg_t	pec_pointer_me		  :	 1;
+		bdrkreg_t	pec_overrun		  :	 1;
+	} md_protocol_err_clr_fld_s;
+} md_protocol_err_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains the address of the page and the requestor which caused a   *
+ * migration threshold to be exceeded. Also contains the type of        *
+ * threshold exceeded and an overrun bit. For Value mode type           *
+ * interrupts, it indicates whether the local or the remote counter     *
+ * triggered the interrupt. Unlike most registers, when the overrun     *
+ * bit is set the register contains information on the most recent      *
+ * (the last) migration candidate.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mig_candidate_u {
+	bdrkreg_t	md_mig_candidate_regval;
+	struct  {
+		bdrkreg_t	mc_address                :	21;
+                bdrkreg_t       mc_initiator              :     11;
+                bdrkreg_t       mc_overrun                :      1;
+                bdrkreg_t       mc_type                   :      1;
+                bdrkreg_t       mc_local                  :      1;
+                bdrkreg_t       mc_reserved               :     28;
+                bdrkreg_t       mc_valid                  :      1;
+	} md_mig_candidate_fld_s;
+} md_mig_candidate_u_t;
+
+#else
+
+typedef union md_mig_candidate_u {
+	bdrkreg_t	md_mig_candidate_regval;
+	struct	{
+		bdrkreg_t	mc_valid		  :	 1;
+		bdrkreg_t	mc_reserved		  :	28;
+		bdrkreg_t	mc_local		  :	 1;
+		bdrkreg_t	mc_type			  :	 1;
+		bdrkreg_t	mc_overrun		  :	 1;
+		bdrkreg_t	mc_initiator		  :	11;
+		bdrkreg_t	mc_address		  :	21;
+	} md_mig_candidate_fld_s;
+} md_mig_candidate_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains the address of the page and the requestor which caused a   *
+ * migration threshold to be exceeded. Also contains the type of        *
+ * threshold exceeded and an overrun bit. For Value mode type           *
+ * interrupts, it indicates whether the local or the remote counter     *
+ * triggered the interrupt. Unlike most registers, when the overrun     *
+ * bit is set the register contains information on the most recent      *
+ * (the last) migration candidate.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mig_candidate_clr_u {
+	bdrkreg_t	md_mig_candidate_clr_regval;
+	struct  {
+		bdrkreg_t	mcc_address               :	21;
+                bdrkreg_t       mcc_initiator             :     11;
+                bdrkreg_t       mcc_overrun               :      1;
+                bdrkreg_t       mcc_type                  :      1;
+                bdrkreg_t       mcc_local                 :      1;
+                bdrkreg_t       mcc_reserved              :     28;
+                bdrkreg_t       mcc_valid                 :      1;
+	} md_mig_candidate_clr_fld_s;
+} md_mig_candidate_clr_u_t;
+
+#else
+
+typedef union md_mig_candidate_clr_u {
+	bdrkreg_t	md_mig_candidate_clr_regval;
+	struct	{
+		bdrkreg_t	mcc_valid		  :	 1;
+		bdrkreg_t	mcc_reserved		  :	28;
+		bdrkreg_t	mcc_local		  :	 1;
+		bdrkreg_t	mcc_type		  :	 1;
+		bdrkreg_t	mcc_overrun		  :	 1;
+		bdrkreg_t	mcc_initiator		  :	11;
+		bdrkreg_t	mcc_address		  :	21;
+	} md_mig_candidate_clr_fld_s;
+} md_mig_candidate_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Controls the generation of page-migration interrupts and loading    *
+ * of the MIGRATION_CANDIDATE register for pages which are using the    *
+ * difference between the requestor and home counts. If the             *
+ * difference is greater-than or equal to than the threshold            *
+ * contained in the register, and the valid bit is set, the migration   *
+ * candidate is loaded (and an interrupt generated if enabled by the    *
+ * page migration mode).                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mig_diff_thresh_u {
+	bdrkreg_t	md_mig_diff_thresh_regval;
+	struct  {
+		bdrkreg_t	mdt_threshold             :	15;
+                bdrkreg_t       mdt_reserved_1            :     17;
+                bdrkreg_t       mdt_th_action             :      3;
+                bdrkreg_t       mdt_sat_action            :      3;
+                bdrkreg_t       mdt_reserved              :     25;
+                bdrkreg_t       mdt_valid                 :      1;
+	} md_mig_diff_thresh_fld_s;
+} md_mig_diff_thresh_u_t;
+
+#else
+
+typedef union md_mig_diff_thresh_u {
+	bdrkreg_t	md_mig_diff_thresh_regval;
+	struct	{
+		bdrkreg_t	mdt_valid		  :	 1;
+		bdrkreg_t	mdt_reserved		  :	25;
+		bdrkreg_t	mdt_sat_action		  :	 3;
+		bdrkreg_t	mdt_th_action		  :	 3;
+		bdrkreg_t	mdt_reserved_1		  :	17;
+		bdrkreg_t	mdt_threshold		  :	15;
+	} md_mig_diff_thresh_fld_s;
+} md_mig_diff_thresh_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Controls the generation of page-migration interrupts and loading    *
+ * of the MIGRATION_CANDIDATE register for pages that are using the     *
+ * absolute value of the requestor count. If the value is               *
+ * greater-than or equal to the threshold contained in the register,    *
+ * and the register valid bit is set, the migration candidate is        *
+ * loaded and an interrupt generated. For the value mode of page        *
+ * migration, there are two variations. In the first variation,         *
+ * interrupts are only generated when the remote counter reaches the    *
+ * threshold, not when the local counter reaches the threshold. In      *
+ * the second mode, both the local counter and the remote counter       *
+ * generate interrupts if they reach the threshold. This second mode    *
+ * is useful for performance monitoring, to track the number of local   *
+ * and remote references to a page. LOCAL_INT determines whether we     *
+ * will generate interrupts when the local counter reaches the          *
+ * threshold.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mig_value_thresh_u {
+	bdrkreg_t	md_mig_value_thresh_regval;
+	struct  {
+		bdrkreg_t	mvt_threshold             :	15;
+                bdrkreg_t       mvt_reserved_1            :     17;
+                bdrkreg_t       mvt_th_action             :      3;
+                bdrkreg_t       mvt_sat_action            :      3;
+                bdrkreg_t       mvt_reserved              :     24;
+                bdrkreg_t       mvt_local_int             :      1;
+                bdrkreg_t       mvt_valid                 :      1;
+	} md_mig_value_thresh_fld_s;
+} md_mig_value_thresh_u_t;
+
+#else
+
+typedef union md_mig_value_thresh_u {
+        bdrkreg_t       md_mig_value_thresh_regval;
+        struct  {
+                bdrkreg_t       mvt_valid                 :      1;
+                bdrkreg_t       mvt_local_int             :      1;
+                bdrkreg_t       mvt_reserved              :     24;
+                bdrkreg_t       mvt_sat_action            :      3;
+                bdrkreg_t       mvt_th_action             :      3;
+                bdrkreg_t       mvt_reserved_1            :     17;
+                bdrkreg_t       mvt_threshold             :     15;
+        } md_mig_value_thresh_fld_s;
+} md_mig_value_thresh_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains the controls for the sizing of the three MOQH request      *
+ * queues. The maximum (and default) value is 4. Queue sizes are in     *
+ * flits. One header equals one flit.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_outgoing_rq_queue_size_u {
+	bdrkreg_t	md_outgoing_rq_queue_size_regval;
+	struct  {
+		bdrkreg_t	orqs_reserved_3           :	 8;
+                bdrkreg_t       orqs_moqh_p0_rq_size      :      3;
+                bdrkreg_t       orqs_reserved_2           :      5;
+                bdrkreg_t       orqs_moqh_p1_rq_size      :      3;
+                bdrkreg_t       orqs_reserved_1           :      5;
+                bdrkreg_t       orqs_moqh_np_rq_size      :      3;
+                bdrkreg_t       orqs_reserved             :     37;
+	} md_outgoing_rq_queue_size_fld_s;
+} md_outgoing_rq_queue_size_u_t;
+
+#else
+
+typedef union md_outgoing_rq_queue_size_u {
+	bdrkreg_t	md_outgoing_rq_queue_size_regval;
+	struct	{
+		bdrkreg_t	orqs_reserved		  :	37;
+		bdrkreg_t	orqs_moqh_np_rq_size	  :	 3;
+		bdrkreg_t	orqs_reserved_1		  :	 5;
+		bdrkreg_t	orqs_moqh_p1_rq_size	  :	 3;
+		bdrkreg_t	orqs_reserved_2		  :	 5;
+		bdrkreg_t	orqs_moqh_p0_rq_size	  :	 3;
+		bdrkreg_t	orqs_reserved_3		  :	 8;
+	} md_outgoing_rq_queue_size_fld_s;
+} md_outgoing_rq_queue_size_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains the 32-bit directory word failing BIST.                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_db_err_data_u {
+	bdrkreg_t	md_bist_db_err_data_regval;
+	struct  {
+		bdrkreg_t	bded_db_er_d              :	32;
+		bdrkreg_t       bded_reserved             :     32;
+	} md_bist_db_err_data_fld_s;
+} md_bist_db_err_data_u_t;
+
+#else
+
+typedef union md_bist_db_err_data_u {
+	bdrkreg_t	md_bist_db_err_data_regval;
+	struct	{
+		bdrkreg_t	bded_reserved		  :	32;
+		bdrkreg_t	bded_db_er_d		  :	32;
+	} md_bist_db_err_data_fld_s;
+} md_bist_db_err_data_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains 2 bits that allow the selection of DB debug information    *
+ * at the debug port (see the design specification for descrition of    *
+ * the available debug information).                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_db_debug_u {
+	bdrkreg_t	md_db_debug_regval;
+	struct  {
+		bdrkreg_t	dd_db_debug_sel           :	 2;
+		bdrkreg_t       dd_reserved               :     62;
+	} md_db_debug_fld_s;
+} md_db_debug_u_t;
+
+#else
+
+typedef union md_db_debug_u {
+	bdrkreg_t	md_db_debug_regval;
+	struct	{
+		bdrkreg_t	dd_reserved		  :	62;
+		bdrkreg_t	dd_db_debug_sel		  :	 2;
+	} md_db_debug_fld_s;
+} md_db_debug_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains the IgnoreECC bit. When this bit is set, all ECC errors    *
+ * are ignored. ECC bits will still be generated on writebacks.         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mb_ecc_config_u {
+	bdrkreg_t	md_mb_ecc_config_regval;
+	struct  {
+		bdrkreg_t	mec_ignore_dataecc        :	 1;
+		bdrkreg_t       mec_reserved              :     63;
+	} md_mb_ecc_config_fld_s;
+} md_mb_ecc_config_u_t;
+
+#else
+
+typedef union md_mb_ecc_config_u {
+	bdrkreg_t	md_mb_ecc_config_regval;
+	struct	{
+		bdrkreg_t	mec_reserved		  :	63;
+		bdrkreg_t	mec_ignore_dataecc	  :	 1;
+	} md_mb_ecc_config_fld_s;
+} md_mb_ecc_config_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Contains information on read memory errors (both       *
+ * correctable and uncorrectable) and write memory errors (always       *
+ * uncorrectable). The errors are prioritized as follows:               *
+ *  highest: uncorrectable read error (READ_UCE)                        *
+ *  middle: write error (WRITE_UCE)                                     *
+ *  lowest: correctable read error (READ_CE)                            *
+ * Each type of error maintains a two-bit valid/overrun field           *
+ * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field       *
+ * corresponds to the valid bit, and bit 1 of each two-bit field        *
+ * corresponds to the overrun bit.                                      *
+ * The rule for the valid bit is that it gets set whenever that error   *
+ * occurs, regardless of whether a higher priority error has occured.   *
+ * The rule for the overrun bit is that it gets set whenever we are     *
+ * unable to record the address information for this particular         *
+ * error, due to a previous error of the same or higher priority.       *
+ * Note that the syndrome and address information always corresponds    *
+ * to the earliest, highest priority error.                             *
+ *  Finally, the UCE_DIFF_ADDR bit is set whenever there have been      *
+ * several uncorrectable errors, to different cache line addresses.     *
+ * If all the UCEs were to the same cache line address, then            *
+ * UCE_DIFF_ADDR will be 0. This allows the operating system to         *
+ * detect the case where a UCE error is read exclusively, and then      *
+ * written back by the processor. If the bit is 0, it indicates that    *
+ * no information has been lost about UCEs on other cache lines. In     *
+ * particular, partial writes do a read modify write of the cache       *
+ * line. A UCE read error will be set when the cache line is read,      *
+ * and a UCE write error will occur when the cache line is written      *
+ * back, but the UCE_DIFF_ADDR will not be set.                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mem_error_u {
+	bdrkreg_t	md_mem_error_regval;
+	struct  {
+		bdrkreg_t	me_reserved_5             :	 3;
+                bdrkreg_t       me_address                :     30;
+                bdrkreg_t       me_reserved_4             :      7;
+                bdrkreg_t       me_bad_syn                :      8;
+                bdrkreg_t       me_reserved_3             :      4;
+                bdrkreg_t       me_read_ce                :      2;
+                bdrkreg_t       me_reserved_2             :      2;
+                bdrkreg_t       me_write_uce              :      2;
+                bdrkreg_t       me_reserved_1             :      2;
+                bdrkreg_t       me_read_uce               :      2;
+                bdrkreg_t       me_reserved               :      1;
+                bdrkreg_t       me_uce_diff_addr          :      1;
+	} md_mem_error_fld_s;
+} md_mem_error_u_t;
+
+#else
+
+typedef union md_mem_error_u {
+	bdrkreg_t	md_mem_error_regval;
+	struct	{
+		bdrkreg_t	me_uce_diff_addr	  :	 1;
+		bdrkreg_t	me_reserved		  :	 1;
+		bdrkreg_t	me_read_uce		  :	 2;
+		bdrkreg_t	me_reserved_1		  :	 2;
+		bdrkreg_t	me_write_uce		  :	 2;
+		bdrkreg_t	me_reserved_2		  :	 2;
+		bdrkreg_t	me_read_ce		  :	 2;
+		bdrkreg_t	me_reserved_3		  :	 4;
+		bdrkreg_t	me_bad_syn		  :	 8;
+		bdrkreg_t	me_reserved_4		  :	 7;
+		bdrkreg_t	me_address		  :	30;
+		bdrkreg_t	me_reserved_5		  :	 3;
+	} md_mem_error_fld_s;
+} md_mem_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Contains information on read memory errors (both       *
+ * correctable and uncorrectable) and write memory errors (always       *
+ * uncorrectable). The errors are prioritized as follows:               *
+ *  highest: uncorrectable read error (READ_UCE)                        *
+ *  middle: write error (WRITE_UCE)                                     *
+ *  lowest: correctable read error (READ_CE)                            *
+ * Each type of error maintains a two-bit valid/overrun field           *
+ * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field       *
+ * corresponds to the valid bit, and bit 1 of each two-bit field        *
+ * corresponds to the overrun bit.                                      *
+ * The rule for the valid bit is that it gets set whenever that error   *
+ * occurs, regardless of whether a higher priority error has occured.   *
+ * The rule for the overrun bit is that it gets set whenever we are     *
+ * unable to record the address information for this particular         *
+ * error, due to a previous error of the same or higher priority.       *
+ * Note that the syndrome and address information always corresponds    *
+ * to the earliest, highest priority error.                             *
+ *  Finally, the UCE_DIFF_ADDR bit is set whenever there have been      *
+ * several uncorrectable errors, to different cache line addresses.     *
+ * If all the UCEs were to the same cache line address, then            *
+ * UCE_DIFF_ADDR will be 0. This allows the operating system to         *
+ * detect the case where a UCE error is read exclusively, and then      *
+ * written back by the processor. If the bit is 0, it indicates that    *
+ * no information has been lost about UCEs on other cache lines. In     *
+ * particular, partial writes do a read modify write of the cache       *
+ * line. A UCE read error will be set when the cache line is read,      *
+ * and a UCE write error will occur when the cache line is written      *
+ * back, but the UCE_DIFF_ADDR will not be set.                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mem_error_clr_u {
+	bdrkreg_t	md_mem_error_clr_regval;
+	struct  {
+		bdrkreg_t	mec_reserved_5            :	 3;
+                bdrkreg_t       mec_address               :     30;
+                bdrkreg_t       mec_reserved_4            :      7;
+                bdrkreg_t       mec_bad_syn               :      8;
+                bdrkreg_t       mec_reserved_3            :      4;
+                bdrkreg_t       mec_read_ce               :      2;
+                bdrkreg_t       mec_reserved_2            :      2;
+                bdrkreg_t       mec_write_uce             :      2;
+                bdrkreg_t       mec_reserved_1            :      2;
+                bdrkreg_t       mec_read_uce              :      2;
+                bdrkreg_t       mec_reserved              :      1;
+                bdrkreg_t       mec_uce_diff_addr         :      1;
+	} md_mem_error_clr_fld_s;
+} md_mem_error_clr_u_t;
+
+#else
+
+typedef union md_mem_error_clr_u {
+	bdrkreg_t	md_mem_error_clr_regval;
+	struct	{
+		bdrkreg_t	mec_uce_diff_addr	  :	 1;
+		bdrkreg_t	mec_reserved		  :	 1;
+		bdrkreg_t	mec_read_uce		  :	 2;
+		bdrkreg_t	mec_reserved_1		  :	 2;
+		bdrkreg_t	mec_write_uce		  :	 2;
+		bdrkreg_t	mec_reserved_2		  :	 2;
+		bdrkreg_t	mec_read_ce		  :	 2;
+		bdrkreg_t	mec_reserved_3		  :	 4;
+		bdrkreg_t	mec_bad_syn		  :	 8;
+		bdrkreg_t	mec_reserved_4		  :	 7;
+		bdrkreg_t	mec_address		  :	30;
+		bdrkreg_t	mec_reserved_5		  :	 3;
+	} md_mem_error_clr_fld_s;
+} md_mem_error_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains one-quarter of the error memory line failing BIST.         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_mb_err_data_0_u {
+	bdrkreg_t	md_bist_mb_err_data_0_regval;
+	struct  {
+		bdrkreg_t	bmed0_mb_er_d             :	36;
+		bdrkreg_t       bmed0_reserved            :     28;
+	} md_bist_mb_err_data_0_fld_s;
+} md_bist_mb_err_data_0_u_t;
+
+#else
+
+typedef union md_bist_mb_err_data_0_u {
+	bdrkreg_t	md_bist_mb_err_data_0_regval;
+	struct	{
+		bdrkreg_t	bmed0_reserved		  :	28;
+		bdrkreg_t	bmed0_mb_er_d		  :	36;
+	} md_bist_mb_err_data_0_fld_s;
+} md_bist_mb_err_data_0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains one-quarter of the error memory line failing BIST.         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_mb_err_data_1_u {
+	bdrkreg_t	md_bist_mb_err_data_1_regval;
+	struct  {
+		bdrkreg_t	bmed1_mb_er_d             :	36;
+		bdrkreg_t       bmed1_reserved            :     28;
+	} md_bist_mb_err_data_1_fld_s;
+} md_bist_mb_err_data_1_u_t;
+
+#else
+
+typedef union md_bist_mb_err_data_1_u {
+	bdrkreg_t	md_bist_mb_err_data_1_regval;
+	struct	{
+		bdrkreg_t	bmed1_reserved		  :	28;
+		bdrkreg_t	bmed1_mb_er_d		  :	36;
+	} md_bist_mb_err_data_1_fld_s;
+} md_bist_mb_err_data_1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains one-quarter of the error memory line failing BIST.         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_mb_err_data_2_u {
+	bdrkreg_t	md_bist_mb_err_data_2_regval;
+	struct  {
+		bdrkreg_t	bmed2_mb_er_d             :	36;
+		bdrkreg_t       bmed2_reserved            :     28;
+	} md_bist_mb_err_data_2_fld_s;
+} md_bist_mb_err_data_2_u_t;
+
+#else
+
+typedef union md_bist_mb_err_data_2_u {
+	bdrkreg_t	md_bist_mb_err_data_2_regval;
+	struct	{
+		bdrkreg_t	bmed2_reserved		  :	28;
+		bdrkreg_t	bmed2_mb_er_d		  :	36;
+	} md_bist_mb_err_data_2_fld_s;
+} md_bist_mb_err_data_2_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains one-quarter of the error memory line failing BIST.         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_bist_mb_err_data_3_u {
+	bdrkreg_t	md_bist_mb_err_data_3_regval;
+	struct  {
+		bdrkreg_t	bmed3_mb_er_d             :	36;
+		bdrkreg_t       bmed3_reserved            :     28;
+	} md_bist_mb_err_data_3_fld_s;
+} md_bist_mb_err_data_3_u_t;
+
+#else
+
+typedef union md_bist_mb_err_data_3_u {
+	bdrkreg_t	md_bist_mb_err_data_3_regval;
+	struct	{
+		bdrkreg_t	bmed3_reserved		  :	28;
+		bdrkreg_t	bmed3_mb_er_d		  :	36;
+	} md_bist_mb_err_data_3_fld_s;
+} md_bist_mb_err_data_3_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Contains 1 bit that allow the selection of MB debug information     *
+ * at the debug port (see the design specification for the available    *
+ * debug information).                                                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union md_mb_debug_u {
+	bdrkreg_t	md_mb_debug_regval;
+	struct  {
+		bdrkreg_t	md_mb_debug_sel           :	 1;
+		bdrkreg_t       md_reserved               :     63;
+	} md_mb_debug_fld_s;
+} md_mb_debug_u_t;
+
+#else
+
+typedef union md_mb_debug_u {
+	bdrkreg_t	md_mb_debug_regval;
+	struct	{
+		bdrkreg_t	md_reserved		  :	63;
+		bdrkreg_t	md_mb_debug_sel		  :	 1;
+	} md_mb_debug_fld_s;
+} md_mb_debug_u_t;
+
+#endif
+
+
+
+
+
+
+#endif /* _LANGUAGE_C */
+
+/************************************************************************
+ *                                                                      *
+ *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#endif /* _ASM_SN_SN1_HUBMD_H */
diff --git a/include/asm-ia64/sn/sn1/hubmd_next.h b/include/asm-ia64/sn/sn1/hubmd_next.h
new file mode 100644
index 000000000..452167d63
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubmd_next.h
@@ -0,0 +1,815 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBMD_NEXT_H
+#define _ASM_SN_SN1_HUBMD_NEXT_H
+
+#ifdef BRINGUP
+/* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */
+/* In fact, most of this stuff is wrong. Some is correct, such as
+ * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT.
+ */
+
+#define MD_PERF_COUNTERS        6
+#define MD_PERF_SETS            6
+
+#define MD_SIZE_EMPTY           0       
+#define MD_SIZE_64MB            1       
+#define MD_SIZE_128MB           2       
+#define MD_SIZE_256MB           3
+#define MD_SIZE_512MB           4      
+#define MD_SIZE_1GB             5      
+
+#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x2000000L << (size))
+#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   0x20       << (size))
+#define MD_NUM_ENABLED(_x)	((_x & 0x1) + ((_x >> 1) & 0x1) + \
+				((_x >> 2) & 0x1) + ((_x >> 3) & 0x1))
+
+
+/* Hardware page size and shift */
+
+#define MD_PAGE_SIZE            16384    /* Page size in bytes              */
+#define MD_PAGE_NUM_SHFT        14       /* Address to page number shift    */
+
+#define MMC_IO_PROT 		(UINT64_CAST 1 << 45)
+
+/* Register offsets from LOCAL_HUB or REMOTE_HUB */
+#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
+
+/* MD_MIG_VALUE_THRESH bit definitions */
+
+#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_CANDIDATE bit definitions */
+
+#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_CANDIDATE_VALID_SHFT 63
+#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
+#define MD_MIG_CANDIDATE_TYPE_SHFT 30
+#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
+#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
+#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
+#define MD_MIG_CANDIDATE_NODEID_SHFT 20
+#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
+
+
+/* XXX protection and migration are completely revised on SN1.  On
+   SN0, the reference count and protection fields were accessed in the
+   same word, but on SN1 they reside at different addresses.  The
+   users of these macros will need to be rewritten.  Also, the MD page
+   size is 16K on SN1 but 4K on SN0.  */
+
+/* Premium SIMM protection entry shifts and masks. */
+
+#define MD_PPROT_SHFT           0                       /* Prot. field      */
+#define MD_PPROT_MASK           0xf
+#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_PPROT_REFCNT_WIDTH   0x7ffff
+#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
+
+#define MD_PPROT_IO_SHFT        8                       /* I/O Prot field   */
+
+/* Standard SIMM protection entry shifts and masks. */
+
+#define MD_SPROT_SHFT           0                       /* Prot. field      */
+#define MD_SPROT_MASK           0xf
+#define MD_SPROT_IO_SHFT	8
+#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_SPROT_REFCNT_WIDTH   0x7ff
+#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
+
+/* Migration modes used in protection entries */
+
+#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
+#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
+#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
+#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
+
+/*
+ * Operations on Memory/Directory DIMM control register
+ */
+
+#define DIRTYPE_PREMIUM 1
+#define DIRTYPE_STANDARD 0
+
+/*
+ * Operations on page migration count difference and absolute threshold
+ * registers
+ */
+
+#define MD_MIG_VALUE_THRESH_GET(region) (                               \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
+        MD_MIG_VALUE_THRES_VALUE_MASK)
+
+#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                MD_MIG_VALUE_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
+                             | MD_MIG_VALUE_THRES_VALID_MASK))
+
+/*
+ * Operations on page migration candidate register
+ */
+
+#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
+        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
+
+#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
+
+#define MD_MIG_CANDIDATE_NODEID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
+
+#define MD_MIG_CANDIDATE_TYPE(value) ( \
+        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
+
+#define MD_MIG_CANDIDATE_VALID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
+
+/*
+ * Macros to retrieve fields in the protection entry
+ */
+
+/* for Premium SIMM */
+#define MD_PPROT_REFCNT_GET(value) ( \
+        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
+
+/* for Standard SIMM */
+#define MD_SPROT_REFCNT_GET(value) ( \
+        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
+
+#if _LANGUAGE_C
+#ifdef LITTLE_ENDIAN
+
+typedef union md_perf_sel {
+        uint64_t      perf_sel_reg;
+        struct  {
+                uint64_t      perf_sel  :  3,
+				perf_en   :  1,
+				perf_rsvd : 60;
+        } perf_sel_bits;
+} md_perf_sel_t;
+
+#else
+
+typedef union md_perf_sel {
+	uint64_t	perf_sel_reg;
+	struct	{
+		uint64_t	perf_rsvd : 60,
+				perf_en	  :  1,
+				perf_sel  :  3;
+	} perf_sel_bits;
+} md_perf_sel_t;
+
+#endif
+#endif /* _LANGUAGE_C */
+
+#endif /* BRINGUP */
+
+/* Like SN0, SN1 supports a mostly-flat address space with 8
+   CPU-visible, evenly spaced, contiguous regions, or "software
+   banks".  On SN1, software bank n begins at addresses n * 1GB, 
+   0 <= n < 8.
+
+   Physically (and very unlike SN0), each SN1 node board contains 8
+   dimm sockets, arranged as 4 "DIMM banks" of 2 dimms each.  DIMM
+   size and width (x4/x8) is assigned per dimm bank.  Each DIMM bank
+   consists of 2 "physical banks", one on the front sides of the 2
+   DIMMs and the other on the back sides.  Therefore a node has a
+   total of 8 ( = 4 * 2) physical banks.  They are collectively
+   referred to as "locational banks", since the locational bank number
+   depends on the physical location of the DIMMs on the board.
+
+	      Dimm bank 0, Phys bank 0a (locational bank 0a)
+     Slot D0  ----------------------------------------------
+	      Dimm bank 0, Phys bank 1a (locational bank 1a)
+
+	      Dimm bank 1, Phys bank 0a (locational bank 2a)
+     Slot D1  ----------------------------------------------
+	      Dimm bank 1, Phys bank 1a (locational bank 3a)
+
+	      Dimm bank 2, Phys bank 0a (locational bank 4a)
+     Slot D2  ----------------------------------------------
+	      Dimm bank 2, Phys bank 1a (locational bank 5a)
+
+	      Dimm bank 3, Phys bank 0a (locational bank 6a)
+     Slot D3  ----------------------------------------------
+	      Dimm bank 3, Phys bank 1a (locational bank 7a)
+
+	      Dimm bank 0, Phys bank 0b (locational bank 0b)
+     Slot D4  ----------------------------------------------
+	      Dimm bank 0, Phys bank 1b (locational bank 1b)
+
+	      Dimm bank 1, Phys bank 0b (locational bank 2b)
+     Slot D5  ----------------------------------------------
+	      Dimm bank 1, Phys bank 1b (locational bank 3b)
+
+	      Dimm bank 2, Phys bank 0b (locational bank 4b)
+     Slot D6  ----------------------------------------------
+	      Dimm bank 2, Phys bank 1b (locational bank 5b)
+
+	      Dimm bank 3, Phys bank 0b (locational bank 6b)
+     Slot D7  ----------------------------------------------
+	      Dimm bank 3, Phys bank 1b (locational bank 7b)
+
+   Since bank size is assigned per DIMM bank, each pair of locational
+   banks must have the same size.  However, they may be
+   enabled/disabled individually.
+
+   The locational banks map to the software banks via the dimm0_sel
+   field in MD_MEMORY_CONFIG.  When the field is 0 (the usual case),
+   the mapping is direct:  eg. locational bank 1 (dimm bank 0,
+   physical bank 1, which is the back side of the first DIMM pair)
+   corresponds to software bank 1, at node offset 1GB.  More
+   generally, locational bank = software bank XOR dimm0_sel.
+
+   All the PROM's data structures (promlog variables, klconfig, etc.)
+   track memory by the locational bank number.  The kernel usually
+   tracks memory by the software bank number.
+   memsupport.c:slot_psize_compute() performs the mapping.
+
+   (Note:  the terms "locational bank" and "software bank" are not
+   offical in any way, but I've tried to make the PROM use them
+   consistently -- bjj.)
+ */
+
+#define MD_MEM_BANKS 		8
+#define MD_MEM_DIMM_BANKS 	4
+#define MD_BANK_SHFT            30                     /* log2(1 GB)     */
+#define MD_BANK_MASK            (UINT64_CAST 0x7 << 30)
+#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /*  1 GB */
+#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
+#define MD_BANK_GET(addr)	(((addr) & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define MD_BANK_TO_DIMM_BANK(_b) (( (_b) >> 1) & 0x3)
+#define MD_BANK_TO_PHYS_BANK(_b) (( (_b) >> 0) & 0x1)
+#define MD_DIMM_BANK_GET(addr)   MD_BANK_TO_DIMM_BANK(MD_BANK_GET(addr))
+#define MD_PHYS_BANK_GET(addr)   MD_BANK_TO_PHYS_BANK(MD_BANK_GET(addr))
+
+
+/* Split an MD pointer (or message source & suppl. fields) into node, device */
+
+#define MD_PTR_NODE_SHFT	3
+#define MD_PTR_DEVICE_MASK	0x7
+#define MD_PTR_SUBNODE0_MASK	0x1
+#define MD_PTR_SUBNODE1_MASK	0x4
+
+
+/**********************************************************************
+
+ Backdoor protection and page counter structures
+
+**********************************************************************/
+
+/* Protection entries and page counters are interleaved at 4 separate
+   addresses, 0x10 apart.  Software must read/write all four. */
+
+#define BD_ITLV_COUNT		4
+#define BD_ITLV_STRIDE		0x10
+
+/* Protection entries */
+
+/* (these macros work for standard (_rgn < 32) or premium DIMMs) */
+#define MD_PROT_SHFT(_rgn, _io)	((((_rgn) & 0x20) >> 2 | \
+				  ((_rgn) & 0x01) << 2 | \
+				  ((_io)  &  0x1) << 1) * 8)
+#define MD_PROT_MASK(_rgn, _io)	(0xff << MD_PROT_SHFT(_rgn, _io))
+#define MD_PROT_GET(_val, _rgn, _io) \
+	(((_val) & MD_PROT_MASK(_rgn, _io)) >> MD_PROT_SHFT(_rgn, _io))
+
+/* Protection field values */
+
+#define MD_PROT_RW              (UINT64_CAST 0xff)
+#define MD_PROT_RO              (UINT64_CAST 0x0f)
+#define MD_PROT_NO              (UINT64_CAST 0x00)
+
+
+
+
+/**********************************************************************
+
+ Directory format structures
+
+***********************************************************************/
+
+#ifdef _LANGUAGE_C
+
+/* Standard Directory Entries */
+
+#ifdef LITTLE_ENDIAN
+
+struct	md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
+	bdrkreg_t	sdp_format                :	 2;
+        bdrkreg_t       sdp_state                 :      3;
+        bdrkreg_t       sdp_priority              :      3;
+        bdrkreg_t       sdp_pointer1              :      8;
+        bdrkreg_t       sdp_ecc                   :      6;
+        bdrkreg_t       sdp_locprot               :      1;
+        bdrkreg_t       sdp_reserved              :      1;
+        bdrkreg_t       sdp_crit_word_off         :      3;
+        bdrkreg_t       sdp_pointer2              :      5;
+        bdrkreg_t       sdp_fill                  :     32;
+};
+
+#else
+
+struct	md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
+	bdrkreg_t	sdp_fill		  :	32;
+	bdrkreg_t	sdp_pointer2		  :	 5;
+	bdrkreg_t	sdp_crit_word_off	  :	 3;
+	bdrkreg_t	sdp_reserved		  :	 1;
+	bdrkreg_t	sdp_locprot		  :	 1;
+	bdrkreg_t	sdp_ecc			  :	 6;
+	bdrkreg_t	sdp_pointer1		  :	 8;
+	bdrkreg_t	sdp_priority		  :	 3;
+	bdrkreg_t	sdp_state		  :	 3;
+	bdrkreg_t	sdp_format		  :	 2;
+};
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+struct	md_sdir_fine_fmt { /* shared (fine) */
+	bdrkreg_t	sdf_format                :	 2;
+        bdrkreg_t       sdf_tag1                  :      3;
+        bdrkreg_t       sdf_tag2                  :      3;
+        bdrkreg_t       sdf_vector1               :      8;
+        bdrkreg_t       sdf_ecc                   :      6;
+        bdrkreg_t       sdf_locprot               :      1;
+        bdrkreg_t       sdf_tag2valid             :      1;
+        bdrkreg_t       sdf_vector2               :      8;
+        bdrkreg_t       sdf_fill                  :     32;
+};
+
+#else
+
+struct	md_sdir_fine_fmt { /* shared (fine) */
+	bdrkreg_t	sdf_fill		  :	32;
+	bdrkreg_t	sdf_vector2		  :	 8;
+	bdrkreg_t	sdf_tag2valid		  :	 1;
+	bdrkreg_t	sdf_locprot		  :	 1;
+	bdrkreg_t	sdf_ecc			  :	 6;
+	bdrkreg_t	sdf_vector1		  :	 8;
+	bdrkreg_t	sdf_tag2		  :	 3;
+	bdrkreg_t	sdf_tag1		  :	 3;
+	bdrkreg_t	sdf_format		  :	 2;
+};
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+struct	md_sdir_coarse_fmt { /* shared (coarse) */
+	bdrkreg_t	sdc_format                :	 2;
+        bdrkreg_t       sdc_reserved_1            :      6;
+        bdrkreg_t       sdc_vector_a              :      8;
+        bdrkreg_t       sdc_ecc                   :      6;
+        bdrkreg_t       sdc_locprot               :      1;
+        bdrkreg_t       sdc_reserved              :      1;
+        bdrkreg_t       sdc_vector_b              :      8;
+        bdrkreg_t       sdc_fill                  :     32;
+};
+
+#else
+
+struct	md_sdir_coarse_fmt { /* shared (coarse) */
+	bdrkreg_t	sdc_fill		  :	32;
+	bdrkreg_t	sdc_vector_b		  :	 8;
+	bdrkreg_t	sdc_reserved		  :	 1;
+	bdrkreg_t	sdc_locprot		  :	 1;
+	bdrkreg_t	sdc_ecc			  :	 6;
+	bdrkreg_t	sdc_vector_a		  :	 8;
+	bdrkreg_t	sdc_reserved_1		  :	 6;
+	bdrkreg_t	sdc_format		  :	 2;
+};
+
+#endif
+
+typedef union md_sdir {
+	/* The 32 bits of standard directory, in bits 31:0 */
+	uint64_t	sd_val;
+	struct	md_sdir_pointer_fmt	sdp_fmt;
+	struct	md_sdir_fine_fmt	sdf_fmt;
+	struct	md_sdir_coarse_fmt	sdc_fmt;
+} md_sdir_t;
+
+
+/* Premium Directory Entries */
+
+#ifdef LITTLE_ENDIAN
+
+struct	md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
+	bdrkreg_t	pdp_format                :	 2;
+        bdrkreg_t       pdp_state                 :      3;
+        bdrkreg_t       pdp_priority              :      3;
+        bdrkreg_t       pdp_pointer1_a            :      8;
+        bdrkreg_t       pdp_reserved_4            :      6;
+        bdrkreg_t       pdp_pointer1_b            :      3;
+        bdrkreg_t       pdp_reserved_3            :      7;
+        bdrkreg_t       pdp_ecc_a                 :      6;
+        bdrkreg_t       pdp_locprot               :      1;
+        bdrkreg_t       pdp_reserved_2            :      1;
+        bdrkreg_t       pdp_crit_word_off         :      3;
+        bdrkreg_t       pdp_pointer2_a            :      5;
+        bdrkreg_t       pdp_ecc_b                 :      1;
+        bdrkreg_t       pdp_reserved_1            :      5;
+        bdrkreg_t       pdp_pointer2_b            :      3;
+        bdrkreg_t       pdp_reserved              :      7;
+};
+
+#else
+
+struct	md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
+	bdrkreg_t	pdp_reserved		  :	 7;
+	bdrkreg_t	pdp_pointer2_b		  :	 3;
+	bdrkreg_t	pdp_reserved_1		  :	 5;
+	bdrkreg_t	pdp_ecc_b		  :	 1;
+	bdrkreg_t	pdp_pointer2_a		  :	 5;
+	bdrkreg_t	pdp_crit_word_off	  :	 3;
+	bdrkreg_t	pdp_reserved_2		  :	 1;
+	bdrkreg_t	pdp_locprot		  :	 1;
+	bdrkreg_t	pdp_ecc_a		  :	 6;
+	bdrkreg_t	pdp_reserved_3		  :	 7;
+	bdrkreg_t	pdp_pointer1_b		  :	 3;
+	bdrkreg_t	pdp_reserved_4		  :	 6;
+	bdrkreg_t	pdp_pointer1_a		  :	 8;
+	bdrkreg_t	pdp_priority		  :	 3;
+	bdrkreg_t	pdp_state		  :	 3;
+	bdrkreg_t	pdp_format		  :	 2;
+};
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+struct	md_pdir_fine_fmt { /* shared (fine) */
+	bdrkreg_t	pdf_format                :	 2;
+        bdrkreg_t       pdf_tag1_a                :      3;
+        bdrkreg_t       pdf_tag2_a                :      3;
+        bdrkreg_t       pdf_vector1_a             :      8;
+        bdrkreg_t       pdf_reserved_1            :      6;
+        bdrkreg_t       pdf_tag1_b                :      2;
+        bdrkreg_t       pdf_vector1_b             :      8;
+        bdrkreg_t       pdf_ecc_a                 :      6;
+        bdrkreg_t       pdf_locprot               :      1;
+        bdrkreg_t       pdf_tag2valid             :      1;
+        bdrkreg_t       pdf_vector2_a             :      8;
+        bdrkreg_t       pdf_ecc_b                 :      1;
+        bdrkreg_t       pdf_reserved              :      5;
+        bdrkreg_t       pdf_tag2_b                :      2;
+        bdrkreg_t       pdf_vector2_b             :      8;
+};
+
+#else
+
+struct	md_pdir_fine_fmt { /* shared (fine) */
+	bdrkreg_t	pdf_vector2_b		  :	 8;
+	bdrkreg_t	pdf_tag2_b		  :	 2;
+	bdrkreg_t	pdf_reserved		  :	 5;
+	bdrkreg_t	pdf_ecc_b		  :	 1;
+	bdrkreg_t	pdf_vector2_a		  :	 8;
+	bdrkreg_t	pdf_tag2valid		  :	 1;
+	bdrkreg_t	pdf_locprot		  :	 1;
+	bdrkreg_t	pdf_ecc_a		  :	 6;
+	bdrkreg_t	pdf_vector1_b		  :	 8;
+	bdrkreg_t	pdf_tag1_b		  :	 2;
+	bdrkreg_t	pdf_reserved_1		  :	 6;
+	bdrkreg_t	pdf_vector1_a		  :	 8;
+	bdrkreg_t	pdf_tag2_a		  :	 3;
+	bdrkreg_t	pdf_tag1_a		  :	 3;
+	bdrkreg_t	pdf_format		  :	 2;
+};
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+struct	md_pdir_sparse_fmt { /* shared (sparse) */
+	bdrkreg_t	pds_format                :	 2;
+        bdrkreg_t       pds_column_a              :      6;
+        bdrkreg_t       pds_row_a                 :      8;
+        bdrkreg_t       pds_column_b              :     16;
+        bdrkreg_t       pds_ecc_a                 :      6;
+        bdrkreg_t       pds_locprot               :      1;
+        bdrkreg_t       pds_reserved_1            :      1;
+        bdrkreg_t       pds_row_b                 :      8;
+        bdrkreg_t       pds_ecc_b                 :      1;
+        bdrkreg_t       pds_column_c              :     10;
+        bdrkreg_t       pds_reserved              :      5;
+};
+
+#else
+
+struct	md_pdir_sparse_fmt { /* shared (sparse) */
+	bdrkreg_t	pds_reserved		  :	 5;
+	bdrkreg_t	pds_column_c		  :	10;
+	bdrkreg_t	pds_ecc_b		  :	 1;
+	bdrkreg_t	pds_row_b		  :	 8;
+	bdrkreg_t	pds_reserved_1		  :	 1;
+	bdrkreg_t	pds_locprot		  :	 1;
+	bdrkreg_t	pds_ecc_a		  :	 6;
+	bdrkreg_t	pds_column_b		  :	16;
+	bdrkreg_t	pds_row_a		  :	 8;
+	bdrkreg_t	pds_column_a		  :	 6;
+	bdrkreg_t	pds_format		  :	 2;
+};
+
+#endif
+
+typedef union md_pdir {
+	/* The 64 bits of premium directory */
+	uint64_t	pd_val;
+	struct	md_pdir_pointer_fmt	pdp_fmt;
+	struct	md_pdir_fine_fmt	pdf_fmt;
+	struct	md_pdir_sparse_fmt	pds_fmt;
+} md_pdir_t;
+
+#endif /* _LANGUAGE_C */
+
+
+/**********************************************************************
+
+ The defines for backdoor directory and backdoor ECC.
+
+***********************************************************************/
+
+/* Directory formats, for each format's "format" field */
+
+#define MD_FORMAT_UNOWNED	(UINT64_CAST 0x0)	/* 00 */
+#define MD_FORMAT_POINTER	(UINT64_CAST 0x1)	/* 01 */
+#define MD_FORMAT_SHFINE	(UINT64_CAST 0x2)	/* 10 */
+#define MD_FORMAT_SHCOARSE	(UINT64_CAST 0x3)	/* 11 */
+  /* Shared coarse (standard) and shared sparse (premium) both use fmt 0x3 */
+
+
+/*
+ * Cacheline state values.
+ *
+ * These are really *software* notions of the "state" of a cacheline; but the
+ * actual values have been carefully chosen to align with some hardware values!
+ * The MD_FMT_ST_TO_STATE macro is used to convert from hardware format/state
+ * pairs in the directory entried into one of these cacheline state values.
+ */
+
+#define MD_DIR_EXCLUSIVE	(UINT64_CAST 0x0)	/* ptr format, hw-defined */
+#define MD_DIR_UNOWNED		(UINT64_CAST 0x1)	/* format=0 */
+#define MD_DIR_SHARED		(UINT64_CAST 0x2)	/* format=2,3 */
+#define MD_DIR_BUSY_SHARED	(UINT64_CAST 0x4)	/* ptr format, hw-defined */
+#define MD_DIR_BUSY_EXCL	(UINT64_CAST 0x5)	/* ptr format, hw-defined */
+#define MD_DIR_WAIT		(UINT64_CAST 0x6)	/* ptr format, hw-defined */
+#define MD_DIR_POISONED		(UINT64_CAST 0x7)	/* ptr format, hw-defined */
+
+#ifdef _LANGUAGE_C
+
+/* Convert format and state fields into a single "cacheline state" value, defined above */
+
+#define MD_FMT_ST_TO_STATE(fmt, state) \
+  ((fmt) == MD_FORMAT_POINTER ? (state) : \
+   (fmt) == MD_FORMAT_UNOWNED ? MD_DIR_UNOWNED : \
+   MD_DIR_SHARED)
+#define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x))
+
+#endif /* _LANGUAGE_C */
+
+
+
+/* Directory field shifts and masks */
+
+/* Standard */
+
+#define MD_SDIR_FORMAT_SHFT	0			/* All formats */
+#define MD_SDIR_FORMAT_MASK	(0x3 << 0)
+#define MD_SDIR_STATE_SHFT	2			/* Pointer fmt. only */
+#define MD_SDIR_STATE_MASK	(0x7 << 2)
+
+/* Premium */
+
+#define MD_PDIR_FORMAT_SHFT	0			/* All formats */
+#define MD_PDIR_FORMAT_MASK	(0x3 << 0)
+#define MD_PDIR_STATE_SHFT	2			/* Pointer fmt. only */
+#define MD_PDIR_STATE_MASK	(0x7 << 2)
+
+/* Generic */
+
+#define MD_FORMAT_SHFT	0				/* All formats */
+#define MD_FORMAT_MASK	(0x3 << 0)
+#define MD_STATE_SHFT	2				/* Pointer fmt. only */
+#define MD_STATE_MASK	(0x7 << 2)
+
+
+/* Special shifts to reconstruct fields from the _a and _b parts */
+
+/* Standard:  only shared coarse has split fields */
+
+#define MD_SDC_VECTORB_SHFT	8	/* eg: sdc_vector_a is 8 bits */
+
+/* Premium:  pointer, shared fine, shared sparse */
+
+#define MD_PDP_POINTER1A_MASK	0xFF
+#define MD_PDP_POINTER1B_SHFT	8
+#define MD_PDP_POINTER2B_SHFT	5
+#define MD_PDP_ECCB_SHFT	6
+
+#define MD_PDF_VECTOR1B_SHFT	8
+#define MD_PDF_VECTOR2B_SHFT	8
+#define MD_PDF_TAG1B_SHFT	3
+#define MD_PDF_TAG2B_SHFT	3
+#define MD_PDF_ECC_SHFT		6
+
+#define MD_PDS_ROWB_SHFT	8
+#define MD_PDS_COLUMNB_SHFT	6
+#define MD_PDS_COLUMNC_SHFT	(MD_PDS_COLUMNB_SHFT + 16)
+#define MD_PDS_ECC_SHFT		6
+
+
+
+/*
+ * Directory/protection/counter initialization values, premium and standard
+ */
+
+#define MD_PDIR_INIT		0
+#define MD_PDIR_INIT_CNT	0
+#define MD_PDIR_INIT_PROT	0
+
+#define MD_SDIR_INIT		0
+#define MD_SDIR_INIT_CNT	0
+#define MD_SDIR_INIT_PROT	0
+
+#define MD_PDIR_MASK            0xffffffffffffffff
+#define MD_SDIR_MASK            0xffffffff
+
+/* When premium mode is on for probing but standard directory memory
+   is installed, the vaild directory bits depend on the phys. bank */
+#define MD_PDIR_PROBE_MASK(pb)  0xffffffffffffffff
+#define MD_SDIR_PROBE_MASK(pb)  (0xffff0000ffff << ((pb) ? 16 : 0))
+
+
+/*
+ * Misc. field extractions and conversions
+ */
+
+/* Convert an MD pointer (or message source, supplemental fields) */
+
+#define MD_PTR_NODE(x)		((x) >> MD_PTR_NODE_SHFT)
+#define MD_PTR_DEVICE(x)	((x) & MD_PTR_DEVICE_MASK)
+#define MD_PTR_SLICE(x)		(((x) & MD_PTR_SUBNODE0_MASK) | \
+				 ((x) & MD_PTR_SUBNODE1_MASK) >> 1)
+#define MD_PTR_OWNER_CPU(x)	(! ((x) & 2))
+#define MD_PTR_OWNER_IO(x)	((x) & 2)
+
+/* Extract format and raw state from a directory entry */
+
+#define MD_DIR_FORMAT(x)	((x) >> MD_SDIR_FORMAT_SHFT & \
+				 MD_SDIR_FORMAT_MASK >> MD_SDIR_FORMAT_SHFT)
+#define MD_DIR_STVAL(x)		((x) >> MD_SDIR_STATE_SHFT & \
+				 MD_SDIR_STATE_MASK >> MD_SDIR_STATE_SHFT)
+
+/* Mask & Shift to get HSPEC_ADDR from MD DIR_ERROR register */
+#define ERROR_ADDR_SHFT         3
+#define ERROR_HSPEC_SHFT        3
+#define DIR_ERR_HSPEC_MASK      0x1fffffff8
+
+/*
+ *  DIR_ERR* and MEM_ERR* defines are used to avoid ugly
+ *  #ifdefs for SN0 and SN1 in memerror.c code.  See SN0/hubmd.h
+ *  for corresponding SN0 definitions.
+ */
+#define md_dir_error_t  md_dir_error_u_t
+#define md_mem_error_t  md_mem_error_u_t
+#define derr_reg        md_dir_error_regval
+#define merr_reg        md_mem_error_regval
+
+#define DIR_ERR_UCE_VALID       dir_err.md_dir_error_fld_s.de_uce_valid
+#define DIR_ERR_AE_VALID        dir_err.md_dir_error_fld_s.de_ae_valid
+#define DIR_ERR_BAD_SYN         dir_err.md_dir_error_fld_s.de_bad_syn
+#define DIR_ERR_CE_OVERRUN      dir_err.md_dir_error_fld_s.de_ce_overrun
+#define MEM_ERR_ADDRESS         mem_err.md_mem_error_fld_s.me_address
+        /* BRINGUP Can the overrun bit be set without the valid bit? */
+#define MEM_ERR_CE_OVERRUN      (mem_err.md_mem_error_fld_s.me_read_ce >> 1)
+#define MEM_ERR_BAD_SYN         mem_err.md_mem_error_fld_s.me_bad_syn
+#define MEM_ERR_UCE_VALID       (mem_err.md_mem_error_fld_s.me_read_uce & 1)
+
+
+
+/*********************************************************************
+
+ We have the shift and masks of various fields defined below.
+
+ *********************************************************************/
+
+/* MD_REFRESH_CONTROL fields */
+
+#define MRC_ENABLE_SHFT         63
+#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
+#define MRC_ENABLE              (UINT64_CAST 1 << 63)
+#define MRC_COUNTER_SHFT        12
+#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
+#define MRC_CNT_THRESH_MASK     0xfff
+#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x800)
+
+/* MD_DIR_CONFIG fields */
+
+#define MDC_DIR_PREMIUM		(UINT64_CAST 1 << 0)
+#define MDC_IGNORE_ECC_SHFT      1
+#define MDC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 1)
+
+/* MD_MEMORY_CONFIG fields */
+
+#define MMC_RP_CONFIG_SHFT	61
+#define MMC_RP_CONFIG_MASK	(UINT64_CAST 1 << 61)
+#define MMC_RCD_CONFIG_SHFT	60
+#define MMC_RCD_CONFIG_MASK	(UINT64_CAST 1 << 60)
+#define MMC_MB_NEG_EDGE_SHFT	56
+#define MMC_MB_NEG_EDGE_MASK	(UINT64_CAST 0x7 << 56)
+#define MMC_SAMPLE_TIME_SHFT	52
+#define MMC_SAMPLE_TIME_MASK	(UINT64_CAST 0x3 << 52)
+#define MMC_DELAY_MUX_SEL_SHFT	50
+#define MMC_DELAY_MUX_SEL_MASK	(UINT64_CAST 0x3 << 50)
+#define MMC_PHASE_DELAY_SHFT	49
+#define MMC_PHASE_DELAY_MASK	(UINT64_CAST 1 << 49)
+#define MMC_DB_NEG_EDGE_SHFT	48
+#define MMC_DB_NEG_EDGE_MASK	(UINT64_CAST 1 << 48)
+#define MMC_CPU_PROT_IGNORE_SHFT	 47
+#define MMC_CPU_PROT_IGNORE_MASK	(UINT64_CAST 1 << 47)
+#define MMC_IO_PROT_IGNORE_SHFT 46
+#define MMC_IO_PROT_IGNORE_MASK	(UINT64_CAST 1 << 46)
+#define MMC_IO_PROT_EN_SHFT	45
+#define MMC_IO_PROT_EN_MASK	(UINT64_CAST 1 << 45)
+#define MMC_CC_ENABLE_SHFT	44
+#define MMC_CC_ENABLE_MASK	(UINT64_CAST 1 << 44)
+#define MMC_DIMM0_SEL_SHFT	32
+#define MMC_DIMM0_SEL_MASK     (UINT64_CAST 0x3 << 32)
+#define MMC_DIMM_SIZE_SHFT(_dimm)    ((_dimm << 3) + 4)
+#define MMC_DIMM_SIZE_MASK(_dimm)    (UINT64_CAST 0xf << MMC_DIMM_SIZE_SHFT(_dimm))
+#define MMC_DIMM_WIDTH_SHFT(_dimm)    ((_dimm << 3) + 3)
+#define MMC_DIMM_WIDTH_MASK(_dimm)    (UINT64_CAST 0x1 << MMC_DIMM_WIDTH_SHFT(_dimm))
+#define MMC_DIMM_BANKS_SHFT(_dimm)    (_dimm << 3)
+#define MMC_DIMM_BANKS_MASK(_dimm)    (UINT64_CAST 0x3 << MMC_DIMM_BANKS_SHFT(_dimm))
+#define MMC_BANK_ALL_MASK	0xffffffffLL
+/* Default values for write-only bits in MD_MEMORY_CONFIG */
+#define MMC_DEFAULT_BITS	(UINT64_CAST 0x7 << MMC_MB_NEG_EDGE_SHFT)
+
+/* MD_MB_ECC_CONFIG fields */
+
+#define MEC_IGNORE_ECC		(UINT64_CAST 0x1 << 0)
+
+/* MD_BIST_DATA fields */
+
+#define MBD_BIST_WRITE		(UINT64_CAST 1 << 7)
+#define MBD_BIST_CYCLE		(UINT64_CAST 1 << 6)
+#define MBD_BIST_BYTE		(UINT64_CAST 1 << 5)
+#define MBD_BIST_NIBBLE		(UINT64_CAST 1 << 4)
+#define MBD_BIST_DATA_MASK	0xf
+
+/* MD_BIST_CTL fields */
+
+#define MBC_DIMM_SHFT		5
+#define MBC_DIMM_MASK		(UINT64_CAST 0x3 << 5)
+#define MBC_BANK_SHFT		4
+#define MBC_BANK_MASK		(UINT64_CAST 0x1 << 4)
+#define MBC_BIST_RESET		(UINT64_CAST 0x1 << 2)
+#define MBC_BIST_STOP		(UINT64_CAST 0x1 << 1)
+#define MBC_BIST_START		(UINT64_CAST 0x1 << 0)
+
+#define MBC_GO(dimm, bank) \
+    (((dimm) << MBC_DIMM_SHFT) & MBC_DIMM_MASK | \
+     ((bank) << MBC_BANK_SHFT) & MBC_BANK_MASK | \
+     MBC_BIST_START)
+
+/* MD_BIST_STATUS fields */
+
+#define MBS_BIST_DONE		(UINT64_CAST 0X1 << 1)
+#define MBS_BIST_PASSED		(UINT64_CAST 0X1 << 0)
+
+/* MD_JUNK_BUS_TIMING fields */
+
+#define MJT_SYNERGY_ENABLE_SHFT	40
+#define MJT_SYNERGY_ENABLE_MASK	(UINT64_CAST 0Xff << MJT_SYNERGY_ENABLE_SHFT)
+#define MJT_SYNERGY_SETUP_SHFT	32
+#define MJT_SYNERGY_SETUP_MASK	(UINT64_CAST 0Xff << MJT_SYNERGY_SETUP_SHFT)
+#define MJT_UART_ENABLE_SHFT	24
+#define MJT_UART_ENABLE_MASK	(UINT64_CAST 0Xff << MJT_UART_ENABLE_SHFT)
+#define MJT_UART_SETUP_SHFT	16
+#define MJT_UART_SETUP_MASK	(UINT64_CAST 0Xff << MJT_UART_SETUP_SHFT)
+#define MJT_FPROM_ENABLE_SHFT	8
+#define MJT_FPROM_ENABLE_MASK	(UINT64_CAST 0Xff << MJT_FPROM_ENABLE_SHFT)
+#define MJT_FPROM_SETUP_SHFT	0
+#define MJT_FPROM_SETUP_MASK	(UINT64_CAST 0Xff << MJT_FPROM_SETUP_SHFT)
+
+#define MEM_ERROR_VALID_CE      1
+
+
+/* MD_FANDOP_CAC_STAT0, MD_FANDOP_CAC_STAT1 addr field shift */
+
+#define MFC_ADDR_SHFT		6
+
+#endif  /* _ASM_SN_SN1_HUBMD_NEXT_H */
diff --git a/include/asm-ia64/sn/sn1/hubni.h b/include/asm-ia64/sn/sn1/hubni.h
new file mode 100644
index 000000000..018aa9de6
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubni.h
@@ -0,0 +1,1782 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBNI_H
+#define _ASM_SN_SN1_HUBNI_H
+
+
+/************************************************************************
+ *                                                                      *
+ *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
+ *                                                                      *
+ * This file is created by an automated script. Any (minimal) changes   *
+ * made manually to this  file should be made with care.                *
+ *                                                                      *
+ *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
+ *                                                                      *
+ ************************************************************************/
+
+#define    NI_PORT_STATUS            0x00680000    /* LLP Status             */
+
+
+
+#define    NI_PORT_RESET             0x00680008    /*
+                                                    * Reset the Network
+                                                    * Interface
+                                                    */
+
+
+
+#define    NI_RESET_ENABLE           0x00680010    /* Warm Reset Enable      */
+
+
+
+#define    NI_DIAG_PARMS             0x00680018    /*
+                                                    * Diagnostic
+                                                    * Parameters
+                                                    */
+
+
+
+#define    NI_CHANNEL_CONTROL        0x00680020    /*
+                                                    * Virtual channel
+                                                    * control
+                                                    */
+
+
+
+#define    NI_CHANNEL_TEST           0x00680028    /* LLP Test Control.      */
+
+
+
+#define    NI_PORT_PARMS             0x00680030    /* LLP Parameters         */
+
+
+
+#define    NI_CHANNEL_AGE            0x00680038    /*
+                                                    * Network age
+                                                    * injection control
+                                                    */
+
+
+
+#define    NI_PORT_ERRORS            0x00680100    /* Errors                 */
+
+
+
+#define    NI_PORT_HEADER_A          0x00680108    /*
+                                                    * Error Header first
+                                                    * half
+                                                    */
+
+
+
+#define    NI_PORT_HEADER_B          0x00680110    /*
+                                                    * Error Header second
+                                                    * half
+                                                    */
+
+
+
+#define    NI_PORT_SIDEBAND          0x00680118    /* Error Sideband         */
+
+
+
+#define    NI_PORT_ERROR_CLEAR       0x00680120    /*
+                                                    * Clear the Error
+                                                    * bits
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_0          0x00681000    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_1          0x00681008    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_2          0x00681010    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_3          0x00681018    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_4          0x00681020    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_5          0x00681028    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_6          0x00681030    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_7          0x00681038    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_8          0x00681040    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_9          0x00681048    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_10         0x00681050    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_11         0x00681058    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_12         0x00681060    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_13         0x00681068    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_14         0x00681070    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_15         0x00681078    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_16         0x00681080    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_17         0x00681088    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_18         0x00681090    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_19         0x00681098    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_20         0x006810A0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_21         0x006810A8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_22         0x006810B0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_23         0x006810B8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_24         0x006810C0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_25         0x006810C8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_26         0x006810D0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_27         0x006810D8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_28         0x006810E0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_29         0x006810E8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_30         0x006810F0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_31         0x006810F8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_32         0x00681100    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_33         0x00681108    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_34         0x00681110    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_35         0x00681118    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_36         0x00681120    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_37         0x00681128    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_38         0x00681130    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_39         0x00681138    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_40         0x00681140    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_41         0x00681148    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_42         0x00681150    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_43         0x00681158    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_44         0x00681160    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_45         0x00681168    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_46         0x00681170    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_47         0x00681178    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_48         0x00681180    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_49         0x00681188    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_50         0x00681190    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_51         0x00681198    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_52         0x006811A0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_53         0x006811A8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_54         0x006811B0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_55         0x006811B8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_56         0x006811C0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_57         0x006811C8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_58         0x006811D0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_59         0x006811D8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_60         0x006811E0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_61         0x006811E8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_62         0x006811F0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_63         0x006811F8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_64         0x00681200    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_65         0x00681208    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_66         0x00681210    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_67         0x00681218    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_68         0x00681220    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_69         0x00681228    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_70         0x00681230    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_71         0x00681238    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_72         0x00681240    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_73         0x00681248    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_74         0x00681250    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_75         0x00681258    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_76         0x00681260    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_77         0x00681268    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_78         0x00681270    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_79         0x00681278    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_80         0x00681280    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_81         0x00681288    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_82         0x00681290    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_83         0x00681298    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_84         0x006812A0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_85         0x006812A8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_86         0x006812B0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_87         0x006812B8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_88         0x006812C0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_89         0x006812C8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_90         0x006812D0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_91         0x006812D8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_92         0x006812E0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_93         0x006812E8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_94         0x006812F0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_95         0x006812F8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_96         0x00681300    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_97         0x00681308    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_98         0x00681310    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_99         0x00681318    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_100        0x00681320    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_101        0x00681328    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_102        0x00681330    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_103        0x00681338    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_104        0x00681340    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_105        0x00681348    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_106        0x00681350    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_107        0x00681358    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_108        0x00681360    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_109        0x00681368    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_110        0x00681370    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_111        0x00681378    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_112        0x00681380    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_113        0x00681388    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_114        0x00681390    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_115        0x00681398    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_116        0x006813A0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_117        0x006813A8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_118        0x006813B0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_119        0x006813B8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_120        0x006813C0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_121        0x006813C8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_122        0x006813D0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_123        0x006813D8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_124        0x006813E0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_125        0x006813E8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_126        0x006813F0    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_LOCAL_TABLE_127        0x006813F8    /*
+                                                    * Base of Local
+                                                    * Mapping Table 0-127
+                                                    */
+
+
+
+#define    NI_GLOBAL_TABLE           0x00682000    /*
+                                                    * Base of Global
+                                                    * Mapping Table
+                                                    */
+
+
+
+
+
+#ifdef _LANGUAGE_C
+
+/************************************************************************
+ *                                                                      *
+ *  This register describes the LLP status.                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_status_u {
+	bdrkreg_t	ni_port_status_regval;
+	struct  {
+		bdrkreg_t	ps_port_status            :	 2;
+                bdrkreg_t       ps_remote_power           :      1;
+                bdrkreg_t       ps_rsvd                   :     61;
+	} ni_port_status_fld_s;
+} ni_port_status_u_t;
+
+#else
+
+typedef union ni_port_status_u {
+	bdrkreg_t	ni_port_status_regval;
+	struct	{
+		bdrkreg_t	ps_rsvd			  :	61;
+		bdrkreg_t	ps_remote_power		  :	 1;
+		bdrkreg_t	ps_port_status		  :	 2;
+	} ni_port_status_fld_s;
+} ni_port_status_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing this register issues a reset to the network interface.      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_reset_u {
+	bdrkreg_t	ni_port_reset_regval;
+	struct  {
+		bdrkreg_t	pr_link_reset_out         :	 1;
+                bdrkreg_t       pr_port_reset             :      1;
+                bdrkreg_t       pr_local_reset            :      1;
+                bdrkreg_t       pr_rsvd                   :     61;
+	} ni_port_reset_fld_s;
+} ni_port_reset_u_t;
+
+#else
+
+typedef union ni_port_reset_u {
+	bdrkreg_t	ni_port_reset_regval;
+	struct	{
+		bdrkreg_t	pr_rsvd			  :	61;
+		bdrkreg_t	pr_local_reset		  :	 1;
+		bdrkreg_t	pr_port_reset		  :	 1;
+		bdrkreg_t	pr_link_reset_out	  :	 1;
+	} ni_port_reset_fld_s;
+} ni_port_reset_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the warm reset enable bit.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_reset_enable_u {
+	bdrkreg_t	ni_reset_enable_regval;
+	struct  {
+		bdrkreg_t	re_reset_ok               :	 1;
+                bdrkreg_t       re_rsvd                   :     63;
+	} ni_reset_enable_fld_s;
+} ni_reset_enable_u_t;
+
+#else
+
+typedef union ni_reset_enable_u {
+	bdrkreg_t	ni_reset_enable_regval;
+	struct	{
+		bdrkreg_t	re_rsvd			  :	63;
+		bdrkreg_t	re_reset_ok		  :	 1;
+	} ni_reset_enable_fld_s;
+} ni_reset_enable_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains parameters for diagnostics.                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_diag_parms_u {
+	bdrkreg_t	ni_diag_parms_regval;
+	struct  {
+		bdrkreg_t	dp_send_data_error        :	 1;
+                bdrkreg_t       dp_port_disable           :      1;
+                bdrkreg_t       dp_send_err_off           :      1;
+                bdrkreg_t       dp_rsvd                   :     61;
+	} ni_diag_parms_fld_s;
+} ni_diag_parms_u_t;
+
+#else
+
+typedef union ni_diag_parms_u {
+	bdrkreg_t	ni_diag_parms_regval;
+	struct	{
+		bdrkreg_t	dp_rsvd			  :	61;
+		bdrkreg_t	dp_send_err_off		  :	 1;
+		bdrkreg_t	dp_port_disable		  :	 1;
+		bdrkreg_t	dp_send_data_error	  :	 1;
+	} ni_diag_parms_fld_s;
+} ni_diag_parms_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the virtual channel selection control for    *
+ * outgoing messages from the Bedrock.                                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_channel_control_u {
+	bdrkreg_t	ni_channel_control_regval;
+	struct  {
+		bdrkreg_t	cc_vch_one_request        :	 1;
+                bdrkreg_t       cc_vch_two_request        :      1;
+                bdrkreg_t       cc_vch_nine_request       :      1;
+                bdrkreg_t       cc_vch_vector_request     :      1;
+                bdrkreg_t       cc_vch_one_reply          :      1;
+                bdrkreg_t       cc_vch_two_reply          :      1;
+                bdrkreg_t       cc_vch_nine_reply         :      1;
+                bdrkreg_t       cc_vch_vector_reply       :      1;
+                bdrkreg_t       cc_send_vch_sel           :      1;
+                bdrkreg_t       cc_rsvd                   :     55;
+	} ni_channel_control_fld_s;
+} ni_channel_control_u_t;
+
+#else
+
+typedef union ni_channel_control_u {
+	bdrkreg_t	ni_channel_control_regval;
+	struct	{
+		bdrkreg_t	cc_rsvd			  :	55;
+		bdrkreg_t	cc_send_vch_sel		  :	 1;
+		bdrkreg_t	cc_vch_vector_reply	  :	 1;
+		bdrkreg_t	cc_vch_nine_reply	  :	 1;
+		bdrkreg_t	cc_vch_two_reply	  :	 1;
+		bdrkreg_t	cc_vch_one_reply	  :	 1;
+		bdrkreg_t	cc_vch_vector_request	  :	 1;
+		bdrkreg_t	cc_vch_nine_request	  :	 1;
+		bdrkreg_t	cc_vch_two_request	  :	 1;
+		bdrkreg_t	cc_vch_one_request	  :	 1;
+	} ni_channel_control_fld_s;
+} ni_channel_control_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows access to the LLP test logic.                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_channel_test_u {
+	bdrkreg_t	ni_channel_test_regval;
+	struct  {
+		bdrkreg_t	ct_testseed               :	20;
+                bdrkreg_t       ct_testmask               :      8;
+                bdrkreg_t       ct_testdata               :     20;
+                bdrkreg_t       ct_testvalid              :      1;
+                bdrkreg_t       ct_testcberr              :      1;
+                bdrkreg_t       ct_testflit               :      3;
+                bdrkreg_t       ct_testclear              :      1;
+                bdrkreg_t       ct_testerrcapture         :      1;
+                bdrkreg_t       ct_rsvd                   :      9;
+	} ni_channel_test_fld_s;
+} ni_channel_test_u_t;
+
+#else
+
+typedef union ni_channel_test_u {
+	bdrkreg_t	ni_channel_test_regval;
+	struct	{
+		bdrkreg_t	ct_rsvd			  :	 9;
+		bdrkreg_t	ct_testerrcapture	  :	 1;
+		bdrkreg_t	ct_testclear		  :	 1;
+		bdrkreg_t	ct_testflit		  :	 3;
+		bdrkreg_t	ct_testcberr		  :	 1;
+		bdrkreg_t	ct_testvalid		  :	 1;
+		bdrkreg_t	ct_testdata		  :	20;
+		bdrkreg_t	ct_testmask		  :	 8;
+		bdrkreg_t	ct_testseed		  :	20;
+	} ni_channel_test_fld_s;
+} ni_channel_test_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains LLP port parameters and enables for the      *
+ * capture of header data.                                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_parms_u {
+	bdrkreg_t	ni_port_parms_regval;
+	struct  {
+		bdrkreg_t	pp_max_burst              :	10;
+                bdrkreg_t       pp_null_timeout           :      6;
+                bdrkreg_t       pp_max_retry              :     10;
+                bdrkreg_t       pp_d_avail_sel            :      2;
+                bdrkreg_t       pp_rsvd_1                 :      1;
+                bdrkreg_t       pp_first_err_enable       :      1;
+                bdrkreg_t       pp_squash_err_enable      :      1;
+                bdrkreg_t       pp_vch_err_enable         :      4;
+                bdrkreg_t       pp_rsvd                   :     29;
+	} ni_port_parms_fld_s;
+} ni_port_parms_u_t;
+
+#else
+
+typedef union ni_port_parms_u {
+	bdrkreg_t	ni_port_parms_regval;
+	struct	{
+		bdrkreg_t	pp_rsvd			  :	29;
+		bdrkreg_t	pp_vch_err_enable	  :	 4;
+		bdrkreg_t	pp_squash_err_enable	  :	 1;
+		bdrkreg_t	pp_first_err_enable	  :	 1;
+		bdrkreg_t	pp_rsvd_1		  :	 1;
+		bdrkreg_t	pp_d_avail_sel		  :	 2;
+		bdrkreg_t	pp_max_retry		  :	10;
+		bdrkreg_t	pp_null_timeout		  :	 6;
+		bdrkreg_t	pp_max_burst		  :	10;
+	} ni_port_parms_fld_s;
+} ni_port_parms_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the age at which request and reply packets   *
+ * are injected into the network. This feature allows replies to be     *
+ * given a higher fixed priority than requests, which can be            *
+ * important in some network saturation situations.                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_channel_age_u {
+	bdrkreg_t	ni_channel_age_regval;
+	struct  {
+		bdrkreg_t	ca_request_inject_age     :	 8;
+                bdrkreg_t       ca_reply_inject_age       :      8;
+                bdrkreg_t       ca_rsvd                   :     48;
+	} ni_channel_age_fld_s;
+} ni_channel_age_u_t;
+
+#else
+
+typedef union ni_channel_age_u {
+	bdrkreg_t	ni_channel_age_regval;
+	struct	{
+		bdrkreg_t	ca_rsvd			  :	48;
+		bdrkreg_t	ca_reply_inject_age	  :	 8;
+		bdrkreg_t	ca_request_inject_age	  :	 8;
+	} ni_channel_age_fld_s;
+} ni_channel_age_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains latched LLP port and problematic message     *
+ * errors. The contents are the same information as the                 *
+ * NI_PORT_ERROR_CLEAR register, but, in this register read accesses    *
+ * are non-destructive. Bits [52:24] assert the NI interrupt.           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_errors_u {
+	bdrkreg_t	ni_port_errors_regval;
+	struct  {
+		bdrkreg_t	pe_sn_error_count         :	 8;
+                bdrkreg_t       pe_cb_error_count         :      8;
+                bdrkreg_t       pe_retry_count            :      8;
+                bdrkreg_t       pe_tail_timeout           :      4;
+                bdrkreg_t       pe_fifo_overflow          :      4;
+                bdrkreg_t       pe_external_short         :      4;
+                bdrkreg_t       pe_external_long          :      4;
+                bdrkreg_t       pe_external_bad_header    :      4;
+                bdrkreg_t       pe_internal_short         :      4;
+                bdrkreg_t       pe_internal_long          :      4;
+                bdrkreg_t       pe_link_reset_in          :      1;
+                bdrkreg_t       pe_rsvd                   :     11;
+	} ni_port_errors_fld_s;
+} ni_port_errors_u_t;
+
+#else
+
+typedef union ni_port_errors_u {
+	bdrkreg_t	ni_port_errors_regval;
+	struct	{
+		bdrkreg_t	pe_rsvd			  :	11;
+		bdrkreg_t	pe_link_reset_in	  :	 1;
+		bdrkreg_t	pe_internal_long	  :	 4;
+		bdrkreg_t	pe_internal_short	  :	 4;
+		bdrkreg_t	pe_external_bad_header	  :	 4;
+		bdrkreg_t	pe_external_long	  :	 4;
+		bdrkreg_t	pe_external_short	  :	 4;
+		bdrkreg_t	pe_fifo_overflow	  :	 4;
+		bdrkreg_t	pe_tail_timeout		  :	 4;
+		bdrkreg_t	pe_retry_count		  :	 8;
+		bdrkreg_t	pe_cb_error_count	  :	 8;
+		bdrkreg_t	pe_sn_error_count	  :	 8;
+	} ni_port_errors_fld_s;
+} ni_port_errors_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides the sideband data associated with the        *
+ * NI_PORT_HEADER registers and also additional data for error          *
+ * processing. This register is not cleared on reset.                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_sideband_u {
+	bdrkreg_t	ni_port_sideband_regval;
+	struct  {
+		bdrkreg_t	ps_sideband               :	 8;
+                bdrkreg_t       ps_bad_dest               :      1;
+                bdrkreg_t       ps_bad_prexsel            :      1;
+                bdrkreg_t       ps_rcv_error              :      1;
+                bdrkreg_t       ps_bad_message            :      1;
+                bdrkreg_t       ps_squash                 :      1;
+                bdrkreg_t       ps_sn_status              :      1;
+                bdrkreg_t       ps_cb_status              :      1;
+                bdrkreg_t       ps_send_error             :      1;
+                bdrkreg_t       ps_vch_active             :      4;
+                bdrkreg_t       ps_rsvd                   :     44;
+	} ni_port_sideband_fld_s;
+} ni_port_sideband_u_t;
+
+#else
+
+typedef union ni_port_sideband_u {
+	bdrkreg_t	ni_port_sideband_regval;
+	struct	{
+		bdrkreg_t	ps_rsvd			  :	44;
+		bdrkreg_t	ps_vch_active		  :	 4;
+		bdrkreg_t	ps_send_error		  :	 1;
+		bdrkreg_t	ps_cb_status		  :	 1;
+		bdrkreg_t	ps_sn_status		  :	 1;
+		bdrkreg_t	ps_squash		  :	 1;
+		bdrkreg_t	ps_bad_message		  :	 1;
+		bdrkreg_t	ps_rcv_error		  :	 1;
+		bdrkreg_t	ps_bad_prexsel		  :	 1;
+		bdrkreg_t	ps_bad_dest		  :	 1;
+		bdrkreg_t	ps_sideband		  :	 8;
+	} ni_port_sideband_fld_s;
+} ni_port_sideband_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains latched LLP port and problematic message     *
+ * errors. The contents are the same information as the                 *
+ * NI_PORT_ERROR_CLEAR register, but, in this register read accesses    *
+ * are non-destructive. Bits [52:24] assert the NI interrupt.           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_error_clear_u {
+	bdrkreg_t	ni_port_error_clear_regval;
+	struct  {
+		bdrkreg_t	pec_sn_error_count        :	 8;
+                bdrkreg_t       pec_cb_error_count        :      8;
+                bdrkreg_t       pec_retry_count           :      8;
+                bdrkreg_t       pec_tail_timeout          :      4;
+                bdrkreg_t       pec_fifo_overflow         :      4;
+                bdrkreg_t       pec_external_short        :      4;
+                bdrkreg_t       pec_external_long         :      4;
+                bdrkreg_t       pec_external_bad_header   :      4;
+                bdrkreg_t       pec_internal_short        :      4;
+                bdrkreg_t       pec_internal_long         :      4;
+                bdrkreg_t       pec_link_reset_in         :      1;
+                bdrkreg_t       pec_rsvd                  :     11;
+	} ni_port_error_clear_fld_s;
+} ni_port_error_clear_u_t;
+
+#else
+
+typedef union ni_port_error_clear_u {
+	bdrkreg_t	ni_port_error_clear_regval;
+	struct	{
+		bdrkreg_t	pec_rsvd		  :	11;
+		bdrkreg_t	pec_link_reset_in	  :	 1;
+		bdrkreg_t	pec_internal_long	  :	 4;
+		bdrkreg_t	pec_internal_short	  :	 4;
+		bdrkreg_t	pec_external_bad_header	  :	 4;
+		bdrkreg_t	pec_external_long	  :	 4;
+		bdrkreg_t	pec_external_short	  :	 4;
+		bdrkreg_t	pec_fifo_overflow	  :	 4;
+		bdrkreg_t	pec_tail_timeout	  :	 4;
+		bdrkreg_t	pec_retry_count		  :	 8;
+		bdrkreg_t	pec_cb_error_count	  :	 8;
+		bdrkreg_t	pec_sn_error_count	  :	 8;
+	} ni_port_error_clear_fld_s;
+} ni_port_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Lookup table for the next hop's exit port. The table entry          *
+ * selection is based on the 7-bit LocalCube routing destination.       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_local_table_0_u {
+	bdrkreg_t	ni_local_table_0_regval;
+	struct  {
+		bdrkreg_t	lt0_next_exit_port        :	 4;
+                bdrkreg_t       lt0_next_vch_lsb          :      1;
+                bdrkreg_t       lt0_rsvd                  :     59;
+	} ni_local_table_0_fld_s;
+} ni_local_table_0_u_t;
+
+#else
+
+typedef union ni_local_table_0_u {
+	bdrkreg_t	ni_local_table_0_regval;
+	struct	{
+		bdrkreg_t	lt0_rsvd		  :	59;
+		bdrkreg_t	lt0_next_vch_lsb	  :	 1;
+		bdrkreg_t	lt0_next_exit_port	  :	 4;
+	} ni_local_table_0_fld_s;
+} ni_local_table_0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Lookup table for the next hop's exit port. The table entry          *
+ * selection is based on the 7-bit LocalCube routing destination.       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_local_table_127_u {
+	bdrkreg_t	ni_local_table_127_regval;
+	struct  {
+		bdrkreg_t	lt1_next_exit_port        :	 4;
+                bdrkreg_t       lt1_next_vch_lsb          :      1;
+                bdrkreg_t       lt1_rsvd                  :     59;
+	} ni_local_table_127_fld_s;
+} ni_local_table_127_u_t;
+
+#else
+
+typedef union ni_local_table_127_u {
+	bdrkreg_t	ni_local_table_127_regval;
+	struct	{
+		bdrkreg_t	lt1_rsvd		  :	59;
+		bdrkreg_t	lt1_next_vch_lsb	  :	 1;
+		bdrkreg_t	lt1_next_exit_port	  :	 4;
+	} ni_local_table_127_fld_s;
+} ni_local_table_127_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Lookup table for the next hop's exit port. The table entry          *
+ * selection is based on the 1-bit MetaCube routing destination.        *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_global_table_u {
+	bdrkreg_t	ni_global_table_regval;
+	struct  {
+		bdrkreg_t	gt_next_exit_port         :	 4;
+                bdrkreg_t       gt_next_vch_lsb           :      1;
+                bdrkreg_t       gt_rsvd                   :     59;
+	} ni_global_table_fld_s;
+} ni_global_table_u_t;
+
+#else
+
+typedef union ni_global_table_u {
+	bdrkreg_t	ni_global_table_regval;
+	struct	{
+		bdrkreg_t	gt_rsvd			  :	59;
+		bdrkreg_t	gt_next_vch_lsb		  :	 1;
+		bdrkreg_t	gt_next_exit_port	  :	 4;
+	} ni_global_table_fld_s;
+} ni_global_table_u_t;
+
+#endif
+
+
+
+
+
+
+#endif /* _LANGUAGE_C */
+
+/************************************************************************
+ *                                                                      *
+ * The following defines which were not formed into structures are      *
+ * probably indentical to another register, and the name of the         *
+ * register is provided against each of these registers. This           *
+ * information needs to be checked carefully                            *
+ *                                                                      *
+ *           NI_LOCAL_TABLE_1          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_2          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_3          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_4          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_5          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_6          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_7          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_8          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_9          NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_10         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_11         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_12         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_13         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_14         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_15         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_16         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_17         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_18         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_19         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_20         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_21         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_22         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_23         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_24         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_25         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_26         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_27         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_28         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_29         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_30         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_31         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_32         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_33         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_34         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_35         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_36         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_37         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_38         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_39         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_40         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_41         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_42         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_43         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_44         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_45         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_46         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_47         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_48         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_49         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_50         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_51         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_52         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_53         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_54         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_55         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_56         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_57         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_58         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_59         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_60         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_61         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_62         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_63         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_64         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_65         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_66         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_67         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_68         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_69         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_70         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_71         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_72         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_73         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_74         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_75         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_76         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_77         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_78         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_79         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_80         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_81         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_82         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_83         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_84         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_85         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_86         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_87         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_88         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_89         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_90         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_91         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_92         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_93         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_94         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_95         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_96         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_97         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_98         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_99         NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_100        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_101        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_102        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_103        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_104        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_105        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_106        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_107        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_108        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_109        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_110        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_111        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_112        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_113        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_114        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_115        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_116        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_117        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_118        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_119        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_120        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_121        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_122        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_123        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_124        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_125        NI_LOCAL_TABLE_0                 *
+ *           NI_LOCAL_TABLE_126        NI_LOCAL_TABLE_0                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+/************************************************************************
+ *                                                                      *
+ * The following defines were not formed into structures                *
+ *                                                                      *
+ * This could be because the document did not contain details of the    *
+ * register, or because the automated script did not recognize the      *
+ * register details in the documentation. If these register need        *
+ * structure definition, please create them manually                    *
+ *                                                                      *
+ *           NI_PORT_HEADER_A         0x680108                          *
+ *           NI_PORT_HEADER_B         0x680110                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+/************************************************************************
+ *                                                                      *
+ *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+
+#endif /* _ASM_SN_SN1_HUBNI_H */
diff --git a/include/asm-ia64/sn/sn1/hubni_next.h b/include/asm-ia64/sn/sn1/hubni_next.h
new file mode 100644
index 000000000..3d0dbed4c
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubni_next.h
@@ -0,0 +1,175 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBNI_NEXT_H
+#define _ASM_SN_SN1_HUBNI_NEXT_H
+
+#define NI_LOCAL_ENTRIES        128
+#define NI_META_ENTRIES        1
+
+#define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE_0 + (8 * (_x)))
+#define NI_META_TABLE(_x)       (NI_GLOBAL_TABLE + (8 * (_x)))
+
+/**************************************************************
+
+  Masks and shifts for NI registers are defined below. 
+
+**************************************************************/
+
+#define NPS_LINKUP_SHFT        1
+#define NPS_LINKUP_MASK        (UINT64_CAST 0x1 << 1)
+
+
+#define NPR_LOCALRESET          (UINT64_CAST 1 << 2)    /* Reset loc. bdrck */
+#define NPR_PORTRESET           (UINT64_CAST 1 << 1)    /* Send warm reset  */
+#define NPR_LINKRESET           (UINT64_CAST 1 << 0)    /* Send link reset  */
+
+/* NI_DIAG_PARMS bit definitions */
+#define NDP_SENDERROR           (UINT64_CAST 1 <<  0)   /* Send data error  */
+#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  1)   /* Port disable     */
+#define NDP_SENDERROFF          (UINT64_CAST 1 <<  2)   /* Disable send error recovery */
+
+
+/* NI_PORT_ERROR mask and shift definitions (some are not present in SN0) */
+
+#define NPE_LINKRESET		(UINT64_CAST 1 << 52)
+#define NPE_INTLONG_SHFT	48
+#define NPE_INTLONG_MASK	(UINT64_CAST 0xf << NPE_INTLONG_SHFT)
+#define NPE_INTSHORT_SHFT	44
+#define NPE_INTSHORT_MASK	(UINT64_CAST 0xf << NPE_INTSHORT_SHFT)
+#define NPE_EXTBADHEADER_SHFT	40
+#define NPE_EXTBADHEADER_MASK	(UINT64_CAST 0xf << NPE_EXTBADHEADER_SHFT)
+#define NPE_EXTLONG_SHFT	36
+#define NPE_EXTLONG_MASK	(UINT64_CAST 0xf << NPE_EXTLONG_SHFT)
+#define NPE_EXTSHORT_SHFT	32
+#define NPE_EXTSHORT_MASK	(UINT64_CAST 0xf << NPE_EXTSHORT_SHFT)
+#define NPE_FIFOOVFLOW_SHFT	28
+#define NPE_FIFOOVFLOW_MASK	(UINT64_CAST 0xf << NPE_FIFOOVFLOW_SHFT)
+#define NPE_TAILTO_SHFT		24
+#define NPE_TAILTO_MASK		(UINT64_CAST 0xf << NPE_TAILTO_SHFT)
+#define NPE_RETRYCOUNT_SHFT	16
+#define NPE_RETRYCOUNT_MASK	(UINT64_CAST 0xff << NPE_RETRYCOUNT_SHFT)
+#define NPE_CBERRCOUNT_SHFT	8
+#define NPE_CBERRCOUNT_MASK	(UINT64_CAST 0xff << NPE_CBERRCOUNT_SHFT)
+#define NPE_SNERRCOUNT_SHFT	0
+#define NPE_SNERRCOUNT_MASK	(UINT64_CAST 0xff << NPE_SNERRCOUNT_SHFT)
+
+#define NPE_COUNT_MAX		0xff
+
+#define NPE_FATAL_ERRORS	(NPE_LINKRESET | NPE_INTLONG_MASK |\
+				 NPE_INTSHORT_MASK | NPE_EXTBADHEADER_MASK |\
+				 NPE_EXTLONG_MASK | NPE_EXTSHORT_MASK |\
+				 NPE_FIFOOVFLOW_MASK | NPE_TAILTO_MASK)
+
+#ifdef _LANGUAGE_C
+/* NI_PORT_HEADER[AB] registers (not automatically generated) */
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_header_a_u {
+	bdrkreg_t	ni_port_header_a_regval;
+	struct  {
+		bdrkreg_t	pha_v                     :	 1;
+                bdrkreg_t       pha_age                   :      8;
+                bdrkreg_t       pha_direction             :      4;
+                bdrkreg_t       pha_destination           :      8;
+                bdrkreg_t       pha_reserved_1            :      3;
+                bdrkreg_t       pha_command               :      8;
+                bdrkreg_t       pha_prexsel               :      3;
+                bdrkreg_t       pha_address_b             :     27;
+                bdrkreg_t       pha_reserved              :      2;
+	} ni_port_header_a_fld_s;
+} ni_port_header_a_u_t;
+
+#else
+
+typedef union ni_port_header_a_u {
+	bdrkreg_t	ni_port_header_a_regval;
+	struct	{
+		bdrkreg_t	pha_reserved		  :	 2;
+		bdrkreg_t	pha_address_b		  :	27;
+		bdrkreg_t	pha_prexsel		  :	 3;
+		bdrkreg_t	pha_command		  :	 8;
+		bdrkreg_t	pha_reserved_1		  :	 3;
+		bdrkreg_t	pha_destination		  :	 8;
+		bdrkreg_t	pha_direction		  :	 4;
+		bdrkreg_t	pha_age			  :	 8;
+		bdrkreg_t	pha_v			  :	 1;
+	} ni_port_header_a_fld_s;
+} ni_port_header_a_u_t;
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+typedef union ni_port_header_b_u {
+	bdrkreg_t	ni_port_header_b_regval;
+	struct  {
+		bdrkreg_t	phb_supplemental           :	11;
+                bdrkreg_t       phb_reserved_2            :      5;
+                bdrkreg_t       phb_source                :     11;
+                bdrkreg_t       phb_reserved_1            :      8;
+                bdrkreg_t       phb_address_a             :      3;
+                bdrkreg_t       phb_address_c             :      8;
+                bdrkreg_t       phb_reserved              :     18;
+	} ni_port_header_b_fld_s;
+} ni_port_header_b_u_t;
+
+#else
+
+typedef union ni_port_header_b_u {
+	bdrkreg_t	ni_port_header_b_regval;
+	struct	{
+		bdrkreg_t	phb_reserved		  :	18;
+		bdrkreg_t	phb_address_c		  :	 8;
+		bdrkreg_t	phb_address_a		  :	 3;
+		bdrkreg_t	phb_reserved_1		  :	 8;
+		bdrkreg_t	phb_source		  :	11;
+		bdrkreg_t	phb_reserved_2		  :	 5;
+		bdrkreg_t	phb_supplemental	   :	11;
+	} ni_port_header_b_fld_s;
+} ni_port_header_b_u_t;
+
+#endif
+#endif
+
+/* NI_RESET_ENABLE mask definitions */
+
+#define NRE_RESETOK		(UINT64_CAST 1)	/* Let LLP reset bedrock */
+
+/* NI PORT_ERRORS, Max number of RETRY_COUNT, Check Bit, and Sequence   */
+/* Number errors (8 bit counters that do not wrap).                     */
+#define NI_LLP_RETRY_MAX        0xff
+#define NI_LLP_CB_MAX           0xff
+#define NI_LLP_SN_MAX           0xff
+
+/* NI_PORT_PARMS shift and mask definitions */
+
+#define NPP_VCH_ERR_EN_SHFT	31
+#define NPP_VCH_ERR_EN_MASK	(0xf << NPP_VCH_ERR_EN_SHFT)
+#define NPP_SQUASH_ERR_EN_SHFT	30
+#define NPP_SQUASH_ERR_EN_MASK	(0x1 << NPP_SQUASH_ERR_EN_SHFT)
+#define NPP_FIRST_ERR_EN_SHFT	29
+#define NPP_FIRST_ERR_EN_MASK	(0x1 << NPP_FIRST_ERR_EN_SHFT)
+#define NPP_D_AVAIL_SEL_SHFT	26
+#define NPP_D_AVAIL_SEL_MASK	(0x3 << NPP_D_AVAIL_SEL_SHFT)
+#define NPP_MAX_RETRY_SHFT	16
+#define NPP_MAX_RETRY_MASK	(0x3ff << NPP_MAX_RETRY_SHFT)
+#define NPP_NULL_TIMEOUT_SHFT	10
+#define NPP_NULL_TIMEOUT_MASK	(0x3f << NPP_NULL_TIMEOUT_SHFT)
+#define NPP_MAX_BURST_SHFT	0
+#define NPP_MAX_BURST_MASK	(0x3ff << NPP_MAX_BURST_SHFT)
+
+#define NPP_RESET_DEFAULTS	(0xf << NPP_VCH_ERR_EN_SHFT |   \
+				 0x1 << NPP_FIRST_ERR_EN_SHFT | \
+				 0x3ff << NPP_MAX_RETRY_SHFT |  \
+				 0x6 << NPP_NULL_TIMEOUT_SHFT | \
+				 0x3f0 << NPP_MAX_BURST_SHFT)
+
+#endif  /* _ASM_SN_SN1_HUBNI_NEXT_H */
diff --git a/include/asm-ia64/sn/sn1/hubpi.h b/include/asm-ia64/sn/sn1/hubpi.h
new file mode 100644
index 000000000..4b81ca32b
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubpi.h
@@ -0,0 +1,4264 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBPI_H
+#define _ASM_SN_SN1_HUBPI_H
+
+/************************************************************************
+ *                                                                      *
+ *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
+ *                                                                      *
+ * This file is created by an automated script. Any (minimal) changes   *
+ * made manually to this  file should be made with care.                *
+ *                                                                      *
+ *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
+ *                                                                      *
+ ************************************************************************/
+
+
+#define    PI_CPU_PROTECT            0x00000000    /* CPU Protection         */
+
+
+
+#define    PI_PROT_OVRRD             0x00000008    /*
+                                                    * Clear CPU
+                                                    * Protection bit in 
+                                                    * CPU_PROTECT
+                                                    */
+
+
+
+#define    PI_IO_PROTECT             0x00000010    /*
+                                                    * Interrupt Pending
+                                                    * Protection for IO
+                                                    * access
+                                                    */
+
+
+
+#define    PI_REGION_PRESENT         0x00000018    /* Region present         */
+
+
+
+#define    PI_CPU_NUM                0x00000020    /* CPU Number ID          */
+
+
+
+#define    PI_CALIAS_SIZE            0x00000028    /* Cached Alias Size      */
+
+
+
+#define    PI_MAX_CRB_TIMEOUT        0x00000030    /*
+                                                    * Maximum Timeout for
+                                                    * CRB
+                                                    */
+
+
+
+#define    PI_CRB_SFACTOR            0x00000038    /*
+                                                    * Scale Factor for
+                                                    * CRB Timeout
+                                                    */
+
+
+
+#define    PI_CPU_PRESENT_A          0x00000040    /*
+                                                    * CPU Present for
+                                                    * CPU_A
+                                                    */
+
+
+
+#define    PI_CPU_PRESENT_B          0x00000048    /*
+                                                    * CPU Present for
+                                                    * CPU_B
+                                                    */
+
+
+
+#define    PI_CPU_ENABLE_A           0x00000050    /*
+                                                    * CPU Enable for
+                                                    * CPU_A
+                                                    */
+
+
+
+#define    PI_CPU_ENABLE_B           0x00000058    /*
+                                                    * CPU Enable for
+                                                    * CPU_B
+                                                    */
+
+
+
+#define    PI_REPLY_LEVEL            0x00010060    /*
+                                                    * Reply FIFO Priority
+                                                    * Control
+                                                    */
+
+
+
+#define    PI_GFX_CREDIT_MODE        0x00020068    /*
+                                                    * Graphics Credit
+                                                    * Mode
+                                                    */
+
+
+
+#define    PI_NMI_A                  0x00000070    /*
+                                                    * Non-maskable
+                                                    * Interrupt to CPU A
+                                                    */
+
+
+
+#define    PI_NMI_B                  0x00000078    /*
+                                                    * Non-maskable
+                                                    * Interrupt to CPU B
+                                                    */
+
+
+
+#define    PI_INT_PEND_MOD           0x00000090    /*
+                                                    * Interrupt Pending
+                                                    * Modify
+                                                    */
+
+
+
+#define    PI_INT_PEND0              0x00000098    /* Interrupt Pending 0    */
+
+
+
+#define    PI_INT_PEND1              0x000000A0    /* Interrupt Pending 1    */
+
+
+
+#define    PI_INT_MASK0_A            0x000000A8    /*
+                                                    * Interrupt Mask 0
+                                                    * for CPU A
+                                                    */
+
+
+
+#define    PI_INT_MASK1_A            0x000000B0    /*
+                                                    * Interrupt Mask 1
+                                                    * for CPU A
+                                                    */
+
+
+
+#define    PI_INT_MASK0_B            0x000000B8    /*
+                                                    * Interrupt Mask 0
+                                                    * for CPU B
+                                                    */
+
+
+
+#define    PI_INT_MASK1_B            0x000000C0    /*
+                                                    * Interrupt Mask 1
+                                                    * for CPU B
+                                                    */
+
+
+
+#define    PI_CC_PEND_SET_A          0x000000C8    /*
+                                                    * CC Interrupt
+                                                    * Pending for CPU A
+                                                    */
+
+
+
+#define    PI_CC_PEND_SET_B          0x000000D0    /*
+                                                    * CC Interrupt
+                                                    * Pending for CPU B
+                                                    */
+
+
+
+#define    PI_CC_PEND_CLR_A          0x000000D8    /*
+                                                    * CPU to CPU
+                                                    * Interrupt Pending
+                                                    * Clear for CPU A
+                                                    */
+
+
+
+#define    PI_CC_PEND_CLR_B          0x000000E0    /*
+                                                    * CPU to CPU
+                                                    * Interrupt Pending
+                                                    * Clear for CPU B
+                                                    */
+
+
+
+#define    PI_CC_MASK                0x000000E8    /*
+                                                    * Mask of both
+                                                    * CC_PENDs
+                                                    */
+
+
+
+#define    PI_INT_PEND1_REMAP        0x000000F0    /*
+                                                    * Remap Interrupt
+                                                    * Pending
+                                                    */
+
+
+
+#define    PI_RT_COUNTER             0x00030100    /* Real Time Counter      */
+
+
+
+#define    PI_RT_COMPARE_A           0x00000108    /* Real Time Compare A    */
+
+
+
+#define    PI_RT_COMPARE_B           0x00000110    /* Real Time Compare B    */
+
+
+
+#define    PI_PROFILE_COMPARE        0x00000118    /* Profiling Compare      */
+
+
+
+#define    PI_RT_INT_PEND_A          0x00000120    /*
+                                                    * RT interrupt
+                                                    * pending
+                                                    */
+
+
+
+#define    PI_RT_INT_PEND_B          0x00000128    /*
+                                                    * RT interrupt
+                                                    * pending
+                                                    */
+
+
+
+#define    PI_PROF_INT_PEND_A        0x00000130    /*
+                                                    * Profiling interrupt
+                                                    * pending
+                                                    */
+
+
+
+#define    PI_PROF_INT_PEND_B        0x00000138    /*
+                                                    * Profiling interrupt
+                                                    * pending
+                                                    */
+
+
+
+#define    PI_RT_INT_EN_A            0x00000140    /* RT Interrupt Enable    */
+
+
+
+#define    PI_RT_INT_EN_B            0x00000148    /* RT Interrupt Enable    */
+
+
+
+#define    PI_PROF_INT_EN_A          0x00000150    /*
+                                                    * Profiling Interrupt
+                                                    * Enable
+                                                    */
+
+
+
+#define    PI_PROF_INT_EN_B          0x00000158    /*
+                                                    * Profiling Interrupt
+                                                    * Enable
+                                                    */
+
+
+
+#define    PI_DEBUG_SEL              0x00000160    /* PI Debug Select        */
+
+
+
+#define    PI_INT_PEND_MOD_ALIAS     0x00000180    /*
+                                                    * Interrupt Pending
+                                                    * Modify
+                                                    */
+
+
+
+#define    PI_PERF_CNTL_A            0x00040200    /*
+                                                    * Performance Counter
+                                                    * Control A
+                                                    */
+
+
+
+#define    PI_PERF_CNTR0_A           0x00040208    /*
+                                                    * Performance Counter
+                                                    * 0 A
+                                                    */
+
+
+
+#define    PI_PERF_CNTR1_A           0x00040210    /*
+                                                    * Performance Counter
+                                                    * 1 A
+                                                    */
+
+
+
+#define    PI_PERF_CNTL_B            0x00050200    /*
+                                                    * Performance Counter
+                                                    * Control B
+                                                    */
+
+
+
+#define    PI_PERF_CNTR0_B           0x00050208    /*
+                                                    * Performance Counter
+                                                    * 0 B
+                                                    */
+
+
+
+#define    PI_PERF_CNTR1_B           0x00050210    /*
+                                                    * Performance Counter
+                                                    * 1 B
+                                                    */
+
+
+
+#define    PI_GFX_PAGE_A             0x00000300    /* Graphics Page          */
+
+
+
+#define    PI_GFX_CREDIT_CNTR_A      0x00000308    /*
+                                                    * Graphics Credit
+                                                    * Counter
+                                                    */
+
+
+
+#define    PI_GFX_BIAS_A             0x00000310    /* TRex+ BIAS             */
+
+
+
+#define    PI_GFX_INT_CNTR_A         0x00000318    /*
+                                                    * Graphics Interrupt
+                                                    * Counter
+                                                    */
+
+
+
+#define    PI_GFX_INT_CMP_A          0x00000320    /*
+                                                    * Graphics Interrupt
+                                                    * Compare
+                                                    */
+
+
+
+#define    PI_GFX_PAGE_B             0x00000328    /* Graphics Page          */
+
+
+
+#define    PI_GFX_CREDIT_CNTR_B      0x00000330    /*
+                                                    * Graphics Credit
+                                                    * Counter
+                                                    */
+
+
+
+#define    PI_GFX_BIAS_B             0x00000338    /* TRex+ BIAS             */
+
+
+
+#define    PI_GFX_INT_CNTR_B         0x00000340    /*
+                                                    * Graphics Interrupt
+                                                    * Counter
+                                                    */
+
+
+
+#define    PI_GFX_INT_CMP_B          0x00000348    /*
+                                                    * Graphics Interrupt
+                                                    * Compare
+                                                    */
+
+
+
+#define    PI_ERR_INT_PEND_WR        0x000003F8    /*
+                                                    * Error Interrupt
+                                                    * Pending (Writable)
+                                                    */
+
+
+
+#define    PI_ERR_INT_PEND           0x00000400    /*
+                                                    * Error Interrupt
+                                                    * Pending
+                                                    */
+
+
+
+#define    PI_ERR_INT_MASK_A         0x00000408    /*
+                                                    * Error Interrupt
+                                                    * Mask CPU_A
+                                                    */
+
+
+
+#define    PI_ERR_INT_MASK_B         0x00000410    /*
+                                                    * Error Interrupt
+                                                    * Mask CPU_B
+                                                    */
+
+
+
+#define    PI_ERR_STACK_ADDR_A       0x00000418    /*
+                                                    * Error Stack Address
+                                                    * Pointer
+                                                    */
+
+
+
+#define    PI_ERR_STACK_ADDR_B       0x00000420    /*
+                                                    * Error Stack Address
+                                                    * Pointer
+                                                    */
+
+
+
+#define    PI_ERR_STACK_SIZE         0x00000428    /* Error Stack Size       */
+
+
+
+#define    PI_ERR_STATUS0_A          0x00000430    /* Error Status 0         */
+
+
+
+#define    PI_ERR_STATUS0_A_CLR      0x00000438    /* Error Status 0         */
+
+
+
+#define    PI_ERR_STATUS1_A          0x00000440    /* Error Status 1         */
+
+
+
+#define    PI_ERR_STATUS1_A_CLR      0x00000448    /* Error Status 1         */
+
+
+
+#define    PI_ERR_STATUS0_B          0x00000450    /* Error Status 0         */
+
+
+
+#define    PI_ERR_STATUS0_B_CLR      0x00000458    /* Error Status 0         */
+
+
+
+#define    PI_ERR_STATUS1_B          0x00000460    /* Error Status 1         */
+
+
+
+#define    PI_ERR_STATUS1_B_CLR      0x00000468    /* Error Status 1         */
+
+
+
+#define    PI_SPOOL_CMP_A            0x00000470    /* Spool Compare          */
+
+
+
+#define    PI_SPOOL_CMP_B            0x00000478    /* Spool Compare          */
+
+
+
+#define    PI_CRB_TIMEOUT_A          0x00000480    /*
+                                                    * CRB entries which
+                                                    * have timed out but
+                                                    * are still valid
+                                                    */
+
+
+
+#define    PI_CRB_TIMEOUT_B          0x00000488    /*
+                                                    * CRB entries which
+                                                    * have timed out but
+                                                    * are still valid
+                                                    */
+
+
+
+#define    PI_SYSAD_ERRCHK_EN        0x00000490    /*
+                                                    * enables
+                                                    * sysad/cmd/state
+                                                    * error checking
+                                                    */
+
+
+
+#define    PI_FORCE_BAD_CHECK_BIT_A  0x00000498    /*
+                                                    * force SysAD Check
+                                                    * Bit error
+                                                    */
+
+
+
+#define    PI_FORCE_BAD_CHECK_BIT_B  0x000004A0    /*
+                                                    * force SysAD Check
+                                                    * Bit error
+                                                    */
+
+
+
+#define    PI_NACK_CNT_A             0x000004A8    /*
+                                                    * consecutive NACK
+                                                    * counter
+                                                    */
+
+
+
+#define    PI_NACK_CNT_B             0x000004B0    /*
+                                                    * consecutive NACK
+                                                    * counter
+                                                    */
+
+
+
+#define    PI_NACK_CMP               0x000004B8    /* NACK count compare     */
+
+
+
+#define    PI_SPOOL_MASK             0x000004C0    /* Spool error mask       */
+
+
+
+#define    PI_SPURIOUS_HDR_0         0x000004C8    /* Spurious Error 0       */
+
+
+
+#define    PI_SPURIOUS_HDR_1         0x000004D0    /* Spurious Error 1       */
+
+
+
+#define    PI_ERR_INJECT             0x000004D8    /*
+                                                    * SysAD bus error
+                                                    * injection
+                                                    */
+
+
+
+
+
+#ifdef _LANGUAGE_C
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This read/write register determines on a               *
+ * bit-per-region basis whether incoming CPU-initiated PIO Read and     *
+ * Write to local PI registers are allowed. If access is allowed, the   *
+ * PI's response to a partial read is a PRPLY message, and the          *
+ * response to a partial write is a PACK message. If access is not      *
+ * allowed, the PI's response to a partial read is a PRERR message,     *
+ * and the response to a partial write is a PWERR message.              *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_cpu_protect_u {
+	bdrkreg_t	pi_cpu_protect_regval;
+	struct  {
+		bdrkreg_t	cp_cpu_protect            :	64;
+	} pi_cpu_protect_fld_s;
+} pi_cpu_protect_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write with a special data pattern allows any CPU to set its       *
+ * region's bit in CPU_PROTECT. This register has data pattern          *
+ * protection.                                                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_prot_ovrrd_u {
+	bdrkreg_t	pi_prot_ovrrd_regval;
+	struct  {
+		bdrkreg_t	po_prot_ovrrd             :	64;
+	} pi_prot_ovrrd_fld_s;
+} pi_prot_ovrrd_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This read/write register determines on a               *
+ * bit-per-region basis whether incoming IO-initiated interrupts are    *
+ * allowed to set bits in INT_PEND0 and INT_PEND1. If access is         *
+ * allowed, the PI's response to a partial read is a PRPLY message,     *
+ * and the response to a partial write is a PACK message. If access     *
+ * is not allowed, the PI's response to a partial read is a PRERR       *
+ * message, and the response to a partial write is a PWERR message.     *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_io_protect_u {
+	bdrkreg_t	pi_io_protect_regval;
+	struct  {
+		bdrkreg_t	ip_io_protect             :	64;
+	} pi_io_protect_fld_s;
+} pi_io_protect_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This read/write register determines on a               *
+ * bit-per-region basis whether read access from a local processor to   *
+ * the region is permissible. For example, setting a bit to 0           *
+ * prevents speculative reads to that non-existent node. If a read      *
+ * request to a non-present region occurs, an ERR response is issued    *
+ * to the TRex+ (no PI error registers are modified). It is up to       *
+ * software to load this register with the proper contents.             *
+ * Region-present checking is only done for coherent read requests -    *
+ * partial reads/writes will be issued to a non-present region. The     *
+ * setting of these bits does not affect a node's access to its         *
+ * CALIAS space.                                                        *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_region_present_u {
+	bdrkreg_t	pi_region_present_regval;
+	struct  {
+		bdrkreg_t	rp_region_present         :	64;
+	} pi_region_present_fld_s;
+} pi_region_present_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A read to the location will allow a CPU to identify itself as       *
+ * either CPU_A or CPU_B, and will indicate whether the CPU is          *
+ * connected to PI 0 or PI 1.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_cpu_num_u {
+	bdrkreg_t	pi_cpu_num_regval;
+	struct  {
+		bdrkreg_t	cn_cpu_num                :	 1;
+                bdrkreg_t       cn_pi_id                  :      1;
+                bdrkreg_t       cn_rsvd                   :     62;
+	} pi_cpu_num_fld_s;
+} pi_cpu_num_u_t;
+
+#else
+
+typedef union pi_cpu_num_u {
+	bdrkreg_t	pi_cpu_num_regval;
+	struct	{
+		bdrkreg_t	cn_rsvd			  :	62;
+		bdrkreg_t	cn_pi_id		  :	 1;
+		bdrkreg_t	cn_cpu_num		  :	 1;
+	} pi_cpu_num_fld_s;
+} pi_cpu_num_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This read/write location determines the size of the    *
+ * Calias Space.                                                        *
+ * This register is not reset by a soft reset.                          *
+ * NOTE: For predictable behavior, all Calias spaces in a system must   *
+ * be set to the same size.                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_calias_size_u {
+	bdrkreg_t	pi_calias_size_regval;
+	struct  {
+		bdrkreg_t	cs_calias_size            :	 4;
+		bdrkreg_t       cs_rsvd                   :     60;
+	} pi_calias_size_fld_s;
+} pi_calias_size_u_t;
+
+#else
+
+typedef union pi_calias_size_u {
+	bdrkreg_t	pi_calias_size_regval;
+	struct	{
+		bdrkreg_t	cs_rsvd			  :	60;
+		bdrkreg_t	cs_calias_size		  :	 4;
+	} pi_calias_size_fld_s;
+} pi_calias_size_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This Read/Write location determines at which value (increment)      *
+ * the CRB Timeout Counters cause a timeout error to occur. See         *
+ * Section 3.4.2.2, &quot;Time-outs in RRB and WRB&quot; in the         *
+ * Processor Interface chapter, volume 1 of this document for more      *
+ * details.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_max_crb_timeout_u {
+	bdrkreg_t	pi_max_crb_timeout_regval;
+	struct  {
+		bdrkreg_t	mct_max_timeout           :	 8;
+		bdrkreg_t       mct_rsvd                  :     56;
+	} pi_max_crb_timeout_fld_s;
+} pi_max_crb_timeout_u_t;
+
+#else
+
+typedef union pi_max_crb_timeout_u {
+	bdrkreg_t	pi_max_crb_timeout_regval;
+	struct	{
+		bdrkreg_t	mct_rsvd		  :	56;
+		bdrkreg_t	mct_max_timeout		  :	 8;
+	} pi_max_crb_timeout_fld_s;
+} pi_max_crb_timeout_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This Read/Write location determines how often a valid CRB's         *
+ * Timeout Counter is incremented. See Section 3.4.2.2,                 *
+ * &quot;Time-outs in RRB and WRB&quot; in the Processor Interface      *
+ * chapter, volume 1 of this document for more details.                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_crb_sfactor_u {
+	bdrkreg_t	pi_crb_sfactor_regval;
+	struct  {
+		bdrkreg_t	cs_sfactor                :	24;
+		bdrkreg_t       cs_rsvd                   :     40;
+	} pi_crb_sfactor_fld_s;
+} pi_crb_sfactor_u_t;
+
+#else
+
+typedef union pi_crb_sfactor_u {
+	bdrkreg_t	pi_crb_sfactor_regval;
+	struct	{
+		bdrkreg_t	cs_rsvd			  :	40;
+		bdrkreg_t	cs_sfactor		  :	24;
+	} pi_crb_sfactor_fld_s;
+} pi_crb_sfactor_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. The PI sets this      *
+ * bit when it sees the first transaction initiated by the associated   *
+ * CPU.                                                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_cpu_present_a_u {
+	bdrkreg_t	pi_cpu_present_a_regval;
+	struct  {
+		bdrkreg_t	cpa_cpu_present           :	 1;
+		bdrkreg_t       cpa_rsvd                  :     63;
+	} pi_cpu_present_a_fld_s;
+} pi_cpu_present_a_u_t;
+
+#else
+
+typedef union pi_cpu_present_a_u {
+	bdrkreg_t	pi_cpu_present_a_regval;
+	struct	{
+		bdrkreg_t	cpa_rsvd		  :	63;
+		bdrkreg_t	cpa_cpu_present		  :	 1;
+	} pi_cpu_present_a_fld_s;
+} pi_cpu_present_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. The PI sets this      *
+ * bit when it sees the first transaction initiated by the associated   *
+ * CPU.                                                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_cpu_present_b_u {
+	bdrkreg_t	pi_cpu_present_b_regval;
+	struct  {
+		bdrkreg_t	cpb_cpu_present           :	 1;
+		bdrkreg_t       cpb_rsvd                  :     63;
+	} pi_cpu_present_b_fld_s;
+} pi_cpu_present_b_u_t;
+
+#else
+
+typedef union pi_cpu_present_b_u {
+	bdrkreg_t	pi_cpu_present_b_regval;
+	struct	{
+		bdrkreg_t	cpb_rsvd		  :	63;
+		bdrkreg_t	cpb_cpu_present		  :	 1;
+	} pi_cpu_present_b_fld_s;
+} pi_cpu_present_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There is one of these registers for each CPU. This     *
+ * Read/Write location determines whether the associated CPU is         *
+ * enabled to issue external requests. When this bit is zero for a      *
+ * processor, the PI ignores SysReq_L from that processor, and so       *
+ * never grants it the bus.                                             *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_cpu_enable_a_u {
+	bdrkreg_t	pi_cpu_enable_a_regval;
+	struct  {
+		bdrkreg_t	cea_cpu_enable            :	 1;
+		bdrkreg_t       cea_rsvd                  :     63;
+	} pi_cpu_enable_a_fld_s;
+} pi_cpu_enable_a_u_t;
+
+#else
+
+typedef union pi_cpu_enable_a_u {
+	bdrkreg_t	pi_cpu_enable_a_regval;
+	struct	{
+		bdrkreg_t	cea_rsvd		  :	63;
+		bdrkreg_t	cea_cpu_enable		  :	 1;
+	} pi_cpu_enable_a_fld_s;
+} pi_cpu_enable_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There is one of these registers for each CPU. This     *
+ * Read/Write location determines whether the associated CPU is         *
+ * enabled to issue external requests. When this bit is zero for a      *
+ * processor, the PI ignores SysReq_L from that processor, and so       *
+ * never grants it the bus.                                             *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_cpu_enable_b_u {
+	bdrkreg_t	pi_cpu_enable_b_regval;
+	struct  {
+		bdrkreg_t	ceb_cpu_enable            :	 1;
+		bdrkreg_t       ceb_rsvd                  :     63;
+	} pi_cpu_enable_b_fld_s;
+} pi_cpu_enable_b_u_t;
+
+#else
+
+typedef union pi_cpu_enable_b_u {
+	bdrkreg_t	pi_cpu_enable_b_regval;
+	struct	{
+		bdrkreg_t	ceb_rsvd		  :	63;
+		bdrkreg_t	ceb_cpu_enable		  :	 1;
+	} pi_cpu_enable_b_fld_s;
+} pi_cpu_enable_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. A write to this       *
+ * location will cause an NMI to be issued to the CPU.                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_nmi_a_u {
+	bdrkreg_t	pi_nmi_a_regval;
+	struct  {
+		bdrkreg_t	na_nmi_cpu                :	64;
+	} pi_nmi_a_fld_s;
+} pi_nmi_a_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. A write to this       *
+ * location will cause an NMI to be issued to the CPU.                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_nmi_b_u {
+	bdrkreg_t	pi_nmi_b_regval;
+	struct  {
+		bdrkreg_t	nb_nmi_cpu                :	64;
+	} pi_nmi_b_fld_s;
+} pi_nmi_b_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register allows a single bit in the INT_PEND0 or    *
+ * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is    *
+ * modified in INT_PEND0, while if 6 is set, a bit is modified in       *
+ * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine    *
+ * which bit in the register is effected. The value of 8 will           *
+ * determine whether the desired bit is set (8=1) or cleared (8=0).     *
+ * This is the only register which is accessible by IO issued PWRI      *
+ * command and is protected through the IO_PROTECT register. If the     *
+ * region bit in the IO_PROTECT is not set then a WERR reply is         *
+ * issued. CPU access is controlled through CPU_PROTECT. The contents   *
+ * of this register are masked with the contents of INT_MASK_A          *
+ * (INT_MASK_B) to determine whether an L2 interrupt is issued to       *
+ * CPU_A (CPU_B).                                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_pend_mod_u {
+	bdrkreg_t	pi_int_pend_mod_regval;
+	struct  {
+		bdrkreg_t	ipm_bit_select            :	 6;
+                bdrkreg_t       ipm_reg_select            :      1;
+                bdrkreg_t       ipm_rsvd_1                :      1;
+                bdrkreg_t       ipm_value                 :      1;
+                bdrkreg_t       ipm_rsvd                  :     55;
+	} pi_int_pend_mod_fld_s;
+} pi_int_pend_mod_u_t;
+
+#else
+
+typedef union pi_int_pend_mod_u {
+	bdrkreg_t	pi_int_pend_mod_regval;
+	struct	{
+		bdrkreg_t	ipm_rsvd		  :	55;
+		bdrkreg_t	ipm_value		  :	 1;
+		bdrkreg_t	ipm_rsvd_1		  :	 1;
+		bdrkreg_t	ipm_reg_select		  :	 1;
+		bdrkreg_t	ipm_bit_select		  :	 6;
+	} pi_int_pend_mod_fld_s;
+} pi_int_pend_mod_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read-only register provides information about interrupts       *
+ * that are currently pending. The interrupts in this register map to   *
+ * interrupt level 2 (L2). The GFX_INT_A/B bits are set by hardware     *
+ * but must be cleared by software.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_pend0_u {
+	bdrkreg_t	pi_int_pend0_regval;
+	struct  {
+		bdrkreg_t	ip_int_pend0_lo           :	 1;
+                bdrkreg_t       ip_gfx_int_a              :      1;
+                bdrkreg_t       ip_gfx_int_b              :      1;
+                bdrkreg_t       ip_page_migration         :      1;
+                bdrkreg_t       ip_uart_ucntrl            :      1;
+                bdrkreg_t       ip_or_cc_pend_a           :      1;
+                bdrkreg_t       ip_or_cc_pend_b           :      1;
+                bdrkreg_t       ip_int_pend0_hi           :     57;
+	} pi_int_pend0_fld_s;
+} pi_int_pend0_u_t;
+
+#else
+
+typedef union pi_int_pend0_u {
+	bdrkreg_t	pi_int_pend0_regval;
+	struct	{
+		bdrkreg_t	ip_int_pend0_hi		  :	57;
+		bdrkreg_t	ip_or_cc_pend_b		  :	 1;
+		bdrkreg_t	ip_or_cc_pend_a		  :	 1;
+		bdrkreg_t	ip_uart_ucntrl		  :	 1;
+		bdrkreg_t	ip_page_migration	  :	 1;
+		bdrkreg_t	ip_gfx_int_b		  :	 1;
+		bdrkreg_t	ip_gfx_int_a		  :	 1;
+		bdrkreg_t	ip_int_pend0_lo		  :	 1;
+	} pi_int_pend0_fld_s;
+} pi_int_pend0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read-only register provides information about interrupts       *
+ * that are currently pending. The interrupts in this register map to   *
+ * interrupt level 3 (L3), unless remapped by the INT_PEND1_REMAP       *
+ * register. The SYS_COR_ERR_A/B, RTC_DROP_OUT, and NACK_INT_A/B bits   *
+ * are set by hardware but must be cleared by software. The             *
+ * SYSTEM_SHUTDOWN, NI_ERROR, LB_ERROR and XB_ERROR bits just reflect   *
+ * the value of other logic, and cannot be changed by PI register       *
+ * writes.                                                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_pend1_u {
+	bdrkreg_t	pi_int_pend1_regval;
+	struct  {
+		bdrkreg_t	ip_int_pend1              :	54;
+                bdrkreg_t       ip_xb_error               :      1;
+                bdrkreg_t       ip_lb_error               :      1;
+                bdrkreg_t       ip_nack_int_a             :      1;
+                bdrkreg_t       ip_nack_int_b             :      1;
+                bdrkreg_t       ip_perf_cntr_oflow        :      1;
+                bdrkreg_t       ip_sys_cor_err_b          :      1;
+                bdrkreg_t       ip_sys_cor_err_a          :      1;
+                bdrkreg_t       ip_md_corr_error          :      1;
+                bdrkreg_t       ip_ni_error               :      1;
+                bdrkreg_t       ip_system_shutdown        :      1;
+	} pi_int_pend1_fld_s;
+} pi_int_pend1_u_t;
+
+#else
+
+typedef union pi_int_pend1_u {
+	bdrkreg_t	pi_int_pend1_regval;
+	struct	{
+		bdrkreg_t	ip_system_shutdown	  :	 1;
+		bdrkreg_t	ip_ni_error		  :	 1;
+		bdrkreg_t	ip_md_corr_error	  :	 1;
+		bdrkreg_t	ip_sys_cor_err_a	  :	 1;
+		bdrkreg_t	ip_sys_cor_err_b	  :	 1;
+		bdrkreg_t	ip_perf_cntr_oflow	  :	 1;
+		bdrkreg_t	ip_nack_int_b		  :	 1;
+		bdrkreg_t	ip_nack_int_a		  :	 1;
+		bdrkreg_t	ip_lb_error		  :	 1;
+		bdrkreg_t	ip_xb_error		  :	 1;
+		bdrkreg_t	ip_int_pend1		  :	54;
+	} pi_int_pend1_fld_s;
+} pi_int_pend1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read/write register masks the contents of INT_PEND0 to         *
+ * determine whether an L2 interrupt (bit 10 of the processor's Cause   *
+ * register) is sent to CPU_A if the same bit in the INT_PEND0          *
+ * register is also set. Only one processor in a Bedrock should         *
+ * enable the PAGE_MIGRATION bit/interrupt.                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_mask0_a_u {
+	bdrkreg_t	pi_int_mask0_a_regval;
+	struct  {
+		bdrkreg_t	ima_int_mask0_lo          :	 1;
+                bdrkreg_t       ima_gfx_int_a             :      1;
+                bdrkreg_t       ima_gfx_int_b             :      1;
+                bdrkreg_t       ima_page_migration        :      1;
+                bdrkreg_t       ima_uart_ucntrl           :      1;
+                bdrkreg_t       ima_or_ccp_mask_a         :      1;
+                bdrkreg_t       ima_or_ccp_mask_b         :      1;
+                bdrkreg_t       ima_int_mask0_hi          :     57;
+	} pi_int_mask0_a_fld_s;
+} pi_int_mask0_a_u_t;
+
+#else
+
+typedef union pi_int_mask0_a_u {
+	bdrkreg_t	pi_int_mask0_a_regval;
+	struct	{
+		bdrkreg_t	ima_int_mask0_hi	  :	57;
+		bdrkreg_t	ima_or_ccp_mask_b	  :	 1;
+		bdrkreg_t	ima_or_ccp_mask_a	  :	 1;
+		bdrkreg_t	ima_uart_ucntrl		  :	 1;
+		bdrkreg_t	ima_page_migration	  :	 1;
+		bdrkreg_t	ima_gfx_int_b		  :	 1;
+		bdrkreg_t	ima_gfx_int_a		  :	 1;
+		bdrkreg_t	ima_int_mask0_lo	  :	 1;
+	} pi_int_mask0_a_fld_s;
+} pi_int_mask0_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read/write register masks the contents of INT_PEND1 to         *
+ * determine whether an interrupt should be sent. Bits 63:32 always     *
+ * generate an L3 interrupt (bit 11 of the processor's Cause            *
+ * register) is sent to CPU_A if the same bit in the INT_PEND1          *
+ * register is set. Bits 31:0 can generate either an L3 or L2           *
+ * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only      *
+ * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR,     *
+ * XB_ERROR and MD_CORR_ERROR bits.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_int_mask1_a_u {
+	bdrkreg_t	pi_int_mask1_a_regval;
+	struct  {
+		bdrkreg_t	ima_int_mask1             :	64;
+	} pi_int_mask1_a_fld_s;
+} pi_int_mask1_a_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read/write register masks the contents of INT_PEND0 to         *
+ * determine whether an L2 interrupt (bit 10 of the processor's Cause   *
+ * register) is sent to CPU_B if the same bit in the INT_PEND0          *
+ * register is also set. Only one processor in a Bedrock should         *
+ * enable the PAGE_MIGRATION bit/interrupt.                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_mask0_b_u {
+	bdrkreg_t	pi_int_mask0_b_regval;
+	struct  {
+		bdrkreg_t	imb_int_mask0_lo          :	 1;
+                bdrkreg_t       imb_gfx_int_a             :      1;
+                bdrkreg_t       imb_gfx_int_b             :      1;
+                bdrkreg_t       imb_page_migration        :      1;
+                bdrkreg_t       imb_uart_ucntrl           :      1;
+                bdrkreg_t       imb_or_ccp_mask_a         :      1;
+                bdrkreg_t       imb_or_ccp_mask_b         :      1;
+                bdrkreg_t       imb_int_mask0_hi          :     57;
+	} pi_int_mask0_b_fld_s;
+} pi_int_mask0_b_u_t;
+
+#else
+
+typedef union pi_int_mask0_b_u {
+	bdrkreg_t	pi_int_mask0_b_regval;
+	struct	{
+		bdrkreg_t	imb_int_mask0_hi	  :	57;
+		bdrkreg_t	imb_or_ccp_mask_b	  :	 1;
+		bdrkreg_t	imb_or_ccp_mask_a	  :	 1;
+		bdrkreg_t	imb_uart_ucntrl		  :	 1;
+		bdrkreg_t	imb_page_migration	  :	 1;
+		bdrkreg_t	imb_gfx_int_b		  :	 1;
+		bdrkreg_t	imb_gfx_int_a		  :	 1;
+		bdrkreg_t	imb_int_mask0_lo	  :	 1;
+	} pi_int_mask0_b_fld_s;
+} pi_int_mask0_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read/write register masks the contents of INT_PEND1 to         *
+ * determine whether an interrupt should be sent. Bits 63:32 always     *
+ * generate an L3 interrupt (bit 11 of the processor's Cause            *
+ * register) is sent to CPU_B if the same bit in the INT_PEND1          *
+ * register is set. Bits 31:0 can generate either an L3 or L2           *
+ * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only      *
+ * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR,     *
+ * XB_ERROR and MD_CORR_ERROR bits.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_int_mask1_b_u {
+	bdrkreg_t	pi_int_mask1_b_regval;
+	struct  {
+		bdrkreg_t	imb_int_mask1             :	64;
+	} pi_int_mask1_b_fld_s;
+} pi_int_mask1_b_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. These registers do    *
+ * not have access protection. A store to this location by a CPU will   *
+ * cause the bit corresponding to the source's region to be set in      *
+ * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B)   *
+ * determines on a bit-per-region basis whether a CPU-to-CPU            *
+ * interrupt is pending CPU_A (or CPU_B).                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_cc_pend_set_a_u {
+	bdrkreg_t	pi_cc_pend_set_a_regval;
+	struct  {
+		bdrkreg_t	cpsa_cc_pend              :	64;
+	} pi_cc_pend_set_a_fld_s;
+} pi_cc_pend_set_a_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. These registers do    *
+ * not have access protection. A store to this location by a CPU will   *
+ * cause the bit corresponding to the source's region to be set in      *
+ * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B)   *
+ * determines on a bit-per-region basis whether a CPU-to-CPU            *
+ * interrupt is pending CPU_A (or CPU_B).                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_cc_pend_set_b_u {
+	bdrkreg_t	pi_cc_pend_set_b_regval;
+	struct  {
+		bdrkreg_t	cpsb_cc_pend              :	64;
+	} pi_cc_pend_set_b_fld_s;
+} pi_cc_pend_set_b_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Reading this          *
+ * location will return the contents of CC_PEND_A (or CC_PEND_B).       *
+ * Writing this location will clear the bits corresponding to which     *
+ * data bits are driven high during the store; therefore, storing all   *
+ * ones would clear all bits.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_cc_pend_clr_a_u {
+	bdrkreg_t	pi_cc_pend_clr_a_regval;
+	struct  {
+		bdrkreg_t	cpca_cc_pend              :	64;
+	} pi_cc_pend_clr_a_fld_s;
+} pi_cc_pend_clr_a_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Reading this          *
+ * location will return the contents of CC_PEND_A (or CC_PEND_B).       *
+ * Writing this location will clear the bits corresponding to which     *
+ * data bits are driven high during the store; therefore, storing all   *
+ * ones would clear all bits.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_cc_pend_clr_b_u {
+	bdrkreg_t	pi_cc_pend_clr_b_regval;
+	struct  {
+		bdrkreg_t	cpcb_cc_pend              :	64;
+	} pi_cc_pend_clr_b_fld_s;
+} pi_cc_pend_clr_b_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read/write register masks the contents of both CC_PEND_A and   *
+ * CC_PEND_B.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+typedef union pi_cc_mask_u {
+	bdrkreg_t	pi_cc_mask_regval;
+	struct  {
+		bdrkreg_t	cm_cc_mask                :	64;
+	} pi_cc_mask_fld_s;
+} pi_cc_mask_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This read/write register redirects INT_PEND1[31:0] from L3 to L2    *
+ * interrupt level.Bit 4 in this register is used to enable error       *
+ * interrupt forwarding to the II. When this bit is set, if any of      *
+ * the three memory interrupts (correctable error, uncorrectable        *
+ * error, or page migration), or the NI, LB or XB error interrupts      *
+ * are set, the PI_II_ERROR_INT wire will be asserted. When this wire   *
+ * is asserted, the II will send an interrupt to the node specified     *
+ * in its IIDSR (Interrupt Destination Register). This allows these     *
+ * interrupts to be forwarded to another node.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_pend1_remap_u {
+	bdrkreg_t	pi_int_pend1_remap_regval;
+	struct  {
+		bdrkreg_t	ipr_remap_0               :	 1;
+                bdrkreg_t       ipr_remap_1               :      1;
+                bdrkreg_t       ipr_remap_2               :      1;
+                bdrkreg_t       ipr_remap_3               :      1;
+                bdrkreg_t       ipr_error_forward         :      1;
+                bdrkreg_t       ipr_reserved              :     59;
+	} pi_int_pend1_remap_fld_s;
+} pi_int_pend1_remap_u_t;
+
+#else
+
+typedef union pi_int_pend1_remap_u {
+	bdrkreg_t	pi_int_pend1_remap_regval;
+	struct	{
+		bdrkreg_t	ipr_reserved		  :	59;
+		bdrkreg_t	ipr_error_forward	  :	 1;
+		bdrkreg_t	ipr_remap_3		  :	 1;
+		bdrkreg_t	ipr_remap_2		  :	 1;
+		bdrkreg_t	ipr_remap_1		  :	 1;
+		bdrkreg_t	ipr_remap_0		  :	 1;
+	} pi_int_pend1_remap_fld_s;
+} pi_int_pend1_remap_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. When the real time    *
+ * counter (RT_Counter) is equal to the value in this register, the     *
+ * RT_INT_PEND register is set, which causes a Level-4 interrupt to     *
+ * be sent to the processor.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_compare_a_u {
+	bdrkreg_t	pi_rt_compare_a_regval;
+	struct  {
+		bdrkreg_t	rca_rt_compare            :	55;
+		bdrkreg_t       rca_rsvd                  :      9;
+	} pi_rt_compare_a_fld_s;
+} pi_rt_compare_a_u_t;
+
+#else
+
+typedef union pi_rt_compare_a_u {
+        bdrkreg_t       pi_rt_compare_a_regval;
+        struct  {
+                bdrkreg_t       rca_rsvd                  :      9;
+                bdrkreg_t       rca_rt_compare            :     55;
+        } pi_rt_compare_a_fld_s;
+} pi_rt_compare_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. When the real time    *
+ * counter (RT_Counter) is equal to the value in this register, the     *
+ * RT_INT_PEND register is set, which causes a Level-4 interrupt to     *
+ * be sent to the processor.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_compare_b_u {
+	bdrkreg_t	pi_rt_compare_b_regval;
+	struct  {
+		bdrkreg_t	rcb_rt_compare            :	55;
+		bdrkreg_t       rcb_rsvd                  :      9;
+	} pi_rt_compare_b_fld_s;
+} pi_rt_compare_b_u_t;
+
+#else
+
+typedef union pi_rt_compare_b_u {
+	bdrkreg_t	pi_rt_compare_b_regval;
+	struct	{
+		bdrkreg_t	rcb_rsvd		  :	 9;
+		bdrkreg_t	rcb_rt_compare		  :	55;
+	} pi_rt_compare_b_fld_s;
+} pi_rt_compare_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  When the least significant 32 bits of the real time counter         *
+ * (RT_Counter) are equal to the value in this register, the            *
+ * PROF_INT_PEND_A and PROF_INT_PEND_B registers are set to 0x1.        *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_profile_compare_u {
+	bdrkreg_t	pi_profile_compare_regval;
+	struct  {
+		bdrkreg_t	pc_profile_compare        :	32;
+		bdrkreg_t       pc_rsvd                   :     32;
+	} pi_profile_compare_fld_s;
+} pi_profile_compare_u_t;
+
+#else
+
+typedef union pi_profile_compare_u {
+	bdrkreg_t	pi_profile_compare_regval;
+	struct	{
+		bdrkreg_t	pc_rsvd			  :	32;
+		bdrkreg_t	pc_profile_compare	  :	32;
+	} pi_profile_compare_fld_s;
+} pi_profile_compare_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. If the bit in the     *
+ * corresponding RT_INT_EN_A/B register is set, the processor's level   *
+ * 5 interrupt is set to the value of the RTC_INT_PEND bit in this      *
+ * register. Storing any value to this location will clear the          *
+ * RTC_INT_PEND bit in the register.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_int_pend_a_u {
+	bdrkreg_t	pi_rt_int_pend_a_regval;
+	struct  {
+		bdrkreg_t	ripa_rtc_int_pend         :	 1;
+		bdrkreg_t       ripa_rsvd                 :     63;
+	} pi_rt_int_pend_a_fld_s;
+} pi_rt_int_pend_a_u_t;
+
+#else
+
+typedef union pi_rt_int_pend_a_u {
+	bdrkreg_t	pi_rt_int_pend_a_regval;
+	struct	{
+		bdrkreg_t	ripa_rsvd		  :	63;
+		bdrkreg_t	ripa_rtc_int_pend	  :	 1;
+	} pi_rt_int_pend_a_fld_s;
+} pi_rt_int_pend_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. If the bit in the     *
+ * corresponding RT_INT_EN_A/B register is set, the processor's level   *
+ * 5 interrupt is set to the value of the RTC_INT_PEND bit in this      *
+ * register. Storing any value to this location will clear the          *
+ * RTC_INT_PEND bit in the register.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_int_pend_b_u {
+	bdrkreg_t	pi_rt_int_pend_b_regval;
+	struct  {
+		bdrkreg_t	ripb_rtc_int_pend         :	 1;
+		bdrkreg_t       ripb_rsvd                 :     63;
+	} pi_rt_int_pend_b_fld_s;
+} pi_rt_int_pend_b_u_t;
+
+#else
+
+typedef union pi_rt_int_pend_b_u {
+	bdrkreg_t	pi_rt_int_pend_b_regval;
+	struct	{
+		bdrkreg_t	ripb_rsvd		  :	63;
+		bdrkreg_t	ripb_rtc_int_pend	  :	 1;
+	} pi_rt_int_pend_b_fld_s;
+} pi_rt_int_pend_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Both registers are    *
+ * set when the PROFILE_COMPARE register is equal to bits [31:0] of     *
+ * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B      *
+ * register is set, the processor's level 5 interrupt is set to the     *
+ * value of the PROF_INT_PEND bit in this register. Storing any value   *
+ * to this location will clear the PROF_INT_PEND bit in the register.   *
+ * The reason for having A and B versions of this register is that      *
+ * they need to be cleared independently.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_prof_int_pend_a_u {
+	bdrkreg_t	pi_prof_int_pend_a_regval;
+	struct  {
+		bdrkreg_t	pipa_prof_int_pend        :	 1;
+		bdrkreg_t       pipa_rsvd                 :     63;
+	} pi_prof_int_pend_a_fld_s;
+} pi_prof_int_pend_a_u_t;
+
+#else
+
+typedef union pi_prof_int_pend_a_u {
+	bdrkreg_t	pi_prof_int_pend_a_regval;
+	struct	{
+		bdrkreg_t	pipa_rsvd		  :	63;
+		bdrkreg_t	pipa_prof_int_pend	  :	 1;
+	} pi_prof_int_pend_a_fld_s;
+} pi_prof_int_pend_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Both registers are    *
+ * set when the PROFILE_COMPARE register is equal to bits [31:0] of     *
+ * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B      *
+ * register is set, the processor's level 5 interrupt is set to the     *
+ * value of the PROF_INT_PEND bit in this register. Storing any value   *
+ * to this location will clear the PROF_INT_PEND bit in the register.   *
+ * The reason for having A and B versions of this register is that      *
+ * they need to be cleared independently.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_prof_int_pend_b_u {
+	bdrkreg_t	pi_prof_int_pend_b_regval;
+	struct  {
+		bdrkreg_t	pipb_prof_int_pend        :	 1;
+		bdrkreg_t       pipb_rsvd                 :     63;
+	} pi_prof_int_pend_b_fld_s;
+} pi_prof_int_pend_b_u_t;
+
+#else
+
+typedef union pi_prof_int_pend_b_u {
+	bdrkreg_t	pi_prof_int_pend_b_regval;
+	struct	{
+		bdrkreg_t	pipb_rsvd		  :	63;
+		bdrkreg_t	pipb_prof_int_pend	  :	 1;
+	} pi_prof_int_pend_b_fld_s;
+} pi_prof_int_pend_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Enables RTC           *
+ * interrupt to the associated CPU.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_int_en_a_u {
+	bdrkreg_t	pi_rt_int_en_a_regval;
+	struct  {
+		bdrkreg_t	riea_rtc_int_en           :	 1;
+		bdrkreg_t       riea_rsvd                 :     63;
+	} pi_rt_int_en_a_fld_s;
+} pi_rt_int_en_a_u_t;
+
+#else
+
+typedef union pi_rt_int_en_a_u {
+        bdrkreg_t       pi_rt_int_en_a_regval;
+        struct  {
+                bdrkreg_t       riea_rsvd                 :     63;
+                bdrkreg_t       riea_rtc_int_en           :      1;
+        } pi_rt_int_en_a_fld_s;
+} pi_rt_int_en_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Enables RTC           *
+ * interrupt to the associated CPU.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_int_en_b_u {
+	bdrkreg_t	pi_rt_int_en_b_regval;
+	struct  {
+		bdrkreg_t	rieb_rtc_int_en           :	 1;
+		bdrkreg_t       rieb_rsvd                 :     63;
+	} pi_rt_int_en_b_fld_s;
+} pi_rt_int_en_b_u_t;
+
+#else
+
+typedef union pi_rt_int_en_b_u {
+        bdrkreg_t       pi_rt_int_en_b_regval;
+        struct  {
+                bdrkreg_t       rieb_rsvd                 :     63;
+                bdrkreg_t       rieb_rtc_int_en           :      1;
+        } pi_rt_int_en_b_fld_s;
+} pi_rt_int_en_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Enables profiling     *
+ * interrupt to the associated CPU.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_prof_int_en_a_u {
+	bdrkreg_t	pi_prof_int_en_a_regval;
+	struct  {
+		bdrkreg_t	piea_prof_int_en          :	 1;
+		bdrkreg_t       piea_rsvd                 :     63;
+	} pi_prof_int_en_a_fld_s;
+} pi_prof_int_en_a_u_t;
+
+#else
+
+typedef union pi_prof_int_en_a_u {
+	bdrkreg_t	pi_prof_int_en_a_regval;
+	struct	{
+		bdrkreg_t	piea_rsvd		  :	63;
+		bdrkreg_t	piea_prof_int_en	  :	 1;
+	} pi_prof_int_en_a_fld_s;
+} pi_prof_int_en_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. Enables profiling     *
+ * interrupt to the associated CPU.                                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_prof_int_en_b_u {
+	bdrkreg_t	pi_prof_int_en_b_regval;
+	struct  {
+		bdrkreg_t	pieb_prof_int_en          :	 1;
+		bdrkreg_t       pieb_rsvd                 :     63;
+	} pi_prof_int_en_b_fld_s;
+} pi_prof_int_en_b_u_t;
+
+#else
+
+typedef union pi_prof_int_en_b_u {
+	bdrkreg_t	pi_prof_int_en_b_regval;
+	struct	{
+		bdrkreg_t	pieb_rsvd		  :	63;
+		bdrkreg_t	pieb_prof_int_en	  :	 1;
+	} pi_prof_int_en_b_fld_s;
+} pi_prof_int_en_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls operation of the debug data from the PI,     *
+ * along with Debug_Sel[2:0] from the Debug module. For some values     *
+ * of Debug_Sel[2:0], the B_SEL bit selects whether the debug bits      *
+ * are looking at the processor A or processor B logic. The remaining   *
+ * bits select which signal(s) are ORed to create DebugData bits 31     *
+ * and 30 for all of the PI debug selections.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_debug_sel_u {
+	bdrkreg_t	pi_debug_sel_regval;
+	struct  {
+		bdrkreg_t	ds_low_t5cc_a             :	 1;
+                bdrkreg_t       ds_low_t5cc_b             :      1;
+                bdrkreg_t       ds_low_totcc_a            :      1;
+                bdrkreg_t       ds_low_totcc_b            :      1;
+                bdrkreg_t       ds_low_reqcc_a            :      1;
+                bdrkreg_t       ds_low_reqcc_b            :      1;
+                bdrkreg_t       ds_low_rplcc_a            :      1;
+                bdrkreg_t       ds_low_rplcc_b            :      1;
+                bdrkreg_t       ds_low_intcc              :      1;
+                bdrkreg_t       ds_low_perf_inc_a_0       :      1;
+                bdrkreg_t       ds_low_perf_inc_a_1       :      1;
+                bdrkreg_t       ds_low_perf_inc_b_0       :      1;
+                bdrkreg_t       ds_low_perf_inc_b_1       :      1;
+                bdrkreg_t       ds_high_t5cc_a            :      1;
+                bdrkreg_t       ds_high_t5cc_b            :      1;
+                bdrkreg_t       ds_high_totcc_a           :      1;
+                bdrkreg_t       ds_high_totcc_b           :      1;
+                bdrkreg_t       ds_high_reqcc_a           :      1;
+                bdrkreg_t       ds_high_reqcc_b           :      1;
+                bdrkreg_t       ds_high_rplcc_a           :      1;
+                bdrkreg_t       ds_high_rplcc_b           :      1;
+                bdrkreg_t       ds_high_intcc             :      1;
+                bdrkreg_t       ds_high_perf_inc_a_0      :      1;
+                bdrkreg_t       ds_high_perf_inc_a_1      :      1;
+                bdrkreg_t       ds_high_perf_inc_b_0      :      1;
+                bdrkreg_t       ds_high_perf_inc_b_1      :      1;
+                bdrkreg_t       ds_b_sel                  :      1;
+                bdrkreg_t       ds_rsvd                   :     37;
+	} pi_debug_sel_fld_s;
+} pi_debug_sel_u_t;
+
+#else
+
+typedef union pi_debug_sel_u {
+	bdrkreg_t	pi_debug_sel_regval;
+	struct	{
+		bdrkreg_t	ds_rsvd			  :	37;
+		bdrkreg_t	ds_b_sel		  :	 1;
+		bdrkreg_t	ds_high_perf_inc_b_1	  :	 1;
+		bdrkreg_t	ds_high_perf_inc_b_0	  :	 1;
+		bdrkreg_t	ds_high_perf_inc_a_1	  :	 1;
+		bdrkreg_t	ds_high_perf_inc_a_0	  :	 1;
+		bdrkreg_t	ds_high_intcc		  :	 1;
+		bdrkreg_t	ds_high_rplcc_b		  :	 1;
+		bdrkreg_t	ds_high_rplcc_a		  :	 1;
+		bdrkreg_t	ds_high_reqcc_b		  :	 1;
+		bdrkreg_t	ds_high_reqcc_a		  :	 1;
+		bdrkreg_t	ds_high_totcc_b		  :	 1;
+		bdrkreg_t	ds_high_totcc_a		  :	 1;
+		bdrkreg_t	ds_high_t5cc_b		  :	 1;
+		bdrkreg_t	ds_high_t5cc_a		  :	 1;
+		bdrkreg_t	ds_low_perf_inc_b_1	  :	 1;
+		bdrkreg_t	ds_low_perf_inc_b_0	  :	 1;
+		bdrkreg_t	ds_low_perf_inc_a_1	  :	 1;
+		bdrkreg_t	ds_low_perf_inc_a_0	  :	 1;
+		bdrkreg_t	ds_low_intcc		  :	 1;
+		bdrkreg_t	ds_low_rplcc_b		  :	 1;
+		bdrkreg_t	ds_low_rplcc_a		  :	 1;
+		bdrkreg_t	ds_low_reqcc_b		  :	 1;
+		bdrkreg_t	ds_low_reqcc_a		  :	 1;
+		bdrkreg_t	ds_low_totcc_b		  :	 1;
+		bdrkreg_t	ds_low_totcc_a		  :	 1;
+		bdrkreg_t	ds_low_t5cc_b		  :	 1;
+		bdrkreg_t	ds_low_t5cc_a		  :	 1;
+	} pi_debug_sel_fld_s;
+} pi_debug_sel_u_t;
+
+#endif
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register allows a single bit in the INT_PEND0 or    *
+ * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is    *
+ * modified in INT_PEND0, while if 6 is set, a bit is modified in       *
+ * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine    *
+ * which bit in the register is effected. The value of 8 will           *
+ * determine whether the desired bit is set (8=1) or cleared (8=0).     *
+ * This is the only register which is accessible by IO issued PWRI      *
+ * command and is protected through the IO_PROTECT register. If the     *
+ * region bit in the IO_PROTECT is not set then a WERR reply is         *
+ * issued. CPU access is controlled through CPU_PROTECT. The contents   *
+ * of this register are masked with the contents of INT_MASK_A          *
+ * (INT_MASK_B) to determine whether an L2 interrupt is issued to       *
+ * CPU_A (CPU_B).                                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_int_pend_mod_alias_u {
+	bdrkreg_t	pi_int_pend_mod_alias_regval;
+	struct  {
+		bdrkreg_t	ipma_bit_select           :	 6;
+                bdrkreg_t       ipma_reg_select           :      1;
+                bdrkreg_t       ipma_rsvd_1               :      1;
+                bdrkreg_t       ipma_value                :      1;
+                bdrkreg_t       ipma_rsvd                 :     55;
+	} pi_int_pend_mod_alias_fld_s;
+} pi_int_pend_mod_alias_u_t;
+
+#else
+
+typedef union pi_int_pend_mod_alias_u {
+	bdrkreg_t	pi_int_pend_mod_alias_regval;
+	struct	{
+		bdrkreg_t	ipma_rsvd		  :	55;
+		bdrkreg_t	ipma_value		  :	 1;
+		bdrkreg_t	ipma_rsvd_1		  :	 1;
+		bdrkreg_t	ipma_reg_select		  :	 1;
+		bdrkreg_t	ipma_bit_select		  :	 6;
+	} pi_int_pend_mod_alias_fld_s;
+} pi_int_pend_mod_alias_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. This register         *
+ * specifies the value of the Graphics Page. Uncached writes into the   *
+ * Graphics Page (with uncached attribute of IO) are done with GFXWS    *
+ * commands rather than the normal PWRI commands. GFXWS commands are    *
+ * tracked with the graphics credit counters.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_page_a_u {
+	bdrkreg_t	pi_gfx_page_a_regval;
+	struct  {
+		bdrkreg_t	gpa_rsvd_1                :	17;
+                bdrkreg_t       gpa_gfx_page_addr         :     23;
+                bdrkreg_t       gpa_en_gfx_page           :      1;
+                bdrkreg_t       gpa_rsvd                  :     23;
+	} pi_gfx_page_a_fld_s;
+} pi_gfx_page_a_u_t;
+
+#else
+
+typedef union pi_gfx_page_a_u {
+	bdrkreg_t	pi_gfx_page_a_regval;
+	struct	{
+		bdrkreg_t	gpa_rsvd		  :	23;
+		bdrkreg_t	gpa_en_gfx_page		  :	 1;
+		bdrkreg_t	gpa_gfx_page_addr	  :	23;
+		bdrkreg_t	gpa_rsvd_1		  :	17;
+	} pi_gfx_page_a_fld_s;
+} pi_gfx_page_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. This register         *
+ * counts graphics credits. This counter is decremented for each        *
+ * doubleword sent to graphics with GFXWS or GFXWL commands. It is      *
+ * incremented for each doubleword acknowledge from graphics. When      *
+ * this counter has a smaller value than the GFX_BIAS register,         *
+ * SysWrRdy_L is deasserted, an interrupt is sent to the processor,     *
+ * and SysWrRdy_L is allowed to be asserted again. This is the basic    *
+ * mechanism for flow-controlling graphics writes.                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_credit_cntr_a_u {
+	bdrkreg_t	pi_gfx_credit_cntr_a_regval;
+	struct  {
+		bdrkreg_t	gcca_gfx_credit_cntr      :	12;
+		bdrkreg_t       gcca_rsvd                 :     52;
+	} pi_gfx_credit_cntr_a_fld_s;
+} pi_gfx_credit_cntr_a_u_t;
+
+#else
+
+typedef union pi_gfx_credit_cntr_a_u {
+	bdrkreg_t	pi_gfx_credit_cntr_a_regval;
+	struct	{
+		bdrkreg_t	gcca_rsvd		  :	52;
+		bdrkreg_t	gcca_gfx_credit_cntr	  :	12;
+	} pi_gfx_credit_cntr_a_fld_s;
+} pi_gfx_credit_cntr_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. When the graphics     *
+ * credit counter is less than or equal to this value, a flow control   *
+ * interrupt is sent.                                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_bias_a_u {
+	bdrkreg_t	pi_gfx_bias_a_regval;
+	struct  {
+		bdrkreg_t	gba_gfx_bias              :	12;
+		bdrkreg_t       gba_rsvd                  :     52;
+	} pi_gfx_bias_a_fld_s;
+} pi_gfx_bias_a_u_t;
+
+#else
+
+typedef union pi_gfx_bias_a_u {
+	bdrkreg_t	pi_gfx_bias_a_regval;
+	struct	{
+		bdrkreg_t	gba_rsvd		  :	52;
+		bdrkreg_t	gba_gfx_bias		  :	12;
+	} pi_gfx_bias_a_fld_s;
+} pi_gfx_bias_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There is one of these registers for each CPU. When     *
+ * this counter reaches the value of the GFX_INT_CMP register, an       *
+ * interrupt is sent to the associated processor. At each clock         *
+ * cycle, the value in this register can be changed by any one of the   *
+ * following actions:                                                   *
+ * - Written by software.                                               *
+ * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or   *
+ * soft reset occurs, thus preventing an additional interrupt.          *
+ * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value.       *
+ * - Incremented (by one at each clock) for each clock that the         *
+ * GFX_CREDIT_CNTR is less than or equal to zero.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_int_cntr_a_u {
+	bdrkreg_t	pi_gfx_int_cntr_a_regval;
+	struct  {
+		bdrkreg_t	gica_gfx_int_cntr         :	26;
+		bdrkreg_t       gica_rsvd                 :     38;
+	} pi_gfx_int_cntr_a_fld_s;
+} pi_gfx_int_cntr_a_u_t;
+
+#else
+
+typedef union pi_gfx_int_cntr_a_u {
+	bdrkreg_t	pi_gfx_int_cntr_a_regval;
+	struct	{
+		bdrkreg_t	gica_rsvd		  :	38;
+		bdrkreg_t	gica_gfx_int_cntr	  :	26;
+	} pi_gfx_int_cntr_a_fld_s;
+} pi_gfx_int_cntr_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. The value in this     *
+ * register is loaded into the GFX_INT_CNTR register when an            *
+ * interrupt, NMI, or soft reset is sent to the processor. The value    *
+ * in this register is compared to the value of GFX_INT_CNTR and an     *
+ * interrupt is sent when they become equal.                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LINUX
+
+typedef union pi_gfx_int_cmp_a_u {
+	bdrkreg_t	pi_gfx_int_cmp_a_regval;
+	struct  {
+		bdrkreg_t	gica_gfx_int_cmp          :	26;
+		bdrkreg_t       gica_rsvd                 :     38;
+	} pi_gfx_int_cmp_a_fld_s;
+} pi_gfx_int_cmp_a_u_t;
+
+#else
+
+typedef union pi_gfx_int_cmp_a_u {
+	bdrkreg_t	pi_gfx_int_cmp_a_regval;
+	struct	{
+		bdrkreg_t	gica_rsvd		  :	38;
+		bdrkreg_t	gica_gfx_int_cmp	  :	26;
+	} pi_gfx_int_cmp_a_fld_s;
+} pi_gfx_int_cmp_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. This register         *
+ * specifies the value of the Graphics Page. Uncached writes into the   *
+ * Graphics Page (with uncached attribute of IO) are done with GFXWS    *
+ * commands rather than the normal PWRI commands. GFXWS commands are    *
+ * tracked with the graphics credit counters.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_page_b_u {
+	bdrkreg_t	pi_gfx_page_b_regval;
+	struct  {
+		bdrkreg_t	gpb_rsvd_1                :	17;
+                bdrkreg_t       gpb_gfx_page_addr         :     23;
+                bdrkreg_t       gpb_en_gfx_page           :      1;
+                bdrkreg_t       gpb_rsvd                  :     23;
+	} pi_gfx_page_b_fld_s;
+} pi_gfx_page_b_u_t;
+
+#else
+
+typedef union pi_gfx_page_b_u {
+	bdrkreg_t	pi_gfx_page_b_regval;
+	struct	{
+		bdrkreg_t	gpb_rsvd		  :	23;
+		bdrkreg_t	gpb_en_gfx_page		  :	 1;
+		bdrkreg_t	gpb_gfx_page_addr	  :	23;
+		bdrkreg_t	gpb_rsvd_1		  :	17;
+	} pi_gfx_page_b_fld_s;
+} pi_gfx_page_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. This register         *
+ * counts graphics credits. This counter is decremented for each        *
+ * doubleword sent to graphics with GFXWS or GFXWL commands. It is      *
+ * incremented for each doubleword acknowledge from graphics. When      *
+ * this counter has a smaller value than the GFX_BIAS register,         *
+ * SysWrRdy_L is deasserted, an interrupt is sent to the processor,     *
+ * and SysWrRdy_L is allowed to be asserted again. This is the basic    *
+ * mechanism for flow-controlling graphics writes.                      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_credit_cntr_b_u {
+	bdrkreg_t	pi_gfx_credit_cntr_b_regval;
+	struct  {
+		bdrkreg_t	gccb_gfx_credit_cntr      :	12;
+		bdrkreg_t       gccb_rsvd                 :     52;
+	} pi_gfx_credit_cntr_b_fld_s;
+} pi_gfx_credit_cntr_b_u_t;
+
+#else
+
+typedef union pi_gfx_credit_cntr_b_u {
+	bdrkreg_t	pi_gfx_credit_cntr_b_regval;
+	struct	{
+		bdrkreg_t	gccb_rsvd		  :	52;
+		bdrkreg_t	gccb_gfx_credit_cntr	  :	12;
+	} pi_gfx_credit_cntr_b_fld_s;
+} pi_gfx_credit_cntr_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. When the graphics     *
+ * credit counter is less than or equal to this value, a flow control   *
+ * interrupt is sent.                                                   *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_bias_b_u {
+	bdrkreg_t	pi_gfx_bias_b_regval;
+	struct  {
+		bdrkreg_t	gbb_gfx_bias              :	12;
+		bdrkreg_t       gbb_rsvd                  :     52;
+	} pi_gfx_bias_b_fld_s;
+} pi_gfx_bias_b_u_t;
+
+#else
+
+typedef union pi_gfx_bias_b_u {
+	bdrkreg_t	pi_gfx_bias_b_regval;
+	struct	{
+		bdrkreg_t	gbb_rsvd		  :	52;
+		bdrkreg_t	gbb_gfx_bias		  :	12;
+	} pi_gfx_bias_b_fld_s;
+} pi_gfx_bias_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There is one of these registers for each CPU. When     *
+ * this counter reaches the value of the GFX_INT_CMP register, an       *
+ * interrupt is sent to the associated processor. At each clock         *
+ * cycle, the value in this register can be changed by any one of the   *
+ * following actions:                                                   *
+ * - Written by software.                                               *
+ * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or   *
+ * soft reset occurs, thus preventing an additional interrupt.          *
+ * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value.       *
+ * - Incremented (by one at each clock) for each clock that the         *
+ * GFX_CREDIT_CNTR is less than or equal to zero.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_int_cntr_b_u {
+	bdrkreg_t	pi_gfx_int_cntr_b_regval;
+	struct  {
+		bdrkreg_t	gicb_gfx_int_cntr         :	26;
+		bdrkreg_t       gicb_rsvd                 :     38;
+	} pi_gfx_int_cntr_b_fld_s;
+} pi_gfx_int_cntr_b_u_t;
+
+#else
+
+typedef union pi_gfx_int_cntr_b_u {
+	bdrkreg_t	pi_gfx_int_cntr_b_regval;
+	struct	{
+		bdrkreg_t	gicb_rsvd		  :	38;
+		bdrkreg_t	gicb_gfx_int_cntr	  :	26;
+	} pi_gfx_int_cntr_b_fld_s;
+} pi_gfx_int_cntr_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. The value in this     *
+ * register is loaded into the GFX_INT_CNTR register when an            *
+ * interrupt, NMI, or soft reset is sent to the processor. The value    *
+ * in this register is compared to the value of GFX_INT_CNTR and an     *
+ * interrupt is sent when they become equal.                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_int_cmp_b_u {
+	bdrkreg_t	pi_gfx_int_cmp_b_regval;
+	struct  {
+		bdrkreg_t	gicb_gfx_int_cmp          :	26;
+		bdrkreg_t       gicb_rsvd                 :     38;
+	} pi_gfx_int_cmp_b_fld_s;
+} pi_gfx_int_cmp_b_u_t;
+
+#else
+
+typedef union pi_gfx_int_cmp_b_u {
+	bdrkreg_t	pi_gfx_int_cmp_b_regval;
+	struct	{
+		bdrkreg_t	gicb_rsvd		  :	38;
+		bdrkreg_t	gicb_gfx_int_cmp	  :	26;
+	} pi_gfx_int_cmp_b_fld_s;
+} pi_gfx_int_cmp_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A read of this register returns all sources of         *
+ * Bedrock Error Interrupts. Storing to the write-with-clear location   *
+ * clears any bit for which a one appears on the data bus. Storing to   *
+ * the writable location does a direct write to all unreserved bits     *
+ * (except for MEM_UNC).                                                *
+ * In Synergy mode, the processor that is the source of the command     *
+ * that got an error is independent of the A or B SysAD bus. So in      *
+ * Synergy mode, Synergy provides the source processor number in bit    *
+ * 52 of the SysAD bus in all commands. The PI saves this in the RRB    *
+ * or WRB entry, and uses that value to determine which error bit (A    *
+ * or B) to set, as well as which ERR_STATUS and spool registers to     *
+ * use, for all error types in this register that are specified as an   *
+ * error to CPU_A or CPU_B.                                             *
+ * This register is not cleared at reset.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_int_pend_wr_u {
+	bdrkreg_t	pi_err_int_pend_wr_regval;
+	struct  {
+		bdrkreg_t	eipw_spool_comp_b         :	 1;
+                bdrkreg_t       eipw_spool_comp_a         :      1;
+                bdrkreg_t       eipw_spurious_b           :      1;
+                bdrkreg_t       eipw_spurious_a           :      1;
+                bdrkreg_t       eipw_wrb_terr_b           :      1;
+                bdrkreg_t       eipw_wrb_terr_a           :      1;
+                bdrkreg_t       eipw_wrb_werr_b           :      1;
+                bdrkreg_t       eipw_wrb_werr_a           :      1;
+                bdrkreg_t       eipw_sysstate_par_b       :      1;
+                bdrkreg_t       eipw_sysstate_par_a       :      1;
+                bdrkreg_t       eipw_sysad_data_ecc_b     :      1;
+                bdrkreg_t       eipw_sysad_data_ecc_a     :      1;
+                bdrkreg_t       eipw_sysad_addr_ecc_b     :      1;
+                bdrkreg_t       eipw_sysad_addr_ecc_a     :      1;
+                bdrkreg_t       eipw_syscmd_data_par_b    :      1;
+                bdrkreg_t       eipw_syscmd_data_par_a    :      1;
+                bdrkreg_t       eipw_syscmd_addr_par_b    :      1;
+                bdrkreg_t       eipw_syscmd_addr_par_a    :      1;
+                bdrkreg_t       eipw_spool_err_b          :      1;
+                bdrkreg_t       eipw_spool_err_a          :      1;
+                bdrkreg_t       eipw_ue_uncached_b        :      1;
+                bdrkreg_t       eipw_ue_uncached_a        :      1;
+                bdrkreg_t       eipw_sysstate_tag_b       :      1;
+                bdrkreg_t       eipw_sysstate_tag_a       :      1;
+                bdrkreg_t       eipw_mem_unc              :      1;
+                bdrkreg_t       eipw_sysad_bad_data_b     :      1;
+                bdrkreg_t       eipw_sysad_bad_data_a     :      1;
+                bdrkreg_t       eipw_ue_cached_b          :      1;
+                bdrkreg_t       eipw_ue_cached_a          :      1;
+                bdrkreg_t       eipw_pkt_len_err_b        :      1;
+                bdrkreg_t       eipw_pkt_len_err_a        :      1;
+                bdrkreg_t       eipw_irb_err_b            :      1;
+                bdrkreg_t       eipw_irb_err_a            :      1;
+                bdrkreg_t       eipw_irb_timeout_b        :      1;
+                bdrkreg_t       eipw_irb_timeout_a        :      1;
+                bdrkreg_t       eipw_rsvd                 :     29;
+	} pi_err_int_pend_wr_fld_s;
+} pi_err_int_pend_wr_u_t;
+
+#else
+
+typedef union pi_err_int_pend_wr_u {
+	bdrkreg_t	pi_err_int_pend_wr_regval;
+	struct	{
+		bdrkreg_t	eipw_rsvd		  :	29;
+		bdrkreg_t	eipw_irb_timeout_a	  :	 1;
+		bdrkreg_t	eipw_irb_timeout_b	  :	 1;
+		bdrkreg_t	eipw_irb_err_a		  :	 1;
+		bdrkreg_t	eipw_irb_err_b		  :	 1;
+		bdrkreg_t	eipw_pkt_len_err_a	  :	 1;
+		bdrkreg_t	eipw_pkt_len_err_b	  :	 1;
+		bdrkreg_t	eipw_ue_cached_a	  :	 1;
+		bdrkreg_t	eipw_ue_cached_b	  :	 1;
+		bdrkreg_t	eipw_sysad_bad_data_a	  :	 1;
+		bdrkreg_t	eipw_sysad_bad_data_b	  :	 1;
+		bdrkreg_t	eipw_mem_unc		  :	 1;
+		bdrkreg_t	eipw_sysstate_tag_a	  :	 1;
+		bdrkreg_t	eipw_sysstate_tag_b	  :	 1;
+		bdrkreg_t	eipw_ue_uncached_a	  :	 1;
+		bdrkreg_t	eipw_ue_uncached_b	  :	 1;
+		bdrkreg_t	eipw_spool_err_a	  :	 1;
+		bdrkreg_t	eipw_spool_err_b	  :	 1;
+		bdrkreg_t	eipw_syscmd_addr_par_a	  :	 1;
+		bdrkreg_t	eipw_syscmd_addr_par_b	  :	 1;
+		bdrkreg_t	eipw_syscmd_data_par_a	  :	 1;
+		bdrkreg_t	eipw_syscmd_data_par_b	  :	 1;
+		bdrkreg_t	eipw_sysad_addr_ecc_a	  :	 1;
+		bdrkreg_t	eipw_sysad_addr_ecc_b	  :	 1;
+		bdrkreg_t	eipw_sysad_data_ecc_a	  :	 1;
+		bdrkreg_t	eipw_sysad_data_ecc_b	  :	 1;
+		bdrkreg_t	eipw_sysstate_par_a	  :	 1;
+		bdrkreg_t	eipw_sysstate_par_b	  :	 1;
+		bdrkreg_t	eipw_wrb_werr_a		  :	 1;
+		bdrkreg_t	eipw_wrb_werr_b		  :	 1;
+		bdrkreg_t	eipw_wrb_terr_a		  :	 1;
+		bdrkreg_t	eipw_wrb_terr_b		  :	 1;
+		bdrkreg_t	eipw_spurious_a		  :	 1;
+		bdrkreg_t	eipw_spurious_b		  :	 1;
+		bdrkreg_t	eipw_spool_comp_a	  :	 1;
+		bdrkreg_t	eipw_spool_comp_b	  :	 1;
+	} pi_err_int_pend_wr_fld_s;
+} pi_err_int_pend_wr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A read of this register returns all sources of         *
+ * Bedrock Error Interrupts. Storing to the write-with-clear location   *
+ * clears any bit for which a one appears on the data bus. Storing to   *
+ * the writable location does a direct write to all unreserved bits     *
+ * (except for MEM_UNC).                                                *
+ * In Synergy mode, the processor that is the source of the command     *
+ * that got an error is independent of the A or B SysAD bus. So in      *
+ * Synergy mode, Synergy provides the source processor number in bit    *
+ * 52 of the SysAD bus in all commands. The PI saves this in the RRB    *
+ * or WRB entry, and uses that value to determine which error bit (A    *
+ * or B) to set, as well as which ERR_STATUS and spool registers to     *
+ * use, for all error types in this register that are specified as an   *
+ * error to CPU_A or CPU_B.                                             *
+ * This register is not cleared at reset.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_int_pend_u {
+	bdrkreg_t	pi_err_int_pend_regval;
+	struct  {
+		bdrkreg_t	eip_spool_comp_b          :	 1;
+                bdrkreg_t       eip_spool_comp_a          :      1;
+                bdrkreg_t       eip_spurious_b            :      1;
+                bdrkreg_t       eip_spurious_a            :      1;
+                bdrkreg_t       eip_wrb_terr_b            :      1;
+                bdrkreg_t       eip_wrb_terr_a            :      1;
+                bdrkreg_t       eip_wrb_werr_b            :      1;
+                bdrkreg_t       eip_wrb_werr_a            :      1;
+                bdrkreg_t       eip_sysstate_par_b        :      1;
+                bdrkreg_t       eip_sysstate_par_a        :      1;
+                bdrkreg_t       eip_sysad_data_ecc_b      :      1;
+                bdrkreg_t       eip_sysad_data_ecc_a      :      1;
+                bdrkreg_t       eip_sysad_addr_ecc_b      :      1;
+                bdrkreg_t       eip_sysad_addr_ecc_a      :      1;
+                bdrkreg_t       eip_syscmd_data_par_b     :      1;
+                bdrkreg_t       eip_syscmd_data_par_a     :      1;
+                bdrkreg_t       eip_syscmd_addr_par_b     :      1;
+                bdrkreg_t       eip_syscmd_addr_par_a     :      1;
+                bdrkreg_t       eip_spool_err_b           :      1;
+                bdrkreg_t       eip_spool_err_a           :      1;
+                bdrkreg_t       eip_ue_uncached_b         :      1;
+                bdrkreg_t       eip_ue_uncached_a         :      1;
+                bdrkreg_t       eip_sysstate_tag_b        :      1;
+                bdrkreg_t       eip_sysstate_tag_a        :      1;
+                bdrkreg_t       eip_mem_unc               :      1;
+                bdrkreg_t       eip_sysad_bad_data_b      :      1;
+                bdrkreg_t       eip_sysad_bad_data_a      :      1;
+                bdrkreg_t       eip_ue_cached_b           :      1;
+                bdrkreg_t       eip_ue_cached_a           :      1;
+                bdrkreg_t       eip_pkt_len_err_b         :      1;
+                bdrkreg_t       eip_pkt_len_err_a         :      1;
+                bdrkreg_t       eip_irb_err_b             :      1;
+                bdrkreg_t       eip_irb_err_a             :      1;
+                bdrkreg_t       eip_irb_timeout_b         :      1;
+                bdrkreg_t       eip_irb_timeout_a         :      1;
+                bdrkreg_t       eip_rsvd                  :     29;
+	} pi_err_int_pend_fld_s;
+} pi_err_int_pend_u_t;
+
+#else
+
+typedef union pi_err_int_pend_u {
+	bdrkreg_t	pi_err_int_pend_regval;
+	struct	{
+		bdrkreg_t	eip_rsvd		  :	29;
+		bdrkreg_t	eip_irb_timeout_a	  :	 1;
+		bdrkreg_t	eip_irb_timeout_b	  :	 1;
+		bdrkreg_t	eip_irb_err_a		  :	 1;
+		bdrkreg_t	eip_irb_err_b		  :	 1;
+		bdrkreg_t	eip_pkt_len_err_a	  :	 1;
+		bdrkreg_t	eip_pkt_len_err_b	  :	 1;
+		bdrkreg_t	eip_ue_cached_a		  :	 1;
+		bdrkreg_t	eip_ue_cached_b		  :	 1;
+		bdrkreg_t	eip_sysad_bad_data_a	  :	 1;
+		bdrkreg_t	eip_sysad_bad_data_b	  :	 1;
+		bdrkreg_t	eip_mem_unc		  :	 1;
+		bdrkreg_t	eip_sysstate_tag_a	  :	 1;
+		bdrkreg_t	eip_sysstate_tag_b	  :	 1;
+		bdrkreg_t	eip_ue_uncached_a	  :	 1;
+		bdrkreg_t	eip_ue_uncached_b	  :	 1;
+		bdrkreg_t	eip_spool_err_a		  :	 1;
+		bdrkreg_t	eip_spool_err_b		  :	 1;
+		bdrkreg_t	eip_syscmd_addr_par_a	  :	 1;
+		bdrkreg_t	eip_syscmd_addr_par_b	  :	 1;
+		bdrkreg_t	eip_syscmd_data_par_a	  :	 1;
+		bdrkreg_t	eip_syscmd_data_par_b	  :	 1;
+		bdrkreg_t	eip_sysad_addr_ecc_a	  :	 1;
+		bdrkreg_t	eip_sysad_addr_ecc_b	  :	 1;
+		bdrkreg_t	eip_sysad_data_ecc_a	  :	 1;
+		bdrkreg_t	eip_sysad_data_ecc_b	  :	 1;
+		bdrkreg_t	eip_sysstate_par_a	  :	 1;
+		bdrkreg_t	eip_sysstate_par_b	  :	 1;
+		bdrkreg_t	eip_wrb_werr_a		  :	 1;
+		bdrkreg_t	eip_wrb_werr_b		  :	 1;
+		bdrkreg_t	eip_wrb_terr_a		  :	 1;
+		bdrkreg_t	eip_wrb_terr_b		  :	 1;
+		bdrkreg_t	eip_spurious_a		  :	 1;
+		bdrkreg_t	eip_spurious_b		  :	 1;
+		bdrkreg_t	eip_spool_comp_a	  :	 1;
+		bdrkreg_t	eip_spool_comp_b	  :	 1;
+	} pi_err_int_pend_fld_s;
+} pi_err_int_pend_u_t;
+
+#endif
+
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. This read/write       *
+ * register masks the contents of ERR_INT_PEND to determine which       *
+ * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set    *
+ * allows the interrupt. Only one processor in a Bedrock should         *
+ * enable the Memory/Directory Uncorrectable Error bit.                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_int_mask_a_u {
+	bdrkreg_t	pi_err_int_mask_a_regval;
+	struct  {
+		bdrkreg_t	eima_mask                 :	35;
+		bdrkreg_t       eima_rsvd                 :     29;
+	} pi_err_int_mask_a_fld_s;
+} pi_err_int_mask_a_u_t;
+
+#else
+
+typedef union pi_err_int_mask_a_u {
+	bdrkreg_t	pi_err_int_mask_a_regval;
+	struct	{
+		bdrkreg_t	eima_rsvd		  :	29;
+		bdrkreg_t	eima_mask		  :	35;
+	} pi_err_int_mask_a_fld_s;
+} pi_err_int_mask_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. This read/write       *
+ * register masks the contents of ERR_INT_PEND to determine which       *
+ * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set    *
+ * allows the interrupt. Only one processor in a Bedrock should         *
+ * enable the Memory/Directory Uncorrectable Error bit.                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_int_mask_b_u {
+	bdrkreg_t	pi_err_int_mask_b_regval;
+	struct  {
+		bdrkreg_t	eimb_mask                 :	35;
+		bdrkreg_t       eimb_rsvd                 :     29;
+	} pi_err_int_mask_b_fld_s;
+} pi_err_int_mask_b_u_t;
+
+#else
+
+typedef union pi_err_int_mask_b_u {
+	bdrkreg_t	pi_err_int_mask_b_regval;
+	struct	{
+		bdrkreg_t	eimb_rsvd		  :	29;
+		bdrkreg_t	eimb_mask		  :	35;
+	} pi_err_int_mask_b_fld_s;
+} pi_err_int_mask_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There is one of these registers for each CPU. This     *
+ * register is the address of the next write to the error stack. This   *
+ * register is incremented after each such write. Only the low N bits   *
+ * are incremented, where N is defined by the size of the error stack   *
+ * specified in the ERR_STACK_SIZE register.                            *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_stack_addr_a_u {
+	bdrkreg_t	pi_err_stack_addr_a_regval;
+	struct  {
+		bdrkreg_t	esaa_rsvd_1               :	 3;
+                bdrkreg_t       esaa_addr                 :     30;
+                bdrkreg_t       esaa_rsvd                 :     31;
+	} pi_err_stack_addr_a_fld_s;
+} pi_err_stack_addr_a_u_t;
+
+#else
+
+typedef union pi_err_stack_addr_a_u {
+	bdrkreg_t	pi_err_stack_addr_a_regval;
+	struct	{
+		bdrkreg_t	esaa_rsvd		  :	31;
+		bdrkreg_t	esaa_addr		  :	30;
+		bdrkreg_t	esaa_rsvd_1		  :	 3;
+	} pi_err_stack_addr_a_fld_s;
+} pi_err_stack_addr_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There is one of these registers for each CPU. This     *
+ * register is the address of the next write to the error stack. This   *
+ * register is incremented after each such write. Only the low N bits   *
+ * are incremented, where N is defined by the size of the error stack   *
+ * specified in the ERR_STACK_SIZE register.                            *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_stack_addr_b_u {
+	bdrkreg_t	pi_err_stack_addr_b_regval;
+	struct  {
+		bdrkreg_t	esab_rsvd_1               :	 3;
+                bdrkreg_t       esab_addr                 :     30;
+                bdrkreg_t       esab_rsvd                 :     31;
+	} pi_err_stack_addr_b_fld_s;
+} pi_err_stack_addr_b_u_t;
+
+#else
+
+typedef union pi_err_stack_addr_b_u {
+	bdrkreg_t	pi_err_stack_addr_b_regval;
+	struct	{
+		bdrkreg_t	esab_rsvd		  :	31;
+		bdrkreg_t	esab_addr		  :	30;
+		bdrkreg_t	esab_rsvd_1		  :	 3;
+	} pi_err_stack_addr_b_fld_s;
+} pi_err_stack_addr_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  Sets the size (number of 64-bit entries) in the        *
+ * error stack that is spooled to local memory when an error occurs.    *
+ * Table16 defines the format of each entry in the spooled error        *
+ * stack.                                                               *
+ * This register is not reset by a soft reset.                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_stack_size_u {
+	bdrkreg_t	pi_err_stack_size_regval;
+	struct  {
+		bdrkreg_t	ess_size                  :	 4;
+                bdrkreg_t       ess_rsvd                  :     60;
+	} pi_err_stack_size_fld_s;
+} pi_err_stack_size_u_t;
+
+#else
+
+typedef union pi_err_stack_size_u {
+	bdrkreg_t	pi_err_stack_size_regval;
+	struct	{
+		bdrkreg_t	ess_rsvd		  :	60;
+		bdrkreg_t	ess_size		  :	 4;
+	} pi_err_stack_size_fld_s;
+} pi_err_stack_size_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_A and ERR_STATUS1_A registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status0_a_u {
+	bdrkreg_t	pi_err_status0_a_regval;
+	struct  {
+		bdrkreg_t	esa_error_type            :	 3;
+                bdrkreg_t       esa_proc_req_num          :      3;
+                bdrkreg_t       esa_supplemental          :     11;
+                bdrkreg_t       esa_cmd                   :      8;
+                bdrkreg_t       esa_addr                  :     37;
+                bdrkreg_t       esa_over_run              :      1;
+                bdrkreg_t       esa_valid                 :      1;
+	} pi_err_status0_a_fld_s;
+} pi_err_status0_a_u_t;
+
+#else
+
+typedef union pi_err_status0_a_u {
+	bdrkreg_t	pi_err_status0_a_regval;
+	struct	{
+		bdrkreg_t	esa_valid		  :	 1;
+		bdrkreg_t	esa_over_run		  :	 1;
+		bdrkreg_t	esa_addr		  :	37;
+		bdrkreg_t	esa_cmd			  :	 8;
+		bdrkreg_t	esa_supplemental	  :	11;
+		bdrkreg_t	esa_proc_req_num	  :	 3;
+		bdrkreg_t	esa_error_type		  :	 3;
+	} pi_err_status0_a_fld_s;
+} pi_err_status0_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_A and ERR_STATUS1_A registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status0_a_clr_u {
+	bdrkreg_t	pi_err_status0_a_clr_regval;
+	struct  {
+		bdrkreg_t	esac_error_type           :	 3;
+                bdrkreg_t       esac_proc_req_num         :      3;
+                bdrkreg_t       esac_supplemental         :     11;
+                bdrkreg_t       esac_cmd                  :      8;
+                bdrkreg_t       esac_addr                 :     37;
+                bdrkreg_t       esac_over_run             :      1;
+                bdrkreg_t       esac_valid                :      1;
+	} pi_err_status0_a_clr_fld_s;
+} pi_err_status0_a_clr_u_t;
+
+#else
+
+typedef union pi_err_status0_a_clr_u {
+	bdrkreg_t	pi_err_status0_a_clr_regval;
+	struct	{
+		bdrkreg_t	esac_valid		  :	 1;
+		bdrkreg_t	esac_over_run		  :	 1;
+		bdrkreg_t	esac_addr		  :	37;
+		bdrkreg_t	esac_cmd		  :	 8;
+		bdrkreg_t	esac_supplemental	  :	11;
+		bdrkreg_t	esac_proc_req_num	  :	 3;
+		bdrkreg_t	esac_error_type		  :	 3;
+	} pi_err_status0_a_clr_fld_s;
+} pi_err_status0_a_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_A and ERR_STATUS1_A registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status1_a_u {
+	bdrkreg_t	pi_err_status1_a_regval;
+	struct  {
+		bdrkreg_t	esa_spool_count           :	21;
+                bdrkreg_t       esa_time_out_count        :      8;
+                bdrkreg_t       esa_inval_count           :     10;
+                bdrkreg_t       esa_crb_num               :      3;
+                bdrkreg_t       esa_wrb                   :      1;
+                bdrkreg_t       esa_e_bits                :      2;
+                bdrkreg_t       esa_t_bit                 :      1;
+                bdrkreg_t       esa_i_bit                 :      1;
+                bdrkreg_t       esa_h_bit                 :      1;
+                bdrkreg_t       esa_w_bit                 :      1;
+                bdrkreg_t       esa_a_bit                 :      1;
+                bdrkreg_t       esa_r_bit                 :      1;
+                bdrkreg_t       esa_v_bit                 :      1;
+                bdrkreg_t       esa_p_bit                 :      1;
+                bdrkreg_t       esa_source                :     11;
+	} pi_err_status1_a_fld_s;
+} pi_err_status1_a_u_t;
+
+#else
+
+typedef union pi_err_status1_a_u {
+	bdrkreg_t	pi_err_status1_a_regval;
+	struct	{
+		bdrkreg_t	esa_source		  :	11;
+		bdrkreg_t	esa_p_bit		  :	 1;
+		bdrkreg_t	esa_v_bit		  :	 1;
+		bdrkreg_t	esa_r_bit		  :	 1;
+		bdrkreg_t	esa_a_bit		  :	 1;
+		bdrkreg_t	esa_w_bit		  :	 1;
+		bdrkreg_t	esa_h_bit		  :	 1;
+		bdrkreg_t	esa_i_bit		  :	 1;
+		bdrkreg_t	esa_t_bit		  :	 1;
+		bdrkreg_t	esa_e_bits		  :	 2;
+		bdrkreg_t	esa_wrb			  :	 1;
+		bdrkreg_t	esa_crb_num		  :	 3;
+		bdrkreg_t	esa_inval_count		  :	10;
+		bdrkreg_t	esa_time_out_count	  :	 8;
+		bdrkreg_t	esa_spool_count		  :	21;
+	} pi_err_status1_a_fld_s;
+} pi_err_status1_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_A and ERR_STATUS1_A registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status1_a_clr_u {
+	bdrkreg_t	pi_err_status1_a_clr_regval;
+	struct  {
+		bdrkreg_t	esac_spool_count          :	21;
+                bdrkreg_t       esac_time_out_count       :      8;
+                bdrkreg_t       esac_inval_count          :     10;
+                bdrkreg_t       esac_crb_num              :      3;
+                bdrkreg_t       esac_wrb                  :      1;
+                bdrkreg_t       esac_e_bits               :      2;
+                bdrkreg_t       esac_t_bit                :      1;
+                bdrkreg_t       esac_i_bit                :      1;
+                bdrkreg_t       esac_h_bit                :      1;
+                bdrkreg_t       esac_w_bit                :      1;
+                bdrkreg_t       esac_a_bit                :      1;
+                bdrkreg_t       esac_r_bit                :      1;
+                bdrkreg_t       esac_v_bit                :      1;
+                bdrkreg_t       esac_p_bit                :      1;
+                bdrkreg_t       esac_source               :     11;
+	} pi_err_status1_a_clr_fld_s;
+} pi_err_status1_a_clr_u_t;
+
+#else
+
+typedef union pi_err_status1_a_clr_u {
+	bdrkreg_t	pi_err_status1_a_clr_regval;
+	struct	{
+		bdrkreg_t	esac_source		  :	11;
+		bdrkreg_t	esac_p_bit		  :	 1;
+		bdrkreg_t	esac_v_bit		  :	 1;
+		bdrkreg_t	esac_r_bit		  :	 1;
+		bdrkreg_t	esac_a_bit		  :	 1;
+		bdrkreg_t	esac_w_bit		  :	 1;
+		bdrkreg_t	esac_h_bit		  :	 1;
+		bdrkreg_t	esac_i_bit		  :	 1;
+		bdrkreg_t	esac_t_bit		  :	 1;
+		bdrkreg_t	esac_e_bits		  :	 2;
+		bdrkreg_t	esac_wrb		  :	 1;
+		bdrkreg_t	esac_crb_num		  :	 3;
+		bdrkreg_t	esac_inval_count	  :	10;
+		bdrkreg_t	esac_time_out_count	  :	 8;
+		bdrkreg_t	esac_spool_count	  :	21;
+	} pi_err_status1_a_clr_fld_s;
+} pi_err_status1_a_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_B and ERR_STATUS1_B registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status0_b_u {
+	bdrkreg_t	pi_err_status0_b_regval;
+	struct  {
+		bdrkreg_t	esb_error_type            :	 3;
+                bdrkreg_t       esb_proc_request_number   :      3;
+                bdrkreg_t       esb_supplemental          :     11;
+                bdrkreg_t       esb_cmd                   :      8;
+                bdrkreg_t       esb_addr                  :     37;
+                bdrkreg_t       esb_over_run              :      1;
+                bdrkreg_t       esb_valid                 :      1;
+	} pi_err_status0_b_fld_s;
+} pi_err_status0_b_u_t;
+
+#else
+
+typedef union pi_err_status0_b_u {
+	bdrkreg_t	pi_err_status0_b_regval;
+	struct	{
+		bdrkreg_t	esb_valid		  :	 1;
+		bdrkreg_t	esb_over_run		  :	 1;
+		bdrkreg_t	esb_addr		  :	37;
+		bdrkreg_t	esb_cmd			  :	 8;
+		bdrkreg_t	esb_supplemental	  :	11;
+		bdrkreg_t	esb_proc_request_number	  :	 3;
+		bdrkreg_t	esb_error_type		  :	 3;
+	} pi_err_status0_b_fld_s;
+} pi_err_status0_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_B and ERR_STATUS1_B registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status0_b_clr_u {
+	bdrkreg_t	pi_err_status0_b_clr_regval;
+	struct  {
+		bdrkreg_t	esbc_error_type           :	 3;
+                bdrkreg_t       esbc_proc_request_number  :      3;
+                bdrkreg_t       esbc_supplemental         :     11;
+                bdrkreg_t       esbc_cmd                  :      8;
+                bdrkreg_t       esbc_addr                 :     37;
+                bdrkreg_t       esbc_over_run             :      1;
+                bdrkreg_t       esbc_valid                :      1;
+	} pi_err_status0_b_clr_fld_s;
+} pi_err_status0_b_clr_u_t;
+
+#else
+
+typedef union pi_err_status0_b_clr_u {
+	bdrkreg_t	pi_err_status0_b_clr_regval;
+	struct	{
+		bdrkreg_t	esbc_valid		  :	 1;
+		bdrkreg_t	esbc_over_run		  :	 1;
+		bdrkreg_t	esbc_addr		  :	37;
+		bdrkreg_t	esbc_cmd		  :	 8;
+		bdrkreg_t	esbc_supplemental	  :	11;
+		bdrkreg_t	esbc_proc_request_number  :	 3;
+		bdrkreg_t	esbc_error_type		  :	 3;
+	} pi_err_status0_b_clr_fld_s;
+} pi_err_status0_b_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_B and ERR_STATUS1_B registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status1_b_u {
+	bdrkreg_t	pi_err_status1_b_regval;
+	struct  {
+		bdrkreg_t	esb_spool_count           :	21;
+                bdrkreg_t       esb_time_out_count        :      8;
+                bdrkreg_t       esb_inval_count           :     10;
+                bdrkreg_t       esb_crb_num               :      3;
+                bdrkreg_t       esb_wrb                   :      1;
+                bdrkreg_t       esb_e_bits                :      2;
+                bdrkreg_t       esb_t_bit                 :      1;
+                bdrkreg_t       esb_i_bit                 :      1;
+                bdrkreg_t       esb_h_bit                 :      1;
+                bdrkreg_t       esb_w_bit                 :      1;
+                bdrkreg_t       esb_a_bit                 :      1;
+                bdrkreg_t       esb_r_bit                 :      1;
+                bdrkreg_t       esb_v_bit                 :      1;
+                bdrkreg_t       esb_p_bit                 :      1;
+                bdrkreg_t       esb_source                :     11;
+	} pi_err_status1_b_fld_s;
+} pi_err_status1_b_u_t;
+
+#else
+
+typedef union pi_err_status1_b_u {
+	bdrkreg_t	pi_err_status1_b_regval;
+	struct	{
+		bdrkreg_t	esb_source		  :	11;
+		bdrkreg_t	esb_p_bit		  :	 1;
+		bdrkreg_t	esb_v_bit		  :	 1;
+		bdrkreg_t	esb_r_bit		  :	 1;
+		bdrkreg_t	esb_a_bit		  :	 1;
+		bdrkreg_t	esb_w_bit		  :	 1;
+		bdrkreg_t	esb_h_bit		  :	 1;
+		bdrkreg_t	esb_i_bit		  :	 1;
+		bdrkreg_t	esb_t_bit		  :	 1;
+		bdrkreg_t	esb_e_bits		  :	 2;
+		bdrkreg_t	esb_wrb			  :	 1;
+		bdrkreg_t	esb_crb_num		  :	 3;
+		bdrkreg_t	esb_inval_count		  :	10;
+		bdrkreg_t	esb_time_out_count	  :	 8;
+		bdrkreg_t	esb_spool_count		  :	21;
+	} pi_err_status1_b_fld_s;
+} pi_err_status1_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. Writing this register with   *
+ * the Write-clear address (with any data) clears both the              *
+ * ERR_STATUS0_B and ERR_STATUS1_B registers.                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_status1_b_clr_u {
+	bdrkreg_t	pi_err_status1_b_clr_regval;
+	struct  {
+		bdrkreg_t	esbc_spool_count          :	21;
+                bdrkreg_t       esbc_time_out_count       :      8;
+                bdrkreg_t       esbc_inval_count          :     10;
+                bdrkreg_t       esbc_crb_num              :      3;
+                bdrkreg_t       esbc_wrb                  :      1;
+                bdrkreg_t       esbc_e_bits               :      2;
+                bdrkreg_t       esbc_t_bit                :      1;
+                bdrkreg_t       esbc_i_bit                :      1;
+                bdrkreg_t       esbc_h_bit                :      1;
+                bdrkreg_t       esbc_w_bit                :      1;
+                bdrkreg_t       esbc_a_bit                :      1;
+                bdrkreg_t       esbc_r_bit                :      1;
+                bdrkreg_t       esbc_v_bit                :      1;
+                bdrkreg_t       esbc_p_bit                :      1;
+                bdrkreg_t       esbc_source               :     11;
+	} pi_err_status1_b_clr_fld_s;
+} pi_err_status1_b_clr_u_t;
+
+#else
+
+typedef union pi_err_status1_b_clr_u {
+	bdrkreg_t	pi_err_status1_b_clr_regval;
+	struct	{
+		bdrkreg_t	esbc_source		  :	11;
+		bdrkreg_t	esbc_p_bit		  :	 1;
+		bdrkreg_t	esbc_v_bit		  :	 1;
+		bdrkreg_t	esbc_r_bit		  :	 1;
+		bdrkreg_t	esbc_a_bit		  :	 1;
+		bdrkreg_t	esbc_w_bit		  :	 1;
+		bdrkreg_t	esbc_h_bit		  :	 1;
+		bdrkreg_t	esbc_i_bit		  :	 1;
+		bdrkreg_t	esbc_t_bit		  :	 1;
+		bdrkreg_t	esbc_e_bits		  :	 2;
+		bdrkreg_t	esbc_wrb		  :	 1;
+		bdrkreg_t	esbc_crb_num		  :	 3;
+		bdrkreg_t	esbc_inval_count	  :	10;
+		bdrkreg_t	esbc_time_out_count	  :	 8;
+		bdrkreg_t	esbc_spool_count	  :	21;
+	} pi_err_status1_b_clr_fld_s;
+} pi_err_status1_b_clr_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_spool_cmp_a_u {
+	bdrkreg_t	pi_spool_cmp_a_regval;
+	struct  {
+		bdrkreg_t	sca_compare               :	20;
+		bdrkreg_t       sca_rsvd                  :     44;
+	} pi_spool_cmp_a_fld_s;
+} pi_spool_cmp_a_u_t;
+
+#else
+
+typedef union pi_spool_cmp_a_u {
+	bdrkreg_t	pi_spool_cmp_a_regval;
+	struct	{
+		bdrkreg_t	sca_rsvd		  :	44;
+		bdrkreg_t	sca_compare		  :	20;
+	} pi_spool_cmp_a_fld_s;
+} pi_spool_cmp_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_spool_cmp_b_u {
+	bdrkreg_t	pi_spool_cmp_b_regval;
+	struct  {
+		bdrkreg_t	scb_compare               :	20;
+		bdrkreg_t       scb_rsvd                  :     44;
+	} pi_spool_cmp_b_fld_s;
+} pi_spool_cmp_b_u_t;
+
+#else
+
+typedef union pi_spool_cmp_b_u {
+	bdrkreg_t	pi_spool_cmp_b_regval;
+	struct	{
+		bdrkreg_t	scb_rsvd		  :	44;
+		bdrkreg_t	scb_compare		  :	20;
+	} pi_spool_cmp_b_fld_s;
+} pi_spool_cmp_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. A timeout can be      *
+ * forced by writing one(s).                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_crb_timeout_a_u {
+	bdrkreg_t	pi_crb_timeout_a_regval;
+	struct  {
+		bdrkreg_t	cta_rrb                   :	 4;
+                bdrkreg_t       cta_wrb                   :      8;
+                bdrkreg_t       cta_rsvd                  :     52;
+	} pi_crb_timeout_a_fld_s;
+} pi_crb_timeout_a_u_t;
+
+#else
+
+typedef union pi_crb_timeout_a_u {
+	bdrkreg_t	pi_crb_timeout_a_regval;
+	struct	{
+		bdrkreg_t	cta_rsvd		  :	52;
+		bdrkreg_t	cta_wrb			  :	 8;
+		bdrkreg_t	cta_rrb			  :	 4;
+	} pi_crb_timeout_a_fld_s;
+} pi_crb_timeout_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. A timeout can be      *
+ * forced by writing one(s).                                            *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_crb_timeout_b_u {
+	bdrkreg_t	pi_crb_timeout_b_regval;
+	struct  {
+		bdrkreg_t	ctb_rrb                   :	 4;
+                bdrkreg_t       ctb_wrb                   :      8;
+                bdrkreg_t       ctb_rsvd                  :     52;
+	} pi_crb_timeout_b_fld_s;
+} pi_crb_timeout_b_u_t;
+
+#else
+
+typedef union pi_crb_timeout_b_u {
+	bdrkreg_t	pi_crb_timeout_b_regval;
+	struct	{
+		bdrkreg_t	ctb_rsvd		  :	52;
+		bdrkreg_t	ctb_wrb			  :	 8;
+		bdrkreg_t	ctb_rrb			  :	 4;
+	} pi_crb_timeout_b_fld_s;
+} pi_crb_timeout_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls error checking and forwarding of SysAD       *
+ * errors.                                                              *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_sysad_errchk_en_u {
+	bdrkreg_t	pi_sysad_errchk_en_regval;
+	struct  {
+		bdrkreg_t	see_ecc_gen_en            :	 1;
+                bdrkreg_t       see_qual_gen_en           :      1;
+                bdrkreg_t       see_sadp_chk_en           :      1;
+                bdrkreg_t       see_cmdp_chk_en           :      1;
+                bdrkreg_t       see_state_chk_en          :      1;
+                bdrkreg_t       see_qual_chk_en           :      1;
+                bdrkreg_t       see_rsvd                  :     58;
+	} pi_sysad_errchk_en_fld_s;
+} pi_sysad_errchk_en_u_t;
+
+#else
+
+typedef union pi_sysad_errchk_en_u {
+	bdrkreg_t	pi_sysad_errchk_en_regval;
+	struct	{
+		bdrkreg_t	see_rsvd		  :	58;
+		bdrkreg_t	see_qual_chk_en		  :	 1;
+		bdrkreg_t	see_state_chk_en	  :	 1;
+		bdrkreg_t	see_cmdp_chk_en		  :	 1;
+		bdrkreg_t	see_sadp_chk_en		  :	 1;
+		bdrkreg_t	see_qual_gen_en		  :	 1;
+		bdrkreg_t	see_ecc_gen_en		  :	 1;
+	} pi_sysad_errchk_en_fld_s;
+} pi_sysad_errchk_en_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. If any bit in this    *
+ * register is set, then whenever reply data arrives with the UE        *
+ * (uncorrectable error) indication set, the check-bits that are        *
+ * generated and sent to the SysAD will be inverted corresponding to    *
+ * the bits set in the register. This will also prevent the assertion   *
+ * of the data quality indicator.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_force_bad_check_bit_a_u {
+	bdrkreg_t	pi_force_bad_check_bit_a_regval;
+	struct  {
+		bdrkreg_t	fbcba_bad_check_bit       :	 8;
+		bdrkreg_t       fbcba_rsvd                :     56;
+	} pi_force_bad_check_bit_a_fld_s;
+} pi_force_bad_check_bit_a_u_t;
+
+#else
+
+typedef union pi_force_bad_check_bit_a_u {
+	bdrkreg_t	pi_force_bad_check_bit_a_regval;
+	struct	{
+		bdrkreg_t	fbcba_rsvd		  :	56;
+		bdrkreg_t	fbcba_bad_check_bit	  :	 8;
+	} pi_force_bad_check_bit_a_fld_s;
+} pi_force_bad_check_bit_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. If any bit in this    *
+ * register is set, then whenever reply data arrives with the UE        *
+ * (uncorrectable error) indication set, the check-bits that are        *
+ * generated and sent to the SysAD will be inverted corresponding to    *
+ * the bits set in the register. This will also prevent the assertion   *
+ * of the data quality indicator.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_force_bad_check_bit_b_u {
+	bdrkreg_t	pi_force_bad_check_bit_b_regval;
+	struct  {
+		bdrkreg_t	fbcbb_bad_check_bit       :	 8;
+		bdrkreg_t       fbcbb_rsvd                :     56;
+	} pi_force_bad_check_bit_b_fld_s;
+} pi_force_bad_check_bit_b_u_t;
+
+#else
+
+typedef union pi_force_bad_check_bit_b_u {
+	bdrkreg_t	pi_force_bad_check_bit_b_regval;
+	struct	{
+		bdrkreg_t	fbcbb_rsvd		  :	56;
+		bdrkreg_t	fbcbb_bad_check_bit	  :	 8;
+	} pi_force_bad_check_bit_b_fld_s;
+} pi_force_bad_check_bit_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. When a counter is     *
+ * enabled, it increments each time a DNACK reply is received. The      *
+ * counter is cleared when any other reply is received. The register    *
+ * is cleared when the CNT_EN bit is zero. If a DNACK reply is          *
+ * received when the counter equals the value in the NACK_CMP           *
+ * register, the counter is cleared, an error response is sent to the   *
+ * CPU instead of a nack response, and the NACK_INT_A/B bit is set in   *
+ * INT_PEND1.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_nack_cnt_a_u {
+	bdrkreg_t	pi_nack_cnt_a_regval;
+	struct  {
+		bdrkreg_t	nca_nack_cnt              :	20;
+                bdrkreg_t       nca_cnt_en                :      1;
+                bdrkreg_t       nca_rsvd                  :     43;
+	} pi_nack_cnt_a_fld_s;
+} pi_nack_cnt_a_u_t;
+
+#else
+
+typedef union pi_nack_cnt_a_u {
+	bdrkreg_t	pi_nack_cnt_a_regval;
+	struct	{
+		bdrkreg_t	nca_rsvd		  :	43;
+		bdrkreg_t	nca_cnt_en		  :	 1;
+		bdrkreg_t	nca_nack_cnt		  :	20;
+	} pi_nack_cnt_a_fld_s;
+} pi_nack_cnt_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There is one of these registers for each CPU. When a counter is     *
+ * enabled, it increments each time a DNACK reply is received. The      *
+ * counter is cleared when any other reply is received. The register    *
+ * is cleared when the CNT_EN bit is zero. If a DNACK reply is          *
+ * received when the counter equals the value in the NACK_CMP           *
+ * register, the counter is cleared, an error response is sent to the   *
+ * CPU instead of a nack response, and the NACK_INT_A/B bit is set in   *
+ * INT_PEND1.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_nack_cnt_b_u {
+	bdrkreg_t	pi_nack_cnt_b_regval;
+	struct  {
+		bdrkreg_t	ncb_nack_cnt              :	20;
+                bdrkreg_t       ncb_cnt_en                :      1;
+                bdrkreg_t       ncb_rsvd                  :     43;
+	} pi_nack_cnt_b_fld_s;
+} pi_nack_cnt_b_u_t;
+
+#else
+
+typedef union pi_nack_cnt_b_u {
+	bdrkreg_t	pi_nack_cnt_b_regval;
+	struct	{
+		bdrkreg_t	ncb_rsvd		  :	43;
+		bdrkreg_t	ncb_cnt_en		  :	 1;
+		bdrkreg_t	ncb_nack_cnt		  :	20;
+	} pi_nack_cnt_b_fld_s;
+} pi_nack_cnt_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  The setting of this register affects both CPUs on this PI.          *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_nack_cmp_u {
+	bdrkreg_t	pi_nack_cmp_regval;
+	struct  {
+		bdrkreg_t	nc_nack_cmp               :	20;
+		bdrkreg_t       nc_rsvd                   :     44;
+	} pi_nack_cmp_fld_s;
+} pi_nack_cmp_u_t;
+
+#else
+
+typedef union pi_nack_cmp_u {
+	bdrkreg_t	pi_nack_cmp_regval;
+	struct	{
+		bdrkreg_t	nc_rsvd			  :	44;
+		bdrkreg_t	nc_nack_cmp		  :	20;
+	} pi_nack_cmp_fld_s;
+} pi_nack_cmp_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls which errors are spooled. When a bit in      *
+ * this register is set, the corresponding error is spooled. The        *
+ * setting of this register affects both CPUs on this PI.               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_spool_mask_u {
+	bdrkreg_t	pi_spool_mask_regval;
+	struct  {
+		bdrkreg_t	sm_access_err             :	 1;
+                bdrkreg_t       sm_uncached_err           :      1;
+                bdrkreg_t       sm_dir_err                :      1;
+                bdrkreg_t       sm_timeout_err            :      1;
+                bdrkreg_t       sm_poison_err             :      1;
+                bdrkreg_t       sm_nack_oflow_err         :      1;
+                bdrkreg_t       sm_rsvd                   :     58;
+	} pi_spool_mask_fld_s;
+} pi_spool_mask_u_t;
+
+#else
+
+typedef union pi_spool_mask_u {
+	bdrkreg_t	pi_spool_mask_regval;
+	struct	{
+		bdrkreg_t	sm_rsvd			  :	58;
+		bdrkreg_t	sm_nack_oflow_err	  :	 1;
+		bdrkreg_t	sm_poison_err		  :	 1;
+		bdrkreg_t	sm_timeout_err		  :	 1;
+		bdrkreg_t	sm_dir_err		  :	 1;
+		bdrkreg_t	sm_uncached_err		  :	 1;
+		bdrkreg_t	sm_access_err		  :	 1;
+	} pi_spool_mask_fld_s;
+} pi_spool_mask_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. When the VALID bit is        *
+ * zero, this register (along with SPURIOUS_HDR_1) will capture the     *
+ * header of an incoming spurious message received from the XBar. A     *
+ * spurious message is a message that does not match up with any of     *
+ * the CRB entries. This is a read/write register, so it is cleared     *
+ * by writing of all zeros.                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_spurious_hdr_0_u {
+	bdrkreg_t	pi_spurious_hdr_0_regval;
+	struct  {
+		bdrkreg_t	sh0_prev_valid_b          :	 1;
+                bdrkreg_t       sh0_prev_valid_a          :      1;
+                bdrkreg_t       sh0_rsvd                  :      4;
+                bdrkreg_t       sh0_supplemental          :     11;
+                bdrkreg_t       sh0_cmd                   :      8;
+                bdrkreg_t       sh0_addr                  :     37;
+                bdrkreg_t       sh0_tail                  :      1;
+                bdrkreg_t       sh0_valid                 :      1;
+	} pi_spurious_hdr_0_fld_s;
+} pi_spurious_hdr_0_u_t;
+
+#else
+
+typedef union pi_spurious_hdr_0_u {
+	bdrkreg_t	pi_spurious_hdr_0_regval;
+	struct	{
+		bdrkreg_t	sh0_valid		  :	 1;
+		bdrkreg_t	sh0_tail		  :	 1;
+		bdrkreg_t	sh0_addr		  :	37;
+		bdrkreg_t	sh0_cmd			  :	 8;
+		bdrkreg_t	sh0_supplemental	  :	11;
+		bdrkreg_t	sh0_rsvd		  :	 4;
+		bdrkreg_t	sh0_prev_valid_a	  :	 1;
+		bdrkreg_t	sh0_prev_valid_b	  :	 1;
+	} pi_spurious_hdr_0_fld_s;
+} pi_spurious_hdr_0_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is not cleared at reset. When the VALID bit in        *
+ * SPURIOUS_HDR_0 is zero, this register (along with SPURIOUS_HDR_0)    *
+ * will capture the header of an incoming spurious message received     *
+ * from the XBar. A spurious message is a message that does not match   *
+ * up with any of the CRB entries. This is a read/write register, so    *
+ * it is cleared by writing of all zeros.                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_spurious_hdr_1_u {
+	bdrkreg_t	pi_spurious_hdr_1_regval;
+	struct  {
+		bdrkreg_t	sh1_rsvd                  :	53;
+		bdrkreg_t       sh1_source                :     11;
+	} pi_spurious_hdr_1_fld_s;
+} pi_spurious_hdr_1_u_t;
+
+#else
+
+typedef union pi_spurious_hdr_1_u {
+	bdrkreg_t	pi_spurious_hdr_1_regval;
+	struct	{
+		bdrkreg_t	sh1_source		  :	11;
+		bdrkreg_t	sh1_rsvd		  :	53;
+	} pi_spurious_hdr_1_fld_s;
+} pi_spurious_hdr_1_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register controls the injection of errors in      *
+ * outbound SysAD transfers. When a write sets a bit in this            *
+ * register, the PI logic is "armed" to inject that error. At the       *
+ * first transfer of the specified type, the error is injected and      *
+ * the bit in this register is cleared. Writing to this register does   *
+ * not cause a transaction to occur. A bit in this register will        *
+ * remain set until a transaction of the specified type occurs as a     *
+ * result of normal system activity. This register can be polled to     *
+ * determine if an error has been injected or is still "armed".         *
+ * This register does not control injection of data quality bad         *
+ * indicator on a data cycle. This type of error can be created by      *
+ * reading from a memory location that has an uncorrectable ECC         *
+ * error.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_err_inject_u {
+	bdrkreg_t	pi_err_inject_regval;
+	struct  {
+		bdrkreg_t	ei_cmd_syscmd_par_a       :	 1;
+                bdrkreg_t       ei_data_syscmd_par_a      :      1;
+                bdrkreg_t       ei_cmd_sysad_corecc_a     :      1;
+                bdrkreg_t       ei_data_sysad_corecc_a    :      1;
+                bdrkreg_t       ei_cmd_sysad_uncecc_a     :      1;
+                bdrkreg_t       ei_data_sysad_uncecc_a    :      1;
+                bdrkreg_t       ei_sysresp_par_a          :      1;
+                bdrkreg_t       ei_reserved_1             :     25;
+                bdrkreg_t       ei_cmd_syscmd_par_b       :      1;
+                bdrkreg_t       ei_data_syscmd_par_b      :      1;
+                bdrkreg_t       ei_cmd_sysad_corecc_b     :      1;
+                bdrkreg_t       ei_data_sysad_corecc_b    :      1;
+                bdrkreg_t       ei_cmd_sysad_uncecc_b     :      1;
+                bdrkreg_t       ei_data_sysad_uncecc_b    :      1;
+                bdrkreg_t       ei_sysresp_par_b          :      1;
+                bdrkreg_t       ei_reserved               :     25;
+	} pi_err_inject_fld_s;
+} pi_err_inject_u_t;
+
+#else
+
+typedef union pi_err_inject_u {
+	bdrkreg_t	pi_err_inject_regval;
+	struct	{
+		bdrkreg_t	ei_reserved		  :	25;
+		bdrkreg_t	ei_sysresp_par_b	  :	 1;
+		bdrkreg_t	ei_data_sysad_uncecc_b	  :	 1;
+		bdrkreg_t	ei_cmd_sysad_uncecc_b	  :	 1;
+		bdrkreg_t	ei_data_sysad_corecc_b	  :	 1;
+		bdrkreg_t	ei_cmd_sysad_corecc_b	  :	 1;
+		bdrkreg_t	ei_data_syscmd_par_b	  :	 1;
+		bdrkreg_t	ei_cmd_syscmd_par_b	  :	 1;
+		bdrkreg_t	ei_reserved_1		  :	25;
+		bdrkreg_t	ei_sysresp_par_a	  :	 1;
+		bdrkreg_t	ei_data_sysad_uncecc_a	  :	 1;
+		bdrkreg_t	ei_cmd_sysad_uncecc_a	  :	 1;
+		bdrkreg_t	ei_data_sysad_corecc_a	  :	 1;
+		bdrkreg_t	ei_cmd_sysad_corecc_a	  :	 1;
+		bdrkreg_t	ei_data_syscmd_par_a	  :	 1;
+		bdrkreg_t	ei_cmd_syscmd_par_a	  :	 1;
+	} pi_err_inject_fld_s;
+} pi_err_inject_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This Read/Write location determines at what point the TRex+ is      *
+ * stopped from issuing requests, based on the number of entries in     *
+ * the incoming reply FIFO. When the number of entries in the Reply     *
+ * FIFO is greater than the value of this register, the PI will         *
+ * deassert both SysWrRdy and SysRdRdy to both processors. The Reply    *
+ * FIFO has a depth of 0x3F entries, so setting this register to 0x3F   *
+ * effectively disables this feature, allowing requests to be issued    *
+ * always. Setting this register to 0x00 effectively lowers the         *
+ * TRex+'s priority below the reply FIFO, disabling TRex+ requests      *
+ * any time there is an entry waiting in the incoming FIFO.This         *
+ * register is in its own 64KB page so that it can be mapped to user    *
+ * space.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_reply_level_u {
+	bdrkreg_t	pi_reply_level_regval;
+	struct  {
+		bdrkreg_t	rl_reply_level            :	 6;
+		bdrkreg_t	rl_rsvd			  :	58;
+	} pi_reply_level_fld_s;
+} pi_reply_level_u_t;
+
+#else
+
+typedef union pi_reply_level_u {
+	bdrkreg_t	pi_reply_level_regval;
+	struct	{
+		bdrkreg_t	rl_rsvd			  :	58;
+		bdrkreg_t	rl_reply_level		  :	 6;
+	} pi_reply_level_fld_s;
+} pi_reply_level_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register is used to change the graphics credit counter         *
+ * operation from "Doubleword" mode to "Transaction" mode. This         *
+ * register is in its own 64KB page so that it can be mapped to user    *
+ * space.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_gfx_credit_mode_u {
+	bdrkreg_t	pi_gfx_credit_mode_regval;
+	struct  {
+		bdrkreg_t	gcm_trans_mode            :	 1;
+		bdrkreg_t       gcm_rsvd                  :     63;
+	} pi_gfx_credit_mode_fld_s;
+} pi_gfx_credit_mode_u_t;
+
+#else
+
+typedef union pi_gfx_credit_mode_u {
+	bdrkreg_t	pi_gfx_credit_mode_regval;
+	struct	{
+		bdrkreg_t	gcm_rsvd		  :	63;
+		bdrkreg_t	gcm_trans_mode		  :	 1;
+	} pi_gfx_credit_mode_fld_s;
+} pi_gfx_credit_mode_u_t;
+
+#endif
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This location contains a 55-bit read/write counter that wraps to    *
+ * zero when the maximum value is reached. This counter is              *
+ * incremented at each rising edge of the global clock (GCLK). This     *
+ * register is in its own 64KB page so that it can be mapped to user    *
+ * space.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_rt_counter_u {
+	bdrkreg_t	pi_rt_counter_regval;
+	struct  {
+		bdrkreg_t	rc_count                  :	55;
+		bdrkreg_t       rc_rsvd                   :      9;
+	} pi_rt_counter_fld_s;
+} pi_rt_counter_u_t;
+
+#else
+
+typedef union pi_rt_counter_u {
+	bdrkreg_t	pi_rt_counter_regval;
+	struct	{
+		bdrkreg_t	rc_rsvd			  :	 9;
+		bdrkreg_t	rc_count		  :	55;
+	} pi_rt_counter_fld_s;
+} pi_rt_counter_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls the performance counters for one CPU.        *
+ * There are two counters for each CPU. Each counter can be             *
+ * configured to count a variety of events. The performance counter     *
+ * registers for each processor are in their own 64KB page so that      *
+ * they can be mapped to user space.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_perf_cntl_a_u {
+	bdrkreg_t	pi_perf_cntl_a_regval;
+	struct  {
+		bdrkreg_t	pca_cntr_0_select         :	28;
+                bdrkreg_t       pca_cntr_0_mode           :      3;
+                bdrkreg_t       pca_cntr_0_enable         :      1;
+                bdrkreg_t       pca_cntr_1_select         :     28;
+                bdrkreg_t       pca_cntr_1_mode           :      3;
+                bdrkreg_t       pca_cntr_1_enable         :      1;
+	} pi_perf_cntl_a_fld_s;
+} pi_perf_cntl_a_u_t;
+
+#else
+
+typedef union pi_perf_cntl_a_u {
+	bdrkreg_t	pi_perf_cntl_a_regval;
+	struct	{
+		bdrkreg_t	pca_cntr_1_enable	  :	 1;
+		bdrkreg_t	pca_cntr_1_mode		  :	 3;
+		bdrkreg_t	pca_cntr_1_select	  :	28;
+		bdrkreg_t	pca_cntr_0_enable	  :	 1;
+		bdrkreg_t	pca_cntr_0_mode		  :	 3;
+		bdrkreg_t	pca_cntr_0_select	  :	28;
+	} pi_perf_cntl_a_fld_s;
+} pi_perf_cntl_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register accesses the performance counter 0 for each CPU.      *
+ * Each performance counter is 40-bits wide. On overflow, It wraps to   *
+ * zero, sets the overflow bit in this register, and sets the           *
+ * PERF_CNTR_OFLOW bit in the INT_PEND1 register.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_perf_cntr0_a_u {
+	bdrkreg_t	pi_perf_cntr0_a_regval;
+	struct  {
+		bdrkreg_t	pca_count_value           :	40;
+                bdrkreg_t       pca_overflow              :      1;
+                bdrkreg_t       pca_rsvd                  :     23;
+	} pi_perf_cntr0_a_fld_s;
+} pi_perf_cntr0_a_u_t;
+
+#else
+
+typedef union pi_perf_cntr0_a_u {
+	bdrkreg_t	pi_perf_cntr0_a_regval;
+	struct	{
+		bdrkreg_t	pca_rsvd		  :	23;
+		bdrkreg_t	pca_overflow		  :	 1;
+		bdrkreg_t	pca_count_value		  :	40;
+	} pi_perf_cntr0_a_fld_s;
+} pi_perf_cntr0_a_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register accesses the performance counter 1for each CPU.       *
+ * Each performance counter is 40-bits wide. On overflow, It wraps to   *
+ * zero, sets the overflow bit in this register, and sets the           *
+ * PERF_CNTR_OFLOW bit in the INT_PEND1 register.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_perf_cntr1_a_u {
+	bdrkreg_t	pi_perf_cntr1_a_regval;
+	struct  {
+		bdrkreg_t	pca_count_value           :	40;
+                bdrkreg_t       pca_overflow              :      1;
+                bdrkreg_t       pca_rsvd                  :     23;
+	} pi_perf_cntr1_a_fld_s;
+} pi_perf_cntr1_a_u_t;
+
+#else
+
+typedef union pi_perf_cntr1_a_u {
+	bdrkreg_t	pi_perf_cntr1_a_regval;
+	struct	{
+		bdrkreg_t	pca_rsvd		  :	23;
+		bdrkreg_t	pca_overflow		  :	 1;
+		bdrkreg_t	pca_count_value		  :	40;
+	} pi_perf_cntr1_a_fld_s;
+} pi_perf_cntr1_a_u_t;
+
+#endif
+
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls the performance counters for one CPU.        *
+ * There are two counters for each CPU. Each counter can be             *
+ * configured to count a variety of events. The performance counter     *
+ * registers for each processor are in their own 64KB page so that      *
+ * they can be mapped to user space.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_perf_cntl_b_u {
+	bdrkreg_t	pi_perf_cntl_b_regval;
+	struct  {
+		bdrkreg_t	pcb_cntr_0_select         :	28;
+                bdrkreg_t       pcb_cntr_0_mode           :      3;
+                bdrkreg_t       pcb_cntr_0_enable         :      1;
+                bdrkreg_t       pcb_cntr_1_select         :     28;
+                bdrkreg_t       pcb_cntr_1_mode           :      3;
+                bdrkreg_t       pcb_cntr_1_enable         :      1;
+	} pi_perf_cntl_b_fld_s;
+} pi_perf_cntl_b_u_t;
+
+#else
+
+typedef union pi_perf_cntl_b_u {
+	bdrkreg_t	pi_perf_cntl_b_regval;
+	struct	{
+		bdrkreg_t	pcb_cntr_1_enable	  :	 1;
+		bdrkreg_t	pcb_cntr_1_mode		  :	 3;
+		bdrkreg_t	pcb_cntr_1_select	  :	28;
+		bdrkreg_t	pcb_cntr_0_enable	  :	 1;
+		bdrkreg_t	pcb_cntr_0_mode		  :	 3;
+		bdrkreg_t	pcb_cntr_0_select	  :	28;
+	} pi_perf_cntl_b_fld_s;
+} pi_perf_cntl_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register accesses the performance counter 0 for each CPU.      *
+ * Each performance counter is 40-bits wide. On overflow, It wraps to   *
+ * zero, sets the overflow bit in this register, and sets the           *
+ * PERF_CNTR_OFLOW bit in the INT_PEND1 register.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_perf_cntr0_b_u {
+	bdrkreg_t	pi_perf_cntr0_b_regval;
+	struct  {
+		bdrkreg_t	pcb_count_value           :	40;
+                bdrkreg_t       pcb_overflow              :      1;
+                bdrkreg_t       pcb_rsvd                  :     23;
+	} pi_perf_cntr0_b_fld_s;
+} pi_perf_cntr0_b_u_t;
+
+#else
+
+typedef union pi_perf_cntr0_b_u {
+	bdrkreg_t	pi_perf_cntr0_b_regval;
+	struct	{
+		bdrkreg_t	pcb_rsvd		  :	23;
+		bdrkreg_t	pcb_overflow		  :	 1;
+		bdrkreg_t	pcb_count_value		  :	40;
+	} pi_perf_cntr0_b_fld_s;
+} pi_perf_cntr0_b_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register accesses the performance counter 1for each CPU.       *
+ * Each performance counter is 40-bits wide. On overflow, It wraps to   *
+ * zero, sets the overflow bit in this register, and sets the           *
+ * PERF_CNTR_OFLOW bit in the INT_PEND1 register.                       *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union pi_perf_cntr1_b_u {
+	bdrkreg_t	pi_perf_cntr1_b_regval;
+	struct  {
+		bdrkreg_t	pcb_count_value           :	40;
+                bdrkreg_t       pcb_overflow              :      1;
+                bdrkreg_t       pcb_rsvd                  :     23;
+	} pi_perf_cntr1_b_fld_s;
+} pi_perf_cntr1_b_u_t;
+
+#else
+
+typedef union pi_perf_cntr1_b_u {
+	bdrkreg_t	pi_perf_cntr1_b_regval;
+	struct	{
+		bdrkreg_t	pcb_rsvd		  :	23;
+		bdrkreg_t	pcb_overflow		  :	 1;
+		bdrkreg_t	pcb_count_value		  :	40;
+	} pi_perf_cntr1_b_fld_s;
+} pi_perf_cntr1_b_u_t;
+
+#endif
+
+
+
+
+
+
+#endif /* _LANGUAGE_C */
+
+/************************************************************************
+ *                                                                      *
+ *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+#define PI_GFX_OFFSET		(PI_GFX_PAGE_B - PI_GFX_PAGE_A)
+#define PI_GFX_PAGE_ENABLE	0x0000010000000000LL
+
+
+#endif /* _ASM_SN_SN1_HUBPI_H */
diff --git a/include/asm-ia64/sn/sn1/hubpi_next.h b/include/asm-ia64/sn/sn1/hubpi_next.h
new file mode 100644
index 000000000..1e31d2722
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubpi_next.h
@@ -0,0 +1,332 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBPI_NEXT_H
+#define _ASM_SN_SN1_HUBPI_NEXT_H
+
+
+/* define for remote PI_1 space. It is always half of a node_addressspace
+ * from PI_0. The normal REMOTE_HUB space for PI registers access
+ * the PI_0 space, unless they are qualified by PI_1.
+ */
+#define PI_0(x)			(x)
+#define PI_1(x)			((x) + 0x200000)
+#define PIREG(x,sn)		((sn) ? PI_1(x) : PI_0(x))
+
+#define PI_MIN_STACK_SIZE 4096  /* For figuring out the size to set */
+#define PI_STACK_SIZE_SHFT      12      /* 4k */
+
+#define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
+#define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
+#define PI_RDCLR_OFFSET         (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
+/* these macros are correct, but fix their users to understand two PIs
+   and 4 CPUs (slices) per bedrock */
+#define PI_INT_MASK_OFFSET      (PI_INT_MASK0_B - PI_INT_MASK0_A)
+#define PI_INT_SET_OFFSET       (PI_CC_PEND_CLR_B - PI_CC_PEND_CLR_A)
+#define PI_NMI_OFFSET		(PI_NMI_B - PI_NMI_A)
+
+#define ERR_STACK_SIZE_BYTES(_sz) \
+       ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
+
+#define PI_CRB_STS_P	(1 << 9) 	/* "P" (partial word read/write) bit */
+#define PI_CRB_STS_V	(1 << 8)	/* "V" (valid) bit */
+#define PI_CRB_STS_R	(1 << 7)	/* "R" (response data sent to CPU) */
+#define PI_CRB_STS_A	(1 << 6)	/* "A" (data ack. received) bit */
+#define PI_CRB_STS_W	(1 << 5)	/* "W" (waiting for write compl.) */
+#define PI_CRB_STS_H	(1 << 4)	/* "H" (gathering invalidates) bit */
+#define PI_CRB_STS_I	(1 << 3)	/* "I" (targ. inbound invalidate) */
+#define PI_CRB_STS_T	(1 << 2)	/* "T" (targ. inbound intervention) */
+#define PI_CRB_STS_E	(0x3)		/* "E" (coherent read type) */
+
+/* When the "P" bit is set in the sk_crb_sts field of an error stack
+ * entry, the "R," "A," "H," and "I" bits are actually bits 6..3 of
+ * the address.  This macro extracts those address bits and shifts
+ * them to their proper positions, ready to be ORed in to the rest of
+ * the address (which is calculated as sk_addr << 7).
+ */
+#define PI_CRB_STS_ADDR_BITS(sts) \
+    ((sts) & (PI_CRB_STS_I | PI_CRB_STS_H) | \
+     ((sts) & (PI_CRB_STS_A | PI_CRB_STS_R)) >> 1)
+
+#ifdef _LANGUAGE_C
+/*
+ * format of error stack and error status registers.
+ */
+
+#ifdef LITTLE_ENDIAN
+
+struct err_stack_format {
+        uint64_t      sk_err_type:  3,   /* error type        */
+                        sk_suppl   :  3,   /* lowest 3 bit of supplemental */
+                        sk_t5_req  :  3,   /* RRB T5 request number */
+                        sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                        sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                        sk_crb_sts : 10,   /* status from RRB or WRB */
+                        sk_cmd     :  8,   /* message command */
+			sk_addr    : 33;   /* address */
+};
+
+#else
+
+struct err_stack_format {
+	uint64_t	sk_addr	   : 33,   /* address */
+			sk_cmd	   :  8,   /* message command */
+			sk_crb_sts : 10,   /* status from RRB or WRB */
+			sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+			sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+			sk_t5_req  :  3,   /* RRB T5 request number */
+			sk_suppl   :  3,   /* lowest 3 bit of supplemental */
+			sk_err_type:  3;   /* error type	*/
+};
+
+#endif
+
+typedef union pi_err_stack {
+        uint64_t      pi_stk_word;
+        struct  err_stack_format pi_stk_fmt;
+} pi_err_stack_t;
+
+/* Simplified version of pi_err_status0_a_u_t (PI_ERR_STATUS0_A) */
+#ifdef LITTLE_ENDIAN
+
+struct err_status0_format {
+	uint64_t	s0_err_type	:  3,	/* Encoded error cause */
+                        s0_proc_req_num :  3,   /* Request number for RRB only */
+                        s0_supplemental : 11,   /* ncoming message sup field */
+                        s0_cmd          :  8,   /* Incoming message command */
+                        s0_addr         : 37,   /* Address */
+                        s0_over_run     :  1,   /* Subsequent errors spooled */
+			s0_valid        :  1;   /* error is valid */
+};
+
+#else
+
+struct err_status0_format {
+	uint64_t	s0_valid	:  1,	/* error is valid */
+			s0_over_run	:  1,	/* Subsequent errors spooled */
+			s0_addr		: 37,	/* Address */
+			s0_cmd		:  8,	/* Incoming message command */
+			s0_supplemental : 11,	/* ncoming message sup field */
+			s0_proc_req_num :  3,	/* Request number for RRB only */
+			s0_err_type	:  3;	/* Encoded error cause */
+};
+
+#endif
+
+
+typedef union pi_err_stat0 {
+	uint64_t	pi_stat0_word;
+        struct err_status0_format pi_stat0_fmt;
+} pi_err_stat0_t;
+
+/* Simplified version of pi_err_status1_a_u_t (PI_ERR_STATUS1_A) */
+
+#ifdef LITTLE_ENDIAN
+
+struct err_status1_format {
+	 uint64_t	s1_spl_cnt : 21,   /* number spooled to memory */
+                        s1_to_cnt  :  8,   /* crb timeout counter */
+                        s1_inval_cnt:10,   /* signed invalidate counter RRB */
+                        s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                        s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                        s1_crb_sts : 10,   /* status from RRB or WRB */
+			s1_src     : 11;   /* message source */
+};
+
+#else
+
+struct err_status1_format {
+	uint64_t	s1_src	   : 11,   /* message source */
+			s1_crb_sts : 10,   /* status from RRB or WRB */
+			s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+			s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+			s1_inval_cnt:10,   /* signed invalidate counter RRB */
+			s1_to_cnt  :  8,   /* crb timeout counter */
+			s1_spl_cnt : 21;   /* number spooled to memory */
+};
+
+#endif
+
+typedef union pi_err_stat1 {
+	uint64_t	pi_stat1_word;
+	struct err_status1_format pi_stat1_fmt;
+} pi_err_stat1_t;
+#endif
+
+/* Error stack types (sk_err_type) for reads:	*/
+#define PI_ERR_RD_AERR		0	/* Read Access Error */
+#define PI_ERR_RD_PRERR         1	/* Uncached Partitial Read */
+#define PI_ERR_RD_DERR          2	/* Directory Error */
+#define PI_ERR_RD_TERR          3	/* read timeout */
+#define PI_ERR_RD_PERR		4	/* Poison Access Violation */
+#define PI_ERR_RD_NACK		5	/* Excessive NACKs	*/
+#define PI_ERR_RD_RDE		6	/* Response Data Error	*/
+#define PI_ERR_RD_PLERR		7	/* Packet Length Error */
+/* Error stack types (sk_err_type) for writes:	*/
+#define PI_ERR_WR_WERR          0	/* Write Access Error */
+#define PI_ERR_WR_PWERR         1	/* Uncached Write Error */
+#define PI_ERR_WR_TERR          3	/* write timeout */
+#define PI_ERR_WR_RDE		6	/* Response Data Error */
+#define PI_ERR_WR_PLERR		7	/* Packet Length Error */
+
+
+/* For backwards compatibility */
+#define PI_RT_COUNT	PI_RT_COUNTER    /* Real Time Counter 		    */
+#define PI_RT_EN_A	PI_RT_INT_EN_A   /* RT int for CPU A enable         */
+#define PI_RT_EN_B	PI_RT_INT_EN_B   /* RT int for CPU B enable         */
+#define PI_PROF_EN_A	PI_PROF_INT_EN_A /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B	PI_PROF_INT_EN_B /* PROF int for CPU B enable       */
+#define PI_RT_PEND_A    PI_RT_INT_PEND_A /* RT interrupt pending 	    */
+#define PI_RT_PEND_B    PI_RT_INT_PEND_B /* RT interrupt pending 	    */
+#define PI_PROF_PEND_A  PI_PROF_INT_PEND_A /* Profiling interrupt pending   */
+#define PI_PROF_PEND_B  PI_PROF_INT_PEND_B /* Profiling interrupt pending   */
+
+
+/* Bits in PI_SYSAD_ERRCHK_EN */
+#define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
+#define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
+#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
+#define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
+
+/* CALIAS values */
+#define PI_CALIAS_SIZE_0        0
+#define PI_CALIAS_SIZE_4K       1
+#define PI_CALIAS_SIZE_8K       2
+#define PI_CALIAS_SIZE_16K      3
+#define PI_CALIAS_SIZE_32K      4
+#define PI_CALIAS_SIZE_64K      5
+#define PI_CALIAS_SIZE_128K     6
+#define PI_CALIAS_SIZE_256K     7
+#define PI_CALIAS_SIZE_512K     8
+#define PI_CALIAS_SIZE_1M       9
+#define PI_CALIAS_SIZE_2M       10
+#define PI_CALIAS_SIZE_4M       11
+#define PI_CALIAS_SIZE_8M       12
+#define PI_CALIAS_SIZE_16M      13
+#define PI_CALIAS_SIZE_32M      14
+#define PI_CALIAS_SIZE_64M      15
+
+/* Fields in PI_ERR_STATUS0_[AB] */
+#define PI_ERR_ST0_VALID_MASK	0x8000000000000000
+#define PI_ERR_ST0_VALID_SHFT	63
+
+/* Fields in PI_SPURIOUS_HDR_0 */
+#define PI_SPURIOUS_HDR_VALID_MASK	0x8000000000000000
+#define PI_SPURIOUS_HDR_VALID_SHFT	63
+
+/* Fields in PI_NACK_CNT_A/B */
+#define PI_NACK_CNT_EN_SHFT	20
+#define PI_NACK_CNT_EN_MASK	0x100000
+#define PI_NACK_CNT_MASK	0x0fffff
+#define PI_NACK_CNT_MAX		0x0fffff
+
+/* Bits in PI_ERR_INT_PEND */
+#define PI_ERR_SPOOL_CMP_B	0x000000001	/* Spool end hit high water */
+#define PI_ERR_SPOOL_CMP_A	0x000000002
+#define PI_ERR_SPUR_MSG_B	0x000000004	/* Spurious message intr.   */
+#define PI_ERR_SPUR_MSG_A	0x000000008
+#define PI_ERR_WRB_TERR_B	0x000000010	/* WRB TERR		    */
+#define PI_ERR_WRB_TERR_A	0x000000020
+#define PI_ERR_WRB_WERR_B	0x000000040	/* WRB WERR 		    */
+#define PI_ERR_WRB_WERR_A	0x000000080
+#define PI_ERR_SYSSTATE_B	0x000000100	/* SysState parity error    */
+#define PI_ERR_SYSSTATE_A	0x000000200
+#define PI_ERR_SYSAD_DATA_B	0x000000400	/* SysAD data parity error  */
+#define PI_ERR_SYSAD_DATA_A	0x000000800
+#define PI_ERR_SYSAD_ADDR_B	0x000001000	/* SysAD addr parity error  */
+#define PI_ERR_SYSAD_ADDR_A	0x000002000
+#define PI_ERR_SYSCMD_DATA_B	0x000004000	/* SysCmd data parity error */
+#define PI_ERR_SYSCMD_DATA_A	0x000008000
+#define PI_ERR_SYSCMD_ADDR_B	0x000010000	/* SysCmd addr parity error */
+#define PI_ERR_SYSCMD_ADDR_A	0x000020000
+#define PI_ERR_BAD_SPOOL_B	0x000040000	/* Error spooling to memory */
+#define PI_ERR_BAD_SPOOL_A	0x000080000
+#define PI_ERR_UNCAC_UNCORR_B	0x000100000	/* Uncached uncorrectable   */
+#define PI_ERR_UNCAC_UNCORR_A	0x000200000
+#define PI_ERR_SYSSTATE_TAG_B	0x000400000	/* SysState tag parity error */
+#define PI_ERR_SYSSTATE_TAG_A	0x000800000
+#define PI_ERR_MD_UNCORR	0x001000000	/* Must be cleared in MD    */
+#define PI_ERR_SYSAD_BAD_DATA_B	0x002000000	/* SysAD Data quality bad   */
+#define PI_ERR_SYSAD_BAD_DATA_A	0x004000000
+#define PI_ERR_UE_CACHED_B	0x008000000	/* UE during cached load    */
+#define PI_ERR_UE_CACHED_A	0x010000000
+#define PI_ERR_PKT_LEN_ERR_B	0x020000000	/* Xbar data too long/short */
+#define PI_ERR_PKT_LEN_ERR_A	0x040000000
+#define PI_ERR_IRB_ERR_B	0x080000000	/* Protocol error           */
+#define PI_ERR_IRB_ERR_A	0x100000000
+#define PI_ERR_IRB_TIMEOUT_B	0x200000000	/* IRB_B got a timeout      */
+#define PI_ERR_IRB_TIMEOUT_A	0x400000000
+
+#define PI_ERR_CLEAR_ALL_A	0x554aaaaaa
+#define PI_ERR_CLEAR_ALL_B	0x2aa555555
+
+
+/*
+ * The following three macros define all possible error int pends. 
+ */
+
+#define PI_FATAL_ERR_CPU_A	(PI_ERR_SYSAD_BAD_DATA_A | \
+				 PI_ERR_SYSSTATE_TAG_A 	| \
+				 PI_ERR_BAD_SPOOL_A 	| \
+				 PI_ERR_SYSCMD_ADDR_A 	| \
+				 PI_ERR_SYSCMD_DATA_A 	| \
+				 PI_ERR_SYSAD_ADDR_A 	| \
+				 PI_ERR_SYSAD_DATA_A	| \
+				 PI_ERR_SYSSTATE_A)
+
+#define PI_MISC_ERR_CPU_A	(PI_ERR_IRB_TIMEOUT_A   | \
+				 PI_ERR_IRB_ERR_A       | \
+				 PI_ERR_PKT_LEN_ERR_A   | \
+				 PI_ERR_UE_CACHED_A     | \
+				 PI_ERR_UNCAC_UNCORR_A 	| \
+				 PI_ERR_WRB_WERR_A 	| \
+				 PI_ERR_WRB_TERR_A 	| \
+				 PI_ERR_SPUR_MSG_A 	| \
+				 PI_ERR_SPOOL_CMP_A)
+
+#define PI_FATAL_ERR_CPU_B	(PI_ERR_SYSAD_BAD_DATA_B | \
+				 PI_ERR_SYSSTATE_TAG_B 	| \
+				 PI_ERR_BAD_SPOOL_B 	| \
+				 PI_ERR_SYSCMD_ADDR_B 	| \
+				 PI_ERR_SYSCMD_DATA_B 	| \
+				 PI_ERR_SYSAD_ADDR_B 	| \
+				 PI_ERR_SYSAD_DATA_B	| \
+				 PI_ERR_SYSSTATE_B)
+
+#define PI_MISC_ERR_CPU_B 	(PI_ERR_IRB_TIMEOUT_B   | \
+				 PI_ERR_IRB_ERR_B       | \
+				 PI_ERR_PKT_LEN_ERR_B   | \
+				 PI_ERR_UE_CACHED_B     | \
+				 PI_ERR_UNCAC_UNCORR_B  | \
+				 PI_ERR_WRB_WERR_B 	| \
+				 PI_ERR_WRB_TERR_B 	| \
+				 PI_ERR_SPUR_MSG_B 	| \
+				 PI_ERR_SPOOL_CMP_B)
+
+#define PI_ERR_GENERIC	(PI_ERR_MD_UNCORR)
+
+/* Values for PI_MAX_CRB_TIMEOUT and PI_CRB_SFACTOR */
+#define PMCT_MAX	0xff
+#define PCS_MAX		0xffffff
+
+/* pi_err_status0_a_u_t address shift */
+#define ERR_STAT0_ADDR_SHFT     3
+
+/* PI error read/write bit (RRB == 0, WRB == 1)	*/
+/* pi_err_status1_a_u_t.pi_err_status1_a_fld_s.esa_wrb */
+#define PI_ERR_RRB	0
+#define PI_ERR_WRB	1
+
+/* Error stack address shift, for use with pi_stk_fmt.sk_addr */
+#define ERR_STK_ADDR_SHFT	3
+
+#endif /* _ASM_SN_SN1_HUBPI_NEXT_H */
diff --git a/include/asm-ia64/sn/sn1/hubxb.h b/include/asm-ia64/sn/sn1/hubxb.h
new file mode 100644
index 000000000..21044fdfd
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubxb.h
@@ -0,0 +1,1289 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBXB_H
+#define _ASM_SN_SN1_HUBXB_H
+
+/************************************************************************
+ *                                                                      *
+ *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
+ *                                                                      *
+ * This file is created by an automated script. Any (minimal) changes   *
+ * made manually to this  file should be made with care.                *
+ *                                                                      *
+ *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
+ *                                                                      *
+ ************************************************************************/
+
+
+#define    XB_PARMS                  0x00700000    /*
+                                                    * Controls
+                                                    * crossbar-wide
+                                                    * parameters.
+                                                    */
+
+
+
+#define    XB_SLOW_GNT               0x00700008    /*
+                                                    * Controls wavefront
+                                                    * arbiter grant
+                                                    * frequency, used to
+                                                    * slow XB grants
+                                                    */
+
+
+
+#define    XB_SPEW_CONTROL           0x00700010    /*
+                                                    * Controls spew
+                                                    * settings (debug
+                                                    * only).
+                                                    */
+
+
+
+#define    XB_IOQ_ARB_TRIGGER        0x00700018    /*
+                                                    * Controls IOQ
+                                                    * trigger level
+                                                    */
+
+
+
+#define    XB_FIRST_ERROR            0x00700090    /*
+                                                    * Records the first
+                                                    * crossbar error
+                                                    * seen.
+                                                    */
+
+
+
+#define    XB_POQ0_ERROR             0x00700020    /*
+                                                    * POQ0 error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_PIQ0_ERROR             0x00700028    /*
+                                                    * PIQ0 error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_POQ1_ERROR             0x00700030    /*
+                                                    * POQ1 error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_PIQ1_ERROR             0x00700038    /*
+                                                    * PIQ1 error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MP0_ERROR              0x00700040    /*
+                                                    * MOQ for PI0 error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MP1_ERROR              0x00700048    /*
+                                                    * MOQ for PI1 error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MMQ_ERROR              0x00700050    /*
+                                                    * MOQ for misc. (LB,
+                                                    * NI, II) error
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MIQ_ERROR              0x00700058    /*
+                                                    * MIQ error register,
+                                                    * addtional MIQ
+                                                    * errors are logged
+                                                    * in MD &quot;Input
+                                                    * Error
+                                                    * Registers&quot;.
+                                                    */
+
+
+
+#define    XB_NOQ_ERROR              0x00700060    /* NOQ error register.    */
+
+
+
+#define    XB_NIQ_ERROR              0x00700068    /* NIQ error register.    */
+
+
+
+#define    XB_IOQ_ERROR              0x00700070    /* IOQ error register.    */
+
+
+
+#define    XB_IIQ_ERROR              0x00700078    /* IIQ error register.    */
+
+
+
+#define    XB_LOQ_ERROR              0x00700080    /* LOQ error register.    */
+
+
+
+#define    XB_LIQ_ERROR              0x00700088    /* LIQ error register.    */
+
+
+
+#define    XB_DEBUG_DATA_CTL         0x00700098    /*
+                                                    * Debug Datapath
+                                                    * Select
+                                                    */
+
+
+
+#define    XB_DEBUG_ARB_CTL          0x007000A0    /*
+                                                    * XB master debug
+                                                    * control
+                                                    */
+
+
+
+#define    XB_POQ0_ERROR_CLEAR       0x00700120    /*
+                                                    * Clears
+                                                    * XB_POQ0_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_PIQ0_ERROR_CLEAR       0x00700128    /*
+                                                    * Clears
+                                                    * XB_PIQ0_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_POQ1_ERROR_CLEAR       0x00700130    /*
+                                                    * Clears
+                                                    * XB_POQ1_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_PIQ1_ERROR_CLEAR       0x00700138    /*
+                                                    * Clears
+                                                    * XB_PIQ1_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MP0_ERROR_CLEAR        0x00700140    /*
+                                                    * Clears XB_MP0_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MP1_ERROR_CLEAR        0x00700148    /*
+                                                    * Clears XB_MP1_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_MMQ_ERROR_CLEAR        0x00700150    /*
+                                                    * Clears XB_MMQ_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_XM_MIQ_ERROR_CLEAR     0x00700158    /*
+                                                    * Clears XB_MIQ_ERROR
+                                                    * register
+                                                    */
+
+
+
+#define    XB_NOQ_ERROR_CLEAR        0x00700160    /*
+                                                    * Clears XB_NOQ_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_NIQ_ERROR_CLEAR        0x00700168    /*
+                                                    * Clears XB_NIQ_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_IOQ_ERROR_CLEAR        0x00700170    /*
+                                                    * Clears XB_IOQ
+                                                    * _ERROR register.
+                                                    */
+
+
+
+#define    XB_IIQ_ERROR_CLEAR        0x00700178    /*
+                                                    * Clears XB_IIQ
+                                                    * _ERROR register.
+                                                    */
+
+
+
+#define    XB_LOQ_ERROR_CLEAR        0x00700180    /*
+                                                    * Clears XB_LOQ_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_LIQ_ERROR_CLEAR        0x00700188    /*
+                                                    * Clears XB_LIQ_ERROR
+                                                    * register.
+                                                    */
+
+
+
+#define    XB_FIRST_ERROR_CLEAR      0x00700190    /*
+                                                    * Clears
+                                                    * XB_FIRST_ERROR
+                                                    * register
+                                                    */
+
+
+
+
+
+#ifdef _LANGUAGE_C
+
+/************************************************************************
+ *                                                                      *
+ *  Access to parameters which control various aspects of the           *
+ * crossbar's operation.                                                *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_parms_u {
+	bdrkreg_t	xb_parms_regval;
+	struct  {
+		bdrkreg_t	p_byp_en                  :	 1;
+                bdrkreg_t       p_rsrvd_1                 :      3;
+                bdrkreg_t       p_age_wrap                :      8;
+                bdrkreg_t       p_deadlock_to_wrap        :     20;
+                bdrkreg_t       p_tail_to_wrap            :     20;
+                bdrkreg_t       p_rsrvd                   :     12;
+	} xb_parms_fld_s;
+} xb_parms_u_t;
+
+#else
+
+typedef union xb_parms_u {
+	bdrkreg_t	xb_parms_regval;
+	struct	{
+		bdrkreg_t	p_rsrvd			  :	12;
+		bdrkreg_t	p_tail_to_wrap		  :	20;
+		bdrkreg_t	p_deadlock_to_wrap	  :	20;
+		bdrkreg_t	p_age_wrap		  :	 8;
+		bdrkreg_t	p_rsrvd_1		  :	 3;
+		bdrkreg_t	p_byp_en		  :	 1;
+	} xb_parms_fld_s;
+} xb_parms_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Sets the period of wavefront grants given to each unit. The         *
+ * register's value corresponds to the number of cycles between each    *
+ * wavefront grant opportunity given to the requesting unit. If set     *
+ * to 0xF, no grants are given to this unit. If set to 0xE, the unit    *
+ * is granted at the slowest rate (sometimes called "molasses mode").   *
+ * This feature can be used to apply backpressure to a unit's output    *
+ * queue(s). The setting does not affect bypass grants.                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_slow_gnt_u {
+	bdrkreg_t	xb_slow_gnt_regval;
+	struct  {
+		bdrkreg_t	sg_lb_slow_gnt            :	 4;
+                bdrkreg_t       sg_ii_slow_gnt            :      4;
+                bdrkreg_t       sg_ni_slow_gnt            :      4;
+                bdrkreg_t       sg_mmq_slow_gnt           :      4;
+                bdrkreg_t       sg_mp1_slow_gnt           :      4;
+                bdrkreg_t       sg_mp0_slow_gnt           :      4;
+                bdrkreg_t       sg_pi1_slow_gnt           :      4;
+                bdrkreg_t       sg_pi0_slow_gnt           :      4;
+                bdrkreg_t       sg_rsrvd                  :     32;
+	} xb_slow_gnt_fld_s;
+} xb_slow_gnt_u_t;
+
+#else
+
+typedef union xb_slow_gnt_u {
+	bdrkreg_t	xb_slow_gnt_regval;
+	struct	{
+		bdrkreg_t	sg_rsrvd		  :	32;
+		bdrkreg_t	sg_pi0_slow_gnt		  :	 4;
+		bdrkreg_t	sg_pi1_slow_gnt		  :	 4;
+		bdrkreg_t	sg_mp0_slow_gnt		  :	 4;
+		bdrkreg_t	sg_mp1_slow_gnt		  :	 4;
+		bdrkreg_t	sg_mmq_slow_gnt		  :	 4;
+		bdrkreg_t	sg_ni_slow_gnt		  :	 4;
+		bdrkreg_t	sg_ii_slow_gnt		  :	 4;
+		bdrkreg_t	sg_lb_slow_gnt		  :	 4;
+	} xb_slow_gnt_fld_s;
+} xb_slow_gnt_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Enables snooping of internal crossbar traffic by spewing all        *
+ * traffic across a selected crossbar point to the PI1 port. Only one   *
+ * bit should be set at any one time, and any bit set will preclude     *
+ * using the P1 for anything but a debug connection.                    *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_spew_control_u {
+	bdrkreg_t	xb_spew_control_regval;
+	struct  {
+		bdrkreg_t	sc_snoop_liq              :	 1;
+                bdrkreg_t       sc_snoop_iiq              :      1;
+                bdrkreg_t       sc_snoop_niq              :      1;
+                bdrkreg_t       sc_snoop_miq              :      1;
+                bdrkreg_t       sc_snoop_piq0             :      1;
+                bdrkreg_t       sc_snoop_loq              :      1;
+                bdrkreg_t       sc_snoop_ioq              :      1;
+                bdrkreg_t       sc_snoop_noq              :      1;
+                bdrkreg_t       sc_snoop_mmq              :      1;
+                bdrkreg_t       sc_snoop_mp0              :      1;
+                bdrkreg_t       sc_snoop_poq0             :      1;
+                bdrkreg_t       sc_rsrvd                  :     53;
+	} xb_spew_control_fld_s;
+} xb_spew_control_u_t;
+
+#else
+
+typedef union xb_spew_control_u {
+	bdrkreg_t	xb_spew_control_regval;
+	struct	{
+		bdrkreg_t	sc_rsrvd		  :	53;
+		bdrkreg_t	sc_snoop_poq0		  :	 1;
+		bdrkreg_t	sc_snoop_mp0		  :	 1;
+		bdrkreg_t	sc_snoop_mmq		  :	 1;
+		bdrkreg_t	sc_snoop_noq		  :	 1;
+		bdrkreg_t	sc_snoop_ioq		  :	 1;
+		bdrkreg_t	sc_snoop_loq		  :	 1;
+		bdrkreg_t	sc_snoop_piq0		  :	 1;
+		bdrkreg_t	sc_snoop_miq		  :	 1;
+		bdrkreg_t	sc_snoop_niq		  :	 1;
+		bdrkreg_t	sc_snoop_iiq		  :	 1;
+		bdrkreg_t	sc_snoop_liq		  :	 1;
+	} xb_spew_control_fld_s;
+} xb_spew_control_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Number of clocks the IOQ will wait before beginning XB              *
+ * arbitration. This is set so that the slower IOQ data rate can        *
+ * catch up up with the XB data rate in the IOQ buffer.                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_ioq_arb_trigger_u {
+	bdrkreg_t	xb_ioq_arb_trigger_regval;
+	struct  {
+		bdrkreg_t	iat_ioq_arb_trigger       :	 4;
+	        bdrkreg_t       iat_rsrvd                 :     60;
+	} xb_ioq_arb_trigger_fld_s;
+} xb_ioq_arb_trigger_u_t;
+
+#else
+
+typedef union xb_ioq_arb_trigger_u {
+	bdrkreg_t	xb_ioq_arb_trigger_regval;
+	struct	{
+		bdrkreg_t	iat_rsrvd		  :	60;
+		bdrkreg_t	iat_ioq_arb_trigger	  :	 4;
+	} xb_ioq_arb_trigger_fld_s;
+} xb_ioq_arb_trigger_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by POQ0.Can be written to test software, will   *
+ * cause an interrupt.                                                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_poq0_error_u {
+	bdrkreg_t	xb_poq0_error_regval;
+	struct  {
+		bdrkreg_t	pe_invalid_xsel           :	 2;
+                bdrkreg_t       pe_rsrvd_3                :      2;
+                bdrkreg_t       pe_overflow               :      2;
+                bdrkreg_t       pe_rsrvd_2                :      2;
+                bdrkreg_t       pe_underflow              :      2;
+                bdrkreg_t       pe_rsrvd_1                :      2;
+                bdrkreg_t       pe_tail_timeout           :      2;
+                bdrkreg_t       pe_unused                 :      6;
+                bdrkreg_t       pe_rsrvd                  :     44;
+	} xb_poq0_error_fld_s;
+} xb_poq0_error_u_t;
+
+#else
+
+typedef union xb_poq0_error_u {
+	bdrkreg_t	xb_poq0_error_regval;
+	struct	{
+		bdrkreg_t	pe_rsrvd		  :	44;
+		bdrkreg_t	pe_unused		  :	 6;
+		bdrkreg_t	pe_tail_timeout		  :	 2;
+		bdrkreg_t	pe_rsrvd_1		  :	 2;
+		bdrkreg_t	pe_underflow		  :	 2;
+		bdrkreg_t	pe_rsrvd_2		  :	 2;
+		bdrkreg_t	pe_overflow		  :	 2;
+		bdrkreg_t	pe_rsrvd_3		  :	 2;
+		bdrkreg_t	pe_invalid_xsel		  :	 2;
+	} xb_poq0_error_fld_s;
+} xb_poq0_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
+ * precludes PIQ underflow.                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_piq0_error_u {
+	bdrkreg_t	xb_piq0_error_regval;
+	struct  {
+		bdrkreg_t	pe_overflow               :	 2;
+                bdrkreg_t       pe_rsrvd_1                :      2;
+                bdrkreg_t       pe_deadlock_timeout       :      2;
+                bdrkreg_t       pe_rsrvd                  :     58;
+	} xb_piq0_error_fld_s;
+} xb_piq0_error_u_t;
+
+#else
+
+typedef union xb_piq0_error_u {
+	bdrkreg_t	xb_piq0_error_regval;
+	struct	{
+		bdrkreg_t	pe_rsrvd		  :	58;
+		bdrkreg_t	pe_deadlock_timeout	  :	 2;
+		bdrkreg_t	pe_rsrvd_1		  :	 2;
+		bdrkreg_t	pe_overflow		  :	 2;
+	} xb_piq0_error_fld_s;
+} xb_piq0_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
+ * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
+ * errors are possible.                                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_mp0_error_u {
+	bdrkreg_t	xb_mp0_error_regval;
+	struct  {
+		bdrkreg_t	me_rsrvd_3                :	 4;
+                bdrkreg_t       me_overflow               :      2;
+                bdrkreg_t       me_rsrvd_2                :      2;
+                bdrkreg_t       me_underflow              :      2;
+                bdrkreg_t       me_rsrvd_1                :      2;
+                bdrkreg_t       me_tail_timeout           :      2;
+                bdrkreg_t       me_rsrvd                  :     50;
+	} xb_mp0_error_fld_s;
+} xb_mp0_error_u_t;
+
+#else
+
+typedef union xb_mp0_error_u {
+	bdrkreg_t	xb_mp0_error_regval;
+	struct	{
+		bdrkreg_t	me_rsrvd		  :	50;
+		bdrkreg_t	me_tail_timeout		  :	 2;
+		bdrkreg_t	me_rsrvd_1		  :	 2;
+		bdrkreg_t	me_underflow		  :	 2;
+		bdrkreg_t	me_rsrvd_2		  :	 2;
+		bdrkreg_t	me_overflow		  :	 2;
+		bdrkreg_t	me_rsrvd_3		  :	 4;
+	} xb_mp0_error_fld_s;
+} xb_mp0_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by MIQ.                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_miq_error_u {
+	bdrkreg_t	xb_miq_error_regval;
+	struct  {
+		bdrkreg_t	me_rsrvd_1                :	 4;
+                bdrkreg_t       me_deadlock_timeout       :      4;
+                bdrkreg_t       me_rsrvd                  :     56;
+	} xb_miq_error_fld_s;
+} xb_miq_error_u_t;
+
+#else
+
+typedef union xb_miq_error_u {
+	bdrkreg_t	xb_miq_error_regval;
+	struct	{
+		bdrkreg_t	me_rsrvd		  :	56;
+		bdrkreg_t	me_deadlock_timeout	  :	 4;
+		bdrkreg_t	me_rsrvd_1		  :	 4;
+	} xb_miq_error_fld_s;
+} xb_miq_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by NOQ.                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_noq_error_u {
+	bdrkreg_t	xb_noq_error_regval;
+	struct  {
+		bdrkreg_t	ne_rsvd                   :	 4;
+                bdrkreg_t       ne_overflow               :      4;
+                bdrkreg_t       ne_underflow              :      4;
+                bdrkreg_t       ne_tail_timeout           :      4;
+                bdrkreg_t       ne_rsrvd                  :     48;
+	} xb_noq_error_fld_s;
+} xb_noq_error_u_t;
+
+#else
+
+typedef union xb_noq_error_u {
+	bdrkreg_t	xb_noq_error_regval;
+	struct	{
+		bdrkreg_t	ne_rsrvd		  :	48;
+		bdrkreg_t	ne_tail_timeout		  :	 4;
+		bdrkreg_t	ne_underflow		  :	 4;
+		bdrkreg_t	ne_overflow		  :	 4;
+		bdrkreg_t	ne_rsvd			  :	 4;
+	} xb_noq_error_fld_s;
+} xb_noq_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by LOQ.                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_loq_error_u {
+	bdrkreg_t	xb_loq_error_regval;
+	struct  {
+		bdrkreg_t	le_invalid_xsel           :	 2;
+                bdrkreg_t       le_rsrvd_1                :      6;
+                bdrkreg_t       le_underflow              :      2;
+                bdrkreg_t       le_rsvd                   :      2;
+                bdrkreg_t       le_tail_timeout           :      2;
+                bdrkreg_t       le_rsrvd                  :     50;
+	} xb_loq_error_fld_s;
+} xb_loq_error_u_t;
+
+#else
+
+typedef union xb_loq_error_u {
+	bdrkreg_t	xb_loq_error_regval;
+	struct	{
+		bdrkreg_t	le_rsrvd		  :	50;
+		bdrkreg_t	le_tail_timeout		  :	 2;
+		bdrkreg_t	le_rsvd			  :	 2;
+		bdrkreg_t	le_underflow		  :	 2;
+		bdrkreg_t	le_rsrvd_1		  :	 6;
+		bdrkreg_t	le_invalid_xsel		  :	 2;
+	} xb_loq_error_fld_s;
+} xb_loq_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by LIQ. Note that the LIQ only records errors   *
+ * for the request channel. The reply channel can never deadlock or     *
+ * overflow because it does not have hardware flow control.             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_liq_error_u {
+	bdrkreg_t	xb_liq_error_regval;
+	struct  {
+		bdrkreg_t	le_overflow               :	 1;
+                bdrkreg_t       le_rsrvd_1                :      3;
+                bdrkreg_t       le_deadlock_timeout       :      1;
+                bdrkreg_t       le_rsrvd                  :     59;
+	} xb_liq_error_fld_s;
+} xb_liq_error_u_t;
+
+#else
+
+typedef union xb_liq_error_u {
+	bdrkreg_t	xb_liq_error_regval;
+	struct	{
+		bdrkreg_t	le_rsrvd		  :	59;
+		bdrkreg_t	le_deadlock_timeout	  :	 1;
+		bdrkreg_t	le_rsrvd_1		  :	 3;
+		bdrkreg_t	le_overflow		  :	 1;
+	} xb_liq_error_fld_s;
+} xb_liq_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  First error is latched whenever the Valid bit is clear and an       *
+ * error occurs. Any valid bit on in this register causes an            *
+ * interrupt to PI0 and PI1. This interrupt bit will persist until      *
+ * the specific error register to capture the error is cleared, then    *
+ * the FIRST_ERROR register is cleared (in that oder.) The              *
+ * FIRST_ERROR register is not writable, but will be set when any of    *
+ * the corresponding error registers are written by software.           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_first_error_u {
+	bdrkreg_t	xb_first_error_regval;
+	struct  {
+		bdrkreg_t	fe_type                   :	 4;
+                bdrkreg_t       fe_channel                :      4;
+                bdrkreg_t       fe_source                 :      4;
+                bdrkreg_t       fe_valid                  :      1;
+                bdrkreg_t       fe_rsrvd                  :     51;
+	} xb_first_error_fld_s;
+} xb_first_error_u_t;
+
+#else
+
+typedef union xb_first_error_u {
+	bdrkreg_t	xb_first_error_regval;
+	struct	{
+		bdrkreg_t	fe_rsrvd		  :	51;
+		bdrkreg_t	fe_valid		  :	 1;
+		bdrkreg_t	fe_source		  :	 4;
+		bdrkreg_t	fe_channel		  :	 4;
+		bdrkreg_t	fe_type			  :	 4;
+	} xb_first_error_fld_s;
+} xb_first_error_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Controls DEBUG_DATA mux setting. Allows user to watch the output    *
+ * of any OQ or input of any IQ on the DEBUG port. Note that bits       *
+ * 13:0 are one-hot. If more than one bit is set in [13:0], the debug   *
+ * output is undefined. Details on the debug output lines can be        *
+ * found in the XB chapter of the Bedrock Interface Specification.      *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_debug_data_ctl_u {
+	bdrkreg_t	xb_debug_data_ctl_regval;
+	struct  {
+		bdrkreg_t	ddc_observe_liq_traffic   :	 1;
+                bdrkreg_t       ddc_observe_iiq_traffic   :      1;
+                bdrkreg_t       ddc_observe_niq_traffic   :      1;
+                bdrkreg_t       ddc_observe_miq_traffic   :      1;
+                bdrkreg_t       ddc_observe_piq1_traffic  :      1;
+                bdrkreg_t       ddc_observe_piq0_traffic  :      1;
+                bdrkreg_t       ddc_observe_loq_traffic   :      1;
+                bdrkreg_t       ddc_observe_ioq_traffic   :      1;
+                bdrkreg_t       ddc_observe_noq_traffic   :      1;
+                bdrkreg_t       ddc_observe_mp1_traffic   :      1;
+                bdrkreg_t       ddc_observe_mp0_traffic   :      1;
+                bdrkreg_t       ddc_observe_mmq_traffic   :      1;
+                bdrkreg_t       ddc_observe_poq1_traffic  :      1;
+                bdrkreg_t       ddc_observe_poq0_traffic  :      1;
+                bdrkreg_t       ddc_observe_source_field  :      1;
+                bdrkreg_t       ddc_observe_lodata        :      1;
+                bdrkreg_t       ddc_rsrvd                 :     48;
+	} xb_debug_data_ctl_fld_s;
+} xb_debug_data_ctl_u_t;
+
+#else
+
+typedef union xb_debug_data_ctl_u {
+	bdrkreg_t	xb_debug_data_ctl_regval;
+	struct	{
+		bdrkreg_t	ddc_rsrvd		  :	48;
+		bdrkreg_t	ddc_observe_lodata	  :	 1;
+		bdrkreg_t	ddc_observe_source_field  :	 1;
+		bdrkreg_t	ddc_observe_poq0_traffic  :	 1;
+		bdrkreg_t	ddc_observe_poq1_traffic  :	 1;
+		bdrkreg_t	ddc_observe_mmq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_mp0_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_mp1_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_noq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_ioq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_loq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_piq0_traffic  :	 1;
+		bdrkreg_t	ddc_observe_piq1_traffic  :	 1;
+		bdrkreg_t	ddc_observe_miq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_niq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_iiq_traffic	  :	 1;
+		bdrkreg_t	ddc_observe_liq_traffic	  :	 1;
+	} xb_debug_data_ctl_fld_s;
+} xb_debug_data_ctl_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Controls debug mux setting for XB Input/Output Queues and           *
+ * Arbiter. Can select one of the following values. Details on the      *
+ * debug output lines can be found in the XB chapter of the Bedrock     *
+ * Interface Specification.                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_debug_arb_ctl_u {
+	bdrkreg_t	xb_debug_arb_ctl_regval;
+	struct  {
+		bdrkreg_t	dac_xb_debug_select       :	 3;
+		bdrkreg_t       dac_rsrvd                 :     61;
+	} xb_debug_arb_ctl_fld_s;
+} xb_debug_arb_ctl_u_t;
+
+#else
+
+typedef union xb_debug_arb_ctl_u {
+        bdrkreg_t       xb_debug_arb_ctl_regval;
+        struct  {
+                bdrkreg_t       dac_rsrvd                 :     61;
+                bdrkreg_t       dac_xb_debug_select       :      3;
+        } xb_debug_arb_ctl_fld_s;
+} xb_debug_arb_ctl_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by POQ0.Can be written to test software, will   *
+ * cause an interrupt.                                                  *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_poq0_error_clear_u {
+	bdrkreg_t	xb_poq0_error_clear_regval;
+	struct  {
+		bdrkreg_t	pec_invalid_xsel          :	 2;
+                bdrkreg_t       pec_rsrvd_3               :      2;
+                bdrkreg_t       pec_overflow              :      2;
+                bdrkreg_t       pec_rsrvd_2               :      2;
+                bdrkreg_t       pec_underflow             :      2;
+                bdrkreg_t       pec_rsrvd_1               :      2;
+                bdrkreg_t       pec_tail_timeout          :      2;
+                bdrkreg_t       pec_unused                :      6;
+                bdrkreg_t       pec_rsrvd                 :     44;
+	} xb_poq0_error_clear_fld_s;
+} xb_poq0_error_clear_u_t;
+
+#else
+
+typedef union xb_poq0_error_clear_u {
+	bdrkreg_t	xb_poq0_error_clear_regval;
+	struct	{
+		bdrkreg_t	pec_rsrvd		  :	44;
+		bdrkreg_t	pec_unused		  :	 6;
+		bdrkreg_t	pec_tail_timeout	  :	 2;
+		bdrkreg_t	pec_rsrvd_1		  :	 2;
+		bdrkreg_t	pec_underflow		  :	 2;
+		bdrkreg_t	pec_rsrvd_2		  :	 2;
+		bdrkreg_t	pec_overflow		  :	 2;
+		bdrkreg_t	pec_rsrvd_3		  :	 2;
+		bdrkreg_t	pec_invalid_xsel	  :	 2;
+	} xb_poq0_error_clear_fld_s;
+} xb_poq0_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
+ * precludes PIQ underflow.                                             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_piq0_error_clear_u {
+	bdrkreg_t	xb_piq0_error_clear_regval;
+	struct  {
+		bdrkreg_t	pec_overflow              :	 2;
+                bdrkreg_t       pec_rsrvd_1               :      2;
+                bdrkreg_t       pec_deadlock_timeout      :      2;
+                bdrkreg_t       pec_rsrvd                 :     58;
+	} xb_piq0_error_clear_fld_s;
+} xb_piq0_error_clear_u_t;
+
+#else
+
+typedef union xb_piq0_error_clear_u {
+	bdrkreg_t	xb_piq0_error_clear_regval;
+	struct	{
+		bdrkreg_t	pec_rsrvd		  :	58;
+		bdrkreg_t	pec_deadlock_timeout	  :	 2;
+		bdrkreg_t	pec_rsrvd_1		  :	 2;
+		bdrkreg_t	pec_overflow		  :	 2;
+	} xb_piq0_error_clear_fld_s;
+} xb_piq0_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
+ * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
+ * errors are possible.                                                 *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_mp0_error_clear_u {
+	bdrkreg_t	xb_mp0_error_clear_regval;
+	struct  {
+		bdrkreg_t	mec_rsrvd_3               :	 4;
+                bdrkreg_t       mec_overflow              :      2;
+                bdrkreg_t       mec_rsrvd_2               :      2;
+                bdrkreg_t       mec_underflow             :      2;
+                bdrkreg_t       mec_rsrvd_1               :      2;
+                bdrkreg_t       mec_tail_timeout          :      2;
+                bdrkreg_t       mec_rsrvd                 :     50;
+	} xb_mp0_error_clear_fld_s;
+} xb_mp0_error_clear_u_t;
+
+#else
+
+typedef union xb_mp0_error_clear_u {
+	bdrkreg_t	xb_mp0_error_clear_regval;
+	struct	{
+		bdrkreg_t	mec_rsrvd		  :	50;
+		bdrkreg_t	mec_tail_timeout	  :	 2;
+		bdrkreg_t	mec_rsrvd_1		  :	 2;
+		bdrkreg_t	mec_underflow		  :	 2;
+		bdrkreg_t	mec_rsrvd_2		  :	 2;
+		bdrkreg_t	mec_overflow		  :	 2;
+		bdrkreg_t	mec_rsrvd_3		  :	 4;
+	} xb_mp0_error_clear_fld_s;
+} xb_mp0_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by MIQ.                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_xm_miq_error_clear_u {
+	bdrkreg_t	xb_xm_miq_error_clear_regval;
+	struct  {
+		bdrkreg_t	xmec_rsrvd_1              :	 4;
+                bdrkreg_t       xmec_deadlock_timeout     :      4;
+                bdrkreg_t       xmec_rsrvd                :     56;
+	} xb_xm_miq_error_clear_fld_s;
+} xb_xm_miq_error_clear_u_t;
+
+#else
+
+typedef union xb_xm_miq_error_clear_u {
+	bdrkreg_t	xb_xm_miq_error_clear_regval;
+	struct	{
+		bdrkreg_t	xmec_rsrvd		  :	56;
+		bdrkreg_t	xmec_deadlock_timeout	  :	 4;
+		bdrkreg_t	xmec_rsrvd_1		  :	 4;
+	} xb_xm_miq_error_clear_fld_s;
+} xb_xm_miq_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by NOQ.                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_noq_error_clear_u {
+	bdrkreg_t	xb_noq_error_clear_regval;
+	struct  {
+		bdrkreg_t	nec_rsvd                  :	 4;
+                bdrkreg_t       nec_overflow              :      4;
+                bdrkreg_t       nec_underflow             :      4;
+                bdrkreg_t       nec_tail_timeout          :      4;
+                bdrkreg_t       nec_rsrvd                 :     48;
+	} xb_noq_error_clear_fld_s;
+} xb_noq_error_clear_u_t;
+
+#else
+
+typedef union xb_noq_error_clear_u {
+	bdrkreg_t	xb_noq_error_clear_regval;
+	struct	{
+		bdrkreg_t	nec_rsrvd		  :	48;
+		bdrkreg_t	nec_tail_timeout	  :	 4;
+		bdrkreg_t	nec_underflow		  :	 4;
+		bdrkreg_t	nec_overflow		  :	 4;
+		bdrkreg_t	nec_rsvd		  :	 4;
+	} xb_noq_error_clear_fld_s;
+} xb_noq_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by LOQ.                                         *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_loq_error_clear_u {
+	bdrkreg_t	xb_loq_error_clear_regval;
+	struct  {
+		bdrkreg_t	lec_invalid_xsel          :	 2;
+                bdrkreg_t       lec_rsrvd_1               :      6;
+                bdrkreg_t       lec_underflow             :      2;
+                bdrkreg_t       lec_rsvd                  :      2;
+                bdrkreg_t       lec_tail_timeout          :      2;
+                bdrkreg_t       lec_rsrvd                 :     50;
+	} xb_loq_error_clear_fld_s;
+} xb_loq_error_clear_u_t;
+
+#else
+
+typedef union xb_loq_error_clear_u {
+	bdrkreg_t	xb_loq_error_clear_regval;
+	struct	{
+		bdrkreg_t	lec_rsrvd		  :	50;
+		bdrkreg_t	lec_tail_timeout	  :	 2;
+		bdrkreg_t	lec_rsvd		  :	 2;
+		bdrkreg_t	lec_underflow		  :	 2;
+		bdrkreg_t	lec_rsrvd_1		  :	 6;
+		bdrkreg_t	lec_invalid_xsel	  :	 2;
+	} xb_loq_error_clear_fld_s;
+} xb_loq_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  Records errors seen by LIQ. Note that the LIQ only records errors   *
+ * for the request channel. The reply channel can never deadlock or     *
+ * overflow because it does not have hardware flow control.             *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_liq_error_clear_u {
+	bdrkreg_t	xb_liq_error_clear_regval;
+	struct  {
+		bdrkreg_t	lec_overflow              :	 1;
+                bdrkreg_t       lec_rsrvd_1               :      3;
+                bdrkreg_t       lec_deadlock_timeout      :      1;
+                bdrkreg_t       lec_rsrvd                 :     59;
+	} xb_liq_error_clear_fld_s;
+} xb_liq_error_clear_u_t;
+
+#else
+
+typedef union xb_liq_error_clear_u {
+        bdrkreg_t       xb_liq_error_clear_regval;
+        struct  {
+                bdrkreg_t       lec_rsrvd                 :     59;
+                bdrkreg_t       lec_deadlock_timeout      :      1;
+                bdrkreg_t       lec_rsrvd_1               :      3;
+                bdrkreg_t       lec_overflow              :      1;
+        } xb_liq_error_clear_fld_s;
+} xb_liq_error_clear_u_t;
+
+#endif
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  First error is latched whenever the Valid bit is clear and an       *
+ * error occurs. Any valid bit on in this register causes an            *
+ * interrupt to PI0 and PI1. This interrupt bit will persist until      *
+ * the specific error register to capture the error is cleared, then    *
+ * the FIRST_ERROR register is cleared (in that oder.) The              *
+ * FIRST_ERROR register is not writable, but will be set when any of    *
+ * the corresponding error registers are written by software.           *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xb_first_error_clear_u {
+	bdrkreg_t	xb_first_error_clear_regval;
+	struct  {
+		bdrkreg_t	fec_type                  :	 4;
+                bdrkreg_t       fec_channel               :      4;
+                bdrkreg_t       fec_source                :      4;
+                bdrkreg_t       fec_valid                 :      1;
+                bdrkreg_t       fec_rsrvd                 :     51;
+	} xb_first_error_clear_fld_s;
+} xb_first_error_clear_u_t;
+
+#else
+
+typedef union xb_first_error_clear_u {
+	bdrkreg_t	xb_first_error_clear_regval;
+	struct	{
+		bdrkreg_t	fec_rsrvd		  :	51;
+		bdrkreg_t	fec_valid		  :	 1;
+		bdrkreg_t	fec_source		  :	 4;
+		bdrkreg_t	fec_channel		  :	 4;
+		bdrkreg_t	fec_type		  :	 4;
+	} xb_first_error_clear_fld_s;
+} xb_first_error_clear_u_t;
+
+#endif
+
+
+
+
+
+
+#endif /* _LANGUAGE_C */
+
+/************************************************************************
+ *                                                                      *
+ * The following defines were not formed into structures                *
+ *                                                                      *
+ * This could be because the document did not contain details of the    *
+ * register, or because the automated script did not recognize the      *
+ * register details in the documentation. If these register need        *
+ * structure definition, please create them manually                    *
+ *                                                                      *
+ *           XB_POQ1_ERROR            0x700030                          *
+ *           XB_PIQ1_ERROR            0x700038                          *
+ *           XB_MP1_ERROR             0x700048                          *
+ *           XB_MMQ_ERROR             0x700050                          *
+ *           XB_NIQ_ERROR             0x700068                          *
+ *           XB_IOQ_ERROR             0x700070                          *
+ *           XB_IIQ_ERROR             0x700078                          *
+ *           XB_POQ1_ERROR_CLEAR      0x700130                          *
+ *           XB_PIQ1_ERROR_CLEAR      0x700138                          *
+ *           XB_MP1_ERROR_CLEAR       0x700148                          *
+ *           XB_MMQ_ERROR_CLEAR       0x700150                          *
+ *           XB_NIQ_ERROR_CLEAR       0x700168                          *
+ *           XB_IOQ_ERROR_CLEAR       0x700170                          *
+ *           XB_IIQ_ERROR_CLEAR       0x700178                          *
+ *                                                                      *
+ ************************************************************************/
+
+
+/************************************************************************
+ *                                                                      *
+ *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
+ *                                                                      *
+ ************************************************************************/
+
+
+
+
+
+#endif /* _ASM_SN_SN1_HUBXB_H */
diff --git a/include/asm-ia64/sn/sn1/hubxb_next.h b/include/asm-ia64/sn/sn1/hubxb_next.h
new file mode 100644
index 000000000..ce3fea50c
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/hubxb_next.h
@@ -0,0 +1,32 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_HUBXB_NEXT_H
+#define _ASM_SN_SN1_HUBXB_NEXT_H
+
+/* XB_FIRST_ERROR fe_source field encoding */
+#define XVE_SOURCE_POQ0 0xf	/* 1111 */
+#define XVE_SOURCE_PIQ0 0xe	/* 1110 */
+#define XVE_SOURCE_POQ1 0xd	/* 1101 */
+#define XVE_SOURCE_PIQ1 0xc	/* 1100 */
+#define XVE_SOURCE_MP0  0xb	/* 1011 */
+#define XVE_SOURCE_MP1  0xa	/* 1010 */
+#define XVE_SOURCE_MMQ  0x9	/* 1001 */
+#define XVE_SOURCE_MIQ  0x8	/* 1000 */
+#define XVE_SOURCE_NOQ  0x7	/* 0111 */
+#define XVE_SOURCE_NIQ  0x6	/* 0110 */
+#define XVE_SOURCE_IOQ  0x5	/* 0101 */
+#define XVE_SOURCE_IIQ  0x4	/* 0100 */
+#define XVE_SOURCE_LOQ  0x3	/* 0011 */
+#define XVE_SOURCE_LIQ  0x2	/* 0010 */
+
+/* XB_PARMS fields */
+#define XBP_RESET_DEFAULTS	0x0008000080000021LL
+
+#endif	/* _ASM_SN_SN1_HUBXB_NEXT_H */
diff --git a/include/asm-ia64/sn/sn1/ip27config.h b/include/asm-ia64/sn/sn1/ip27config.h
new file mode 100644
index 000000000..2803ebaff
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/ip27config.h
@@ -0,0 +1,657 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_SN1_IP27CONFIG_H
+#define _ASM_SN_SN1_IP27CONFIG_H
+
+
+/*
+ * Structure: 	ip27config_s
+ * Typedef:	ip27config_t
+ * Purpose: 	Maps out the region of the boot prom used to define
+ *		configuration information.
+ * Notes:       Corresponds to ip27config structure found in start.s.
+ *		Fields are ulong where possible to facilitate IP27 PROM fetches.
+ */
+
+#define CONFIG_INFO_OFFSET		0x60
+
+#define IP27CONFIG_ADDR			(LBOOT_BASE	    + \
+					 CONFIG_INFO_OFFSET)
+#define IP27CONFIG_ADDR_NODE(n)		(NODE_RBOOT_BASE(n) + \
+					 CONFIG_INFO_OFFSET)
+
+/* Offset to the config_type field within local ip27config structure */
+#define CONFIG_FLAGS_ADDR			(IP27CONFIG_ADDR + 72)
+/* Offset to the config_type field in the ip27config structure on 
+ * node with nasid n
+ */
+#define CONFIG_FLAGS_ADDR_NODE(n)		(IP27CONFIG_ADDR_NODE(n) + 72)
+
+/* Meaning of each valid bit in the config flags 
+ * None are currently defined
+ */
+
+/* Meaning of each mach_type value
+ */
+#define SN1_MACH_TYPE 0
+
+/*
+ * Since 800 ns works well with various HUB frequencies, (such as 360,
+ * 380, 390, and 400 MHZ), we now use 800ns rtc cycle time instead of
+ * 1 microsec.
+ */
+#define IP27_RTC_FREQ			1250	/* 800ns cycle time */
+
+#if _LANGUAGE_C
+
+typedef	struct ip27config_s {		/* KEEP IN SYNC w/ start.s & below  */
+    uint		time_const;	/* Time constant 		    */
+    uint		r10k_mode;	/* R10k boot mode bits 		    */
+
+    uint64_t		magic;		/* CONFIG_MAGIC			    */
+
+    uint64_t		freq_cpu;	/* Hz 				    */
+    uint64_t		freq_hub;	/* Hz 				    */
+    uint64_t		freq_rtc;	/* Hz 				    */
+
+    uint		ecc_enable;	/* ECC enable flag		    */
+    uint		fprom_cyc;	/* FPROM_CYC speed control  	    */
+
+    uint		mach_type;	/* Inidicate IP27 (0) or Sn00 (1)    */
+
+    uint		check_sum_adj;	/* Used after config hdr overlay    */
+					/* to make the checksum 0 again     */
+    uint		flash_count;	/* Value incr'd on each PROM flash  */
+    uint		fprom_wr;	/* FPROM_WR speed control  	    */
+
+    uint		pvers_vers;	/* Prom version number		    */
+    uint		pvers_rev;	/* Prom revision number		    */
+    uint		config_type;	/* To support special configurations
+					 * (none currently defined)
+					 */
+} ip27config_t;
+
+typedef	struct {
+    uint		r10k_mode;	/* R10k boot mode bits 		    */
+    uint		freq_cpu;	/* Hz 				    */
+    uint		freq_hub;	/* Hz 				    */
+    char		fprom_cyc;	/* FPROM_CYC speed control  	    */
+    char		mach_type;	/* IP35(0) is only type defined      */
+    char		fprom_wr;	/* FPROM_WR speed control  	    */
+} config_modifiable_t;
+
+#define IP27CONFIG		(*(ip27config_t *) IP27CONFIG_ADDR)
+#define IP27CONFIG_NODE(n)	(*(ip27config_t *) IP27CONFIG_ADDR_NODE(n))
+#define SN00			0 /* IP35 has no Speedo equivalent */
+
+/* Get the config flags from local ip27config */
+#define CONFIG_FLAGS		(*(uint *) (CONFIG_FLAGS_ADDR))
+
+/* Get the config flags from ip27config on the node
+ * with nasid n
+ */
+#define CONFIG_FLAGS_NODE(n)	(*(uint *) (CONFIG_FLAGS_ADDR_NODE(n)))
+
+/* Macro to check if the local ip27config indicates a config
+ * of 12 p 4io
+ */
+#define CONFIG_12P4I		(0) /* IP35 has no 12p4i equivalent */
+
+/* Macro to check if the ip27config on node with nasid n
+ * indicates a config of 12 p 4io
+ */
+#define CONFIG_12P4I_NODE(n)	(0)
+
+#endif /* _LANGUAGE_C */
+
+#if _LANGUAGE_ASSEMBLY
+	.struct		0		/* KEEP IN SYNC WITH C structure */
+
+ip27c_time_const:	.word	0
+ip27c_r10k_mode:	.word	0
+
+ip27c_magic:		.dword	0
+
+ip27c_freq_cpu:		.dword	0
+ip27c_freq_hub:		.dword	0
+ip27c_freq_rtc:		.dword	0
+
+ip27c_ecc_enable:	.word	1
+ip27c_fprom_cyc:	.word	0
+
+ip27c_mach_type:	.word	0
+ip27c_check_sum_adj:	.word	0
+
+ip27c_flash_count:	.word	0
+ip27c_fprom_wr:		.word	0
+
+ip27c_pvers_vers:	.word	0
+ip27c_pvers_rev:	.word	0
+
+ip27c_config_type:	.word 	0	/* To recognize special configs */
+#endif /* _LANGUAGE_ASSEMBLY */
+
+/*
+ * R10000 Configuration Cycle - These define the SYSAD values used
+ * during the reset cycle.
+ */
+
+#define	IP27C_R10000_KSEG0CA_SHFT	0
+#define	IP27C_R10000_KSEG0CA_MASK	(7 << IP27C_R10000_KSEG0CA_SHFT)
+#define	IP27C_R10000_KSEG0CA(_B)	 ((_B) << IP27C_R10000_KSEG0CA_SHFT)
+
+#define	IP27C_R10000_DEVNUM_SHFT	3
+#define	IP27C_R10000_DEVNUM_MASK	(3 << IP27C_R10000_DEVNUM_SHFT)
+#define	IP27C_R10000_DEVNUM(_B)		((_B) << IP27C_R10000_DEVNUM_SHFT)
+
+#define	IP27C_R10000_CRPT_SHFT		5
+#define	IP27C_R10000_CRPT_MASK		(1 << IP27C_R10000_CRPT_SHFT)
+#define	IP27C_R10000_CPRT(_B)		((_B)<<IP27C_R10000_CRPT_SHFT)
+
+#define	IP27C_R10000_PER_SHFT		6
+#define	IP27C_R10000_PER_MASK		(1 << IP27C_R10000_PER_SHFT)
+#define	IP27C_R10000_PER(_B)		((_B) << IP27C_R10000_PER_SHFT)
+
+#define	IP27C_R10000_PRM_SHFT		7
+#define	IP27C_R10000_PRM_MASK		(3 << IP27C_R10000_PRM_SHFT)
+#define	IP27C_R10000_PRM(_B)		((_B) << IP27C_R10000_PRM_SHFT)
+
+#define	IP27C_R10000_SCD_SHFT		9
+#define	IP27C_R10000_SCD_MASK		(0xf << IP27C_R10000_SCD_MASK)
+#define	IP27C_R10000_SCD(_B)		((_B) << IP27C_R10000_SCD_SHFT)
+
+#define	IP27C_R10000_SCBS_SHFT		13
+#define	IP27C_R10000_SCBS_MASK		(1 << IP27C_R10000_SCBS_SHFT)
+#define	IP27C_R10000_SCBS(_B)		(((_B)) << IP27C_R10000_SCBS_SHFT)
+
+#define	IP27C_R10000_SCCE_SHFT		14
+#define	IP27C_R10000_SCCE_MASK		(1 << IP27C_R10000_SCCE_SHFT)
+#define	IP27C_R10000_SCCE(_B)		((_B) << IP27C_R10000_SCCE_SHFT)
+
+#define	IP27C_R10000_ME_SHFT		15
+#define	IP27C_R10000_ME_MASK		(1 << IP27C_R10000_ME_SHFT)
+#define	IP27C_R10000_ME(_B)		((_B) << IP27C_R10000_ME_SHFT)
+
+#define	IP27C_R10000_SCS_SHFT		16
+#define	IP27C_R10000_SCS_MASK		(7 << IP27C_R10000_SCS_SHFT)
+#define	IP27C_R10000_SCS(_B)		((_B) << IP27C_R10000_SCS_SHFT)
+
+#define	IP27C_R10000_SCCD_SHFT		19
+#define	IP27C_R10000_SCCD_MASK		(7 << IP27C_R10000_SCCD_SHFT)
+#define	IP27C_R10000_SCCD(_B)		((_B) << IP27C_R10000_SCCD_SHFT)
+
+#define	IP27C_R10000_SCCT_SHFT		25
+#define	IP27C_R10000_SCCT_MASK		(0xf << IP27C_R10000_SCCT_SHFT)
+#define	IP27C_R10000_SCCT(_B)		((_B) << IP27C_R10000_SCCT_SHFT)
+
+#define	IP27C_R10000_ODSC_SHFT		29
+#define IP27C_R10000_ODSC_MASK		(1 << IP27C_R10000_ODSC_SHFT)
+#define	IP27C_R10000_ODSC(_B)		((_B) << IP27C_R10000_ODSC_SHFT)
+
+#define	IP27C_R10000_ODSYS_SHFT		30
+#define	IP27C_R10000_ODSYS_MASK		(1 << IP27C_R10000_ODSYS_SHFT)
+#define	IP27C_R10000_ODSYS(_B)		((_B) << IP27C_R10000_ODSYS_SHFT)
+
+#define	IP27C_R10000_CTM_SHFT		31
+#define	IP27C_R10000_CTM_MASK		(1 << IP27C_R10000_CTM_SHFT)
+#define	IP27C_R10000_CTM(_B)		((_B) << IP27C_R10000_CTM_SHFT)
+
+#define IP27C_MHZ(x)			(1000000 * (x))
+#define IP27C_KHZ(x)			(1000 * (x))
+#define IP27C_MB(x)			((x) << 20)
+
+/*
+ * PROM Configurations
+ */
+
+#define CONFIG_MAGIC		0x69703237636f6e66
+
+/* The high 32 bits of the "mode bits".  Bits 7..0 contain one more
+ * than the number of 5ms clocks in the 100ms "long delay" intervals
+ * of the TRex reset sequence.  Bit 8 is the "synergy mode" bit.
+ */
+#define CONFIG_TIME_CONST	0x15
+
+#define CONFIG_ECC_ENABLE	1
+#define CONFIG_CHECK_SUM_ADJ	0
+#define CONFIG_DEFAULT_FLASH_COUNT    0
+
+/*
+ * Some promICEs have trouble if CONFIG_FPROM_SETUP is too low.
+ * The nominal value for 100 MHz hub is 5, for 200MHz bedrock is 16.
+ * any update to the below should also reflected in the logic in
+ *   IO7prom/flashprom.c function _verify_config_info and _fill_in_config_info
+ */
+
+/* default junk bus timing values to use */
+#define CONFIG_SYNERGY_ENABLE	0xff
+#define CONFIG_SYNERGY_SETUP	0xff
+#define CONFIG_UART_ENABLE	0x0c
+#define CONFIG_UART_SETUP	0x02
+#define CONFIG_FPROM_ENABLE	0x10
+#define CONFIG_FPROM_SETUP	0x10
+
+#define CONFIG_FREQ_RTC	IP27C_KHZ(IP27_RTC_FREQ)
+
+#if _LANGUAGE_C
+
+/* we are going to define all the known configs is a table
+ * for building hex images we will pull out the particular
+ * slice we care about by using the IP27_CONFIG_XX_XX as
+ * entries into the table
+ * to keep the table of reasonable size we only include the
+ * values that differ across configurations
+ * please note then that this makes assumptions about what
+ * will and will not change across configurations
+ */
+
+/* these numbers are as the are ordered in the table below */
+#define	IP27_CONFIG_UNKNOWN -1
+#define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0
+#define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1
+#define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2
+#define IP27_CONFIG_SN1_8MB_200_500_250_TABLE 3
+#define IP27_CONFIG_SN1_8MB_200_400_267_TABLE 4
+#define IP27_CONFIG_SN1_4MB_180_360_240_TABLE 5
+#define NUMB_IP_CONFIGS 6
+
+#ifdef DEF_IP_CONFIG_TABLE
+/*
+ * N.B.: A new entry needs to be added here everytime a new config is added
+ * The table is indexed by the PIMM PSC value
+ */
+
+static int psc_to_flash_config[] = {
+        IP27_CONFIG_SN1_4MB_200_400_267_TABLE,	/* 0x0 */
+        IP27_CONFIG_SN1_8MB_200_500_250_TABLE,	/* 0x1 */
+        IP27_CONFIG_SN1_8MB_200_400_267_TABLE,	/* 0x2 */
+        IP27_CONFIG_UNKNOWN,	/* 0x3 */
+        IP27_CONFIG_UNKNOWN,	/* 0x4 */
+        IP27_CONFIG_UNKNOWN,	/* 0x5 */
+        IP27_CONFIG_UNKNOWN,	/* 0x6 */
+        IP27_CONFIG_UNKNOWN,	/* 0x7 */
+        IP27_CONFIG_SN1_4MB_180_360_240_TABLE,	/* 0x8 */
+        IP27_CONFIG_UNKNOWN,	/* 0x9 */
+        IP27_CONFIG_UNKNOWN,	/* 0xa */
+        IP27_CONFIG_UNKNOWN,	/* 0xb */
+        IP27_CONFIG_UNKNOWN,	/* 0xc */
+        IP27_CONFIG_UNKNOWN,	/* 0xd */
+        IP27_CONFIG_SN00_4MB_100_200_133_TABLE, /* 0xe  O200 PIMM for bringup */
+        IP27_CONFIG_UNKNOWN	/* 0xf == PIMM not installed */
+};
+
+static config_modifiable_t ip_config_table[NUMB_IP_CONFIGS] = {
+/* the 1MB_200_400_200 values (Generic settings, will work for any config.) */
+{
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(1)	 + \
+	 IP27C_R10000_SCCD(3)	 + \
+	 IP27C_R10000_SCCT(9)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0)),
+	IP27C_MHZ(400),
+	IP27C_MHZ(200),
+	CONFIG_FPROM_SETUP,
+	SN1_MACH_TYPE,
+	CONFIG_FPROM_ENABLE
+},
+
+/* the 4MB_100_200_133 values (O200 PIMM w/translation board, PSC 0xe)
+ * (SysAD at 100MHz (SCD=3), and bedrock core at 200 MHz) */
+{
+ /* ODSYS == 0 means HSTL1 on SysAD bus; other PIMMs use HSTL2 */
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(3)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(9)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(0)	 + \
+	 IP27C_R10000_CTM(0)),
+	IP27C_MHZ(200),
+	IP27C_MHZ(200),
+	CONFIG_FPROM_SETUP,
+	SN1_MACH_TYPE,
+	CONFIG_FPROM_ENABLE
+},
+
+/* 4MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1602-001, PSC 0x0) */
+{
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(3)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(0xa)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0)),
+	IP27C_MHZ(400),
+	IP27C_MHZ(200),
+	CONFIG_FPROM_SETUP,
+	SN1_MACH_TYPE,
+	CONFIG_FPROM_ENABLE
+},
+
+/* 8MB_200_500_250 values (R14K, 4.0ns, DDR1, 030-1520-001, PSC 0x1) */
+{
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(4)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(4)	 + \
+	 IP27C_R10000_SCCD(3)	 + \
+	 IP27C_R10000_SCCT(0xa)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0)),
+	IP27C_MHZ(500),
+	IP27C_MHZ(200),
+	CONFIG_FPROM_SETUP,
+	SN1_MACH_TYPE,
+	CONFIG_FPROM_ENABLE
+},
+
+/* 8MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1616-001, PSC 0x2) */
+{
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(4)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(0xa)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0)),
+	IP27C_MHZ(400),
+	IP27C_MHZ(200),
+	CONFIG_FPROM_SETUP,
+	SN1_MACH_TYPE,
+	CONFIG_FPROM_ENABLE
+},
+
+/* 4MB_180_360_240 values (R12KS, 3.7ns, LWR, 030-1627-001, PSC 0x8)
+ * (SysAD at 180 MHz (SCD=3, the fastest possible), bedrock core at 200MHz) */
+{
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(3)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(9)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0)),
+	IP27C_MHZ(360),
+	IP27C_MHZ(200),
+	CONFIG_FPROM_SETUP,
+	SN1_MACH_TYPE,
+	CONFIG_FPROM_ENABLE
+},
+
+};
+#else
+extern	config_modifiable_t	ip_config_table[];
+#endif /* DEF_IP27_CONFIG_TABLE */
+
+#ifdef IP27_CONFIG_SN00_4MB_100_200_133
+#define CONFIG_CPU_MODE	ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].r10k_mode
+#define CONFIG_FREQ_CPU	ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_cpu
+#define CONFIG_FREQ_HUB	ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_hub
+#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_cyc
+#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].mach_type
+#define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_wr
+#endif /* IP27_CONFIG_SN00_4MB_100_200_133 */
+
+#ifdef IP27_CONFIG_SN1_1MB_200_400_200
+#define CONFIG_CPU_MODE	ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].r10k_mode
+#define CONFIG_FREQ_CPU	ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_cpu
+#define CONFIG_FREQ_HUB	ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_hub
+#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_cyc
+#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].mach_type
+#define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_wr
+#endif /* IP27_CONFIG_SN1_1MB_200_400_200 */
+
+#ifdef IP27_CONFIG_SN1_4MB_200_400_267
+#define CONFIG_CPU_MODE	ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].r10k_mode
+#define CONFIG_FREQ_CPU	ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_cpu
+#define CONFIG_FREQ_HUB	ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_hub
+#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_cyc
+#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].mach_type
+#define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_wr
+#endif /* IP27_CONFIG_SN1_4MB_200_400_267 */
+
+#ifdef IP27_CONFIG_SN1_8MB_200_500_250
+#define CONFIG_CPU_MODE	ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].r10k_mode
+#define CONFIG_FREQ_CPU	ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_cpu
+#define CONFIG_FREQ_HUB	ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_hub
+#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_cyc
+#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].mach_type
+#define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_wr
+#endif /* IP27_CONFIG_SN1_8MB_200_500_250 */
+
+#ifdef IP27_CONFIG_SN1_8MB_200_400_267
+#define CONFIG_CPU_MODE	ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].r10k_mode
+#define CONFIG_FREQ_CPU	ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_cpu
+#define CONFIG_FREQ_HUB	ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_hub
+#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_cyc
+#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].mach_type
+#define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_wr
+#endif /* IP27_CONFIG_SN1_8MB_200_400_267 */
+
+#ifdef IP27_CONFIG_SN1_4MB_180_360_240
+#define CONFIG_CPU_MODE	ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].r10k_mode
+#define CONFIG_FREQ_CPU	ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_cpu
+#define CONFIG_FREQ_HUB	ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_hub
+#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_cyc
+#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].mach_type
+#define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr
+#endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
+
+#endif /* _LANGUAGE_C */
+
+#if _LANGUAGE_ASSEMBLY
+
+/* these need to be in here since we need assembly definitions
+ * for building hex images (as required by start.s)
+ */
+#ifdef IP27_CONFIG_SN00_4MB_100_200_133
+#ifdef IRIX
+/* Set PrcReqMax to 0 to reduce memory problems */
+#define	BRINGUP_PRM_VAL	0
+#else
+#define	BRINGUP_PRM_VAL	3
+#endif
+#define CONFIG_CPU_MODE \
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(BRINGUP_PRM_VAL)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(3)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(9)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(0)	 + \
+	 IP27C_R10000_CTM(0))
+#define CONFIG_FREQ_CPU IP27C_MHZ(200)
+#define CONFIG_FREQ_HUB IP27C_MHZ(200)
+#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
+#define CONFIG_MACH_TYPE SN1_MACH_TYPE
+#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
+#endif /* IP27_CONFIG_SN00_4MB_100_200_133 */
+
+#ifdef IP27_CONFIG_SN1_1MB_200_400_200
+#define CONFIG_CPU_MODE \
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(1)	 + \
+	 IP27C_R10000_SCCD(3)	 + \
+	 IP27C_R10000_SCCT(9)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0))
+#define CONFIG_FREQ_CPU IP27C_MHZ(400)
+#define CONFIG_FREQ_HUB IP27C_MHZ(200)
+#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
+#define CONFIG_MACH_TYPE SN1_MACH_TYPE
+#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
+#endif /* IP27_CONFIG_SN1_1MB_200_400_200 */
+
+#ifdef IP27_CONFIG_SN1_4MB_200_400_267
+#define CONFIG_CPU_MODE \
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(3)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(0xa)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0))
+#define CONFIG_FREQ_CPU IP27C_MHZ(400)
+#define CONFIG_FREQ_HUB IP27C_MHZ(200)
+#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
+#define CONFIG_MACH_TYPE SN1_MACH_TYPE
+#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
+#endif /* IP27_CONFIG_SN1_4MB_200_400_267 */
+
+#ifdef IP27_CONFIG_SN1_8MB_200_500_250
+#define CONFIG_CPU_MODE \
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(4)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(4)	 + \
+	 IP27C_R10000_SCCD(3)	 + \
+	 IP27C_R10000_SCCT(0xa)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0))
+#define CONFIG_FREQ_CPU IP27C_MHZ(500)
+#define CONFIG_FREQ_HUB IP27C_MHZ(200)
+#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
+#define CONFIG_MACH_TYPE SN1_MACH_TYPE
+#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
+#endif /* IP27_CONFIG_SN1_8MB_200_500_250 */
+
+#ifdef IP27_CONFIG_SN1_8MB_200_400_267
+#define CONFIG_CPU_MODE \
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(4)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(0xa)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0))
+#define CONFIG_FREQ_CPU IP27C_MHZ(400)
+#define CONFIG_FREQ_HUB IP27C_MHZ(200)
+#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
+#define CONFIG_MACH_TYPE SN1_MACH_TYPE
+#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
+#endif /* IP27_CONFIG_SN1_8MB_200_400_267 */
+
+#ifdef IP27_CONFIG_SN1_4MB_180_360_240
+#define CONFIG_CPU_MODE \
+	(IP27C_R10000_KSEG0CA(5) + \
+	 IP27C_R10000_DEVNUM(0)	 + \
+	 IP27C_R10000_CPRT(0)	 + \
+	 IP27C_R10000_PER(0)	 + \
+	 IP27C_R10000_PRM(3)	 + \
+	 IP27C_R10000_SCD(3)	 + \
+	 IP27C_R10000_SCBS(1)	 + \
+	 IP27C_R10000_SCCE(0)	 + \
+	 IP27C_R10000_ME(1)	 + \
+	 IP27C_R10000_SCS(3)	 + \
+	 IP27C_R10000_SCCD(2)	 + \
+	 IP27C_R10000_SCCT(9)	 + \
+	 IP27C_R10000_ODSC(0)	 + \
+	 IP27C_R10000_ODSYS(1)	 + \
+	 IP27C_R10000_CTM(0))
+#define CONFIG_FREQ_CPU IP27C_MHZ(360)
+#define CONFIG_FREQ_HUB IP27C_MHZ(200)
+#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
+#define CONFIG_MACH_TYPE SN1_MACH_TYPE
+#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
+#endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
+
+#endif /* _LANGUAGE_C */
+
+#endif /* _ASM_SN_SN1_IP27CONFIG_H */
diff --git a/include/asm-ia64/sn/sn1/kldir.h b/include/asm-ia64/sn/sn1/kldir.h
new file mode 100644
index 000000000..e8d4935d8
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/kldir.h
@@ -0,0 +1,222 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_SN1_KLDIR_H
+#define _ASM_SN_SN1_KLDIR_H
+
+/*
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.  The minimum memory bank
+ * size on IP35 is 64M, which provides a limit on the amount of space
+ * the PROM can assume it has available.
+ *
+ * Most of the addresses below are defined as macros in this file, or
+ * in SN/addrs.h or SN/SN1/addrs.h.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x4000000 (64M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      IO7 TEXT/DATA/BSS/stack            |
+ * 0x3000000 (48M)         +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x2102000 (>33M)        +-----------------------------------------+
+ *                         |      IP35 Topology (PCFG) + misc data   |
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO7 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x1C00000 (28M)         +-----------------------------------------+
+ *                         |      IP35 PROM TEXT/DATA/BSS/stack      |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Routing temp. space                |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      Diagnostics temp. space            |
+ * 0x1500000 (21M)         +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x1400000 (20M)         +-----------------------------------------+
+ *                         |      IO7 PROM temporary copy            |
+ * 0x1300000 (19M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |      (UNIX DATA starts above 0x1000000) |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x0310000 (3.1M)        +-----------------------------------------+
+ *                         |      SYMMON, loaded just below UNIX     |
+ *                         |      (For UNIX Debug only)              |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x006C000 (432K)        +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x004C000 (304K)        +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x0040000 (256K)        +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP35PROM, IO7PROM and IRIX.
+ *
+ * 0x40000 (256K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      KLCONFIG (64K)                     |
+ *                         |                                         |
+ * 0x30000 (192K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (64K)              |
+ *                         |                                         |
+ * 0x20000 (128K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 3)|
+ * 0x18800 (98K)           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 3)	     |
+ * 0x18400 (97K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 3)         |
+ * 0x18000 (96K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x13c00 (79K)           +-----------------------------------------+
+ *                         |      GPDA (8k)                          |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 2)|
+ * 0x10800 (66k)	   +-----------------------------------------+
+ *			   |      cache error eframe (CPU 2)	     |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 2)         |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x0b400 (45K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x0b000 (44K)           +-----------------------------------------+
+ *                         |      NMI Eframe areas (4)       	     |
+ * 0x0a000 (40K)           +-----------------------------------------+
+ *                         |      NMI Register save areas (4)        |
+ * 0x09000 (36K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 1)|
+ * 0x08800 (34K)           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 1)	     |
+ * 0x08400 (33K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 1)         |
+ * 0x08000 (32K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x04000 (16K)           +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x03000 (12K)           +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x02c00 (11K)           +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x02800 (10K)           +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x02400 (9K)            +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x02000 (8K)            +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x01000 (4K)            +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 0)|
+ * 0x00800 (2k)	           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 0)	     |
+ * 0x00400 (1K)            +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 0)         |
+ * 0x00000 (0K)            +-----------------------------------------+
+ */
+
+/*
+ * NOTE:  To change the kernel load address, you must update:
+ *  - the appropriate elspec files in irix/kern/master.d
+ *  - NODEBUGUNIX_ADDR in SN/SN1/addrs.h
+ *  - IP27_FREEMEM_OFFSET below
+ *  - KERNEL_START_OFFSET below (if supporting cells)
+ */
+
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE		0x8000
+
+#if defined (PROM) || defined (SABLE)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP35
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET		0x2400
+#define IP27_LAUNCH_SIZE		0x400
+#define IP27_LAUNCH_COUNT		4
+#define IP27_LAUNCH_STRIDE		0x100 /* could be as small as 0x80 */
+
+#define IP27_KLCONFIG_OFFSET		0x30000
+#define IP27_KLCONFIG_SIZE		0x10000
+#define IP27_KLCONFIG_COUNT		1
+#define IP27_KLCONFIG_STRIDE		0
+
+#define IP27_NMI_OFFSET			0x3000
+#define IP27_NMI_SIZE			0x100
+#define IP27_NMI_COUNT			4
+#define IP27_NMI_STRIDE			0x40
+
+#define IP27_PI_ERROR_OFFSET		0x20000
+#define IP27_PI_ERROR_SIZE		0x10000
+#define IP27_PI_ERROR_COUNT		1
+#define IP27_PI_ERROR_STRIDE		0
+
+#define IP27_SYMMON_STK_OFFSET		0x4c000
+#define IP27_SYMMON_STK_SIZE		0x20000
+#define IP27_SYMMON_STK_COUNT		4
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE		0x8000
+
+#define IP27_FREEMEM_OFFSET		0x40000
+#define IP27_FREEMEM_SIZE		-1
+#define IP27_FREEMEM_COUNT		1
+#define IP27_FREEMEM_STRIDE		0
+
+#endif /* PROM || SABLE*/
+/*
+ * There will be only one of these in a partition so the IO7 must set it up.
+ */
+#define IO6_GDA_OFFSET			0xb000
+#define IO6_GDA_SIZE			0x400
+#define IO6_GDA_COUNT			1
+#define IO6_GDA_STRIDE			0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET		0x9000
+#define IP27_NMI_KREGS_CPU_SIZE		0x400
+/*
+ * save area of kernel nmi regs in eframe format 
+ */
+#define IP27_NMI_EFRAME_OFFSET		0xa000
+#define IP27_NMI_EFRAME_SIZE		0x400
+
+#define GPDA_OFFSET			0x11c00
+
+#endif /* _ASM_SN_SN1_KLDIR_H */
diff --git a/include/asm-ia64/sn/sn1/leds.h b/include/asm-ia64/sn/sn1/leds.h
new file mode 100644
index 000000000..85eb645ca
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/leds.h
@@ -0,0 +1,35 @@
+#ifndef _ASM_SN_SN1_LED_H
+#define _ASM_SN_SN1_LED_H
+
+/*
+ * Copyright (C) 2000 Silicon Graphics, Inc
+ * Copyright (C) 2000 Jack Steiner (steiner@sgi.com)
+ */
+
+#include <asm/smp.h>
+
+#define LED0		0xc0000b00100000c0LL	/* ZZZ fixme */
+
+
+
+#define LED_AP_START	0x01		/* AP processor started */
+#define LED_AP_IDLE	0x01
+
+/*
+ * Basic macros for flashing the LEDS on an SGI, SN1.
+ */
+
+extern __inline__ void
+HUB_SET_LED(int val)
+{
+	long	*ledp;
+	int	eid;
+
+	eid = hard_processor_sapicid() & 3;
+	ledp = (long*) (LED0 + (eid<<3));
+	*ledp = val;
+}
+
+
+#endif /* _ASM_SN_SN1_LED_H */
+
diff --git a/include/asm-ia64/sn/sn1/promlog.h b/include/asm-ia64/sn/sn1/promlog.h
new file mode 100644
index 000000000..4c4b9f2e9
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/promlog.h
@@ -0,0 +1,85 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef	_ASM_SN_SN1_PROMLOG_H
+#define	_ASM_SN_SN1_PROMLOG_H
+
+#include <asm/sn/fprom.h>
+
+#define PROMLOG_MAGIC			0x504c4f49
+#define PROMLOG_VERSION			1
+
+#define PROMLOG_OFFSET_MAGIC		0x10
+#define PROMLOG_OFFSET_VERSION		0x14
+#define PROMLOG_OFFSET_SEQUENCE		0x18
+#define PROMLOG_OFFSET_ENTRY0		0x100
+
+#define PROMLOG_ERROR_NONE		0
+#define PROMLOG_ERROR_PROM	       -1
+#define PROMLOG_ERROR_MAGIC	       -2
+#define PROMLOG_ERROR_CORRUPT	       -3
+#define PROMLOG_ERROR_BOL	       -4
+#define PROMLOG_ERROR_EOL	       -5
+#define PROMLOG_ERROR_POS	       -6
+#define PROMLOG_ERROR_REPLACE	       -7
+#define PROMLOG_ERROR_COMPACT	       -8
+#define PROMLOG_ERROR_FULL	       -9
+#define PROMLOG_ERROR_ARG	       -10
+#define PROMLOG_ERROR_UNUSED	       -11	  	
+
+#define PROMLOG_TYPE_UNUSED		0xf
+#define PROMLOG_TYPE_LOG		3
+#define PROMLOG_TYPE_LIST		2
+#define PROMLOG_TYPE_VAR		1
+#define PROMLOG_TYPE_DELETED		0
+
+#define PROMLOG_TYPE_ANY		98
+#define PROMLOG_TYPE_INVALID		99
+
+#define PROMLOG_KEY_MAX			14
+#define PROMLOG_VALUE_MAX		47
+#define PROMLOG_CPU_MAX			4
+
+typedef struct promlog_header_s {
+    unsigned int	unused[4];
+    unsigned int	magic;
+    unsigned int	version;
+    unsigned int	sequence;
+} promlog_header_t;
+
+typedef unsigned int promlog_pos_t;
+
+typedef struct promlog_ent_s {		/* PROM individual entry */
+    uint		type		: 4;
+    uint		cpu_num		: 4;
+    char		key[PROMLOG_KEY_MAX + 1];
+
+    char		value[PROMLOG_VALUE_MAX + 1];
+
+} promlog_ent_t;
+
+typedef struct promlog_s {		/* Activation handle */
+    fprom_t		f;
+    int			sector_base;
+    int			cpu_num;
+
+    int			active;		/* Active sector, 0 or 1 */
+
+    promlog_pos_t	log_start;
+    promlog_pos_t	log_end;
+
+    promlog_pos_t	alt_start;
+    promlog_pos_t	alt_end;
+
+    promlog_pos_t	pos;
+    promlog_ent_t	ent;
+} promlog_t;
+
+#endif /* _ASM_SN_SN1_PROMLOG_H */
diff --git a/include/asm-ia64/sn/sn1/router.h b/include/asm-ia64/sn/sn1/router.h
new file mode 100644
index 000000000..9ae47bc12
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/router.h
@@ -0,0 +1,669 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef	_ASM_SN_SN1_ROUTER_H
+#define	_ASM_SN_SN1_ROUTER_H
+
+/*
+ * Router Register definitions
+ *
+ * Macro argument _L always stands for a link number (1 to 8, inclusive).
+ */
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+
+#include <asm/sn/vector.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/arch.h>
+
+typedef uint64_t	router_reg_t;
+
+#define MAX_ROUTERS	64
+
+#define MAX_ROUTER_PATH	80
+
+#define ROUTER_REG_CAST		(volatile router_reg_t *)
+#define PS_UINT_CAST		(__psunsigned_t)
+#define UINT64_CAST		(uint64_t)
+typedef signed char port_no_t;	 /* Type for router port number      */
+
+#elif _LANGUAGE_ASSEMBLY
+
+#define ROUTERREG_CAST
+#define PS_UINT_CAST
+#define UINT64_CAST
+
+#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+
+#define MAX_ROUTER_PORTS (8)	 /* Max. number of ports on a router */
+
+#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1)	/* for 0 based references */
+
+#define PORT_INVALID (-1)	 /* Invalid port number              */
+
+#define	IS_META(_rp)	((_rp)->flags & PCFG_ROUTER_META)
+
+#define	IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)
+
+/*
+ * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
+ * port to generate an output port.
+ *
+ * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
+ * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
+ *
+ * These are written to work on unsigned data.
+ */
+
+#define RR_TURN(_L, count)	((_L) + (count) > MAX_ROUTER_PORTS ?	\
+				 (_L) + (count) - MAX_ROUTER_PORTS :	\
+				 (_L) + (count))
+
+#define RR_DISTANCE(_LS, _LD)	((_LD) >= (_LS) ?			\
+				 (_LD) - (_LS) :			\
+				 (_LD) + MAX_ROUTER_PORTS - (_LS))
+
+/* Router register addresses */
+
+#define RR_STATUS_REV_ID	0x00000	/* Status register and Revision ID  */
+#define RR_PORT_RESET		0x00008	/* Multiple port reset              */
+#define RR_PROT_CONF		0x00010	/* Inter-partition protection conf. */
+#define RR_GLOBAL_PORT_DEF	0x00018 /* Global Port definitions          */
+#define RR_GLOBAL_PARMS0	0x00020	/* Parameters shared by all 8 ports */
+#define RR_GLOBAL_PARMS1	0x00028	/* Parameters shared by all 8 ports */
+#define RR_DIAG_PARMS		0x00030	/* Parameters for diag. testing     */
+#define RR_DEBUG_ADDR		0x00038 /* Debug address select - debug port*/
+#define RR_LB_TO_L2		0x00040 /* Local Block to L2 cntrl intf reg */ 
+#define RR_L2_TO_LB		0x00048 /* L2 cntrl intf to Local Block reg */
+#define RR_JBUS_CONTROL		0x00050 /* read/write timing for JBUS intf  */
+
+#define RR_SCRATCH_REG0		0x00100	/* Scratch 0 is 64 bits */
+#define RR_SCRATCH_REG1		0x00108	/* Scratch 1 is 64 bits */
+#define RR_SCRATCH_REG2		0x00110	/* Scratch 2 is 64 bits */
+#define RR_SCRATCH_REG3		0x00118	/* Scratch 3 is 1 bit */
+#define RR_SCRATCH_REG4		0x00120	/* Scratch 4 is 1 bit */
+
+#define RR_JBUS0(_D)		(((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses   */
+#define RR_JBUS1(_D)		(((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses   */
+
+#define RR_SCRATCH_REG0_WZ	0x00500	/* Scratch 0 is 64 bits */
+#define RR_SCRATCH_REG1_WZ	0x00508	/* Scratch 1 is 64 bits */
+#define RR_SCRATCH_REG2_WZ	0x00510	/* Scratch 2 is 64 bits */
+#define RR_SCRATCH_REG3_SZ	0x00518	/* Scratch 3 is 1 bit */
+#define RR_SCRATCH_REG4_SZ	0x00520	/* Scratch 4 is 1 bit */
+
+#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
+/* Port-specific registers (_L is the link number from 1 to 8) */
+
+#define RR_PORT_PARMS(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters     */
+#define RR_STATUS_ERROR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs  */
+#define RR_CHANNEL_TEST(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
+#define RR_RESET_MASK(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask  */
+#define RR_HISTOGRAM0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
+#define RR_HISTOGRAM1(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
+#define RR_HISTOGRAM0_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
+#define RR_HISTOGRAM1_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
+#define RR_ERROR_CLEAR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors  */
+#define RR_GLOBAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
+#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
+#define RR_LOCAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
+#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))
+
+#define RR_META_ENTRIES		16
+
+#define RR_LOCAL_ENTRIES	128
+
+/*
+ * RR_STATUS_REV_ID mask and shift definitions
+ */
+
+#define RSRI_INPORT_SHFT	52
+#define RSRI_INPORT_MASK	(UINT64_CAST 0xf << 52)
+#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
+#define RSRI_LINKWORKING(_L)	(UINT64_CAST 1 << (35 + 2 * (_L)))
+#define RSRI_LINKRESETFAIL(_L)	(UINT64_CAST 1 << (34 + 2 * (_L)))
+#define RSRI_LSTAT_SHFT(_L)	(34 + 2 * (_L))
+#define RSRI_LSTAT_MASK(_L)	(UINT64_CAST 0x3 << 34 + 2 * (_L))
+#define RSRI_LOCALSBERROR	(UINT64_CAST 1 << 35)
+#define RSRI_LOCALSTUCK		(UINT64_CAST 1 << 34)
+#define RSRI_LOCALBADVEC	(UINT64_CAST 1 << 33)
+#define RSRI_LOCALTAILERR	(UINT64_CAST 1 << 32)
+#define RSRI_LOCAL_SHFT 	32
+#define RSRI_LOCAL_MASK		(UINT64_CAST 0xf << 32)
+#define RSRI_CHIPREV_SHFT	28
+#define RSRI_CHIPREV_MASK	(UINT64_CAST 0xf << 28)
+#define RSRI_CHIPID_SHFT	12
+#define RSRI_CHIPID_MASK	(UINT64_CAST 0xffff << 12)
+#define RSRI_MFGID_SHFT		1
+#define RSRI_MFGID_MASK		(UINT64_CAST 0x7ff << 1)
+
+#define RSRI_LSTAT_WENTDOWN	0
+#define RSRI_LSTAT_RESETFAIL	1
+#define RSRI_LSTAT_LINKUP	2
+#define RSRI_LSTAT_NOTUSED	3
+
+/*
+ * RR_PORT_RESET mask definitions
+ */
+
+#define RPRESET_WARM		(UINT64_CAST 1 << 9)
+#define RPRESET_LINK(_L)	(UINT64_CAST 1 << (_L))
+#define RPRESET_LOCAL		(UINT64_CAST 1)
+
+/*
+ * RR_PROT_CONF mask and shift definitions
+ */
+
+#define RPCONF_DIRCMPDIS_SHFT	13
+#define RPCONF_DIRCMPDIS_MASK	(UINT64_CAST 1 << 13)
+#define RPCONF_FORCELOCAL	(UINT64_CAST 1 << 12)
+#define RPCONF_FLOCAL_SHFT	12
+#define RPCONF_METAID_SHFT	8
+#define RPCONF_METAID_MASK	(UINT64_CAST 0xf << 8)
+#define RPCONF_RESETOK(_L)	(UINT64_CAST 1 << ((_L) - 1))
+
+/*
+ * RR_GLOBAL_PORT_DEF mask and shift definitions
+ */
+
+#define RGPD_MGLBLNHBR_ID_SHFT	12	/* -global neighbor ID */
+#define RGPD_MGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 12)
+#define RGPD_MGLBLNHBR_VLD_SHFT	11	/* -global neighbor Valid */
+#define RGPD_MGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 11)
+#define RGPD_MGLBLPORT_SHFT	8	/* -global neighbor Port */
+#define RGPD_MGLBLPORT_MASK	(UINT64_CAST 0x7 << 8)
+#define RGPD_PGLBLNHBR_ID_SHFT	4	/* +global neighbor ID */
+#define RGPD_PGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 4)
+#define RGPD_PGLBLNHBR_VLD_SHFT	3	/* +global neighbor Valid */
+#define RGPD_PGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 3)
+#define RGPD_PGLBLPORT_SHFT	0	/* +global neighbor Port */
+#define RGPD_PGLBLPORT_MASK	(UINT64_CAST 0x7 << 0)
+
+#define GLBL_PARMS_REGS		2	/* Two Global Parms registers */
+
+/*
+ * RR_GLOBAL_PARMS0 mask and shift definitions
+ */
+
+#define RGPARM0_ARB_VALUE_SHFT	54	/* Local Block Arbitration State */
+#define RGPARM0_ARB_VALUE_MASK	(UINT64_CAST 0x7 << 54)
+#define RGPARM0_ROTATEARB_SHFT	53	/* Rotate Local Block Arbitration */
+#define RGPARM0_ROTATEARB_MASK	(UINT64_CAST 0x1 << 53)
+#define RGPARM0_FAIREN_SHFT	52	/* Fairness logic Enable */
+#define RGPARM0_FAIREN_MASK	(UINT64_CAST 0x1 << 52)
+#define RGPARM0_LOCGNTTO_SHFT	40	/* Local grant timeout */
+#define RGPARM0_LOCGNTTO_MASK	(UINT64_CAST 0xfff << 40)
+#define RGPARM0_DATELINE_SHFT	38	/* Dateline crossing router */
+#define RGPARM0_DATELINE_MASK	(UINT64_CAST 0x1 << 38)
+#define RGPARM0_MAXRETRY_SHFT	28	/* Max retry count */
+#define RGPARM0_MAXRETRY_MASK	(UINT64_CAST 0x3ff << 28)
+#define RGPARM0_URGWRAP_SHFT	20	/* Urgent wrap */
+#define RGPARM0_URGWRAP_MASK	(UINT64_CAST 0xff << 20)
+#define RGPARM0_DEADLKTO_SHFT	16	/* Deadlock timeout */
+#define RGPARM0_DEADLKTO_MASK	(UINT64_CAST 0xf << 16)
+#define RGPARM0_URGVAL_SHFT	12	/* Urgent value */
+#define RGPARM0_URGVAL_MASK	(UINT64_CAST 0xf << 12)
+#define RGPARM0_VCHSELEN_SHFT	11	/* VCH_SEL_EN */
+#define RGPARM0_VCHSELEN_MASK	(UINT64_CAST 0x1 << 11)
+#define RGPARM0_LOCURGTO_SHFT	9	/* Local urgent timeout */
+#define RGPARM0_LOCURGTO_MASK	(UINT64_CAST 0x3 << 9)
+#define RGPARM0_TAILVAL_SHFT	5	/* Tail value */
+#define RGPARM0_TAILVAL_MASK	(UINT64_CAST 0xf << 5)
+#define RGPARM0_CLOCK_SHFT	1	/* Global clock select */
+#define RGPARM0_CLOCK_MASK	(UINT64_CAST 0xf << 1)
+#define RGPARM0_BYPEN_SHFT	0
+#define RGPARM0_BYPEN_MASK	(UINT64_CAST 1)	/* Bypass enable */
+
+/*
+ * RR_GLOBAL_PARMS1 shift and mask definitions
+ */
+
+#define RGPARM1_TTOWRAP_SHFT	12	/* Tail timeout wrap */
+#define RGPARM1_TTOWRAP_MASK	(UINT64_CAST 0xfffff << 12)
+#define RGPARM1_AGERATE_SHFT	8	/* Age rate */
+#define RGPARM1_AGERATE_MASK	(UINT64_CAST 0xf << 8)
+#define RGPARM1_JSWSTAT_SHFT	0	/* JTAG Sw Register bits */
+#define RGPARM1_JSWSTAT_MASK	(UINT64_CAST 0xff << 0)
+
+/*
+ * RR_DIAG_PARMS mask and shift definitions
+ */
+
+#define RDPARM_ABSHISTOGRAM	(UINT64_CAST 1 << 17)	/* Absolute histgrm */
+#define RDPARM_DEADLOCKRESET	(UINT64_CAST 1 << 16)	/* Reset on deadlck */
+#define RDPARM_DISABLE(_L)	(UINT64_CAST 1 << ((_L) +  7))
+#define RDPARM_SENDERROR(_L)	(UINT64_CAST 1 << ((_L) -  1))
+
+/*
+ * RR_DEBUG_ADDR mask and shift definitions
+ */
+
+#define RDA_DATA_SHFT		10	/* Observed debug data */
+#define RDA_DATA_MASK		(UINT64_CAST 0xffff << 10)
+#define RDA_ADDR_SHFT		0	/* debug address for data */
+#define RDA_ADDR_MASK		(UINT64_CAST 0x3ff << 0)
+
+/*
+ * RR_LB_TO_L2 mask and shift definitions
+ */
+
+#define RLBTOL2_DATA_VLD_SHFT	32	/* data is valid for JTAG controller */
+#define RLBTOL2_DATA_VLD_MASK	(UINT64_CAST 0x1 << 32)
+#define RLBTOL2_DATA_SHFT	0	/* data bits for JTAG controller */
+#define RLBTOL2_DATA_MASK	(UINT64_CAST 0xffffffff)
+
+/*
+ * RR_L2_TO_LB mask and shift definitions
+ */
+
+#define RL2TOLB_DATA_VLD_SHFT	33	/* data is valid from JTAG controller */
+#define RL2TOLB_DATA_VLD_MASK	(UINT64_CAST 0x1 << 33)
+#define RL2TOLB_PARITY_SHFT	32	/* sw implemented parity for data */
+#define RL2TOLB_PARITY_MASK	(UINT64_CAST 0x1 << 32)
+#define RL2TOLB_DATA_SHFT	0	/* data bits from JTAG controller */
+#define RL2TOLB_DATA_MASK	(UINT64_CAST 0xffffffff)
+
+/*
+ * RR_JBUS_CONTROL mask and shift definitions
+ */
+
+#define RJC_POS_BITS_SHFT	20	/* Router position bits */
+#define RJC_POS_BITS_MASK	(UINT64_CAST 0xf << 20)
+#define RJC_RD_DATA_STROBE_SHFT	16	/* count when read data is strobed in */
+#define RJC_RD_DATA_STROBE_MASK	(UINT64_CAST 0xf << 16)
+#define RJC_WE_OE_HOLD_SHFT	8	/* time OE or WE is held */
+#define RJC_WE_OE_HOLD_MASK	(UINT64_CAST 0xff << 8)
+#define RJC_ADDR_SET_HLD_SHFT	0	/* time address driven around OE/WE */
+#define RJC_ADDR_SET_HLD_MASK	(UINT64_CAST 0xff)
+
+/*
+ * RR_SCRATCH_REGx mask and shift definitions
+ *  note: these fields represent a software convention, and are not
+ *        understood/interpreted by the hardware. 
+ */
+
+#define	RSCR0_BOOTED_SHFT	63
+#define	RSCR0_BOOTED_MASK	(UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT)
+#define RSCR0_LOCALID_SHFT	56
+#define RSCR0_LOCALID_MASK	(UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT)
+#define	RSCR0_UNUSED_SHFT	48
+#define	RSCR0_UNUSED_MASK	(UINT64_CAST 0xff << RSCR0_UNUSED_SHFT)
+#define RSCR0_NIC_SHFT		0
+#define RSCR0_NIC_MASK		(UINT64_CAST 0xffffffffffff)
+
+#define RSCR1_MODID_SHFT	0
+#define RSCR1_MODID_MASK	(UINT64_CAST 0xffff)
+
+/*
+ * RR_VECTOR_HW_BAR mask and shift definitions
+ */
+
+#define BAR_TX_SHFT		27	/* Barrier in trans(m)it when read */
+#define BAR_TX_MASK		(UINT64_CAST 1 << BAR_TX_SHFT)
+#define BAR_VLD_SHFT		26	/* Valid Configuration */
+#define BAR_VLD_MASK		(UINT64_CAST 1 << BAR_VLD_SHFT)
+#define BAR_SEQ_SHFT		24	/* Sequence number */
+#define BAR_SEQ_MASK		(UINT64_CAST 3 << BAR_SEQ_SHFT)
+#define BAR_LEAFSTATE_SHFT	18	/* Leaf State */
+#define BAR_LEAFSTATE_MASK	(UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT)
+#define BAR_PARENT_SHFT		14	/* Parent Port */
+#define BAR_PARENT_MASK		(UINT64_CAST 0xf << BAR_PARENT_SHFT)
+#define BAR_CHILDREN_SHFT	6	/* Child Select port bits */
+#define BAR_CHILDREN_MASK	(UINT64_CAST 0xff << BAR_CHILDREN_SHFT)
+#define BAR_LEAFCOUNT_SHFT	0	/* Leaf Count to trigger parent */
+#define BAR_LEAFCOUNT_MASK	(UINT64_CAST 0x3f)
+
+/*
+ * RR_PORT_PARMS(_L) mask and shift definitions
+ */
+
+#define RPPARM_MIPRESETEN_SHFT	29	/* Message In Progress reset enable */
+#define RPPARM_MIPRESETEN_MASK	(UINT64_CAST 0x1 << 29)
+#define RPPARM_UBAREN_SHFT	28	/* Enable user barrier requests */
+#define RPPARM_UBAREN_MASK	(UINT64_CAST 0x1 << 28)
+#define RPPARM_OUTPDTO_SHFT	24	/* Output Port Deadlock TO value */
+#define RPPARM_OUTPDTO_MASK	(UINT64_CAST 0xf << 24)
+#define RPPARM_PORTMATE_SHFT	21	/* Port Mate for the port */
+#define RPPARM_PORTMATE_MASK	(UINT64_CAST 0x7 << 21)
+#define RPPARM_HISTEN_SHFT	20	/* Histogram counter enable */
+#define RPPARM_HISTEN_MASK	(UINT64_CAST 0x1 << 20)
+#define RPPARM_HISTSEL_SHFT	18
+#define RPPARM_HISTSEL_MASK	(UINT64_CAST 0x3 << 18)
+#define RPPARM_DAMQHS_SHFT	16
+#define RPPARM_DAMQHS_MASK	(UINT64_CAST 0x3 << 16)
+#define RPPARM_NULLTO_SHFT	10
+#define RPPARM_NULLTO_MASK	(UINT64_CAST 0x3f << 10)
+#define RPPARM_MAXBURST_SHFT	0
+#define RPPARM_MAXBURST_MASK	(UINT64_CAST 0x3ff)
+
+/*
+ * NOTE: Normally the kernel tracks only UTILIZATION statistics.
+ * The other 2 should not be used, except during any experimentation
+ * with the router.
+ */
+#define RPPARM_HISTSEL_AGE	0	/* Histogram age characterization.  */
+#define RPPARM_HISTSEL_UTIL	1	/* Histogram link utilization 	    */
+#define RPPARM_HISTSEL_DAMQ	2	/* Histogram DAMQ characterization. */
+
+/*
+ * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions
+ */
+#define RSERR_POWERNOK		(UINT64_CAST 1 << 38)
+#define RSERR_PORT_DEADLOCK     (UINT64_CAST 1 << 37)
+#define RSERR_WARMRESET         (UINT64_CAST 1 << 36)
+#define RSERR_LINKRESET         (UINT64_CAST 1 << 35)
+#define RSERR_RETRYTIMEOUT      (UINT64_CAST 1 << 34)
+#define RSERR_FIFOOVERFLOW	(UINT64_CAST 1 << 33)
+#define RSERR_ILLEGALPORT	(UINT64_CAST 1 << 32)
+#define RSERR_DEADLOCKTO_SHFT	28
+#define RSERR_DEADLOCKTO_MASK	(UINT64_CAST 0xf << 28)
+#define RSERR_RECVTAILTO_SHFT	24
+#define RSERR_RECVTAILTO_MASK	(UINT64_CAST 0xf << 24)
+#define RSERR_RETRYCNT_SHFT	16
+#define RSERR_RETRYCNT_MASK	(UINT64_CAST 0xff << 16)
+#define RSERR_CBERRCNT_SHFT	8
+#define RSERR_CBERRCNT_MASK	(UINT64_CAST 0xff << 8)
+#define RSERR_SNERRCNT_SHFT	0
+#define RSERR_SNERRCNT_MASK	(UINT64_CAST 0xff << 0)
+
+
+#define PORT_STATUS_UP		(1 << 0)	/* Router link up */
+#define PORT_STATUS_FENCE	(1 << 1)	/* Router link fenced */
+#define PORT_STATUS_RESETFAIL	(1 << 2)	/* Router link didnot 
+						 * come out of reset */
+#define PORT_STATUS_DISCFAIL	(1 << 3)	/* Router link failed after 
+						 * out of reset but before
+						 * router tables were
+						 * programmed
+						 */
+#define PORT_STATUS_KERNFAIL	(1 << 4)	/* Router link failed
+						 * after reset and the 
+						 * router tables were
+						 * programmed
+						 */
+#define PORT_STATUS_UNDEF	(1 << 5)	/* Unable to pinpoint
+						 * why the router link
+						 * went down
+						 */	
+#define PROBE_RESULT_BAD	(-1)		/* Set if any of the router
+						 * links failed after reset
+						 */
+#define PROBE_RESULT_GOOD	(0)		/* Set if all the router links
+						 * which came out of reset 
+						 * are up
+						 */
+
+/* Should be enough for 256 CPUs */
+#define MAX_RTR_BREADTH		64		/* Max # of routers possible */
+
+/* Get the require set of bits in a var. corr to a sequence of bits  */
+#define GET_FIELD(var, fname) \
+        ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT)
+/* Set the require set of bits in a var. corr to a sequence of bits  */
+#define SET_FIELD(var, fname, fval) \
+        ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT)
+
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+
+typedef struct router_map_ent_s {
+	uint64_t	nic;
+	moduleid_t	module;
+	slotid_t	slot;
+} router_map_ent_t;
+
+struct rr_status_error_fmt {
+	uint64_t	rserr_unused		: 30,
+			rserr_fifooverflow	: 1,
+			rserr_illegalport	: 1,
+			rserr_deadlockto	: 4,
+			rserr_recvtailto	: 4,
+			rserr_retrycnt		: 8,
+			rserr_cberrcnt		: 8,
+			rserr_snerrcnt		: 8;
+};
+
+/*
+ * This type is used to store "absolute" counts of router events
+ */
+typedef int	router_count_t;
+
+/* All utilizations are on a scale from 0 - 1023. */
+#define RP_BYPASS_UTIL	0
+#define RP_RCV_UTIL	1
+#define RP_SEND_UTIL	2
+#define RP_TOTAL_PKTS	3	/* Free running clock/packet counter */
+
+#define RP_NUM_UTILS	3
+
+#define RP_HIST_REGS	2
+#define RP_NUM_BUCKETS  4
+#define RP_HIST_TYPES	3
+
+#define RP_AGE0		0
+#define RP_AGE1		1
+#define RP_AGE2		2
+#define RP_AGE3		3
+
+
+#define RR_UTIL_SCALE	1024
+
+/*
+ * Router port-oriented information
+ */
+typedef struct router_port_info_s {
+	router_reg_t	rp_histograms[RP_HIST_REGS];/* Port usage info */
+	router_reg_t	rp_port_error;		/* Port error info */
+	router_count_t	rp_retry_errors;	/* Total retry errors */
+	router_count_t	rp_sn_errors;		/* Total sn errors */
+	router_count_t	rp_cb_errors;		/* Total cb errors */
+	int		rp_overflows;		/* Total count overflows */
+	int		rp_excess_err;		/* Port has excessive errors */
+	ushort		rp_util[RP_NUM_BUCKETS];/* Port utilization */
+} router_port_info_t;
+
+#define ROUTER_INFO_VERSION	7
+
+struct lboard_s;
+
+/*
+ * Router information
+ */
+typedef struct router_info_s {
+	char		ri_version;	/* structure version		    */
+	cnodeid_t	ri_cnode;	/* cnode of its legal guardian hub  */
+	nasid_t		ri_nasid;	/* Nasid of same 		    */
+	char		ri_ledcache;	/* Last LED bitmap		    */
+	char		ri_leds;	/* Current LED bitmap		    */
+	char		ri_portmask;	/* Active port bitmap		    */
+	router_reg_t	ri_stat_rev_id;	/* Status rev ID value		    */
+	net_vec_t	ri_vector;	/* vector from guardian to router   */
+	int		ri_writeid;	/* router's vector write ID	    */
+	int64_t	ri_timebase;	/* Time of first sample		    */
+	int64_t	ri_timestamp;	/* Time of last sample		    */
+	router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info      */
+	moduleid_t	ri_module;	/* Which module are we in?	    */
+	slotid_t	ri_slotnum;	/* Which slot are we in?	    */
+	router_reg_t	ri_glbl_parms[GLBL_PARMS_REGS];
+					/* Global parms0&1 register contents*/
+	devfs_handle_t	ri_vertex;	/* hardware graph vertex            */
+	router_reg_t	ri_prot_conf;	/* protection config. register	    */
+	int64_t	ri_per_minute;	/* Ticks per minute		    */
+
+	/*
+	 * Everything below here is for kernel use only and may change at	
+	 * at any time with or without a change in teh revision number
+	 *
+	 * Any pointers or things that come and go with DEBUG must go at
+ 	 * the bottom of the structure, below the user stuff.
+	 */
+	char		ri_hist_type;   /* histogram type		    */
+	devfs_handle_t	ri_guardian;	/* guardian node for the router	    */
+	int64_t	ri_last_print;	/* When did we last print	    */
+	char		ri_print;	/* Should we print 		    */
+	char 		ri_just_blink;	/* Should we blink the LEDs         */
+	
+#ifdef DEBUG
+	int64_t	ri_deltatime;	/* Time it took to sample	    */
+#endif
+	lock_t		ri_lock;	/* Lock for access to router info   */
+	net_vec_t	*ri_vecarray;	/* Pointer to array of vectors	    */
+	struct lboard_s	*ri_brd;	/* Pointer to board structure	    */
+	char *		ri_name;	/* This board's hwg path 	    */
+        unsigned char	ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a 
+					message to availmon */
+} router_info_t;
+
+
+/* Router info location specifiers */
+
+#define RIP_PROMLOG			2	/* Router info in promlog */
+#define RIP_CONSOLE			4	/* Router info on console */
+
+#define ROUTER_INFO_PRINT(_rip,_where)	(_rip->ri_print |= _where)	
+					/* Set the field used to check if a 
+					 * router info can be printed
+					 */
+#define IS_ROUTER_INFO_PRINTED(_rip,_where)	\
+					(_rip->ri_print & _where)	
+					/* Was the router info printed to
+					 * the given location (_where) ?
+					 * Mainly used to prevent duplicate
+					 * router error states.
+					 */
+#define ROUTER_INFO_LOCK(_rip,_s)	_s = mutex_spinlock(&(_rip->ri_lock))
+					/* Take the lock on router info
+					 * to gain exclusive access
+					 */
+#define ROUTER_INFO_UNLOCK(_rip,_s)	mutex_spinunlock(&(_rip->ri_lock),_s)
+					/* Release the lock on router info */
+/* 
+ * Router info hanging in the nodepda 
+ */
+typedef struct nodepda_router_info_s {
+	devfs_handle_t 	router_vhdl;	/* vertex handle of the router 	    */
+	short		router_port;	/* port thru which we entered       */
+	short		router_portmask;
+	moduleid_t	router_module;	/* module in which router is there  */
+	slotid_t	router_slot;	/* router slot			    */
+	unsigned char	router_type;	/* kind of router 		    */
+	net_vec_t	router_vector;	/* vector from the guardian node    */
+
+	router_info_t	*router_infop;	/* info hanging off the hwg vertex  */
+	struct nodepda_router_info_s *router_next;
+	                                /* pointer to next element 	    */
+} nodepda_router_info_t;
+
+#define ROUTER_NAME_SIZE	20	/* Max size of a router name */
+
+#define NORMAL_ROUTER_NAME	"normal_router"
+#define NULL_ROUTER_NAME	"null_router"
+#define META_ROUTER_NAME	"meta_router"
+#define UNKNOWN_ROUTER_NAME	"unknown_router" 
+
+/* The following definitions are needed by the router traversing
+ * code either using the hardware graph or using vector operations.
+ */
+/* Structure of the router queue element */
+typedef struct router_elt_s {
+	union {
+		/* queue element structure during router probing */
+		struct {
+			/* number-in-a-can (unique) for the router */
+			nic_t		nic;	
+			/* vector route from the master hub to 
+			 * this router.
+			 */
+			net_vec_t	vec;	
+			/* port status */
+			uint64_t	status;	
+			char		port_status[MAX_ROUTER_PORTS + 1];
+		} r_elt;
+		/* queue element structure during router guardian 
+		 * assignment
+		 */
+		struct {
+			/* vertex handle for the router */
+			devfs_handle_t	vhdl;
+			/* guardian for this router */
+			devfs_handle_t	guard;	
+			/* vector router from the guardian to the router */
+			net_vec_t	vec;
+		} k_elt;
+	} u;
+	                        /* easy to use port status interpretation */
+} router_elt_t;
+
+/* structure of the router queue */
+
+typedef struct router_queue_s {
+	char		head;	/* Point where a queue element is inserted */
+	char		tail;	/* Point where a queue element is removed */
+	int		type;
+	router_elt_t	array[MAX_RTR_BREADTH];
+	                        /* Entries for queue elements */
+} router_queue_t;
+
+
+#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+
+/*
+ * RR_HISTOGRAM(_L) mask and shift definitions
+ * There are two 64 bit histogram registers, so the following macros take
+ * into account dealing with an array of 4 32 bit values indexed by _x
+ */
+
+#define RHIST_BUCKET_SHFT(_x)	(32 * ((_x) & 0x1))
+#define RHIST_BUCKET_MASK(_x)	(UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1))
+#define RHIST_GET_BUCKET(_x, _reg)	\
+	((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x))
+
+/*
+ * RR_RESET_MASK(_L) mask and shift definitions
+ */
+
+#define RRM_RESETOK(_L)		(UINT64_CAST 1 << ((_L) - 1))
+#define RRM_RESETOK_ALL		(UINT64_CAST 0x3f)
+
+/*
+ * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions
+ */
+
+#define RTABLE_SHFT(_L)		(4 * ((_L) - 1))
+#define RTABLE_MASK(_L)		(UINT64_CAST 0x7 << RTABLE_SHFT(_L))
+
+
+#define	ROUTERINFO_STKSZ	4096
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#if defined(_LANGUAGE_C_PLUS_PLUS)
+extern "C" {
+#endif
+
+int router_reg_read(router_info_t *rip, int regno, router_reg_t *val);
+int router_reg_write(router_info_t *rip, int regno, router_reg_t val);
+int router_get_info(devfs_handle_t routerv, router_info_t *, int);
+int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip);
+int router_set_leds(router_info_t *rip);
+void router_print_state(router_info_t *rip, int level,
+		   void (*pf)(int, char *, ...),int print_where);
+void capture_router_stats(router_info_t *rip);
+
+
+int 	probe_routers(void);
+void 	get_routername(unsigned char brd_type,char *rtrname);
+void 	router_guardians_set(devfs_handle_t hwgraph_root);
+int 	router_hist_reselect(router_info_t *, int64_t);
+#if defined(_LANGUAGE_C_PLUS_PLUS)
+}
+#endif
+#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+
+#endif /* _ASM_SN_SN1_ROUTER_H */
diff --git a/include/asm-ia64/sn/sn1/slotnum.h b/include/asm-ia64/sn/sn1/slotnum.h
new file mode 100644
index 000000000..e814d546a
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/slotnum.h
@@ -0,0 +1,86 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#ifndef _ASM_SN_SN1_SLOTNUM_H
+#define _ASM_SN_SN1_SLOTNUM_H
+
+#define SLOTNUM_MAXLENGTH	16
+
+/*
+ * This file attempts to define a slot number space across all slots
+ * a IP27 module.  Here, we deal with the top level slots.
+ *
+ *	Node slots
+ *	Router slots
+ *	Crosstalk slots
+ *
+ *	Other slots are children of their parent crosstalk slot:
+ *		PCI slots
+ *		VME slots
+ */
+// #include <slotnum.h>
+
+// #ifdef NOTDEF	/* moved to sys/slotnum.h */
+#define SLOTNUM_NODE_CLASS	0x00	/* Node   */
+#define SLOTNUM_ROUTER_CLASS	0x10	/* Router */
+#define SLOTNUM_XTALK_CLASS	0x20	/* Xtalk  */
+#define SLOTNUM_MIDPLANE_CLASS	0x30	/* Midplane */
+#define SLOTNUM_XBOW_CLASS	0x40	/* Xbow  */
+#define SLOTNUM_KNODE_CLASS	0x50	/* Kego node */
+#define SLOTNUM_INVALID_CLASS	0xf0	/* Invalid */
+
+#define SLOTNUM_CLASS_MASK	0xf0
+#define SLOTNUM_SLOT_MASK	0x0f
+
+#define SLOTNUM_GETCLASS(_sn)	((_sn) & SLOTNUM_CLASS_MASK)
+#define SLOTNUM_GETSLOT(_sn)	((_sn) & SLOTNUM_SLOT_MASK)
+// #endif	/* NOTDEF */
+
+/* This determines module to pnode mapping. */
+/* NODESLOTS_PER_MODULE has changed from 4 to 6
+ * to support the 12P 4IO configuration. This change
+ * helps in minimum  number of changes to code which
+ * depend on the number of node boards within a module.
+ */
+#define NODESLOTS_PER_MODULE		6
+#define NODESLOTS_PER_MODULE_SHFT	2
+
+#define HIGHEST_I2C_VISIBLE_NODESLOT	4
+#define	RTRSLOTS_PER_MODULE		2
+
+#if __KERNEL__
+#include <asm/sn/xtalk/xtalk.h>
+
+extern slotid_t xbwidget_to_xtslot(int crossbow, int widget);
+extern slotid_t hub_slotbits_to_slot(slotid_t slotbits);
+extern slotid_t hub_slot_to_crossbow(slotid_t hub_slot);
+extern slotid_t router_slotbits_to_slot(slotid_t slotbits);
+extern slotid_t get_node_slotid(nasid_t nasid);
+extern slotid_t get_my_slotid(void);
+extern slotid_t get_node_crossbow(nasid_t);
+extern xwidgetnum_t hub_slot_to_widget(slotid_t);
+extern void get_slotname(slotid_t, char *);
+extern void get_my_slotname(char *);
+extern slotid_t get_widget_slotnum(int xbow, int widget);
+extern void get_widget_slotname(int, int, char *);
+extern void router_slotbits_to_slotname(int, char *);
+extern slotid_t meta_router_slotbits_to_slot(slotid_t) ;
+extern slotid_t hub_slot_get(void);
+
+extern int node_can_talk_to_elsc(void);
+
+extern int  slot_to_widget(int) ;
+#define MAX_IO_SLOT_NUM		12
+#define MAX_NODE_SLOT_NUM	4
+#define MAX_ROUTER_SLOTNUM	2
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SN_SN1_SLOTNUM_H */
diff --git a/include/asm-ia64/sn/sn1/sn1.h b/include/asm-ia64/sn/sn1/sn1.h
new file mode 100644
index 000000000..e03c2847a
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/sn1.h
@@ -0,0 +1,34 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+/*
+ * sn1.h -- hardware specific defines for sn1 boards
+ * The defines used here are used to limit the size of 
+ * various datastructures in the PROM. eg. KLCFGINFO, MPCONF etc.
+ */
+
+#ifndef _ASM_SN_SN1_SN1_H
+#define _ASM_SN_SN1_SN1_H
+
+extern xwidgetnum_t hub_widget_id(nasid_t);
+extern nasid_t get_nasid(void);
+extern int	get_slice(void);
+extern int     is_fine_dirmode(void);
+extern hubreg_t get_hub_chiprev(nasid_t nasid);
+extern hubreg_t get_region(cnodeid_t);
+extern hubreg_t nasid_to_region(nasid_t);
+extern int      verify_snchip_rev(void);
+extern void 	ni_reset_port(void);
+
+#ifdef SN1_USE_POISON_BITS
+extern int hub_bte_poison_ok(void);
+#endif /* SN1_USE_POISON_BITS */
+
+#endif /* _ASM_SN_SN1_SN1_H */
diff --git a/include/asm-ia64/sn/sn1/uart16550.h b/include/asm-ia64/sn/sn1/uart16550.h
new file mode 100644
index 000000000..128796a8a
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/uart16550.h
@@ -0,0 +1,214 @@
+
+/*
+ * Definitions for 16550  chip
+ */
+
+	/* defined as offsets from the data register */
+#define REG_DAT     0   /* receive/transmit data */
+#define REG_ICR     1   /* interrupt control register */
+#define REG_ISR     2   /* interrupt status register */
+#define REG_FCR     2   /* fifo control register */
+#define REG_LCR     3   /* line control register */
+#define REG_MCR     4   /* modem control register */
+#define REG_LSR     5   /* line status register */
+#define REG_MSR     6   /* modem status register */
+#define REG_SCR     7   /* Scratch register      */
+#define REG_DLL     0   /* divisor latch (lsb) */
+#define REG_DLH     1   /* divisor latch (msb) */
+#define REG_EFR		2	/* 16650 enhanced feature register */
+
+/*
+ * 16450/16550 Registers Structure.
+ */
+
+/* Line Control Register */
+#define		LCR_WLS0	0x01	/*word length select bit 0 */	
+#define		LCR_WLS1	0x02	/*word length select bit 2 */	
+#define		LCR_STB	0x04		/* number of stop bits */
+#define		LCR_PEN	0x08		/* parity enable */
+#define		LCR_EPS	0x10		/* even parity select */
+#define		LCR_SETBREAK 0x40	/* break key */
+#define		LCR_DLAB	0x80	/* divisor latch access bit */
+#define 	LCR_RXLEN   0x03    /* # of data bits per received/xmitted char */
+#define 	LCR_STOP1   0x00
+#define 	LCR_STOP2   0x04
+#define 	LCR_PAREN   0x08
+#define 	LCR_PAREVN  0x10
+#define 	LCR_PARMARK 0x20
+#define 	LCR_SNDBRK  0x40
+#define 	LCR_DLAB    0x80
+
+
+#define		LCR_BITS5	0x00	/* 5 bits per char */
+#define		LCR_BITS6	0x01	/* 6 bits per char */
+#define		LCR_BITS7	0x02	/* 7 bits per char */
+#define		LCR_BITS8	0x03	/* 8 bits per char */
+
+#define		LCR_MASK_BITS_CHAR 		0x03
+#define 	LCR_MASK_STOP_BITS		0x04
+#define		LCR_MASK_PARITY_BITS	0x18
+
+
+/* Line Status Register */
+#define		LSR_RCA	0x01		/* data ready */
+#define		LSR_OVRRUN	0x02	/* overrun error */
+#define		LSR_PARERR	0x04	/* parity error */
+#define		LSR_FRMERR	0x08	/* framing error */
+#define		LSR_BRKDET 	0x10	/* a break has arrived */
+#define		LSR_XHRE	0x20	/* tx hold reg is now empty */
+#define		LSR_XSRE	0x40	/* tx shift reg is now empty */
+#define		LSR_RFBE	0x80	/* rx FIFO Buffer error */
+
+/* Interrupt Status Regisger */
+#define		ISR_MSTATUS	0x00
+#define		ISR_TxRDY	0x02
+#define		ISR_RxRDY	0x04
+#define		ISR_ERROR_INTR	0x08
+#define		ISR_FFTMOUT 0x0c	/* FIFO Timeout */
+#define		ISR_RSTATUS 0x06	/* Receiver Line status */
+
+/* Interrupt Enable Register */
+#define		ICR_RIEN	0x01	/* Received Data Ready */
+#define		ICR_TIEN	0x02	/* Tx Hold Register Empty */
+#define		ICR_SIEN	0x04	/* Receiver Line Status */
+#define		ICR_MIEN	0x08	/* Modem Status */
+
+/* Modem Control Register */
+#define		MCR_DTR		0x01	/* Data Terminal Ready */
+#define		MCR_RTS		0x02	/* Request To Send */
+#define		MCR_OUT1	0x04	/* Aux output - not used */
+#define		MCR_OUT2	0x08	/* turns intr to 386 on/off */	
+#define		MCR_LOOP	0x10	/* loopback for diagnostics */
+#define		MCR_AFE 	0x20	/* Auto flow control enable */
+
+/* Modem Status Register */
+#define		MSR_DCTS	0x01	/* Delta Clear To Send */
+#define		MSR_DDSR	0x02	/* Delta Data Set Ready */
+#define		MSR_DRI		0x04	/* Trail Edge Ring Indicator */
+#define		MSR_DDCD	0x08	/* Delta Data Carrier Detect */
+#define		MSR_CTS		0x10	/* Clear To Send */
+#define		MSR_DSR		0x20	/* Data Set Ready */
+#define		MSR_RI		0x40	/* Ring Indicator */
+#define		MSR_DCD		0x80	/* Data Carrier Detect */
+
+#define 	DELTAS(x) 	((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD))
+#define 	STATES(x) 	((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD))
+
+
+#define		FCR_FIFOEN	0x01	/* enable receive/transmit fifo */
+#define		FCR_RxFIFO	0x02	/* enable receive fifo */
+#define		FCR_TxFIFO	0x04	/* enable transmit fifo */
+#define 	FCR_MODE1	0x08	/* change to mode 1 */
+#define		RxLVL0		0x00	/* Rx fifo level at 1	*/
+#define		RxLVL1		0x40	/* Rx fifo level at 4 */
+#define		RxLVL2		0x80	/* Rx fifo level at 8 */
+#define		RxLVL3		0xc0	/* Rx fifo level at 14 */
+
+#define 	FIFOEN		(FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) 
+
+#define		FCT_TxMASK	0x30	/* mask for Tx trigger */
+#define		FCT_RxMASK	0xc0	/* mask for Rx trigger */
+
+/* enhanced festures register */
+#define		EFR_SFLOW	0x0f	/* various S/w Flow Controls */
+#define 	EFR_EIC		0x10	/* Enhanced Interrupt Control bit */
+#define 	EFR_SCD		0x20	/* Special Character Detect */
+#define 	EFR_RTS		0x40	/* RTS flow control */
+#define 	EFR_CTS		0x80	/* CTS flow control */
+
+/* Rx Tx software flow controls in 16650 enhanced mode */
+#define		SFLOW_Tx0	0x00	/* no Xmit flow control */
+#define		SFLOW_Tx1	0x08	/* Transmit Xon1, Xoff1 */
+#define		SFLOW_Tx2	0x04	/* Transmit Xon2, Xoff2 */
+#define		SFLOW_Tx3	0x0c	/* Transmit Xon1,Xon2, Xoff1,Xoff2 */
+#define		SFLOW_Rx0	0x00	/* no Rcv flow control */
+#define		SFLOW_Rx1	0x02	/* Receiver compares Xon1, Xoff1 */
+#define		SFLOW_Rx2	0x01	/* Receiver compares Xon2, Xoff2 */
+
+#define	ASSERT_DTR(x)		(x |= MCR_DTR)
+#define	ASSERT_RTS(x)		(x |= MCR_RTS)
+#define DU_RTS_ASSERTED(x)  (((x) & MCR_RTS) != 0)
+#define DU_RTS_ASSERT(x)    ((x) |= MCR_RTS)
+#define DU_RTS_DEASSERT(x)  ((x) &= ~MCR_RTS)
+
+
+/*
+ * ioctl(fd, I_STR, arg)
+ * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI
+ */
+#define SIOC        ('z' << 8)  /* z for z85130 */
+#define SIOC_EXTCLK (SIOC | 1)  /* select/de-select external clock */
+#define SIOC_RS422  (SIOC | 2)  /* select/de-select RS422 protocol */
+#define SIOC_ITIMER (SIOC | 3)  /* upstream timer adjustment */
+#define SIOC_LOOPBACK   (SIOC | 4)  /* diagnostic loopback test mode */
+
+
+/* channel control register */
+#define	DMA_INT_MASK		0xe0	/* ring intr mask */
+#define DMA_INT_TH25		0x20	/* 25% threshold */
+#define DMA_INT_TH50		0x40	/* 50% threshold */
+#define DMA_INT_TH75		0x60	/* 75% threshold */
+#define DMA_INT_EMPTY		0x80	/* ring buffer empty */
+#define DMA_INT_NEMPTY		0xa0	/* ring buffer not empty */
+#define DMA_INT_FULL		0xc0	/* ring buffer full */
+#define DMA_INT_NFULL		0xe0	/* ring buffer not full */
+
+#define DMA_CHANNEL_RESET	0x400	/* reset dma channel */
+#define DMA_ENABLE			0x200	/* enable DMA */
+
+/* peripheral controller intr status bits applicable to serial ports */
+#define ISA_SERIAL0_MASK 		0x03f00000	/* mask for port #1 intrs */
+#define ISA_SERIAL0_DIR			0x00100000	/* device intr request */
+#define ISA_SERIAL0_Tx_THIR		0x00200000	/* Transmit DMA threshold */
+#define ISA_SERIAL0_Tx_PREQ		0x00400000	/* Transmit DMA pair req */
+#define ISA_SERIAL0_Tx_MEMERR	0x00800000	/* Transmit DMA memory err */
+#define ISA_SERIAL0_Rx_THIR		0x01000000	/* Receive DMA threshold  */
+#define ISA_SERIAL0_Rx_OVERRUN	0x02000000	/* Receive DMA over-run  */
+
+#define ISA_SERIAL1_MASK 		0xfc000000	/* mask for port #1 intrs */
+#define ISA_SERIAL1_DIR			0x04000000	/* device intr request */
+#define ISA_SERIAL1_Tx_THIR		0x08000000	/* Transmit DMA threshold */
+#define ISA_SERIAL1_Tx_PREQ		0x10000000	/* Transmit DMA pair req */
+#define ISA_SERIAL1_Tx_MEMERR	0x20000000	/* Transmit DMA memory err */
+#define ISA_SERIAL1_Rx_THIR		0x40000000	/* Receive DMA threshold  */
+#define ISA_SERIAL1_Rx_OVERRUN	0x80000000	/* Receive DMA over-run  */
+
+#define MAX_RING_BLOCKS		128			/* 4096/32 */
+#define MAX_RING_SIZE		4096
+
+/* DMA Input Control Byte */
+#define	DMA_IC_OVRRUN	0x01	/* overrun error */
+#define	DMA_IC_PARERR	0x02	/* parity error */
+#define	DMA_IC_FRMERR	0x04	/* framing error */
+#define	DMA_IC_BRKDET 	0x08	/* a break has arrived */
+#define DMA_IC_VALID	0x80	/* pair is valid */
+
+/* DMA Output Control Byte */
+#define DMA_OC_TxINTR	0x20	/* set Tx intr after processing byte */
+#define DMA_OC_INVALID	0x00	/* invalid pair */
+#define DMA_OC_WTHR		0x40	/* Write byte to THR */
+#define DMA_OC_WMCR		0x80	/* Write byte to MCR */
+#define DMA_OC_DELAY	0xc0	/* time delay before next xmit */
+
+/* ring id's */
+#define RID_SERIAL0_TX	0x4		/* serial port 0, transmit ring buffer */
+#define RID_SERIAL0_RX	0x5		/* serial port 0, receive ring buffer */
+#define RID_SERIAL1_TX	0x6		/* serial port 1, transmit ring buffer */
+#define RID_SERIAL1_RX	0x7		/* serial port 1, receive ring buffer */
+
+#define CLOCK_XIN			22
+#define PRESCALER_DIVISOR	3
+#define CLOCK_ACE			7333333
+
+/*
+ * increment the ring offset. One way to do this would be to add b'100000.
+ * this would let the offset value roll over automatically when it reaches
+ * its maximum value (127). However when we use the offset, we must use
+ * the appropriate bits only by masking with 0xfe0.
+ * The other option is to shift the offset right by 5 bits and look at its
+ * value. Then increment if required and shift back
+ * note: 127 * 2^5 = 4064
+ */
+#define INC_RING_POINTER(x) \
+	( ((x & 0xffe0) < 4064) ? (x += 32) : 0 )
+
diff --git a/include/asm-ia64/sn/sn1/war.h b/include/asm-ia64/sn/sn1/war.h
new file mode 100644
index 000000000..a79bc7f85
--- /dev/null
+++ b/include/asm-ia64/sn/sn1/war.h
@@ -0,0 +1,25 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN1_WAR_H
+#define _ASM_SN_SN1_WAR_H
+
+/****************************************************************************
+ * Support macros and defitions for hardware workarounds in		    *
+ * early chip versions.                                                     *
+ ****************************************************************************/
+
+/*
+ * This is the bitmap of runtime-switched workarounds.
+ */
+typedef short warbits_t;
+
+extern int warbits_override;
+
+#endif /*  _ASM_SN_SN1_WAR_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
new file mode 100644
index 000000000..2239c26c3
--- /dev/null
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -0,0 +1,199 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ */
+
+
+#ifndef _ASM_IA64_SN_SN_CPUID_H
+#define _ASM_IA64_SN_SN_CPUID_H
+
+#include <linux/config.h>
+#include <asm/sn/mmzone_sn1.h>
+
+/*
+ * Functions for converting between cpuids, nodeids and NASIDs.
+ * 
+ * These are for SGI platforms only.
+ *
+ */
+
+
+
+
+/*
+ * The following assumes the following mappings for LID register values:
+ *
+ *         LID
+ *		31:24 - id   Contains the NASID
+ *		23:16 - eid  Contains 0-3 to identify the cpu on the node
+ *				bit 17 - synergy number
+ *				bit 16 - FSB number 
+ *
+ * 	   SAPICID
+ *		This is the same as 31:24 of LID
+ *
+ * The macros convert between cpuid & slice/fsb/synergy/nasid/cnodeid.
+ * These terms are described below:
+ *
+ *
+ *          -----   -----           -----   -----       CPU
+ *          | 0 |   | 1 |           | 2 |   | 3 |       SLICE
+ *          -----   -----           -----   -----
+ *            |       |               |       |
+ *            |       |               |       |
+ *          0 |       | 1           0 |       | 1       FSB
+ *             -------                 -------  
+ *                |                       |
+ *                |                       |
+ *             -------                 -------
+ *             |     |                 |     |
+ *             |  0  |                 |  1  |         SYNERGY
+ *             |     |                 |     |
+ *             -------                 -------
+ *                |                       |
+ *                |                       |
+ *             -------------------------------
+ *             |                             |
+ *             |         BEDROCK             |        NASID   (0..127)
+ *             |                             |        CNODEID (0..numnodes-1)
+ *             |                             |
+ *             |                             |
+ *             -------------------------------
+ *                           |
+ *
+ */
+
+
+
+#define sapicid_to_nasid(sid)		((sid) >> 8)
+#define sapicid_to_synergy(sid)		(((sid) >> 1) & 1)
+#define sapicid_to_fsb(sid)		((sid) & 1)
+#define sapicid_to_slice(sid)		((sid) & 3)
+
+/*
+ * NOTE: id & eid refer to Intels definitions of the LID register
+ *	(id = NASID, eid = slice)
+ * NOTE: on non-MP systems, only cpuid 0 exists
+ */
+#define id_eid_to_sapicid(id,eid)       (((id)<<8) | (eid))
+#define id_eid_to_cpuid(id,eid)         ((NASID_TO_CNODEID(id)<<2) | (eid))
+
+
+/*
+ * The following table/struct is for translating between sapicid and cpuids.
+ * It is also used for managing PTC coherency domains.
+ */
+typedef struct {
+	u8	domain;
+	u8	reserved;
+	u16	sapicid;
+} sn_sapicid_info_t;
+
+extern sn_sapicid_info_t	sn_sapicid_info[];	/* indexed by cpuid */
+
+
+
+/*
+ * cpuid_to_spaicid  - Convert a cpuid to a SAPIC id of the cpu. 
+ * The SAPIC id is the same as bits 31:16 of the LID register.
+ */
+static __inline__ int
+cpuid_to_spaicid(int cpuid)
+{
+#ifdef CONFIG_SMP
+	return cpu_physical_id(cpuid);
+#else
+	return ((ia64_get_lid() >> 16) & 0xffff);
+#endif
+}
+
+
+/*
+ * cpuid_to_fsb_slot  - convert a cpuid to the fsb slot number that it is in.
+ *   (there are 2 cpus per FSB. This function returns 0 or 1)
+ */
+static __inline__ int
+cpuid_to_fsb_slot(int cpuid)
+{
+	return sapicid_to_fsb(cpuid_to_spaicid(cpuid));
+}
+
+
+/*
+ * cpuid_to_synergy  - convert a cpuid to the synergy that it resides on
+ *   (there are 2 synergies per node. Function returns 0 or 1 to
+ *    specify which synergy the cpu is on)
+ */
+static __inline__ int
+cpuid_to_synergy(int cpuid)
+{
+	return sapicid_to_synergy(cpuid_to_spaicid(cpuid));
+}
+
+
+/*
+ * cpuid_to_slice  - convert a cpuid to the slice that it resides on
+ *  There are 4 cpus per node. This function returns 0 .. 3)
+ */
+static __inline__ int
+cpuid_to_slice(int cpuid)
+{
+	return sapicid_to_slice(cpuid_to_spaicid(cpuid));
+}
+
+
+/*
+ * cpuid_to_nasid  - convert a cpuid to the NASID that it resides on
+ */
+static __inline__ int
+cpuid_to_nasid(int cpuid)
+{
+	return sapicid_to_nasid(cpuid_to_spaicid(cpuid));
+}
+
+
+/*
+ * cpuid_to_cnodeid  - convert a cpuid to the cnode that it resides on
+ */
+static __inline__ int
+cpuid_to_cnodeid(int cpuid)
+{
+	return nasid_map[cpuid_to_nasid(cpuid)];
+}
+
+static __inline__ int
+cnodeid_to_nasid(int cnodeid)
+{
+	int i;
+	for (i = 0; i < MAXNASIDS; i++) {
+		if (nasid_map[i] == cnodeid) {
+			return(i);
+		}
+	}
+	return(-1);
+}
+
+static __inline__ int
+cnode_slice_to_cpuid(int cnodeid, int slice) {
+	return(id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),slice));
+}
+
+static __inline__ int
+cpuid_to_subnode(int cpuid) {
+	int ret = cpuid_to_slice(cpuid);
+	if (ret < 2) return 0;
+	else return 1;
+}
+
+static __inline__ int
+cpuid_to_localslice(int cpuid) {
+	return(cpuid_to_slice(cpuid) & 1);
+}
+
+
+#endif /* _ASM_IA64_SN_SN_CPUID_H */
diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h
new file mode 100644
index 000000000..fbbb8030e
--- /dev/null
+++ b/include/asm-ia64/sn/sn_fru.h
@@ -0,0 +1,49 @@
+/**************************************************************************
+ *									  *
+ *		 Copyright (C) 1992-1997, Silicon Graphics, Inc.	  *
+ *									  *
+ *  These coded instructions, statements, and computer programs	 contain  *
+ *  unpublished	 proprietary  information of Silicon Graphics, Inc., and  *
+ *  are protected by Federal copyright law.  They  may	not be disclosed  *
+ *  to	third  parties	or copied or duplicated in any form, in whole or  *
+ *  in part, without the prior written consent of Silicon Graphics, Inc.  *
+ *									  *
+ **************************************************************************/
+#ifndef __SYS_SN_SN0_FRU_H__
+#define __SYS_SN_SN0_FRU_H__
+
+#define MAX_DIMMS			8	 /* max # of dimm banks */
+#define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
+
+typedef unsigned char confidence_t;
+
+typedef struct kf_mem_s {
+	confidence_t km_confidence; /* confidence level that the memory is bad
+				     * is this necessary ?
+				     */
+	confidence_t km_dimm[MAX_DIMMS];
+				    /* confidence level that dimm[i] is bad
+				     *I think this is the right number
+				     */
+
+} kf_mem_t;
+
+typedef struct kf_cpu_s {
+	confidence_t	kc_confidence; /* confidence level that cpu is bad */
+	confidence_t	kc_icache; /* confidence level that instr. cache is bad */
+	confidence_t	kc_dcache; /* confidence level that data   cache is bad */
+	confidence_t	kc_scache; /* confidence level that sec.   cache is bad */
+	confidence_t	kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+} kf_cpu_t;
+
+
+typedef struct kf_pci_bus_s {
+	confidence_t	kpb_belief;	/* confidence level  that the  pci bus is bad */
+	confidence_t	kpb_pcidev_belief[MAX_PCIDEV];
+					/* confidence level that the pci dev is bad */
+} kf_pci_bus_t;
+
+
+
+#endif /* #ifdef __SYS_SN_SN0_FRU_H__ */
+
diff --git a/include/asm-ia64/sn/sn_private.h b/include/asm-ia64/sn/sn_private.h
new file mode 100644
index 000000000..e63ba5b38
--- /dev/null
+++ b/include/asm-ia64/sn/sn_private.h
@@ -0,0 +1,303 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_PRIVATE_H
+#define _ASM_SN_PRIVATE_H
+
+#include <linux/config.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xtalk_private.h>
+
+extern nasid_t master_nasid;
+
+extern hubreg_t get_region(cnodeid_t);
+extern hubreg_t	nasid_to_region(nasid_t);
+/* promif.c */
+#ifndef CONFIG_IA64_SGI_IO
+extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes);
+#endif
+extern void he_arcs_set_vectors(void);
+extern void mem_init(void);
+#ifndef CONFIG_IA64_SGI_IO
+extern int cpu_enabled(cpuid_t);
+#endif
+extern void cpu_unenable(cpuid_t);
+extern nasid_t get_lowest_nasid(void);
+extern __psunsigned_t get_master_bridge_base(void);
+extern void set_master_bridge_base(void);
+extern int check_nasid_equiv(nasid_t, nasid_t);
+extern nasid_t get_console_nasid(void);
+extern char get_console_pcislot(void);
+#ifndef CONFIG_IA64_SGI_IO
+extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
+#endif
+
+extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
+
+/* memsupport.c */
+extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
+extern int memory_present(paddr_t);
+extern int memory_read_accessible(paddr_t);
+extern int memory_write_accessible(paddr_t);
+extern void memory_set_access(paddr_t, int, int);
+extern void show_dir_state(paddr_t, void (*)(char *, ...));
+extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
+extern void set_dir_owner(paddr_t, int);
+extern void set_dir_state(paddr_t, int);
+extern void set_dir_state_POISONED(paddr_t);
+extern void set_dir_state_UNOWNED(paddr_t);
+extern int is_POISONED_dir_state(paddr_t);
+extern int is_UNOWNED_dir_state(paddr_t);
+extern void get_dir_ent(paddr_t paddr, int *state,
+			uint64_t *vec_ptr, hubreg_t *elo);
+
+/* intr.c */
+#if defined(NEW_INTERRUPTS)
+extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
+extern void intr_unreserve_level(cpuid_t cpu, int level);
+extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
+			intr_func_t intr_func, void *intr_arg,
+			intr_func_t intr_prefunc);
+extern int intr_disconnect_level(cpuid_t cpu, int bit);
+extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
+			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
+			      char *intr_name,int *resp_bit);
+#endif	/* NEW_INTERRUPTS */
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+extern void setrtvector(intr_func_t);
+extern void install_cpuintr(cpuid_t cpu);
+extern void install_dbgintr(cpuid_t cpu);
+extern void install_tlbintr(cpuid_t cpu);
+extern void hub_migrintr_init(cnodeid_t /*cnode*/);
+extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
+extern int cause_intr_disconnect(int level);
+extern void intr_reserve_hardwired(cnodeid_t);
+extern void intr_clear_all(nasid_t);
+extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
+extern int protected_broadcast(hubreg_t intrbit);
+
+/* error_dump.c */
+extern char *hub_rrb_err_type[];
+extern char *hub_wrb_err_type[];
+
+void nmi_dump(void);
+void install_cpu_nmi_handler(int slice);
+
+/* klclock.c */
+extern void hub_rtc_init(cnodeid_t);
+
+/* bte.c */
+void bte_lateinit(void);
+void bte_wait_for_xfer_completion(void *);
+
+/* klgraph.c */
+void klhwg_add_all_nodes(devfs_handle_t);
+void klhwg_add_all_modules(devfs_handle_t);
+
+/* klidbg.c */
+void install_klidbg_functions(void);
+
+/* klnuma.c */
+extern void replicate_kernel_text(int numnodes);
+extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
+extern void setup_replication_mask(int maxnodes);
+
+/* init.c */
+extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
+#ifndef CONFIG_IA64_SGI_IO
+extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
+extern void init_platform_pda(pda_t *ppda, cpuid_t cpu);
+#endif
+extern void per_cpu_init(void);
+extern void per_hub_init(cnodeid_t);
+#ifndef CONFIG_IA64_SGI_IO
+extern cpumask_t boot_cpumask;
+#endif
+extern int is_fine_dirmode(void);
+extern void update_node_information(cnodeid_t);
+ 
+#ifndef CONFIG_IA64_SGI_IO
+/* clksupport.c */
+extern void early_counter_intr(eframe_t *);
+#endif
+
+/* hubio.c */
+extern void hubio_init(void);
+extern void hub_merge_clean(nasid_t nasid);
+extern void hub_set_piomode(nasid_t nasid, int conveyor);
+
+/* huberror.c */
+extern void hub_error_init(cnodeid_t);
+extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
+extern void hubni_error_handler(char *, int);
+extern int check_ni_errors(void);
+
+/* Used for debugger to signal upper software a breakpoint has taken place */
+
+extern void		*debugger_update;
+extern __psunsigned_t	debugger_stopped;
+
+/* 
+ * IP27 piomap, created by hub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_piomap_s by generic xtalk routines.
+ */
+struct hub_piomap_s {
+	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
+	devfs_handle_t		hpio_hub;	/* which hub's mapping registers are set up */
+	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
+	char			hpio_bigwin_num;/* if big window map, which one */
+	int 			hpio_flags;	/* defined below */
+};
+/* hub_piomap flags */
+#define HUB_PIOMAP_IS_VALID		0x1
+#define HUB_PIOMAP_IS_BIGWINDOW		0x2
+#define HUB_PIOMAP_IS_FIXED		0x4
+
+#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
+#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
+#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
+
+#if TBD
+ /* Ensure that hpio_xtalk_info is first */
+ #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0)
+#endif
+
+
+/* 
+ * IP27 dmamap, created by hub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_dmamap_s by generic xtalk routines.
+ */
+struct hub_dmamap_s {
+	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
+	devfs_handle_t		hdma_hub;	/* which hub we go through */
+	int			hdma_flags;	/* defined below */
+};
+/* hub_dmamap flags */
+#define HUB_DMAMAP_IS_VALID		0x1
+#define HUB_DMAMAP_USED			0x2
+#define	HUB_DMAMAP_IS_FIXED		0x4
+
+#if TBD
+ /* Ensure that hdma_xtalk_info is first */
+ #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0)
+#endif
+
+/* 
+ * IP27 interrupt handle, created by hub_intr_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_intr_s by generic xtalk routines.
+ */
+struct hub_intr_s {
+	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
+	ilvl_t			i_swlevel;	/* software level for blocking intr */
+	cpuid_t			i_cpuid;	/* which cpu */
+	int			i_bit;		/* which bit */
+	int			i_flags;
+};
+/* flag values */
+#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
+#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
+
+#if TBD
+ /* Ensure that i_xtalk_info is first */
+ #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0)
+#endif
+
+
+/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */
+/* TBD: IP27-dependent stuff currently in nodepda.h should be here */
+typedef struct hubinfo_s {
+	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
+	cnodeid_t			h_cnodeid;	/* compact nodeid */
+	nasid_t				h_nasid;	/* nasid */
+
+	/* structures for PIO management */
+	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
+	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
+	sv_t				h_bwwait;	/* wait for big window to free */
+	spinlock_t			h_bwlock;	/* guard big window piomap's */
+	spinlock_t			h_crblock;      /* gaurd CRB error handling */
+	int				h_num_big_window_fixed;	/* count number of FIXED maps */
+	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
+	hub_intr_t			hub_ii_errintr;
+} *hubinfo_t;
+
+#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
+
+#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
+
+#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
+
+/*
+ * Hub info PIO map access functions.
+ */
+#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
+			(&hinfo->h_big_window_piomap[win])
+#define	hubinfo_swin_piomap_get(hinfo, win)	\
+			(&hinfo->h_small_window_piomap[win])
+	
+/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */
+/* TBD: IP27-dependent stuff currently in pda.h should be here */
+typedef struct cpuinfo_s {
+#ifndef CONFIG_IA64_SGI_IO
+	pda_t		*ci_cpupda;	/* pointer to CPU's private data area */
+#endif
+	cpuid_t		ci_cpuid;	/* CPU ID */
+} *cpuinfo_t;
+
+#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
+
+#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
+
+/* Special initialization function for xswitch vertices created during startup. */
+extern void xswitch_vertex_init(devfs_handle_t xswitch);
+
+extern xtalk_provider_t hub_provider;
+
+/* du.c */
+int ducons_write(char *buf, int len);
+
+/* memerror.c */
+
+extern void install_eccintr(cpuid_t cpu);
+extern void memerror_get_stats(cnodeid_t cnode,
+			       int *bank_stats, int *bank_stats_max);
+extern void probe_md_errors(nasid_t);
+/* sysctlr.c */
+extern void sysctlr_init(void);
+extern void sysctlr_power_off(int sdonly);
+extern void sysctlr_keepalive(void);
+
+#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
+
+/* Useful definitions to get the memory dimm given a physical
+ * address.
+ */
+#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
+extern void membank_pathname_get(paddr_t,char *);
+
+/* To redirect the output into the error buffer */
+#define errbuf_print(_s)	printf("#%s",_s)
+
+extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
+void bootstrap(void);
+
+/* sndrv.c */
+extern int sndrv_attach(devfs_handle_t vertex);
+
+#endif /* _ASM_SN_PRIVATE_H */
diff --git a/include/asm-ia64/sn/synergy.h b/include/asm-ia64/sn/synergy.h
new file mode 100644
index 000000000..c3cbf387c
--- /dev/null
+++ b/include/asm-ia64/sn/synergy.h
@@ -0,0 +1,127 @@
+#ifndef ASM_IA64_SN_SYNERGY_H
+#define ASM_IA64_SN_SYNERGY_H
+
+#include "asm/io.h"
+#include "asm/sn/intr_public.h"
+
+
+/*
+ * Definitions for the synergy asic driver
+ * 
+ * These are for SGI platforms only.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc
+ * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
+ */
+
+
+#define SSPEC_BASE	(0xe0000000000)
+#define LB_REG_BASE	(SSPEC_BASE + 0x0)
+
+#define VEC_MASK3A_ADDR	(0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK3B_ADDR	(0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK3A	(0x2a0)
+#define VEC_MASK3B	(0x2a8)
+
+#define VEC_MASK2A_ADDR	(0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK2B_ADDR	(0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK2A	(0x2b0)
+#define VEC_MASK2B	(0x2b8)
+
+#define VEC_MASK1A_ADDR	(0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK1B_ADDR	(0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK1A	(0x2c0)
+#define VEC_MASK1B	(0x2c8)
+
+#define VEC_MASK0A_ADDR	(0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK0B_ADDR	(0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK0A	(0x2d0)
+#define VEC_MASK0B	(0x2d8)
+
+#define WRITE_LOCAL_SYNERGY_REG(addr, value)	__synergy_out(addr, value)
+
+#define HUBREG_CAST             (volatile hubreg_t *)
+#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
+#define SYN_UNCACHED_SPACE      0xc000000000000000
+#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_LREG_BASE(_n)      (NODE_HSPEC_BASE(_n) + 0x30000000)
+#define RREG_BASE(_n)           (NODE_LREG_BASE(_n))
+#define REMOTE_HSPEC(_n, _x)    (HUBREG_CAST (RREG_BASE(_n) + (_x)))
+#define    HSPEC_SYNERGY0_0          0x04000000    /* Synergy0 Registers     */
+#define    HSPEC_SYNERGY1_0          0x05000000    /* Synergy1 Registers     */
+#define HS_SYNERGY_STRIDE               (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
+
+
+#define HUB_L(_a)                       *(_a)
+#define HUB_S(_a, _d)                   *(_a) = (_d)
+
+
+#define REMOTE_SYNERGY_LOAD(nasid, fsb, reg)  __remote_synergy_in(nasid, fsb, reg)
+#define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
+
+extern inline void
+__remote_synergy_out(int nasid, int fsb, unsigned long reg, unsigned long val) {
+	unsigned long addr = ((RREG_BASE(nasid)) + 
+		((HSPEC_SYNERGY0_0 | (fsb)*HS_SYNERGY_STRIDE) | ((reg) << 2)));
+
+	HUB_S((unsigned long *)(addr),      (val) >> 48);
+	HUB_S((unsigned long *)(addr+0x08), (val) >> 32);
+	HUB_S((unsigned long *)(addr+0x10), (val) >> 16);
+	HUB_S((unsigned long *)(addr+0x18), (val)      );
+	__ia64_mf_a();
+}
+
+extern inline unsigned long
+__remote_synergy_in(int nasid, int fsb, unsigned long reg) {
+	volatile unsigned long *addr = (unsigned long *) ((RREG_BASE(nasid)) + 
+		((HSPEC_SYNERGY0_0 | (fsb)*HS_SYNERGY_STRIDE) | (reg)));
+	unsigned long ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+extern inline void
+__synergy_out(unsigned long addr, unsigned long value)
+{
+	volatile unsigned long *adr = (unsigned long *)
+			(addr | __IA64_UNCACHED_OFFSET);
+
+	*adr = value;
+	__ia64_mf_a();
+}
+
+#define READ_LOCAL_SYNERGY_REG(addr)	__synergy_in(addr)
+
+extern inline unsigned long
+__synergy_in(unsigned long addr)
+{
+	unsigned long ret, *adr = (unsigned long *)
+			(addr | __IA64_UNCACHED_OFFSET);
+
+	ret = *adr;
+	__ia64_mf_a();
+	return ret;
+}
+
+struct sn1_intr_action {
+	void (*handler)(int, void *, struct pt_regs *);
+	void *intr_arg;
+	unsigned long flags;
+	struct sn1_intr_action * next;
+};
+
+typedef struct synergy_da_s {
+	hub_intmasks_t	s_intmasks;
+}synergy_da_t;
+
+struct sn1_cnode_action_list {
+	spinlock_t action_list_lock;
+	struct sn1_intr_action *action_list;
+};
+	
+
+/* Temporary defintions for testing: */
+
+#endif ASM_IA64_SN_SYNERGY_H
diff --git a/include/asm-ia64/sn/systeminfo.h b/include/asm-ia64/sn/systeminfo.h
new file mode 100644
index 000000000..9ac52b247
--- /dev/null
+++ b/include/asm-ia64/sn/systeminfo.h
@@ -0,0 +1,72 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SYSTEMINFO_H
+#define _ASM_SN_SYSTEMINFO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_SERIAL_SIZE 16
+
+typedef struct module_info_s {
+	uint64_t serial_num;
+	int mod_num;
+	char serial_str[MAX_SERIAL_SIZE];
+} module_info_t;
+
+
+
+/*
+ * Commands to sysinfo()
+ */
+
+#define SI_SYSNAME		1	/* return name of operating system */
+#define SI_HOSTNAME		2	/* return name of node */
+#define SI_RELEASE 		3	/* return release of operating system */
+#define SI_VERSION		4	/* return version field of utsname */
+#define SI_MACHINE		5	/* return kind of machine */
+#define SI_ARCHITECTURE		6	/* return instruction set arch */
+#define SI_HW_SERIAL		7	/* return hardware serial number */
+#define SI_HW_PROVIDER		8	/* return hardware manufacturer */
+#define SI_SRPC_DOMAIN		9	/* return secure RPC domain */
+#define SI_INITTAB_NAME	       10	/* return name of inittab file used */
+
+#define _MIPS_SI_VENDOR		100	/* return system provider */
+#define _MIPS_SI_OS_PROVIDER	101	/* return OS manufacturer */
+#define _MIPS_SI_OS_NAME	102	/* return OS name */
+#define _MIPS_SI_HW_NAME	103	/* return system name */
+#define _MIPS_SI_NUM_PROCESSORS	104	/* return number of processors */
+#define _MIPS_SI_HOSTID		105	/* return hostid */
+#define _MIPS_SI_OSREL_MAJ	106	/* return OS major release number */
+#define _MIPS_SI_OSREL_MIN	107	/* return OS minor release number */
+#define _MIPS_SI_OSREL_PATCH	108	/* return OS release number */
+#define _MIPS_SI_PROCESSORS	109	/* return CPU revison id */
+#define _MIPS_SI_AVAIL_PROCESSORS 110	/* return number of available processors */
+#define	_MIPS_SI_SERIAL		111
+/*
+ * These commands are unpublished interfaces to sysinfo().
+ */
+#define SI_SET_HOSTNAME		258	/* set name of node */
+					/*  -unpublished option */
+#define SI_SET_SRPC_DOMAIN	265	/* set secure RPC domain */
+					/* -unpublished option */
+
+#if !defined(__KERNEL__)
+int sysinfo(int, char *, long);
+int get_num_modules(void);
+int get_module_info(int, module_info_t *, size_t);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASM_SN_SYSTEMINFO_H */
diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h
new file mode 100644
index 000000000..7c5596634
--- /dev/null
+++ b/include/asm-ia64/sn/types.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_TYPES_H
+#define _ASM_SN_TYPES_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+typedef unsigned long 	cpuid_t;
+typedef unsigned long 	cpumask_t;
+/* typedef unsigned long	cnodemask_t; */
+typedef signed short	nasid_t;	/* node id in numa-as-id space */
+typedef signed short	cnodeid_t;	/* node id in compact-id space */
+typedef signed char	partid_t;	/* partition ID type */
+typedef signed short	moduleid_t;	/* user-visible module number type */
+typedef signed short	cmoduleid_t;	/* kernel compact module id type */
+typedef unsigned char	clusterid_t;	/* Clusterid of the cell */
+
+#if defined(CONFIG_IA64_SGI_IO)
+#define __psunsigned_t uint64_t
+#define lock_t uint64_t
+#define sv_t uint64_t
+
+typedef unsigned long iopaddr_t;
+typedef unsigned char uchar_t;
+typedef unsigned long paddr_t;
+typedef unsigned long pfn_t;
+#endif        /* CONFIG_IA64_SGI_IO */
+
+#endif /* _ASM_SN_TYPES_H */
diff --git a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h
new file mode 100644
index 000000000..9b064ac3d
--- /dev/null
+++ b/include/asm-ia64/sn/vector.h
@@ -0,0 +1,119 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_VECTOR_H
+#define _ASM_SN_VECTOR_H
+
+#include <linux/config.h>
+
+#define NET_VEC_NULL            ((net_vec_t)  0)
+#define NET_VEC_BAD             ((net_vec_t) -1)
+
+#ifdef RTL
+
+#define VEC_POLLS_W		16	/* Polls before write times out */
+#define VEC_POLLS_R		16	/* Polls before read times out */
+#define VEC_POLLS_X		16	/* Polls before exch times out */
+
+#define VEC_RETRIES_W		1	/* Retries before write fails */
+#define VEC_RETRIES_R		1	/* Retries before read fails */
+#define VEC_RETRIES_X		1	/* Retries before exch fails */
+
+#else /* RTL */
+
+#define VEC_POLLS_W		128	/* Polls before write times out */
+#define VEC_POLLS_R		128	/* Polls before read times out */
+#define VEC_POLLS_X		128	/* Polls before exch times out */
+
+#define VEC_RETRIES_W		8	/* Retries before write fails */
+#define VEC_RETRIES_R           8	/* Retries before read fails */
+#define VEC_RETRIES_X		4	/* Retries before exch fails */
+
+#endif /* RTL */
+
+#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#define VECTOR_PARMS		LB_VECTOR_PARMS
+#define VECTOR_ROUTE		LB_VECTOR_ROUTE
+#define VECTOR_DATA		LB_VECTOR_DATA
+#define VECTOR_STATUS		LB_VECTOR_STATUS
+#define VECTOR_RETURN		LB_VECTOR_RETURN
+#define VECTOR_READ_DATA	LB_VECTOR_READ_DATA
+#define VECTOR_STATUS_CLEAR	LB_VECTOR_STATUS_CLEAR
+#define VP_PIOID_SHFT		LVP_PIOID_SHFT
+#define VP_PIOID_MASK		LVP_PIOID_MASK
+#define VP_WRITEID_SHFT		LVP_WRITEID_SHFT
+#define VP_WRITEID_MASK		LVP_WRITEID_MASK
+#define VP_ADDRESS_MASK		LVP_ADDRESS_MASK
+#define VP_TYPE_SHFT		LVP_TYPE_SHFT
+#define VP_TYPE_MASK		LVP_TYPE_MASK
+#define VS_VALID		LVS_VALID
+#define VS_OVERRUN		LVS_OVERRUN
+#define VS_TARGET_SHFT		LVS_TARGET_SHFT
+#define VS_TARGET_MASK		LVS_TARGET_MASK
+#define VS_PIOID_SHFT		LVS_PIOID_SHFT
+#define VS_PIOID_MASK		LVS_PIOID_MASK
+#define VS_WRITEID_SHFT		LVS_WRITEID_SHFT
+#define VS_WRITEID_MASK		LVS_WRITEID_MASK
+#define VS_ADDRESS_MASK		LVS_ADDRESS_MASK
+#define VS_TYPE_SHFT		LVS_TYPE_SHFT
+#define VS_TYPE_MASK		LVS_TYPE_MASK
+#define VS_ERROR_MASK		LVS_ERROR_MASK
+#endif
+
+#define NET_ERROR_NONE          0       /* No error             */
+#define NET_ERROR_HARDWARE     -1       /* Hardware error       */
+#define NET_ERROR_OVERRUN      -2       /* Extra response(s)    */
+#define NET_ERROR_REPLY        -3       /* Reply parms mismatch */
+#define NET_ERROR_ADDRESS      -4       /* Addr error response  */
+#define NET_ERROR_COMMAND      -5       /* Cmd error response   */
+#define NET_ERROR_PROT         -6       /* Prot error response  */
+#define NET_ERROR_TIMEOUT      -7       /* Too many retries     */
+#define NET_ERROR_VECTOR       -8       /* Invalid vector/path  */
+#define NET_ERROR_ROUTERLOCK   -9       /* Timeout locking rtr  */
+#define NET_ERROR_INVAL	       -10	/* Invalid vector request */
+
+#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+typedef uint64_t              net_reg_t;
+typedef uint64_t              net_vec_t;
+
+int             vector_write(net_vec_t dest,
+                              int write_id, int address,
+                              uint64_t value);
+
+int             vector_read(net_vec_t dest,
+                             int write_id, int address,
+                             uint64_t *value);
+
+int             vector_write_node(net_vec_t dest, nasid_t nasid,
+                              int write_id, int address,
+                              uint64_t value);
+
+int             vector_read_node(net_vec_t dest, nasid_t nasid,
+                             int write_id, int address,
+                             uint64_t *value);
+
+int             vector_length(net_vec_t vec);
+net_vec_t       vector_get(net_vec_t vec, int n);
+net_vec_t       vector_prefix(net_vec_t vec, int n);
+net_vec_t       vector_modify(net_vec_t entry, int n, int route);
+net_vec_t       vector_reverse(net_vec_t vec);
+net_vec_t       vector_concat(net_vec_t vec1, net_vec_t vec2);
+
+char		*net_errmsg(int);
+
+#ifndef _STANDALONE
+int hub_vector_write(cnodeid_t cnode, net_vec_t vector, int writeid,
+	int addr, net_reg_t value);
+int hub_vector_read(cnodeid_t cnode, net_vec_t vector, int writeid,
+	int addr, net_reg_t *value);
+#endif
+
+#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+
+#endif /* _ASM_SN_VECTOR_H */
diff --git a/include/asm-ia64/sn/war.h b/include/asm-ia64/sn/war.h
new file mode 100644
index 000000000..867e125f0
--- /dev/null
+++ b/include/asm-ia64/sn/war.h
@@ -0,0 +1,18 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_WAR_H
+#define _ASM_SN_WAR_H
+
+#include <linux/config.h>
+#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#include <asm/sn/sn1/war.h>
+#endif
+
+#endif /* _ASM_SN_WAR_H */
diff --git a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h
new file mode 100644
index 000000000..c2b71497b
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xbow.h
@@ -0,0 +1,895 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_SN_XTALK_XBOW_H
+#define _ASM_SN_SN_XTALK_XBOW_H
+
+/*
+ * xbow.h - header file for crossbow chip and xbow section of xbridge
+ */
+
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xswitch.h>
+#ifdef LANGUAGE_C
+#include <asm/sn/xtalk/xbow_info.h>
+#endif
+
+
+#define	XBOW_DRV_PREFIX	"xbow_"
+
+/* The crossbow chip supports 8 8/16 bits I/O ports, numbered 0x8 through 0xf.
+ * It also implements the widget 0 address space and register set.
+ */
+#define XBOW_PORT_0	0x0
+#define XBOW_PORT_8	0x8
+#define XBOW_PORT_9	0x9
+#define XBOW_PORT_A	0xa
+#define XBOW_PORT_B	0xb
+#define XBOW_PORT_C	0xc
+#define XBOW_PORT_D	0xd
+#define XBOW_PORT_E	0xe
+#define XBOW_PORT_F	0xf
+
+#define MAX_XBOW_PORTS	8	/* number of ports on xbow chip */
+#define BASE_XBOW_PORT	XBOW_PORT_8	/* Lowest external port */
+#define MAX_PORT_NUM	0x10	/* maximum port number + 1 */
+#define XBOW_WIDGET_ID	0	/* xbow is itself widget 0 */
+
+#define	XBOW_CREDIT	4
+
+#define MAX_XBOW_NAME 	16
+
+#if LANGUAGE_C
+typedef uint32_t      xbowreg_t;
+
+#define XBOWCONST	(xbowreg_t)
+
+/* Generic xbow register, given base and offset */
+#define XBOW_REG_PTR(base, offset) ((volatile xbowreg_t*) \
+	((__psunsigned_t)(base) + (__psunsigned_t)(offset)))
+
+/* Register set for each xbow link */
+typedef volatile struct xb_linkregs_s {
+#ifdef LITTLE_ENDIAN
+/* 
+ * we access these through synergy unswizzled space, so the address
+ * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
+ * That's why we put the register first and filler second.
+ */
+    xbowreg_t               link_ibf;
+    xbowreg_t               filler0;	/* filler for proper alignment */
+    xbowreg_t               link_control;
+    xbowreg_t               filler1;
+    xbowreg_t               link_status;
+    xbowreg_t               filler2;
+    xbowreg_t               link_arb_upper;
+    xbowreg_t               filler3;
+    xbowreg_t               link_arb_lower;
+    xbowreg_t               filler4;
+    xbowreg_t               link_status_clr;
+    xbowreg_t               filler5;
+    xbowreg_t               link_reset;
+    xbowreg_t               filler6;
+    xbowreg_t               link_aux_status;
+    xbowreg_t               filler7;
+#else
+    xbowreg_t               filler0;	/* filler for proper alignment */
+    xbowreg_t               link_ibf;
+    xbowreg_t               filler1;
+    xbowreg_t               link_control;
+    xbowreg_t               filler2;
+    xbowreg_t               link_status;
+    xbowreg_t               filler3;
+    xbowreg_t               link_arb_upper;
+    xbowreg_t               filler4;
+    xbowreg_t               link_arb_lower;
+    xbowreg_t               filler5;
+    xbowreg_t               link_status_clr;
+    xbowreg_t               filler6;
+    xbowreg_t               link_reset;
+    xbowreg_t               filler7;
+    xbowreg_t               link_aux_status;
+#endif /* LITTLE_ENDIAN */
+} xb_linkregs_t;
+
+typedef volatile struct xbow_s {
+    /* standard widget configuration                       0x000000-0x000057 */
+    widget_cfg_t            xb_widget;  /* 0x000000 */
+
+    /* helper fieldnames for accessing bridge widget */
+
+#define xb_wid_id                       xb_widget.w_id
+#define xb_wid_stat                     xb_widget.w_status
+#define xb_wid_err_upper                xb_widget.w_err_upper_addr
+#define xb_wid_err_lower                xb_widget.w_err_lower_addr
+#define xb_wid_control                  xb_widget.w_control
+#define xb_wid_req_timeout              xb_widget.w_req_timeout
+#define xb_wid_int_upper                xb_widget.w_intdest_upper_addr
+#define xb_wid_int_lower                xb_widget.w_intdest_lower_addr
+#define xb_wid_err_cmdword              xb_widget.w_err_cmd_word
+#define xb_wid_llp                      xb_widget.w_llp_cfg
+#define xb_wid_stat_clr                 xb_widget.w_tflush
+
+#ifdef LITTLE_ENDIAN
+/* 
+ * we access these through synergy unswizzled space, so the address
+ * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
+ * That's why we put the register first and filler second.
+ */
+    /* xbow-specific widget configuration                  0x000058-0x0000FF */
+    xbowreg_t               xb_wid_arb_reload;  /* 0x00005C */
+    xbowreg_t               _pad_000058;
+    xbowreg_t               xb_perf_ctr_a;      /* 0x000064 */
+    xbowreg_t               _pad_000060;
+    xbowreg_t               xb_perf_ctr_b;      /* 0x00006c */
+    xbowreg_t               _pad_000068;
+    xbowreg_t               xb_nic;     /* 0x000074 */
+    xbowreg_t               _pad_000070;
+
+    /* Xbridge only */
+    xbowreg_t               xb_w0_rst_fnc;      /* 0x00007C */
+    xbowreg_t               _pad_000078;
+    xbowreg_t               xb_l8_rst_fnc;      /* 0x000084 */
+    xbowreg_t               _pad_000080;
+    xbowreg_t               xb_l9_rst_fnc;      /* 0x00008c */
+    xbowreg_t               _pad_000088;
+    xbowreg_t               xb_la_rst_fnc;      /* 0x000094 */
+    xbowreg_t               _pad_000090;
+    xbowreg_t               xb_lb_rst_fnc;      /* 0x00009c */
+    xbowreg_t               _pad_000098;
+    xbowreg_t               xb_lc_rst_fnc;      /* 0x0000a4 */
+    xbowreg_t               _pad_0000a0;
+    xbowreg_t               xb_ld_rst_fnc;      /* 0x0000ac */
+    xbowreg_t               _pad_0000a8;
+    xbowreg_t               xb_le_rst_fnc;      /* 0x0000b4 */
+    xbowreg_t               _pad_0000b0;
+    xbowreg_t               xb_lf_rst_fnc;      /* 0x0000bc */
+    xbowreg_t               _pad_0000b8;
+    xbowreg_t               xb_lock;            /* 0x0000c4 */
+    xbowreg_t               _pad_0000c0;
+    xbowreg_t               xb_lock_clr;        /* 0x0000cc */
+    xbowreg_t               _pad_0000c8;
+    /* end of Xbridge only */
+    xbowreg_t               _pad_0000d0[12];
+#else
+    /* xbow-specific widget configuration                  0x000058-0x0000FF */
+    xbowreg_t               _pad_000058;
+    xbowreg_t               xb_wid_arb_reload;  /* 0x00005C */
+    xbowreg_t               _pad_000060;
+    xbowreg_t               xb_perf_ctr_a;      /* 0x000064 */
+    xbowreg_t               _pad_000068;
+    xbowreg_t               xb_perf_ctr_b;      /* 0x00006c */
+    xbowreg_t               _pad_000070;
+    xbowreg_t               xb_nic;     /* 0x000074 */
+
+    /* Xbridge only */
+    xbowreg_t               _pad_000078;
+    xbowreg_t               xb_w0_rst_fnc;      /* 0x00007C */
+    xbowreg_t               _pad_000080;
+    xbowreg_t               xb_l8_rst_fnc;      /* 0x000084 */
+    xbowreg_t               _pad_000088;
+    xbowreg_t               xb_l9_rst_fnc;      /* 0x00008c */
+    xbowreg_t               _pad_000090;
+    xbowreg_t               xb_la_rst_fnc;      /* 0x000094 */
+    xbowreg_t               _pad_000098;
+    xbowreg_t               xb_lb_rst_fnc;      /* 0x00009c */
+    xbowreg_t               _pad_0000a0;
+    xbowreg_t               xb_lc_rst_fnc;      /* 0x0000a4 */
+    xbowreg_t               _pad_0000a8;
+    xbowreg_t               xb_ld_rst_fnc;      /* 0x0000ac */
+    xbowreg_t               _pad_0000b0;
+    xbowreg_t               xb_le_rst_fnc;      /* 0x0000b4 */
+    xbowreg_t               _pad_0000b8;
+    xbowreg_t               xb_lf_rst_fnc;      /* 0x0000bc */
+    xbowreg_t               _pad_0000c0;
+    xbowreg_t               xb_lock;            /* 0x0000c4 */
+    xbowreg_t               _pad_0000c8;
+    xbowreg_t               xb_lock_clr;        /* 0x0000cc */
+    /* end of Xbridge only */
+    xbowreg_t               _pad_0000d0[12];
+#endif /* LITTLE_ENDIAN */
+
+    /* Link Specific Registers, port 8..15                 0x000100-0x000300 */
+    xb_linkregs_t           xb_link_raw[MAX_XBOW_PORTS];
+#define xb_link(p)      xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
+
+} xbow_t;
+
+/* Configuration structure which describes each xbow link */
+typedef struct xbow_cfg_s {
+    int			    xb_port;	/* port number (0-15) */
+    int			    xb_flags;	/* port software flags */
+    short		    xb_shift;	/* shift for arb reg (mask is 0xff) */
+    short		    xb_ul;	/* upper or lower arb reg */
+    int			    xb_pad;	/* use this later (pad to ptr align) */
+    xb_linkregs_t	   *xb_linkregs;	/* pointer to link registers */
+    widget_cfg_t	   *xb_widget;	/* pointer to widget registers */
+    char		    xb_name[MAX_XBOW_NAME];	/* port name */
+    xbowreg_t		    xb_sh_arb_upper;	/* shadow upper arb register */
+    xbowreg_t		    xb_sh_arb_lower;	/* shadow lower arb register */
+} xbow_cfg_t;
+
+#define XB_FLAGS_EXISTS		0x1	/* device exists */
+#define XB_FLAGS_MASTER		0x2
+#define XB_FLAGS_SLAVE		0x0
+#define XB_FLAGS_GBR		0x4
+#define XB_FLAGS_16BIT		0x8
+#define XB_FLAGS_8BIT		0x0
+
+/* get xbow config information for port p */
+#define XB_CONFIG(p)	xbow_cfg[xb_ports[p]]
+
+/* is widget port number valid?  (based on version 7.0 of xbow spec) */
+#define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
+
+/* whether to use upper or lower arbitration register, given source widget id */
+#define XBOW_ARB_IS_UPPER(wid) 	((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
+#define XBOW_ARB_IS_LOWER(wid) 	((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
+
+/* offset of arbitration register, given source widget id */
+#define XBOW_ARB_OFF(wid) 	(XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
+
+#endif				/* LANGUAGE_C */
+
+#define	XBOW_WID_ID		WIDGET_ID
+#define	XBOW_WID_STAT		WIDGET_STATUS
+#define	XBOW_WID_ERR_UPPER	WIDGET_ERR_UPPER_ADDR
+#define	XBOW_WID_ERR_LOWER	WIDGET_ERR_LOWER_ADDR
+#define	XBOW_WID_CONTROL	WIDGET_CONTROL
+#define	XBOW_WID_REQ_TO		WIDGET_REQ_TIMEOUT
+#define	XBOW_WID_INT_UPPER	WIDGET_INTDEST_UPPER_ADDR
+#define	XBOW_WID_INT_LOWER	WIDGET_INTDEST_LOWER_ADDR
+#define	XBOW_WID_ERR_CMDWORD	WIDGET_ERR_CMD_WORD
+#define	XBOW_WID_LLP		WIDGET_LLP_CFG
+#define	XBOW_WID_STAT_CLR	WIDGET_TFLUSH
+#define XBOW_WID_ARB_RELOAD 	0x5c
+#define XBOW_WID_PERF_CTR_A 	0x64
+#define XBOW_WID_PERF_CTR_B 	0x6c
+#define XBOW_WID_NIC 		0x74
+
+/* Xbridge only */
+#define XBOW_W0_RST_FNC		0x00007C
+#define	XBOW_L8_RST_FNC		0x000084
+#define	XBOW_L9_RST_FNC		0x00008c
+#define	XBOW_LA_RST_FNC		0x000094
+#define	XBOW_LB_RST_FNC		0x00009c
+#define	XBOW_LC_RST_FNC		0x0000a4
+#define	XBOW_LD_RST_FNC		0x0000ac
+#define	XBOW_LE_RST_FNC		0x0000b4
+#define	XBOW_LF_RST_FNC		0x0000bc
+#define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
+				(XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
+				((x) == 0) ? XBOW_W0_RST_FNC : 0
+#define XBOW_LOCK		0x0000c4
+#define XBOW_LOCK_CLR		0x0000cc
+/* End of Xbridge only */
+
+/* used only in ide, but defined here within the reserved portion */
+/*              of the widget0 address space (before 0xf4) */
+#define	XBOW_WID_UNDEF		0xe4
+
+/* pointer to link arbitration register, given xbow base, dst and src widget id */
+#define XBOW_PRIO_ARBREG_PTR(base, dst_wid, src_wid) \
+	XBOW_REG_PTR(XBOW_PRIO_LINKREGS_PTR(base, dst_wid), XBOW_ARB_OFF(src_wid))
+
+/* pointer to link registers base, given xbow base and destination widget id */
+#define XBOW_PRIO_LINKREGS_PTR(base, dst_wid) (xb_linkregs_t*) \
+	XBOW_REG_PTR(base, XB_LINK_REG_BASE(dst_wid))
+
+/* xbow link register set base, legal value for x is 0x8..0xf */
+#define	XB_LINK_BASE		0x100
+#define	XB_LINK_OFFSET		0x40
+#define	XB_LINK_REG_BASE(x)	(XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
+
+#define	XB_LINK_IBUF_FLUSH(x)	(XB_LINK_REG_BASE(x) + 0x4)
+#define	XB_LINK_CTRL(x)		(XB_LINK_REG_BASE(x) + 0xc)
+#define	XB_LINK_STATUS(x)	(XB_LINK_REG_BASE(x) + 0x14)
+#define	XB_LINK_ARB_UPPER(x)	(XB_LINK_REG_BASE(x) + 0x1c)
+#define	XB_LINK_ARB_LOWER(x)	(XB_LINK_REG_BASE(x) + 0x24)
+#define	XB_LINK_STATUS_CLR(x)	(XB_LINK_REG_BASE(x) + 0x2c)
+#define	XB_LINK_RESET(x)	(XB_LINK_REG_BASE(x) + 0x34)
+#define	XB_LINK_AUX_STATUS(x)	(XB_LINK_REG_BASE(x) + 0x3c)
+
+/* link_control(x) */
+#define	XB_CTRL_LINKALIVE_IE		0x80000000	/* link comes alive */
+     /* reserved:			0x40000000 */
+#define	XB_CTRL_PERF_CTR_MODE_MSK	0x30000000	/* perf counter mode */
+#define	XB_CTRL_IBUF_LEVEL_MSK		0x0e000000	/* input packet buffer level */
+#define	XB_CTRL_8BIT_MODE		0x01000000	/* force link into 8 bit mode */
+#define XB_CTRL_BAD_LLP_PKT		0x00800000	/* force bad LLP packet */
+#define XB_CTRL_WIDGET_CR_MSK		0x007c0000	/* LLP widget credit mask */
+#define XB_CTRL_WIDGET_CR_SHFT	18			/* LLP widget credit shift */
+#define XB_CTRL_ILLEGAL_DST_IE		0x00020000	/* illegal destination */
+#define XB_CTRL_OALLOC_IBUF_IE		0x00010000	/* overallocated input buffer */
+     /* reserved:			0x0000fe00 */
+#define XB_CTRL_BNDWDTH_ALLOC_IE	0x00000100	/* bandwidth alloc */
+#define XB_CTRL_RCV_CNT_OFLOW_IE	0x00000080	/* rcv retry overflow */
+#define XB_CTRL_XMT_CNT_OFLOW_IE	0x00000040	/* xmt retry overflow */
+#define XB_CTRL_XMT_MAX_RTRY_IE		0x00000020	/* max transmit retry */
+#define XB_CTRL_RCV_IE			0x00000010	/* receive */
+#define XB_CTRL_XMT_RTRY_IE		0x00000008	/* transmit retry */
+     /* reserved:			0x00000004 */
+#define	XB_CTRL_MAXREQ_TOUT_IE		0x00000002	/* maximum request timeout */
+#define	XB_CTRL_SRC_TOUT_IE		0x00000001	/* source timeout */
+
+/* link_status(x) */
+#define	XB_STAT_LINKALIVE		XB_CTRL_LINKALIVE_IE
+     /* reserved:			0x7ff80000 */
+#define	XB_STAT_MULTI_ERR		0x00040000	/* multi error */
+#define	XB_STAT_ILLEGAL_DST_ERR		XB_CTRL_ILLEGAL_DST_IE
+#define	XB_STAT_OALLOC_IBUF_ERR		XB_CTRL_OALLOC_IBUF_IE
+#define	XB_STAT_BNDWDTH_ALLOC_ID_MSK	0x0000ff00	/* port bitmask */
+#define	XB_STAT_RCV_CNT_OFLOW_ERR	XB_CTRL_RCV_CNT_OFLOW_IE
+#define	XB_STAT_XMT_CNT_OFLOW_ERR	XB_CTRL_XMT_CNT_OFLOW_IE
+#define	XB_STAT_XMT_MAX_RTRY_ERR	XB_CTRL_XMT_MAX_RTRY_IE
+#define	XB_STAT_RCV_ERR			XB_CTRL_RCV_IE
+#define	XB_STAT_XMT_RTRY_ERR		XB_CTRL_XMT_RTRY_IE
+     /* reserved:			0x00000004 */
+#define	XB_STAT_MAXREQ_TOUT_ERR		XB_CTRL_MAXREQ_TOUT_IE
+#define	XB_STAT_SRC_TOUT_ERR		XB_CTRL_SRC_TOUT_IE
+
+/* link_aux_status(x) */
+#define	XB_AUX_STAT_RCV_CNT	0xff000000
+#define	XB_AUX_STAT_XMT_CNT	0x00ff0000
+#define	XB_AUX_STAT_TOUT_DST	0x0000ff00
+#define	XB_AUX_LINKFAIL_RST_BAD	0x00000040
+#define	XB_AUX_STAT_PRESENT	0x00000020
+#define	XB_AUX_STAT_PORT_WIDTH	0x00000010
+     /*	reserved:		0x0000000f */
+
+/*
+ * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
+ * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
+ */
+#define	XB_ARB_GBR_MSK		0x1f
+#define	XB_ARB_RR_MSK		0x7
+#define	XB_ARB_GBR_SHFT(x)	(((x) & 0x3) * 8)
+#define	XB_ARB_RR_SHFT(x)	(((x) & 0x3) * 8 + 5)
+#define	XB_ARB_GBR_CNT(reg,x)	((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
+#define	XB_ARB_RR_CNT(reg,x)	((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
+
+/* XBOW_WID_STAT */
+#define	XB_WID_STAT_LINK_INTR_SHFT	(24)
+#define	XB_WID_STAT_LINK_INTR_MASK	(0xFF << XB_WID_STAT_LINK_INTR_SHFT)
+#define	XB_WID_STAT_LINK_INTR(x)	(0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
+#define	XB_WID_STAT_WIDGET0_INTR	0x00800000
+#define XB_WID_STAT_SRCID_MASK		0x000003c0	/* Xbridge only */
+#define	XB_WID_STAT_REG_ACC_ERR		0x00000020
+#define XB_WID_STAT_RECV_TOUT		0x00000010	/* Xbridge only */
+#define XB_WID_STAT_ARB_TOUT		0x00000008	/* Xbridge only */
+#define	XB_WID_STAT_XTALK_ERR		0x00000004
+#define XB_WID_STAT_DST_TOUT		0x00000002	/* Xbridge only */
+#define	XB_WID_STAT_MULTI_ERR		0x00000001
+
+#define XB_WID_STAT_SRCID_SHFT		6
+
+/* XBOW_WID_CONTROL */
+#define XB_WID_CTRL_REG_ACC_IE		XB_WID_STAT_REG_ACC_ERR
+#define XB_WID_CTRL_RECV_TOUT		XB_WID_STAT_RECV_TOUT
+#define XB_WID_CTRL_ARB_TOUT		XB_WID_STAT_ARB_TOUT
+#define XB_WID_CTRL_XTALK_IE		XB_WID_STAT_XTALK_ERR
+
+/* XBOW_WID_INT_UPPER */
+/* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
+
+/* XBOW WIDGET part number, in the ID register */
+#define XBOW_WIDGET_PART_NUM	0x0		/* crossbow */
+#define XXBOW_WIDGET_PART_NUM	0xd000		/* Xbridge */
+#define	XBOW_WIDGET_MFGR_NUM	0x0
+#define	XXBOW_WIDGET_MFGR_NUM	0x0
+
+#define	XBOW_REV_1_0		0x1	/* xbow rev 1.0 is "1" */
+#define	XBOW_REV_1_1		0x2	/* xbow rev 1.1 is "2" */
+#define XBOW_REV_1_2		0x3	/* xbow rev 1.2 is "3" */
+#define XBOW_REV_1_3		0x4	/* xbow rev 1.3 is "4" */
+#define XBOW_REV_2_0		0x5	/* xbow rev 2.0 is "5" */
+
+#define XXBOW_PART_REV_1_0		(XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
+#define XXBOW_PART_REV_2_0		(XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
+
+/* XBOW_WID_ARB_RELOAD */
+#define	XBOW_WID_ARB_RELOAD_INT	0x3f	/* GBR reload interval */
+
+
+#define nasid_has_xbridge(nasid)	\
+	(XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM)
+
+
+#ifdef _LANGUAGE_C
+/*
+ * XBOW Widget 0 Register formats.
+ * Format for many of these registers are similar to the standard
+ * widget register format described as part of xtalk specification
+ * Standard widget register field format description is available in
+ * xwidget.h
+ * Following structures define the format for xbow widget 0 registers
+ */
+/*
+ * Xbow Widget 0 Command error word
+ */
+#ifdef LITTLE_ENDIAN
+
+typedef union xbw0_cmdword_u {
+    xbowreg_t               cmdword;
+    struct {
+	uint32_t              rsvd:8,		/* Reserved */
+                                barr:1,         /* Barrier operation */
+                                error:1,        /* Error Occured */
+                                vbpm:1,         /* Virtual Backplane message */
+                                gbr:1,  /* GBR enable ?                 */
+                                ds:2,   /* Data size                    */
+                                ct:1,   /* Is it a coherent transaction */
+                                tnum:5,         /* Transaction Number */
+                                pactyp:4,       /* Packet type: */
+                                srcid:4,        /* Source ID number */
+                                destid:4;       /* Desination ID number */
+
+    } xbw0_cmdfield;
+} xbw0_cmdword_t;
+
+#else
+
+typedef union xbw0_cmdword_u {
+    xbowreg_t		    cmdword;
+    struct {
+	uint32_t		destid:4,	/* Desination ID number */
+				srcid:4,	/* Source ID number */
+				pactyp:4,	/* Packet type: */
+				tnum:5,		/* Transaction Number */
+				ct:1,	/* Is it a coherent transaction */
+				ds:2,	/* Data size			*/
+				gbr:1,	/* GBR enable ?			*/
+				vbpm:1,		/* Virtual Backplane message */
+				error:1,	/* Error Occured */
+				barr:1,		/* Barrier operation */
+				rsvd:8;		/* Reserved */
+    } xbw0_cmdfield;
+} xbw0_cmdword_t;
+
+#endif
+
+#define	xbcmd_destid	xbw0_cmdfield.destid
+#define	xbcmd_srcid	xbw0_cmdfield.srcid
+#define	xbcmd_pactyp	xbw0_cmdfield.pactyp
+#define	xbcmd_tnum	xbw0_cmdfield.tnum
+#define	xbcmd_ct	xbw0_cmdfield.ct
+#define	xbcmd_ds	xbw0_cmdfield.ds
+#define	xbcmd_gbr	xbw0_cmdfield.gbr
+#define	xbcmd_vbpm	xbw0_cmdfield.vbpm
+#define	xbcmd_error	xbw0_cmdfield.error
+#define	xbcmd_barr	xbw0_cmdfield.barr
+
+/*
+ * Values for field PACTYP in xbow error command word
+ */
+#define	XBCMDTYP_READREQ	0	/* Read Request   packet  */
+#define	XBCMDTYP_READRESP	1	/* Read Response packet   */
+#define	XBCMDTYP_WRREQ_RESP	2	/* Write Request with response    */
+#define	XBCMDTYP_WRRESP		3	/* Write Response */
+#define	XBCMDTYP_WRREQ_NORESP	4	/* Write request with  No Response */
+#define	XBCMDTYP_FETCHOP	6	/* Fetch & Op packet      */
+#define	XBCMDTYP_STOREOP	8	/* Store & Op packet      */
+#define	XBCMDTYP_SPLPKT_REQ	0xE	/* Special packet request */
+#define	XBCMDTYP_SPLPKT_RESP	0xF	/* Special packet response        */
+
+/*
+ * Values for field ds (datasize) in xbow error command word
+ */
+#define	XBCMDSZ_DOUBLEWORD	0
+#define	XBCMDSZ_QUARTRCACHE	1
+#define	XBCMDSZ_FULLCACHE	2
+
+/*
+ * Xbow widget 0 Status register format.
+ */
+#ifdef LITTLE_ENDIAN
+
+typedef union xbw0_status_u {
+    xbowreg_t               statusword;
+    struct {
+       uint32_t		mult_err:1,	/* Multiple error occured */
+                                connect_tout:1, /* Connection timeout   */
+                                xtalk_err:1,    /* Xtalk pkt with error bit */
+                                /* End of Xbridge only */
+                                w0_arb_tout,    /* arbiter timeout err */
+                                w0_recv_tout,   /* receive timeout err */
+                                /* Xbridge only */
+                                regacc_err:1,   /* Reg Access error     */
+                                src_id:4,       /* source id. Xbridge only */
+                                resvd1:13,
+                                wid0intr:1;     /* Widget 0 err intr */
+    } xbw0_stfield;
+} xbw0_status_t;
+
+#else
+
+typedef union xbw0_status_u {
+    xbowreg_t		    statusword;
+    struct {
+	uint32_t		linkXintr:8,	/* link(x) error intr */
+				wid0intr:1,	/* Widget 0 err intr */
+				resvd1:13,
+				src_id:4,	/* source id. Xbridge only */
+				regacc_err:1,	/* Reg Access error	*/
+				/* Xbridge only */
+				w0_recv_tout,	/* receive timeout err */
+				w0_arb_tout,	/* arbiter timeout err */
+				/* End of Xbridge only */
+				xtalk_err:1,	/* Xtalk pkt with error bit */
+				connect_tout:1, /* Connection timeout	*/
+				mult_err:1;	/* Multiple error occured */
+    } xbw0_stfield;
+} xbw0_status_t;
+
+#endif
+
+#define	xbst_linkXintr		xbw0_stfield.linkXintr
+#define	xbst_w0intr		xbw0_stfield.wid0intr
+#define	xbst_regacc_err		xbw0_stfield.regacc_err
+#define	xbst_xtalk_err		xbw0_stfield.xtalk_err
+#define	xbst_connect_tout	xbw0_stfield.connect_tout
+#define	xbst_mult_err		xbw0_stfield.mult_err
+#define xbst_src_id		xbw0_stfield.src_id	    /* Xbridge only */
+#define xbst_w0_recv_tout	xbw0_stfield.w0_recv_tout   /* Xbridge only */
+#define xbst_w0_arb_tout	xbw0_stfield.w0_arb_tout    /* Xbridge only */
+
+/*
+ * Xbow widget 0 Control register format
+ */
+#ifdef LITTLE_ENDIAN
+
+typedef union xbw0_ctrl_u {
+    xbowreg_t               ctrlword;
+    struct {
+	uint32_t              
+				resvd3:1,
+                                conntout_intr:1,
+                                xtalkerr_intr:1,
+                                w0_arg_tout_intr:1,     /* Xbridge only */
+                                w0_recv_tout_intr:1,    /* Xbridge only */
+                                accerr_intr:1,
+                                enable_w0_tout_cntr:1,  /* Xbridge only */
+                                enable_watchdog:1,      /* Xbridge only */
+                                resvd1:24;
+    } xbw0_ctrlfield;
+} xbw0_ctrl_t;
+
+#else
+
+typedef union xbw0_ctrl_u {
+    xbowreg_t		    ctrlword;
+    struct {
+	uint32_t
+				resvd1:24,
+				enable_watchdog:1,	/* Xbridge only */
+				enable_w0_tout_cntr:1,	/* Xbridge only */
+				accerr_intr:1,
+				w0_recv_tout_intr:1,	/* Xbridge only */
+				w0_arg_tout_intr:1,	/* Xbridge only */
+				xtalkerr_intr:1,
+				conntout_intr:1,
+				resvd3:1;
+    } xbw0_ctrlfield;
+} xbw0_ctrl_t;
+
+#endif
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xbow_linkctrl_u {
+    xbowreg_t               xbl_ctrlword;
+    struct {
+	uint32_t 		srcto_intr:1,
+                                maxto_intr:1, 
+                                rsvd3:1,
+                                trx_retry_intr:1, 
+                                rcv_err_intr:1, 
+                                trx_max_retry_intr:1,
+                                trxov_intr:1, 
+                                rcvov_intr:1,
+                                bwalloc_intr:1, 
+                                rsvd2:7, 
+                                obuf_intr:1,
+                                idest_intr:1, 
+                                llp_credit:5, 
+                                force_badllp:1,
+                                send_bm8:1, 
+                                inbuf_level:3, 
+                                perf_mode:2,
+                                rsvd1:1, 
+       		                alive_intr:1;
+
+    } xb_linkcontrol;
+} xbow_linkctrl_t;
+
+#else
+
+typedef union xbow_linkctrl_u {
+    xbowreg_t		    xbl_ctrlword;
+    struct {
+	uint32_t		alive_intr:1, 
+				rsvd1:1, 
+				perf_mode:2,
+				inbuf_level:3, 
+				send_bm8:1, 
+				force_badllp:1,
+				llp_credit:5, 
+				idest_intr:1, 
+				obuf_intr:1,
+				rsvd2:7, 
+				bwalloc_intr:1, 
+				rcvov_intr:1,
+				trxov_intr:1, 
+				trx_max_retry_intr:1,
+				rcv_err_intr:1, 
+				trx_retry_intr:1, 
+				rsvd3:1,
+				maxto_intr:1, 
+				srcto_intr:1;
+    } xb_linkcontrol;
+} xbow_linkctrl_t;
+
+#endif
+
+
+#define	xbctl_accerr_intr	(xbw0_ctrlfield.accerr_intr)
+#define	xbctl_xtalkerr_intr	(xbw0_ctrlfield.xtalkerr_intr)
+#define	xbctl_cnntout_intr	(xbw0_ctrlfield.conntout_intr)
+
+#define	XBW0_CTRL_ACCERR_INTR	(1 << 5)
+#define	XBW0_CTRL_XTERR_INTR	(1 << 2)
+#define	XBW0_CTRL_CONNTOUT_INTR	(1 << 1)
+
+/*
+ * Xbow Link specific Registers structure definitions.
+ */
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xbow_linkX_status_u {
+    xbowreg_t               linkstatus;
+    struct {
+	uint32_t               pkt_toutsrc:1,
+                                pkt_toutconn:1, /* max_req_tout in Xbridge */
+                                pkt_toutdest:1, /* reserved in Xbridge */
+                                llp_xmitretry:1,
+                                llp_rcverror:1,
+                                llp_maxtxretry:1,
+                                llp_txovflow:1,
+                                llp_rxovflow:1,
+                                bw_errport:8,   /* BW allocation error port   */
+                                ioe:1,          /* Input overallocation error */
+                                illdest:1,
+                                merror:1,
+                                resvd1:12,
+				alive:1;
+    } xb_linkstatus;
+} xbwX_stat_t;
+
+#else
+
+typedef union xbow_linkX_status_u {
+    xbowreg_t		    linkstatus;
+    struct {
+	uint32_t		alive:1,
+				resvd1:12,
+				merror:1,
+				illdest:1,
+				ioe:1,		/* Input overallocation error */
+				bw_errport:8,	/* BW allocation error port   */
+				llp_rxovflow:1,
+				llp_txovflow:1,
+				llp_maxtxretry:1,
+				llp_rcverror:1,
+				llp_xmitretry:1,
+				pkt_toutdest:1, /* reserved in Xbridge */
+				pkt_toutconn:1, /* max_req_tout in Xbridge */
+				pkt_toutsrc:1;
+    } xb_linkstatus;
+} xbwX_stat_t;
+
+#endif
+
+#define	link_alive		xb_linkstatus.alive
+#define	link_multierror		xb_linkstatus.merror
+#define	link_illegal_dest	xb_linkstatus.illdest
+#define	link_ioe		xb_linkstatus.ioe
+#define link_max_req_tout	xb_linkstatus.pkt_toutconn  /* Xbridge */
+#define link_pkt_toutconn	xb_linkstatus.pkt_toutconn  /* Xbow */
+#define link_pkt_toutdest	xb_linkstatus.pkt_toutdest
+#define	link_pkt_toutsrc	xb_linkstatus.pkt_toutsrc
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xbow_aux_linkX_status_u {
+    xbowreg_t               aux_linkstatus;
+    struct {
+	uint32_t 		rsvd2:4,
+                                bit_mode_8:1,
+                                wid_present:1,
+                                fail_mode:1,
+                                rsvd1:1,
+                                to_src_loc:8,
+                                tx_retry_cnt:8,
+				rx_err_cnt:8;
+    } xb_aux_linkstatus;
+} xbow_aux_link_status_t;
+
+#else
+
+typedef union xbow_aux_linkX_status_u {
+    xbowreg_t		    aux_linkstatus;
+    struct {
+	uint32_t		rx_err_cnt:8,
+				tx_retry_cnt:8,
+				to_src_loc:8,
+				rsvd1:1,
+				fail_mode:1,
+				wid_present:1,
+				bit_mode_8:1,
+				rsvd2:4;
+    } xb_aux_linkstatus;
+} xbow_aux_link_status_t;
+
+#endif
+
+
+#ifdef LITTLE_ENDIAN
+
+typedef union xbow_perf_count_u {
+    xbowreg_t               xb_counter_val;
+    struct {
+        uint32_t 		count:20,
+                                link_select:3,
+				rsvd:9;
+    } xb_perf;
+} xbow_perfcount_t;
+
+#else
+
+typedef union xbow_perf_count_u {
+    xbowreg_t               xb_counter_val;
+    struct {
+	uint32_t              rsvd:9, 
+				link_select:3, 
+				count:20;
+    } xb_perf;
+} xbow_perfcount_t;
+
+#endif
+
+#define XBOW_COUNTER_MASK	0xFFFFF
+
+extern int              xbow_widget_present(xbow_t * xbow, int port);
+
+extern xwidget_intr_preset_f xbow_intr_preset;
+extern xswitch_reset_link_f xbow_reset_link;
+void                    xbow_mlreset(xbow_t *);
+
+/* ========================================================================
+ */
+
+#ifdef	MACROFIELD_LINE
+/*
+ * This table forms a relation between the byte offset macros normally
+ * used for ASM coding and the calculated byte offsets of the fields
+ * in the C structure.
+ *
+ * See xbow_check.c xbow_html.c for further details.
+ */
+#ifndef MACROFIELD_LINE_BITFIELD
+#define MACROFIELD_LINE_BITFIELD(m)	/* ignored */
+#endif
+
+struct macrofield_s     xbow_macrofield[] =
+{
+
+    MACROFIELD_LINE(XBOW_WID_ID, xb_wid_id)
+    MACROFIELD_LINE(XBOW_WID_STAT, xb_wid_stat)
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xF))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xE))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xD))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xC))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xB))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xA))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x9))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x8))
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_WIDGET0_INTR)
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_REG_ACC_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_XTALK_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_WID_STAT_MULTI_ERR)
+    MACROFIELD_LINE(XBOW_WID_ERR_UPPER, xb_wid_err_upper)
+    MACROFIELD_LINE(XBOW_WID_ERR_LOWER, xb_wid_err_lower)
+    MACROFIELD_LINE(XBOW_WID_CONTROL, xb_wid_control)
+    MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_REG_ACC_IE)
+    MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_XTALK_IE)
+    MACROFIELD_LINE(XBOW_WID_REQ_TO, xb_wid_req_timeout)
+    MACROFIELD_LINE(XBOW_WID_INT_UPPER, xb_wid_int_upper)
+    MACROFIELD_LINE(XBOW_WID_INT_LOWER, xb_wid_int_lower)
+    MACROFIELD_LINE(XBOW_WID_ERR_CMDWORD, xb_wid_err_cmdword)
+    MACROFIELD_LINE(XBOW_WID_LLP, xb_wid_llp)
+    MACROFIELD_LINE(XBOW_WID_STAT_CLR, xb_wid_stat_clr)
+    MACROFIELD_LINE(XBOW_WID_ARB_RELOAD, xb_wid_arb_reload)
+    MACROFIELD_LINE(XBOW_WID_PERF_CTR_A, xb_perf_ctr_a)
+    MACROFIELD_LINE(XBOW_WID_PERF_CTR_B, xb_perf_ctr_b)
+    MACROFIELD_LINE(XBOW_WID_NIC, xb_nic)
+    MACROFIELD_LINE(XB_LINK_REG_BASE(8), xb_link(8))
+    MACROFIELD_LINE(XB_LINK_IBUF_FLUSH(8), xb_link(8).link_ibf)
+    MACROFIELD_LINE(XB_LINK_CTRL(8), xb_link(8).link_control)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_LINKALIVE_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_PERF_CTR_MODE_MSK)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_IBUF_LEVEL_MSK)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_8BIT_MODE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_BAD_LLP_PKT)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_WIDGET_CR_MSK)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_ILLEGAL_DST_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_OALLOC_IBUF_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_BNDWDTH_ALLOC_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_CNT_OFLOW_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_CNT_OFLOW_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_MAX_RTRY_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_RTRY_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_MAXREQ_TOUT_IE)
+    MACROFIELD_LINE_BITFIELD(XB_CTRL_SRC_TOUT_IE)
+    MACROFIELD_LINE(XB_LINK_STATUS(8), xb_link(8).link_status)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_LINKALIVE)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_MULTI_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_ILLEGAL_DST_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_OALLOC_IBUF_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_BNDWDTH_ALLOC_ID_MSK)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_CNT_OFLOW_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_CNT_OFLOW_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_MAX_RTRY_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_RTRY_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_MAXREQ_TOUT_ERR)
+    MACROFIELD_LINE_BITFIELD(XB_STAT_SRC_TOUT_ERR)
+    MACROFIELD_LINE(XB_LINK_ARB_UPPER(8), xb_link(8).link_arb_upper)
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xb))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xb))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xa))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xa))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x9))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x9))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x8))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x8))
+    MACROFIELD_LINE(XB_LINK_ARB_LOWER(8), xb_link(8).link_arb_lower)
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xf))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xf))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xe))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xe))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xd))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xd))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xc))
+    MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xc))
+    MACROFIELD_LINE(XB_LINK_STATUS_CLR(8), xb_link(8).link_status_clr)
+    MACROFIELD_LINE(XB_LINK_RESET(8), xb_link(8).link_reset)
+    MACROFIELD_LINE(XB_LINK_AUX_STATUS(8), xb_link(8).link_aux_status)
+    MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_RCV_CNT)
+    MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_XMT_CNT)
+    MACROFIELD_LINE_BITFIELD(XB_AUX_LINKFAIL_RST_BAD)
+    MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PRESENT)
+    MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PORT_WIDTH)
+    MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_TOUT_DST)
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0x8), xb_link(0x8))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0x9), xb_link(0x9))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0xA), xb_link(0xA))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0xB), xb_link(0xB))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0xC), xb_link(0xC))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0xD), xb_link(0xD))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0xE), xb_link(0xE))
+    MACROFIELD_LINE(XB_LINK_REG_BASE(0xF), xb_link(0xF))
+};				/* xbow_macrofield[] */
+
+#endif				/* MACROFIELD_LINE */
+
+#endif				/* _LANGUAGE_C */
+#endif                          /* _ASM_SN_SN_XTALK_XBOW_H */
diff --git a/include/asm-ia64/sn/xtalk/xbow_info.h b/include/asm-ia64/sn/xtalk/xbow_info.h
new file mode 100644
index 000000000..2d0084031
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xbow_info.h
@@ -0,0 +1,67 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_XTALK_XBOW_INFO_H
+#define _ASM_SN_XTALK_XBOW_INFO_H
+
+#define XBOW_PERF_MODES	       0x03
+#define XBOW_PERF_COUNTERS     0x02
+
+#define XBOW_MONITOR_NONE      0x00
+#define XBOW_MONITOR_SRC_LINK  0x01
+#define XBOW_MONITOR_DEST_LINK 0x02
+#define XBOW_MONITOR_INP_PKT   0x03
+#define XBOW_MONITOR_MULTIPLEX 0x04
+
+#define XBOW_LINK_MULTIPLEX    0x20
+
+#define XBOW_PERF_TIMEOUT	4
+#define XBOW_STATS_TIMEOUT	HZ
+
+typedef struct xbow_perf_link {
+    uint64_t              xlp_cumulative[XBOW_PERF_MODES];
+    unsigned char           xlp_link_alive;
+} xbow_perf_link_t;
+
+
+typedef struct xbow_link_status {
+    uint64_t              rx_err_count;
+    uint64_t              tx_retry_count;
+} xbow_link_status_t;
+
+
+
+typedef struct xbow_perf {
+    uint32_t              xp_current;
+    unsigned char           xp_link;
+    unsigned char           xp_mode;
+    unsigned char           xp_curlink;
+    unsigned char           xp_curmode;
+    volatile uint32_t    *xp_perf_reg;
+} xbow_perf_t;
+
+extern void             xbow_update_perf_counters(devfs_handle_t);
+extern xbow_perf_link_t *xbow_get_perf_counters(devfs_handle_t);
+extern int              xbow_enable_perf_counter(devfs_handle_t, int, int, int);
+
+#define XBOWIOC_PERF_ENABLE	  	1
+#define XBOWIOC_PERF_DISABLE	 	2
+#define XBOWIOC_PERF_GET	 	3
+#define XBOWIOC_LLP_ERROR_ENABLE 	4
+#define XBOWIOC_LLP_ERROR_DISABLE	5
+#define XBOWIOC_LLP_ERROR_GET	 	6
+
+
+struct xbow_perfarg_t {
+    int                     link;
+    int                     mode;
+    int                     counter;
+};
+
+#endif				/* _ASM_SN_XTALK_XBOW_INFO_H */
diff --git a/include/asm-ia64/sn/xtalk/xswitch.h b/include/asm-ia64/sn/xtalk/xswitch.h
new file mode 100644
index 000000000..8ca7fbc40
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xswitch.h
@@ -0,0 +1,59 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_XTALK_XSWITCH_H
+#define _ASM_SN_XTALK_XSWITCH_H
+
+/*
+ * xswitch.h - controls the format of the data
+ * provided by xswitch verticies back to the
+ * xtalk bus providers.
+ */
+
+#if LANGUAGE_C
+
+typedef struct xswitch_info_s *xswitch_info_t;
+
+typedef int
+                        xswitch_reset_link_f(devfs_handle_t xconn);
+
+typedef struct xswitch_provider_s {
+    xswitch_reset_link_f   *reset_link;
+} xswitch_provider_t;
+
+extern void             xswitch_provider_register(devfs_handle_t sw_vhdl, xswitch_provider_t * xsw_fns);
+
+xswitch_reset_link_f    xswitch_reset_link;
+
+extern xswitch_info_t   xswitch_info_new(devfs_handle_t vhdl);
+
+extern void             xswitch_info_link_is_ok(xswitch_info_t xswitch_info,
+						xwidgetnum_t port);
+extern void             xswitch_info_vhdl_set(xswitch_info_t xswitch_info,
+					      xwidgetnum_t port,
+					      devfs_handle_t xwidget);
+extern void             xswitch_info_master_assignment_set(xswitch_info_t xswitch_info,
+						       xwidgetnum_t port,
+					       devfs_handle_t master_vhdl);
+
+extern xswitch_info_t   xswitch_info_get(devfs_handle_t vhdl);
+
+extern int              xswitch_info_link_ok(xswitch_info_t xswitch_info,
+					     xwidgetnum_t port);
+extern devfs_handle_t     xswitch_info_vhdl_get(xswitch_info_t xswitch_info,
+					      xwidgetnum_t port);
+extern devfs_handle_t     xswitch_info_master_assignment_get(xswitch_info_t xswitch_info,
+						      xwidgetnum_t port);
+
+extern int		xswitch_id_get(devfs_handle_t vhdl);
+extern void		xswitch_id_set(devfs_handle_t vhdl,int xbow_num);
+
+#endif				/* LANGUAGE_C */
+
+#endif				/* _ASM_SN_XTALK_XSWITCH_H */
diff --git a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h
new file mode 100644
index 000000000..9ad747538
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xtalk.h
@@ -0,0 +1,408 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_XTALK_XTALK_H
+#define _ASM_SN_XTALK_XTALK_H
+
+/*
+ * xtalk.h -- platform-independent crosstalk interface
+ */
+/*
+ * User-level device driver visible types
+ */
+typedef char            xwidgetnum_t;	/* xtalk widget number  (0..15) */
+
+#define XWIDGET_NONE		-1
+
+typedef int xwidget_part_num_t;	/* xtalk widget part number */
+
+#define XWIDGET_PART_NUM_NONE	-1
+
+typedef int             xwidget_rev_num_t;	/* xtalk widget revision number */
+
+#define XWIDGET_REV_NUM_NONE	-1
+
+typedef int xwidget_mfg_num_t;	/* xtalk widget manufacturing ID */
+
+#define XWIDGET_MFG_NUM_NONE	-1
+
+typedef struct xtalk_piomap_s *xtalk_piomap_t;
+
+/* It is often convenient to fold the XIO target port
+ * number into the XIO address.
+ */
+#define	XIO_NOWHERE	(0xFFFFFFFFFFFFFFFFull)
+#define	XIO_ADDR_BITS	(0x0000FFFFFFFFFFFFull)
+#define	XIO_PORT_BITS	(0xF000000000000000ull)
+#define	XIO_PORT_SHIFT	(60)
+
+#define	XIO_PACKED(x)	(((x)&XIO_PORT_BITS) != 0)
+#define	XIO_ADDR(x)	((x)&XIO_ADDR_BITS)
+#define	XIO_PORT(x)	((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
+#define	XIO_PACK(p,o)	((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
+
+
+/*
+ * Kernel/driver only definitions
+ */
+#if __KERNEL__
+
+#include <asm/types.h>
+#include <asm/sn/types.h>
+#include <asm/sn/alenlist.h>
+#include <asm/sn/ioerror.h>
+#include <asm/sn/iobus.h>
+#include <asm/sn/dmamap.h>
+
+struct xwidget_hwid_s;
+
+/*
+ *    Acceptable flag bits for xtalk service calls
+ *
+ * XTALK_FIXED: require that mappings be established
+ *	using fixed sharable resources; address
+ *	translation results will be permanently
+ *	available. (PIOMAP_FIXED and DMAMAP_FIXED are
+ *	the same numeric value and are acceptable).
+ * XTALK_NOSLEEP: if any part of the operation would
+ *	sleep waiting for resoruces, return an error
+ *	instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are
+ *	the same numeric value and are acceptable).
+ * XTALK_INPLACE: when operating on alenlist structures,
+ *	reuse the source alenlist rather than creating a
+ *	new one. (PIOMAP_INPLACE and DMAMAP_INPLACE are
+ *	the same numeric value and are acceptable).
+ */
+#define	XTALK_FIXED		DMAMAP_FIXED
+#define	XTALK_NOSLEEP		DMAMAP_NOSLEEP
+#define	XTALK_INPLACE		DMAMAP_INPLACE
+
+/* PIO MANAGEMENT */
+typedef xtalk_piomap_t
+xtalk_piomap_alloc_f    (devfs_handle_t dev,	/* set up mapping for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 iopaddr_t xtalk_addr,	/* map for this xtalk_addr range */
+			 size_t byte_count,
+			 size_t byte_count_max,		/* maximum size of a mapping */
+			 unsigned flags);	/* defined in sys/pio.h */
+typedef void
+xtalk_piomap_free_f     (xtalk_piomap_t xtalk_piomap);
+
+typedef caddr_t
+xtalk_piomap_addr_f     (xtalk_piomap_t xtalk_piomap,	/* mapping resources */
+			 iopaddr_t xtalk_addr,	/* map for this xtalk address */
+			 size_t byte_count);	/* map this many bytes */
+
+typedef void
+xtalk_piomap_done_f     (xtalk_piomap_t xtalk_piomap);
+
+typedef caddr_t
+xtalk_piotrans_addr_f   (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 iopaddr_t xtalk_addr,	/* Crosstalk address */
+			 size_t byte_count,	/* map this many bytes */
+			 unsigned flags);	/* (currently unused) */
+
+extern caddr_t
+xtalk_pio_addr		(devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 iopaddr_t xtalk_addr,	/* Crosstalk address */
+			 size_t byte_count,	/* map this many bytes */
+			 xtalk_piomap_t *xtalk_piomapp,	/* RETURNS mapping resources */
+			 unsigned flags);	/* (currently unused) */
+
+/* DMA MANAGEMENT */
+
+typedef struct xtalk_dmamap_s *xtalk_dmamap_t;
+
+typedef xtalk_dmamap_t
+xtalk_dmamap_alloc_f    (devfs_handle_t dev,	/* set up mappings for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 size_t byte_count_max,		/* max size of a mapping */
+			 unsigned flags);	/* defined in dma.h */
+
+typedef void
+xtalk_dmamap_free_f     (xtalk_dmamap_t dmamap);
+
+typedef iopaddr_t
+xtalk_dmamap_addr_f     (xtalk_dmamap_t dmamap,		/* use these mapping resources */
+			 paddr_t paddr,		/* map for this address */
+			 size_t byte_count);	/* map this many bytes */
+
+typedef alenlist_t
+xtalk_dmamap_list_f     (xtalk_dmamap_t dmamap,		/* use these mapping resources */
+			 alenlist_t alenlist,	/* map this address/length list */
+			 unsigned flags);
+
+typedef void
+xtalk_dmamap_done_f     (xtalk_dmamap_t dmamap);
+
+typedef iopaddr_t
+xtalk_dmatrans_addr_f   (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 paddr_t paddr,		/* system physical address */
+			 size_t byte_count,	/* length */
+			 unsigned flags);
+
+typedef alenlist_t
+xtalk_dmatrans_list_f   (devfs_handle_t dev,	/* translate for this device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 alenlist_t palenlist,	/* system address/length list */
+			 unsigned flags);
+
+typedef void
+xtalk_dmamap_drain_f	(xtalk_dmamap_t map);	/* drain this map's channel */
+
+typedef void
+xtalk_dmaaddr_drain_f	(devfs_handle_t vhdl,	/* drain channel from this device */
+			 paddr_t addr,		/* to this physical address */
+			 size_t bytes);		/* for this many bytes */
+
+typedef void
+xtalk_dmalist_drain_f	(devfs_handle_t vhdl,	/* drain channel from this device */
+			 alenlist_t list);	/* for this set of physical blocks */
+
+
+/* INTERRUPT MANAGEMENT */
+
+/*
+ * A xtalk interrupt resource handle.  When resources are allocated
+ * in order to satisfy a xtalk_intr_alloc request, a xtalk_intr handle
+ * is returned.  xtalk_intr_connect associates a software handler with
+
+ * these system resources.
+ */
+typedef struct xtalk_intr_s *xtalk_intr_t;
+
+
+/*
+ * When a crosstalk device connects an interrupt, it passes in a function
+ * that knows how to set its xtalk interrupt register appropriately.  The
+ * low-level interrupt code may invoke this function later in order to
+ * migrate an interrupt transparently to the device driver(s) that use this
+ * interrupt.
+ *
+ * The argument passed to this function contains enough information for a
+ * crosstalk device to (re-)target an interrupt.  A function of this type
+ * must be supplied by every crosstalk driver.
+ */
+typedef int
+xtalk_intr_setfunc_f    (xtalk_intr_t intr_hdl);	/* interrupt handle */
+
+typedef xtalk_intr_t
+xtalk_intr_alloc_f      (devfs_handle_t dev,	/* which crosstalk device */
+			 device_desc_t dev_desc,	/* device descriptor */
+			 devfs_handle_t owner_dev);	/* owner of this intr */
+
+typedef void
+xtalk_intr_free_f       (xtalk_intr_t intr_hdl);
+
+typedef int
+xtalk_intr_connect_f    (xtalk_intr_t intr_hdl,		/* xtalk intr resource handle */
+			 intr_func_t intr_func,		/* xtalk intr handler */
+			 void *intr_arg,	/* arg to intr handler */
+			 xtalk_intr_setfunc_f *setfunc,		/* func to set intr hw */
+			 void *setfunc_arg,	/* arg to setfunc. This must be */
+							/* sufficient to determine which */
+							/* interrupt on which board needs */
+							/* to be set. */
+			 void *thread);		/* which intr thread to use */
+
+typedef void
+xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl);
+
+typedef devfs_handle_t
+xtalk_intr_cpu_get_f    (xtalk_intr_t intr_hdl);	/* xtalk intr resource handle */
+
+/* CONFIGURATION MANAGEMENT */
+
+typedef void
+xtalk_provider_startup_f (devfs_handle_t xtalk_provider);
+
+typedef void
+xtalk_provider_shutdown_f (devfs_handle_t xtalk_provider);
+
+typedef void
+xtalk_widgetdev_enable_f (devfs_handle_t, int);
+
+typedef void
+xtalk_widgetdev_shutdown_f (devfs_handle_t, int);
+
+typedef int
+xtalk_dma_enabled_f (devfs_handle_t);
+
+/* Error Management */
+
+typedef int
+xtalk_error_devenable_f (devfs_handle_t xconn_vhdl,
+			 int devnum,
+			 int error_code);
+
+/* Early Action Support */
+typedef caddr_t
+xtalk_early_piotrans_addr_f (xwidget_part_num_t part_num,
+			     xwidget_mfg_num_t mfg_num,
+			     int which,
+			     iopaddr_t xtalk_addr,
+			     size_t byte_count,
+			     unsigned flags);
+
+/*
+ * Adapters that provide a crosstalk interface adhere to this software interface.
+ */
+typedef struct xtalk_provider_s {
+    /* PIO MANAGEMENT */
+    xtalk_piomap_alloc_f   *piomap_alloc;
+    xtalk_piomap_free_f    *piomap_free;
+    xtalk_piomap_addr_f    *piomap_addr;
+    xtalk_piomap_done_f    *piomap_done;
+    xtalk_piotrans_addr_f  *piotrans_addr;
+
+    /* DMA MANAGEMENT */
+    xtalk_dmamap_alloc_f   *dmamap_alloc;
+    xtalk_dmamap_free_f    *dmamap_free;
+    xtalk_dmamap_addr_f    *dmamap_addr;
+    xtalk_dmamap_list_f    *dmamap_list;
+    xtalk_dmamap_done_f    *dmamap_done;
+    xtalk_dmatrans_addr_f  *dmatrans_addr;
+    xtalk_dmatrans_list_f  *dmatrans_list;
+    xtalk_dmamap_drain_f   *dmamap_drain;
+    xtalk_dmaaddr_drain_f  *dmaaddr_drain;
+    xtalk_dmalist_drain_f  *dmalist_drain;
+
+    /* INTERRUPT MANAGEMENT */
+    xtalk_intr_alloc_f     *intr_alloc;
+    xtalk_intr_free_f      *intr_free;
+    xtalk_intr_connect_f   *intr_connect;
+    xtalk_intr_disconnect_f *intr_disconnect;
+    xtalk_intr_cpu_get_f   *intr_cpu_get;
+
+    /* CONFIGURATION MANAGEMENT */
+    xtalk_provider_startup_f *provider_startup;
+    xtalk_provider_shutdown_f *provider_shutdown;
+
+    /* Error Management     */
+    xtalk_error_devenable_f *error_devenable;
+} xtalk_provider_t;
+
+/* Crosstalk devices use these standard Crosstalk provider interfaces */
+extern xtalk_piomap_alloc_f xtalk_piomap_alloc;
+extern xtalk_piomap_free_f xtalk_piomap_free;
+extern xtalk_piomap_addr_f xtalk_piomap_addr;
+extern xtalk_piomap_done_f xtalk_piomap_done;
+extern xtalk_piotrans_addr_f xtalk_piotrans_addr;
+extern xtalk_dmamap_alloc_f xtalk_dmamap_alloc;
+extern xtalk_dmamap_free_f xtalk_dmamap_free;
+extern xtalk_dmamap_addr_f xtalk_dmamap_addr;
+extern xtalk_dmamap_list_f xtalk_dmamap_list;
+extern xtalk_dmamap_done_f xtalk_dmamap_done;
+extern xtalk_dmatrans_addr_f xtalk_dmatrans_addr;
+extern xtalk_dmatrans_list_f xtalk_dmatrans_list;
+extern xtalk_dmamap_drain_f xtalk_dmamap_drain;
+extern xtalk_dmaaddr_drain_f xtalk_dmaaddr_drain;
+extern xtalk_dmalist_drain_f xtalk_dmalist_drain;
+extern xtalk_intr_alloc_f xtalk_intr_alloc;
+extern xtalk_intr_free_f xtalk_intr_free;
+extern xtalk_intr_connect_f xtalk_intr_connect;
+extern xtalk_intr_disconnect_f xtalk_intr_disconnect;
+extern xtalk_intr_cpu_get_f xtalk_intr_cpu_get;
+extern xtalk_provider_startup_f xtalk_provider_startup;
+extern xtalk_provider_shutdown_f xtalk_provider_shutdown;
+extern xtalk_widgetdev_enable_f xtalk_widgetdev_enable;
+extern xtalk_widgetdev_shutdown_f xtalk_widgetdev_shutdown;
+extern xtalk_dma_enabled_f xtalk_dma_enabled;
+extern xtalk_error_devenable_f xtalk_error_devenable;
+extern xtalk_early_piotrans_addr_f xtalk_early_piotrans_addr;
+
+/* error management */
+
+extern int              xtalk_error_handler(devfs_handle_t,
+					    int,
+					    ioerror_mode_t,
+					    ioerror_t *);
+
+/*
+ * Generic crosstalk interface, for use with all crosstalk providers
+ * and all crosstalk devices.
+ */
+typedef unchar xtalk_intr_vector_t;	/* crosstalk interrupt vector (0..255) */
+
+#define XTALK_INTR_VECTOR_NONE	(xtalk_intr_vector_t)0
+
+/* Generic crosstalk interrupt interfaces */
+extern devfs_handle_t     xtalk_intr_dev_get(xtalk_intr_t xtalk_intr);
+extern xwidgetnum_t     xtalk_intr_target_get(xtalk_intr_t xtalk_intr);
+extern xtalk_intr_vector_t xtalk_intr_vector_get(xtalk_intr_t xtalk_intr);
+extern iopaddr_t        xtalk_intr_addr_get(xtalk_intr_t xtalk_intr);
+extern devfs_handle_t     xtalk_intr_cpu_get(xtalk_intr_t xtalk_intr);
+extern void            *xtalk_intr_sfarg_get(xtalk_intr_t xtalk_intr);
+
+extern int		xtalk_intr_flags_get(xtalk_intr_t xtalk_intr);
+/* XTALK_INTR flags */
+#define XTALK_INTR_NOTHREAD	1	/* interrupt handler wants to be called at interrupt level */
+
+/* Generic crosstalk pio interfaces */
+extern devfs_handle_t     xtalk_pio_dev_get(xtalk_piomap_t xtalk_piomap);
+extern xwidgetnum_t     xtalk_pio_target_get(xtalk_piomap_t xtalk_piomap);
+extern iopaddr_t        xtalk_pio_xtalk_addr_get(xtalk_piomap_t xtalk_piomap);
+extern size_t           xtalk_pio_mapsz_get(xtalk_piomap_t xtalk_piomap);
+extern caddr_t          xtalk_pio_kvaddr_get(xtalk_piomap_t xtalk_piomap);
+
+/* Generic crosstalk dma interfaces */
+extern devfs_handle_t     xtalk_dma_dev_get(xtalk_dmamap_t xtalk_dmamap);
+extern xwidgetnum_t     xtalk_dma_target_get(xtalk_dmamap_t xtalk_dmamap);
+
+/* Register/unregister Crosstalk providers and get implementation handle */
+extern void             xtalk_set_early_piotrans_addr(xtalk_early_piotrans_addr_f *);
+extern void             xtalk_provider_register(devfs_handle_t provider, xtalk_provider_t *xtalk_fns);
+extern void             xtalk_provider_unregister(devfs_handle_t provider);
+extern xtalk_provider_t *xtalk_provider_fns_get(devfs_handle_t provider);
+
+/* Crosstalk Switch generic layer, for use by initialization code */
+extern void             xswitch_census(devfs_handle_t xswitchv);
+extern void             xswitch_init_widgets(devfs_handle_t xswitchv);
+
+/* early init interrupt management */
+
+typedef void
+xwidget_intr_preset_f   (void *which_widget,
+			 int which_widget_intr,
+			 xwidgetnum_t targ,
+			 iopaddr_t addr,
+			 xtalk_intr_vector_t vect);
+
+typedef void
+xtalk_intr_prealloc_f   (void *which_xtalk,
+			 xtalk_intr_vector_t xtalk_vector,
+			 xwidget_intr_preset_f *preset_func,
+			 void *which_widget,
+			 int which_widget_intr);
+
+typedef void
+xtalk_intr_preconn_f    (void *which_xtalk,
+			 xtalk_intr_vector_t xtalk_vector,
+			 intr_func_t intr_func,
+			 intr_arg_t intr_arg);
+
+
+#define XTALK_ADDR_TO_UPPER(xtalk_addr) (((iopaddr_t)(xtalk_addr) >> 32) & 0xffff)
+#define XTALK_ADDR_TO_LOWER(xtalk_addr) ((iopaddr_t)(xtalk_addr) & 0xffffffff)
+
+typedef xtalk_intr_setfunc_f *xtalk_intr_setfunc_t;
+
+typedef void		xtalk_iter_f(devfs_handle_t vhdl);
+
+extern void		xtalk_iterate(char *prefix, xtalk_iter_f *func);
+
+extern int		xtalk_device_powerup(devfs_handle_t, xwidgetnum_t);
+extern int		xtalk_device_shutdown(devfs_handle_t, xwidgetnum_t);
+extern int		xtalk_device_inquiry(devfs_handle_t, xwidgetnum_t);
+
+#endif				/* __KERNEL__ */
+#endif				/* _ASM_SN_XTALK_XTALK_H */
diff --git a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h
new file mode 100644
index 000000000..b0c1794e3
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xtalk_private.h
@@ -0,0 +1,90 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_XTALK_XTALK_PRIVATE_H
+#define _ASM_SN_XTALK_XTALK_PRIVATE_H
+
+#ifdef IRIX
+#include <sys/ioerror.h>	/* for error function and arg types */
+#else
+#include <asm/sn/ioerror.h>        /* for error function and arg types */
+#endif
+
+/*
+ * xtalk_private.h -- private definitions for xtalk
+ * crosstalk drivers should NOT include this file.
+ */
+
+/*
+ * All Crosstalk providers set up PIO using this information.
+ */
+struct xtalk_piomap_s {
+    devfs_handle_t            xp_dev;	/* a requestor of this mapping */
+    xwidgetnum_t            xp_target;	/* target (node's widget number) */
+    iopaddr_t               xp_xtalk_addr;	/* which crosstalk addr is mapped */
+    size_t                  xp_mapsz;	/* size of this mapping */
+    caddr_t                 xp_kvaddr;	/* kernel virtual address to use */
+};
+
+/*
+ * All Crosstalk providers set up DMA using this information.
+ */
+struct xtalk_dmamap_s {
+    devfs_handle_t            xd_dev;	/* a requestor of this mapping */
+    xwidgetnum_t            xd_target;	/* target (node's widget number) */
+};
+
+/*
+ * All Crosstalk providers set up interrupts using this information.
+ */
+struct xtalk_intr_s {
+    int                     xi_flags;	/* XTALK_INTR flags */
+    devfs_handle_t            xi_dev;	/* requestor of this intr */
+    xwidgetnum_t            xi_target;	/* master's widget number */
+    xtalk_intr_vector_t     xi_vector;	/* 8-bit interrupt vector */
+    iopaddr_t               xi_addr;	/* xtalk address to generate intr */
+    void                   *xi_sfarg;	/* argument for setfunc */
+    xtalk_intr_setfunc_t    xi_setfunc;		/* device's setfunc routine */
+};
+
+/*
+ * Xtalk interrupt handler structure access functions
+ */
+#define	xtalk_intr_arg(xt)	((xt)->xi_sfarg)
+
+#define	xwidget_hwid_is_sn0_xswitch(_hwid)	\
+		(((_hwid)->part_num == XBOW_WIDGET_PART_NUM ) &&  	\
+		 ((_hwid)->mfg_num == XBOW_WIDGET_MFGR_NUM ))
+
+#define	xwidget_hwid_is_sn1_xswitch(_hwid)	\
+		(((_hwid)->part_num == XXBOW_WIDGET_PART_NUM ) &&  	\
+		 ((_hwid)->mfg_num == XXBOW_WIDGET_MFGR_NUM ))
+
+#define	xwidget_hwid_is_xswitch(_hwid)	\
+		(xwidget_hwid_is_sn0_xswitch(_hwid) ||			\
+			xwidget_hwid_is_sn1_xswitch(_hwid))
+
+/* common iograph info for all widgets,
+ * stashed in FASTINFO of widget connection points.
+ */
+struct xwidget_info_s {
+    char                   *w_fingerprint;
+    devfs_handle_t            w_vertex;	/* back pointer to vertex */
+    xwidgetnum_t            w_id;	/* widget id */
+    struct xwidget_hwid_s   w_hwid;	/* hardware identification (part/rev/mfg) */
+    devfs_handle_t            w_master;	/* CACHED widget's master */
+    xwidgetnum_t            w_masterid;		/* CACHED widget's master's widgetnum */
+    error_handler_f        *w_efunc;	/* error handling function */
+    error_handler_arg_t     w_einfo;	/* first parameter for efunc */
+    char		   *w_name;	/* canonical hwgraph name */	
+};
+
+extern char             widget_info_fingerprint[];
+
+#endif				/* _ASM_SN_XTALK_XTALK_PRIVATE_H */
diff --git a/include/asm-ia64/sn/xtalk/xtalkaddrs.h b/include/asm-ia64/sn/xtalk/xtalkaddrs.h
new file mode 100644
index 000000000..c1ff9578f
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xtalkaddrs.h
@@ -0,0 +1,113 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_XTALK_XTALKADDRS_H
+#define _ASM_SN_XTALK_XTALKADDRS_H
+
+/*
+ * CrossTalk to SN0 Hub addressing support
+ *
+ * This file defines the mapping conventions used by the Hub's
+ * I/O interface when it receives a read or write request from 
+ * a CrossTalk widget.  
+ *
+ * Format for non-Memory accesses:
+ *
+ *  +--------------+------------------------------------------------+
+ *  | 0  | XXXXX   |        SN0Addr                                |
+ *  +----+---------+------------------------------------------------+
+ *    47  46     40 39                                             0
+ *	bit 47 indicates Memory (0)
+ *	bits 46..40 are unused
+ *	bits 39..0 hold the memory address
+ *			(bits 39..31 hold the nodeID in N mode
+ *			 bits 39..32 hold the nodeID in M mode
+ * By design, this looks exactly like a 0-extended SN0 Address, so
+ * we don't need to do any conversions.
+ *
+ *
+ *
+ * Format for non-Memory accesses:
+ *
+ *  +--------------+------+---------+------+--+---------------------+
+ *  | 1  | DstNode | XXXX | BigW=0  | SW=1 | 1|   Addr              |
+ *  +----+---------+------+---------+------+--+---------------------+
+ *    47  46     38 37  31 30     28 27  24 23 22                  0
+ *
+ *	bit 47 indicates IO (1)
+ *      bits 46..38 hold the destination node ID
+ *      bits 37..31 are unused
+ *      bits 30..28 hold the big window being addressed
+ *      bits 27..24 hold the small window being addressed
+ *                  0 always refers to the xbow
+ *                  1 always refers to the hub itself
+ *      bit 23 indicates local (0) or remote (1)
+ *             no accessing checks are done if this bit is 0
+ *      bits 22..0 hold the register address
+ *                 bits 22..21 determine which section of the hub
+ *                              00 -> PI
+ *                              01 -> MD
+ *                              10 -> IO
+ *                              11 -> NI
+ * This looks very much like a REMOTE_HUB access, except the nodeID
+ * is in a different place, and the highest xtalk bit is set.
+ */
+
+#include <linux/config.h>
+
+/* Hub-specific xtalk definitions */
+
+#define HX_MEM_BIT		0L	/* Hub's idea of xtalk memory access */
+#define HX_IO_BIT		1L	/* Hub's idea of xtalk register access */
+#define HX_ACCTYPE_SHIFT	47
+
+#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#define HX_NODE_SHIFT		39
+#endif
+
+#define HX_BIGWIN_SHIFT		28
+
+#define HX_SWIN_SHIFT		23
+
+#define HX_LOCACC		0L	/* local access */
+#define HX_REMACC		1L	/* remote access */
+#define HX_ACCESS_SHIFT		23
+
+/*
+ * Pre-calculate the fixed portion of a crosstalk address that maps
+ * to local register space on a hub.
+ */
+#define HX_REG_BASE		((HX_IO_BIT<<HX_ACCTYPE_SHIFT) + \
+				(0L<<HX_BIGWIN_SHIFT) + \
+				(1L<<HX_SWIN_SHIFT) + IALIAS_SIZE + \
+				(HX_REMACC<<HX_ACCESS_SHIFT))
+
+/* 
+ * Return a crosstalk address which a widget can use to access a
+ * designated register on a designated node.
+ */
+#define HUBREG_AS_XTALKADDR(nasid, regaddr) \
+	((iopaddr_t)(HX_REG_BASE + (((long)nasid)<<HX_NODE_SHIFT) + ((long)regaddr)))
+
+#if TBD
+#assert sizeof(iopaddr_t) == 8
+#endif /* TBD */
+
+/*
+ * Get widget part number, given node id and widget id. 
+ * Always do a 32-bit read, because some widgets, e.g., Bridge, require so.
+ * Widget ID is at offset 0 for 64-bit access.  Add 4 to get lower 32 bits
+ * in big endian mode. 
+ * XXX Double check this with Hub, Xbow, Bridge and other hardware folks.
+ */
+#define XWIDGET_ID_READ(nasid, widget) \
+        (widgetreg_t)(*(volatile uint32_t *)(NODE_SWIN_BASE(nasid, widget) + WIDGET_ID))
+
+
+#endif /* _ASM_SN_XTALK_XTALKADDRS_H */
diff --git a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h
new file mode 100644
index 000000000..da74fc3d0
--- /dev/null
+++ b/include/asm-ia64/sn/xtalk/xwidget.h
@@ -0,0 +1,308 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef __ASM_SN_XTALK_XWIDGET_H__
+#define __ASM_SN_XTALK_XWIDGET_H__
+
+/*
+ * xwidget.h - generic crosstalk widget header file
+ */
+
+#include <asm/sn/xtalk/xtalk.h>
+#if LANGUAGE_C
+#include <asm/sn/cdl.h>
+#endif /* LANGUAGE_C */
+
+#ifdef LITTLE_ENDIAN
+#define WIDGET_ID			0x00
+#define WIDGET_STATUS			0x08
+#define WIDGET_ERR_UPPER_ADDR		0x10
+#define WIDGET_ERR_LOWER_ADDR		0x18
+#define WIDGET_CONTROL			0x20
+#define WIDGET_REQ_TIMEOUT		0x28
+#define WIDGET_INTDEST_UPPER_ADDR	0x30
+#define WIDGET_INTDEST_LOWER_ADDR	0x38
+#define WIDGET_ERR_CMD_WORD		0x40
+#define WIDGET_LLP_CFG			0x48
+#define WIDGET_TFLUSH			0x50
+#else	/* !LITTLE_ENDIAN */
+#define WIDGET_ID                       0x04
+#define WIDGET_STATUS                   0x0c
+#define WIDGET_ERR_UPPER_ADDR           0x14
+#define WIDGET_ERR_LOWER_ADDR           0x1c
+#define WIDGET_CONTROL                  0x24
+#define WIDGET_REQ_TIMEOUT              0x2c
+#define WIDGET_INTDEST_UPPER_ADDR       0x34
+#define WIDGET_INTDEST_LOWER_ADDR       0x3c
+#define WIDGET_ERR_CMD_WORD             0x44
+#define WIDGET_LLP_CFG                  0x4c
+#define WIDGET_TFLUSH                   0x54
+#endif
+
+/* WIDGET_ID */
+#define WIDGET_REV_NUM			0xf0000000
+#define WIDGET_PART_NUM			0x0ffff000
+#define WIDGET_MFG_NUM			0x00000ffe
+#define WIDGET_REV_NUM_SHFT		28
+#define WIDGET_PART_NUM_SHFT		12
+#define WIDGET_MFG_NUM_SHFT		1
+
+#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
+#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
+#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
+#define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \
+					XWIDGET_REV_NUM(widgetid))
+
+/* WIDGET_STATUS */
+#define WIDGET_LLP_REC_CNT		0xff000000
+#define WIDGET_LLP_TX_CNT		0x00ff0000
+#define WIDGET_PENDING			0x0000001f
+
+/* WIDGET_ERR_UPPER_ADDR */
+#define	WIDGET_ERR_UPPER_ADDR_ONLY	0x0000ffff
+
+/* WIDGET_CONTROL */
+#define WIDGET_F_BAD_PKT		0x00010000
+#define WIDGET_LLP_XBAR_CRD		0x0000f000
+#define	WIDGET_LLP_XBAR_CRD_SHFT	12
+#define WIDGET_CLR_RLLP_CNT		0x00000800
+#define WIDGET_CLR_TLLP_CNT		0x00000400
+#define WIDGET_SYS_END			0x00000200
+#define WIDGET_MAX_TRANS		0x000001f0
+#define WIDGET_PCI_SPEED		0x00000030
+#define WIDGET_PCI_SPEED_SHFT		4
+#define WIDGET_PCI_SPEED_33MHZ 0
+#define WIDGET_PCI_SPEED_66MHZ 1
+#define WIDGET_WIDGET_ID		0x0000000f
+
+/* WIDGET_INTDEST_UPPER_ADDR */
+#define WIDGET_INT_VECTOR		0xff000000
+#define WIDGET_INT_VECTOR_SHFT		24
+#define WIDGET_TARGET_ID		0x000f0000
+#define WIDGET_TARGET_ID_SHFT		16
+#define WIDGET_UPP_ADDR			0x0000ffff
+
+/* WIDGET_ERR_CMD_WORD */
+#define WIDGET_DIDN			0xf0000000
+#define WIDGET_SIDN			0x0f000000
+#define WIDGET_PACTYP			0x00f00000
+#define WIDGET_TNUM			0x000f8000
+#define WIDGET_COHERENT			0x00004000
+#define WIDGET_DS			0x00003000
+#define WIDGET_GBR			0x00000800
+#define WIDGET_VBPM			0x00000400
+#define WIDGET_ERROR			0x00000200
+#define WIDGET_BARRIER			0x00000100
+
+/* WIDGET_LLP_CFG */
+#define WIDGET_LLP_MAXRETRY		0x03ff0000
+#define WIDGET_LLP_MAXRETRY_SHFT	16
+#define WIDGET_LLP_NULLTIMEOUT		0x0000fc00
+#define WIDGET_LLP_NULLTIMEOUT_SHFT	10
+#define WIDGET_LLP_MAXBURST		0x000003ff
+#define WIDGET_LLP_MAXBURST_SHFT	0
+
+/*
+ * according to the crosstalk spec, only 32-bits access to the widget
+ * configuration registers is allowed.  some widgets may allow 64-bits
+ * access but software should not depend on it.  registers beyond the
+ * widget target flush register are widget dependent thus will not be
+ * defined here
+ */
+#if _LANGUAGE_C
+typedef uint32_t      widgetreg_t;
+
+/* widget configuration registers */
+typedef volatile struct widget_cfg {
+#ifdef LITTLE_ENDIAN
+/*
+ * we access these through synergy unswizzled space, so the address
+ * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
+ * That's why we put the register first and filler second.
+ */
+    widgetreg_t		    w_id;	/* 0x04 */
+    widgetreg_t		    w_pad_0;	/* 0x00 */
+    widgetreg_t		    w_status;	/* 0x0c */
+    widgetreg_t		    w_pad_1;	/* 0x08 */
+    widgetreg_t		    w_err_upper_addr;	/* 0x14 */
+    widgetreg_t		    w_pad_2;	/* 0x10 */
+    widgetreg_t		    w_err_lower_addr;	/* 0x1c */
+    widgetreg_t		    w_pad_3;	/* 0x18 */
+    widgetreg_t		    w_control;	/* 0x24 */
+    widgetreg_t		    w_pad_4;	/* 0x20 */
+    widgetreg_t		    w_req_timeout;	/* 0x2c */
+    widgetreg_t		    w_pad_5;	/* 0x28 */
+    widgetreg_t		    w_intdest_upper_addr;	/* 0x34 */
+    widgetreg_t		    w_pad_6;	/* 0x30 */
+    widgetreg_t		    w_intdest_lower_addr;	/* 0x3c */
+    widgetreg_t		    w_pad_7;	/* 0x38 */
+    widgetreg_t		    w_err_cmd_word;	/* 0x44 */
+    widgetreg_t		    w_pad_8;	/* 0x40 */
+    widgetreg_t		    w_llp_cfg;	/* 0x4c */
+    widgetreg_t		    w_pad_9;	/* 0x48 */
+    widgetreg_t		    w_tflush;	/* 0x54 */
+    widgetreg_t		    w_pad_10;	/* 0x50 */
+#else
+    widgetreg_t		    w_pad_0;	/* 0x00 */
+    widgetreg_t		    w_id;	/* 0x04 */
+    widgetreg_t		    w_pad_1;	/* 0x08 */
+    widgetreg_t		    w_status;	/* 0x0c */
+    widgetreg_t		    w_pad_2;	/* 0x10 */
+    widgetreg_t		    w_err_upper_addr;	/* 0x14 */
+    widgetreg_t		    w_pad_3;	/* 0x18 */
+    widgetreg_t		    w_err_lower_addr;	/* 0x1c */
+    widgetreg_t		    w_pad_4;	/* 0x20 */
+    widgetreg_t		    w_control;	/* 0x24 */
+    widgetreg_t		    w_pad_5;	/* 0x28 */
+    widgetreg_t		    w_req_timeout;	/* 0x2c */
+    widgetreg_t		    w_pad_6;	/* 0x30 */
+    widgetreg_t		    w_intdest_upper_addr;	/* 0x34 */
+    widgetreg_t		    w_pad_7;	/* 0x38 */
+    widgetreg_t		    w_intdest_lower_addr;	/* 0x3c */
+    widgetreg_t		    w_pad_8;	/* 0x40 */
+    widgetreg_t		    w_err_cmd_word;	/* 0x44 */
+    widgetreg_t		    w_pad_9;	/* 0x48 */
+    widgetreg_t		    w_llp_cfg;	/* 0x4c */
+    widgetreg_t		    w_pad_10;	/* 0x50 */
+    widgetreg_t		    w_tflush;	/* 0x54 */
+#endif /* LITTLE_ENDIAN */
+} widget_cfg_t;
+
+#ifdef LITTLE_ENDIAN
+typedef struct {
+    unsigned                other:8;
+    unsigned                bo:1;
+    unsigned                error:1;
+    unsigned                vbpm:1;
+    unsigned                gbr:1;
+    unsigned                ds:2;
+    unsigned                ct:1;
+    unsigned                tnum:5;
+    unsigned                pactyp:4;
+    unsigned                sidn:4;
+    unsigned                didn:4;
+} w_err_cmd_word_f;
+#else
+typedef struct {
+    unsigned                didn:4;
+    unsigned                sidn:4;
+    unsigned                pactyp:4;
+    unsigned                tnum:5;
+    unsigned                ct:1;
+    unsigned                ds:2;
+    unsigned                gbr:1;
+    unsigned                vbpm:1;
+    unsigned                error:1;
+    unsigned                bo:1;
+    unsigned                other:8;
+} w_err_cmd_word_f;
+#endif
+
+#ifdef LITTLE_ENDIAN
+typedef union {
+    w_err_cmd_word_f        f;
+    widgetreg_t             r;
+} w_err_cmd_word_u;
+#else
+typedef union {
+    widgetreg_t             r;
+    w_err_cmd_word_f        f;
+} w_err_cmd_word_u;
+#endif
+
+/* IO widget initialization function */
+typedef struct xwidget_info_s *xwidget_info_t;
+
+/*
+ * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
+ */
+#ifdef LITTLE_ENDIAN
+typedef struct xwidget_hwid_s {
+    xwidget_mfg_num_t       mfg_num;
+    xwidget_rev_num_t       rev_num;
+    xwidget_part_num_t      part_num;
+}                      *xwidget_hwid_t;
+#else
+typedef struct xwidget_hwid_s {
+    xwidget_part_num_t      part_num;
+    xwidget_rev_num_t       rev_num;
+    xwidget_mfg_num_t       mfg_num;
+}                      *xwidget_hwid_t;
+#endif
+
+
+/*
+ * Returns 1 if a driver that handles devices described by hwid1 is able
+ * to manage a device with hardwareid hwid2.  NOTE: We don't check rev
+ * numbers at all.
+ */
+#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \
+	(((hwid1)->part_num == (hwid2)->part_num) && \
+	(((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+	((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+	((hwid1)->mfg_num == (hwid2)->mfg_num)))
+
+
+/* Generic crosstalk widget initialization interface */
+#if __KERNEL__
+
+extern int              xwidget_driver_register(xwidget_part_num_t part_num,
+						xwidget_mfg_num_t mfg_num,
+						char *driver_prefix,
+						unsigned flags);
+
+extern void             xwidget_driver_unregister(char *driver_prefix);
+
+extern int              xwidget_register(struct xwidget_hwid_s *hwid,
+					 devfs_handle_t dev,
+					 xwidgetnum_t id,
+					 devfs_handle_t master,
+					 xwidgetnum_t targetid,
+					 async_attach_t aa);
+
+extern int		xwidget_unregister(devfs_handle_t);
+extern void	        xwidget_error_register(devfs_handle_t xwidget,
+						error_handler_f * efunc,
+						error_handler_arg_t einfo);
+
+extern void             xwidget_reset(devfs_handle_t xwidget);
+extern void             xwidget_gfx_reset(devfs_handle_t xwidget);
+extern char		*xwidget_name_get(devfs_handle_t xwidget);	
+
+/* Generic crosstalk widget information access interface */
+extern xwidget_info_t   xwidget_info_chk(devfs_handle_t widget);
+extern xwidget_info_t   xwidget_info_get(devfs_handle_t widget);
+extern void             xwidget_info_set(devfs_handle_t widget, xwidget_info_t widget_info);
+extern devfs_handle_t     xwidget_info_dev_get(xwidget_info_t xwidget_info);
+extern xwidgetnum_t     xwidget_info_id_get(xwidget_info_t xwidget_info);
+extern int              xwidget_info_type_get(xwidget_info_t xwidget_info);
+extern int              xwidget_info_state_get(xwidget_info_t xwidget_info);
+extern devfs_handle_t     xwidget_info_master_get(xwidget_info_t xwidget_info);
+extern xwidgetnum_t     xwidget_info_masterid_get(xwidget_info_t xwidget_info);
+extern xwidget_part_num_t xwidget_info_part_num_get(xwidget_info_t xwidget_info);
+extern xwidget_rev_num_t xwidget_info_rev_num_get(xwidget_info_t xwidget_info);
+extern xwidget_mfg_num_t xwidget_info_mfg_num_get(xwidget_info_t xwidget_info);
+
+
+/*
+ * TBD: DELETE THIS ENTIRE STRUCTURE!  Equivalent is now in
+ * xtalk_private.h: xwidget_info_s
+ * This is just here for now because we still have a lot of
+ * junk referencing it.
+ * However, since nobody looks inside ...
+ */
+typedef struct v_widget_s {
+    unsigned                v_widget_s_is_really_empty;
+#define	v_widget_s_is_really_empty	and using this would be a syntax error.
+} v_widget_t;
+#endif				/* _KERNEL */
+
+#endif				/* _LANGUAGE_C */
+
+#endif				/* __ASM_SN_XTALK_XWIDGET_H__ */
diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
index eb421385c..70ff9bda4 100644
--- a/include/asm-ia64/spinlock.h
+++ b/include/asm-ia64/spinlock.h
@@ -18,8 +18,9 @@
 #undef NEW_LOCK
 
 #ifdef NEW_LOCK
+
 typedef struct { 
-	volatile unsigned char lock;
+	volatile unsigned int lock;
 } spinlock_t;
 
 #define SPIN_LOCK_UNLOCKED			(spinlock_t) { 0 }
@@ -38,7 +39,7 @@ typedef struct {
 		"mov r30=1\n"								\
 		"mov ar.ccv=r0\n"							\
 		";;\n"									\
-		IA64_SEMFIX"cmpxchg1.acq r30=[%0],r30,ar.ccv\n"				\
+		IA64_SEMFIX"cmpxchg4.acq r30=[%0],r30,ar.ccv\n"				\
 		";;\n"									\
 		"cmp.ne p15,p0=r30,r0\n"						\
 		"(p15) br.call.spnt.few b7=ia64_spinlock_contention\n"			\
@@ -48,18 +49,16 @@ typedef struct {
 		: "ar.ccv", "ar.pfs", "b7", "p15", "r28", "r29", "r30", "memory");	\
 }
 
-#define spin_trylock(x)								\
-({										\
-	register char *addr __asm__ ("r31") = (char *) &(x)->lock;		\
-	register long result;							\
-										\
-	__asm__ __volatile__ (							\
-		"mov r30=1\n"							\
-		"mov ar.ccv=r0\n"						\
-		";;\n"								\
-		IA64_SEMFIX"cmpxchg1.acq %0=[%1],r30,ar.ccv\n"			\
-		: "=r"(result) : "r"(addr) : "ar.ccv", "r30", "memory");	\
-	(result == 0);								\
+#define spin_trylock(x)									\
+({											\
+	register long result;								\
+											\
+	__asm__ __volatile__ (								\
+		"mov ar.ccv=r0\n"							\
+		";;\n"									\
+		IA64_SEMFIX"cmpxchg4.acq %0=[%2],%1,ar.ccv\n"				\
+		: "=r"(result) : "r"(1), "r"(&(x)->lock) : "ar.ccv", "memory");		\
+	(result == 0);									\
 })
 
 #define spin_is_locked(x)	((x)->lock != 0)
diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h
index 4bff3ff94..6fd4ce627 100644
--- a/include/asm-ia64/system.h
+++ b/include/asm-ia64/system.h
@@ -27,7 +27,8 @@
 
 #define GATE_ADDR		(0xa000000000000000 + PAGE_SIZE)
 
-#if defined(CONFIG_ITANIUM_ASTEP_SPECIFIC) || defined(CONFIG_ITANIUM_BSTEP_SPECIFIC)
+#if defined(CONFIG_ITANIUM_ASTEP_SPECIFIC) \
+    || defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC)
   /* Workaround for Errata 97.  */
 # define IA64_SEMFIX_INSN	mf;
 # define IA64_SEMFIX	"mf;"
diff --git a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h
index 6e8aef3df..b0b4f836f 100644
--- a/include/asm-ia64/uaccess.h
+++ b/include/asm-ia64/uaccess.h
@@ -125,46 +125,28 @@ extern void __get_user_unknown (void);
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
-#define __get_user_64(addr)								\
+/* We need to declare the __ex_table section before we can use it in .xdata.  */
+__asm__ (".section \"__ex_table\", \"a\"\n\t.previous");
+
+#define __get_user_64(addr)									\
 	__asm__ ("\n1:\tld8 %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 (2b-1b)|1\n"						\
-		 "\t.previous"								\
-		: "=r"(__gu_val), "=r"(__gu_err)					\
-		: "m"(__m(addr)), "1"(__gu_err));
-
-#define __get_user_32(addr)								\
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)|1\n"			\
+		: "=r"(__gu_val), "=r"(__gu_err) : "m"(__m(addr)), "1"(__gu_err));
+
+#define __get_user_32(addr)									\
 	__asm__ ("\n1:\tld4 %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 (2b-1b)|1\n"						\
-		 "\t.previous"								\
-		: "=r"(__gu_val), "=r"(__gu_err)					\
-		: "m"(__m(addr)), "1"(__gu_err));
-
-#define __get_user_16(addr)								\
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)|1\n"			\
+		: "=r"(__gu_val), "=r"(__gu_err) : "m"(__m(addr)), "1"(__gu_err));
+
+#define __get_user_16(addr)									\
 	__asm__ ("\n1:\tld2 %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 (2b-1b)|1\n"						\
-		 "\t.previous"								\
-		: "=r"(__gu_val), "=r"(__gu_err)					\
-		: "m"(__m(addr)), "1"(__gu_err));
-
-#define __get_user_8(addr)								\
-	__asm__ ("\n1:\tld1 %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 (2b-1b)|1\n"						\
-		 "\t.previous"								\
-		: "=r"(__gu_val), "=r"(__gu_err)					\
-		: "m"(__m(addr)), "1"(__gu_err));
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)|1\n"			\
+		: "=r"(__gu_val), "=r"(__gu_err) : "m"(__m(addr)), "1"(__gu_err));
 
+#define __get_user_8(addr)									\
+	__asm__ ("\n1:\tld1 %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n"	\
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)|1\n"			\
+		: "=r"(__gu_val), "=r"(__gu_err) : "m"(__m(addr)), "1"(__gu_err));
 
 extern void __put_user_unknown (void);
 
@@ -206,46 +188,26 @@ extern void __put_user_unknown (void);
 #define __put_user_64(x,addr)								\
 	__asm__ __volatile__ (								\
 		 "\n1:\tst8 %1=%r2%P1\t// %0 gets overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 2b-1b\n"							\
-		 "\t.previous"								\
-		: "=r"(__pu_err)							\
-		: "m"(__m(addr)), "rO"(x), "0"(__pu_err))
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)\n"			\
+		: "=r"(__pu_err) : "m"(__m(addr)), "rO"(x), "0"(__pu_err))
 
 #define __put_user_32(x,addr)								\
 	__asm__ __volatile__ (								\
 		 "\n1:\tst4 %1=%r2%P1\t// %0 gets overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 2b-1b\n"							\
-		 "\t.previous"								\
-		: "=r"(__pu_err)							\
-		: "m"(__m(addr)), "rO"(x), "0"(__pu_err))
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)\n"			\
+		: "=r"(__pu_err) : "m"(__m(addr)), "rO"(x), "0"(__pu_err))
 
 #define __put_user_16(x,addr)								\
 	__asm__ __volatile__ (								\
 		 "\n1:\tst2 %1=%r2%P1\t// %0 gets overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 2b-1b\n"							\
-		 "\t.previous"								\
-		: "=r"(__pu_err)							\
-		: "m"(__m(addr)), "rO"(x), "0"(__pu_err))
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)\n"			\
+		: "=r"(__pu_err) : "m"(__m(addr)), "rO"(x), "0"(__pu_err))
 
 #define __put_user_8(x,addr)								\
 	__asm__ __volatile__ (								\
 		 "\n1:\tst1 %1=%r2%P1\t// %0 gets overwritten by exception handler\n"	\
-		 "2:\n"									\
-		 "\t.section __ex_table,\"a\"\n"					\
-		 "\t\tdata4 @gprel(1b)\n"						\
-		 "\t\tdata4 2b-1b\n"							\
-		 "\t.previous"								\
-		: "=r"(__pu_err)							\
-		: "m"(__m(addr)), "rO"(x), "0"(__pu_err))
+		 "2:\n\t.xdata4 \"__ex_table\", @gprel(1b), (2b-1b)\n"			\
+		: "=r"(__pu_err) : "m"(__m(addr)), "rO"(x), "0"(__pu_err))
 
 /*
  * Complex access routines
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index 8b13b8f95..d2e3bdd3e 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -160,7 +160,7 @@
 #define __NR_nanosleep			1168
 #define __NR_nfsservctl			1169
 #define __NR_prctl			1170
-#define __NR_getpagesize		1171
+/* 1171 is reserved for backwards compatibility with old __NR_getpagesize */
 #define __NR_mmap2			1172
 #define __NR_pciconfig_read		1173
 #define __NR_pciconfig_write		1174
@@ -196,7 +196,7 @@
 #define __NR_getsockopt			1204
 #define __NR_sendmsg			1205
 #define __NR_recvmsg			1206
-#define __NR_sys_pivot_root		1207
+#define __NR_pivot_root			1207
 #define __NR_mincore			1208
 #define __NR_madvise			1209
 #define __NR_stat			1210
diff --git a/include/asm-m68k/delay.h b/include/asm-m68k/delay.h
index 731dd0b1a..5955a384c 100644
--- a/include/asm-m68k/delay.h
+++ b/include/asm-m68k/delay.h
@@ -1,10 +1,12 @@
 #ifndef _M68K_DELAY_H
 #define _M68K_DELAY_H
 
+#include <asm/param.h>
+
 /*
  * Copyright (C) 1994 Hamish Macdonald
  *
- * Delay routines, using a pre-computed "loops_per_second" value.
+ * Delay routines, using a pre-computed "loops_per_jiffy" value.
  */
 
 extern __inline__ void __delay(unsigned long loops)
@@ -13,6 +15,8 @@ extern __inline__ void __delay(unsigned long loops)
 		: "=d" (loops) : "0" (loops));
 }
 
+extern void __bad_udelay(void);
+
 /*
  * Use only for very small delays ( < 1 msec).  Should probably use a
  * lookup table, really, as the multiplications take much too long with
@@ -20,17 +24,25 @@ extern __inline__ void __delay(unsigned long loops)
  * first constant multiplications gets optimized away if the delay is
  * a constant)  
  */
-extern __inline__ void udelay(unsigned long usecs)
+static inline void __const_udelay(unsigned long xloops)
 {
 	unsigned long tmp;
 
-	usecs *= 4295;		/* 2**32 / 1000000 */
 	__asm__ ("mulul %2,%0:%1"
-		: "=d" (usecs), "=d" (tmp)
-		: "d" (usecs), "1" (loops_per_sec));
-	__delay(usecs);
+		: "=d" (xloops), "=d" (tmp)
+		: "d" (xloops), "1" (loops_per_jiffy));
+	__delay(xloops * HZ);
+}
+
+static inline void __udelay(unsigned long usecs)
+{
+	__const_udelay(usecs * 4295);	/* 2**32 / 1000000 */
 }
 
+#define udelay(n) (__builtin_constant_p(n) ? \
+	((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 4295)) : \
+	__udelay(n))
+
 extern __inline__ unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c)
 {
 	unsigned long tmp;
diff --git a/include/asm-m68k/floppy.h b/include/asm-m68k/floppy.h
index eace8b552..9caeb6371 100644
--- a/include/asm-m68k/floppy.h
+++ b/include/asm-m68k/floppy.h
@@ -15,6 +15,7 @@
 
 asmlinkage void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs);
 
+#undef MAX_DMA_ADDRESS
 #define MAX_DMA_ADDRESS   0x00  /* nothing like that */
 
 extern spinlock_t  dma_spin_lock;
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index b8057d1ec..7e4cfcc27 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -14,7 +14,7 @@
 #include <asm/virtconvert.h>
 
 /*
- * These are for ISA/PCI shared memory _only_ and should never be used
+ * These are for PCI shared memory _only_ and should never be used
  * on any other type of memory, including Zorro memory. They are meant to
  * access the bus in the bus byte order which is little-endian!.
  *
@@ -47,8 +47,11 @@
 #define outb(x,addr) ((void) writeb(x,addr))
 #define outb_p(x,addr) outb(x,addr)
 
+#ifndef CONFIG_SUN3
 #define IO_SPACE_LIMIT 0xffff
-
+#else
+#define IO_SPACE_LIMIT 0x0fffffff
+#endif
 
 /* Values for nocacheflag and cmode */
 #define IOMAP_FULL_CACHING		0
diff --git a/include/asm-m68k/movs.h b/include/asm-m68k/movs.h
index 540d3e60e..67dbea369 100644
--- a/include/asm-m68k/movs.h
+++ b/include/asm-m68k/movs.h
@@ -10,46 +10,46 @@
 /* Set DFC register value */
 
 #define SET_DFC(x) \
-        __asm__ __volatile__ ("movec %0,%%dfc" : : "r" (x))
+        __asm__ __volatile__ (" movec %0,%/dfc" : : "d" (x));
 
 /* Get DFC register value */
 
 #define GET_DFC(x) \
-        __asm__ __volatile__ ("movec %%dfc,%0" : "=r" (x))
+        __asm__ __volatile__ (" movec %/dfc, %0" : "=d" (x) : );
 
 /* Set SFC register value */
 
 #define SET_SFC(x) \
-        __asm__ __volatile__ ("movec %0,%%sfc" : : "r" (x))
+        __asm__ __volatile__ (" movec %0,%/sfc" : : "d" (x));
 
 /* Get SFC register value */
 
 #define GET_SFC(x) \
-        __asm__ __volatile__ ("movec %%sfc,%0" : "=r" (x))
+        __asm__ __volatile__ (" movec %/sfc, %0" : "=d" (x) : );
 
 #define SET_VBR(x) \
-        __asm__ __volatile__ ("movec %0,%%vbr" : : "r" (x))
+        __asm__ __volatile__ (" movec %0,%/vbr" : : "r" (x));
 
 #define GET_VBR(x) \
-        __asm__ __volatile__ ("movec %%vbr,%0" : "=r" (x))
+        __asm__ __volatile__ (" movec %/vbr, %0" : "=g" (x) : );
 
-/* Set a byte using the "moves" instruction */
+/* Set a byte using the "movs" instruction */
 
 #define SET_CONTROL_BYTE(addr,value) \
-        __asm__ __volatile__ ("movesb %1,%0" : "=m" (addr) : "d" (value))
+        __asm__ __volatile__ (" movsb %0, %1@" : : "d" (value), "a" (addr));
 
-/* Get a byte using the "moves" instruction */
+/* Get a byte using the "movs" instruction */
 
 #define GET_CONTROL_BYTE(addr,value) \
-        __asm__ __volatile__ ("movesb %1,%0" : "=d" (value) : "m" (addr))
+        __asm__ __volatile__ (" movsb %1@, %0" : "=d" (value) : "a" (addr));
 
-/* Set a (long)word using the "moves" instruction */
+/* Set a (long)word using the "movs" instruction */
 
 #define SET_CONTROL_WORD(addr,value) \
-        __asm__ __volatile__ ("movesl %1,%0" : "=m" (addr) : "r" (value))
+        __asm__ __volatile__ (" movsl %0, %1@" : : "d" (value), "a" (addr));
 
-/* Get a (long)word using the "moves" instruction */
+/* Get a (long)word using the "movs" instruction */
 
 #define GET_CONTROL_WORD(addr,value) \
-        __asm__ __volatile__ ("movesl %1,%0" : "=d" (value) : "m" (addr))
+        __asm__ __volatile__ (" movsl %1@, %0" : "=d" (value) : "a" (addr));
 #endif
diff --git a/include/asm-m68k/param.h b/include/asm-m68k/param.h
index 7d37eb540..9c9d81d0f 100644
--- a/include/asm-m68k/param.h
+++ b/include/asm-m68k/param.h
@@ -1,8 +1,6 @@
 #ifndef _M68K_PARAM_H
 #define _M68K_PARAM_H
 
-#include <linux/config.h>
-
 #ifndef HZ
 #define HZ 100
 #ifdef __KERNEL__
@@ -10,11 +8,7 @@
 #endif
 #endif
 
-#ifndef CONFIG_SUN3
-#define EXEC_PAGESIZE	4096
-#else
 #define EXEC_PAGESIZE	8192
-#endif
 
 #ifndef NGROUPS
 #define NGROUPS		32
diff --git a/include/asm-m68k/serial.h b/include/asm-m68k/serial.h
index 15cc547a0..8f8245d5d 100644
--- a/include/asm-m68k/serial.h
+++ b/include/asm-m68k/serial.h
@@ -35,6 +35,9 @@
 #define FOURPORT_FLAGS ASYNC_FOURPORT
 #define ACCENT_FLAGS 0
 #define BOCA_FLAGS 0
+#define RS_TABLE_SIZE  64
+#else
+#define RS_TABLE_SIZE  4
 #endif
 	
 #define STD_SERIAL_PORT_DEFNS			\
diff --git a/include/asm-m68k/traps.h b/include/asm-m68k/traps.h
index c4a7d6baa..ac3abb335 100644
--- a/include/asm-m68k/traps.h
+++ b/include/asm-m68k/traps.h
@@ -151,7 +151,7 @@ extern e_vector vectors[];
 # define MMU060_RW_W	(0x00800000)	/* write */
 # define MMU060_RW_R	(0x01000000)	/* read */
 # define MMU060_RW_RMW	(0x01800000)	/* read/modify/write */
-# define MMU060_W		(0x00800000)	/* general write, includes rmw */
+# define MMU060_W	(0x00800000)	/* general write, includes rmw */
 #define	MMU060_SIZ	(0x00600000)	/* transfer size */
 #define	MMU060_TT	(0x00180000)	/* transfer type (TT) bits */
 #define	MMU060_TM	(0x00070000)	/* transfer modifier (TM) bits */
@@ -172,12 +172,11 @@ extern e_vector vectors[];
 #define	MMU060_SEE	(0x00000001)	/* software emulated error */
 
 /* cases of missing or invalid descriptors */
-#define MMU060_DESC_ERR	(MMU060_TWE | MMU060_PTA | MMU060_PTB | \
-						 MMU060_IL  | MMU060_PF)
+#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \
+			 MMU060_IL  | MMU060_PF)
 /* bits that indicate real errors */
-#define MMU060_ERR_BITS	(MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | \
-						 MMU060_SP  | MMU060_WP  | MMU060_RE | \
-						 MMU060_WE)
+#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \
+			 MMU060_WP  | MMU060_TWE | MMU060_RE       | MMU060_WE)
 
 /* structure for stack frames */
 
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index ed5c57692..5fdb1c6ad 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -16,10 +16,10 @@
 
 static void __init check_bugs(void)
 {
-	extern unsigned long loops_per_sec;
+	extern unsigned long loops_per_jiffy;
 	char *p= &system_utsname.machine[2]; /* "sh" */
 
-	cpu_data->loops_per_sec = loops_per_sec;
+	cpu_data->loops_per_jiffy = loops_per_jiffy;
 	
 	switch (cpu_data->type) {
 	case CPU_SH7708:
diff --git a/include/asm-sh/delay.h b/include/asm-sh/delay.h
index 38e5a48c0..2c1fb7b92 100644
--- a/include/asm-sh/delay.h
+++ b/include/asm-sh/delay.h
@@ -2,41 +2,19 @@
 #define __ASM_SH_DELAY_H
 
 /*
- * Copyright (C) 1999  Kaz Kojima
+ * Copyright (C) 1993 Linus Torvalds
+ *
+ * Delay routines calling functions in arch/sh/lib/delay.c
  */
+ 
+extern void __bad_udelay(void);
 
-#include <linux/config.h>
+extern void __udelay(unsigned long usecs);
+extern void __const_udelay(unsigned long usecs);
+extern void __delay(unsigned long loops);
 
-extern __inline__ void __delay(unsigned long loops)
-{
-	__asm__ __volatile__(
-		"tst	%0, %0\n\t"
-		"1:\t"
-		"bf/s	1b\n\t"
-		" dt	%0"
-		: "=r" (loops)
-		: "0" (loops)
-		: "t");
-}
-
-extern __inline__ void __udelay(unsigned long usecs, unsigned long lps)
-{
-	usecs *= 0x000010c6;		/* 2**32 / 1000000 */
-	__asm__("dmulu.l	%0, %2\n\t"
-		"sts	$mach, %0"
-		: "=r" (usecs)
-		: "0" (usecs), "r" (lps)
-		: "macl", "mach");
-        __delay(usecs);
-}
-
-
-#ifdef CONFIG_SMP
-#define __udelay_val cpu_data[smp_processor_id()].udelay_val
-#else
-#define __udelay_val (current_cpu_data.loops_per_sec)
-#endif
-
-#define udelay(usecs) __udelay((usecs),__udelay_val)
+#define udelay(n) (__builtin_constant_p(n) ? \
+	((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
+	__udelay(n))
 
 #endif /* __ASM_SH_DELAY_H */
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index 268754e71..3a1f034c2 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -104,6 +104,7 @@ extern __inline__ void destroy_context(struct mm_struct *mm)
 #define MMU_PTEL	0xFF000004	/* Page table entry register LOW */
 #define MMU_TTB		0xFF000008	/* Translation table base register */
 #define MMU_TEA		0xFF00000C	/* TLB Exception Address */
+#define MMU_PTEA	0xFF000034	/* Page table entry assistance register */
 
 #define MMUCR		0xFF000010	/* MMU Control Register */
 
diff --git a/include/asm-sh/param.h b/include/asm-sh/param.h
index bc1879c96..fc134a5bc 100644
--- a/include/asm-sh/param.h
+++ b/include/asm-sh/param.h
@@ -20,4 +20,8 @@
 
 #define MAXHOSTNAMELEN	64	/* max length of hostname */
 
+#ifdef __KERNEL__
+#define CLOCKS_PER_SEC	HZ	/* frequency at which times() counts */
+#endif
+
 #endif /* __ASM_SH_PARAM_H */
diff --git a/include/asm-sh/pgtable-2level.h b/include/asm-sh/pgtable-2level.h
index 8fc2666e7..5a11978af 100644
--- a/include/asm-sh/pgtable-2level.h
+++ b/include/asm-sh/pgtable-2level.h
@@ -29,9 +29,9 @@
  * setup: the pgd is never bad, and a pmd always exists (as it's folded
  * into the pgd entry)
  */
-extern inline int pgd_none(pgd_t pgd)		{ return 0; }
-extern inline int pgd_bad(pgd_t pgd)		{ return 0; }
-extern inline int pgd_present(pgd_t pgd)	{ return 1; }
+static inline int pgd_none(pgd_t pgd)		{ return 0; }
+static inline int pgd_bad(pgd_t pgd)		{ return 0; }
+static inline int pgd_present(pgd_t pgd)	{ return 1; }
 #define pgd_clear(xp)	do { } while (0)
 
 /*
@@ -50,7 +50,7 @@ extern inline int pgd_present(pgd_t pgd)	{ return 1; }
 #define pgd_page(pgd) \
 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
 
-extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
+static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 {
 	return (pmd_t *) dir;
 }
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 2246e5c0d..b1a6f9461 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -105,8 +105,23 @@ extern unsigned long empty_zero_page[1024];
 #define _PAGE_ACCESSED 	0x400  /* software: page referenced */
 #define _PAGE_U0_SHARED 0x800  /* software: page is shared in user space */
 
+
+/* software: moves to PTEA.TC (Timing Control) */
+#define _PAGE_PCC_AREA5	0x00000000	/* use BSC registers for area5 */
+#define _PAGE_PCC_AREA6	0x80000000	/* use BSC registers for area6 */
+
+/* software: moves to PTEA.SA[2:0] (Space Attributes) */
+#define _PAGE_PCC_IODYN 0x00000001	/* IO space, dynamically sized bus */
+#define _PAGE_PCC_IO8	0x20000000	/* IO space, 8 bit bus */
+#define _PAGE_PCC_IO16	0x20000001	/* IO space, 16 bit bus */
+#define _PAGE_PCC_COM8	0x40000000	/* Common Memory space, 8 bit bus */
+#define _PAGE_PCC_COM16	0x40000001	/* Common Memory space, 16 bit bus */
+#define _PAGE_PCC_ATR8	0x60000000	/* Attribute Memory space, 8 bit bus */
+#define _PAGE_PCC_ATR16	0x60000001	/* Attribute Memory space, 6 bit bus */
+
+
 /* Mask which drop software flags */
-#define _PAGE_FLAGS_HARDWARE_MASK	0x1ffff1ff
+#define _PAGE_FLAGS_HARDWARE_MASK	0x1ffff1fe
 /* Hardware flags: SZ=1 (4k-byte) */
 #define _PAGE_FLAGS_HARD		0x00000010
 
@@ -126,6 +141,8 @@ extern unsigned long empty_zero_page[1024];
 #define PAGE_READONLY	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
 #define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
 #define PAGE_KERNEL_RO	__pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+#define PAGE_KERNEL_PCC(slot, type) \
+			__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type))
 
 /*
  * As i386 and MIPS, SuperH can't do page protection for execute, and
@@ -178,23 +195,23 @@ extern void __handle_bad_pmd_kernel(pmd_t * pmd);
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
  */
-extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
-extern inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
-extern inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
-extern inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
-extern inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; }
-extern inline int pte_shared(pte_t pte){ return pte_val(pte) & _PAGE_SHARED; }
-
-extern inline pte_t pte_rdprotect(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
-extern inline pte_t pte_exprotect(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
-extern inline pte_t pte_mkclean(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
-extern inline pte_t pte_mkold(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
-extern inline pte_t pte_wrprotect(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
-extern inline pte_t pte_mkread(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
-extern inline pte_t pte_mkexec(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
-extern inline pte_t pte_mkdirty(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
-extern inline pte_t pte_mkyoung(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
-extern inline pte_t pte_mkwrite(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
+static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; }
+static inline int pte_shared(pte_t pte){ return pte_val(pte) & _PAGE_SHARED; }
+
+static inline pte_t pte_rdprotect(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
+static inline pte_t pte_exprotect(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
+static inline pte_t pte_mkclean(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
+static inline pte_t pte_mkold(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
+static inline pte_t pte_wrprotect(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
+static inline pte_t pte_mkread(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
+static inline pte_t pte_mkexec(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
+static inline pte_t pte_mkdirty(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
+static inline pte_t pte_mkyoung(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
+static inline pte_t pte_mkwrite(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
 
 /*
  * Conversion functions: convert a page and protection to a page entry,
@@ -215,7 +232,7 @@ extern inline pte_t pte_mkwrite(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) |
 #define mk_pte_phys(physpage, pgprot) \
 ({ pte_t __pte; set_pte(&__pte, __pte(physpage + pgprot_val(pgprot))); __pte; })
 
-extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
 
 #define page_pte(page) page_pte_prot(page, __pgprot(0))
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 8c4ba40d8..3259acb23 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -29,7 +29,7 @@ enum cpu_type {
 
 struct sh_cpuinfo {
 	enum cpu_type type;
-	unsigned long loops_per_sec;
+	unsigned long loops_per_jiffy;
 
 	char	hard_math;
 
@@ -164,9 +164,9 @@ extern __inline__ void release_fpu(void)
 	unsigned long __dummy;
 
 	/* Set FD flag in SR */
-	__asm__ __volatile__("stc	$sr, %0\n\t"
+	__asm__ __volatile__("stc	sr, %0\n\t"
 			     "or	%1, %0\n\t"
-			     "ldc	%0, $sr"
+			     "ldc	%0, sr"
 			     : "=&r" (__dummy)
 			     : "r" (SR_FD));
 }
@@ -176,9 +176,9 @@ extern __inline__ void grab_fpu(void)
 	unsigned long __dummy;
 
 	/* Clear out FD flag in SR */
-	__asm__ __volatile__("stc	$sr, %0\n\t"
+	__asm__ __volatile__("stc	sr, %0\n\t"
 			     "and	%1, %0\n\t"
-			     "ldc	%0, $sr"
+			     "ldc	%0, sr"
 			     : "=&r" (__dummy)
 			     : "r" (~SR_FD));
 }
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
index e716331ee..081adbfb3 100644
--- a/include/asm-sh/ptrace.h
+++ b/include/asm-sh/ptrace.h
@@ -42,6 +42,11 @@
 #define REG_XDREG14	47
 #define REG_FPSCR	48
 
+#define PTRACE_SETOPTIONS         21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD     0x00000001
+
 /*
  * This struct defines the way the registers are stored on the
  * kernel stack during a system call or other kernel entry.
diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h
new file mode 100644
index 000000000..3321bc7e8
--- /dev/null
+++ b/include/asm-sh/rtc.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_RTC_H
+#define _ASM_RTC_H
+
+#include <asm/machvec.h>
+
+#define rtc_gettimeofday sh_mv.mv_rtc_gettimeofday
+#define rtc_settimeofday sh_mv.mv_rtc_settimeofday
+
+extern void sh_rtc_gettimeofday(struct timeval *tv);
+extern int sh_rtc_settimeofday(const struct timeval *tv);
+
+#endif /* _ASM_RTC_H */
diff --git a/include/asm-sh/siginfo.h b/include/asm-sh/siginfo.h
index aa4354a45..aa6a1c46f 100644
--- a/include/asm-sh/siginfo.h
+++ b/include/asm-sh/siginfo.h
@@ -216,7 +216,7 @@ typedef struct sigevent {
 #ifdef __KERNEL__
 #include <linux/string.h>
 
-extern inline void copy_siginfo(siginfo_t *to, siginfo_t *from)
+static inline void copy_siginfo(siginfo_t *to, siginfo_t *from)
 {
 	if (from->si_code < 0)
 		memcpy(to, from, sizeof(siginfo_t));
diff --git a/include/asm-sh/timex.h b/include/asm-sh/timex.h
index 2351c2f0b..72a0cd593 100644
--- a/include/asm-sh/timex.h
+++ b/include/asm-sh/timex.h
@@ -6,7 +6,7 @@
 #ifndef __ASM_SH_TIMEX_H
 #define __ASM_SH_TIMEX_H
 
-#define CLOCK_TICK_RATE	1193180 /* Underlying HZ */
+#define CLOCK_TICK_RATE	(current_cpu_data.module_clock/4) /* Underlying HZ */
 #define CLOCK_TICK_FACTOR	20	/* Factor of both 1000000 and CLOCK_TICK_RATE */
 #define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
 	(1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h
index 4fe09b005..947fd12c8 100644
--- a/include/asm-sh/uaccess.h
+++ b/include/asm-sh/uaccess.h
@@ -56,7 +56,7 @@
 #define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
 #define __access_ok(addr,size) (__range_ok(addr,size) == 0)
 
-extern inline int verify_area(int type, const void * addr, unsigned long size)
+static inline int verify_area(int type, const void * addr, unsigned long size)
 {
 	return access_ok(type,addr,size) ? 0 : -EFAULT;
 }
@@ -66,7 +66,7 @@ extern inline int verify_area(int type, const void * addr, unsigned long size)
  * They automatically use the right size if we just have the right
  * pointer type ...
  *
- * As MIPS uses the same address space for kernel and user data, we
+ * As SuperH uses the same address space for kernel and user data, we
  * can just do these as direct assignments.
  *
  * Careful to not
diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h
index 4a55a8929..1e07b88f7 100644
--- a/include/asm-sparc/atomic.h
+++ b/include/asm-sparc/atomic.h
@@ -133,6 +133,8 @@ static __inline__ int atomic_sub_return(int i, atomic_t *v)
 #define atomic_inc(v) atomic_add(1,(v))
 #define atomic_dec(v) atomic_sub(1,(v))
 
+#define atomic_add_negative(i, v) (atomic_add_return((i), (v)) < 0)
+
 #endif /* !(__KERNEL__) */
 
 #endif /* !(__ARCH_SPARC_ATOMIC__) */
diff --git a/include/asm-sparc/contregs.h b/include/asm-sparc/contregs.h
index 3e4f5075e..0e05afe02 100644
--- a/include/asm-sparc/contregs.h
+++ b/include/asm-sparc/contregs.h
@@ -1,4 +1,4 @@
-/* $Id: contregs.h,v 1.7 1998/01/30 10:59:48 jj Exp $ */
+/* $Id: contregs.h,v 1.8 2000/12/28 22:49:11 davem Exp $ */
 #ifndef _SPARC_CONTREGS_H
 #define _SPARC_CONTREGS_H
 
diff --git a/include/asm-sparc/delay.h b/include/asm-sparc/delay.h
index dcb477a6c..e3994705a 100644
--- a/include/asm-sparc/delay.h
+++ b/include/asm-sparc/delay.h
@@ -1,4 +1,4 @@
-/* $Id: delay.h,v 1.10 1997/11/07 18:24:30 mj Exp $
+/* $Id: delay.h,v 1.11 2001/01/01 01:46:15 davem Exp $
  * delay.h: Linux delay routines on the Sparc.
  *
  * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu).
@@ -7,7 +7,7 @@
 #ifndef __SPARC_DELAY_H
 #define __SPARC_DELAY_H
 
-extern unsigned long loops_per_sec;
+extern unsigned long loops_per_jiffy;
 
 extern __inline__ void __delay(unsigned long loops)
 {
diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h
index 2be6f36f0..092f1ca25 100644
--- a/include/asm-sparc/processor.h
+++ b/include/asm-sparc/processor.h
@@ -1,4 +1,4 @@
-/* $Id: processor.h,v 1.78 2000/11/30 08:37:31 anton Exp $
+/* $Id: processor.h,v 1.80 2000/12/31 10:05:43 davem Exp $
  * include/asm-sparc/processor.h
  *
  * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
diff --git a/include/asm-sparc/semaphore-helper.h b/include/asm-sparc/semaphore-helper.h
deleted file mode 100644
index a4dd421be..000000000
--- a/include/asm-sparc/semaphore-helper.h
+++ /dev/null
@@ -1,169 +0,0 @@
-#ifndef _SPARC_SEMAPHORE_HELPER_H
-#define _SPARC_SEMAPHORE_HELPER_H
-
-#include <linux/config.h>
-
-/*
- * (barely) SMP- and interrupt-safe semaphore helper functions, sparc version.
- *
- * (C) Copyright 1999 David S. Miller (davem@redhat.com)
- * (C) Copyright 1999 Jakub Jelinek (jj@ultra.linux.cz)
- */
-#define wake_one_more(sem)	atomic_inc(&(sem)->waking)
-static __inline__ int waking_non_zero(struct semaphore *sem)
-{
-	int ret;
-
-#ifdef CONFIG_SMP
-	int tmp;
-
-	__asm__ __volatile__("
-		rd	%%psr, %%g1
-		or	%%g1, %3, %0
-		wr	%0, 0x0, %%psr
-		nop; nop; nop;
-1:		ldstub	[%2 + 3], %0
-		tst	%0
-		bne	1b
-		ld	[%2], %0
-		andn	%0, 0xff, %1
-		subcc	%0, 0x1ff, %0
-		bl,a	1f
-		 mov	0, %0
-		mov	%0, %1
-		mov	1, %0
-1:		st	%1, [%2]
-		wr	%%g1, 0x0, %%psr
-		nop; nop; nop\n" 
-	: "=&r" (ret), "=&r" (tmp)
-	: "r" (&sem->waking), "i" (PSR_PIL)
-	: "g1", "memory", "cc");
-#else
-	__asm__ __volatile__("
-		rd	%%psr, %%g1
-		or	%%g1, %2, %0
-		wr	%0, 0x0, %%psr
-		nop; nop; nop;
-		ld	[%1], %0
-		subcc	%0, 1, %0
-		bl,a	1f
-		 mov	0, %0
-		st	%0, [%1]
-		mov	1, %0
-1:		wr	%%g1, 0x0, %%psr
-		nop; nop; nop\n" 
-	: "=&r" (ret)
-	: "r" (&sem->waking), "i" (PSR_PIL)
-	: "g1", "memory", "cc");
-#endif
-	return ret;
-}
-
-static __inline__ int waking_non_zero_interruptible(struct semaphore *sem,
-						    struct task_struct *tsk)
-{
-	int ret;
-
-#ifdef CONFIG_SMP
-	int tmp;
-
-	__asm__ __volatile__("
-		rd	%%psr, %%g1
-		or	%%g1, %3, %0
-		wr	%0, 0x0, %%psr
-		nop; nop; nop;
-1:		ldstub	[%2 + 3], %0
-		tst	%0
-		bne	1b
-		ld	[%2], %0
-		andn	%0, 0xff, %1
-		subcc	%0, 0x1ff, %0
-		bl,a	1f
-		 mov	0, %0
-		mov	%0, %1
-		mov	1, %0
-1:		st	%1, [%2]
-		wr	%%g1, 0x0, %%psr
-		nop; nop; nop\n" 
-	: "=&r" (ret), "=&r" (tmp)
-	: "r" (&sem->waking), "i" (PSR_PIL)
-	: "g1", "memory", "cc");
-#else
-	__asm__ __volatile__("
-		rd	%%psr, %%g1
-		or	%%g1, %2, %0
-		wr	%0, 0x0, %%psr
-		nop; nop; nop;
-		ld	[%1], %0
-		subcc	%0, 1, %0
-		bl,a	1f
-		 mov	0, %0
-		st	%0, [%1]
-		mov	1, %0
-1:		wr	%%g1, 0x0, %%psr
-		nop; nop; nop\n" 
-	: "=&r" (ret)
-	: "r" (&sem->waking), "i" (PSR_PIL)
-	: "g1", "memory", "cc");
-#endif
-	if(ret == 0 && signal_pending(tsk)) {
-		atomic_inc(&sem->count);
-		ret = -EINTR;
-	}
-	return ret;
-}
-
-static __inline__ int waking_non_zero_trylock(struct semaphore *sem)
-{
-	int ret;
-
-#ifdef CONFIG_SMP
-	int tmp;
-
-	__asm__ __volatile__("
-		rd	%%psr, %%g1
-		or	%%g1, %3, %0
-		wr	%0, 0x0, %%psr
-		nop; nop; nop;
-1:		ldstub	[%2 + 3], %0
-		tst	%0
-		bne	1b
-		ld	[%2], %0
-		andn	%0, 0xff, %1
-		subcc	%0, 0x1ff, %0
-		bl,a	1f
-		 mov	0, %0
-		mov	%0, %1
-		mov	1, %0
-1:		st	%1, [%2]
-		wr	%%g1, 0x0, %%psr
-		nop; nop; nop\n" 
-	: "=&r" (ret), "=&r" (tmp)
-	: "r" (&sem->waking), "i" (PSR_PIL)
-	: "g1", "memory", "cc");
-#else
-	__asm__ __volatile__("
-		rd	%%psr, %%g1
-		or	%%g1, %2, %0
-		wr	%0, 0x0, %%psr
-		nop; nop; nop;
-		ld	[%1], %0
-		subcc	%0, 1, %0
-		bl,a	1f
-		 mov	0, %0
-		st	%0, [%1]
-		mov	1, %0
-1:		wr	%%g1, 0x0, %%psr
-		nop; nop; nop\n" 
-	: "=&r" (ret)
-	: "r" (&sem->waking), "i" (PSR_PIL)
-	: "g1", "memory", "cc");
-#endif
-	ret = !ret;
-	if(ret == 1)
-		atomic_inc(&sem->count);
-	return ret;
-}
-
-#endif /* !(_SPARC_SEMAPHORE_HELPER_H) */
-
diff --git a/include/asm-sparc/semaphore.h b/include/asm-sparc/semaphore.h
index ec2471223..cee9745b6 100644
--- a/include/asm-sparc/semaphore.h
+++ b/include/asm-sparc/semaphore.h
@@ -10,7 +10,7 @@
 
 struct semaphore {
 	atomic_t count;
-	atomic_t waking;
+	int sleepers;
 	wait_queue_head_t wait;
 #if WAITQUEUE_DEBUG
 	long __magic;
@@ -25,7 +25,7 @@ struct semaphore {
 #endif
 
 #define __SEMAPHORE_INITIALIZER(name,count) \
-{ ATOMIC_INIT(count), ATOMIC_INIT(0), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
+{ ATOMIC_INIT(count), 0, __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
 	__SEM_DEBUG_INIT(name) }
 
 #define __MUTEX_INITIALIZER(name) \
@@ -37,10 +37,10 @@ struct semaphore {
 #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
 #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
 
-extern inline void sema_init (struct semaphore *sem, int val)
+static inline void sema_init (struct semaphore *sem, int val)
 {
 	atomic_set(&sem->count, val);
-	atomic_set(&sem->waking, 0);
+	sem->sleepers = 0;
 	init_waitqueue_head(&sem->wait);
 #if WAITQUEUE_DEBUG
 	sem->__magic = (long)&sem->__magic;
@@ -62,7 +62,7 @@ extern int __down_interruptible(struct semaphore * sem);
 extern int __down_trylock(struct semaphore * sem);
 extern void __up(struct semaphore * sem);
 
-extern inline void down(struct semaphore * sem)
+static inline void down(struct semaphore * sem)
 {
 	register atomic_t *ptr asm("g1");
 	register int increment asm("g2");
@@ -97,7 +97,7 @@ extern inline void down(struct semaphore * sem)
 	: "g3", "g4", "g7", "memory", "cc");
 }
 
-extern inline int down_interruptible(struct semaphore * sem)
+static inline int down_interruptible(struct semaphore * sem)
 {
 	register atomic_t *ptr asm("g1");
 	register int increment asm("g2");
@@ -135,7 +135,7 @@ extern inline int down_interruptible(struct semaphore * sem)
 	return increment;
 }
 
-extern inline int down_trylock(struct semaphore * sem)
+static inline int down_trylock(struct semaphore * sem)
 {
 	register atomic_t *ptr asm("g1");
 	register int increment asm("g2");
@@ -173,7 +173,7 @@ extern inline int down_trylock(struct semaphore * sem)
 	return increment;
 }
 
-extern inline void up(struct semaphore * sem)
+static inline void up(struct semaphore * sem)
 {
 	register atomic_t *ptr asm("g1");
 	register int increment asm("g2");
@@ -262,7 +262,7 @@ struct rw_semaphore {
 #define DECLARE_RWSEM_READ_LOCKED(name) __DECLARE_RWSEM_GENERIC(name,RW_LOCK_BIAS-1)
 #define DECLARE_RWSEM_WRITE_LOCKED(name) __DECLARE_RWSEM_GENERIC(name,0)
 
-extern inline void init_rwsem(struct rw_semaphore *sem)
+static inline void init_rwsem(struct rw_semaphore *sem)
 {
 	sem->count = RW_LOCK_BIAS;
 	sem->lock = 0;
@@ -282,7 +282,7 @@ extern void ___down_write(/* Special calling convention */ void);
 extern void ___up_read(/* Special calling convention */ void);
 extern void ___up_write(/* Special calling convention */ void);
 
-extern inline void down_read(struct rw_semaphore *sem)
+static inline void down_read(struct rw_semaphore *sem)
 {
 	register atomic_t *ptr asm("g1");
 
@@ -308,7 +308,7 @@ extern inline void down_read(struct rw_semaphore *sem)
 #endif
 }
 
-extern inline void down_write(struct rw_semaphore *sem)
+static inline void down_write(struct rw_semaphore *sem)
 {
 	register atomic_t *ptr asm("g1");
 
@@ -342,7 +342,7 @@ extern inline void down_write(struct rw_semaphore *sem)
  * case is when there was a writer waiting, and we've
  * bumped the count to 0: we must wake the writer up.
  */
-extern inline void __up_read(struct rw_semaphore *sem)
+static inline void __up_read(struct rw_semaphore *sem)
 {
 	register atomic_t *ptr asm("g1");
 
@@ -360,7 +360,7 @@ extern inline void __up_read(struct rw_semaphore *sem)
 /* releasing the writer is easy -- just release it and
  * wake up any sleepers.
  */
-extern inline void __up_write(struct rw_semaphore *sem)
+static inline void __up_write(struct rw_semaphore *sem)
 {
 	register atomic_t *ptr asm("g1");
 
@@ -375,7 +375,7 @@ extern inline void __up_write(struct rw_semaphore *sem)
 	: "g2", "g3", "g4", "g7", "memory", "cc");
 }
 
-extern inline void up_read(struct rw_semaphore *sem)
+static inline void up_read(struct rw_semaphore *sem)
 {
 #if WAITQUEUE_DEBUG
 	if (!sem->write_not_granted)
@@ -387,7 +387,7 @@ extern inline void up_read(struct rw_semaphore *sem)
 	__up_read(sem);
 }
 
-extern inline void up_write(struct rw_semaphore *sem)
+static inline void up_write(struct rw_semaphore *sem)
 {
 #if WAITQUEUE_DEBUG
 	if (!sem->read_not_granted)
diff --git a/include/asm-sparc64/delay.h b/include/asm-sparc64/delay.h
index 1dc636453..62e558873 100644
--- a/include/asm-sparc64/delay.h
+++ b/include/asm-sparc64/delay.h
@@ -1,4 +1,4 @@
-/* $Id: delay.h,v 1.9 2000/05/09 17:40:15 davem Exp $
+/* $Id: delay.h,v 1.11 2001/01/02 08:15:32 davem Exp $
  * delay.h: Linux delay routines on the V9.
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu).
@@ -8,6 +8,7 @@
 #define __SPARC64_DELAY_H
 
 #include <linux/config.h>
+#include <linux/param.h>
 #ifdef CONFIG_SMP
 #include <linux/sched.h>
 #include <asm/smp.h>
@@ -37,13 +38,13 @@ extern __inline__ void __udelay(unsigned long usecs, unsigned long lps)
 "	: "=r" (usecs)
 	: "r" (usecs), "r" (lps));
 
-	__delay(usecs);
+	__delay(usecs * HZ);
 }
 
 #ifdef CONFIG_SMP
 #define __udelay_val cpu_data[smp_processor_id()].udelay_val
 #else
-#define __udelay_val loops_per_sec
+#define __udelay_val loops_per_jiffy
 #endif
 
 #define udelay(usecs) __udelay((usecs),__udelay_val)
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h
index f26dd254d..5e9203f13 100644
--- a/include/asm-sparc64/processor.h
+++ b/include/asm-sparc64/processor.h
@@ -1,4 +1,4 @@
-/* $Id: processor.h,v 1.66 2000/11/29 05:56:12 anton Exp $
+/* $Id: processor.h,v 1.68 2000/12/31 10:05:43 davem Exp $
  * include/asm-sparc64/processor.h
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 695d4bb67..0d6f9ac13 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -115,6 +115,7 @@ d_iput:		no		no		yes
 					 * If this dentry points to a directory, then
 					 * s_nfsd_free_path semaphore will be down
 					 */
+#define DCACHE_REFERENCED	0x0008  /* Recently used, don't discard. */
 
 extern spinlock_t dcache_lock;
 
diff --git a/include/linux/delay.h b/include/linux/delay.h
index 0454b786d..fc57b1c89 100644
--- a/include/linux/delay.h
+++ b/include/linux/delay.h
@@ -13,7 +13,7 @@ extern unsigned long loops_per_jiffy;
 
 /*
  * Using udelay() for intervals greater than a few milliseconds can
- * risk overflow for high loops_per_sec (high bogomips) machines. The
+ * risk overflow for high loops_per_jiffy (high bogomips) machines. The
  * mdelay() provides a wrapper to prevent this.  For delays greater
  * than MAX_UDELAY_MS milliseconds, the wrapper is used.  Architecture
  * specific values can be defined in asm-???/delay.h as an override.
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
index cab50dd9e..455acd9ab 100644
--- a/include/linux/mc146818rtc.h
+++ b/include/linux/mc146818rtc.h
@@ -15,6 +15,8 @@
 #include <linux/rtc.h>			/* get the user-level API */
 #include <asm/mc146818rtc.h>		/* register access macros */
 
+extern spinlock_t rtc_lock;		/* serialize CMOS RAM access */
+
 /**********************************************************************
  * register summary
  **********************************************************************/
diff --git a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h
index a8fd001bc..f1ff9ecb4 100644
--- a/include/linux/netfilter_ipv4/ip_conntrack.h
+++ b/include/linux/netfilter_ipv4/ip_conntrack.h
@@ -101,7 +101,7 @@ struct ip_conntrack
 	struct ip_conntrack_tuple_hash tuplehash[IP_CT_DIR_MAX];
 
 	/* Have we seen traffic both ways yet? (bitset) */
-	volatile unsigned int status;
+	volatile unsigned long status;
 
 	/* Timer function; drops refcnt when it goes off. */
 	struct timer_list timeout;
diff --git a/include/linux/netfilter_ipv4/lockhelp.h b/include/linux/netfilter_ipv4/lockhelp.h
index 89dd63f9f..46a688e59 100644
--- a/include/linux/netfilter_ipv4/lockhelp.h
+++ b/include/linux/netfilter_ipv4/lockhelp.h
@@ -19,8 +19,8 @@ struct spinlock_debug
 struct rwlock_debug
 {
 	rwlock_t l;
-	int read_locked_map;
-	int write_locked_map;
+	long read_locked_map;
+	long write_locked_map;
 };
 
 #define DECLARE_LOCK(l) 						\
diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h
index aa1ad6f0f..f6da04e49 100644
--- a/include/linux/netfilter_ipv6.h
+++ b/include/linux/netfilter_ipv6.h
@@ -54,7 +54,7 @@
 #define NF_IP6_NUMHOOKS		5
 
 
-enum nf_ip_hook_priorities {
+enum nf_ip6_hook_priorities {
 	NF_IP6_PRI_FIRST = INT_MIN,
 	NF_IP6_PRI_CONNTRACK = -200,
 	NF_IP6_PRI_MANGLE = -150,
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 2b2a461b8..2490818f4 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -358,6 +358,7 @@
 #define PCI_DEVICE_ID_SI_601		0x0601
 #define PCI_DEVICE_ID_SI_620		0x0620
 #define PCI_DEVICE_ID_SI_630		0x0630
+#define PCI_DEVICE_ID_SI_730		0x0730         
 #define PCI_DEVICE_ID_SI_630_VGA	0x6300
 #define PCI_DEVICE_ID_SI_730_VGA	0x7300
 #define PCI_DEVICE_ID_SI_5107		0x5107
diff --git a/include/linux/rtc.h b/include/linux/rtc.h
index ea2226d1f..fba9111da 100644
--- a/include/linux/rtc.h
+++ b/include/linux/rtc.h
@@ -2,6 +2,8 @@
  * Generic RTC interface.
  * This version contains the part of the user interface to the Real Time Clock
  * service. It is used with both the legacy mc146818 and also  EFI
+ * Struct rtc_time and first 12 ioctl by Paul Gortmaker, 1996 - separated out
+ * from <linux/mc146818rtc.h> to this file for 2.4 kernels.
  * 
  * Copyright (C) 1999 Hewlett-Packard Co.
  * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
diff --git a/include/linux/scc.h b/include/linux/scc.h
index fbe189460..a896704e6 100644
--- a/include/linux/scc.h
+++ b/include/linux/scc.h
@@ -8,7 +8,7 @@
 /* selection of hardware types */
 
 #define PA0HZP		0x00	/* hardware type for PA0HZP SCC card and compatible */
-#define EAGLE         	0x01    /* hardware type for EAGLE card */
+#define EAGLE		0x01    /* hardware type for EAGLE card */
 #define PC100		0x02	/* hardware type for PC100 card */
 #define PRIMUS		0x04	/* hardware type for PRIMUS-PC (DG9BL) card */
 #define DRSI		0x08	/* hardware type for DRSI PC*Packet card */
@@ -28,10 +28,6 @@ enum SCC_ioctl_cmds {
 	SIOCSCCCAL
 };
 
-/* magic number */
-
-#define SCC_MAGIC	0x8530		/* ;-) */
-
 /* Device parameter control (from WAMPES) */
 
 enum L1_params {
@@ -218,7 +214,7 @@ struct scc_kiss {
 
 struct scc_channel {
 	int magic;			/* magic word */
-	
+
 	int init;			/* channel exists? */
 
 	struct net_device *dev;		/* link to device control structure */
@@ -226,12 +222,12 @@ struct scc_channel {
 
 	char brand;			/* manufacturer of the board */
 	long clock;			/* used clock */
-	
+
 	io_port ctrl;			/* I/O address of CONTROL register */
 	io_port	data;			/* I/O address of DATA register */
 	io_port special;		/* I/O address of special function port */
 	int irq;			/* Number of Interrupt */
-	
+
 	char option;
 	char enhanced;			/* Enhanced SCC support */
 
@@ -242,17 +238,15 @@ struct scc_channel {
         struct scc_kiss kiss;		/* control structure for KISS params */
         struct scc_stat stat;		/* statistical information */
         struct scc_modem modem; 	/* modem information */
-        
+
         struct sk_buff_head tx_queue;	/* next tx buffer */
         struct sk_buff *rx_buff;	/* pointer to frame currently received */
         struct sk_buff *tx_buff;	/* pointer to frame currently transmitted */
 
 	/* Timer */
-
 	struct timer_list tx_t;		/* tx timer for this channel */
 	struct timer_list tx_wdog;	/* tx watchdogs */
 };
 
-int scc_init(void);
 #endif /* defined(__KERNEL__) */
 #endif /* defined(_SCC_H) */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 4be0dd7d5..1e3dbe20f 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -136,6 +136,7 @@ struct sched_param {
  */
 extern rwlock_t tasklist_lock;
 extern spinlock_t runqueue_lock;
+extern spinlock_t mmlist_lock;
 
 extern void sched_init(void);
 extern void init_idle(void);
@@ -209,6 +210,9 @@ struct mm_struct {
 	int map_count;				/* number of VMAs */
 	struct semaphore mmap_sem;
 	spinlock_t page_table_lock;
+
+	struct list_head mmlist;		/* List of all active mm's */
+
 	unsigned long start_code, end_code, start_data, end_data;
 	unsigned long start_brk, brk, start_stack;
 	unsigned long arg_start, arg_end, env_start, env_end;
@@ -233,6 +237,7 @@ struct mm_struct {
 	map_count:	1, 				\
 	mmap_sem:	__MUTEX_INITIALIZER(name.mmap_sem), \
 	page_table_lock: SPIN_LOCK_UNLOCKED, 		\
+	mmlist:		LIST_HEAD_INIT(name.mmlist),	\
 }
 
 struct signal_struct {
diff --git a/include/linux/udf_fs.h b/include/linux/udf_fs.h
index c1a255da9..65c6a561a 100644
--- a/include/linux/udf_fs.h
+++ b/include/linux/udf_fs.h
@@ -45,15 +45,15 @@
 #ifdef UDFFS_DEBUG
 #define udf_debug(f, a...) \
 	{ \
-		printk (KERN_DEBUG "UDF-fs DEBUG (%s, %d): %s: ", \
+		printk (KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \
 			__FILE__, __LINE__, __FUNCTION__); \
-		printk (## f, ## a); \
+		printk (f, ##a); \
 	}
 #else
 #define udf_debug(f, a...) /**/
 #endif
 
 #define udf_info(f, a...) \
-		printk (KERN_INFO "UDF-fs INFO " ## f, ## a);
+		printk (KERN_INFO "UDF-fs INFO " f, ##a);
 
 #endif /* !defined(_LINUX_UDF_FS_H) */
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 39e9f2eed..5ca846eb1 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -315,7 +315,41 @@ struct usb_device;
  * Terminate the driver's table with an all-zeroes entry.
  * Init the fields you care about; zeroes are not used in comparisons.
  */
+#define USB_DEVICE_ID_MATCH_VENDOR		0x0001
+#define USB_DEVICE_ID_MATCH_PRODUCT		0x0002
+#define USB_DEVICE_ID_MATCH_DEV_LO		0x0004
+#define USB_DEVICE_ID_MATCH_DEV_HI		0x0008
+#define USB_DEVICE_ID_MATCH_DEV_CLASS		0x0010
+#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS	0x0020
+#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL	0x0040
+#define USB_DEVICE_ID_MATCH_INT_CLASS		0x0080
+#define USB_DEVICE_ID_MATCH_INT_SUBCLASS	0x0100
+#define USB_DEVICE_ID_MATCH_INT_PROTOCOL	0x0200
+
+#define USB_DEVICE_ID_MATCH_DEVICE		(USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT)
+#define USB_DEVICE_ID_MATCH_DEV_RANGE		(USB_DEVICE_ID_MATCH_DEV_LO | USB_DEVICE_ID_MATCH_DEV_HI)
+#define USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION	(USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_RANGE)
+#define USB_DEVICE_ID_MATCH_DEV_INFO \
+	(USB_DEVICE_ID_MATCH_DEV_CLASS | USB_DEVICE_ID_MATCH_DEV_SUBCLASS | USB_DEVICE_ID_MATCH_DEV_PROTOCOL)
+#define USB_DEVICE_ID_MATCH_INT_INFO \
+	(USB_DEVICE_ID_MATCH_INT_CLASS | USB_DEVICE_ID_MATCH_INT_SUBCLASS | USB_DEVICE_ID_MATCH_INT_PROTOCOL)
+
+/* Some useful macros */
+#define USB_DEVICE(vend,prod) \
+	match_flags: USB_DEVICE_ID_MATCH_DEVICE, idVendor: (vend), idProduct: (prod)
+#define USB_DEVICE_VER(vend,prod,lo,hi) \
+	match_flags: USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION, idVendor: (vend), idProduct: (prod), bcdDevice_lo: (lo), bcdDevice_hi: (hi)
+#define USB_DEVICE_INFO(cl,sc,pr) \
+	match_flags: USB_DEVICE_ID_MATCH_DEV_INFO, bDeviceClass: (cl), bDeviceSubClass: (sc), bDeviceProtocol: (pr)
+#define USB_INTERFACE_INFO(cl,sc,pr) \
+	match_flags: USB_DEVICE_ID_MATCH_INT_INFO, bInterfaceClass: (cl), bInterfaceSubClass: (sc), bInterfaceProtocol: (pr)
+
 struct usb_device_id {
+	/* This bitmask is used to determine which of the following fields
+	 * are to be used for matching.
+	 */
+	__u16		match_flags;
+
 	/*
 	 * vendor/product codes are checked, if vendor is nonzero
 	 * Range is for device revision (bcdDevice), inclusive;
diff --git a/include/linux/zorro_ids.h b/include/linux/zorro_ids.h
index 0a09d97bc..7e7490889 100644
--- a/include/linux/zorro_ids.h
+++ b/include/linux/zorro_ids.h
@@ -435,6 +435,7 @@
 /* unofficial ID */
 #define ZORRO_MANUF_INDIVIDUAL_COMPUTERS			0x1212
 #define  ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA			ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x00, 0)
+#define  ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF			ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x17, 0)
 #define  ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL		ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x2A, 0)
 
 #define ZORRO_MANUF_KUPKE_3					0x1248
diff --git a/include/net/irda/irda.h b/include/net/irda/irda.h
index 8bdfee75a..41ad4aa0f 100644
--- a/include/net/irda/irda.h
+++ b/include/net/irda/irda.h
@@ -66,9 +66,9 @@ extern __u32 irda_debug;
 #define IRDA_DEBUG(n, args...) (irda_debug >= (n)) ? (printk(KERN_DEBUG args)) : 0
 #define ASSERT(expr, func) \
 if(!(expr)) { \
-        printk( "Assertion failed! %s,%s,%s,line=%d\n",\
-        #expr,__FILE__,__FUNCTION__,__LINE__); \
-        ##func}
+        printk( "Assertion failed! %s:%s:%d %s\n", \
+        __FILE__,__FUNCTION__,__LINE__,(#expr));  \
+        func }
 #else
 #define IRDA_DEBUG(n, args...)
 #define ASSERT(expr, func)
diff --git a/include/net/sock.h b/include/net/sock.h
index 6272cf459..14c480ea5 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -458,7 +458,7 @@ struct tcp_opt {
 /* Define this to get the sk->debug debugging facility. */
 #define SOCK_DEBUGGING
 #ifdef SOCK_DEBUGGING
-#define SOCK_DEBUG(sk, msg...) do { if((sk) && ((sk)->debug)) printk(KERN_DEBUG ## msg); } while (0)
+#define SOCK_DEBUG(sk, msg...) do { if((sk) && ((sk)->debug)) printk(KERN_DEBUG msg); } while (0)
 #else
 #define SOCK_DEBUG(sk, msg...) do { } while (0)
 #endif