diff options
| -rw-r--r-- | arch/mips/kernel/head.S | 168 | ||||
| -rw-r--r-- | arch/mips/kernel/setup.c | 96 |
2 files changed, 97 insertions, 167 deletions
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index a29592763..330459b5d 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -1,4 +1,4 @@ -/* $Id: head.S,v 1.17 1999/12/04 03:58:59 ralf Exp $ +/* $Id: head.S,v 1.18 2000/03/03 22:17:07 kevink Exp $ * * arch/mips/kernel/head.S * @@ -29,7 +29,6 @@ #include <asm/mipsregs.h> #include <asm/stackframe.h> #include <asm/bootinfo.h> -#include <asm/cpu.h> .text /* @@ -394,12 +393,6 @@ NESTED(kernel_entry, 16, sp) EXPORT(stext) EXPORT(_stext) - /* Determine which MIPS variant we are running on. */ - b cpu_probe - nop - -probe_done: - /* * Stack for kernel and init, current variable */ @@ -421,167 +414,10 @@ probe_done: bne t0, t1, 1b sw zero, (t0) - jal prom_init /* prom_init(argc, argv, envp); */ - nop -#ifdef CONFIG_SGI_IP22 - jal sgi_sysinit - nop -#endif - -#ifdef CONFIG_COBALT_MICRO_SERVER - jal SetUpBootInfo - nop -#endif - - /* - * Determine the mmu/cache attached to this machine, - * then flush the tlb and caches. On the r4xx0 - * variants this also sets CP0_WIRED to zero. - */ - jal loadmmu - nop - - /* Disable coprocessors */ - mfc0 t0, CP0_STATUS - li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX) - and t0, t1 - or t0, ST0_CU0 - mtc0 t0, CP0_STATUS - -1: jal start_kernel + jal init_arch nop - /* - * Main should never return here, but - * just in case, we know what happens. - */ - b 1b - nop # delay slot END(kernel_entry) - /* CPU type probing code, called at Kernel entry. */ - LEAF(cpu_probe) - mfc0 t0, CP0_PRID - la t3, mips_cputype - andi t1, t0, 0xff00 - li t2, PRID_IMP_R2000 - bne t1, t2, 1f - andi t0, 0x00ff - - li t2, CPU_R2000 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R3000 - bne t1, t2, 1f - nop - - li t2, PRID_REV_R3000A - bne t0, t2, 9f - nop - - li t2, CPU_R3000A - b probe_done - sw t2, (t3) -9: - li t2, CPU_R3000 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R6000 - bne t1, t2, 1f - nop - - li t2, CPU_R6000 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R4000 - bne t1, t2, 1f - nop - - li t2, PRID_REV_R4400 - bne t0, t2, 9f - nop - - li t2, CPU_R4400SC - b probe_done - sw t2, (t3) -9: - li t2, CPU_R4000SC - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R6000A - bne t1, t2, 1f - nop - - li t2, CPU_R6000A - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R10000 - bne t1, t2, 1f - nop - - li t2, CPU_R10000 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R8000 - bne t1, t2, 1f - nop - - li t2, CPU_R8000 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R4600 - bne t1, t2, 1f - nop - - li t2, CPU_R4600 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R4700 - bne t1, t2, 1f - nop - - li t2, CPU_R4700 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R4650 - bne t1, t2, 1f - nop - - li t2, CPU_R4650 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_R5000 - bne t1, t2, 1f - nop - - li t2, CPU_R5000 - b probe_done - sw t2, (t3) -1: - li t2, PRID_IMP_NEVADA - bne t1, t2, 1f - nop - - li t2, CPU_NEVADA - b probe_done - sw t2, (t3) -1: - li t2, CPU_UNKNOWN - sw t2, (t3) - - b probe_done - nop - END(cpu_probe) - /* * This buffer is reserved for the use of the cache error handler. */ diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index dad81e5e8..f0f78717e 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -1,4 +1,4 @@ -/* $Id: setup.c,v 1.23 2000/03/02 02:36:50 ralf Exp $ +/* $Id: setup.c,v 1.24 2000/03/06 11:14:23 raiko Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -39,6 +39,7 @@ #include <asm/io.h> #include <asm/stackframe.h> #include <asm/system.h> +#include <asm/cpu.h> #ifdef CONFIG_SGI_IP22 #include <asm/sgialib.h> #endif @@ -119,6 +120,99 @@ unsigned long mips_io_port_base; */ unsigned long isa_slot_offset; +extern int prom_init(int argc, char **argv, char **envp); +extern void sgi_sysinit(void); +extern void SetUpBootInfo(void); +extern void loadmmu(void); +extern asmlinkage void start_kernel(void); + +static inline void cpu_probe(void) +{ + unsigned int prid = read_32bit_cp0_register(CP0_PRID); + switch(prid & 0xff00) { + case PRID_IMP_R2000: + mips_cputype = CPU_R2000; + break; + case PRID_IMP_R3000: + if((prid & 0xff) == PRID_REV_R3000A) + mips_cputype = CPU_R3000A; + else + mips_cputype = CPU_R3000; + break; + case PRID_IMP_R4000: + if((prid & 0xff) == PRID_REV_R4400) + mips_cputype = CPU_R4400SC; + else + mips_cputype = CPU_R4000SC; + break; + case PRID_IMP_R4600: + mips_cputype = CPU_R4600; + break; + case PRID_IMP_R4650: + mips_cputype = CPU_R4650; + break; + case PRID_IMP_R4700: + mips_cputype = CPU_R4700; + break; + case PRID_IMP_R5000: + mips_cputype = CPU_R5000; + break; + case PRID_IMP_NEVADA: + mips_cputype = CPU_NEVADA; + break; + case PRID_IMP_R6000: + mips_cputype = CPU_R6000; + break; + case PRID_IMP_R6000A: + mips_cputype = CPU_R6000A; + break; + case PRID_IMP_R8000: + mips_cputype = CPU_R8000; + break; + case PRID_IMP_R10000: + mips_cputype = CPU_R10000; + break; + default: + mips_cputype = CPU_UNKNOWN; + } +} + +asmlinkage void __init init_arch(int argc, char **argv, char **envp) +{ + unsigned int s; + + /* Determine which MIPS variant we are running on. */ + cpu_probe(); + + prom_init(argc, argv, envp); +#ifdef CONFIG_SGI_IP22 + sgi_sysinit(); +#endif +#ifdef CONFIG_COBALT_MICRO_SERVER + SetUpBootInfo(); +#endif + + /* + * Determine the mmu/cache attached to this machine, + * then flush the tlb and caches. On the r4xx0 + * variants this also sets CP0_WIRED to zero. + */ + loadmmu(); + + /* Disable coprocessors */ + s = read_32bit_cp0_register(CP0_STATUS); + s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX); + s |= ST0_CU0; + write_32bit_cp0_register(CP0_STATUS, s); + + /* + * Main should never return here, but + * just in case, we know what happens. + */ + for(;;) + start_kernel(); +} + static void __init default_irq_setup(void) { panic("Unknown machtype in init_IRQ"); |