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-rw-r--r--include/asm-alpha/bitops.h71
-rw-r--r--include/asm-alpha/byteorder.h6
-rw-r--r--include/asm-alpha/compiler.h74
-rw-r--r--include/asm-alpha/core_apecs.h (renamed from include/asm-alpha/apecs.h)512
-rw-r--r--include/asm-alpha/core_cia.h (renamed from include/asm-alpha/cia.h)532
5 files changed, 691 insertions, 504 deletions
diff --git a/include/asm-alpha/bitops.h b/include/asm-alpha/bitops.h
index 70c857af7..140f5783a 100644
--- a/include/asm-alpha/bitops.h
+++ b/include/asm-alpha/bitops.h
@@ -46,10 +46,10 @@ extern __inline__ void clear_bit(unsigned long nr, volatile void * addr)
__asm__ __volatile__(
"1: ldl_l %0,%1\n"
- " and %0,%3,%2\n\t"
- " beq %2,2f\n\t"
- " xor %0,%3,%0\n\t"
- " stl_c %0,%1\n\t"
+ " and %0,%3,%2\n"
+ " beq %2,2f\n"
+ " xor %0,%3,%0\n"
+ " stl_c %0,%1\n"
" beq %0,3f\n"
"2:\n"
".section .text2,\"ax\"\n"
@@ -66,8 +66,8 @@ extern __inline__ void change_bit(unsigned long nr, volatile void * addr)
__asm__ __volatile__(
"1: ldl_l %0,%1\n"
- " xor %0,%2,%0\n\t"
- " stl_c %0,%1\n\t"
+ " xor %0,%2,%0\n"
+ " stl_c %0,%1\n"
" beq %0,3f\n"
".section .text2,\"ax\"\n"
"3: br 1b\n"
@@ -109,10 +109,10 @@ extern __inline__ unsigned long test_and_clear_bit(unsigned long nr,
__asm__ __volatile__(
"1: ldl_l %0,%1\n"
- " and %0,%3,%2\n\t"
- " beq %2,2f\n\t"
- " xor %0,%3,%0\n\t"
- " stl_c %0,%1\n\t"
+ " and %0,%3,%2\n"
+ " beq %2,2f\n"
+ " xor %0,%3,%0\n"
+ " stl_c %0,%1\n"
" beq %0,3f\n"
"2:\n"
".section .text2,\"ax\"\n"
@@ -133,9 +133,9 @@ extern __inline__ unsigned long test_and_change_bit(unsigned long nr,
__asm__ __volatile__(
"1: ldl_l %0,%1\n"
- " and %0,%3,%2\n\t"
- " xor %0,%3,%0\n\t"
- " stl_c %0,%1\n\t"
+ " and %0,%3,%2\n"
+ " xor %0,%3,%0\n"
+ " stl_c %0,%1\n"
" beq %0,3f\n"
".section .text2,\"ax\"\n"
"3: br 1b\n"
@@ -172,6 +172,11 @@ extern inline unsigned long ffz_b(unsigned long x)
extern inline unsigned long ffz(unsigned long word)
{
+#ifdef __alpha_cix__
+ /* Whee. EV6 can calculate it directly. */
+ unsigned long result;
+ __asm__("ctlz %1,%0" : "=r"(result) : "r"(~word));
+#else
unsigned long bits, qofs, bofs;
__asm__("cmpbge %1,%2,%0" : "=r"(bits) : "r"(word), "r"(~0UL));
@@ -180,8 +185,48 @@ extern inline unsigned long ffz(unsigned long word)
bofs = ffz_b(bits);
return qofs*8 + bofs;
+#endif
}
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+extern inline int ffs(int word)
+{
+ int result = ffz(~word);
+ return word ? result+1 : 0;
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#ifdef __alpha_cix__
+/* Whee. EV6 can calculate it directly. */
+extern __inline__ unsigned long hweight64(unsigned long w)
+{
+ unsigned long result;
+ __asm__("ctpop %1,%0" : "=r"(result) : "r"(w));
+ return result;
+}
+
+#define hweight32(x) hweight64((x) & 0xfffffffful)
+#define hweight16(x) hweight64((x) & 0xfffful)
+#define hweight8(x) hweight64((x) & 0xfful)
+#else
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+#endif
+
+#endif /* __KERNEL__ */
+
/*
* Find next zero bit in a bitmap reasonably efficiently..
*/
diff --git a/include/asm-alpha/byteorder.h b/include/asm-alpha/byteorder.h
index b8afddcd5..e574bb6e7 100644
--- a/include/asm-alpha/byteorder.h
+++ b/include/asm-alpha/byteorder.h
@@ -3,7 +3,11 @@
#include <asm/types.h>
-#ifdef __GNUC__
+/* EGCS 1.1 can, without scheduling, do just as good as we do here
+ with the standard macros. And since it can schedule, it does even
+ better in the end. */
+
+#if defined(__GNUC__) && __GNUC_MINOR__ < 91
static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
{
diff --git a/include/asm-alpha/compiler.h b/include/asm-alpha/compiler.h
new file mode 100644
index 000000000..5656ce953
--- /dev/null
+++ b/include/asm-alpha/compiler.h
@@ -0,0 +1,74 @@
+#ifndef __ALPHA_COMPILER_H
+#define __ALPHA_COMPILER_H
+
+/*
+ * Herein are macros we use when describing various patterns we want to GCC.
+ * In all cases we can get better schedules out of the compiler if we hide
+ * as little as possible inside inline assembly. However, we want to be
+ * able to know what we'll get out before giving up inline assembly. Thus
+ * these tests and macros.
+ */
+
+/*
+ * EGCS (of varying versions) does a good job of using insxl and extxl.
+ */
+
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+#define __kernel_insbl(val, shift) \
+ (((unsigned long)(val) & 0xfful) << ((shift) * 8))
+#define __kernel_inswl(val, shift) \
+ (((unsigned long)(val) & 0xfffful) << ((shift) * 8))
+#else
+#define __kernel_insbl(val, shift) \
+ ({ unsigned long __kir; \
+ __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
+ __kir; })
+#define __kernel_inswl(val, shift) \
+ ({ unsigned long __kir; \
+ __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
+ __kir; })
+#endif
+
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 92
+#define __kernel_extbl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfful)
+#define __kernel_extwl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfffful)
+#else
+#define __kernel_extbl(val, shift) \
+ ({ unsigned long __kir; \
+ __asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
+ __kir; })
+#define __kernel_extwl(val, shift) \
+ ({ unsigned long __kir; \
+ __asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
+ __kir; })
+#endif
+
+
+/*
+ * Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX
+ * extension is enabled. Previous versions did not define anything
+ * we could test during compilation, so allow users to tell us when
+ * the compiler will DTRT.
+ */
+
+#if defined(HAVE_BWX) || defined(__alpha_bwx__)
+#define __kernel_ldbu(mem) (mem)
+#define __kernel_ldwu(mem) (mem)
+#define __kernel_stb(val,mem) ((mem) = (val))
+#define __kernel_stw(val,mem) ((mem) = (val))
+#else
+#define __kernel_ldbu(mem) \
+ ({ unsigned char __kir; \
+ __asm__("ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \
+ __kir; })
+#define __kernel_ldwu(mem) \
+ ({ unsigned short __kir; \
+ __asm__("ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \
+ __kir; })
+#define __kernel_stb(val,mem) \
+ __asm__("stb %1,%0" : "=m"(mem) : "r"(val))
+#define __kernel_stw(val,mem) \
+ __asm__("stw %1,%0" : "=m"(mem) : "r"(val))
+#endif
+
+#endif /* __ALPHA_COMPILER_H */
diff --git a/include/asm-alpha/apecs.h b/include/asm-alpha/core_apecs.h
index 36ac35922..a8f0bd6ef 100644
--- a/include/asm-alpha/apecs.h
+++ b/include/asm-alpha/core_apecs.h
@@ -1,7 +1,9 @@
#ifndef __ALPHA_APECS__H__
#define __ALPHA_APECS__H__
+#include <linux/config.h>
#include <linux/types.h>
+#include <asm/compiler.h>
/*
* APECS is the internal name for the 2107x chipset which provides
@@ -18,9 +20,7 @@
* david.rusling@reo.mts.dec.com Initial Version.
*
*/
-#include <linux/config.h>
-#ifdef CONFIG_ALPHA_XL
/*
An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
that get passed through the PCI<->ISA bridge chip. So we've gotta use
@@ -42,7 +42,7 @@
we can't just use that here, because of header file looping... :-(
Window 1 will be used for all DMA from the ISA bus; yes, that does
- limit what memory an ISA floppy or soundcard or Ethernet can touch, but
+ limit what memory an ISA floppy or sound card or Ethernet can touch, but
it's also a known limitation on other platforms as well. We use the
same technique that is used on INTEL platforms with similar limitation:
set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
@@ -66,7 +66,6 @@
for most other things they are identical. It didn't seem reasonable to
make the AVANTI support pay for the limitations of the XL. It is true,
however, that an XL kernel will run on an AVANTI without problems.
-
*/
#define APECS_XL_DMA_WIN1_BASE (64*1024*1024)
#define APECS_XL_DMA_WIN1_SIZE (64*1024*1024)
@@ -74,23 +73,20 @@
#define APECS_XL_DMA_WIN2_BASE (1024*1024*1024)
#define APECS_XL_DMA_WIN2_SIZE (1024*1024*1024)
-#else /* CONFIG_ALPHA_XL */
-/* these are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64 */
-#ifdef CONFIG_ALPHA_SRM_SETUP
-/* if we are using the SRM PCI setup, we'll need to use variables instead */
+/* These are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64. */
+
#define APECS_DMA_WIN_BASE_DEFAULT (1024*1024*1024)
#define APECS_DMA_WIN_SIZE_DEFAULT (1024*1024*1024)
-extern unsigned int APECS_DMA_WIN_BASE;
-extern unsigned int APECS_DMA_WIN_SIZE;
+#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
+#define APECS_DMA_WIN_BASE alpha_mv.dma_win_base
+#define APECS_DMA_WIN_SIZE alpha_mv.dma_win_size
+#else
+#define APECS_DMA_WIN_BASE APECS_DMA_WIN_BASE_DEFAULT
+#define APECS_DMA_WIN_SIZE APECS_DMA_WIN_SIZE_DEFAULT
+#endif
-#else /* SRM_SETUP */
-#define APECS_DMA_WIN_BASE (1024*1024*1024)
-#define APECS_DMA_WIN_SIZE (1024*1024*1024)
-#endif /* SRM_SETUP */
-
-#endif /* CONFIG_ALPHA_XL */
/*
* 21071-DA Control and Status registers.
@@ -212,6 +208,7 @@ extern unsigned int APECS_DMA_WIN_SIZE;
#define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
#define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
+
/*
* Bit definitions for I/O Controller status register 0:
*/
@@ -225,34 +222,203 @@ extern unsigned int APECS_DMA_WIN_SIZE;
#define APECS_IOC_STAT0_P_NBR_SHIFT 13
#define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff
-#define HAE_ADDRESS APECS_IOC_HAXR1
+#define APECS_HAE_ADDRESS APECS_IOC_HAXR1
+
+
+/*
+ * Data structure for handling APECS machine checks:
+ */
+
+struct el_apecs_mikasa_sysdata_mcheck
+{
+ unsigned long coma_gcr;
+ unsigned long coma_edsr;
+ unsigned long coma_ter;
+ unsigned long coma_elar;
+ unsigned long coma_ehar;
+ unsigned long coma_ldlr;
+ unsigned long coma_ldhr;
+ unsigned long coma_base0;
+ unsigned long coma_base1;
+ unsigned long coma_base2;
+ unsigned long coma_base3;
+ unsigned long coma_cnfg0;
+ unsigned long coma_cnfg1;
+ unsigned long coma_cnfg2;
+ unsigned long coma_cnfg3;
+ unsigned long epic_dcsr;
+ unsigned long epic_pear;
+ unsigned long epic_sear;
+ unsigned long epic_tbr1;
+ unsigned long epic_tbr2;
+ unsigned long epic_pbr1;
+ unsigned long epic_pbr2;
+ unsigned long epic_pmr1;
+ unsigned long epic_pmr2;
+ unsigned long epic_harx1;
+ unsigned long epic_harx2;
+ unsigned long epic_pmlt;
+ unsigned long epic_tag0;
+ unsigned long epic_tag1;
+ unsigned long epic_tag2;
+ unsigned long epic_tag3;
+ unsigned long epic_tag4;
+ unsigned long epic_tag5;
+ unsigned long epic_tag6;
+ unsigned long epic_tag7;
+ unsigned long epic_data0;
+ unsigned long epic_data1;
+ unsigned long epic_data2;
+ unsigned long epic_data3;
+ unsigned long epic_data4;
+ unsigned long epic_data5;
+ unsigned long epic_data6;
+ unsigned long epic_data7;
+
+ unsigned long pceb_vid;
+ unsigned long pceb_did;
+ unsigned long pceb_revision;
+ unsigned long pceb_command;
+ unsigned long pceb_status;
+ unsigned long pceb_latency;
+ unsigned long pceb_control;
+ unsigned long pceb_arbcon;
+ unsigned long pceb_arbpri;
+
+ unsigned long esc_id;
+ unsigned long esc_revision;
+ unsigned long esc_int0;
+ unsigned long esc_int1;
+ unsigned long esc_elcr0;
+ unsigned long esc_elcr1;
+ unsigned long esc_last_eisa;
+ unsigned long esc_nmi_stat;
+
+ unsigned long pci_ir;
+ unsigned long pci_imr;
+ unsigned long svr_mgr;
+};
+
+/* This for the normal APECS machines. */
+struct el_apecs_sysdata_mcheck
+{
+ unsigned long coma_gcr;
+ unsigned long coma_edsr;
+ unsigned long coma_ter;
+ unsigned long coma_elar;
+ unsigned long coma_ehar;
+ unsigned long coma_ldlr;
+ unsigned long coma_ldhr;
+ unsigned long coma_base0;
+ unsigned long coma_base1;
+ unsigned long coma_base2;
+ unsigned long coma_cnfg0;
+ unsigned long coma_cnfg1;
+ unsigned long coma_cnfg2;
+ unsigned long epic_dcsr;
+ unsigned long epic_pear;
+ unsigned long epic_sear;
+ unsigned long epic_tbr1;
+ unsigned long epic_tbr2;
+ unsigned long epic_pbr1;
+ unsigned long epic_pbr2;
+ unsigned long epic_pmr1;
+ unsigned long epic_pmr2;
+ unsigned long epic_harx1;
+ unsigned long epic_harx2;
+ unsigned long epic_pmlt;
+ unsigned long epic_tag0;
+ unsigned long epic_tag1;
+ unsigned long epic_tag2;
+ unsigned long epic_tag3;
+ unsigned long epic_tag4;
+ unsigned long epic_tag5;
+ unsigned long epic_tag6;
+ unsigned long epic_tag7;
+ unsigned long epic_data0;
+ unsigned long epic_data1;
+ unsigned long epic_data2;
+ unsigned long epic_data3;
+ unsigned long epic_data4;
+ unsigned long epic_data5;
+ unsigned long epic_data6;
+ unsigned long epic_data7;
+};
+
+struct el_apecs_procdata
+{
+ unsigned long paltemp[32]; /* PAL TEMP REGS. */
+ /* EV4-specific fields */
+ unsigned long exc_addr; /* Address of excepting instruction. */
+ unsigned long exc_sum; /* Summary of arithmetic traps. */
+ unsigned long exc_mask; /* Exception mask (from exc_sum). */
+ unsigned long iccsr; /* IBox hardware enables. */
+ unsigned long pal_base; /* Base address for PALcode. */
+ unsigned long hier; /* Hardware Interrupt Enable. */
+ unsigned long hirr; /* Hardware Interrupt Request. */
+ unsigned long csr; /* D-stream fault info. */
+ unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */
+ unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */
+ unsigned long abox_ctl; /* ABox Control Register. */
+ unsigned long biu_stat; /* BIU Status. */
+ unsigned long biu_addr; /* BUI Address. */
+ unsigned long biu_ctl; /* BIU Control. */
+ unsigned long fill_syndrome;/* For correcting ECC errors. */
+ unsigned long fill_addr; /* Cache block which was being read */
+ unsigned long va; /* Effective VA of fault or miss. */
+ unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/
+};
+
#ifdef __KERNEL__
+#ifndef __EXTERN_INLINE
+#define __EXTERN_INLINE extern inline
+#define __IO_EXTERN_INLINE
+#endif
+
/*
* Translate physical memory address as seen on (PCI) bus into
* a kernel virtual address and vv.
*/
-/* NOTE: we fudge the window 1 maximum as 48Mb instead of 64Mb, to prevent
- virt_to_bus() from returning an address in the first window, for a
- data area that goes beyond the 64Mb first DMA window. Sigh...
- This MUST match with <asm/dma.h> MAX_DMA_ADDRESS for consistency, but
- we can't just use that here, because of header file looping... :-(
-*/
-extern inline unsigned long virt_to_bus(void * address)
+
+/*
+ * NOTE: we fudge the window 1 maximum as 48Mb instead of 64Mb, to prevent
+ * virt_to_bus() from returning an address in the first window, for a
+ * data area that goes beyond the 64Mb first DMA window. Sigh...
+ * This MUST match with <asm/dma.h> MAX_DMA_ADDRESS for consistency, but
+ * we can't just use that here, because of header file looping... :-(
+ */
+
+__EXTERN_INLINE unsigned long apecs_virt_to_bus(void * address)
+{
+ unsigned long paddr = virt_to_phys(address);
+ return paddr + APECS_DMA_WIN_BASE;
+}
+
+static inline unsigned long apecs_xl_virt_to_bus(void * address)
{
unsigned long paddr = virt_to_phys(address);
-#ifdef CONFIG_ALPHA_XL
if (paddr < APECS_XL_DMA_WIN1_SIZE_PARANOID)
return paddr + APECS_XL_DMA_WIN1_BASE;
else
return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */
-#else /* CONFIG_ALPHA_XL */
- return paddr + APECS_DMA_WIN_BASE;
-#endif /* CONFIG_ALPHA_XL */
}
-extern inline void * bus_to_virt(unsigned long address)
+__EXTERN_INLINE void * apecs_bus_to_virt(unsigned long address)
+{
+ /*
+ * This check is a sanity check but also ensures that bus
+ * address 0 maps to virtual address 0 which is useful to
+ * detect null "pointers" (the NCR driver is much simpler if
+ * NULL pointers are preserved).
+ */
+ if (address < APECS_DMA_WIN_BASE)
+ return 0;
+ return phys_to_virt(address - APECS_DMA_WIN_BASE);
+}
+
+static inline void * apecs_xl_bus_to_virt(unsigned long address)
{
/*
* This check is a sanity check but also ensures that bus
@@ -260,18 +426,13 @@ extern inline void * bus_to_virt(unsigned long address)
* detect null "pointers" (the NCR driver is much simpler if
* NULL pointers are preserved).
*/
-#ifdef CONFIG_ALPHA_XL
if (address < APECS_XL_DMA_WIN1_BASE)
return 0;
else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE))
- return phys_to_virt(address - APECS_XL_DMA_WIN1_BASE);
+ address -= APECS_XL_DMA_WIN1_BASE;
else /* should be more checking here, maybe? */
- return phys_to_virt(address - APECS_XL_DMA_WIN2_BASE);
-#else /* CONFIG_ALPHA_XL */
- if (address < APECS_DMA_WIN_BASE)
- return 0;
- return phys_to_virt(address - APECS_DMA_WIN_BASE);
-#endif /* CONFIG_ALPHA_XL */
+ address -= APECS_XL_DMA_WIN2_BASE;
+ return phys_to_virt(address);
}
/*
@@ -285,46 +446,46 @@ extern inline void * bus_to_virt(unsigned long address)
* data to/from the right byte-lanes.
*/
+#define vip volatile int *
#define vuip volatile unsigned int *
+#define vulp volatile unsigned long *
-extern inline unsigned int __inb(unsigned long addr)
+__EXTERN_INLINE unsigned int apecs_inb(unsigned long addr)
{
- long result = *(vuip) ((addr << 5) + APECS_IO + 0x00);
- result >>= (addr & 3) * 8;
- return 0xffUL & result;
+ long result = *(vip) ((addr << 5) + APECS_IO + 0x00);
+ return __kernel_extbl(result, addr & 3);
}
-extern inline void __outb(unsigned char b, unsigned long addr)
+__EXTERN_INLINE void apecs_outb(unsigned char b, unsigned long addr)
{
unsigned int w;
- asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
+ w = __kernel_insbl(b, addr & 3);
*(vuip) ((addr << 5) + APECS_IO + 0x00) = w;
mb();
}
-extern inline unsigned int __inw(unsigned long addr)
+__EXTERN_INLINE unsigned int apecs_inw(unsigned long addr)
{
- long result = *(vuip) ((addr << 5) + APECS_IO + 0x08);
- result >>= (addr & 3) * 8;
- return 0xffffUL & result;
+ long result = *(vip) ((addr << 5) + APECS_IO + 0x08);
+ return __kernel_extwl(result, addr & 3);
}
-extern inline void __outw(unsigned short b, unsigned long addr)
+__EXTERN_INLINE void apecs_outw(unsigned short b, unsigned long addr)
{
unsigned int w;
- asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
+ w = __kernel_inswl(b, addr & 3);
*(vuip) ((addr << 5) + APECS_IO + 0x08) = w;
mb();
}
-extern inline unsigned int __inl(unsigned long addr)
+__EXTERN_INLINE unsigned int apecs_inl(unsigned long addr)
{
return *(vuip) ((addr << 5) + APECS_IO + 0x18);
}
-extern inline void __outl(unsigned int b, unsigned long addr)
+__EXTERN_INLINE void apecs_outl(unsigned int b, unsigned long addr)
{
*(vuip) ((addr << 5) + APECS_IO + 0x18) = b;
mb();
@@ -335,78 +496,114 @@ extern inline void __outl(unsigned int b, unsigned long addr)
* Memory functions. 64-bit and 32-bit accesses are done through
* dense memory space, everything else through sparse space.
*/
-extern inline unsigned long __readb(unsigned long addr)
+
+__EXTERN_INLINE unsigned long apecs_readb(unsigned long addr)
{
- unsigned long result, shift, msb;
+ unsigned long result, msb;
- shift = (addr & 0x3) * 8;
if (addr >= (1UL << 24)) {
msb = addr & 0xf8000000;
addr -= msb;
- if (msb != hae.cache) {
- set_hae(msb);
- }
+ set_hae(msb);
}
- result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00);
- result >>= shift;
- return 0xffUL & result;
+ result = *(vip) ((addr << 5) + APECS_SPARSE_MEM + 0x00);
+ return __kernel_extbl(result, addr & 3);
}
-extern inline unsigned long __readw(unsigned long addr)
+__EXTERN_INLINE unsigned long apecs_readw(unsigned long addr)
{
- unsigned long result, shift, msb;
+ unsigned long result, msb;
- shift = (addr & 0x3) * 8;
if (addr >= (1UL << 24)) {
msb = addr & 0xf8000000;
addr -= msb;
- if (msb != hae.cache) {
- set_hae(msb);
- }
+ set_hae(msb);
}
- result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08);
- result >>= shift;
- return 0xffffUL & result;
+ result = *(vip) ((addr << 5) + APECS_SPARSE_MEM + 0x08);
+ return __kernel_extwl(result, addr & 3);
}
-extern inline unsigned long __readl(unsigned long addr)
+__EXTERN_INLINE unsigned long apecs_readl(unsigned long addr)
{
return *(vuip) (addr + APECS_DENSE_MEM);
}
-extern inline void __writeb(unsigned char b, unsigned long addr)
+__EXTERN_INLINE unsigned long apecs_readq(unsigned long addr)
+{
+ return *(vulp) (addr + APECS_DENSE_MEM);
+}
+
+__EXTERN_INLINE void apecs_writeb(unsigned char b, unsigned long addr)
{
unsigned long msb;
if (addr >= (1UL << 24)) {
msb = addr & 0xf8000000;
addr -= msb;
- if (msb != hae.cache) {
- set_hae(msb);
- }
+ set_hae(msb);
}
*(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101;
}
-extern inline void __writew(unsigned short b, unsigned long addr)
+__EXTERN_INLINE void apecs_writew(unsigned short b, unsigned long addr)
{
unsigned long msb;
if (addr >= (1UL << 24)) {
msb = addr & 0xf8000000;
addr -= msb;
- if (msb != hae.cache) {
- set_hae(msb);
- }
+ set_hae(msb);
}
*(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001;
}
-extern inline void __writel(unsigned int b, unsigned long addr)
+__EXTERN_INLINE void apecs_writel(unsigned int b, unsigned long addr)
{
*(vuip) (addr + APECS_DENSE_MEM) = b;
}
+__EXTERN_INLINE void apecs_writeq(unsigned long b, unsigned long addr)
+{
+ *(vulp) (addr + APECS_DENSE_MEM) = b;
+}
+
+/* Find the DENSE memory area for a given bus address. */
+
+__EXTERN_INLINE unsigned long apecs_dense_mem(unsigned long addr)
+{
+ return APECS_DENSE_MEM;
+}
+
+#undef vip
+#undef vuip
+#undef vulp
+
+#ifdef __WANT_IO_DEF
+
+#ifdef CONFIG_ALPHA_XL
+#define virt_to_bus apecs_xl_virt_to_bus
+#define bus_to_virt apecs_xl_bus_to_virt
+#else
+#define virt_to_bus apecs_virt_to_bus
+#define bus_to_virt apecs_bus_to_virt
+#endif
+
+#define __inb apecs_inb
+#define __inw apecs_inw
+#define __inl apecs_inl
+#define __outb apecs_outb
+#define __outw apecs_outw
+#define __outl apecs_outl
+#define __readb apecs_readb
+#define __readw apecs_readw
+#define __readl apecs_readl
+#define __readq apecs_readq
+#define __writeb apecs_writeb
+#define __writew apecs_writew
+#define __writel apecs_writel
+#define __writeq apecs_writeq
+#define dense_mem apecs_dense_mem
+
#define inb(port) \
(__builtin_constant_p((port))?__inb(port):_inb(port))
@@ -414,160 +611,17 @@ extern inline void __writel(unsigned int b, unsigned long addr)
(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
#define readl(a) __readl((unsigned long)(a))
+#define readq(a) __readq((unsigned long)(a))
#define writel(v,a) __writel((v),(unsigned long)(a))
+#define writeq(v,a) __writeq((v),(unsigned long)(a))
-#undef vuip
+#endif /* __WANT_IO_DEF */
-extern unsigned long apecs_init (unsigned long mem_start,
- unsigned long mem_end);
+#ifdef __IO_EXTERN_INLINE
+#undef __EXTERN_INLINE
+#undef __IO_EXTERN_INLINE
+#endif
#endif /* __KERNEL__ */
-/*
- * Data structure for handling APECS machine checks:
- */
-#ifdef CONFIG_ALPHA_MIKASA
-struct el_apecs_sysdata_mcheck {
- unsigned long coma_gcr;
- unsigned long coma_edsr;
- unsigned long coma_ter;
- unsigned long coma_elar;
- unsigned long coma_ehar;
- unsigned long coma_ldlr;
- unsigned long coma_ldhr;
- unsigned long coma_base0;
- unsigned long coma_base1;
- unsigned long coma_base2;
- unsigned long coma_base3;
- unsigned long coma_cnfg0;
- unsigned long coma_cnfg1;
- unsigned long coma_cnfg2;
- unsigned long coma_cnfg3;
- unsigned long epic_dcsr;
- unsigned long epic_pear;
- unsigned long epic_sear;
- unsigned long epic_tbr1;
- unsigned long epic_tbr2;
- unsigned long epic_pbr1;
- unsigned long epic_pbr2;
- unsigned long epic_pmr1;
- unsigned long epic_pmr2;
- unsigned long epic_harx1;
- unsigned long epic_harx2;
- unsigned long epic_pmlt;
- unsigned long epic_tag0;
- unsigned long epic_tag1;
- unsigned long epic_tag2;
- unsigned long epic_tag3;
- unsigned long epic_tag4;
- unsigned long epic_tag5;
- unsigned long epic_tag6;
- unsigned long epic_tag7;
- unsigned long epic_data0;
- unsigned long epic_data1;
- unsigned long epic_data2;
- unsigned long epic_data3;
- unsigned long epic_data4;
- unsigned long epic_data5;
- unsigned long epic_data6;
- unsigned long epic_data7;
-
- unsigned long pceb_vid;
- unsigned long pceb_did;
- unsigned long pceb_revision;
- unsigned long pceb_command;
- unsigned long pceb_status;
- unsigned long pceb_latency;
- unsigned long pceb_control;
- unsigned long pceb_arbcon;
- unsigned long pceb_arbpri;
-
- unsigned long esc_id;
- unsigned long esc_revision;
- unsigned long esc_int0;
- unsigned long esc_int1;
- unsigned long esc_elcr0;
- unsigned long esc_elcr1;
- unsigned long esc_last_eisa;
- unsigned long esc_nmi_stat;
-
- unsigned long pci_ir;
- unsigned long pci_imr;
- unsigned long svr_mgr;
-};
-#else /* CONFIG_ALPHA_MIKASA */
-/* this for the normal APECS machines */
-struct el_apecs_sysdata_mcheck {
- unsigned long coma_gcr;
- unsigned long coma_edsr;
- unsigned long coma_ter;
- unsigned long coma_elar;
- unsigned long coma_ehar;
- unsigned long coma_ldlr;
- unsigned long coma_ldhr;
- unsigned long coma_base0;
- unsigned long coma_base1;
- unsigned long coma_base2;
- unsigned long coma_cnfg0;
- unsigned long coma_cnfg1;
- unsigned long coma_cnfg2;
- unsigned long epic_dcsr;
- unsigned long epic_pear;
- unsigned long epic_sear;
- unsigned long epic_tbr1;
- unsigned long epic_tbr2;
- unsigned long epic_pbr1;
- unsigned long epic_pbr2;
- unsigned long epic_pmr1;
- unsigned long epic_pmr2;
- unsigned long epic_harx1;
- unsigned long epic_harx2;
- unsigned long epic_pmlt;
- unsigned long epic_tag0;
- unsigned long epic_tag1;
- unsigned long epic_tag2;
- unsigned long epic_tag3;
- unsigned long epic_tag4;
- unsigned long epic_tag5;
- unsigned long epic_tag6;
- unsigned long epic_tag7;
- unsigned long epic_data0;
- unsigned long epic_data1;
- unsigned long epic_data2;
- unsigned long epic_data3;
- unsigned long epic_data4;
- unsigned long epic_data5;
- unsigned long epic_data6;
- unsigned long epic_data7;
-};
-#endif /* CONFIG_ALPHA_MIKASA */
-
-struct el_procdata {
- unsigned long paltemp[32]; /* PAL TEMP REGS. */
- /* EV4-specific fields */
- unsigned long exc_addr; /* Address of excepting instruction. */
- unsigned long exc_sum; /* Summary of arithmetic traps. */
- unsigned long exc_mask; /* Exception mask (from exc_sum). */
- unsigned long iccsr; /* IBox hardware enables. */
- unsigned long pal_base; /* Base address for PALcode. */
- unsigned long hier; /* Hardware Interrupt Enable. */
- unsigned long hirr; /* Hardware Interrupt Request. */
- unsigned long csr; /* D-stream fault info. */
- unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */
- unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */
- unsigned long abox_ctl; /* ABox Control Register. */
- unsigned long biu_stat; /* BIU Status. */
- unsigned long biu_addr; /* BUI Address. */
- unsigned long biu_ctl; /* BIU Control. */
- unsigned long fill_syndrome;/* For correcting ECC errors. */
- unsigned long fill_addr; /* Cache block which was being read */
- unsigned long va; /* Effective VA of fault or miss. */
- unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/
-};
-
-
-#define RTC_PORT(x) (0x70 + (x))
-#define RTC_ADDR(x) (0x80 | (x))
-#define RTC_ALWAYS_BCD 0
-
#endif /* __ALPHA_APECS__H__ */
diff --git a/include/asm-alpha/cia.h b/include/asm-alpha/core_cia.h
index 38269eaae..32fd81f2e 100644
--- a/include/asm-alpha/cia.h
+++ b/include/asm-alpha/core_cia.h
@@ -3,6 +3,7 @@
#include <linux/config.h>
#include <linux/types.h>
+#include <asm/compiler.h>
/*
* CIA is the internal name for the 2117x chipset which provides
@@ -21,7 +22,7 @@
/*------------------------------------------------------------------------**
** **
-** EB164 I/O procedures **
+** EB164 I/O procedures **
** **
** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
** inportbxt: 8 bits only **
@@ -72,25 +73,20 @@
*
*/
-#define BYTE_ENABLE_SHIFT 5
-#define TRANSFER_LENGTH_SHIFT 3
+#define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
+#define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
+#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
-#define MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
-#define MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
-#define MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
+#define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024)
+#define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024)
-#ifdef CONFIG_ALPHA_SRM_SETUP
-/* if we are using the SRM PCI setup, we'll need to use variables instead */
-#define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024)
-#define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024)
-
-extern unsigned int CIA_DMA_WIN_BASE;
-extern unsigned int CIA_DMA_WIN_SIZE;
-
-#else /* SRM_SETUP */
-#define CIA_DMA_WIN_BASE (1024*1024*1024)
-#define CIA_DMA_WIN_SIZE (1024*1024*1024)
-#endif /* SRM_SETUP */
+#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
+#define CIA_DMA_WIN_BASE alpha_mv.dma_win_base
+#define CIA_DMA_WIN_SIZE alpha_mv.dma_win_size
+#else
+#define CIA_DMA_WIN_BASE CIA_DMA_WIN_SIZE_DEFAULT
+#define CIA_DMA_WIN_SIZE CIA_DMA_WIN_SIZE_DEFAULT
+#endif
/*
* 21171-CA Control and Status Registers (p4-1)
@@ -193,13 +189,10 @@ extern unsigned int CIA_DMA_WIN_SIZE;
#define GRU_LED (IDENT_ADDR + 0x8780000800UL)
#define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
-#if defined(CONFIG_ALPHA_ALCOR)
-#define GRU_INT_REQ_BITS 0x800fffffUL
-#elif defined(CONFIG_ALPHA_XLT)
-#define GRU_INT_REQ_BITS 0x80003fffUL
-#else
-#define GRU_INT_REQ_BITS 0xffffffffUL
-#endif
+#define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
+#define XLT_GRU_INT_REQ_BITS 0x80003fffUL
+#define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
+
/*
* Bit definitions for I/O Controller status register 0:
@@ -214,20 +207,100 @@ extern unsigned int CIA_DMA_WIN_SIZE;
#define CIA_IOC_STAT0_P_NBR_SHIFT 13
#define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff
-#define HAE_ADDRESS CIA_IOC_HAE_MEM
+#define CIA_HAE_ADDRESS CIA_IOC_HAE_MEM
+
+/*
+ * Data structure for handling CIA machine checks.
+ */
+
+/* EV5-specific info. */
+struct el_CIA_procdata {
+ unsigned long shadow[8]; /* PALmode shadow registers */
+ unsigned long paltemp[24]; /* PAL temporary registers */
+ /* EV5-specific fields */
+ unsigned long exc_addr; /* Address of excepting instruction. */
+ unsigned long exc_sum; /* Summary of arithmetic traps. */
+ unsigned long exc_mask; /* Exception mask (from exc_sum). */
+ unsigned long exc_base; /* PALbase at time of exception. */
+ unsigned long isr; /* Interrupt summary register. */
+ unsigned long icsr; /* Ibox control register. */
+ unsigned long ic_perr_stat;
+ unsigned long dc_perr_stat;
+ unsigned long va; /* Effective VA of fault or miss. */
+ unsigned long mm_stat;
+ unsigned long sc_addr;
+ unsigned long sc_stat;
+ unsigned long bc_tag_addr;
+ unsigned long ei_addr;
+ unsigned long fill_syn;
+ unsigned long ei_stat;
+ unsigned long ld_lock;
+};
+
+/* System-specific info. */
+struct el_CIA_sysdata_mcheck {
+ unsigned long coma_gcr;
+ unsigned long coma_edsr;
+ unsigned long coma_ter;
+ unsigned long coma_elar;
+ unsigned long coma_ehar;
+ unsigned long coma_ldlr;
+ unsigned long coma_ldhr;
+ unsigned long coma_base0;
+ unsigned long coma_base1;
+ unsigned long coma_base2;
+ unsigned long coma_cnfg0;
+ unsigned long coma_cnfg1;
+ unsigned long coma_cnfg2;
+ unsigned long epic_dcsr;
+ unsigned long epic_pear;
+ unsigned long epic_sear;
+ unsigned long epic_tbr1;
+ unsigned long epic_tbr2;
+ unsigned long epic_pbr1;
+ unsigned long epic_pbr2;
+ unsigned long epic_pmr1;
+ unsigned long epic_pmr2;
+ unsigned long epic_harx1;
+ unsigned long epic_harx2;
+ unsigned long epic_pmlt;
+ unsigned long epic_tag0;
+ unsigned long epic_tag1;
+ unsigned long epic_tag2;
+ unsigned long epic_tag3;
+ unsigned long epic_tag4;
+ unsigned long epic_tag5;
+ unsigned long epic_tag6;
+ unsigned long epic_tag7;
+ unsigned long epic_data0;
+ unsigned long epic_data1;
+ unsigned long epic_data2;
+ unsigned long epic_data3;
+ unsigned long epic_data4;
+ unsigned long epic_data5;
+ unsigned long epic_data6;
+ unsigned long epic_data7;
+};
+
#ifdef __KERNEL__
+#ifndef __EXTERN_INLINE
+#define __EXTERN_INLINE extern inline
+#define __IO_EXTERN_INLINE
+#endif
+
/*
* Translate physical memory address as seen on (PCI) bus into
* a kernel virtual address and vv.
*/
-extern inline unsigned long virt_to_bus(void * address)
+
+__EXTERN_INLINE unsigned long cia_virt_to_bus(void * address)
{
return virt_to_phys(address) + CIA_DMA_WIN_BASE;
}
-extern inline void * bus_to_virt(unsigned long address)
+__EXTERN_INLINE void * cia_bus_to_virt(unsigned long address)
{
return phys_to_virt(address - CIA_DMA_WIN_BASE);
}
@@ -240,49 +313,47 @@ extern inline void * bus_to_virt(unsigned long address)
* get at PCI memory and I/O.
*/
+#define vip volatile int *
#define vuip volatile unsigned int *
+#define vulp volatile unsigned long *
-extern inline unsigned int __inb(unsigned long addr)
+__EXTERN_INLINE unsigned int cia_inb(unsigned long addr)
{
- long result = *(vuip) ((addr << 5) + CIA_IO + 0x00);
- result >>= (addr & 3) * 8;
- return 0xffUL & result;
+ long result;
+ result = *(vip) ((addr << 5) + CIA_IO + 0x00);
+ return __kernel_extbl(result, addr & 3);
}
-extern inline void __outb(unsigned char b, unsigned long addr)
+__EXTERN_INLINE void cia_outb(unsigned char b, unsigned long addr)
{
- unsigned int w;
-
- asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
+ unsigned int w = __kernel_insbl(b, addr & 3);
*(vuip) ((addr << 5) + CIA_IO + 0x00) = w;
- mb();
+ wmb();
}
-extern inline unsigned int __inw(unsigned long addr)
+__EXTERN_INLINE unsigned int cia_inw(unsigned long addr)
{
- long result = *(vuip) ((addr << 5) + CIA_IO + 0x08);
- result >>= (addr & 3) * 8;
- return 0xffffUL & result;
+ long result;
+ result = *(vip) ((addr << 5) + CIA_IO + 0x08);
+ return __kernel_extwl(result, addr & 3);
}
-extern inline void __outw(unsigned short b, unsigned long addr)
+__EXTERN_INLINE void cia_outw(unsigned short b, unsigned long addr)
{
- unsigned int w;
-
- asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
+ unsigned int w = __kernel_inswl(b, addr & 3);
*(vuip) ((addr << 5) + CIA_IO + 0x08) = w;
- mb();
+ wmb();
}
-extern inline unsigned int __inl(unsigned long addr)
+__EXTERN_INLINE unsigned int cia_inl(unsigned long addr)
{
return *(vuip) ((addr << 5) + CIA_IO + 0x18);
}
-extern inline void __outl(unsigned int b, unsigned long addr)
+__EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr)
{
*(vuip) ((addr << 5) + CIA_IO + 0x18) = b;
- mb();
+ wmb();
}
@@ -318,274 +389,213 @@ extern inline void __outl(unsigned int b, unsigned long addr)
*
*/
-#ifdef CONFIG_ALPHA_SRM_SETUP
-
-extern unsigned long cia_sm_base_r1, cia_sm_base_r2, cia_sm_base_r3;
-
-extern inline unsigned long __readb(unsigned long addr)
+__EXTERN_INLINE unsigned long cia_srm_base(unsigned long addr)
{
- unsigned long result, shift, work;
+ unsigned long mask, base;
- if ((addr >= cia_sm_base_r1) &&
- (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
- work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);
- else
- if ((addr >= cia_sm_base_r2) &&
- (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
- work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);
- else
- if ((addr >= cia_sm_base_r3) &&
- (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
- work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);
+ if (addr >= alpha_mv.sm_base_r1
+ && addr <= alpha_mv.sm_base_r1 + CIA_MEM_R1_MASK) {
+ mask = CIA_MEM_R1_MASK;
+ base = CIA_SPARSE_MEM;
+ }
+ else if (addr >= alpha_mv.sm_base_r2
+ && addr <= alpha_mv.sm_base_r2 + CIA_MEM_R2_MASK) {
+ mask = CIA_MEM_R2_MASK;
+ base = CIA_SPARSE_MEM_R2;
+ }
+ else if (addr >= alpha_mv.sm_base_r3
+ && addr <= alpha_mv.sm_base_r3 + CIA_MEM_R3_MASK) {
+ mask = CIA_MEM_R3_MASK;
+ base = CIA_SPARSE_MEM_R3;
+ }
else
{
#if 0
- printk("__readb: address 0x%lx not covered by HAE\n", addr);
+ printk("cia: address 0x%lx not covered by HAE\n", addr);
#endif
- return 0x0ffUL;
+ return 0;
}
- shift = (addr & 0x3) << 3;
- result = *(vuip) work;
- result >>= shift;
- return 0x0ffUL & result;
+
+ return ((addr & mask) << 5) + base;
}
-extern inline unsigned long __readw(unsigned long addr)
+__EXTERN_INLINE unsigned long cia_srm_readb(unsigned long addr)
{
- unsigned long result, shift, work;
+ unsigned long result, work;
- if ((addr >= cia_sm_base_r1) &&
- (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
- work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x08);
- else
- if ((addr >= cia_sm_base_r2) &&
- (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
- work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x08);
- else
- if ((addr >= cia_sm_base_r3) &&
- (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
- work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x08);
- else
- {
-#if 0
- printk("__readw: address 0x%lx not covered by HAE\n", addr);
-#endif
- return 0x0ffffUL;
- }
- shift = (addr & 0x3) << 3;
- result = *(vuip) work;
- result >>= shift;
- return 0x0ffffUL & result;
+ if ((work = cia_srm_base(addr)) == 0)
+ return 0xff;
+ work += 0x00; /* add transfer length */
+
+ result = *(vip) work;
+ return __kernel_extbl(result, addr & 3);
}
-extern inline void __writeb(unsigned char b, unsigned long addr)
+__EXTERN_INLINE unsigned long cia_srm_readw(unsigned long addr)
{
- unsigned long work;
+ unsigned long result, work;
- if ((addr >= cia_sm_base_r1) &&
- (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
- work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);
- else
- if ((addr >= cia_sm_base_r2) &&
- (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
- work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);
- else
- if ((addr >= cia_sm_base_r3) &&
- (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
- work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);
- else
- {
-#if 0
- printk("__writeb: address 0x%lx not covered by HAE\n", addr);
-#endif
- return;
- }
- *(vuip) work = b * 0x01010101;
+ if ((work = cia_srm_base(addr)) == 0)
+ return 0xffff;
+ work += 0x08; /* add transfer length */
+
+ result = *(vip) work;
+ return __kernel_extwl(result, addr & 3);
}
-extern inline void __writew(unsigned short b, unsigned long addr)
+__EXTERN_INLINE void cia_srm_writeb(unsigned char b, unsigned long addr)
{
- unsigned long work;
-
- if ((addr >= cia_sm_base_r1) &&
- (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
- work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);
- else
- if ((addr >= cia_sm_base_r2) &&
- (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
- work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);
- else
- if ((addr >= cia_sm_base_r3) &&
- (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
- work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);
- else
- {
-#if 0
- printk("__writew: address 0x%lx not covered by HAE\n", addr);
-#endif
- return;
+ unsigned long work = cia_srm_base(addr), w;
+ if (work) {
+ work += 0x00; /* add transfer length */
+ w = __kernel_insbl(b, addr & 3);
+ *(vuip) work = w;
}
- *(vuip) work = b * 0x00010001;
}
-#else /* SRM_SETUP */
-
-extern inline unsigned long __readb(unsigned long addr)
+__EXTERN_INLINE void cia_srm_writew(unsigned short b, unsigned long addr)
{
- unsigned long result, shift, msb;
-
- shift = (addr & 0x3) * 8 ;
- msb = addr & 0xE0000000 ;
- addr &= MEM_R1_MASK ;
- if (msb != hae.cache) {
- set_hae(msb);
+ unsigned long work = cia_srm_base(addr), w;
+ if (work) {
+ work += 0x08; /* add transfer length */
+ w = __kernel_inswl(b, addr & 3);
+ *(vuip) work = w;
}
- result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) ;
- result >>= shift;
- return 0xffUL & result;
}
-extern inline unsigned long __readw(unsigned long addr)
+__EXTERN_INLINE unsigned long cia_readb(unsigned long addr)
{
- unsigned long result, shift, msb;
+ unsigned long result, msb;
- shift = (addr & 0x3) * 8;
- msb = addr & 0xE0000000 ;
- addr &= MEM_R1_MASK ;
- if (msb != hae.cache) {
- set_hae(msb);
- }
- result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
- result >>= shift;
- return 0xffffUL & result;
+ msb = addr & 0xE0000000;
+ addr &= CIA_MEM_R1_MASK;
+ set_hae(msb);
+
+ result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00);
+ return __kernel_extbl(result, addr & 3);
}
-extern inline void __writeb(unsigned char b, unsigned long addr)
+__EXTERN_INLINE unsigned long cia_readw(unsigned long addr)
{
- unsigned long msb ;
+ unsigned long result, msb;
- msb = addr & 0xE0000000 ;
- addr &= MEM_R1_MASK ;
- if (msb != hae.cache) {
- set_hae(msb);
- }
- *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = b * 0x01010101;
+ msb = addr & 0xE0000000;
+ addr &= CIA_MEM_R1_MASK;
+ set_hae(msb);
+
+ result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
+ return __kernel_extwl(result, addr & 3);
}
-extern inline void __writew(unsigned short b, unsigned long addr)
+__EXTERN_INLINE void cia_writeb(unsigned char b, unsigned long addr)
{
- unsigned long msb ;
+ unsigned long msb, w;
- msb = addr & 0xE0000000 ;
- addr &= MEM_R1_MASK ;
- if (msb != hae.cache) {
- set_hae(msb);
- }
- *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = b * 0x00010001;
+ msb = addr & 0xE0000000;
+ addr &= CIA_MEM_R1_MASK;
+ set_hae(msb);
+
+ w = __kernel_insbl(b, addr & 3);
+ *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w;
}
-#endif /* SRM_SETUP */
+__EXTERN_INLINE void cia_writew(unsigned short b, unsigned long addr)
+{
+ unsigned long msb, w;
-extern inline unsigned long __readl(unsigned long addr)
+ msb = addr & 0xE0000000;
+ addr &= CIA_MEM_R1_MASK;
+ set_hae(msb);
+
+ w = __kernel_inswl(b, addr & 3);
+ *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w;
+}
+
+__EXTERN_INLINE unsigned long cia_readl(unsigned long addr)
{
return *(vuip) (addr + CIA_DENSE_MEM);
}
-extern inline void __writel(unsigned int b, unsigned long addr)
+__EXTERN_INLINE unsigned long cia_readq(unsigned long addr)
+{
+ return *(vulp) (addr + CIA_DENSE_MEM);
+}
+
+__EXTERN_INLINE void cia_writel(unsigned int b, unsigned long addr)
{
*(vuip) (addr + CIA_DENSE_MEM) = b;
}
+__EXTERN_INLINE void cia_writeq(unsigned long b, unsigned long addr)
+{
+ *(vulp) (addr + CIA_DENSE_MEM) = b;
+}
+
+/* Find the DENSE memory area for a given bus address. */
+
+__EXTERN_INLINE unsigned long cia_dense_mem(unsigned long addr)
+{
+ return CIA_DENSE_MEM;
+}
+
+#undef vip
+#undef vuip
+#undef vulp
+
+#ifdef __WANT_IO_DEF
+
+#define virt_to_bus cia_virt_to_bus
+#define bus_to_virt cia_bus_to_virt
+#define __inb cia_inb
+#define __inw cia_inw
+#define __inl cia_inl
+#define __outb cia_outb
+#define __outw cia_outw
+#define __outl cia_outl
+
+#ifdef CONFIG_ALPHA_SRM_SETUP
+#define __readb cia_srm_readb
+#define __readw cia_srm_readw
+#define __writeb cia_srm_writeb
+#define __writew cia_srm_writew
+#else
+#define __readb cia_readb
+#define __readw cia_readw
+#define __writeb cia_writeb
+#define __writew cia_writew
+#endif
+
+#define __readl cia_readl
+#define __readq cia_readq
+#define __writel cia_writel
+#define __writeq cia_writeq
+#define dense_mem cia_dense_mem
+
#define inb(port) \
(__builtin_constant_p((port))?__inb(port):_inb(port))
-
#define outb(x, port) \
(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
+#define inw(port) \
+(__builtin_constant_p((port))?__inw(port):_inw(port))
+#define outw(x, port) \
+(__builtin_constant_p((port))?__outw((x),(port)):_outw((x),(port)))
+
+#define inl(port) __inl(port)
+#define outl(x,port) __outl((x),(port))
+
#define readl(a) __readl((unsigned long)(a))
+#define readq(a) __readq((unsigned long)(a))
#define writel(v,a) __writel((v),(unsigned long)(a))
+#define writeq(v,a) __writeq((v),(unsigned long)(a))
-#undef vuip
+#endif /* __WANT_IO_DEF */
-extern unsigned long cia_init (unsigned long mem_start,
- unsigned long mem_end);
+#ifdef __IO_EXTERN_INLINE
+#undef __EXTERN_INLINE
+#undef __IO_EXTERN_INLINE
+#endif
#endif /* __KERNEL__ */
-/*
- * Data structure for handling CIA machine checks:
- */
-/* ev5-specific info: */
-struct el_procdata {
- unsigned long shadow[8]; /* PALmode shadow registers */
- unsigned long paltemp[24]; /* PAL temporary registers */
- /* EV5-specific fields */
- unsigned long exc_addr; /* Address of excepting instruction. */
- unsigned long exc_sum; /* Summary of arithmetic traps. */
- unsigned long exc_mask; /* Exception mask (from exc_sum). */
- unsigned long exc_base; /* PALbase at time of exception. */
- unsigned long isr; /* Interrupt summary register. */
- unsigned long icsr; /* Ibox control register. */
- unsigned long ic_perr_stat;
- unsigned long dc_perr_stat;
- unsigned long va; /* Effective VA of fault or miss. */
- unsigned long mm_stat;
- unsigned long sc_addr;
- unsigned long sc_stat;
- unsigned long bc_tag_addr;
- unsigned long ei_addr;
- unsigned long fill_syn;
- unsigned long ei_stat;
- unsigned long ld_lock;
-};
-
-/* system-specific info: */
-struct el_CIA_sysdata_mcheck {
- unsigned long coma_gcr;
- unsigned long coma_edsr;
- unsigned long coma_ter;
- unsigned long coma_elar;
- unsigned long coma_ehar;
- unsigned long coma_ldlr;
- unsigned long coma_ldhr;
- unsigned long coma_base0;
- unsigned long coma_base1;
- unsigned long coma_base2;
- unsigned long coma_cnfg0;
- unsigned long coma_cnfg1;
- unsigned long coma_cnfg2;
- unsigned long epic_dcsr;
- unsigned long epic_pear;
- unsigned long epic_sear;
- unsigned long epic_tbr1;
- unsigned long epic_tbr2;
- unsigned long epic_pbr1;
- unsigned long epic_pbr2;
- unsigned long epic_pmr1;
- unsigned long epic_pmr2;
- unsigned long epic_harx1;
- unsigned long epic_harx2;
- unsigned long epic_pmlt;
- unsigned long epic_tag0;
- unsigned long epic_tag1;
- unsigned long epic_tag2;
- unsigned long epic_tag3;
- unsigned long epic_tag4;
- unsigned long epic_tag5;
- unsigned long epic_tag6;
- unsigned long epic_tag7;
- unsigned long epic_data0;
- unsigned long epic_data1;
- unsigned long epic_data2;
- unsigned long epic_data3;
- unsigned long epic_data4;
- unsigned long epic_data5;
- unsigned long epic_data6;
- unsigned long epic_data7;
-};
-
-#define RTC_PORT(x) (0x70 + (x))
-#define RTC_ADDR(x) (0x80 | (x))
-#define RTC_ALWAYS_BCD 0
-
#endif /* __ALPHA_CIA__H__ */
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