diff options
| -rw-r--r-- | arch/mips/ddb5074/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/ddb5074/pci.c | 55 | ||||
| -rw-r--r-- | arch/mips/ddb5074/setup.c | 13 | ||||
| -rw-r--r-- | drivers/char/serial.c | 3 |
4 files changed, 57 insertions, 16 deletions
diff --git a/arch/mips/ddb5074/Makefile b/arch/mips/ddb5074/Makefile index d041acef5..559e0bc8e 100644 --- a/arch/mips/ddb5074/Makefile +++ b/arch/mips/ddb5074/Makefile @@ -17,6 +17,6 @@ $(CC) $(CFLAGS) -c $< -o $*.o O_TARGET = ddb5074.a -O_OBJS = setup.o irq.o time.o prom.o pci.o int-handler.o nile4.o +O_OBJS = setup.o irq.o time.o prom.o pci.o pci-dma.o int-handler.o nile4.o include $(TOPDIR)/Rules.make diff --git a/arch/mips/ddb5074/pci.c b/arch/mips/ddb5074/pci.c index e0ca01d17..3b82395b0 100644 --- a/arch/mips/ddb5074/pci.c +++ b/arch/mips/ddb5074/pci.c @@ -168,8 +168,29 @@ struct pci_ops nile4_pci_ops = { nile4_pci_write_config_dword }; +struct { + struct resource ram; + struct resource flash; + struct resource isa_io; + struct resource pci_io; + struct resource isa_mem; + struct resource pci_mem; + struct resource nile4; + struct resource boot; +} ddb5074_resources = { + { "RAM", 0x00000000, 0x03ffffff, + IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 }, + { "Flash ROM", 0x04000000, 0x043fffff }, + { "Nile4 ISA I/O", 0x06000000, 0x060fffff }, + { "Nile4 PCI I/O", 0x06100000, 0x07ffffff }, + { "Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM }, + { "Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM }, + { "Nile4 ctrl", 0x1fa00000, 0x1fbfffff, + IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 }, + { "Boot ROM", 0x1fc00000, 0x1fffffff } +}; -static void __init ddb5074_preassign_resources(void) +static void __init ddb5074_pci_fixup(void) { struct pci_dev *dev; @@ -177,19 +198,24 @@ static void __init ddb5074_preassign_resources(void) if (dev->vendor == PCI_VENDOR_ID_NEC && dev->device == PCI_DEVICE_ID_NEC_NILE4) { /* - * Fixup so the serial driver can use the UART + * The first 64-bit PCI base register should point to the Nile4 + * control registers. Unfortunately this isn't the case, so we fix + * it ourselves. This allows the serial driver to find the UART. */ - dev->resource[0].start = PHYSADDR(NILE4_BASE); - dev->resource[0].end = dev->resource[0].start+NILE4_SIZE-1; - dev->resource[0].flags = IORESOURCE_MEM | - PCI_BASE_ADDRESS_MEM_TYPE_64; - pci_claim_resource(dev, 0); + dev->resource[0] = ddb5074_resources.nile4; + request_resource(&iomem_resource, &dev->resource[0]); /* - * Leave resource[2] (physical memory) alone + * The second 64-bit PCI base register points to the first memory + * bank. Unfortunately the address is wrong, so we fix it (again). */ - pci_claim_resource(dev, 2); + dev->resource[2] = ddb5074_resources.ram; + request_resource(&iomem_resource, &dev->resource[2]); } else if (dev->vendor == PCI_VENDOR_ID_AL && dev->device == PCI_DEVICE_ID_AL_M7101) { + /* + * It's nice to have the LEDs on the GPIO pins available for + * debugging + */ extern struct pci_dev *pci_pmu; u8 t8; @@ -249,8 +275,16 @@ void __init pcibios_init(void) printk("PCI: Probing PCI hardware\n"); ioport_resource.end = 0x1ffffff; /* 32 MB */ iomem_resource.end = 0x1fffffff; /* 512 MB */ + /* `ram' and `nile4' are requested through the Nile4 pci_dev */ + request_resource(&iomem_resource, &ddb5074_resources.flash); + request_resource(&iomem_resource, &ddb5074_resources.isa_io); + request_resource(&iomem_resource, &ddb5074_resources.pci_io); + request_resource(&iomem_resource, &ddb5074_resources.isa_mem); + request_resource(&iomem_resource, &ddb5074_resources.pci_mem); + request_resource(&iomem_resource, &ddb5074_resources.boot); + pci_scan_bus(0, &nile4_pci_ops, NULL); - ddb5074_preassign_resources(); + ddb5074_pci_fixup(); pci_assign_unassigned_resources(); pci_set_bus_ranges(); pcibios_fixup_irqs(); @@ -258,6 +292,7 @@ void __init pcibios_init(void) void __init pcibios_fixup_bus(struct pci_bus *bus) { + bus->resource[1] = &ddb5074_resources.pci_mem; } char *pcibios_setup (char *str) diff --git a/arch/mips/ddb5074/setup.c b/arch/mips/ddb5074/setup.c index 00bfd4c1f..6f0eff4d9 100644 --- a/arch/mips/ddb5074/setup.c +++ b/arch/mips/ddb5074/setup.c @@ -40,12 +40,12 @@ extern void console_setup(char *); extern struct rtc_ops ddb_rtc_ops; +static void (*back_to_prom)(void) = (void (*)(void))0xbfc00000; + static void ddb_machine_restart(char *command) { u32 t; - // FIXME: This doesn't seem to work... - printk("Restarting DDB Vrc-5074..."); /* PCI cold reset */ t = nile4_in32(NILE4_PCICTRL+4); t |= 0x40000000; @@ -54,8 +54,8 @@ static void ddb_machine_restart(char *command) t = nile4_in32(NILE4_CPUSTAT); t |= 1; nile4_out32(NILE4_CPUSTAT, t); - printk("Restart failed!\n"); - do {} while (1); + /* Call the PROM */ + back_to_prom(); } static void ddb_machine_halt(void) @@ -91,6 +91,8 @@ static void __init ddb_time_init(struct irqaction *irq) void __init ddb_setup(void) { + extern int panic_timeout; + irq_setup = ddb_irq_setup; mips_io_port_base = NILE4_PCI_IO_BASE; isa_slot_offset = NILE4_PCI_MEM_BASE; @@ -106,6 +108,9 @@ void __init ddb_setup(void) _machine_power_off = ddb_machine_power_off; rtc_ops = &ddb_rtc_ops; + + /* Reboot on panic */ + panic_timeout = 180; } int __init page_is_ram(unsigned long pagenr) diff --git a/drivers/char/serial.c b/drivers/char/serial.c index a29a904dd..110df61af 100644 --- a/drivers/char/serial.c +++ b/drivers/char/serial.c @@ -4209,9 +4209,10 @@ static struct pci_board pci_boards[] __initdata = { { PCI_VENDOR_ID_ROCKWELL, 0x1004, 0x1048, 0x1500, SPCI_FL_BASE1, 1, 115200 }, -#if 0 /* No definition for PCI_DEVICE_ID_NEC_NILE4 */ +#ifdef CONFIG_DDB5074 /* * NEC Vrc-5074 (Nile 4) builtin UART. + * Conditionally compiled in since this is a motherboard device. */ { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4, PCI_ANY_ID, PCI_ANY_ID, |