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-rw-r--r--arch/mips/arc/console.c25
-rw-r--r--arch/mips/arc/printf.c6
2 files changed, 29 insertions, 2 deletions
diff --git a/arch/mips/arc/console.c b/arch/mips/arc/console.c
index c1934e796..beca1543d 100644
--- a/arch/mips/arc/console.c
+++ b/arch/mips/arc/console.c
@@ -2,25 +2,48 @@
* console.c: SGI arcs console code.
*
* Copyright (C) 1996 David S. Miller (dm@sgi.com)
+ * Compability with board caches, Ulf Carlsson
*
- * $Id: console.c,v 1.2 1998/04/05 11:24:01 ralf Exp $
+ * $Id: console.c,v 1.1 1998/10/18 13:32:08 tsbogend Exp $
*/
#include <linux/init.h>
#include <asm/sgialib.h>
+#include <asm/bcache.h>
+/* The romvec is not compatible with board caches. Thus we disable it during
+ * romvec action. Since r4xx0.c is always compiled and linked with your kernel,
+ * this shouldn't cause any harm regardless what MIPS processor you have.
+ *
+ * The romvec write and read functions seem to interfere with the serial lines
+ * in some way. You should be careful with them.
+ */
+extern struct bcache_ops *bcops;
+
+#ifdef CONFIG_SGI_PROM_CONSOLE
+void prom_putchar(char c)
+#else
__initfunc(void prom_putchar(char c))
+#endif
{
long cnt;
char it = c;
+ bcops->bc_disable();
romvec->write(1, &it, 1, &cnt);
+ bcops->bc_enable();
}
+#ifdef CONFIG_SGI_PROM_CONSOLE
+char prom_getchar(void)
+#else
__initfunc(char prom_getchar(void))
+#endif
{
long cnt;
char c;
+ bcops->bc_disable();
romvec->read(0, &c, 1, &cnt);
+ bcops->bc_enable();
return c;
}
diff --git a/arch/mips/arc/printf.c b/arch/mips/arc/printf.c
index 132f97c82..422578017 100644
--- a/arch/mips/arc/printf.c
+++ b/arch/mips/arc/printf.c
@@ -4,7 +4,7 @@
*
* Copyright (C) 1996 David S. Miller (dm@sgi.com)
*
- * $Id: printf.c,v 1.2 1998/04/05 11:24:03 ralf Exp $
+ * $Id: printf.c,v 1.1 1998/10/18 13:32:09 tsbogend Exp $
*/
#include <linux/init.h>
#include <linux/kernel.h>
@@ -13,7 +13,11 @@
static char ppbuf[1024];
+#ifdef CONFIG_SGI_PROM_CONSOLE
+void prom_printf(char *fmt, ...)
+#else
__initfunc(void prom_printf(char *fmt, ...))
+#endif
{
va_list args;
char ch, *bptr;