diff options
| -rw-r--r-- | arch/mips/gt64120/momenco_ocelot/reset.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/rm7k.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c index a54b9d6ff..039ad758a 100644 --- a/arch/mips/gt64120/momenco_ocelot/reset.c +++ b/arch/mips/gt64120/momenco_ocelot/reset.c @@ -27,7 +27,7 @@ void momenco_ocelot_restart(char *command) * detection stuff. */ clear_cp0_status(ST0_BEV | ST0_ERL); - set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); flush_cache_all(); write_32bit_cp0_register(CP0_WIRED, 0); __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); diff --git a/arch/mips/mm/rm7k.c b/arch/mips/mm/rm7k.c index ac1416e00..9659ac477 100644 --- a/arch/mips/mm/rm7k.c +++ b/arch/mips/mm/rm7k.c @@ -535,7 +535,7 @@ void __init ld_mmu_rm7k(void) printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); + change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); probe_icache(config); probe_dcache(config); |