summaryrefslogtreecommitdiffstats
path: root/drivers/net
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/3c505.c8
-rw-r--r--drivers/net/3c59x.c1223
-rw-r--r--drivers/net/Config.in1
-rw-r--r--drivers/net/eth16i.c2
-rw-r--r--drivers/net/hamradio/Config.in1
-rw-r--r--drivers/net/hamradio/dmascc.c1260
-rw-r--r--drivers/net/ipddp.c3
7 files changed, 2272 insertions, 226 deletions
diff --git a/drivers/net/3c505.c b/drivers/net/3c505.c
index ae1f06c99..d645ce165 100644
--- a/drivers/net/3c505.c
+++ b/drivers/net/3c505.c
@@ -323,7 +323,7 @@ inline static void adapter_reset(struct device *dev)
* never happen in theory, but seems to occur occasionally if the card gets
* prodded at the wrong time.
*/
-static inline void check_dma(struct device *dev)
+static inline void check_3c505_dma(struct device *dev)
{
elp_device *adapter = dev->priv;
if (adapter->dmaing && (jiffies > (adapter->current_dma.start_time + 10))) {
@@ -406,7 +406,7 @@ static int send_pcb(struct device *dev, pcb_struct * pcb)
int timeout;
elp_device *adapter = dev->priv;
- check_dma(dev);
+ check_3c505_dma(dev);
if (adapter->dmaing && adapter->current_dma.direction == 0)
return FALSE;
@@ -723,7 +723,7 @@ static void elp_interrupt(int irq, void *dev_id, struct pt_regs *reg_ptr)
}
} else {
/* has one timed out? */
- check_dma(dev);
+ check_3c505_dma(dev);
}
sti();
@@ -1088,7 +1088,7 @@ static int elp_start_xmit(struct sk_buff *skb, struct device *dev)
return 1;
}
- check_dma(dev);
+ check_3c505_dma(dev);
/*
* if the transmitter is still busy, we have a transmit timeout...
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c
index c2fa5b507..4202f8ef6 100644
--- a/drivers/net/3c59x.c
+++ b/drivers/net/3c59x.c
@@ -1,31 +1,60 @@
-/* 3c59x.c: A 3Com 3c590/3c595 "Vortex" ethernet driver for linux. */
+/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
/*
- Written 1995 by Donald Becker.
+ Written 1996-1997 by Donald Becker.
This software may be used and distributed according to the terms
of the GNU Public License, incorporated herein by reference.
- This driver is for the 3Com "Vortex" series ethercards. Members of
- the series include the 3c590 PCI EtherLink III and 3c595-Tx PCI Fast
- EtherLink.
+ This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
+ Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
+ and the EtherLink XL 3c900 and 3c905 cards.
The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O
Center of Excellence in Space Data and Information Sciences
Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771
*/
-static char *version = "3c59x.c:v0.25 5/17/96 becker@cesdis.gsfc.nasa.gov\n";
+static char *version =
+"3c59x.c:v0.46B 9/25/97 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/vortex.html\n";
-/* "Knobs" that turn on special features. */
-/* Enable the experimental automatic media selection code. */
+/* "Knobs" that adjust features and parameters. */
+/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
+ Setting to > 1512 effectively disables this feature. */
+static const rx_copybreak = 200;
+/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
+static const mtu = 1500;
+/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
+static int max_interrupt_work = 20;
+
+/* Enable the automatic media selection code -- usually set. */
#define AUTOMEDIA 1
-/* Allow the use of bus master transfers instead of programmed-I/O for the
- Tx process. Bus master transfers are always disabled by default, but
- iff this is set they may be turned on using 'options'. */
+/* Allow the use of fragment bus master transfers instead of only
+ programmed-I/O for Vortex cards. Full-bus-master transfers are always
+ enabled by default on Boomerang cards. If VORTEX_BUS_MASTER is defined,
+ the feature may be turned on using 'options'. */
#define VORTEX_BUS_MASTER
+
+/* A few values that may be tweaked. */
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT ((400*HZ)/1000)
+
+/* Keep the ring sizes a power of two for efficiency. */
+#define TX_RING_SIZE 16
+#define RX_RING_SIZE 32
+#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
+
#include <linux/config.h>
+#ifdef MODULE
+#ifdef MODVERSIONS
+#include <linux/modversions.h>
+#endif
#include <linux/module.h>
+#include <linux/version.h>
+#else
+#define MOD_INC_USE_COUNT
+#define MOD_DEC_USE_COUNT
+#endif
#include <linux/kernel.h>
#include <linux/sched.h>
@@ -36,16 +65,10 @@ static char *version = "3c59x.c:v0.25 5/17/96 becker@cesdis.gsfc.nasa.gov\n";
#include <linux/ioport.h>
#include <linux/malloc.h>
#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <linux/delay.h>
-
-#ifdef CONFIG_PCI
#include <linux/pci.h>
#include <linux/bios32.h>
-#endif
-
#include <linux/timer.h>
+#include <asm/irq.h> /* For NR_IRQS only. */
#include <asm/bitops.h>
#include <asm/io.h>
@@ -53,27 +76,60 @@ static char *version = "3c59x.c:v0.25 5/17/96 becker@cesdis.gsfc.nasa.gov\n";
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
+/* Kernel compatibility defines, common to David Hind's PCMCIA package.
+ This is only in the support-all-kernels source code. */
+#ifndef LINUX_VERSION_CODE
+#include <linux/version.h> /* Redundant above, here for easy clean-up. */
+#endif
+#if LINUX_VERSION_CODE < 0x10300
+#define RUN_AT(x) (x) /* What to put in timer->expires. */
+#define DEV_ALLOC_SKB(len) alloc_skb(len, GFP_ATOMIC)
+#if defined(__alpha)
+#error "The Alpha architecture is only support with kernel version 2.0."
+#endif
+#define virt_to_bus(addr) ((unsigned long)addr)
+#define bus_to_virt(addr) ((void*)addr)
+#else /* 1.3.0 and later */
#define RUN_AT(x) (jiffies + (x))
#define DEV_ALLOC_SKB(len) dev_alloc_skb(len + 2)
+#endif
+#ifdef SA_SHIRQ
#define FREE_IRQ(irqnum, dev) free_irq(irqnum, dev)
#define REQUEST_IRQ(i,h,f,n, instance) request_irq(i,h,f,n, instance)
#define IRQ(irq, dev_id, pt_regs) (irq, dev_id, pt_regs)
+#else
+#define FREE_IRQ(irqnum, dev) free_irq(irqnum)
+#define REQUEST_IRQ(i,h,f,n, instance) request_irq(i,h,f,n)
+#define IRQ(irq, dev_id, pt_regs) (irq, pt_regs)
+#endif
+
+#if (LINUX_VERSION_CODE >= 0x10344)
+#define NEW_MULTICAST
+#include <linux/delay.h>
+#else
+#define udelay(microsec) do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
+#endif
+
+#if (LINUX_VERSION_CODE < 0x20123)
+#define test_and_set_bit(val, addr) set_bit(val, addr)
+#endif
/* "Knobs" for adjusting internal parameters. */
/* Put out somewhat more debugging messages. (0 - no msg, 1 minimal msgs). */
-#define VORTEX_DEBUG 2
-
-/* Number of times to check to see if the Tx FIFO has space, used in some
- limited cases. */
-#define WAIT_TX_AVAIL 200
+#define VORTEX_DEBUG 1
+/* Some values here only for performance evaluation and path-coverage
+ debugging. */
+static int rx_nocopy = 0, rx_copy = 0, queued_packet = 0;
/* Operational parameter that usually are not changed. */
-#define TX_TIMEOUT 40 /* Time in jiffies before concluding Tx hung */
-/* The total size is twice that of the original EtherLinkIII series: the
- runtime register window, window 1, is now always mapped in. */
+/* The Vortex size is twice that of the original EtherLinkIII series: the
+ runtime register window, window 1, is now always mapped in.
+ The Boomerang size is twice as large as the Vortex -- it has additional
+ bus master control registers. */
#define VORTEX_TOTAL_SIZE 0x20
+#define BOOMERANG_TOTAL_SIZE 0x40
#ifdef HAVE_DEVLIST
struct netdev_entry tc59x_drv =
@@ -86,27 +142,40 @@ static int vortex_debug = VORTEX_DEBUG;
static int vortex_debug = 1;
#endif
-#ifdef CONFIG_PCI
-static int product_ids[] __initdata = {0x5900, 0x5950, 0x5951, 0x5952, 0, 0};
-#endif
+/* Set iff a MII transceiver on any interface requires mdio preamble. */
+static char mii_preamble_required = 0;
+/* Caution! These entries must be consistent, with the EISA ones last. */
+static const int product_ids[] = {
+ 0x5900, 0x5950, 0x5951, 0x5952, 0x9000, 0x9001, 0x9050, 0x9051, 0, 0};
static const char *product_names[] = {
"3c590 Vortex 10Mbps",
"3c595 Vortex 100baseTX",
"3c595 Vortex 100baseT4",
"3c595 Vortex 100base-MII",
- "EISA Vortex 3c597",
+ "3c900 Boomerang 10baseT",
+ "3c900 Boomerang 10Mbps/Combo",
+ "3c905 Boomerang 100baseTx",
+ "3c905 Boomerang 100baseT4",
+ "3c592 EISA 10mbps Demon/Vortex",
+ "3c597 EISA Fast Demon/Vortex",
};
-#define DEMON_INDEX 5 /* Caution! Must be consistent with above! */
+#define DEMON10_INDEX 8
+#define DEMON100_INDEX 9
/*
Theory of Operation
I. Board Compatibility
-This device driver is designed for the 3Com FastEtherLink, 3Com's PCI to
-10/100baseT adapter. It also works with the 3c590, a similar product
-with only a 10Mbs interface.
+This device driver is designed for the 3Com FastEtherLink and FastEtherLink
+XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
+versions of the FastEtherLink cards. The supported product IDs are
+ 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
+
+The ISA 3c515 is supported with a seperate driver, 3c515.c, included with
+the kernel source or available from
+ cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
II. Board-specific settings
@@ -122,12 +191,33 @@ The 3c59x series use an interface that's very similar to the previous 3c5x9
series. The primary interface is two programmed-I/O FIFOs, with an
alternate single-contiguous-region bus-master transfer (see next).
+The 3c900 "Boomerang" series uses a full-bus-master interface with seperate
+lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
+DEC Tulip and Intel Speedo3. The first chip version retains a compatible
+programmed-I/O interface that will be removed in the 'B' and subsequent
+revisions.
+
One extension that is advertised in a very large font is that the adapters
-are capable of being bus masters. Unfortunately this capability is only for
-a single contiguous region making it less useful than the list of transfer
-regions available with the DEC Tulip or AMD PCnet. Given the significant
-performance impact of taking an extra interrupt for each transfer, using
-DMA transfers is a win only with large blocks.
+are capable of being bus masters. On the Vortex chip this capability was
+only for a single contiguous region making it far less useful than the full
+bus master capability. There is a significant performance impact of taking
+an extra interrupt or polling for the completion of each transfer, as well
+as difficulty sharing the single transfer engine between the transmit and
+receive threads. Using DMA transfers is a win only with large blocks or
+with the flawed versions of the Intel Orion motherboard PCI controller.
+
+The Boomerang chip's full-bus-master interface is useful, and has the
+currently-unused advantages over other similar chips that queued transmit
+packets may be reordered and receive buffer groups are associated with a
+single frame.
+
+With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
+Tather than a fixed intermediate receive buffer, this scheme allocates
+full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
+the copying breakpoint: it is chosen to trade-off the memory wasted by
+passing the full-sized skbuff to the queue layer for all frames vs. the
+copying cost of copying a frame to a correctly-sized skbuff.
+
IIIC. Synchronization
The driver runs as two independent, single-threaded flows of control. One
@@ -137,8 +227,8 @@ threaded by the hardware and other software.
IV. Notes
-Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing both
-3c590 and 3c595 boards.
+Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
+3c590, 3c595, and 3c900 boards.
The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
the EISA version is called "Demon". According to Terry these names come
from rides at the local amusement park.
@@ -169,8 +259,10 @@ limit of 4K.
enum vortex_cmd {
TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
- RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11,
- TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
+ RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
+ UpStall = 6<<11, UpUnstall = (6<<11)+1,
+ DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
+ RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
SetTxThreshold = 18<<11, SetTxStart = 19<<11,
@@ -185,7 +277,8 @@ enum RxFilter {
enum vortex_status {
IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
- IntReq = 0x0040, StatsFull = 0x0080, DMADone = 1<<8,
+ IntReq = 0x0040, StatsFull = 0x0080,
+ DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
DMAInProgress = 1<<11, /* DMA controller is still busy.*/
CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
};
@@ -200,6 +293,7 @@ enum Window1 {
enum Window0 {
Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
Wn0EepromData = 12, /* Window 0: EEPROM results register. */
+ IntrStatus=0x0E, /* Valid in all windows. */
};
enum Win0_EEPROM_bits {
EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
@@ -222,12 +316,12 @@ union wn3_config {
unsigned int ram_size:3, ram_width:1, ram_speed:2, rom_size:2;
int pad8:8;
unsigned int ram_split:2, pad18:2, xcvr:3, pad21:1, autoselect:1;
- int pad24:8;
+ int pad24:7;
} u;
};
-enum Window4 {
- Wn4_Media = 0x0A, /* Window 4: Various transcvr/media bits. */
+enum Window4 { /* Window 4: Xcvr/media bits. */
+ Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
};
enum Win4_Media_bits {
Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
@@ -238,12 +332,54 @@ enum Win4_Media_bits {
enum Window7 { /* Window 7: Bus Master control. */
Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
};
+/* Boomerang bus master control registers. */
+enum MasterCtrl {
+ PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
+ TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
+};
+
+/* The Rx and Tx descriptor lists.
+ Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
+ alignment contraint on tx_ring[] and rx_ring[]. */
+#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
+struct boom_rx_desc {
+ u32 next; /* Last entry points to 0. */
+ s32 status;
+ u32 addr; /* Up to addr/len possible.. */
+ s32 length; /* set high bit to indicate last pair. */
+};
+/* Values for the Rx status entry. */
+enum rx_desc_status {
+ RxDComplete=0x00008000, RxDError=0x4000,
+ /* See boomerang_rx() for actual error bits */
+};
+
+struct boom_tx_desc {
+ u32 next; /* Last entry points to 0. */
+ s32 status; /* bits 0:12 length, others see below. */
+ u32 addr;
+ s32 length;
+};
+
+/* Values for the Tx status entry. */
+enum tx_desc_status {
+ CRCDisable=0x2000, TxDComplete=0x8000,
+ TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
+};
struct vortex_private {
char devname[8]; /* "ethN" string, also for kernel debug. */
const char *product_name;
struct device *next_module;
- struct net_device_stats stats;
+ /* The Rx and Tx rings are here to keep them quad-word-aligned. */
+ struct boom_rx_desc rx_ring[RX_RING_SIZE];
+ struct boom_tx_desc tx_ring[TX_RING_SIZE];
+ /* The addresses of transmit- and receive-in-place skbuffs. */
+ struct sk_buff* rx_skbuff[RX_RING_SIZE];
+ struct sk_buff* tx_skbuff[TX_RING_SIZE];
+ unsigned int cur_rx, cur_tx; /* The next free ring entry */
+ unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
+ struct enet_statistics stats;
struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
struct timer_list timer; /* Media selection timer. */
int options; /* User-settable misc. driver options. */
@@ -251,12 +387,23 @@ struct vortex_private {
unsigned int available_media:8, /* From Wn3_Options */
media_override:3, /* Passed-in media type. */
default_media:3, /* Read from the EEPROM. */
- full_duplex:1, bus_master:1, autoselect:1;
+ full_duplex:1, autoselect:1,
+ bus_master:1, /* Vortex can only do a fragment bus-m. */
+ full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
+ tx_full:1;
+ u16 capabilities; /* Adapter capabilities word. */
+ u16 info1, info2; /* Software information information. */
+ unsigned char phys[2]; /* MII device addresses. */
};
/* The action to take with a media selection timer tick.
Note that we deviate from the 3Com order by checking 10base2 before AUI.
*/
+enum xcvr_types {
+ XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
+ XCVR_100baseFx, XCVR_MII=6, XCVR_Default=8,
+};
+
static struct media_table {
char *name;
unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
@@ -264,30 +411,44 @@ static struct media_table {
next:8; /* The media type to try next. */
short wait; /* Time before we check media status. */
} media_tbl[] = {
- { "10baseT", Media_10TP,0x08, 3 /* 10baseT->10base2 */, (14*HZ)/10},
- { "10Mbs AUI", Media_SQE, 0x20, 8 /* AUI->default */, (1*HZ)/10},
- { "undefined", 0, 0x80, 0 /* Undefined */, 0},
- { "10base2", 0, 0x10, 1 /* 10base2->AUI. */, (1*HZ)/10},
- { "100baseTX", Media_Lnk, 0x02, 5 /* 100baseTX->100baseFX */, (14*HZ)/10},
- { "100baseFX", Media_Lnk, 0x04, 6 /* 100baseFX->MII */, (14*HZ)/10},
- { "MII", 0, 0x40, 0 /* MII->10baseT */, (14*HZ)/10},
- { "undefined", 0, 0x01, 0 /* Undefined/100baseT4 */, 0},
- { "Default", 0, 0xFF, 0 /* Use default */, 0},
+ { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
+ { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
+ { "undefined", 0, 0x80, XCVR_10baseT, 10000},
+ { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
+ { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
+ { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
+ { "MII", 0, 0x40, XCVR_10baseT, 3*HZ },
+ { "undefined", 0, 0x01, XCVR_10baseT, 10000},
+ { "Default", 0, 0xFF, XCVR_10baseT, 10000},
};
static int vortex_scan(struct device *dev);
-static int vortex_found_device(struct device *dev, int ioaddr, int irq,
- int product_index, int options);
+static struct device *vortex_found_device(struct device *dev, int ioaddr,
+ int irq, int product_index,
+ int options, int card_idx);
static int vortex_probe1(struct device *dev);
static int vortex_open(struct device *dev);
+static void mdio_sync(int ioaddr, int bits);
+static int mdio_read(int ioaddr, int phy_id, int location);
+#ifdef HAVE_PRIVATE_IOCTL
+static void mdio_write(int ioaddr, int phy_id, int location, int value);
+#endif
static void vortex_timer(unsigned long arg);
static int vortex_start_xmit(struct sk_buff *skb, struct device *dev);
+static int boomerang_start_xmit(struct sk_buff *skb, struct device *dev);
static int vortex_rx(struct device *dev);
+static int boomerang_rx(struct device *dev);
static void vortex_interrupt IRQ(int irq, void *dev_id, struct pt_regs *regs);
static int vortex_close(struct device *dev);
static void update_stats(int addr, struct device *dev);
-static struct net_device_stats *vortex_get_stats(struct device *dev);
+static struct enet_statistics *vortex_get_stats(struct device *dev);
static void set_rx_mode(struct device *dev);
+#ifdef HAVE_PRIVATE_IOCTL
+static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd);
+#endif
+#ifndef NEW_MULTICAST
+static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
+#endif
/* Unlike the other PCI cards the 59x cards don't need a large contiguous
@@ -307,11 +468,15 @@ static void set_rx_mode(struct device *dev);
/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
/* Note: this is the only limit on the number of cards supported!! */
static int options[8] = { -1, -1, -1, -1, -1, -1, -1, -1,};
+static int full_duplex[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
+/* A list of all installed Vortex devices, for removing the driver module. */
+static struct device *root_vortex_dev = NULL;
+
+/* Variables to work-around the Compaq PCI BIOS32 problem. */
+static int compaq_ioaddr = 0, compaq_irq = 0, compaq_prod_id = 0;
#ifdef MODULE
static int debug = -1;
-/* A list of all installed Vortex devices, for removing the driver module. */
-static struct device *root_vortex_dev = NULL;
int
init_module(void)
@@ -329,7 +494,7 @@ init_module(void)
}
#else
-__initfunc(int tc59x_probe(struct device *dev))
+int tc59x_probe(struct device *dev)
{
int cards_found = 0;
@@ -342,100 +507,148 @@ __initfunc(int tc59x_probe(struct device *dev))
}
#endif /* not MODULE */
-__initfunc(static int vortex_scan(struct device *dev))
+static int vortex_scan(struct device *dev)
{
int cards_found = 0;
-#ifdef CONFIG_PCI
+#ifndef NO_PCI /* Allow an EISA-only driver. */
+ /* Ideally we would detect all cards in slot order. That would
+ be best done a central PCI probe dispatch, which wouldn't work
+ well with the current structure. So instead we detect 3Com cards
+ in slot order. */
if (pcibios_present()) {
static int pci_index = 0;
- static int board_index = 0;
- for (; product_ids[board_index]; board_index++, pci_index = 0) {
- for (; pci_index < 16; pci_index++) {
- unsigned char pci_bus, pci_device_fn, pci_irq_line;
- unsigned char pci_latency;
- unsigned int pci_ioaddr;
- unsigned short pci_command;
-
- if (pcibios_find_device(TCOM_VENDOR_ID,
- product_ids[board_index], pci_index,
- &pci_bus, &pci_device_fn))
+ unsigned char pci_bus, pci_device_fn;
+
+ for (;pci_index < 0xff; pci_index++) {
+ unsigned char pci_irq_line, pci_latency;
+ unsigned short pci_command, vendor, device;
+ unsigned int pci_ioaddr;
+
+ int board_index = 0;
+ if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8,
+ pci_index, &pci_bus, &pci_device_fn)
+ != PCIBIOS_SUCCESSFUL)
+ break;
+ pcibios_read_config_word(pci_bus, pci_device_fn,
+ PCI_VENDOR_ID, &vendor);
+ pcibios_read_config_word(pci_bus, pci_device_fn,
+ PCI_DEVICE_ID, &device);
+ pcibios_read_config_byte(pci_bus, pci_device_fn,
+ PCI_INTERRUPT_LINE, &pci_irq_line);
+ pcibios_read_config_dword(pci_bus, pci_device_fn,
+ PCI_BASE_ADDRESS_0, &pci_ioaddr);
+ /* Remove I/O space marker in bit 0. */
+ pci_ioaddr &= ~3;
+
+ if (vendor != TCOM_VENDOR_ID)
+ continue;
+
+ for (board_index = 0; product_ids[board_index]; board_index++) {
+ if (device == product_ids[board_index])
break;
- pcibios_read_config_byte(pci_bus, pci_device_fn,
- PCI_INTERRUPT_LINE, &pci_irq_line);
- pcibios_read_config_dword(pci_bus, pci_device_fn,
- PCI_BASE_ADDRESS_0, &pci_ioaddr);
- /* Remove I/O space marker in bit 0. */
- pci_ioaddr &= ~3;
+ }
+ if (product_ids[board_index] == 0) {
+ printk("Unknown 3Com PCI ethernet adapter type %4.4x detected:"
+ " not configured.\n", device);
+ continue;
+ }
+ if (check_region(pci_ioaddr, VORTEX_TOTAL_SIZE))
+ continue;
-#ifdef VORTEX_BUS_MASTER
+ dev = vortex_found_device(dev, pci_ioaddr, pci_irq_line,
+ board_index, dev && dev->mem_start
+ ? dev->mem_start : options[cards_found],
+ cards_found);
+
+ if (dev) {
/* Get and check the bus-master and latency values.
Some PCI BIOSes fail to set the master-enable bit, and
the latency timer must be set to the maximum value to avoid
data corruption that occurs when the timer expires during
- a transfer. Yes, it's a bug. */
+ a transfer -- a bug in the Vortex chip. */
pcibios_read_config_word(pci_bus, pci_device_fn,
PCI_COMMAND, &pci_command);
if ( ! (pci_command & PCI_COMMAND_MASTER)) {
- printk(" PCI Master Bit has not been set! Setting...\n");
+ printk("%s: PCI Master Bit has not been set! "
+ " Setting...\n", dev->name);
pci_command |= PCI_COMMAND_MASTER;
pcibios_write_config_word(pci_bus, pci_device_fn,
PCI_COMMAND, pci_command);
}
pcibios_read_config_byte(pci_bus, pci_device_fn,
PCI_LATENCY_TIMER, &pci_latency);
- if (pci_latency != 255) {
- printk(" Overriding PCI latency timer (CFLT) setting of"
- " %d, new value is 255.\n", pci_latency);
+ if (pci_latency != 248) {
+ printk("%s: Overriding PCI latency"
+ " timer (CFLT) setting of %d, new value is 248.\n",
+ dev->name, pci_latency);
pcibios_write_config_byte(pci_bus, pci_device_fn,
- PCI_LATENCY_TIMER, 255);
+ PCI_LATENCY_TIMER, 248);
}
-#endif /* VORTEX_BUS_MASTER */
- vortex_found_device(dev, pci_ioaddr, pci_irq_line, board_index,
- dev && dev->mem_start ? dev->mem_start
- : options[cards_found]);
dev = 0;
cards_found++;
}
}
}
-#endif /* CONFIG_PCI */
+#endif /* NO_PCI */
/* Now check all slots of the EISA bus. */
if (EISA_bus) {
static int ioaddr = 0x1000;
for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
+ int product_id, product_index;
+ if (check_region(ioaddr, VORTEX_TOTAL_SIZE))
+ continue;
/* Check the standard EISA ID register for an encoded '3Com'. */
if (inw(ioaddr + 0xC80) != 0x6d50)
continue;
/* Check for a product that we support, 3c59{2,7} any rev. */
- if ((inw(ioaddr + 0xC82) & 0xF0FF) != 0x7059 /* 597 */
- && (inw(ioaddr + 0xC82) & 0xF0FF) != 0x2059) /* 592 */
+ product_id = inw(ioaddr + 0xC82) & 0xF0FF;
+ if (product_id == 0x7059) /* 597 */
+ product_index = DEMON100_INDEX;
+ else if (product_id == 0x2059) /* 592 */
+ product_index = DEMON10_INDEX;
+ else
continue;
vortex_found_device(dev, ioaddr, inw(ioaddr + 0xC88) >> 12,
- DEMON_INDEX, dev && dev->mem_start
- ? dev->mem_start : options[cards_found]);
+ product_index, dev && dev->mem_start
+ ? dev->mem_start : options[cards_found],
+ cards_found);
dev = 0;
cards_found++;
}
}
+ /* Special code to work-around the Compaq PCI BIOS32 problem. */
+ if (compaq_ioaddr) {
+ vortex_found_device(dev, compaq_ioaddr, compaq_irq, compaq_prod_id,
+ dev && dev->mem_start ? dev->mem_start
+ : options[cards_found], cards_found);
+ cards_found++;
+ dev = 0;
+ }
+
+ /* Finally check for a 3c515 on the ISA bus. */
+ /* (3c515 support omitted on this version.) */
+
return cards_found;
}
-__initfunc(static int vortex_found_device(struct device *dev, int ioaddr, int irq,
- int product_index, int options))
+static struct device *
+vortex_found_device(struct device *dev, int ioaddr, int irq,
+ int product_index, int options, int card_idx)
{
struct vortex_private *vp;
#ifdef MODULE
/* Allocate and fill new device structure. */
int dev_size = sizeof(struct device) +
- sizeof(struct vortex_private);
-
+ sizeof(struct vortex_private) + 15; /* Pad for alignment */
+
dev = (struct device *) kmalloc(dev_size, GFP_KERNEL);
memset(dev, 0, dev_size);
- dev->priv = ((void *)dev) + sizeof(struct device);
+ /* Align the Rx and Tx ring entries. */
+ dev->priv = (void *)(((long)dev + sizeof(struct device) + 15) & ~15);
vp = (struct vortex_private *)dev->priv;
dev->name = vp->devname; /* An empty string. */
dev->base_addr = ioaddr;
@@ -443,28 +656,36 @@ __initfunc(static int vortex_found_device(struct device *dev, int ioaddr, int ir
dev->init = vortex_probe1;
vp->product_name = product_names[product_index];
vp->options = options;
+ if (card_idx >= 0) {
+ if (full_duplex[card_idx] >= 0)
+ vp->full_duplex = full_duplex[card_idx];
+ } else
+ vp->full_duplex = (options >= 0 && (options & 0x10) ? 1 : 0);
+
if (options >= 0) {
- vp->media_override = ((options & 7) == 2) ? 0 : options & 7;
- vp->full_duplex = (options & 8) ? 1 : 0;
+ vp->media_override = ((options & 7) == XCVR_10baseTOnly) ?
+ XCVR_10baseT : options & 7;
vp->bus_master = (options & 16) ? 1 : 0;
} else {
vp->media_override = 7;
- vp->full_duplex = 0;
vp->bus_master = 0;
}
ether_setup(dev);
vp->next_module = root_vortex_dev;
root_vortex_dev = dev;
if (register_netdev(dev) != 0)
- return -EIO;
+ return 0;
#else /* not a MODULE */
if (dev) {
+ /* Caution: quad-word alignment required for rings! */
dev->priv = kmalloc(sizeof (struct vortex_private), GFP_KERNEL);
memset(dev->priv, 0, sizeof (struct vortex_private));
}
dev = init_etherdev(dev, sizeof(struct vortex_private));
dev->base_addr = ioaddr;
dev->irq = irq;
+ dev->mtu = mtu;
+
vp = (struct vortex_private *)dev->priv;
vp->product_name = product_names[product_index];
vp->options = options;
@@ -480,13 +701,14 @@ __initfunc(static int vortex_found_device(struct device *dev, int ioaddr, int ir
vortex_probe1(dev);
#endif /* MODULE */
- return 0;
+ return dev;
}
-__initfunc(static int vortex_probe1(struct device *dev))
+static int vortex_probe1(struct device *dev)
{
int ioaddr = dev->base_addr;
struct vortex_private *vp = (struct vortex_private *)dev->priv;
+ unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
int i;
printk("%s: 3Com %s at %#3x,", dev->name,
@@ -494,27 +716,33 @@ __initfunc(static int vortex_probe1(struct device *dev))
/* Read the station address from the EEPROM. */
EL3WINDOW(0);
- for (i = 0; i < 3; i++) {
+ for (i = 0; i < 0x18; i++) {
short *phys_addr = (short *)dev->dev_addr;
int timer;
- outw(EEPROM_Read + PhysAddr01 + i, ioaddr + Wn0EepromCmd);
+ outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd);
/* Pause for at least 162 us. for the read to take place. */
- for (timer = 162*4 + 400; timer >= 0; timer--) {
- udelay(1);
+ for (timer = 4; timer >= 0; timer--) {
+ udelay(162);
if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
break;
}
- phys_addr[i] = htons(inw(ioaddr + Wn0EepromData));
+ eeprom[i] = inw(ioaddr + Wn0EepromData);
+ checksum ^= eeprom[i];
+ if (i >= 10 && i < 13)
+ phys_addr[i - 10] = htons(inw(ioaddr + Wn0EepromData));
}
+ checksum = (checksum ^ (checksum >> 8)) & 0xff;
+ if (checksum != 0x00)
+ printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
for (i = 0; i < 6; i++)
printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
printk(", IRQ %d\n", dev->irq);
/* Tell them about an invalid IRQ. */
- if (vortex_debug && (dev->irq <= 0 || dev->irq > 15))
- printk(" *** Warning: this IRQ is unlikely to work!\n");
+ if (vortex_debug && (dev->irq <= 0 || dev->irq >= NR_IRQS))
+ printk(" *** Warning: this IRQ is unlikely to work! ***\n");
{
- char *ram_split[] = {"5:3", "3:1", "1:1", "invalid"};
+ char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
union wn3_config config;
EL3WINDOW(3);
vp->available_media = inw(ioaddr + Wn3_Options);
@@ -532,8 +760,46 @@ __initfunc(static int vortex_probe1(struct device *dev))
vp->default_media = config.u.xcvr;
vp->autoselect = config.u.autoselect;
}
+ if (vp->media_override != 7) {
+ printk(" Media override to transceiver type %d (%s).\n",
+ vp->media_override, media_tbl[vp->media_override].name);
+ dev->if_port = vp->media_override;
+ }
- /* We do a request_region() only to register /proc/ioports info. */
+ if (dev->if_port == XCVR_MII) {
+ int phy, phy_idx = 0;
+ EL3WINDOW(4);
+ for (phy = 0; phy < 32 && phy_idx < sizeof(vp->phys); phy++) {
+ int mii_status;
+ mdio_sync(ioaddr, 32);
+ mii_status = mdio_read(ioaddr, phy, 0);
+ if (mii_status != 0xffff) {
+ vp->phys[phy_idx++] = phy;
+ printk("%s: MII transceiver found at address %d.\n",
+ dev->name, phy);
+ mdio_sync(ioaddr, 32);
+ if ((mdio_read(ioaddr, phy, 1) & 0x0040) == 0)
+ mii_preamble_required = 1;
+ }
+ }
+ if (phy_idx == 0) {
+ printk("%s: ***WARNING*** No MII transceivers found!\n",
+ dev->name);
+ vp->phys[0] = 0;
+ }
+ }
+
+ vp->info1 = eeprom[13];
+ vp->info2 = eeprom[15];
+ vp->capabilities = eeprom[16];
+ if ((vp->capabilities & 0x20) && vp->bus_master) {
+ vp->full_bus_master_tx = 1;
+ printk(" Enabling bus-master transmits and %s receives.\n",
+ (vp->info2 & 1) ? "early" : "whole-frame" );
+ vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
+ }
+
+ /* We do a request_region() to register /proc/ioports info. */
request_region(ioaddr, VORTEX_TOTAL_SIZE, vp->product_name);
/* The 3c59x-specific entries in the device structure. */
@@ -541,10 +807,97 @@ __initfunc(static int vortex_probe1(struct device *dev))
dev->hard_start_xmit = &vortex_start_xmit;
dev->stop = &vortex_close;
dev->get_stats = &vortex_get_stats;
+#ifdef HAVE_PRIVATE_IOCTL
+ dev->do_ioctl = &vortex_ioctl;
+#endif
+#ifdef NEW_MULTICAST
dev->set_multicast_list = &set_rx_mode;
+#else
+ dev->set_multicast_list = &set_multicast_list;
+#endif
return 0;
}
+
+/* Read and write the MII registers using software-generated serial
+ MDIO protocol. The maxium data clock rate is 2.5 Mhz. */
+#define mdio_delay() udelay(1)
+
+#define MDIO_SHIFT_CLK 0x01
+#define MDIO_DIR_WRITE 0x04
+#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
+#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
+#define MDIO_DATA_READ 0x02
+#define MDIO_ENB_IN 0x00
+
+static void mdio_sync(int ioaddr, int bits)
+{
+ int mdio_addr = ioaddr + Wn4_PhysicalMgmt;
+
+ /* Establish sync by sending at least 32 logic ones. */
+ while (-- bits >= 0) {
+ outw(MDIO_DATA_WRITE1, mdio_addr);
+ mdio_delay();
+ outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+}
+static int mdio_read(int ioaddr, int phy_id, int location)
+{
+ int i;
+ int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
+ unsigned int retval = 0;
+ int mdio_addr = ioaddr + Wn4_PhysicalMgmt;
+
+ if (mii_preamble_required)
+ mdio_sync(ioaddr, 32);
+
+ /* Shift the read command bits out. */
+ for (i = 14; i >= 0; i--) {
+ int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
+ outw(dataval, mdio_addr);
+ mdio_delay();
+ outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ /* Read the two transition, 16 data, and wire-idle bits. */
+ for (i = 19; i > 0; i--) {
+ outw(MDIO_ENB_IN, mdio_addr);
+ mdio_delay();
+ retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
+ outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ return retval>>1 & 0xffff;
+}
+
+static void mdio_write(int ioaddr, int phy_id, int location, int value)
+{
+ int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
+ int mdio_addr = ioaddr + Wn4_PhysicalMgmt;
+ int i;
+
+ if (mii_preamble_required)
+ mdio_sync(ioaddr, 32);
+
+ /* Shift the command bits out. */
+ for (i = 31; i >= 0; i--) {
+ int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
+ outw(dataval, mdio_addr);
+ mdio_delay();
+ outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ /* Leave the interface idle. */
+ for (i = 1; i >= 0; i--) {
+ outw(MDIO_ENB_IN, mdio_addr);
+ mdio_delay();
+ outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+
+ return;
+}
static int
@@ -557,8 +910,6 @@ vortex_open(struct device *dev)
/* Before initializing select the active media port. */
EL3WINDOW(3);
- if (vp->full_duplex)
- outb(0x20, ioaddr + Wn3_MAC_Ctrl); /* Set the full-duplex bit. */
config.i = inl(ioaddr + Wn3_Config);
if (vp->media_override != 7) {
@@ -569,7 +920,7 @@ vortex_open(struct device *dev)
dev->if_port = vp->media_override;
} else if (vp->autoselect) {
/* Find first available media type, starting with 100baseTx. */
- dev->if_port = 4;
+ dev->if_port = XCVR_100baseTx;
while (! (vp->available_media & media_tbl[dev->if_port].mask))
dev->if_port = media_tbl[dev->if_port].next;
@@ -588,6 +939,30 @@ vortex_open(struct device *dev)
config.u.xcvr = dev->if_port;
outl(config.i, ioaddr + Wn3_Config);
+ if (dev->if_port == XCVR_MII) {
+ int mii_reg1, mii_reg5;
+ /* We cheat here: we know that we are using the 83840 transceiver
+ which summarizes the FD status in an extended register. */
+ EL3WINDOW(4);
+ /* Read BMSR (reg1) only to clear old status. */
+ mii_reg1 = mdio_read(ioaddr, vp->phys[0], 1);
+ mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5);
+ if (mii_reg5 == 0xffff || mii_reg5 == 0x0000)
+ ; /* No MII device or no link partner report */
+ else if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
+ || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
+ vp->full_duplex = 1;
+ if (vortex_debug > 1)
+ printk("%s: MII #%d status %4.4x, link partner capability %4.4x,"
+ " setting %s-duplex.\n", dev->name, vp->phys[0],
+ mii_reg1, mii_reg5, vp->full_duplex ? "full" : "half");
+ EL3WINDOW(3);
+ }
+
+ /* Set the full-duplex bit. */
+ outb(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
+ (dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl);
+
if (vortex_debug > 1) {
printk("%s: vortex_open() InternalConfig %8.8x.\n",
dev->name, config.i);
@@ -595,22 +970,32 @@ vortex_open(struct device *dev)
outw(TxReset, ioaddr + EL3_CMD);
for (i = 20; i >= 0 ; i--)
- if ( ! inw(ioaddr + EL3_STATUS) & CmdInProgress)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
break;
outw(RxReset, ioaddr + EL3_CMD);
/* Wait a few ticks for the RxReset command to complete. */
for (i = 20; i >= 0 ; i--)
- if ( ! inw(ioaddr + EL3_STATUS) & CmdInProgress)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
break;
outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
+#ifdef SA_SHIRQ
/* Use the now-standard shared IRQ implementation. */
if (request_irq(dev->irq, &vortex_interrupt, SA_SHIRQ,
vp->product_name, dev)) {
return -EAGAIN;
}
+#else
+ if (dev->irq == 0 || irq2dev_map[dev->irq] != NULL)
+ return -EAGAIN;
+ irq2dev_map[dev->irq] = dev;
+ if (request_irq(dev->irq, &vortex_interrupt, 0, vp->product_name)) {
+ irq2dev_map[dev->irq] = NULL;
+ return -EAGAIN;
+ }
+#endif
if (vortex_debug > 1) {
EL3WINDOW(4);
@@ -625,7 +1010,7 @@ vortex_open(struct device *dev)
for (; i < 12; i+=2)
outw(0, ioaddr + i);
- if (dev->if_port == 3)
+ if (dev->if_port == XCVR_10base2)
/* Start the thinnet transceiver. We should really wait 50ms...*/
outw(StartCoax, ioaddr + EL3_CMD);
EL3WINDOW(4);
@@ -635,18 +1020,52 @@ vortex_open(struct device *dev)
/* Switch to the stats window, and clear all stats by reading. */
outw(StatsDisable, ioaddr + EL3_CMD);
EL3WINDOW(6);
- for (i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
inb(ioaddr + i);
inw(ioaddr + 10);
inw(ioaddr + 12);
/* New: On the Vortex we must also clear the BadSSD counter. */
EL3WINDOW(4);
inb(ioaddr + 12);
+ /* ..and on the Boomerang we enable the extra statistics bits. */
+ outw(0x0040, ioaddr + Wn4_NetDiag);
/* Switch to register set 7 for normal use. */
EL3WINDOW(7);
- /* Set receiver mode: presumably accept b-case and phys addr only. */
+ if (vp->full_bus_master_rx) { /* Boomerang bus master. */
+ vp->cur_rx = vp->dirty_rx = 0;
+ /* Initialize the RxEarly register as recommended. */
+ outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
+ outl(0x0020, ioaddr + PktStatus);
+ if (vortex_debug > 2)
+ printk("%s: Filling in the Rx ring.\n", dev->name);
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ struct sk_buff *skb;
+ vp->rx_ring[i].next = virt_to_bus(&vp->rx_ring[i+1]);
+ vp->rx_ring[i].status = 0; /* Clear complete bit. */
+ vp->rx_ring[i].length = PKT_BUF_SZ | LAST_FRAG;
+ skb = dev_alloc_skb(PKT_BUF_SZ);
+ vp->rx_skbuff[i] = skb;
+ if (skb == NULL)
+ break; /* Bad news! */
+ skb->dev = dev; /* Mark as being used by this device. */
+ skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
+ vp->rx_ring[i].addr = virt_to_bus(skb->tail);
+ }
+ vp->rx_ring[i-1].next = virt_to_bus(&vp->rx_ring[0]); /* Wrap the ring. */
+ outl(virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr);
+ }
+ if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
+ dev->hard_start_xmit = &boomerang_start_xmit;
+ vp->cur_tx = vp->dirty_tx = 0;
+ outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
+ /* Clear the Tx ring. */
+ for (i = 0; i < TX_RING_SIZE; i++)
+ vp->tx_skbuff[i] = 0;
+ outl(0, ioaddr + DownListPtr);
+ }
+ /* Set reciever mode: presumably accept b-case and phys addr only. */
set_rx_mode(dev);
outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
@@ -657,12 +1076,18 @@ vortex_open(struct device *dev)
outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
/* Allow status bits to be seen. */
- outw(SetStatusEnb | 0xff, ioaddr + EL3_CMD);
+ outw(SetStatusEnb | AdapterFailure|IntReq|StatsFull|TxComplete|
+ (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
+ (vp->full_bus_master_rx ? UpComplete : RxComplete) |
+ (vp->bus_master ? DMADone : 0),
+ ioaddr + EL3_CMD);
/* Ack all pending events, and set active indicator mask. */
outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
ioaddr + EL3_CMD);
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
- | DMADone, ioaddr + EL3_CMD);
+ | AdapterFailure | TxComplete
+ | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete,
+ ioaddr + EL3_CMD);
MOD_INC_USE_COUNT;
@@ -688,7 +1113,7 @@ static void vortex_timer(unsigned long data)
EL3WINDOW(4);
media_status = inw(ioaddr + Wn4_Media);
switch (dev->if_port) {
- case 0: case 4: case 5: /* 10baseT, 100baseTX, 100baseFX */
+ case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
if (media_status & Media_LnkBeat) {
ok = 1;
if (vortex_debug > 1)
@@ -697,8 +1122,20 @@ static void vortex_timer(unsigned long data)
} else if (vortex_debug > 1)
printk("%s: Media %s is has no link beat, %x.\n",
dev->name, media_tbl[dev->if_port].name, media_status);
-
+
break;
+ case XCVR_MII:
+ {
+ int mii_reg1 = mdio_read(ioaddr, vp->phys[0], 1);
+ int mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5);
+ if (vortex_debug > 1)
+ printk("%s: MII #%d status register is %4.4x, "
+ "link partner capability %4.4x.\n",
+ dev->name, vp->phys[0], mii_reg1, mii_reg5);
+ if (mii_reg1 & 0x0004)
+ ok = 1;
+ break;
+ }
default: /* Other media types handled by Tx timeouts. */
if (vortex_debug > 1)
printk("%s: Media %s is has no indication, %x.\n",
@@ -711,7 +1148,7 @@ static void vortex_timer(unsigned long data)
do {
dev->if_port = media_tbl[dev->if_port].next;
} while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
- if (dev->if_port == 8) { /* Go back to default. */
+ if (dev->if_port == XCVR_Default) { /* Go back to default. */
dev->if_port = vp->default_media;
if (vortex_debug > 1)
printk("%s: Media selection failing, using default %s port.\n",
@@ -731,7 +1168,8 @@ static void vortex_timer(unsigned long data)
config.u.xcvr = dev->if_port;
outl(config.i, ioaddr + Wn3_Config);
- outw(dev->if_port == 3 ? StartCoax : StopCoax, ioaddr + EL3_CMD);
+ outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
+ ioaddr + EL3_CMD);
}
EL3WINDOW(old_window);
} restore_flags(flags);
@@ -743,66 +1181,118 @@ static void vortex_timer(unsigned long data)
return;
}
-static int
-vortex_start_xmit(struct sk_buff *skb, struct device *dev)
+static void vortex_tx_timeout(struct device *dev)
{
struct vortex_private *vp = (struct vortex_private *)dev->priv;
int ioaddr = dev->base_addr;
+ int i;
- /* Part of the following code is inspired by code from Giuseppe Ciaccio,
- ciaccio@disi.unige.it.
- It works around a ?bug? in the 8K Vortex that only occurs on some
- systems: the TxAvailable interrupt seems to be lost.
- The ugly work-around is to busy-wait for room available in the Tx
- buffer before deciding the transmitter is actually hung.
- This busy-wait should never really occur, since the problem is that
- there actually *is* room in the Tx FIFO.
-
- This pointed out an optimization -- we can ignore dev->tbusy if
- we actually have room for this packet.
- */
-
-#if 0
- /* unstable optimization */
- if (inw(ioaddr + TxFree) > skb->len) /* We actually have free room. */
- dev->tbusy = 0; /* Fake out the check below. */
- else
+ printk("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
+ dev->name, inb(ioaddr + TxStatus),
+ inw(ioaddr + EL3_STATUS));
+ /* Slight code bloat to be user friendly. */
+ if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
+ printk("%s: Transmitter encountered 16 collisions --"
+ " network cable problem?\n", dev->name);
+ if (inw(ioaddr + EL3_STATUS) & IntLatch) {
+ printk("%s: Interrupt posted but not handled --"
+ " IRQ blocked by another device?\n", dev->name);
+ /* Bad idea here.. but we might as well handle a few events. */
+ vortex_interrupt IRQ(dev->irq, dev, 0);
+ }
+#ifndef final_version
+ if (vp->full_bus_master_tx) {
+ printk(" Flags; bus-master %d, full %d; dirty %d current %d.\n",
+ vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx, vp->cur_tx);
+ printk(" Transmit list %8.8x vs. %p.\n", inl(ioaddr + DownListPtr),
+ &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ printk(" %d: @%p length %8.8x status %8.8x\n", i,
+ &vp->tx_ring[i],
+ vp->tx_ring[i].length,
+ vp->tx_ring[i].status);
+ }
+ }
+#ifdef notdef
+ if (vp->full_bus_master_rx) {
+ printk(" Switching to non-bus-master receives.\n");
+ outw(SetStatusEnb | AdapterFailure|IntReq|StatsFull |
+ (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
+ RxComplete | (vp->bus_master ? DMADone : 0),
+ ioaddr + EL3_CMD);
+ }
+ /* Issue TX_RESET and TX_START commands. */
+ outw(TxReset, ioaddr + EL3_CMD);
+ for (i = 20; i >= 0 ; i--)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
+ break;
#endif
- if (dev->tbusy) {
- /* Transmitter timeout, serious problems. */
- int tickssofar = jiffies - dev->trans_start;
- int i;
-
- if (tickssofar < 2) /* We probably aren't empty. */
- return 1;
- /* Wait a while to see if there really is room. */
- for (i = WAIT_TX_AVAIL; i >= 0; i--)
- if (inw(ioaddr + TxFree) > skb->len)
- break;
- if ( i < 0) {
- if (tickssofar < TX_TIMEOUT)
- return 1;
- printk("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
- dev->name, inb(ioaddr + TxStatus), inw(ioaddr + EL3_STATUS));
- /* Issue TX_RESET and TX_START commands. */
- outw(TxReset, ioaddr + EL3_CMD);
- for (i = 20; i >= 0 ; i--)
- if ( ! inw(ioaddr + EL3_STATUS) & CmdInProgress) break;
- outw(TxEnable, ioaddr + EL3_CMD);
- dev->trans_start = jiffies;
- dev->tbusy = 0;
- vp->stats.tx_errors++;
+#endif
+ if (vp->full_bus_master_tx) {
+ /* Change 6/25/97 Michael Sievers sieversm@mail.desy.de
+ The card has been resetted, but the Tx Ring is still full.
+ Since the card won't know where to resume, 'update' the
+ Tx Ring. Probably, we'll lose 16 packets this way, these
+ will be accounted for as 'dropped'. The code to update the
+ Tx Ring is taken from the Interrupt handler. */
+
+ unsigned int dirty_tx = vp->dirty_tx;
+
+ if (vortex_debug > 0)
+ printk("%s: Freeing Tx ring entries:", dev->name);
+ while (vp->cur_tx - dirty_tx > 0) {
+ int entry = dirty_tx % TX_RING_SIZE;
+ if (inl(ioaddr + DownListPtr) ==
+ virt_to_bus(&vp->tx_ring[entry]))
+ break; /* It still hasn't been processed. */
+ if (vp->tx_skbuff[entry]) {
+ if (vortex_debug > 0)
+ printk(" %d\n", entry);
+ dev_kfree_skb(vp->tx_skbuff[entry], FREE_WRITE);
+ vp->tx_skbuff[entry] = 0;
vp->stats.tx_dropped++;
- return 0; /* Yes, silently *drop* the packet! */
}
- dev->tbusy = 0;
+ if (vortex_debug > 0)
+ printk(".\n");
+ vp->stats.tx_errors++;
+ dirty_tx++;
+ }
+ vp->dirty_tx = dirty_tx;
+ vp->tx_full= 0;
+ } else { /* not bus-master, no Tx ring to clear */
+ vp->stats.tx_errors++;
+ vp->stats.tx_dropped++;
}
+
+ /* Issue Tx Enable */
+ outw(TxEnable, ioaddr + EL3_CMD);
+ dev->trans_start = jiffies;
+
+ /* Switch to register set 7 for normal use. */
+ EL3WINDOW(7);
+
+ /* The TxFreeThreshold has to be set again after a reset! */
+ if (vp->full_bus_master_tx) {
+ outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
+ /* This is to be sure that all bus-master Tx features
+ are correctly re-initialized after a reset, although
+ the DownListPtr should already be 0 at this point. */
+ outl(0, ioaddr + DownListPtr);
+ }
+ /* finally, allow new Transmits */
+ dev->tbusy = 0;
+ /* End of Michael Sievers <sieversm@mail.desy.de> changes. */
+}
+
+static int
+vortex_start_xmit(struct sk_buff *skb, struct device *dev)
+{
+ struct vortex_private *vp = (struct vortex_private *)dev->priv;
+ int ioaddr = dev->base_addr;
- /* Block a timer-based transmit from overlapping. This could better be
- done with atomic_swap(1, dev->tbusy), but set_bit() works as well.
- If this ever occurs the queue layer is doing something evil! */
if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
- printk("%s: Transmitter access conflict.\n", dev->name);
+ if (jiffies - dev->trans_start >= TX_TIMEOUT)
+ vortex_tx_timeout(dev);
return 1;
}
@@ -855,7 +1345,7 @@ vortex_start_xmit(struct sk_buff *skb, struct device *dev)
int j;
outw(TxReset, ioaddr + EL3_CMD);
for (j = 20; j >= 0 ; j--)
- if ( ! inw(ioaddr + EL3_STATUS) & CmdInProgress)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
break;
}
outw(TxEnable, ioaddr + EL3_CMD);
@@ -866,16 +1356,80 @@ vortex_start_xmit(struct sk_buff *skb, struct device *dev)
return 0;
}
+static int
+boomerang_start_xmit(struct sk_buff *skb, struct device *dev)
+{
+ struct vortex_private *vp = (struct vortex_private *)dev->priv;
+ int ioaddr = dev->base_addr;
+
+ if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
+ if (jiffies - dev->trans_start >= TX_TIMEOUT)
+ vortex_tx_timeout(dev);
+ return 1;
+ } else {
+ /* Calculate the next Tx descriptor entry. */
+ int entry = vp->cur_tx % TX_RING_SIZE;
+ struct boom_tx_desc *prev_entry =
+ &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
+ unsigned long flags;
+ int i;
+
+ if (vortex_debug > 3)
+ printk("%s: Trying to send a packet, Tx index %d.\n",
+ dev->name, vp->cur_tx);
+ if (vp->tx_full) {
+ if (vortex_debug >0)
+ printk("%s: Tx Ring full, refusing to send buffer.\n",
+ dev->name);
+ return 1;
+ }
+ /* end change 06/25/97 M. Sievers */
+ vp->tx_skbuff[entry] = skb;
+ vp->tx_ring[entry].next = 0;
+ vp->tx_ring[entry].addr = virt_to_bus(skb->data);
+ vp->tx_ring[entry].length = skb->len | LAST_FRAG;
+ vp->tx_ring[entry].status = skb->len | TxIntrUploaded;
+
+ save_flags(flags);
+ cli();
+ outw(DownStall, ioaddr + EL3_CMD);
+ /* Wait for the stall to complete. */
+ for (i = 60; i >= 0 ; i--)
+ if ( (inw(ioaddr + EL3_STATUS) & CmdInProgress) == 0)
+ break;
+ prev_entry->next = virt_to_bus(&vp->tx_ring[entry]);
+ if (inl(ioaddr + DownListPtr) == 0) {
+ outl(virt_to_bus(&vp->tx_ring[entry]), ioaddr + DownListPtr);
+ queued_packet++;
+ }
+ outw(DownUnstall, ioaddr + EL3_CMD);
+ restore_flags(flags);
+
+ vp->cur_tx++;
+ if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1)
+ vp->tx_full = 1;
+ else { /* Clear previous interrupt enable. */
+ prev_entry->status &= ~TxIntrUploaded;
+ dev->tbusy = 0;
+ }
+ dev->trans_start = jiffies;
+ return 0;
+ }
+}
+
/* The interrupt handler does all of the Rx thread work and cleans up
after the Tx thread. */
static void vortex_interrupt IRQ(int irq, void *dev_id, struct pt_regs *regs)
{
- /* Use the now-standard shared IRQ implementation. */
+#ifdef SA_SHIRQ /* Use the now-standard shared IRQ implementation. */
struct device *dev = dev_id;
+#else
+ struct device *dev = (struct device *)(irq2dev_map[irq]);
+#endif
struct vortex_private *lp;
int ioaddr, status;
int latency;
- int i = 0;
+ int i = max_interrupt_work;
if (dev->interrupt)
printk("%s: Re-entering the interrupt handler.\n", dev->name);
@@ -890,17 +1444,20 @@ static void vortex_interrupt IRQ(int irq, void *dev_id, struct pt_regs *regs)
if (vortex_debug > 4)
printk("%s: interrupt, status %4.4x, timer %d.\n", dev->name,
status, latency);
- if ((status & 0xE000) != 0xE000) {
+#ifdef notdef
+ /* This code guard against bogus hangs, but fails with shared IRQs. */
+ if ((status & ~0xE000) == 0x0000) {
static int donedidthis=0;
/* Some interrupt controllers store a bogus interrupt from boot-time.
Ignore a single early interrupt, but don't hang the machine for
other interrupt problems. */
- if (donedidthis++ > 1) {
+ if (donedidthis++ > 100) {
printk("%s: Bogus interrupt, bailing. Status %4.4x, start=%d.\n",
dev->name, status, dev->start);
FREE_IRQ(dev->irq, dev);
}
}
+#endif
do {
if (vortex_debug > 5)
@@ -917,13 +1474,53 @@ static void vortex_interrupt IRQ(int irq, void *dev_id, struct pt_regs *regs)
dev->tbusy = 0;
mark_bh(NET_BH);
}
+ if (status & TxComplete) { /* Really "TxError" for us. */
+ unsigned char tx_status = inb(ioaddr + TxStatus);
+ /* Presumably a tx-timeout. We must merely re-enable. */
+ if (vortex_debug > 2
+ || (tx_status != 0x88 && vortex_debug > 0))
+ printk("%s: Transmit error, Tx status register %2.2x.\n",
+ dev->name, tx_status);
+ if (tx_status & 0x04) lp->stats.tx_fifo_errors++;
+ if (tx_status & 0x38) lp->stats.tx_aborted_errors++;
+ outb(0, ioaddr + TxStatus);
+ outw(TxEnable, ioaddr + EL3_CMD);
+ }
+ if (status & DownComplete) {
+ unsigned int dirty_tx = lp->dirty_tx;
+
+ while (lp->cur_tx - dirty_tx > 0) {
+ int entry = dirty_tx % TX_RING_SIZE;
+ if (inl(ioaddr + DownListPtr) ==
+ virt_to_bus(&lp->tx_ring[entry]))
+ break; /* It still hasn't been processed. */
+ if (lp->tx_skbuff[entry]) {
+ dev_kfree_skb(lp->tx_skbuff[entry], FREE_WRITE);
+ lp->tx_skbuff[entry] = 0;
+ }
+ /* lp->stats.tx_packets++; Counted below. */
+ dirty_tx++;
+ }
+ lp->dirty_tx = dirty_tx;
+ outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
+ if (lp->tx_full && (lp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) {
+ lp->tx_full= 0;
+ dev->tbusy = 0;
+ mark_bh(NET_BH);
+ }
+ }
#ifdef VORTEX_BUS_MASTER
if (status & DMADone) {
outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
dev->tbusy = 0;
+ dev_kfree_skb (lp->tx_skb, FREE_WRITE); /* Release the transfered buffer */
mark_bh(NET_BH);
}
#endif
+ if (status & UpComplete) {
+ boomerang_rx(dev);
+ outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
+ }
if (status & (AdapterFailure | RxEarly | StatsFull)) {
/* Handle all uncommon interrupts at once. */
if (status & RxEarly) { /* Rx early is unused. */
@@ -949,27 +1546,45 @@ static void vortex_interrupt IRQ(int irq, void *dev_id, struct pt_regs *regs)
printk(" %2.2x", inb(ioaddr+reg));
}
EL3WINDOW(7);
- outw(SetIntrEnb | 0x18, ioaddr + EL3_CMD);
+ outw(SetIntrEnb | TxAvailable | RxComplete | AdapterFailure
+ | UpComplete | DownComplete | TxComplete,
+ ioaddr + EL3_CMD);
DoneDidThat++;
}
}
if (status & AdapterFailure) {
- /* Adapter failure requires Rx reset and reinit. */
- outw(RxReset, ioaddr + EL3_CMD);
- /* Set the Rx filter to the current state. */
- set_rx_mode(dev);
- outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
- outw(AckIntr | AdapterFailure, ioaddr + EL3_CMD);
+ u16 fifo_diag;
+ EL3WINDOW(4);
+ fifo_diag = inw(ioaddr + Wn4_FIFODiag);
+ if (vortex_debug > 0)
+ printk("%s: Host error, FIFO diagnostic register %4.4x.\n",
+ dev->name, fifo_diag);
+ /* Adapter failure requires Tx/Rx reset and reinit. */
+ if (fifo_diag & 0x0400) {
+ int j;
+ outw(TxReset, ioaddr + EL3_CMD);
+ for (j = 20; j >= 0 ; j--)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
+ break;
+ outw(TxEnable, ioaddr + EL3_CMD);
+ }
+ if (fifo_diag & 0x2000) {
+ outw(RxReset, ioaddr + EL3_CMD);
+ /* Set the Rx filter to the current state. */
+ set_rx_mode(dev);
+ outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
+ outw(AckIntr | AdapterFailure, ioaddr + EL3_CMD);
+ }
}
}
- if (++i > 10) {
- printk("%s: Infinite loop in interrupt, status %4.4x. "
+ if (--i < 0) {
+ printk("%s: Too much work in interrupt, status %4.4x. "
"Disabling functions (%4.4x).\n",
- dev->name, status, SetStatusEnb | ((~status) & 0xFE));
+ dev->name, status, SetStatusEnb | ((~status) & 0x7FE));
/* Disable all pending interrupts. */
- outw(SetStatusEnb | ((~status) & 0xFE), ioaddr + EL3_CMD);
- outw(AckIntr | 0xFF, ioaddr + EL3_CMD);
+ outw(SetStatusEnb | ((~status) & 0x7FE), ioaddr + EL3_CMD);
+ outw(AckIntr | 0x7FF, ioaddr + EL3_CMD);
break;
}
/* Acknowledge the IRQ. */
@@ -998,7 +1613,7 @@ vortex_rx(struct device *dev)
while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
if (rx_status & 0x4000) { /* Error, update stats. */
unsigned char rx_error = inb(ioaddr + RxErrors);
- if (vortex_debug > 4)
+ if (vortex_debug > 2)
printk(" Rx error: status %2.2x.\n", rx_error);
vp->stats.rx_errors++;
if (rx_error & 0x01) vp->stats.rx_over_errors++;
@@ -1017,28 +1632,36 @@ vortex_rx(struct device *dev)
pkt_len, rx_status);
if (skb != NULL) {
skb->dev = dev;
+#if LINUX_VERSION_CODE >= 0x10300
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
/* 'skb_put()' points to the start of sk_buff data area. */
insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
(pkt_len + 3) >> 2);
+ outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
skb->protocol = eth_type_trans(skb, dev);
- netif_rx(skb);
+#else
+ skb->len = pkt_len;
+ /* 'skb->data' points to the start of sk_buff data area. */
+ insl(ioaddr + RX_FIFO, skb->data, (pkt_len + 3) >> 2);
outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
+#endif /* KERNEL_1_3_0 */
+ netif_rx(skb);
+ dev->last_rx = jiffies;
+ vp->stats.rx_packets++;
/* Wait a limited time to go to next packet. */
for (i = 200; i >= 0; i--)
- if ( ! inw(ioaddr + EL3_STATUS) & CmdInProgress)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
break;
- vp->stats.rx_packets++;
continue;
} else if (vortex_debug)
printk("%s: Couldn't allocate a sk_buff of size %d.\n",
dev->name, pkt_len);
}
- vp->stats.rx_dropped++;
outw(RxDiscard, ioaddr + EL3_CMD);
+ vp->stats.rx_dropped++;
/* Wait a limited time to skip this packet. */
for (i = 200; i >= 0; i--)
- if ( ! inw(ioaddr + EL3_STATUS) & CmdInProgress)
+ if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
break;
}
@@ -1046,17 +1669,111 @@ vortex_rx(struct device *dev)
}
static int
+boomerang_rx(struct device *dev)
+{
+ struct vortex_private *vp = (struct vortex_private *)dev->priv;
+ int entry = vp->cur_rx % RX_RING_SIZE;
+ int ioaddr = dev->base_addr;
+ int rx_status;
+
+ if (vortex_debug > 5)
+ printk(" In boomerang_rx(), status %4.4x, rx_status %4.4x.\n",
+ inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
+ while ((rx_status = vp->rx_ring[entry].status) & RxDComplete) {
+ if (rx_status & RxDError) { /* Error, update stats. */
+ unsigned char rx_error = rx_status >> 16;
+ if (vortex_debug > 2)
+ printk(" Rx error: status %2.2x.\n", rx_error);
+ vp->stats.rx_errors++;
+ if (rx_error & 0x01) vp->stats.rx_over_errors++;
+ if (rx_error & 0x02) vp->stats.rx_length_errors++;
+ if (rx_error & 0x04) vp->stats.rx_frame_errors++;
+ if (rx_error & 0x08) vp->stats.rx_crc_errors++;
+ if (rx_error & 0x10) vp->stats.rx_length_errors++;
+ } else {
+ /* The packet length: up to 4.5K!. */
+ short pkt_len = rx_status & 0x1fff;
+ struct sk_buff *skb;
+
+ if (vortex_debug > 4)
+ printk("Receiving packet size %d status %4.4x.\n",
+ pkt_len, rx_status);
+
+ /* Check if the packet is long enough to just accept without
+ copying to a properly sized skbuff. */
+ if (pkt_len < rx_copybreak
+ && (skb = DEV_ALLOC_SKB(pkt_len + 2)) != 0) {
+ skb->dev = dev;
+ skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
+ /* 'skb_put()' points to the start of sk_buff data area. */
+ memcpy(skb_put(skb, pkt_len),
+ bus_to_virt(vp->rx_ring[entry].addr),
+ pkt_len);
+ rx_copy++;
+ } else{
+ void *temp;
+ /* Pass up the skbuff already on the Rx ring. */
+ skb = vp->rx_skbuff[entry];
+ vp->rx_skbuff[entry] = NULL;
+ temp = skb_put(skb, pkt_len);
+ /* Remove this checking code for final release. */
+ if (bus_to_virt(vp->rx_ring[entry].addr) != temp)
+ printk("%s: Warning -- the skbuff addresses do not match"
+ " in boomerang_rx: %p vs. %p / %p.\n", dev->name,
+ bus_to_virt(vp->rx_ring[entry].addr),
+ skb->head, temp);
+ rx_nocopy++;
+ }
+#if LINUX_VERSION_CODE > 0x10300
+ skb->protocol = eth_type_trans(skb, dev);
+#else
+ skb->len = pkt_len;
+#endif
+ netif_rx(skb);
+ dev->last_rx = jiffies;
+ vp->stats.rx_packets++;
+ }
+ entry = (++vp->cur_rx) % RX_RING_SIZE;
+ }
+ /* Refill the Rx ring buffers. */
+ for (; vp->dirty_rx < vp->cur_rx; vp->dirty_rx++) {
+ struct sk_buff *skb;
+ entry = vp->dirty_rx % RX_RING_SIZE;
+ if (vp->rx_skbuff[entry] == NULL) {
+ skb = dev_alloc_skb(PKT_BUF_SZ);
+ if (skb == NULL)
+ break; /* Bad news! */
+ skb->dev = dev; /* Mark as being used by this device. */
+#if LINUX_VERSION_CODE > 0x10300
+ skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
+ vp->rx_ring[entry].addr = virt_to_bus(skb->tail);
+#else
+ vp->rx_ring[entry].addr = virt_to_bus(skb->data);
+#endif
+ vp->rx_skbuff[entry] = skb;
+ }
+ vp->rx_ring[entry].status = 0; /* Clear complete bit. */
+ }
+ return 0;
+}
+
+static int
vortex_close(struct device *dev)
{
struct vortex_private *vp = (struct vortex_private *)dev->priv;
int ioaddr = dev->base_addr;
+ int i;
dev->start = 0;
dev->tbusy = 1;
- if (vortex_debug > 1)
+ if (vortex_debug > 1) {
printk("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus));
+ printk("%s: vortex close stats: rx_nocopy %d rx_copy %d"
+ " tx_queued %d.\n",
+ dev->name, rx_nocopy, rx_copy, queued_packet);
+ }
del_timer(&vp->timer);
@@ -1067,27 +1784,57 @@ vortex_close(struct device *dev)
outw(RxDisable, ioaddr + EL3_CMD);
outw(TxDisable, ioaddr + EL3_CMD);
- if (dev->if_port == 3)
+ if (dev->if_port == XCVR_10base2)
/* Turn off thinnet power. Green! */
outw(StopCoax, ioaddr + EL3_CMD);
- FREE_IRQ(dev->irq, dev);
+#ifdef SA_SHIRQ
+ free_irq(dev->irq, dev);
+#else
+ free_irq(dev->irq);
+ irq2dev_map[dev->irq] = 0;
+#endif
+
+ outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
update_stats(ioaddr, dev);
+ if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
+ outl(0, ioaddr + UpListPtr);
+ for (i = 0; i < RX_RING_SIZE; i++)
+ if (vp->rx_skbuff[i]) {
+#if LINUX_VERSION_CODE < 0x20100
+ vp->rx_skbuff[i]->free = 1;
+#endif
+ dev_kfree_skb (vp->rx_skbuff[i], FREE_WRITE);
+ vp->rx_skbuff[i] = 0;
+ }
+ }
+ if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
+ outl(0, ioaddr + DownListPtr);
+ for (i = 0; i < TX_RING_SIZE; i++)
+ if (vp->tx_skbuff[i]) {
+ dev_kfree_skb(vp->tx_skbuff[i], FREE_WRITE);
+ vp->tx_skbuff[i] = 0;
+ }
+ }
+
MOD_DEC_USE_COUNT;
return 0;
}
-static struct net_device_stats *vortex_get_stats(struct device *dev)
+static struct enet_statistics *
+vortex_get_stats(struct device *dev)
{
struct vortex_private *vp = (struct vortex_private *)dev->priv;
unsigned long flags;
- save_flags(flags);
- cli();
- update_stats(dev->base_addr, dev);
- restore_flags(flags);
+ if (dev->start) {
+ save_flags(flags);
+ cli();
+ update_stats(dev->base_addr, dev);
+ restore_flags(flags);
+ }
return &vp->stats;
}
@@ -1129,6 +1876,37 @@ static void update_stats(int ioaddr, struct device *dev)
return;
}
+#ifdef HAVE_PRIVATE_IOCTL
+static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd)
+{
+ struct vortex_private *vp = (struct vortex_private *)dev->priv;
+ int ioaddr = dev->base_addr;
+ u16 *data = (u16 *)&rq->ifr_data;
+ int phy = vp->phys[0] & 0x1f;
+
+ if (vortex_debug > 2)
+ printk("%s: In ioct(%-.6s, %#4.4x) %4.4x %4.4x %4.4x %4.4x.\n",
+ dev->name, rq->ifr_ifrn.ifrn_name, cmd,
+ data[0], data[1], data[2], data[3]);
+
+ switch(cmd) {
+ case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
+ data[0] = phy;
+ case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
+ EL3WINDOW(4);
+ data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f);
+ return 0;
+ case SIOCDEVPRIVATE+2: /* Write the specified MII register */
+ if (!suser())
+ return -EPERM;
+ mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+#endif /* HAVE_PRIVATE_IOCTL */
+
/* This new version of set_rx_mode() supports v1.4 kernels.
The Vortex chip has no documented multicast filter, so the only
multicast setting is to receive all multicast frames. At least
@@ -1145,11 +1923,19 @@ set_rx_mode(struct device *dev)
new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
} else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
- } else
+ } else
new_mode = SetRxFilter | RxStation | RxBroadcast;
outw(new_mode, ioaddr + EL3_CMD);
}
+#ifndef NEW_MULTICAST
+/* The old interface to set the Rx mode. */
+static void
+set_multicast_list(struct device *dev, int num_addrs, void *addrs)
+{
+ set_rx_mode(dev);
+}
+#endif
#ifdef MODULE
void
@@ -1167,12 +1953,15 @@ cleanup_module(void)
root_vortex_dev = next_dev;
}
}
-#endif /* MODULE */
+
+#endif /* MODULE */
/*
* Local variables:
- * compile-command: "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c 3c59x.c -o ../../modules/3c59x.o"
+ * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c"
* c-indent-level: 4
+ * c-basic-offset: 4
* tab-width: 4
* End:
*/
+
diff --git a/drivers/net/Config.in b/drivers/net/Config.in
index 603657a85..f53d758d2 100644
--- a/drivers/net/Config.in
+++ b/drivers/net/Config.in
@@ -181,7 +181,6 @@ if [ "$CONFIG_WAN_ROUTER" != "n" ]; then
bool ' WANPIPE Frame Relay support' CONFIG_WANPIPE_FR
bool ' WANPIPE PPP support' CONFIG_WANPIPE_PPP
fi
- dep_tristate 'High-speed (DMA) SCC driver for AX.25' CONFIG_DMASCC $CONFIG_AX25
fi
fi
#
diff --git a/drivers/net/eth16i.c b/drivers/net/eth16i.c
index fa5ae74e4..dbf0f3beb 100644
--- a/drivers/net/eth16i.c
+++ b/drivers/net/eth16i.c
@@ -265,7 +265,7 @@ static char *version =
/* Macro to slow down io between EEPROM clock transitions */
-#define eeprom_slow_io() do { int _i = 40; while(--_i > 0) { __SLOW_DOWN_IO; }}while(0)
+#define eeprom_slow_io() udelay(100) /* FIXME: smaller but right value here */
/* Jumperless Configuration Register (BMPR19) */
#define JUMPERLESS_CONFIG 19
diff --git a/drivers/net/hamradio/Config.in b/drivers/net/hamradio/Config.in
index 94a86238f..85434e502 100644
--- a/drivers/net/hamradio/Config.in
+++ b/drivers/net/hamradio/Config.in
@@ -26,6 +26,7 @@ if [ "$CONFIG_HAMRADIO" != "n" ] ; then
# tristate 'Serial port 6PACK driver' CONFIG_6PACK
tristate 'BPQ Ethernet driver' CONFIG_BPQETHER
+ tristate 'High-speed (DMA) SCC driver for AX.25' CONFIG_DMASCC $CONFIG_AX25
tristate 'Z8530 SCC driver' CONFIG_SCC
if [ "$CONFIG_SCC" != "n" ]; then
bool ' additional delay for PA0HZP OptoSCC compatible boards' CONFIG_SCC_DELAY
diff --git a/drivers/net/hamradio/dmascc.c b/drivers/net/hamradio/dmascc.c
new file mode 100644
index 000000000..33b473d32
--- /dev/null
+++ b/drivers/net/hamradio/dmascc.c
@@ -0,0 +1,1260 @@
+/*
+ * $Id: dmascc.c,v 1.2 1997/12/02 16:49:49 oe1kib Exp $
+ *
+ * Driver for high-speed SCC boards (those with DMA support)
+ * Copyright (C) 1997 Klaus Kudielka
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <linux/module.h>
+#include <linux/dmascc.h>
+#include <linux/errno.h>
+#include <linux/if_arp.h>
+#include <linux/in.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/netdevice.h>
+#include <linux/sockios.h>
+#include <linux/tqueue.h>
+#include <linux/version.h>
+#include <asm/atomic.h>
+#include <asm/bitops.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/segment.h>
+#include <asm/uaccess.h>
+#include <net/ax25.h>
+#include <stdio.h>
+#include "z8530.h"
+
+
+/* Number of buffers per channel */
+
+#define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (2 recommended) */
+#define NUM_RX_BUF 2 /* NUM_RX_BUF >= 1 (2 recommended) */
+#define BUF_SIZE 2016
+
+
+/* Cards supported */
+
+#define HW_PI { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
+ 0, 8, 1843200, 3686400 }
+#define HW_PI2 { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
+ 0, 8, 3686400, 7372800 }
+#define HW_TWIN { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
+ 0, 4, 6144000, 6144000 }
+
+#define HARDWARE { HW_PI, HW_PI2, HW_TWIN }
+
+#define TYPE_PI 0
+#define TYPE_PI2 1
+#define TYPE_TWIN 2
+#define NUM_TYPES 3
+
+#define MAX_NUM_DEVS 32
+
+
+/* SCC chips supported */
+
+#define Z8530 0
+#define Z85C30 1
+#define Z85230 2
+
+#define CHIPNAMES { "Z8530", "Z85C30", "Z85230" }
+
+
+/* I/O registers */
+
+/* 8530 registers relative to card base */
+#define SCCB_CMD 0x00
+#define SCCB_DATA 0x01
+#define SCCA_CMD 0x02
+#define SCCA_DATA 0x03
+
+/* 8254 registers relative to card base */
+#define TMR_CNT0 0x00
+#define TMR_CNT1 0x01
+#define TMR_CNT2 0x02
+#define TMR_CTRL 0x03
+
+/* Additional PI/PI2 registers relative to card base */
+#define PI_DREQ_MASK 0x04
+
+/* Additional PackeTwin registers relative to card base */
+#define TWIN_INT_REG 0x08
+#define TWIN_CLR_TMR1 0x09
+#define TWIN_CLR_TMR2 0x0a
+#define TWIN_SPARE_1 0x0b
+#define TWIN_DMA_CFG 0x08
+#define TWIN_SERIAL_CFG 0x09
+#define TWIN_DMA_CLR_FF 0x0a
+#define TWIN_SPARE_2 0x0b
+
+
+/* PackeTwin I/O register values */
+
+/* INT_REG */
+#define TWIN_SCC_MSK 0x01
+#define TWIN_TMR1_MSK 0x02
+#define TWIN_TMR2_MSK 0x04
+#define TWIN_INT_MSK 0x07
+
+/* SERIAL_CFG */
+#define TWIN_DTRA_ON 0x01
+#define TWIN_DTRB_ON 0x02
+#define TWIN_EXTCLKA 0x04
+#define TWIN_EXTCLKB 0x08
+#define TWIN_LOOPA_ON 0x10
+#define TWIN_LOOPB_ON 0x20
+#define TWIN_EI 0x80
+
+/* DMA_CFG */
+#define TWIN_DMA_HDX_T1 0x08
+#define TWIN_DMA_HDX_R1 0x0a
+#define TWIN_DMA_HDX_T3 0x14
+#define TWIN_DMA_HDX_R3 0x16
+#define TWIN_DMA_FDX_T3R1 0x1b
+#define TWIN_DMA_FDX_T1R3 0x1d
+
+
+/* Status values */
+
+/* tx_state */
+#define TX_IDLE 0
+#define TX_OFF 1
+#define TX_TXDELAY 2
+#define TX_ACTIVE 3
+#define TX_SQDELAY 4
+
+
+/* Data types */
+
+struct scc_hardware {
+ char *name;
+ int io_region;
+ int io_delta;
+ int io_size;
+ int num_devs;
+ int scc_offset;
+ int tmr_offset;
+ int tmr_hz;
+ int pclk_hz;
+};
+
+struct scc_priv {
+ char name[10];
+ struct enet_statistics stats;
+ struct scc_info *info;
+ int channel;
+ int cmd, data, tmr;
+ struct scc_param param;
+ char rx_buf[NUM_RX_BUF][BUF_SIZE];
+ int rx_len[NUM_RX_BUF];
+ int rx_ptr;
+ struct tq_struct rx_task;
+ int rx_head, rx_tail, rx_count;
+ int rx_over;
+ char tx_buf[NUM_TX_BUF][BUF_SIZE];
+ int tx_len[NUM_TX_BUF];
+ int tx_ptr;
+ int tx_head, tx_tail, tx_count;
+ int tx_sem, tx_state;
+ unsigned long tx_start;
+ int status;
+};
+
+struct scc_info {
+ int type;
+ int chip;
+ int open;
+ int scc_base;
+ int tmr_base;
+ int twin_serial_cfg;
+ struct device dev[2];
+ struct scc_priv priv[2];
+ struct scc_info *next;
+};
+
+
+/* Function declarations */
+
+int dmascc_init(void) __init;
+static int setup_adapter(int io, int h, int n) __init;
+
+static inline void write_scc(int ctl, int reg, int val);
+static inline int read_scc(int ctl, int reg);
+static int scc_open(struct device *dev);
+static int scc_close(struct device *dev);
+static int scc_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
+static int scc_send_packet(struct sk_buff *skb, struct device *dev);
+static struct enet_statistics *scc_get_stats(struct device *dev);
+static int scc_set_mac_address(struct device *dev, void *sa);
+static void scc_isr(int irq, void *dev_id, struct pt_regs * regs);
+static inline void z8530_isr(struct scc_info *info);
+static void rx_isr(struct device *dev);
+static void special_condition(struct device *dev, int rc);
+static void rx_bh(void *arg);
+static void tx_isr(struct device *dev);
+static void es_isr(struct device *dev);
+static void tm_isr(struct device *dev);
+static inline void delay(struct device *dev, int t);
+static inline unsigned char random(void);
+
+
+/* Initialization variables */
+
+static int io[MAX_NUM_DEVS] __initdata = { 0, };
+/* Beware! hw[] is also used in cleanup_module(). If __initdata also applies
+ to modules, we may not declare hw[] as __initdata */
+static struct scc_hardware hw[NUM_TYPES] __initdata = HARDWARE;
+static char ax25_broadcast[7] __initdata =
+ { 'Q'<<1, 'S'<<1, 'T'<<1, ' '<<1, ' '<<1, ' '<<1, '0'<<1 };
+static char ax25_test[7] __initdata =
+ { 'L'<<1, 'I'<<1, 'N'<<1, 'U'<<1, 'X'<<1, ' '<<1, '1'<<1 };
+
+
+/* Global variables */
+
+static struct scc_info *first = NULL;
+static unsigned long rand;
+
+
+
+/* Module functions */
+
+#ifdef MODULE
+
+
+MODULE_AUTHOR("Klaus Kudielka <oe1kib@oe1xtu.ampr.org>");
+MODULE_DESCRIPTION("Driver for high-speed SCC boards");
+MODULE_PARM(io, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");
+
+
+int init_module(void)
+{
+ return dmascc_init();
+}
+
+
+void cleanup_module(void)
+{
+ int i;
+ struct scc_info *info;
+
+ while (first) {
+ info = first;
+
+ /* Unregister devices */
+ for (i = 0; i < 2; i++) {
+ if (info->dev[i].name)
+ unregister_netdev(&info->dev[i]);
+ }
+
+ /* Reset board */
+ if (info->type == TYPE_TWIN)
+ outb_p(0, info->dev[0].base_addr + TWIN_SERIAL_CFG);
+ write_scc(info->priv[0].cmd, R9, FHWRES);
+ release_region(info->dev[0].base_addr,
+ hw[info->type].io_size);
+
+ /* Free memory */
+ first = info->next;
+ kfree_s(info, sizeof(struct scc_info));
+ }
+}
+
+
+#else
+
+
+__initfunc(void dmascc_setup(char *str, int *ints))
+{
+ int i;
+
+ for (i = 0; i < MAX_NUM_DEVS && i < ints[0]; i++)
+ io[i] = ints[i+1];
+}
+
+
+#endif
+
+
+/* Initialization functions */
+
+__initfunc(int dmascc_init(void))
+{
+ int h, i, j, n, base[MAX_NUM_DEVS], tcmd, t0, t1, status;
+ unsigned long time, start[MAX_NUM_DEVS], stop[MAX_NUM_DEVS];
+
+ /* Initialize random number generator */
+ rand = jiffies;
+
+ /* Cards found = 0 */
+ n = 0;
+
+ /* Run autodetection for each card type */
+ for (h = 0; h < NUM_TYPES; h++) {
+
+ if (io[0]) {
+ /* User-specified I/O address regions */
+ for (i = 0; i < hw[h].num_devs; i++) base[i] = 0;
+ for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
+ j = (io[i] - hw[h].io_region) / hw[h].io_delta;
+ if (j >= 0 &&
+ j < hw[h].num_devs &&
+ hw[h].io_region + j * hw[h].io_delta == io[i])
+ base[j] = io[i];
+ }
+ } else {
+ /* Default I/O address regions */
+ for (i = 0; i < hw[h].num_devs; i++)
+ base[i] = hw[h].io_region + i * hw[h].io_delta;
+ }
+
+ /* Check valid I/O address regions */
+ for (i = 0; i < hw[h].num_devs; i++)
+ if (base[i] && check_region(base[i], hw[h].io_size))
+ base[i] = 0;
+
+ /* Start timers */
+ for (i = 0; i < hw[h].num_devs; i++)
+ if (base[i]) {
+ tcmd = base[i] + hw[h].tmr_offset + TMR_CTRL;
+ t0 = base[i] + hw[h].tmr_offset + TMR_CNT0;
+ t1 = base[i] + hw[h].tmr_offset + TMR_CNT1;
+ /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
+ outb_p(0x36, tcmd);
+ outb_p((hw[h].tmr_hz/TMR_0_HZ) & 0xFF, t0);
+ outb_p((hw[h].tmr_hz/TMR_0_HZ) >> 8, t0);
+ /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
+ outb_p(0x70, tcmd);
+ outb_p((TMR_0_HZ/HZ*10) & 0xFF, t1);
+ outb_p((TMR_0_HZ/HZ*10) >> 8, t1);
+ /* Timer 2: LSB+MSB, Mode 0 */
+ outb_p(0xb0, tcmd);
+ }
+
+ /* Initialize start values in case we miss the null count bit */
+ time = jiffies;
+ for (i = 0; i < hw[h].num_devs; i++) start[i] = time;
+
+ /* Timing loop */
+ while (jiffies - time < 12) {
+ for (i = 0; i < hw[h].num_devs; i++)
+ if (base[i]) {
+ /* Read back Timer 1: Status */
+ outb_p(0xE4, base[i] + hw[h].tmr_offset + TMR_CTRL);
+ status = inb_p(base[i] + hw[h].tmr_offset + TMR_CNT1);
+ if ((status & 0x3F) != 0x30) base[i] = 0;
+ if (status & 0x40) start[i] = jiffies;
+ if (~status & 0x80) stop[i] = jiffies;
+ }
+ }
+
+ /* Evaluate measurements */
+ for (i = 0; i < hw[h].num_devs; i++)
+ if (base[i]) {
+ time = stop[i] - start[i];
+ if (time < 9 || time > 11)
+ /* The time expired doesn't match */
+ base[i] = 0;
+ else {
+ /* Ok, we have found an adapter */
+ if (setup_adapter(base[i], h, n) == 0)
+ n++;
+ }
+ }
+
+ } /* NUM_TYPES */
+
+ /* If any adapter was successfully initialized, return ok */
+ if (n) return 0;
+
+ /* If no adapter found, return error */
+ printk("dmascc: no adapters found\n");
+ return -EIO;
+}
+
+
+__initfunc(int setup_adapter(int io, int h, int n))
+{
+ int i, irq, chip;
+ struct scc_info *info;
+ struct device *dev;
+ struct scc_priv *priv;
+ unsigned long time;
+ unsigned int irqs;
+ int tmr = io + hw[h].tmr_offset;
+ int scc = io + hw[h].scc_offset;
+ int cmd = scc + SCCA_CMD;
+ char *chipnames[] = CHIPNAMES;
+
+ /* Reset 8530 */
+ write_scc(cmd, R9, FHWRES | MIE | NV);
+
+ /* Determine type of chip */
+ write_scc(cmd, R15, 1);
+ if (!read_scc(cmd, R15)) {
+ /* WR7' not present. This is an ordinary Z8530 SCC. */
+ chip = Z8530;
+ } else {
+ /* Put one character in TX FIFO */
+ write_scc(cmd, R8, 0);
+ if (read_scc(cmd, R0) & Tx_BUF_EMP) {
+ /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
+ chip = Z85230;
+ } else {
+ /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
+ chip = Z85C30;
+ }
+ }
+ write_scc(cmd, R15, 0);
+
+ /* Start IRQ auto-detection */
+ sti();
+ irqs = probe_irq_on();
+
+ /* Enable interrupts */
+ switch (h) {
+ case TYPE_PI:
+ case TYPE_PI2:
+ outb_p(0, io + PI_DREQ_MASK);
+ write_scc(cmd, R15, CTSIE);
+ write_scc(cmd, R0, RES_EXT_INT);
+ write_scc(cmd, R1, EXT_INT_ENAB);
+ break;
+ case TYPE_TWIN:
+ outb_p(0, io + TWIN_DMA_CFG);
+ inb_p(io + TWIN_CLR_TMR1);
+ inb_p(io + TWIN_CLR_TMR2);
+ outb_p(TWIN_EI, io + TWIN_SERIAL_CFG);
+ break;
+ }
+
+ /* Start timer */
+ outb_p(1, tmr + TMR_CNT1);
+ outb_p(0, tmr + TMR_CNT1);
+ /* Wait and detect IRQ */
+ time = jiffies; while (jiffies - time < 2 + HZ / TMR_0_HZ);
+ irq = probe_irq_off(irqs);
+
+ /* Clear pending interrupt, disable interrupts */
+ switch (h) {
+ case TYPE_PI:
+ case TYPE_PI2:
+ write_scc(cmd, R1, 0);
+ write_scc(cmd, R15, 0);
+ write_scc(cmd, R0, RES_EXT_INT);
+ break;
+ case TYPE_TWIN:
+ inb_p(io + TWIN_CLR_TMR1);
+ outb_p(0, io + TWIN_SERIAL_CFG);
+ break;
+ }
+
+ if (irq <= 0) {
+ printk("dmascc: could not find irq of %s at %#3x (irq=%d)\n",
+ hw[h].name, io, irq);
+ return -1;
+ }
+
+ /* Allocate memory */
+ info = kmalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
+ if (!info) {
+ printk("dmascc: could not allocate memory for %s at %#3x\n",
+ hw[h].name, io);
+ return -1;
+ }
+
+ /* Set up data structures */
+ memset(info, 0, sizeof(struct scc_info));
+ info->type = h;
+ info->chip = chip;
+ info->scc_base = io + hw[h].scc_offset;
+ info->tmr_base = io + hw[h].tmr_offset;
+ info->twin_serial_cfg = 0;
+ for (i = 0; i < 2; i++) {
+ dev = &info->dev[i];
+ priv = &info->priv[i];
+ sprintf(priv->name, "dmascc%i", 2*n+i);
+ priv->info = info;
+ priv->channel = i;
+ priv->cmd = info->scc_base + (i ? SCCB_CMD : SCCA_CMD);
+ priv->data = info->scc_base + (i ? SCCB_DATA : SCCA_DATA);
+ priv->tmr = info->tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
+ priv->param.pclk_hz = hw[h].pclk_hz;
+ priv->param.brg_tc = -1;
+ priv->param.clocks = TCTRxCP | RCRTxCP;
+ priv->param.txdelay = TMR_0_HZ * 10 / 1000;
+ priv->param.txtime = HZ * 3;
+ priv->param.sqdelay = TMR_0_HZ * 1 / 1000;
+ priv->param.slottime = TMR_0_HZ * 10 / 1000;
+ priv->param.waittime = TMR_0_HZ * 100 / 1000;
+ priv->param.persist = 32;
+ priv->rx_task.routine = rx_bh;
+ priv->rx_task.data = dev;
+ dev->priv = priv;
+ dev->name = priv->name;
+ dev->base_addr = io;
+ dev->irq = irq;
+ dev->open = scc_open;
+ dev->stop = scc_close;
+ dev->do_ioctl = scc_ioctl;
+ dev->hard_start_xmit = scc_send_packet;
+ dev->get_stats = scc_get_stats;
+ dev->hard_header = ax25_encapsulate;
+ dev->rebuild_header = ax25_rebuild_header;
+ dev->set_mac_address = scc_set_mac_address;
+ dev->type = ARPHRD_AX25;
+ dev->hard_header_len = 73;
+ dev->mtu = 1500;
+ dev->addr_len = 7;
+ dev->tx_queue_len = 64;
+ memcpy(dev->broadcast, ax25_broadcast, 7);
+ memcpy(dev->dev_addr, ax25_test, 7);
+ dev->flags = 0;
+ dev_init_buffers(dev);
+ if (register_netdev(dev)) {
+ printk("dmascc: could not register %s\n", dev->name);
+ dev->name = NULL;
+ }
+ }
+
+ request_region(io, hw[h].io_size, "dmascc");
+
+ info->next = first;
+ first = info;
+ printk("dmascc: found %s (%s) at %#3x, irq %d\n", hw[h].name,
+ chipnames[chip], io, irq);
+ return 0;
+}
+
+
+/* Driver functions */
+
+static inline void write_scc(int ctl, int reg, int val)
+{
+ outb_p(reg, ctl);
+ outb_p(val, ctl);
+}
+
+
+static inline int read_scc(int ctl, int reg)
+{
+ outb_p(reg, ctl);
+ return inb_p(ctl);
+}
+
+
+static int scc_open(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ struct scc_info *info = priv->info;
+ int io = dev->base_addr;
+ int cmd = priv->cmd;
+
+ /* Request IRQ if not already used by other channel */
+ if (!info->open) {
+ if (request_irq(dev->irq, scc_isr, SA_INTERRUPT, "dmascc", info))
+ return -EAGAIN;
+ }
+
+ /* Request DMA if required */
+ if (dev->dma && request_dma(dev->dma, "dmascc")) {
+ if (!info->open) free_irq(dev->irq, info);
+ return -EAGAIN;
+ }
+
+ /* Initialize local variables */
+ dev->tbusy = 0;
+ priv->rx_ptr = 0;
+ priv->rx_over = 0;
+ priv->rx_head = priv->rx_tail = priv->rx_count = 0;
+ priv->tx_state = TX_IDLE;
+ priv->tx_head = priv->tx_tail = priv->tx_count = 0;
+ priv->tx_ptr = 0;
+ priv->tx_sem = 0;
+
+ /* Reset channel */
+ write_scc(cmd, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
+ /* X1 clock, SDLC mode */
+ write_scc(cmd, R4, SDLC | X1CLK);
+ /* DMA */
+ write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN);
+ /* 8 bit RX char, RX disable */
+ write_scc(cmd, R3, Rx8);
+ /* 8 bit TX char, TX disable */
+ write_scc(cmd, R5, Tx8);
+ /* SDLC address field */
+ write_scc(cmd, R6, 0);
+ /* SDLC flag */
+ write_scc(cmd, R7, FLAG);
+ switch (info->chip) {
+ case Z85C30:
+ /* Select WR7' */
+ write_scc(cmd, R15, 1);
+ /* Auto EOM reset */
+ write_scc(cmd, R7, 0x02);
+ write_scc(cmd, R15, 0);
+ break;
+ case Z85230:
+ /* Select WR7' */
+ write_scc(cmd, R15, 1);
+ /* RX FIFO half full (interrupt only), Auto EOM reset,
+ TX FIFO empty (DMA only) */
+ write_scc(cmd, R7, dev->dma ? 0x22 : 0x0a);
+ write_scc(cmd, R15, 0);
+ break;
+ }
+ /* Preset CRC, NRZ(I) encoding */
+ write_scc(cmd, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
+
+ /* Configure baud rate generator */
+ if (priv->param.brg_tc >= 0) {
+ /* Program BR generator */
+ write_scc(cmd, R12, priv->param.brg_tc & 0xFF);
+ write_scc(cmd, R13, (priv->param.brg_tc>>8) & 0xFF);
+ /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
+ PackeTwin, not connected on the PI2); set DPLL source to BRG */
+ write_scc(cmd, R14, SSBR | DTRREQ | BRSRC | BRENABL);
+ /* Enable DPLL */
+ write_scc(cmd, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
+ } else {
+ /* Disable BR generator */
+ write_scc(cmd, R14, DTRREQ | BRSRC);
+ }
+
+ /* Configure clocks */
+ if (info->type == TYPE_TWIN) {
+ /* Disable external TX clock receiver */
+ outb_p((info->twin_serial_cfg &=
+ ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
+ io + TWIN_SERIAL_CFG);
+ }
+ write_scc(cmd, R11, priv->param.clocks);
+ if ((info->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
+ /* Enable external TX clock receiver */
+ outb_p((info->twin_serial_cfg |=
+ (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
+ io + TWIN_SERIAL_CFG);
+ }
+
+ /* Configure PackeTwin */
+ if (info->type == TYPE_TWIN) {
+ /* Assert DTR, enable interrupts */
+ outb_p((info->twin_serial_cfg |= TWIN_EI |
+ (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
+ io + TWIN_SERIAL_CFG);
+ }
+
+ /* Read current status */
+ priv->status = read_scc(cmd, R0);
+ /* Enable SYNC, DCD, and CTS interrupts */
+ write_scc(cmd, R15, DCDIE | CTSIE | SYNCIE);
+
+ /* Configure PI2 DMA */
+ if (info->type <= TYPE_PI2) outb_p(1, io + PI_DREQ_MASK);
+
+ dev->start = 1;
+ info->open++;
+ MOD_INC_USE_COUNT;
+
+ return 0;
+}
+
+
+static int scc_close(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ struct scc_info *info = priv->info;
+ int io = dev->base_addr;
+ int cmd = priv->cmd;
+
+ dev->start = 0;
+ info->open--;
+ MOD_DEC_USE_COUNT;
+
+ if (info->type == TYPE_TWIN)
+ /* Drop DTR */
+ outb_p((info->twin_serial_cfg &=
+ (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
+ io + TWIN_SERIAL_CFG);
+
+ /* Reset channel, free DMA */
+ write_scc(cmd, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
+ if (dev->dma) {
+ if (info->type == TYPE_TWIN) outb_p(0, io + TWIN_DMA_CFG);
+ free_dma(dev->dma);
+ }
+
+ if (!info->open) {
+ if (info->type <= TYPE_PI2) outb_p(0, io + PI_DREQ_MASK);
+ free_irq(dev->irq, info);
+ }
+ return 0;
+}
+
+
+static int scc_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
+{
+ int rc;
+ struct scc_priv *priv = dev->priv;
+
+ switch (cmd) {
+ case SIOCGSCCPARAM:
+ rc = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct scc_param));
+ if (rc) return rc;
+ copy_to_user(ifr->ifr_data, &priv->param, sizeof(struct scc_param));
+ return 0;
+ case SIOCSSCCPARAM:
+ if (!suser()) return -EPERM;
+ rc = verify_area(VERIFY_READ, ifr->ifr_data, sizeof(struct scc_param));
+ if (rc) return rc;
+ if (dev->start) return -EAGAIN;
+ copy_from_user(&priv->param, ifr->ifr_data, sizeof(struct scc_param));
+ dev->dma = priv->param.dma;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+
+static int scc_send_packet(struct sk_buff *skb, struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ struct scc_info *info = priv->info;
+ int cmd = priv->cmd;
+ unsigned long flags;
+ int i;
+
+ /* Block a timer-based transmit from overlapping */
+ if (test_and_set_bit(0, (void *) &priv->tx_sem) != 0) {
+ atomic_inc((void *) &priv->stats.tx_dropped);
+ dev_kfree_skb(skb, FREE_WRITE);
+ return 0;
+ }
+
+ /* Return with an error if we cannot accept more data */
+ if (dev->tbusy) {
+ priv->tx_sem = 0;
+ return -1;
+ }
+
+ /* Transfer data to DMA buffer */
+ i = priv->tx_head;
+ memcpy(priv->tx_buf[i], skb->data+1, skb->len-1);
+ priv->tx_len[i] = skb->len-1;
+
+ save_flags(flags);
+ cli();
+
+ /* Set the busy flag if we just filled up the last buffer */
+ priv->tx_head = (i + 1) % NUM_TX_BUF;
+ priv->tx_count++;
+ if (priv->tx_count == NUM_TX_BUF) dev->tbusy = 1;
+
+ /* Set new TX state */
+ if (priv->tx_state == TX_IDLE) {
+ /* Assert RTS, start timer */
+ priv->tx_state = TX_TXDELAY;
+ if (info->type <= TYPE_PI2) outb_p(0, dev->base_addr + PI_DREQ_MASK);
+ write_scc(cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
+ if (info->type <= TYPE_PI2) outb_p(1, dev->base_addr + PI_DREQ_MASK);
+ priv->tx_start = jiffies;
+ delay(dev, priv->param.txdelay);
+ }
+
+ restore_flags(flags);
+
+ dev_kfree_skb(skb, FREE_WRITE);
+
+ priv->tx_sem = 0;
+ return 0;
+}
+
+
+static struct enet_statistics *scc_get_stats(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+
+ return &priv->stats;
+}
+
+
+static int scc_set_mac_address(struct device *dev, void *sa)
+{
+ memcpy(dev->dev_addr, ((struct sockaddr *)sa)->sa_data, dev->addr_len);
+ return 0;
+}
+
+
+static void scc_isr(int irq, void *dev_id, struct pt_regs * regs)
+{
+ struct scc_info *info = dev_id;
+ int is, io = info->dev[0].base_addr;
+
+ /* We're a fast IRQ handler and are called with interrupts disabled */
+
+ /* IRQ sharing doesn't make sense due to ISA's edge-triggered
+ interrupts, hence it is safe to return if we have found and
+ processed a single device. */
+
+ /* Interrupt processing: We loop until we know that the IRQ line is
+ low. If another positive edge occurs afterwards during the ISR,
+ another interrupt will be triggered by the interrupt controller
+ as soon as the IRQ level is enabled again (see asm/irq.h). */
+
+ switch (info->type) {
+ case TYPE_PI:
+ case TYPE_PI2:
+ outb_p(0, io + PI_DREQ_MASK);
+ z8530_isr(info);
+ outb_p(1, io + PI_DREQ_MASK);
+ return;
+ case TYPE_TWIN:
+ while ((is = ~inb_p(io + TWIN_INT_REG)) &
+ TWIN_INT_MSK) {
+ if (is & TWIN_SCC_MSK) {
+ z8530_isr(info);
+ } else if (is & TWIN_TMR1_MSK) {
+ inb_p(io + TWIN_CLR_TMR1);
+ tm_isr(&info->dev[0]);
+ } else {
+ inb_p(io + TWIN_CLR_TMR2);
+ tm_isr(&info->dev[1]);
+ }
+ }
+ /* No interrupts pending from the PackeTwin */
+ return;
+ }
+}
+
+
+static inline void z8530_isr(struct scc_info *info)
+{
+ int is, a_cmd;
+
+ a_cmd = info->scc_base + SCCA_CMD;
+
+ while ((is = read_scc(a_cmd, R3))) {
+ if (is & CHARxIP) {
+ rx_isr(&info->dev[0]);
+ } else if (is & CHATxIP) {
+ tx_isr(&info->dev[0]);
+ } else if (is & CHAEXT) {
+ es_isr(&info->dev[0]);
+ } else if (is & CHBRxIP) {
+ rx_isr(&info->dev[1]);
+ } else if (is & CHBTxIP) {
+ tx_isr(&info->dev[1]);
+ } else {
+ es_isr(&info->dev[1]);
+ }
+ }
+ /* Ok, no interrupts pending from this 8530. The INT line should
+ be inactive now. */
+}
+
+
+static void rx_isr(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ int cmd = priv->cmd;
+
+ if (dev->dma) {
+ /* Check special condition and perform error reset. See 2.4.7.5. */
+ special_condition(dev, read_scc(cmd, R1));
+ write_scc(cmd, R0, ERR_RES);
+ } else {
+ /* Check special condition for each character. Error reset not necessary.
+ Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
+ int rc;
+ while (read_scc(cmd, R0) & Rx_CH_AV) {
+ rc = read_scc(cmd, R1);
+ if (priv->rx_ptr < BUF_SIZE)
+ priv->rx_buf[priv->rx_head][priv->rx_ptr++] = read_scc(cmd, R8);
+ else {
+ priv->rx_over = 2;
+ read_scc(cmd, R8);
+ }
+ special_condition(dev, rc);
+ }
+ }
+}
+
+
+static void special_condition(struct device *dev, int rc)
+{
+ struct scc_priv *priv = dev->priv;
+ int cb, cmd = priv->cmd;
+
+ /* See Figure 2-15. Only overrun and EOF need to be checked. */
+
+ if (rc & Rx_OVR) {
+ /* Receiver overrun */
+ priv->rx_over = 1;
+ if (!dev->dma) write_scc(cmd, R0, ERR_RES);
+ } else if (rc & END_FR) {
+ /* End of frame. Get byte count */
+ if (dev->dma) {
+ disable_dma(dev->dma);
+ clear_dma_ff(dev->dma);
+ cb = BUF_SIZE - get_dma_residue(dev->dma) - 2;
+ } else {
+ cb = priv->rx_ptr - 2;
+ }
+ if (priv->rx_over) {
+ /* We had an overrun */
+ priv->stats.rx_errors++;
+ if (priv->rx_over == 2) priv->stats.rx_length_errors++;
+ else priv->stats.rx_fifo_errors++;
+ priv->rx_over = 0;
+ } else if (rc & CRC_ERR) {
+ /* Count invalid CRC only if packet length >= minimum */
+ if (cb >= 8) {
+ priv->stats.rx_errors++;
+ priv->stats.rx_crc_errors++;
+ }
+ } else {
+ if (cb >= 8) {
+ /* Put good frame in FIFO */
+ priv->rx_len[priv->rx_head] = cb;
+ priv->rx_head = (priv->rx_head + 1) % NUM_RX_BUF;
+ priv->rx_count++;
+ if (priv->rx_count == NUM_RX_BUF) {
+ /* Disable receiver if FIFO full */
+ write_scc(cmd, R3, Rx8);
+ priv->stats.rx_errors++;
+ priv->stats.rx_over_errors++;
+ }
+ /* Mark bottom half handler */
+ queue_task(&priv->rx_task, &tq_immediate);
+ mark_bh(IMMEDIATE_BH);
+ }
+ }
+ /* Get ready for new frame */
+ if (dev->dma) {
+ set_dma_addr(dev->dma, (int) priv->rx_buf[priv->rx_head]);
+ set_dma_count(dev->dma, BUF_SIZE);
+ enable_dma(dev->dma);
+ } else {
+ priv->rx_ptr = 0;
+ }
+ }
+}
+
+
+static void rx_bh(void *arg)
+{
+ struct device *dev = arg;
+ struct scc_priv *priv = dev->priv;
+ struct scc_info *info = priv->info;
+ int cmd = priv->cmd;
+ int i = priv->rx_tail;
+ int cb;
+ unsigned long flags;
+ struct sk_buff *skb;
+ unsigned char *data;
+
+ save_flags(flags);
+ cli();
+
+ while (priv->rx_count) {
+ restore_flags(flags);
+ cb = priv->rx_len[i];
+ /* Allocate buffer */
+ skb = dev_alloc_skb(cb+1);
+ if (skb == NULL) {
+ /* Drop packet */
+ priv->stats.rx_dropped++;
+ } else {
+ /* Fill buffer */
+ data = skb_put(skb, cb+1);
+ data[0] = 0;
+ memcpy(&data[1], priv->rx_buf[i], cb);
+ skb->dev = dev;
+ skb->protocol = ntohs(ETH_P_AX25);
+ skb->mac.raw = skb->data;
+ netif_rx(skb);
+ priv->stats.rx_packets++;
+ }
+ save_flags(flags);
+ cli();
+ /* Enable receiver if RX buffers have been unavailable */
+ if ((priv->rx_count == NUM_RX_BUF) && (priv->status & DCD)) {
+ if (info->type <= TYPE_PI2) outb_p(0, dev->base_addr + PI_DREQ_MASK);
+ write_scc(cmd, R3, RxENABLE | Rx8 | RxCRC_ENAB);
+ if (info->type <= TYPE_PI2) outb_p(1, dev->base_addr + PI_DREQ_MASK);
+ }
+ /* Move tail */
+ priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
+ priv->rx_count--;
+ }
+
+ restore_flags(flags);
+}
+
+
+static void tx_isr(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ int cmd = priv->cmd;
+ int i = priv->tx_tail, p = priv->tx_ptr;
+
+ /* Suspend TX interrupts if we don't want to send anything.
+ See Figure 2-22. */
+ if (p == priv->tx_len[i]) {
+ write_scc(cmd, R0, RES_Tx_P);
+ return;
+ }
+
+ /* Write characters */
+ while ((read_scc(cmd, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
+ write_scc(cmd, R8, priv->tx_buf[i][p++]);
+ }
+ priv->tx_ptr = p;
+
+}
+
+
+static void es_isr(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ struct scc_info *info = priv->info;
+ int i, cmd = priv->cmd;
+ int st, dst, res;
+
+ /* Read status and reset interrupt bit */
+ st = read_scc(cmd, R0);
+ write_scc(cmd, R0, RES_EXT_INT);
+ dst = priv->status ^ st;
+ priv->status = st;
+
+ /* Since the EOM latch is reset automatically, we assume that
+ it has been zero if and only if we are in the TX_ACTIVE state.
+ Otherwise we follow 2.4.9.6. */
+
+ /* Transmit underrun */
+ if ((priv->tx_state == TX_ACTIVE) && (st & TxEOM)) {
+ /* Get remaining bytes */
+ i = priv->tx_tail;
+ if (dev->dma) {
+ disable_dma(dev->dma);
+ clear_dma_ff(dev->dma);
+ res = get_dma_residue(dev->dma);
+ } else {
+ res = priv->tx_len[i] - priv->tx_ptr;
+ if (res) write_scc(cmd, R0, RES_Tx_P);
+ priv->tx_ptr = 0;
+ }
+ /* Remove frame from FIFO */
+ priv->tx_tail = (i + 1) % NUM_TX_BUF;
+ priv->tx_count--;
+ dev->tbusy = 0;
+ /* Check if another frame is available and we are allowed to transmit */
+ if (priv->tx_count && (jiffies - priv->tx_start) < priv->param.txtime) {
+ if (dev->dma) {
+ set_dma_addr(dev->dma, (int) priv->tx_buf[priv->tx_tail]);
+ set_dma_count(dev->dma, priv->tx_len[priv->tx_tail]);
+ enable_dma(dev->dma);
+ } else {
+ /* If we have an ESCC, we are allowed to write data bytes
+ immediately. Otherwise we have to wait for the next
+ TX interrupt. See Figure 2-22. */
+ if (info->chip == Z85230) {
+ tx_isr(dev);
+ }
+ }
+ } else {
+ /* No frame available. Disable interrupts. */
+ priv->tx_state = TX_SQDELAY;
+ delay(dev, priv->param.sqdelay);
+ write_scc(cmd, R15, DCDIE | CTSIE | SYNCIE);
+ write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN);
+ }
+ /* Update packet statistics */
+ if (res) {
+ priv->stats.tx_errors++;
+ priv->stats.tx_fifo_errors++;
+ } else {
+ priv->stats.tx_packets++;
+ }
+ /* Inform upper layers */
+ mark_bh(NET_BH);
+ }
+
+ /* DCD transition */
+ if ((priv->tx_state < TX_TXDELAY) && (dst & DCD)) {
+ /* Transmitter state change */
+ priv->tx_state = TX_OFF;
+ /* Enable or disable receiver */
+ if (st & DCD) {
+ if (dev->dma) {
+ /* Program DMA controller */
+ disable_dma(dev->dma);
+ clear_dma_ff(dev->dma);
+ set_dma_mode(dev->dma, DMA_MODE_READ);
+ set_dma_addr(dev->dma, (int) priv->rx_buf[priv->rx_head]);
+ set_dma_count(dev->dma, BUF_SIZE);
+ enable_dma(dev->dma);
+ /* Configure PackeTwin DMA */
+ if (info->type == TYPE_TWIN) {
+ outb_p((dev->dma == 1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
+ dev->base_addr + TWIN_DMA_CFG);
+ }
+ /* Sp. cond. intr. only, ext int enable */
+ write_scc(cmd, R1, EXT_INT_ENAB | INT_ERR_Rx |
+ WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
+ } else {
+ /* Intr. on all Rx characters and Sp. cond., ext int enable */
+ write_scc(cmd, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
+ WT_FN_RDYFN);
+ }
+ if (priv->rx_count < NUM_RX_BUF) {
+ /* Enable receiver */
+ write_scc(cmd, R3, RxENABLE | Rx8 | RxCRC_ENAB);
+ }
+ } else {
+ /* Disable DMA */
+ if (dev->dma) disable_dma(dev->dma);
+ /* Disable receiver */
+ write_scc(cmd, R3, Rx8);
+ /* DMA disable, RX int disable, Ext int enable */
+ write_scc(cmd, R1, EXT_INT_ENAB | WT_RDY_RT | WT_FN_RDYFN);
+ /* Transmitter state change */
+ if (random() > priv->param.persist)
+ delay(dev, priv->param.slottime);
+ else {
+ if (priv->tx_count) {
+ priv->tx_state = TX_TXDELAY;
+ write_scc(cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
+ priv->tx_start = jiffies;
+ delay(dev, priv->param.txdelay);
+ } else {
+ priv->tx_state = TX_IDLE;
+ }
+ }
+ }
+ }
+
+ /* CTS transition */
+ if ((info->type <= TYPE_PI2) && (dst & CTS) && (~st & CTS)) {
+ /* Timer has expired */
+ tm_isr(dev);
+ }
+
+ /* /SYNC/HUNT transition */
+ if ((dst & SYNC_HUNT) && (~st & SYNC_HUNT)) {
+ /* Reset current frame and clear RX FIFO */
+ while (read_scc(cmd, R0) & Rx_CH_AV) read_scc(cmd, R8);
+ priv->rx_over = 0;
+ if (dev->dma) {
+ disable_dma(dev->dma);
+ clear_dma_ff(dev->dma);
+ set_dma_addr(dev->dma, (int) priv->rx_buf[priv->rx_head]);
+ set_dma_count(dev->dma, BUF_SIZE);
+ enable_dma(dev->dma);
+ } else {
+ priv->rx_ptr = 0;
+ }
+ }
+}
+
+
+static void tm_isr(struct device *dev)
+{
+ struct scc_priv *priv = dev->priv;
+ struct scc_info *info = priv->info;
+ int cmd = priv->cmd;
+
+ switch (priv->tx_state) {
+ case TX_OFF:
+ if (~priv->status & DCD) {
+ if (random() > priv->param.persist) delay(dev, priv->param.slottime);
+ else {
+ if (priv->tx_count) {
+ priv->tx_state = TX_TXDELAY;
+ write_scc(cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
+ priv->tx_start = jiffies;
+ delay(dev, priv->param.txdelay);
+ } else {
+ priv->tx_state = TX_IDLE;
+ }
+ }
+ }
+ break;
+ case TX_TXDELAY:
+ priv->tx_state = TX_ACTIVE;
+ if (dev->dma) {
+ /* Program DMA controller */
+ disable_dma(dev->dma);
+ clear_dma_ff(dev->dma);
+ set_dma_mode(dev->dma, DMA_MODE_WRITE);
+ set_dma_addr(dev->dma, (int) priv->tx_buf[priv->tx_tail]);
+ set_dma_count(dev->dma, priv->tx_len[priv->tx_tail]);
+ enable_dma(dev->dma);
+ /* Configure PackeTwin DMA */
+ if (info->type == TYPE_TWIN) {
+ outb_p((dev->dma == 1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
+ dev->base_addr + TWIN_DMA_CFG);
+ }
+ /* Enable interrupts and DMA. On the PackeTwin, the DTR//REQ pin
+ is used for TX DMA requests, but we enable the WAIT/DMA request
+ pin, anyway */
+ write_scc(cmd, R15, TxUIE | DCDIE | CTSIE | SYNCIE);
+ write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN | WT_RDY_ENAB);
+ } else {
+ write_scc(cmd, R15, TxUIE | DCDIE | CTSIE | SYNCIE);
+ write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
+ tx_isr(dev);
+ }
+ if (info->chip == Z8530) write_scc(cmd, R0, RES_EOM_L);
+ break;
+ case TX_SQDELAY:
+ /* Disable transmitter */
+ write_scc(cmd, R5, TxCRC_ENAB | Tx8);
+ /* Transmitter state change: Switch to TX_OFF and wait at least
+ 1 slottime. */
+ priv->tx_state = TX_OFF;
+ if (~priv->status & DCD) delay(dev, priv->param.waittime);
+ }
+}
+
+
+static inline void delay(struct device *dev, int t)
+{
+ struct scc_priv *priv = dev->priv;
+ int tmr = priv->tmr;
+
+ outb_p(t & 0xFF, tmr);
+ outb_p((t >> 8) & 0xFF, tmr);
+}
+
+
+static inline unsigned char random(void)
+{
+ /* See "Numerical Recipes in C", second edition, p. 284 */
+ rand = rand * 1664525L + 1013904223L;
+ return (unsigned char) (rand >> 24);
+}
+
+
diff --git a/drivers/net/ipddp.c b/drivers/net/ipddp.c
index fdca59467..fa3072a6c 100644
--- a/drivers/net/ipddp.c
+++ b/drivers/net/ipddp.c
@@ -1,5 +1,3 @@
-#warning "Needs new networking merges before it will work"
-#if 0
/*
* ipddp.c: IP-over-DDP driver for Linux
*
@@ -309,4 +307,3 @@ void cleanup_module(void)
}
#endif /* MODULE */
-#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-20 04:30:58 +0000