diff options
Diffstat (limited to 'include/asm-alpha')
37 files changed, 1185 insertions, 1658 deletions
diff --git a/include/asm-alpha/cache.h b/include/asm-alpha/cache.h index 5e46073a8..b7662d726 100644 --- a/include/asm-alpha/cache.h +++ b/include/asm-alpha/cache.h @@ -10,4 +10,6 @@ #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define SMP_CACHE_BYTES L1_CACHE_BYTES +#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) + #endif diff --git a/include/asm-alpha/compiler.h b/include/asm-alpha/compiler.h index 5656ce953..d3b2808e8 100644 --- a/include/asm-alpha/compiler.h +++ b/include/asm-alpha/compiler.h @@ -13,11 +13,13 @@ * EGCS (of varying versions) does a good job of using insxl and extxl. */ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 +#if 0 && (__GNUC__ > 2 || __GNUC_MINOR__ >= 91) #define __kernel_insbl(val, shift) \ (((unsigned long)(val) & 0xfful) << ((shift) * 8)) #define __kernel_inswl(val, shift) \ (((unsigned long)(val) & 0xfffful) << ((shift) * 8)) +#define __kernel_insql(val, shift) \ + ((unsigned long)(val) << ((shift) * 8)) #else #define __kernel_insbl(val, shift) \ ({ unsigned long __kir; \ @@ -27,9 +29,13 @@ ({ unsigned long __kir; \ __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ __kir; }) +#define __kernel_insql(val, shift) \ + ({ unsigned long __kir; \ + __asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ + __kir; }) #endif -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 92 +#if 0 && (__GNUC__ > 2 || __GNUC_MINOR__ >= 92) #define __kernel_extbl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfful) #define __kernel_extwl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfffful) #else @@ -47,11 +53,10 @@ /* * Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX * extension is enabled. Previous versions did not define anything - * we could test during compilation, so allow users to tell us when - * the compiler will DTRT. + * we could test during compilation -- too bad, so sad. */ -#if defined(HAVE_BWX) || defined(__alpha_bwx__) +#if defined(__alpha_bwx__) #define __kernel_ldbu(mem) (mem) #define __kernel_ldwu(mem) (mem) #define __kernel_stb(val,mem) ((mem) = (val)) diff --git a/include/asm-alpha/core_apecs.h b/include/asm-alpha/core_apecs.h index 3346346f9..f9796c1d5 100644 --- a/include/asm-alpha/core_apecs.h +++ b/include/asm-alpha/core_apecs.h @@ -67,25 +67,17 @@ make the AVANTI support pay for the limitations of the XL. It is true, however, that an XL kernel will run on an AVANTI without problems. */ -#define APECS_XL_DMA_WIN1_BASE (64*1024*1024) -#define APECS_XL_DMA_WIN1_SIZE (64*1024*1024) -#define APECS_XL_DMA_WIN1_SIZE_PARANOID (48*1024*1024) -#define APECS_XL_DMA_WIN2_BASE (1024*1024*1024) -#define APECS_XL_DMA_WIN2_SIZE (1024*1024*1024) +#define APECS_XL_DMA_WIN1_BASE (64UL*1024*1024) +#define APECS_XL_DMA_WIN1_SIZE (64UL*1024*1024) +#define APECS_XL_DMA_WIN1_SIZE_PARANOID (48UL*1024*1024) +#define APECS_XL_DMA_WIN2_BASE (1UL*1024*1024*1024) +#define APECS_XL_DMA_WIN2_SIZE (1UL*1024*1024*1024) /* These are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64. */ -#define APECS_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define APECS_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define APECS_DMA_WIN_BASE alpha_mv.dma_win_base -#define APECS_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define APECS_DMA_WIN_BASE APECS_DMA_WIN_BASE_DEFAULT -#define APECS_DMA_WIN_SIZE APECS_DMA_WIN_SIZE_DEFAULT -#endif +#define APECS_DMA_WIN_BASE (1UL*1024*1024*1024) +#define APECS_DMA_WIN_SIZE (1UL*1024*1024*1024) /* @@ -400,9 +392,9 @@ static inline unsigned long apecs_xl_virt_to_bus(void * address) { unsigned long paddr = virt_to_phys(address); if (paddr < APECS_XL_DMA_WIN1_SIZE_PARANOID) - return paddr + APECS_XL_DMA_WIN1_BASE; + return paddr + APECS_XL_DMA_WIN1_BASE; else - return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */ + return paddr + APECS_XL_DMA_WIN2_BASE; } __EXTERN_INLINE void * apecs_bus_to_virt(unsigned long address) @@ -426,12 +418,12 @@ static inline void * apecs_xl_bus_to_virt(unsigned long address) * detect null "pointers" (the NCR driver is much simpler if * NULL pointers are preserved). */ - if (address < APECS_XL_DMA_WIN1_BASE) - return 0; - else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE)) - address -= APECS_XL_DMA_WIN1_BASE; + if (address < APECS_XL_DMA_WIN1_BASE) + return 0; + else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE)) + address -= APECS_XL_DMA_WIN1_BASE; else /* should be more checking here, maybe? */ - address -= APECS_XL_DMA_WIN2_BASE; + address -= APECS_XL_DMA_WIN2_BASE; return phys_to_virt(address); } @@ -501,6 +493,7 @@ __EXTERN_INLINE unsigned long apecs_readb(unsigned long addr) { unsigned long result, msb; + addr -= APECS_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -514,6 +507,7 @@ __EXTERN_INLINE unsigned long apecs_readw(unsigned long addr) { unsigned long result, msb; + addr -= APECS_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -525,18 +519,19 @@ __EXTERN_INLINE unsigned long apecs_readw(unsigned long addr) __EXTERN_INLINE unsigned long apecs_readl(unsigned long addr) { - return *(vuip) (addr + APECS_DENSE_MEM); + return *(vuip)addr; } __EXTERN_INLINE unsigned long apecs_readq(unsigned long addr) { - return *(vulp) (addr + APECS_DENSE_MEM); + return *(vulp)addr; } __EXTERN_INLINE void apecs_writeb(unsigned char b, unsigned long addr) { unsigned long msb; + addr -= APECS_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -549,6 +544,7 @@ __EXTERN_INLINE void apecs_writew(unsigned short b, unsigned long addr) { unsigned long msb; + addr -= APECS_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -559,19 +555,22 @@ __EXTERN_INLINE void apecs_writew(unsigned short b, unsigned long addr) __EXTERN_INLINE void apecs_writel(unsigned int b, unsigned long addr) { - *(vuip) (addr + APECS_DENSE_MEM) = b; + *(vuip)addr = b; } __EXTERN_INLINE void apecs_writeq(unsigned long b, unsigned long addr) { - *(vulp) (addr + APECS_DENSE_MEM) = b; + *(vulp)addr = b; } -/* Find the DENSE memory area for a given bus address. */ +__EXTERN_INLINE unsigned long apecs_ioremap(unsigned long addr) +{ + return addr + APECS_DENSE_MEM; +} -__EXTERN_INLINE unsigned long apecs_dense_mem(unsigned long addr) +__EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr) { - return APECS_DENSE_MEM; + return addr >= IDENT_ADDR + 0x180000000UL; } #undef vip @@ -602,18 +601,18 @@ __EXTERN_INLINE unsigned long apecs_dense_mem(unsigned long addr) #define __writew apecs_writew #define __writel apecs_writel #define __writeq apecs_writeq -#define dense_mem apecs_dense_mem +#define __ioremap apecs_ioremap +#define __is_ioaddr apecs_is_ioaddr #define inb(port) \ -(__builtin_constant_p((port))?__inb(port):_inb(port)) - + (__builtin_constant_p((port))?__inb(port):_inb(port)) #define outb(x, port) \ -(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_cia.h b/include/asm-alpha/core_cia.h index 3407d0159..b549029d1 100644 --- a/include/asm-alpha/core_cia.h +++ b/include/asm-alpha/core_cia.h @@ -1,7 +1,9 @@ #ifndef __ALPHA_CIA__H__ #define __ALPHA_CIA__H__ -#include <linux/config.h> +/* Define to experiment with fitting everything into one 512MB HAE window. */ +#define CIA_ONE_HAE_WINDOW 1 + #include <linux/types.h> #include <asm/compiler.h> @@ -11,7 +13,7 @@ * * This file is based on: * - * DECchip 21171 Core Logic Chipset + * DECchip 21171 Core Logic Chipset * Technical Reference Manual * * EC-QE18B-TE @@ -39,17 +41,15 @@ /* CIA ADDRESS BIT DEFINITIONS * - * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | \_/ \_/ - * | | | - * +-- IO space, not cached. Byte Enable --+ | - * Transfer Length --+ - * - * + * 3333 3333 3322 2222 2222 1111 1111 11 + * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- + * 1 000 + * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- + * | |\| + * | Byte Enable --+ | + * | Transfer Length --+ + * +-- IO space, not cached * * Byte Transfer * Enable Length Transfer Byte Address @@ -77,16 +77,19 @@ #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */ #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */ -#define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) +#define CIA_DMA_WIN_BASE (1UL*1024*1024*1024) +#define CIA_DMA_WIN_SIZE (2UL*1024*1024*1024) + +/* Window 0 at 1GB size 1GB mapping to 0. */ +#define CIA_DMA_WIN0_BASE_DEFAULT (1UL*1024*1024*1024) +#define CIA_DMA_WIN0_SIZE_DEFAULT (1UL*1024*1024*1024) +#define CIA_DMA_WIN0_TRAN_DEFAULT (0UL) + +/* Window 1 at 2GB size 1GB mapping to 1GB. */ +#define CIA_DMA_WIN1_BASE_DEFAULT (2UL*1024*1024*1024) +#define CIA_DMA_WIN1_SIZE_DEFAULT (1UL*1024*1024*1024) +#define CIA_DMA_WIN1_TRAN_DEFAULT (1UL*1024*1024*1024) -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define CIA_DMA_WIN_BASE alpha_mv.dma_win_base -#define CIA_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define CIA_DMA_WIN_BASE CIA_DMA_WIN_SIZE_DEFAULT -#define CIA_DMA_WIN_SIZE CIA_DMA_WIN_SIZE_DEFAULT -#endif /* * 21171-CA Control and Status Registers (p4-1) @@ -207,7 +210,9 @@ #define CIA_IOC_STAT0_P_NBR_SHIFT 13 #define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff +#if !CIA_ONE_HAE_WINDOW #define CIA_HAE_ADDRESS CIA_IOC_HAE_MEM +#endif /* * Data structure for handling CIA machine checks. @@ -239,47 +244,47 @@ struct el_CIA_procdata { /* System-specific info. */ struct el_CIA_sysdata_mcheck { - unsigned long coma_gcr; - unsigned long coma_edsr; - unsigned long coma_ter; - unsigned long coma_elar; - unsigned long coma_ehar; - unsigned long coma_ldlr; - unsigned long coma_ldhr; - unsigned long coma_base0; - unsigned long coma_base1; - unsigned long coma_base2; - unsigned long coma_cnfg0; - unsigned long coma_cnfg1; - unsigned long coma_cnfg2; - unsigned long epic_dcsr; - unsigned long epic_pear; - unsigned long epic_sear; - unsigned long epic_tbr1; - unsigned long epic_tbr2; - unsigned long epic_pbr1; - unsigned long epic_pbr2; - unsigned long epic_pmr1; - unsigned long epic_pmr2; - unsigned long epic_harx1; - unsigned long epic_harx2; - unsigned long epic_pmlt; - unsigned long epic_tag0; - unsigned long epic_tag1; - unsigned long epic_tag2; - unsigned long epic_tag3; - unsigned long epic_tag4; - unsigned long epic_tag5; - unsigned long epic_tag6; - unsigned long epic_tag7; - unsigned long epic_data0; - unsigned long epic_data1; - unsigned long epic_data2; - unsigned long epic_data3; - unsigned long epic_data4; - unsigned long epic_data5; - unsigned long epic_data6; - unsigned long epic_data7; + unsigned long coma_gcr; + unsigned long coma_edsr; + unsigned long coma_ter; + unsigned long coma_elar; + unsigned long coma_ehar; + unsigned long coma_ldlr; + unsigned long coma_ldhr; + unsigned long coma_base0; + unsigned long coma_base1; + unsigned long coma_base2; + unsigned long coma_cnfg0; + unsigned long coma_cnfg1; + unsigned long coma_cnfg2; + unsigned long epic_dcsr; + unsigned long epic_pear; + unsigned long epic_sear; + unsigned long epic_tbr1; + unsigned long epic_tbr2; + unsigned long epic_pbr1; + unsigned long epic_pbr2; + unsigned long epic_pmr1; + unsigned long epic_pmr2; + unsigned long epic_harx1; + unsigned long epic_harx2; + unsigned long epic_pmlt; + unsigned long epic_tag0; + unsigned long epic_tag1; + unsigned long epic_tag2; + unsigned long epic_tag3; + unsigned long epic_tag4; + unsigned long epic_tag5; + unsigned long epic_tag6; + unsigned long epic_tag7; + unsigned long epic_data0; + unsigned long epic_data1; + unsigned long epic_data2; + unsigned long epic_data3; + unsigned long epic_data4; + unsigned long epic_data5; + unsigned long epic_data6; + unsigned long epic_data7; }; @@ -360,8 +365,8 @@ __EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr) /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. - * - * For reading and writing 8 and 16 bit quantities we need to + * + * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 @@ -370,10 +375,10 @@ __EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr) * See p 6-17 of the specification but it looks something like this: * * 21164 Address: - * - * 3 2 1 + * + * 3 2 1 * 9876543210987654321098765432109876543210 - * 1ZZZZ0.PCI.QW.Address............BBLL + * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset @@ -381,95 +386,26 @@ __EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr) * * PCI Address: * - * 3 2 1 + * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR - * + * */ -__EXTERN_INLINE unsigned long cia_srm_base(unsigned long addr) -{ - unsigned long mask, base; - - if (addr >= alpha_mv.sm_base_r1 - && addr <= alpha_mv.sm_base_r1 + CIA_MEM_R1_MASK) { - mask = CIA_MEM_R1_MASK; - base = CIA_SPARSE_MEM; - } - else if (addr >= alpha_mv.sm_base_r2 - && addr <= alpha_mv.sm_base_r2 + CIA_MEM_R2_MASK) { - mask = CIA_MEM_R2_MASK; - base = CIA_SPARSE_MEM_R2; - } - else if (addr >= alpha_mv.sm_base_r3 - && addr <= alpha_mv.sm_base_r3 + CIA_MEM_R3_MASK) { - mask = CIA_MEM_R3_MASK; - base = CIA_SPARSE_MEM_R3; - } - else - { -#if 0 - printk("cia: address 0x%lx not covered by HAE\n", addr); -#endif - return 0; - } - - return ((addr & mask) << 5) + base; -} - -__EXTERN_INLINE unsigned long cia_srm_readb(unsigned long addr) -{ - unsigned long result, work; - - if ((work = cia_srm_base(addr)) == 0) - return 0xff; - work += 0x00; /* add transfer length */ - - result = *(vip) work; - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE unsigned long cia_srm_readw(unsigned long addr) -{ - unsigned long result, work; - - if ((work = cia_srm_base(addr)) == 0) - return 0xffff; - work += 0x08; /* add transfer length */ - - result = *(vip) work; - return __kernel_extwl(result, addr & 3); -} - -__EXTERN_INLINE void cia_srm_writeb(unsigned char b, unsigned long addr) -{ - unsigned long work = cia_srm_base(addr), w; - if (work) { - work += 0x00; /* add transfer length */ - w = __kernel_insbl(b, addr & 3); - *(vuip) work = w; - } -} - -__EXTERN_INLINE void cia_srm_writew(unsigned short b, unsigned long addr) -{ - unsigned long work = cia_srm_base(addr), w; - if (work) { - work += 0x08; /* add transfer length */ - w = __kernel_inswl(b, addr & 3); - *(vuip) work = w; - } -} - __EXTERN_INLINE unsigned long cia_readb(unsigned long addr) { - unsigned long result, msb; + unsigned long result; +#if !CIA_ONE_HAE_WINDOW + unsigned long msb; + /* Note that CIA_DENSE_MEM has no bits not masked in these + operations, so we don't have to subtract it back out. */ msb = addr & 0xE0000000; - addr &= CIA_MEM_R1_MASK; set_hae(msb); +#endif + addr &= CIA_MEM_R1_MASK; result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00); return __kernel_extbl(result, addr & 3); @@ -477,11 +413,16 @@ __EXTERN_INLINE unsigned long cia_readb(unsigned long addr) __EXTERN_INLINE unsigned long cia_readw(unsigned long addr) { - unsigned long result, msb; + unsigned long result; +#if !CIA_ONE_HAE_WINDOW + unsigned long msb; + /* Note that CIA_DENSE_MEM has no bits not masked in these + operations, so we don't have to subtract it back out. */ msb = addr & 0xE0000000; - addr &= CIA_MEM_R1_MASK; set_hae(msb); +#endif + addr &= CIA_MEM_R1_MASK; result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08); return __kernel_extwl(result, addr & 3); @@ -489,11 +430,16 @@ __EXTERN_INLINE unsigned long cia_readw(unsigned long addr) __EXTERN_INLINE void cia_writeb(unsigned char b, unsigned long addr) { - unsigned long msb, w; + unsigned long w; +#if !CIA_ONE_HAE_WINDOW + unsigned long msb; + /* Note that CIA_DENSE_MEM has no bits not masked in these + operations, so we don't have to subtract it back out. */ msb = addr & 0xE0000000; - addr &= CIA_MEM_R1_MASK; set_hae(msb); +#endif + addr &= CIA_MEM_R1_MASK; w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w; @@ -501,11 +447,16 @@ __EXTERN_INLINE void cia_writeb(unsigned char b, unsigned long addr) __EXTERN_INLINE void cia_writew(unsigned short b, unsigned long addr) { - unsigned long msb, w; + unsigned long w; +#if !CIA_ONE_HAE_WINDOW + unsigned long msb; + /* Note that CIA_DENSE_MEM has no bits not masked in these + operations, so we don't have to subtract it back out. */ msb = addr & 0xE0000000; - addr &= CIA_MEM_R1_MASK; set_hae(msb); +#endif + addr &= CIA_MEM_R1_MASK; w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w; @@ -513,29 +464,32 @@ __EXTERN_INLINE void cia_writew(unsigned short b, unsigned long addr) __EXTERN_INLINE unsigned long cia_readl(unsigned long addr) { - return *(vuip) (addr + CIA_DENSE_MEM); + return *(vuip)addr; } __EXTERN_INLINE unsigned long cia_readq(unsigned long addr) { - return *(vulp) (addr + CIA_DENSE_MEM); + return *(vulp)addr; } __EXTERN_INLINE void cia_writel(unsigned int b, unsigned long addr) { - *(vuip) (addr + CIA_DENSE_MEM) = b; + *(vuip)addr = b; } __EXTERN_INLINE void cia_writeq(unsigned long b, unsigned long addr) { - *(vulp) (addr + CIA_DENSE_MEM) = b; + *(vulp)addr = b; } -/* Find the DENSE memory area for a given bus address. */ +__EXTERN_INLINE unsigned long cia_ioremap(unsigned long addr) +{ + return addr + CIA_DENSE_MEM; +} -__EXTERN_INLINE unsigned long cia_dense_mem(unsigned long addr) +__EXTERN_INLINE int cia_is_ioaddr(unsigned long addr) { - return CIA_DENSE_MEM; + return addr >= IDENT_ADDR + 0x8000000000UL; } #undef vip @@ -553,41 +507,26 @@ __EXTERN_INLINE unsigned long cia_dense_mem(unsigned long addr) #define __outw cia_outw #define __outl cia_outl -#ifdef CONFIG_ALPHA_SRM_SETUP -#define __readb cia_srm_readb -#define __readw cia_srm_readw -#define __writeb cia_srm_writeb -#define __writew cia_srm_writew -#else #define __readb cia_readb #define __readw cia_readw #define __writeb cia_writeb #define __writew cia_writew -#endif - #define __readl cia_readl #define __readq cia_readq #define __writel cia_writel #define __writeq cia_writeq -#define dense_mem cia_dense_mem +#define __ioremap cia_ioremap +#define __is_ioaddr cia_is_ioaddr #define inb(port) \ -(__builtin_constant_p((port))?__inb(port):_inb(port)) + (__builtin_constant_p((port))?__inb(port):_inb(port)) #define outb(x, port) \ -(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) - -#define inw(port) \ -(__builtin_constant_p((port))?__inw(port):_inw(port)) -#define outw(x, port) \ -(__builtin_constant_p((port))?__outw((x),(port)):_outw((x),(port))) - -#define inl(port) __inl(port) -#define outl(x,port) __outl((x),(port)) + (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_lca.h b/include/asm-alpha/core_lca.h index 63f258924..644512cba 100644 --- a/include/asm-alpha/core_lca.h +++ b/include/asm-alpha/core_lca.h @@ -1,7 +1,6 @@ #ifndef __ALPHA_LCA__H__ #define __ALPHA_LCA__H__ -#include <linux/config.h> #include <asm/system.h> #include <asm/compiler.h> @@ -56,16 +55,9 @@ * ugh). */ -#define LCA_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define LCA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) +#define LCA_DMA_WIN_BASE (1UL*1024*1024*1024) +#define LCA_DMA_WIN_SIZE (1UL*1024*1024*1024) -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define LCA_DMA_WIN_BASE alpha_mv.dma_win_base -#define LCA_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define LCA_DMA_WIN_BASE LCA_DMA_WIN_BASE_DEFAULT -#define LCA_DMA_WIN_SIZE LCA_DMA_WIN_SIZE_DEFAULT -#endif /* * Memory Controller registers: @@ -305,6 +297,7 @@ __EXTERN_INLINE unsigned long lca_readb(unsigned long addr) { unsigned long result, msb; + addr -= LCA_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -318,6 +311,7 @@ __EXTERN_INLINE unsigned long lca_readw(unsigned long addr) { unsigned long result, msb; + addr -= LCA_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -329,12 +323,12 @@ __EXTERN_INLINE unsigned long lca_readw(unsigned long addr) __EXTERN_INLINE unsigned long lca_readl(unsigned long addr) { - return *(vuip) (addr + LCA_DENSE_MEM); + return *(vuip)addr; } __EXTERN_INLINE unsigned long lca_readq(unsigned long addr) { - return *(vulp) (addr + LCA_DENSE_MEM); + return *(vulp)addr; } __EXTERN_INLINE void lca_writeb(unsigned char b, unsigned long addr) @@ -342,6 +336,7 @@ __EXTERN_INLINE void lca_writeb(unsigned char b, unsigned long addr) unsigned long msb; unsigned long w; + addr -= LCA_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -356,6 +351,7 @@ __EXTERN_INLINE void lca_writew(unsigned short b, unsigned long addr) unsigned long msb; unsigned long w; + addr -= LCA_DENSE_MEM; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; @@ -367,19 +363,22 @@ __EXTERN_INLINE void lca_writew(unsigned short b, unsigned long addr) __EXTERN_INLINE void lca_writel(unsigned int b, unsigned long addr) { - *(vuip) (addr + LCA_DENSE_MEM) = b; + *(vuip)addr = b; } __EXTERN_INLINE void lca_writeq(unsigned long b, unsigned long addr) { - *(vulp) (addr + LCA_DENSE_MEM) = b; + *(vulp)addr = b; } -/* Find the DENSE memory area for a given bus address. */ +__EXTERN_INLINE unsigned long lca_ioremap(unsigned long addr) +{ + return addr + LCA_DENSE_MEM; +} -__EXTERN_INLINE unsigned long lca_dense_mem(unsigned long addr) +__EXTERN_INLINE int lca_is_ioaddr(unsigned long addr) { - return LCA_DENSE_MEM; + return addr >= IDENT_ADDR + 0x120000000UL; } #undef vip @@ -404,18 +403,18 @@ __EXTERN_INLINE unsigned long lca_dense_mem(unsigned long addr) #define __readq lca_readq #define __writel lca_writel #define __writeq lca_writeq -#define dense_mem lca_dense_mem +#define __ioremap lca_ioremap +#define __is_ioaddr lca_is_ioaddr #define inb(port) \ -(__builtin_constant_p((port))?__inb(port):_inb(port)) - + (__builtin_constant_p((port))?__inb(port):_inb(port)) #define outb(x, port) \ -(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_mcpcia.h b/include/asm-alpha/core_mcpcia.h index 84eab12d8..577704129 100644 --- a/include/asm-alpha/core_mcpcia.h +++ b/include/asm-alpha/core_mcpcia.h @@ -1,7 +1,10 @@ #ifndef __ALPHA_MCPCIA__H__ #define __ALPHA_MCPCIA__H__ -#include <linux/config.h> +/* Define to experiment with fitting everything into one 128MB HAE window. + One window per bus, that is. */ +#define MCPCIA_ONE_HAE_WINDOW 1 + #include <linux/types.h> #include <linux/pci.h> #include <asm/compiler.h> @@ -37,17 +40,15 @@ /* MCPCIA ADDRESS BIT DEFINITIONS * - * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | \_/ \_/ - * | | | - * +-- IO space, not cached. Byte Enable --+ | - * Transfer Length --+ - * - * + * 3333 3333 3322 2222 2222 1111 1111 11 + * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- + * 1 000 + * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- + * | |\| + * | Byte Enable --+ | + * | Transfer Length --+ + * +-- IO space, not cached * * Byte Transfer * Enable Length Transfer Byte Address @@ -73,106 +74,119 @@ #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */ -#define MCPCIA_DMA_WIN_BASE_DEFAULT (2*1024*1024*1024U) -#define MCPCIA_DMA_WIN_SIZE_DEFAULT (2*1024*1024*1024U) +#define MCPCIA_DMA_WIN_BASE (2UL*1024*1024*1024) +#define MCPCIA_DMA_WIN_SIZE (2UL*1024*1024*1024) -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define MCPCIA_DMA_WIN_BASE alpha_mv.dma_win_base -#define MCPCIA_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define MCPCIA_DMA_WIN_BASE MCPCIA_DMA_WIN_BASE_DEFAULT -#define MCPCIA_DMA_WIN_SIZE MCPCIA_DMA_WIN_SIZE_DEFAULT -#endif +#define MCPCIA_MID(m) ((unsigned long)(m) << 33) -#define HOSE(h) (((unsigned long)(h)) << 33) +/* + * Memory spaces: + */ +#define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m)) +#define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m)) +#define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m)) +#define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m)) +#define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m)) +#define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m)) +#define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m)) +#define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m)) /* * General Registers */ -#define MCPCIA_REV(h) (IDENT_ADDR + 0xf9e0000000UL + HOSE(h)) -#define MCPCIA_WHOAMI(h) (IDENT_ADDR + 0xf9e0000040UL + HOSE(h)) -#define MCPCIA_PCI_LAT(h) (IDENT_ADDR + 0xf9e0000080UL + HOSE(h)) -#define MCPCIA_CAP_CTRL(h) (IDENT_ADDR + 0xf9e0000100UL + HOSE(h)) -#define MCPCIA_HAE_MEM(h) (IDENT_ADDR + 0xf9e0000400UL + HOSE(h)) -#define MCPCIA_HAE_IO(h) (IDENT_ADDR + 0xf9e0000440UL + HOSE(h)) -#if 0 -#define MCPCIA_IACK_SC(h) (IDENT_ADDR + 0xf9e0000480UL + HOSE(h)) -#endif -#define MCPCIA_HAE_DENSE(h) (IDENT_ADDR + 0xf9e00004c0UL + HOSE(h)) +#define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000) +#define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040) +#define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080) +#define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100) +#define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400) +#define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440) +#define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480) +#define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0) /* * Interrupt Control registers */ -#define MCPCIA_INT_CTL(h) (IDENT_ADDR + 0xf9e0000500UL + HOSE(h)) -#define MCPCIA_INT_REQ(h) (IDENT_ADDR + 0xf9e0000540UL + HOSE(h)) -#define MCPCIA_INT_TARG(h) (IDENT_ADDR + 0xf9e0000580UL + HOSE(h)) -#define MCPCIA_INT_ADR(h) (IDENT_ADDR + 0xf9e00005c0UL + HOSE(h)) -#define MCPCIA_INT_ADR_EXT(h) (IDENT_ADDR + 0xf9e0000600UL + HOSE(h)) -#define MCPCIA_INT_MASK0(h) (IDENT_ADDR + 0xf9e0000640UL + HOSE(h)) -#define MCPCIA_INT_MASK1(h) (IDENT_ADDR + 0xf9e0000680UL + HOSE(h)) -#define MCPCIA_INT_ACK0(h) (IDENT_ADDR + 0xf9f0003f00UL + HOSE(h)) -#define MCPCIA_INT_ACK1(h) (IDENT_ADDR + 0xf9e0003f40UL + HOSE(h)) +#define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500) +#define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540) +#define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580) +#define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0) +#define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600) +#define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640) +#define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680) +#define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00) +#define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40) /* * Performance Monitor registers */ -#define MCPCIA_PERF_MONITOR(h) (IDENT_ADDR + 0xf9e0000300UL + HOSE(h)) -#define MCPCIA_PERF_CONTROL(h) (IDENT_ADDR + 0xf9e0000340UL + HOSE(h)) +#define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300) +#define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340) /* * Diagnostic Registers */ -#define MCPCIA_CAP_DIAG(h) (IDENT_ADDR + 0xf9e0000700UL + HOSE(h)) -#define MCPCIA_TOP_OF_MEM(h) (IDENT_ADDR + 0xf9e00007c0UL + HOSE(h)) +#define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700) +#define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0) /* * Error registers */ -#define MCPCIA_MC_ERR0(h) (IDENT_ADDR + 0xf9e0000800UL + HOSE(h)) -#define MCPCIA_MC_ERR1(h) (IDENT_ADDR + 0xf9e0000840UL + HOSE(h)) -#define MCPCIA_CAP_ERR(h) (IDENT_ADDR + 0xf9e0000880UL + HOSE(h)) -#define MCPCIA_PCI_ERR1(h) (IDENT_ADDR + 0xf9e0001040UL + HOSE(h)) +#define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800) +#define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840) +#define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880) +#define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040) +#define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000) +#define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040) +#define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080) +#define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000) +#define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040) +#define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080) /* * PCI Address Translation Registers. */ -#define MCPCIA_SG_TBIA(h) (IDENT_ADDR + 0xf9e0001300UL + HOSE(h)) -#define MCPCIA_HBASE(h) (IDENT_ADDR + 0xf9e0001340UL + HOSE(h)) +#define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300) +#define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340) -#define MCPCIA_W0_BASE(h) (IDENT_ADDR + 0xf9e0001400UL + HOSE(h)) -#define MCPCIA_W0_MASK(h) (IDENT_ADDR + 0xf9e0001440UL + HOSE(h)) -#define MCPCIA_T0_BASE(h) (IDENT_ADDR + 0xf9e0001480UL + HOSE(h)) +#define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400) +#define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440) +#define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480) -#define MCPCIA_W1_BASE(h) (IDENT_ADDR + 0xf9e0001500UL + HOSE(h)) -#define MCPCIA_W1_MASK(h) (IDENT_ADDR + 0xf9e0001540UL + HOSE(h)) -#define MCPCIA_T1_BASE(h) (IDENT_ADDR + 0xf9e0001580UL + HOSE(h)) +#define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500) +#define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540) +#define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580) -#define MCPCIA_W2_BASE(h) (IDENT_ADDR + 0xf9e0001600UL + HOSE(h)) -#define MCPCIA_W2_MASK(h) (IDENT_ADDR + 0xf9e0001640UL + HOSE(h)) -#define MCPCIA_T2_BASE(h) (IDENT_ADDR + 0xf9e0001680UL + HOSE(h)) +#define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600) +#define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640) +#define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680) -#define MCPCIA_W3_BASE(h) (IDENT_ADDR + 0xf9e0001700UL + HOSE(h)) -#define MCPCIA_W3_MASK(h) (IDENT_ADDR + 0xf9e0001740UL + HOSE(h)) -#define MCPCIA_T3_BASE(h) (IDENT_ADDR + 0xf9e0001780UL + HOSE(h)) +#define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700) +#define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740) +#define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780) -/* - * Memory spaces: +/* Hack! Only words for bus 0. */ + +#if !MCPCIA_ONE_HAE_WINDOW +#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4) +#endif +#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4) + +/* + * The canonical non-remaped I/O and MEM addresses have these values + * subtracted out. This is arranged so that folks manipulating ISA + * devices can use their familiar numbers and have them map to bus 0. */ -#define MCPCIA_CONF(h) (IDENT_ADDR + 0xf9c0000000UL + HOSE(h)) -#define MCPCIA_IO(h) (IDENT_ADDR + 0xf980000000UL + HOSE(h)) -#define MCPCIA_SPARSE(h) (IDENT_ADDR + 0xf800000000UL + HOSE(h)) -#define MCPCIA_DENSE(h) (IDENT_ADDR + 0xf900000000UL + HOSE(h)) -#define _MCPCIA_IACK_SC(h) (IDENT_ADDR + 0xf9f0003f00UL + HOSE(h)) -#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(0) -#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(0) +#define MCPCIA_IO_BIAS MCPCIA_IO(4) +#define MCPCIA_MEM_BIAS MCPCIA_DENSE(4) + /* * Data structure for handling MCPCIA machine checks: */ struct el_MCPCIA_uncorrected_frame_mcheck { - struct el_common header; - struct el_common_EV5_uncorrectable_mcheck procdata; + struct el_common header; + struct el_common_EV5_uncorrectable_mcheck procdata; }; @@ -215,91 +229,81 @@ __EXTERN_INLINE void * mcpcia_bus_to_virt(unsigned long address) #define vuip volatile unsigned int * #define vulp volatile unsigned long * -#if 0 /* BWIO */ -__EXTERN_INLINE unsigned int mcpcia_bw_inb(unsigned long addr) -{ - return __kernel_ldbu(*(vucp)(addr+MCPCIA_BW_IO)); -} - -__EXTERN_INLINE void mcpcia_bw_outb(unsigned char b, unsigned long addr) +__EXTERN_INLINE unsigned int mcpcia_inb(unsigned long in_addr) { - __kernel_stb(b, *(vucp)(addr+MCPCIA_BW_IO)); - mb(); -} + unsigned long addr, hose, result; -__EXTERN_INLINE unsigned int mcpcia_bw_inw(unsigned long addr) -{ - return __kernel_ldwu(*(vusp)(addr+MCPCIA_BW_IO)); -} + addr = in_addr & 0xffffUL; + hose = in_addr & ~0xffffUL; -__EXTERN_INLINE void mcpcia_bw_outw(unsigned short b, unsigned long addr) -{ - __kernel_stw(b, *(vusp)(addr+MCPCIA_BW_IO)); - mb(); -} + /* ??? I wish I could get rid of this. But there's no ioremap + equivalent for I/O space. PCI I/O can be forced into the + correct hose's I/O region, but that doesn't take care of + legacy ISA crap. */ + hose += MCPCIA_IO_BIAS; -__EXTERN_INLINE unsigned int mcpcia_bw_inl(unsigned long addr) -{ - return *(vuip)(addr+MCPCIA_BW_IO); -} - -__EXTERN_INLINE void mcpcia_bw_outl(unsigned int b, unsigned long addr) -{ - *(vuip)(addr+MCPCIA_BW_IO) = b; - mb(); -} -#endif - -__EXTERN_INLINE unsigned int mcpcia_inb(unsigned long in_addr) -{ - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - long result = *(vip) ((addr << 5) + MCPCIA_IO(hose) + 0x00); + result = *(vip) ((addr << 5) + hose + 0x00); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE void mcpcia_outb(unsigned char b, unsigned long in_addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - unsigned long w; + unsigned long addr, hose, w; + + addr = in_addr & 0xffffUL; + hose = in_addr & ~0xffffUL; + hose += MCPCIA_IO_BIAS; w = __kernel_insbl(b, addr & 3); - *(vuip) ((addr << 5) + MCPCIA_IO(hose) + 0x00) = w; + *(vuip) ((addr << 5) + hose + 0x00) = w; mb(); } __EXTERN_INLINE unsigned int mcpcia_inw(unsigned long in_addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - long result = *(vip) ((addr << 5) + MCPCIA_IO(hose) + 0x08); + unsigned long addr, hose, result; + + addr = in_addr & 0xffffUL; + hose = in_addr & ~0xffffUL; + hose += MCPCIA_IO_BIAS; + + result = *(vip) ((addr << 5) + hose + 0x08); return __kernel_extwl(result, addr & 3); } __EXTERN_INLINE void mcpcia_outw(unsigned short b, unsigned long in_addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - unsigned long w; + unsigned long addr, hose, w; + + addr = in_addr & 0xffffUL; + hose = in_addr & ~0xffffUL; + hose += MCPCIA_IO_BIAS; w = __kernel_inswl(b, addr & 3); - *(vuip) ((addr << 5) + MCPCIA_IO(hose) + 0x08) = w; + *(vuip) ((addr << 5) + hose + 0x08) = w; mb(); } __EXTERN_INLINE unsigned int mcpcia_inl(unsigned long in_addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - return *(vuip) ((addr << 5) + MCPCIA_IO(hose) + 0x18); + unsigned long addr, hose; + + addr = in_addr & 0xffffUL; + hose = in_addr & ~0xffffUL; + hose += MCPCIA_IO_BIAS; + + return *(vuip) ((addr << 5) + hose + 0x18); } __EXTERN_INLINE void mcpcia_outl(unsigned int b, unsigned long in_addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - *(vuip) ((addr << 5) + MCPCIA_IO(hose) + 0x18) = b; + unsigned long addr, hose; + + addr = in_addr & 0xffffUL; + hose = in_addr & ~0xffffUL; + hose += MCPCIA_IO_BIAS; + + *(vuip) ((addr << 5) + hose + 0x18) = b; mb(); } @@ -307,8 +311,8 @@ __EXTERN_INLINE void mcpcia_outl(unsigned int b, unsigned long in_addr) /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. - * - * For reading and writing 8 and 16 bit quantities we need to + * + * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 @@ -317,10 +321,10 @@ __EXTERN_INLINE void mcpcia_outl(unsigned int b, unsigned long in_addr) * See p 6-17 of the specification but it looks something like this: * * 21164 Address: - * + * * 3 2 1 * 9876543210987654321098765432109876543210 - * 1ZZZZ0.PCI.QW.Address............BBLL + * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset @@ -333,125 +337,34 @@ __EXTERN_INLINE void mcpcia_outl(unsigned int b, unsigned long in_addr) * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR - * + * */ -#if 0 /* BWIO */ -__EXTERN_INLINE unsigned long mcpcia_bw_readb(unsigned long addr) -{ - return __kernel_ldbu(*(vucp)(addr+MCPCIA_BW_MEM)); -} - -__EXTERN_INLINE unsigned long mcpcia_bw_readw(unsigned long addr) -{ - return __kernel_ldbw(*(vusp)(addr+MCPCIA_BW_MEM)); -} - -__EXTERN_INLINE unsigned long mcpcia_bw_readl(unsigned long addr) -{ - return *(vuip)(addr + MCPCIA_BW_MEM); -} - -__EXTERN_INLINE unsigned long mcpcia_bw_readq(unsigned long addr) -{ - return *(vulp)(addr + MCPCIA_BW_MEM); -} - -__EXTERN_INLINE void mcpcia_bw_writeb(unsigned char b, unsigned long addr) -{ - __kernel_stb(b, *(vucp)(addr+MCPCIA_BW_MEM)); -} - -__EXTERN_INLINE void mcpcia_bw_writew(unsigned short b, unsigned long addr) -{ - __kernel_stw(b, *(vusp)(addr+MCPCIA_BW_MEM)); -} - -__EXTERN_INLINE void mcpcia_bw_writel(unsigned int b, unsigned long addr) -{ - *(vuip)(addr+MCPCIA_BW_MEM) = b; -} - -__EXTERN_INLINE void mcpcia_bw_writeq(unsigned long b, unsigned long addr) +__EXTERN_INLINE unsigned long mcpcia_ioremap(unsigned long addr) { - *(vulp)(addr+MCPCIA_BW_MEM) = b; + return addr + MCPCIA_MEM_BIAS; } -#endif -__EXTERN_INLINE unsigned long mcpcia_srm_base(unsigned long addr) +__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr) { - unsigned long mask, base; - unsigned long hose = (addr >> 32) & 3; - - if (addr >= alpha_mv.sm_base_r1 - && addr <= alpha_mv.sm_base_r1 + MCPCIA_MEM_MASK) { - mask = MCPCIA_MEM_MASK; - base = MCPCIA_SPARSE(hose); - } - else - { -#if 0 - printk("mcpcia: address 0x%lx not covered by HAE\n", addr); -#endif - return 0; - } - - return ((addr & mask) << 5) + base; -} - -__EXTERN_INLINE unsigned long mcpcia_srm_readb(unsigned long addr) -{ - unsigned long result, work; - - if ((work = mcpcia_srm_base(addr)) == 0) - return 0xff; - work += 0x00; /* add transfer length */ - - result = *(vip) work; - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE unsigned long mcpcia_srm_readw(unsigned long addr) -{ - unsigned long result, work; - - if ((work = mcpcia_srm_base(addr)) == 0) - return 0xffff; - work += 0x08; /* add transfer length */ - - result = *(vip) work; - return __kernel_extwl(result, addr & 3); -} - -__EXTERN_INLINE void mcpcia_srm_writeb(unsigned char b, unsigned long addr) -{ - unsigned long work = mcpcia_srm_base(addr); - if (work) { - work += 0x00; /* add transfer length */ - *(vuip) work = b * 0x01010101; - } -} - -__EXTERN_INLINE void mcpcia_srm_writew(unsigned short b, unsigned long addr) -{ - unsigned long work = mcpcia_srm_base(addr); - if (work) { - work += 0x08; /* add transfer length */ - *(vuip) work = b * 0x00010001; - } + return addr >= MCPCIA_SPARSE(0); } __EXTERN_INLINE unsigned long mcpcia_readb(unsigned long in_addr) { unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - unsigned long result, msb, work, temp; + unsigned long hose = in_addr & ~0xffffffffUL; + unsigned long result, work; +#if !MCPCIA_ONE_HAE_WINDOW + unsigned long msb; msb = addr & ~MCPCIA_MEM_MASK; - temp = addr & MCPCIA_MEM_MASK; set_hae(msb); +#endif + addr = addr & MCPCIA_MEM_MASK; - work = ((temp << 5) + MCPCIA_SPARSE(hose) + 0x00); + hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); + work = ((addr << 5) + hose + 0x00); result = *(vip) work; return __kernel_extbl(result, addr & 3); } @@ -459,14 +372,18 @@ __EXTERN_INLINE unsigned long mcpcia_readb(unsigned long in_addr) __EXTERN_INLINE unsigned long mcpcia_readw(unsigned long in_addr) { unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - unsigned long result, msb, work, temp; + unsigned long hose = in_addr & ~0xffffffffUL; + unsigned long result, work; +#if !MCPCIA_ONE_HAE_WINDOW + unsigned long msb; msb = addr & ~MCPCIA_MEM_MASK; - temp = addr & MCPCIA_MEM_MASK ; set_hae(msb); +#endif + addr = addr & MCPCIA_MEM_MASK; - work = ((temp << 5) + MCPCIA_SPARSE(hose) + 0x08); + hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); + work = ((addr << 5) + hose + 0x08); result = *(vip) work; return __kernel_extwl(result, addr & 3); } @@ -474,62 +391,57 @@ __EXTERN_INLINE unsigned long mcpcia_readw(unsigned long in_addr) __EXTERN_INLINE void mcpcia_writeb(unsigned char b, unsigned long in_addr) { unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - unsigned long msb; + unsigned long hose = in_addr & ~0xffffffffUL; + unsigned long w; +#if !MCPCIA_ONE_HAE_WINDOW + unsigned long msb; msb = addr & ~MCPCIA_MEM_MASK; - addr &= MCPCIA_MEM_MASK; set_hae(msb); +#endif + addr = addr & MCPCIA_MEM_MASK; - *(vuip) ((addr << 5) + MCPCIA_SPARSE(hose) + 0x00) = b * 0x01010101; + w = __kernel_insbl(b, in_addr & 3); + hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); + *(vuip) ((addr << 5) + hose + 0x00) = w; } __EXTERN_INLINE void mcpcia_writew(unsigned short b, unsigned long in_addr) { unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - unsigned long msb ; + unsigned long hose = in_addr & ~0xffffffffUL; + unsigned long w; - msb = addr & ~MCPCIA_MEM_MASK ; - addr &= MCPCIA_MEM_MASK ; +#if !MCPCIA_ONE_HAE_WINDOW + unsigned long msb; + msb = addr & ~MCPCIA_MEM_MASK; set_hae(msb); +#endif + addr = addr & MCPCIA_MEM_MASK; - *(vuip) ((addr << 5) + MCPCIA_SPARSE(hose) + 0x08) = b * 0x00010001; -} - -__EXTERN_INLINE unsigned long mcpcia_readl(unsigned long in_addr) -{ - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - return *(vuip) (addr + MCPCIA_DENSE(hose)); + w = __kernel_inswl(b, in_addr & 3); + hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); + *(vuip) ((addr << 5) + hose + 0x08) = w; } -__EXTERN_INLINE unsigned long mcpcia_readq(unsigned long in_addr) +__EXTERN_INLINE unsigned long mcpcia_readl(unsigned long addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - return *(vulp) (addr + MCPCIA_DENSE(hose)); + return *(vuip)addr; } -__EXTERN_INLINE void mcpcia_writel(unsigned int b, unsigned long in_addr) +__EXTERN_INLINE unsigned long mcpcia_readq(unsigned long addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - *(vuip) (addr + MCPCIA_DENSE(hose)) = b; + return *(vulp)addr; } -__EXTERN_INLINE void mcpcia_writeq(unsigned long b, unsigned long in_addr) +__EXTERN_INLINE void mcpcia_writel(unsigned int b, unsigned long addr) { - unsigned long addr = in_addr & 0xffffffffUL; - unsigned long hose = (in_addr >> 32) & 3; - *(vulp) (addr + MCPCIA_DENSE(hose)) = b; + *(vuip)addr = b; } -/* Find the DENSE memory area for a given bus address. */ - -__EXTERN_INLINE unsigned long mcpcia_dense_mem(unsigned long addr) +__EXTERN_INLINE void mcpcia_writeq(unsigned long b, unsigned long addr) { - return MCPCIA_DENSE((addr >> 32) & 3); + *(vulp)addr = b; } #undef vucp @@ -543,69 +455,32 @@ __EXTERN_INLINE unsigned long mcpcia_dense_mem(unsigned long addr) #define virt_to_bus mcpcia_virt_to_bus #define bus_to_virt mcpcia_bus_to_virt -#if 0 /* BWIO */ -# define __inb mcpcia_bw_inb -# define __inw mcpcia_bw_inw -# define __inl mcpcia_bw_inl -# define __outb mcpcia_bw_outb -# define __outw mcpcia_bw_outw -# define __outl mcpcia_bw_outl -# define __readb mcpcia_bw_readb -# define __readw mcpcia_bw_readw -# define __writeb mcpcia_bw_writeb -# define __writew mcpcia_bw_writew -# define __readl mcpcia_bw_readl -# define __readq mcpcia_bw_readq -# define __writel mcpcia_bw_writel -# define __writeq mcpcia_bw_writeq -#else -# define __inb mcpcia_inb -# define __inw mcpcia_inw -# define __inl mcpcia_inl -# define __outb mcpcia_outb -# define __outw mcpcia_outw -# define __outl mcpcia_outl -# ifdef CONFIG_ALPHA_SRM_SETUP -# define __readb mcpcia_srm_readb -# define __readw mcpcia_srm_readw -# define __writeb mcpcia_srm_writeb -# define __writew mcpcia_srm_writew -# else -# define __readb mcpcia_readb -# define __readw mcpcia_readw -# define __writeb mcpcia_writeb -# define __writew mcpcia_writew -# endif -# define __readl mcpcia_readl -# define __readq mcpcia_readq -# define __writel mcpcia_writel -# define __writeq mcpcia_writeq -#endif /* BWIO */ - -#define dense_mem mcpcia_dense_mem - -#if 0 /* BWIO */ -# define inb(port) __inb((port)) -# define inw(port) __inw((port)) -# define inl(port) __inl((port)) -# define outb(x, port) __outb((x),(port)) -# define outw(x, port) __outw((x),(port)) -# define outl(x, port) __outl((x),(port)) -# define readb(addr) __readb((addr)) -# define readw(addr) __readw((addr)) -# define writeb(b, addr) __writeb((b),(addr)) -# define writew(b, addr) __writew((b),(addr)) -#else +#define __inb mcpcia_inb +#define __inw mcpcia_inw +#define __inl mcpcia_inl +#define __outb mcpcia_outb +#define __outw mcpcia_outw +#define __outl mcpcia_outl +#define __readb mcpcia_readb +#define __readw mcpcia_readw +#define __writeb mcpcia_writeb +#define __writew mcpcia_writew +#define __readl mcpcia_readl +#define __readq mcpcia_readq +#define __writel mcpcia_writel +#define __writeq mcpcia_writeq +#define __ioremap mcpcia_ioremap +#define __is_ioaddr mcpcia_is_ioaddr + # define inb(port) \ (__builtin_constant_p((port))?__inb(port):_inb(port)) # define outb(x, port) \ (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) -#endif /* BWIO */ -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_polaris.h b/include/asm-alpha/core_polaris.h index 8caf50622..da53edc22 100644 --- a/include/asm-alpha/core_polaris.h +++ b/include/asm-alpha/core_polaris.h @@ -1,7 +1,6 @@ #ifndef __ALPHA_POLARIS__H__ #define __ALPHA_POLARIS__H__ -#include <linux/config.h> #include <linux/types.h> #include <asm/compiler.h> @@ -19,38 +18,31 @@ */ /* Polaris memory regions */ -#define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000) -#define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000) -#define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000) -#define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000) -#define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000) -#define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000) -#define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000) +#define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000) +#define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000) +#define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000) +#define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000) +#define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000) +#define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000) +#define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000) -#define POLARIS_IACK_SC POLARIS_IACK_BASE +#define POLARIS_IACK_SC POLARIS_IACK_BASE /* The Polaris command/status registers live in PCI Config space for * bus 0/device 0. As such, they may be bytes, words, or doublewords. */ -#define POLARIS_W_VENID (POLARIS_DENSE_CONFIG_BASE) -#define POLARIS_W_DEVID (POLARIS_DENSE_CONFIG_BASE+2) -#define POLARIS_W_CMD (POLARIS_DENSE_CONFIG_BASE+4) -#define POLARIS_W_STATUS (POLARIS_DENSE_CONFIG_BASE+6) +#define POLARIS_W_VENID (POLARIS_DENSE_CONFIG_BASE) +#define POLARIS_W_DEVID (POLARIS_DENSE_CONFIG_BASE+2) +#define POLARIS_W_CMD (POLARIS_DENSE_CONFIG_BASE+4) +#define POLARIS_W_STATUS (POLARIS_DENSE_CONFIG_BASE+6) /* No HAE address. Polaris has no concept of an HAE, since it * supports transfers of all sizes in dense space. */ -#define POLARIS_DMA_WIN_BASE_DEFAULT 0x80000000 /* fixed, 2G @ 2G */ -#define POLARIS_DMA_WIN_SIZE_DEFAULT 0x80000000 /* fixed, 2G @ 2G */ +#define POLARIS_DMA_WIN_BASE 0x80000000UL /* fixed, 2G @ 2G */ +#define POLARIS_DMA_WIN_SIZE 0x80000000UL /* fixed, 2G @ 2G */ -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define POLARIS_DMA_WIN_BASE alpha_mv.dma_win_base -#define POLARIS_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define POLARIS_DMA_WIN_BASE POLARIS_DMA_WIN_BASE_DEFAULT -#define POLARIS_DMA_WIN_SIZE POLARIS_DMA_WIN_SIZE_DEFAULT -#endif /* * Data structure for handling POLARIS machine checks: @@ -62,7 +54,7 @@ struct el_POLARIS_sysdata_mcheck { u_long psc_pcictl2; }; - #ifdef __KERNEL__ +#ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline @@ -96,7 +88,12 @@ __EXTERN_INLINE void * polaris_bus_to_virt(unsigned long address) __EXTERN_INLINE unsigned int polaris_inb(unsigned long addr) { - return __kernel_ldbu(*(vucp)(addr + POLARIS_DENSE_IO_BASE)); + /* ??? I wish I could get rid of this. But there's no ioremap + equivalent for I/O space. PCI I/O can be forced into the + POLARIS I/O region, but that doesn't take care of legacy + ISA crap. */ + + return __kernel_ldbu(*(vucp)(addr + POLARIS_DENSE_IO_BASE)); } __EXTERN_INLINE void polaris_outb(unsigned char b, unsigned long addr) @@ -107,7 +104,7 @@ __EXTERN_INLINE void polaris_outb(unsigned char b, unsigned long addr) __EXTERN_INLINE unsigned int polaris_inw(unsigned long addr) { - return __kernel_ldwu(*(vusp)(addr + POLARIS_DENSE_IO_BASE)); + return __kernel_ldwu(*(vusp)(addr + POLARIS_DENSE_IO_BASE)); } __EXTERN_INLINE void polaris_outw(unsigned short b, unsigned long addr) @@ -118,13 +115,13 @@ __EXTERN_INLINE void polaris_outw(unsigned short b, unsigned long addr) __EXTERN_INLINE unsigned int polaris_inl(unsigned long addr) { - return *(vuip)(addr + POLARIS_DENSE_IO_BASE); + return *(vuip)(addr + POLARIS_DENSE_IO_BASE); } __EXTERN_INLINE void polaris_outl(unsigned int b, unsigned long addr) { - *(vuip)(addr + POLARIS_DENSE_IO_BASE) = b; - mb(); + *(vuip)(addr + POLARIS_DENSE_IO_BASE) = b; + mb(); } /* @@ -136,53 +133,52 @@ __EXTERN_INLINE void polaris_outl(unsigned int b, unsigned long addr) __EXTERN_INLINE unsigned long polaris_readb(unsigned long addr) { - return __kernel_ldbu(*(vucp)(addr + POLARIS_DENSE_MEM_BASE)); + return __kernel_ldbu(*(vucp)addr); } __EXTERN_INLINE unsigned long polaris_readw(unsigned long addr) { - return __kernel_ldwu(*(vusp)(addr + POLARIS_DENSE_MEM_BASE)); + return __kernel_ldwu(*(vusp)addr); } __EXTERN_INLINE unsigned long polaris_readl(unsigned long addr) { - return *(vuip)(addr + POLARIS_DENSE_MEM_BASE); + return *(vuip)addr; } __EXTERN_INLINE unsigned long polaris_readq(unsigned long addr) { - return *(vulp)(addr + POLARIS_DENSE_MEM_BASE); + return *(vulp)addr; } __EXTERN_INLINE void polaris_writeb(unsigned char b, unsigned long addr) { - __kernel_stb(b, *(vucp)(addr + POLARIS_DENSE_MEM_BASE)); - mb(); + __kernel_stb(b, *(vucp)addr); } __EXTERN_INLINE void polaris_writew(unsigned short b, unsigned long addr) { - __kernel_stw(b, *(vusp)(addr + POLARIS_DENSE_MEM_BASE)); - mb(); + __kernel_stw(b, *(vusp)addr); } __EXTERN_INLINE void polaris_writel(unsigned int b, unsigned long addr) { - *(vuip)(addr + POLARIS_DENSE_MEM_BASE) = b; - mb(); + *(vuip)addr = b; } __EXTERN_INLINE void polaris_writeq(unsigned long b, unsigned long addr) { - *(vulp)(addr + POLARIS_DENSE_MEM_BASE) = b; - mb(); + *(vulp)addr = b; } -/* Find the DENSE memory area for a given bus address. */ +__EXTERN_INLINE unsigned long polaris_ioremap(unsigned long addr) +{ + return addr + POLARIS_DENSE_MEM_BASE; +} -__EXTERN_INLINE unsigned long polaris_dense_mem(unsigned long addr) +__EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr) { - return POLARIS_DENSE_MEM_BASE; + return addr >= POLARIS_SPARSE_MEM_BASE; } #undef vucp @@ -209,25 +205,24 @@ __EXTERN_INLINE unsigned long polaris_dense_mem(unsigned long addr) #define __readq polaris_readq #define __writel polaris_writel #define __writeq polaris_writeq -#define dense_mem polaris_dense_mem - -#define inb(port) __inb((port)) -#define inw(port) __inw((port)) -#define inl(port) __inl((port)) - -#define outb(v, port) __outb((v),(port)) -#define outw(v, port) __outw((v),(port)) -#define outl(v, port) __outl((v),(port)) - -#define readb(a) __readb((unsigned long)(a)) -#define readw(a) __readw((unsigned long)(a)) -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) - -#define writeb(v,a) __writeb((v),(unsigned long)(a)) -#define writew(v,a) __writew((v),(unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __ioremap polaris_ioremap +#define __is_ioaddr polaris_is_ioaddr + +#define inb(port) __inb((port)) +#define inw(port) __inw((port)) +#define inl(port) __inl((port)) +#define outb(v, port) __outb((v),(port)) +#define outw(v, port) __outw((v),(port)) +#define outl(v, port) __outl((v),(port)) + +#define __raw_readb(a) __readb((unsigned long)(a)) +#define __raw_readw(a) __readw((unsigned long)(a)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writeb(v,a) __writeb((v),(unsigned long)(a)) +#define __raw_writew(v,a) __writew((v),(unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_pyxis.h b/include/asm-alpha/core_pyxis.h index 213adf4ba..efdcd7d43 100644 --- a/include/asm-alpha/core_pyxis.h +++ b/include/asm-alpha/core_pyxis.h @@ -1,7 +1,6 @@ #ifndef __ALPHA_PYXIS__H__ #define __ALPHA_PYXIS__H__ -#include <linux/config.h> #include <linux/types.h> #include <asm/compiler.h> @@ -34,19 +33,17 @@ **------------------------------------------------------------------------*/ -/* CIA ADDRESS BIT DEFINITIONS - * - * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | \_/ \_/ - * | | | - * +-- IO space, not cached. Byte Enable --+ | - * Transfer Length --+ - * +/* PYXIS ADDRESS BIT DEFINITIONS * + * 3333 3333 3322 2222 2222 1111 1111 11 + * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- + * 1 000 + * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- + * | |\| + * | Byte Enable --+ | + * | Transfer Length --+ + * +-- IO space, not cached * * Byte Transfer * Enable Length Transfer Byte Address @@ -74,16 +71,19 @@ #define PYXIS_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */ #define PYXIS_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */ -#define PYXIS_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define PYXIS_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) +#define PYXIS_DMA_WIN_BASE (1UL*1024*1024*1024) +#define PYXIS_DMA_WIN_SIZE (2UL*1024*1024*1024) + +/* Window 0 at 1GB size 1GB mapping 0 */ +#define PYXIS_DMA_WIN0_BASE_DEFAULT (1UL*1024*1024*1024) +#define PYXIS_DMA_WIN0_SIZE_DEFAULT (1UL*1024*1024*1024) +#define PYXIS_DMA_WIN0_TRAN_DEFAULT (0UL) + +/* Window 0 at 2GB size 1GB mapping 1GB */ +#define PYXIS_DMA_WIN1_BASE_DEFAULT (2UL*1024*1024*1024) +#define PYXIS_DMA_WIN1_SIZE_DEFAULT (1UL*1024*1024*1024) +#define PYXIS_DMA_WIN1_TRAN_DEFAULT (1UL*1024*1024*1024) -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define PYXIS_DMA_WIN_BASE alpha_mv.dma_win_base -#define PYXIS_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define PYXIS_DMA_WIN_BASE PYXIS_DMA_WIN_BASE_DEFAULT -#define PYXIS_DMA_WIN_SIZE PYXIS_DMA_WIN_SIZE_DEFAULT -#endif /* * General Registers @@ -203,47 +203,47 @@ * Data structure for handling PYXIS machine checks: */ struct el_PYXIS_sysdata_mcheck { - u_long coma_gcr; - u_long coma_edsr; - u_long coma_ter; - u_long coma_elar; - u_long coma_ehar; - u_long coma_ldlr; - u_long coma_ldhr; - u_long coma_base0; - u_long coma_base1; - u_long coma_base2; - u_long coma_cnfg0; - u_long coma_cnfg1; - u_long coma_cnfg2; - u_long epic_dcsr; - u_long epic_pear; - u_long epic_sear; - u_long epic_tbr1; - u_long epic_tbr2; - u_long epic_pbr1; - u_long epic_pbr2; - u_long epic_pmr1; - u_long epic_pmr2; - u_long epic_harx1; - u_long epic_harx2; - u_long epic_pmlt; - u_long epic_tag0; - u_long epic_tag1; - u_long epic_tag2; - u_long epic_tag3; - u_long epic_tag4; - u_long epic_tag5; - u_long epic_tag6; - u_long epic_tag7; - u_long epic_data0; - u_long epic_data1; - u_long epic_data2; - u_long epic_data3; - u_long epic_data4; - u_long epic_data5; - u_long epic_data6; - u_long epic_data7; + u_long coma_gcr; + u_long coma_edsr; + u_long coma_ter; + u_long coma_elar; + u_long coma_ehar; + u_long coma_ldlr; + u_long coma_ldhr; + u_long coma_base0; + u_long coma_base1; + u_long coma_base2; + u_long coma_cnfg0; + u_long coma_cnfg1; + u_long coma_cnfg2; + u_long epic_dcsr; + u_long epic_pear; + u_long epic_sear; + u_long epic_tbr1; + u_long epic_tbr2; + u_long epic_pbr1; + u_long epic_pbr2; + u_long epic_pmr1; + u_long epic_pmr2; + u_long epic_harx1; + u_long epic_harx2; + u_long epic_pmlt; + u_long epic_tag0; + u_long epic_tag1; + u_long epic_tag2; + u_long epic_tag3; + u_long epic_tag4; + u_long epic_tag5; + u_long epic_tag6; + u_long epic_tag7; + u_long epic_data0; + u_long epic_data1; + u_long epic_data2; + u_long epic_data3; + u_long epic_data4; + u_long epic_data5; + u_long epic_data6; + u_long epic_data7; }; @@ -285,77 +285,40 @@ __EXTERN_INLINE void * pyxis_bus_to_virt(unsigned long address) #define vuip volatile unsigned int * #define vulp volatile unsigned long * -__EXTERN_INLINE unsigned int pyxis_bw_inb(unsigned long addr) -{ - return __kernel_ldbu(*(vucp)(addr+PYXIS_BW_IO)); -} - -__EXTERN_INLINE void pyxis_bw_outb(unsigned char b, unsigned long addr) -{ - __kernel_stb(b, *(vucp)(addr+PYXIS_BW_IO)); - mb(); -} - -__EXTERN_INLINE unsigned int pyxis_bw_inw(unsigned long addr) -{ - return __kernel_ldwu(*(vusp)(addr+PYXIS_BW_IO)); -} - -__EXTERN_INLINE void pyxis_bw_outw(unsigned short b, unsigned long addr) -{ - __kernel_stw(b, *(vusp)(addr+PYXIS_BW_IO)); - mb(); -} - -__EXTERN_INLINE unsigned int pyxis_bw_inl(unsigned long addr) -{ - return *(vuip)(addr+PYXIS_BW_IO); -} - -__EXTERN_INLINE void pyxis_bw_outl(unsigned int b, unsigned long addr) -{ - *(vuip)(addr+PYXIS_BW_IO) = b; - mb(); -} - __EXTERN_INLINE unsigned int pyxis_inb(unsigned long addr) { - long result = *(vip) ((addr << 5) + PYXIS_IO + 0x00); - return __kernel_extbl(result, addr & 3); + /* ??? I wish I could get rid of this. But there's no ioremap + equivalent for I/O space. PCI I/O can be forced into the + PYXIS I/O region, but that doesn't take care of legacy ISA crap. */ + + return __kernel_ldbu(*(vucp)(addr+PYXIS_BW_IO)); } __EXTERN_INLINE void pyxis_outb(unsigned char b, unsigned long addr) { - unsigned long w; - - w = __kernel_insbl(b, addr & 3); - *(vuip) ((addr << 5) + PYXIS_IO + 0x00) = w; + __kernel_stb(b, *(vucp)(addr+PYXIS_BW_IO)); mb(); } __EXTERN_INLINE unsigned int pyxis_inw(unsigned long addr) { - long result = *(vip) ((addr << 5) + PYXIS_IO + 0x08); - return __kernel_extwl(result, addr & 3); + return __kernel_ldwu(*(vusp)(addr+PYXIS_BW_IO)); } __EXTERN_INLINE void pyxis_outw(unsigned short b, unsigned long addr) { - unsigned long w; - - w = __kernel_inswl(b, addr & 3); - *(vuip) ((addr << 5) + PYXIS_IO + 0x08) = w; + __kernel_stw(b, *(vusp)(addr+PYXIS_BW_IO)); mb(); } __EXTERN_INLINE unsigned int pyxis_inl(unsigned long addr) { - return *(vuip) ((addr << 5) + PYXIS_IO + 0x18); + return *(vuip)(addr+PYXIS_BW_IO); } __EXTERN_INLINE void pyxis_outl(unsigned int b, unsigned long addr) { - *(vuip) ((addr << 5) + PYXIS_IO + 0x18) = b; + *(vuip)(addr+PYXIS_BW_IO) = b; mb(); } @@ -363,8 +326,8 @@ __EXTERN_INLINE void pyxis_outl(unsigned int b, unsigned long addr) /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. - * - * For reading and writing 8 and 16 bit quantities we need to + * + * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 @@ -373,10 +336,10 @@ __EXTERN_INLINE void pyxis_outl(unsigned int b, unsigned long addr) * See p 6-17 of the specification but it looks something like this: * * 21164 Address: - * - * 3 2 1 + * + * 3 2 1 * 9876543210987654321098765432109876543210 - * 1ZZZZ0.PCI.QW.Address............BBLL + * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset @@ -384,201 +347,62 @@ __EXTERN_INLINE void pyxis_outl(unsigned int b, unsigned long addr) * * PCI Address: * - * 3 2 1 + * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR - * + * */ -__EXTERN_INLINE unsigned long pyxis_bw_readb(unsigned long addr) -{ - return __kernel_ldbu(*(vucp)(addr+PYXIS_BW_MEM)); -} - -__EXTERN_INLINE unsigned long pyxis_bw_readw(unsigned long addr) -{ - return __kernel_ldwu(*(vusp)(addr+PYXIS_BW_MEM)); -} - -__EXTERN_INLINE unsigned long pyxis_bw_readl(unsigned long addr) -{ - return *(vuip)(addr+PYXIS_BW_MEM); -} - -__EXTERN_INLINE unsigned long pyxis_bw_readq(unsigned long addr) -{ - return *(vulp)(addr+PYXIS_BW_MEM); -} - -__EXTERN_INLINE void pyxis_bw_writeb(unsigned char b, unsigned long addr) -{ - __kernel_stb(b, *(vucp)(addr+PYXIS_BW_MEM)); - mb(); -} - -__EXTERN_INLINE void pyxis_bw_writew(unsigned short b, unsigned long addr) -{ - __kernel_stw(b, *(vusp)(addr+PYXIS_BW_MEM)); - mb(); -} - -__EXTERN_INLINE void pyxis_bw_writel(unsigned int b, unsigned long addr) -{ - *(vuip)(addr+PYXIS_BW_MEM) = b; -} - -__EXTERN_INLINE void pyxis_bw_writeq(unsigned long b, unsigned long addr) -{ - *(vulp)(addr+PYXIS_BW_MEM) = b; -} - -__EXTERN_INLINE unsigned long pyxis_srm_base(unsigned long addr) -{ - unsigned long mask, base; - - if (addr >= alpha_mv.sm_base_r1 - && addr <= alpha_mv.sm_base_r1 + PYXIS_MEM_R1_MASK) { - mask = PYXIS_MEM_R1_MASK; - base = PYXIS_SPARSE_MEM; - } - else if (addr >= alpha_mv.sm_base_r2 - && addr <= alpha_mv.sm_base_r2 + PYXIS_MEM_R2_MASK) { - mask = PYXIS_MEM_R2_MASK; - base = PYXIS_SPARSE_MEM_R2; - } - else if (addr >= alpha_mv.sm_base_r3 - && addr <= alpha_mv.sm_base_r3 + PYXIS_MEM_R3_MASK) { - mask = PYXIS_MEM_R3_MASK; - base = PYXIS_SPARSE_MEM_R3; - } - else - { -#if 0 - printk("pyxis: address 0x%lx not covered by HAE\n", addr); -#endif - return 0; - } - - return ((addr & mask) << 5) + base; -} - -__EXTERN_INLINE unsigned long pyxis_srm_readb(unsigned long addr) -{ - unsigned long result, work; - - if ((work = pyxis_srm_base(addr)) == 0) - return 0xff; - work += 0x00; /* add transfer length */ - - result = *(vip) work; - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE unsigned long pyxis_srm_readw(unsigned long addr) -{ - unsigned long result, work; - - if ((work = pyxis_srm_base(addr)) == 0) - return 0xffff; - work += 0x08; /* add transfer length */ - - result = *(vip) work; - return __kernel_extwl(result, addr & 3); -} - -__EXTERN_INLINE void pyxis_srm_writeb(unsigned char b, unsigned long addr) -{ - unsigned long work = pyxis_srm_base(addr); - if (work) { - work += 0x00; /* add transfer length */ - *(vuip) work = b * 0x01010101; - } -} - -__EXTERN_INLINE void pyxis_srm_writew(unsigned short b, unsigned long addr) -{ - unsigned long work = pyxis_srm_base(addr); - if (work) { - work += 0x08; /* add transfer length */ - *(vuip) work = b * 0x00010001; - } -} - __EXTERN_INLINE unsigned long pyxis_readb(unsigned long addr) { - unsigned long result, msb, work, temp; - - msb = addr & 0xE0000000UL; - temp = addr & PYXIS_MEM_R1_MASK ; - set_hae(msb); - - work = ((temp << 5) + PYXIS_SPARSE_MEM + 0x00); - result = *(vip) work; - return __kernel_extbl(result, addr & 3); + return __kernel_ldbu(*(vucp)addr); } __EXTERN_INLINE unsigned long pyxis_readw(unsigned long addr) { - unsigned long result, msb, work, temp; - - msb = addr & 0xE0000000UL; - temp = addr & PYXIS_MEM_R1_MASK ; - set_hae(msb); - - work = ((temp << 5) + PYXIS_SPARSE_MEM + 0x08); - result = *(vip) work; - return __kernel_extwl(result, addr & 3); + return __kernel_ldwu(*(vusp)addr); } -__EXTERN_INLINE void pyxis_writeb(unsigned char b, unsigned long addr) +__EXTERN_INLINE unsigned long pyxis_readl(unsigned long addr) { - unsigned long msb ; - - msb = addr & 0xE0000000 ; - addr &= PYXIS_MEM_R1_MASK ; - set_hae(msb); - - *(vuip) ((addr << 5) + PYXIS_SPARSE_MEM + 0x00) = b * 0x01010101; + return *(vuip)addr; } -__EXTERN_INLINE void pyxis_writew(unsigned short b, unsigned long addr) +__EXTERN_INLINE unsigned long pyxis_readq(unsigned long addr) { - unsigned long msb ; - - msb = addr & 0xE0000000 ; - addr &= PYXIS_MEM_R1_MASK ; - set_hae(msb); - - *(vuip) ((addr << 5) + PYXIS_SPARSE_MEM + 0x08) = b * 0x00010001; + return *(vulp)addr; } -__EXTERN_INLINE unsigned long pyxis_readl(unsigned long addr) +__EXTERN_INLINE void pyxis_writeb(unsigned char b, unsigned long addr) { - return *(vuip) (addr + PYXIS_DENSE_MEM); + __kernel_stb(b, *(vucp)addr); } -__EXTERN_INLINE unsigned long pyxis_readq(unsigned long addr) +__EXTERN_INLINE void pyxis_writew(unsigned short b, unsigned long addr) { - return *(vulp) (addr + PYXIS_DENSE_MEM); + __kernel_stw(b, *(vusp)addr); } __EXTERN_INLINE void pyxis_writel(unsigned int b, unsigned long addr) { - *(vuip) (addr + PYXIS_DENSE_MEM) = b; + *(vuip)addr = b; } __EXTERN_INLINE void pyxis_writeq(unsigned long b, unsigned long addr) { - *(vulp) (addr + PYXIS_DENSE_MEM) = b; + *(vulp)addr = b; } -/* Find the DENSE memory area for a given bus address. */ +__EXTERN_INLINE unsigned long pyxis_ioremap(unsigned long addr) +{ + return addr + PYXIS_BW_MEM; +} -__EXTERN_INLINE unsigned long pyxis_dense_mem(unsigned long addr) +__EXTERN_INLINE int pyxis_is_ioaddr(unsigned long addr) { - return PYXIS_DENSE_MEM; + return addr >= IDENT_ADDR + 0x8740000000UL; } #undef vucp @@ -592,69 +416,37 @@ __EXTERN_INLINE unsigned long pyxis_dense_mem(unsigned long addr) #define virt_to_bus pyxis_virt_to_bus #define bus_to_virt pyxis_bus_to_virt -#if defined(BWIO_ENABLED) && !defined(CONFIG_ALPHA_RUFFIAN) -# define __inb pyxis_bw_inb -# define __inw pyxis_bw_inw -# define __inl pyxis_bw_inl -# define __outb pyxis_bw_outb -# define __outw pyxis_bw_outw -# define __outl pyxis_bw_outl -# define __readb pyxis_bw_readb -# define __readw pyxis_bw_readw -# define __writeb pyxis_bw_writeb -# define __writew pyxis_bw_writew -# define __readl pyxis_bw_readl -# define __readq pyxis_bw_readq -# define __writel pyxis_bw_writel -# define __writeq pyxis_bw_writeq -#else -# define __inb pyxis_inb -# define __inw pyxis_inw -# define __inl pyxis_inl -# define __outb pyxis_outb -# define __outw pyxis_outw -# define __outl pyxis_outl -# ifdef CONFIG_ALPHA_SRM_SETUP -# define __readb pyxis_srm_readb -# define __readw pyxis_srm_readw -# define __writeb pyxis_srm_writeb -# define __writew pyxis_srm_writew -# else -# define __readb pyxis_readb -# define __readw pyxis_readw -# define __writeb pyxis_writeb -# define __writew pyxis_writew -# endif -# define __readl pyxis_readl -# define __readq pyxis_readq -# define __writel pyxis_writel -# define __writeq pyxis_writeq -#endif /* BWIO */ - -#define dense_mem pyxis_dense_mem - -#if defined(BWIO_ENABLED) && !defined(CONFIG_ALPHA_RUFFIAN) -# define inb(port) __inb((port)) -# define inw(port) __inw((port)) -# define inl(port) __inl((port)) -# define outb(x, port) __outb((x),(port)) -# define outw(x, port) __outw((x),(port)) -# define outl(x, port) __outl((x),(port)) -# define readb(addr) __readb((addr)) -# define readw(addr) __readw((addr)) -# define writeb(b, addr) __writeb((b),(addr)) -# define writew(b, addr) __writew((b),(addr)) -#else -# define inb(port) \ - (__builtin_constant_p((port))?__inb(port):_inb(port)) -# define outb(x, port) \ - (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) -#endif /* BWIO */ - -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __inb pyxis_inb +#define __inw pyxis_inw +#define __inl pyxis_inl +#define __outb pyxis_outb +#define __outw pyxis_outw +#define __outl pyxis_outl +#define __readb pyxis_readb +#define __readw pyxis_readw +#define __writeb pyxis_writeb +#define __writew pyxis_writew +#define __readl pyxis_readl +#define __readq pyxis_readq +#define __writel pyxis_writel +#define __writeq pyxis_writeq +#define __ioremap pyxis_ioremap +#define __is_ioaddr pyxis_is_ioaddr + +#define inb(port) __inb((port)) +#define inw(port) __inw((port)) +#define inl(port) __inl((port)) +#define outb(x, port) __outb((x),(port)) +#define outw(x, port) __outw((x),(port)) +#define outl(x, port) __outl((x),(port)) +#define __raw_readb(addr) __readb((addr)) +#define __raw_readw(addr) __readw((addr)) +#define __raw_writeb(b, addr) __writeb((b),(addr)) +#define __raw_writew(b, addr) __writew((b),(addr)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_t2.h b/include/asm-alpha/core_t2.h index fdb0f82fe..933be1714 100644 --- a/include/asm-alpha/core_t2.h +++ b/include/asm-alpha/core_t2.h @@ -21,16 +21,8 @@ #define T2_MEM_R1_MASK 0x03ffffff /* Mem sparse region 1 mask is 26 bits */ -#define T2_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define T2_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define T2_DMA_WIN_BASE alpha_mv.dma_win_base -#define T2_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define T2_DMA_WIN_BASE T2_DMA_WIN_BASE_DEFAULT -#define T2_DMA_WIN_SIZE T2_DMA_WIN_SIZE_DEFAULT -#endif +#define T2_DMA_WIN_BASE (1UL*1024*1024*1024) +#define T2_DMA_WIN_SIZE (1UL*1024*1024*1024) /* GAMMA-SABLE is a SABLE with EV5-based CPUs */ #define _GAMMA_BIAS 0x8000000000UL @@ -78,33 +70,33 @@ 3.8fff.ffff * * +--------------+ 3 8000 0000 - * | CPU 0 CSRs | + * | CPU 0 CSRs | * +--------------+ 3 8100 0000 - * | CPU 1 CSRs | + * | CPU 1 CSRs | * +--------------+ 3 8200 0000 - * | CPU 2 CSRs | + * | CPU 2 CSRs | * +--------------+ 3 8300 0000 - * | CPU 3 CSRs | + * | CPU 3 CSRs | * +--------------+ 3 8400 0000 - * | CPU Reserved | + * | CPU Reserved | * +--------------+ 3 8700 0000 - * | Mem Reserved | + * | Mem Reserved | * +--------------+ 3 8800 0000 - * | Mem 0 CSRs | + * | Mem 0 CSRs | * +--------------+ 3 8900 0000 - * | Mem 1 CSRs | + * | Mem 1 CSRs | * +--------------+ 3 8a00 0000 - * | Mem 2 CSRs | + * | Mem 2 CSRs | * +--------------+ 3 8b00 0000 - * | Mem 3 CSRs | - * +--------------+ 3 8c00 0000 - * | Mem Reserved | - * +--------------+ 3 8e00 0000 - * | PCI Bridge | - * +--------------+ 3 8f00 0000 - * | Expansion IO | - * +--------------+ 3 9000 0000 - * + * | Mem 3 CSRs | + * +--------------+ 3 8c00 0000 + * | Mem Reserved | + * +--------------+ 3 8e00 0000 + * | PCI Bridge | + * +--------------+ 3 8f00 0000 + * | Expansion IO | + * +--------------+ 3 9000 0000 + * * */ #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L) @@ -176,7 +168,7 @@ struct el_t2_procdata_mcheck { unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */ }; -/* +/* * Sable processor specific Machine Check Data segment. */ @@ -184,7 +176,7 @@ struct el_t2_logout_header { unsigned int elfl_size; /* size in bytes of logout area. */ int elfl_sbz1:31; /* Should be zero. */ char elfl_retry:1; /* Retry flag. */ - unsigned int elfl_procoffset; /* Processor-specific offset. */ + unsigned int elfl_procoffset; /* Processor-specific offset. */ unsigned int elfl_sysoffset; /* Offset of system-specific. */ unsigned int elfl_error_type; /* PAL error type code. */ unsigned int elfl_frame_rev; /* PAL Frame revision. */ @@ -233,7 +225,7 @@ struct el_t2_data_memory { */ struct el_t2_data_other_cpu { short elco_cpuid; /* CPU ID */ - short elco_res02[3]; + short elco_res02[3]; unsigned long elco_bcc; /* CSR 0 */ unsigned long elco_bcce; /* CSR 1 */ unsigned long elco_bccea; /* CSR 2 */ @@ -256,7 +248,7 @@ struct el_t2_data_other_cpu { * Sable other CPU error frame - sable pfms section 3.44 */ struct el_t2_data_t2{ - struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ + struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ unsigned long elct_iocsr; /* IO Control and Status Register */ unsigned long elct_cerr1; /* Cbus Error Register 1 */ unsigned long elct_cerr2; /* Cbus Error Register 2 */ @@ -294,31 +286,31 @@ struct el_t2_data_corrected { unsigned long elcpb_bc_tag; }; -/* +/* * Sable error log data structure * Note there are 4 memory slots on sable (see t2.h) */ struct el_t2_frame_mcheck { - struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ + struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ struct el_t2_logout_header elfmc_hdr; struct el_t2_procdata_mcheck elfmc_procdata; struct el_t2_sysdata_mcheck elfmc_sysdata; struct el_t2_data_t2 elfmc_t2data; - struct el_t2_data_memory elfmc_memdata[4]; - struct el_t2_frame_header elfmc_footer; /* empty */ + struct el_t2_data_memory elfmc_memdata[4]; + struct el_t2_frame_header elfmc_footer; /* empty */ }; -/* +/* * Sable error log data structures on memory errors */ struct el_t2_frame_corrected { - struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ + struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ struct el_t2_logout_header elfcc_hdr; - struct el_t2_data_corrected elfcc_procdata; + struct el_t2_data_corrected elfcc_procdata; /* struct el_t2_data_t2 elfcc_t2data; */ /* struct el_t2_data_memory elfcc_memdata[4]; */ - struct el_t2_frame_header elfcc_footer; /* empty */ + struct el_t2_frame_header elfcc_footer; /* empty */ }; @@ -398,10 +390,9 @@ __EXTERN_INLINE void t2_outl(unsigned int b, unsigned long addr) /* - * Memory functions. 64-bit and 32-bit accesses are done through - * dense memory space, everything else through sparse space. - * - * For reading and writing 8 and 16 bit quantities we need to + * Memory functions. + * + * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 @@ -410,10 +401,10 @@ __EXTERN_INLINE void t2_outl(unsigned int b, unsigned long addr) * See p 6-17 of the specification but it looks something like this: * * 21164 Address: - * - * 3 2 1 + * + * 3 2 1 * 9876543210987654321098765432109876543210 - * 1ZZZZ0.PCI.QW.Address............BBLL + * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset @@ -421,127 +412,23 @@ __EXTERN_INLINE void t2_outl(unsigned int b, unsigned long addr) * * PCI Address: * - * 3 2 1 + * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR - * + * */ -__EXTERN_INLINE unsigned long t2_srm_base(unsigned long addr) -{ - if ((addr >= alpha_mv.sm_base_r1 - && addr <= alpha_mv.sm_base_r1 + T2_MEM_R1_MASK) - || (addr >= 512*1024 && addr < 1024*1024)) { - return ((addr & T2_MEM_R1_MASK) << 5) + T2_SPARSE_MEM; - } -#if 0 - printk("T2: address 0x%lx not covered by HAE\n", addr); -#endif - return 0; -} - -__EXTERN_INLINE unsigned long t2_srm_readb(unsigned long addr) -{ - unsigned long result, work; - - if ((work = t2_srm_base(addr)) == 0) - return 0xff; - work += 0x00; /* add transfer length */ - - result = *(vip) work; - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE unsigned long t2_srm_readw(unsigned long addr) -{ - unsigned long result, work; - - if ((work = t2_srm_base(addr)) == 0) - return 0xffff; - work += 0x08; /* add transfer length */ - - result = *(vip) work; - return __kernel_extwl(result, addr & 3); -} - -/* On SABLE with T2, we must use SPARSE memory even for 32-bit access ... */ -__EXTERN_INLINE unsigned long t2_srm_readl(unsigned long addr) -{ - unsigned long work; - - if ((work = t2_srm_base(addr)) == 0) - return 0xffffffff; - work += 0x18; /* add transfer length */ - - return *(vuip) work; -} - -/* ... which makes me wonder why we advertise we have DENSE memory at all. - Anyway, guess that means we should emulate 64-bit access as two cycles. */ -__EXTERN_INLINE unsigned long t2_srm_readq(unsigned long addr) -{ - unsigned long work, r0, r1; - - if ((work = t2_srm_base(addr)) == 0) - return ~0UL; - work += 0x18; /* add transfer length */ - - r0 = *(vuip) work; - r1 = *(vuip) (work + (4 << 5)); - return r1 << 32 | r0; -} - -__EXTERN_INLINE void t2_srm_writeb(unsigned char b, unsigned long addr) -{ - unsigned long work = t2_srm_base(addr); - if (work) { - work += 0x00; /* add transfer length */ - *(vuip) work = b * 0x01010101; - } -} - -__EXTERN_INLINE void t2_srm_writew(unsigned short b, unsigned long addr) -{ - unsigned long work = t2_srm_base(addr); - if (work) { - work += 0x08; /* add transfer length */ - *(vuip) work = b * 0x00010001; - } -} - -/* On SABLE with T2, we must use SPARSE memory even for 32-bit access ... */ -__EXTERN_INLINE void t2_srm_writel(unsigned int b, unsigned long addr) -{ - unsigned long work = t2_srm_base(addr); - if (work) { - work += 0x18; /* add transfer length */ - *(vuip) work = b; - } -} - -/* ... which makes me wonder why we advertise we have DENSE memory at all. - Anyway, guess that means we should emulate 64-bit access as two cycles. */ -__EXTERN_INLINE void t2_srm_writeq(unsigned long b, unsigned long addr) -{ - unsigned long work = t2_srm_base(addr); - if (work) { - work += 0x18; /* add transfer length */ - *(vuip) work = b; - *(vuip) (work + (4 << 5)) = b >> 32; - } -} - __EXTERN_INLINE unsigned long t2_readb(unsigned long addr) { unsigned long result, msb; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); - result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00) ; + result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00); return __kernel_extbl(result, addr & 3); } @@ -549,8 +436,8 @@ __EXTERN_INLINE unsigned long t2_readw(unsigned long addr) { unsigned long result, msb; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); @@ -562,8 +449,8 @@ __EXTERN_INLINE unsigned long t2_readl(unsigned long addr) { unsigned long msb; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); return *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); @@ -573,8 +460,8 @@ __EXTERN_INLINE unsigned long t2_readq(unsigned long addr) { unsigned long r0, r1, work, msb; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); work = (addr << 5) + T2_SPARSE_MEM + 0x18; @@ -585,33 +472,35 @@ __EXTERN_INLINE unsigned long t2_readq(unsigned long addr) __EXTERN_INLINE void t2_writeb(unsigned char b, unsigned long addr) { - unsigned long msb ; + unsigned long msb, w; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); - *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = b * 0x01010101; + w = __kernel_insbl(b, addr & 3); + *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; } __EXTERN_INLINE void t2_writew(unsigned short b, unsigned long addr) { - unsigned long msb ; + unsigned long msb, w; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); - *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = b * 0x00010001; + w = __kernel_inswl(b, addr & 3); + *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w; } /* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */ __EXTERN_INLINE void t2_writel(unsigned int b, unsigned long addr) { - unsigned long msb ; + unsigned long msb; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b; @@ -619,10 +508,10 @@ __EXTERN_INLINE void t2_writel(unsigned int b, unsigned long addr) __EXTERN_INLINE void t2_writeq(unsigned long b, unsigned long addr) { - unsigned long msb, work; + unsigned long msb, work; - msb = addr & 0xE0000000 ; - addr &= T2_MEM_R1_MASK ; + msb = addr & 0xE0000000; + addr &= T2_MEM_R1_MASK; set_hae(msb); work = (addr << 5) + T2_SPARSE_MEM + 0x18; @@ -630,11 +519,14 @@ __EXTERN_INLINE void t2_writeq(unsigned long b, unsigned long addr) *(vuip)(work + (4 << 5)) = b >> 32; } -/* Find the DENSE memory area for a given bus address. */ +__EXTERN_INLINE unsigned long t2_ioremap(unsigned long addr) +{ + return addr; +} -__EXTERN_INLINE unsigned long t2_dense_mem(unsigned long addr) +__EXTERN_INLINE int t2_is_ioaddr(unsigned long addr) { - return T2_DENSE_MEM; + return (long)addr >= 0; } #undef vip @@ -650,17 +542,6 @@ __EXTERN_INLINE unsigned long t2_dense_mem(unsigned long addr) #define __outb t2_outb #define __outw t2_outw #define __outl t2_outl - -#ifdef CONFIG_ALPHA_SRM_SETUP -#define __readb t2_srm_readb -#define __readw t2_srm_readw -#define __readl t2_srm_readl -#define __readq t2_srm_readq -#define __writeb t2_srm_writeb -#define __writew t2_srm_writew -#define __writel t2_srm_writel -#define __writeq t2_srm_writeq -#else #define __readb t2_readb #define __readw t2_readw #define __readl t2_readl @@ -669,15 +550,13 @@ __EXTERN_INLINE unsigned long t2_dense_mem(unsigned long addr) #define __writew t2_writew #define __writel t2_writel #define __writeq t2_writeq -#endif - -#define dense_mem t2_dense_mem +#define __ioremap t2_ioremap +#define __is_ioaddr t2_is_ioaddr #define inb(port) \ -(__builtin_constant_p((port))?__inb(port):_inb(port)) - + (__builtin_constant_p((port))?__inb(port):_inb(port)) #define outb(x, port) \ -(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/core_tsunami.h b/include/asm-alpha/core_tsunami.h index 68d30cf86..14bc80e2d 100644 --- a/include/asm-alpha/core_tsunami.h +++ b/include/asm-alpha/core_tsunami.h @@ -1,7 +1,6 @@ #ifndef __ALPHA_TSUNAMI__H__ #define __ALPHA_TSUNAMI__H__ -#include <linux/config.h> #include <linux/types.h> #include <asm/compiler.h> @@ -16,16 +15,25 @@ * */ -#define TSUNAMI_DMA_WIN_BASE_DEFAULT (1024*1024*1024U) -#define TSUNAMI_DMA_WIN_SIZE_DEFAULT (1024*1024*1024U) +/* + * We must actually use 2 windows to direct-map the 2GB space, because + * of an "idiot-syncracy" of the CYPRESS chip used on DS20 and others. + * It may respond to a PCI bus address in the last 1MB of the 4GB + * address range, and that is where real memory may appear. + * + * Sigh... + */ +#define TSUNAMI_DMA_WIN_BASE (1UL*1024*1024*1024) +#define TSUNAMI_DMA_WIN_SIZE (2UL*1024*1024*1024) + +#define TSUNAMI_DMA_WIN0_BASE_DEFAULT (1UL*1024*1024*1024) +#define TSUNAMI_DMA_WIN0_SIZE_DEFAULT (1UL*1024*1024*1024) +#define TSUNAMI_DMA_WIN0_TRAN_DEFAULT (0UL) + +#define TSUNAMI_DMA_WIN1_BASE_DEFAULT (2UL*1024*1024*1024) +#define TSUNAMI_DMA_WIN1_SIZE_DEFAULT (1UL*1024*1024*1024) +#define TSUNAMI_DMA_WIN1_TRAN_DEFAULT (1UL*1024*1024*1024) -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) -#define TSUNAMI_DMA_WIN_BASE alpha_mv.dma_win_base -#define TSUNAMI_DMA_WIN_SIZE alpha_mv.dma_win_size -#else -#define TSUNAMI_DMA_WIN_BASE TSUNAMI_DMA_WIN_BASE_DEFAULT -#define TSUNAMI_DMA_WIN_SIZE TSUNAMI_DMA_WIN_SIZE_DEFAULT -#endif /* XXX: Do we need to conditionalize on this? */ #ifdef USE_48_BIT_KSEG @@ -142,7 +150,7 @@ union TPchipPERROR { unsigned perror_v_rsvd2 : 1; unsigned perror_v_cmd : 4; unsigned perror_v_syn : 8; - } perror_r_bits; + } perror_r_bits; int perror_q_whole [2]; }; @@ -162,7 +170,7 @@ union TPchipWSBA { unsigned wsba_v_rsvd1 : 17; unsigned wsba_v_addr : 12; unsigned wsba_v_rsvd2 : 32; - } wsba_r_bits; + } wsba_r_bits; int wsba_q_whole [2]; }; @@ -256,21 +264,32 @@ union TPchipPERRMASK { unsigned perrmask_v_cre : 1; unsigned perrmask_v_rsvd1 : 20; unsigned perrmask_v_rsvd2 : 32; - } perrmask_r_bits; + } perrmask_r_bits; int perrmask_q_whole [2]; }; /* * Memory spaces: */ -#define HOSE(h) (((unsigned long)(h)) << 33) +#define TSUNAMI_HOSE(h) (((unsigned long)(h)) << 33) +#define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS) + +#define TSUNAMI_MEM(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL) +#define _TSUNAMI_IACK_SC(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL) +#define TSUNAMI_IO(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL) +#define TSUNAMI_CONF(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL) -#define TSUNAMI_MEM(h) (IDENT_ADDR + TS_BIAS + 0x000000000UL + HOSE(h)) -#define _TSUNAMI_IACK_SC(h) (IDENT_ADDR + TS_BIAS + 0x1F8000000UL + HOSE(h)) -#define TSUNAMI_IO(h) (IDENT_ADDR + TS_BIAS + 0x1FC000000UL + HOSE(h)) -#define TSUNAMI_CONF(h) (IDENT_ADDR + TS_BIAS + 0x1FE000000UL + HOSE(h)) +#define TSUNAMI_IACK_SC _TSUNAMI_IACK_SC(0) /* hack! */ -#define TSUNAMI_IACK_SC _TSUNAMI_IACK_SC(0) /* hack! */ + +/* + * The canonical non-remaped I/O and MEM addresses have these values + * subtracted out. This is arranged so that folks manipulating ISA + * devices can use their familiar numbers and have them map to bus 0. + */ + +#define TSUNAMI_IO_BIAS TSUNAMI_IO(0) +#define TSUNAMI_MEM_BIAS TSUNAMI_MEM(0) /* @@ -313,39 +332,47 @@ __EXTERN_INLINE void * tsunami_bus_to_virt(unsigned long address) #define vuip volatile unsigned int * #define vulp volatile unsigned long * -#define XADDR ((addr) & 0xffffffffUL) -#define XHOSE (((addr) >> 32) & 3UL) - __EXTERN_INLINE unsigned int tsunami_inb(unsigned long addr) { - return __kernel_ldbu(*(vucp)(XADDR + TSUNAMI_IO(XHOSE))); + /* ??? I wish I could get rid of this. But there's no ioremap + equivalent for I/O space. PCI I/O can be forced into the + correct hose's I/O region, but that doesn't take care of + legacy ISA crap. */ + + addr += TSUNAMI_IO_BIAS; + return __kernel_ldbu(*(vucp)addr); } __EXTERN_INLINE void tsunami_outb(unsigned char b, unsigned long addr) { - __kernel_stb(b, *(vucp)(XADDR + TSUNAMI_IO(XHOSE))); + addr += TSUNAMI_IO_BIAS; + __kernel_stb(b, *(vucp)addr); mb(); } __EXTERN_INLINE unsigned int tsunami_inw(unsigned long addr) { - return __kernel_ldwu(*(vusp)(XADDR + TSUNAMI_IO(XHOSE))); + addr += TSUNAMI_IO_BIAS; + return __kernel_ldwu(*(vusp)addr); } __EXTERN_INLINE void tsunami_outw(unsigned short b, unsigned long addr) { - __kernel_stw(b, *(vusp)(XADDR + TSUNAMI_IO(XHOSE))); + addr += TSUNAMI_IO_BIAS; + __kernel_stw(b, *(vusp)addr); mb(); } __EXTERN_INLINE unsigned int tsunami_inl(unsigned long addr) { - return *(vuip)(XADDR + TSUNAMI_IO(XHOSE)); + addr += TSUNAMI_IO_BIAS; + return *(vuip)addr; } __EXTERN_INLINE void tsunami_outl(unsigned int b, unsigned long addr) { - *(vuip)(XADDR + TSUNAMI_IO(XHOSE)) = b; + addr += TSUNAMI_IO_BIAS; + *(vuip)addr = b; mb(); } @@ -353,55 +380,54 @@ __EXTERN_INLINE void tsunami_outl(unsigned int b, unsigned long addr) * Memory functions. all accesses are done through linear space. */ +__EXTERN_INLINE unsigned long tsunami_ioremap(unsigned long addr) +{ + return addr + TSUNAMI_MEM_BIAS; +} + +__EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr) +{ + return addr >= TSUNAMI_BASE; +} + __EXTERN_INLINE unsigned long tsunami_readb(unsigned long addr) { - return __kernel_ldbu(*(vucp)(XADDR + TSUNAMI_MEM(XHOSE))); + return __kernel_ldbu(*(vucp)addr); } __EXTERN_INLINE unsigned long tsunami_readw(unsigned long addr) { - return __kernel_ldwu(*(vusp)(XADDR + TSUNAMI_MEM(XHOSE))); + return __kernel_ldwu(*(vusp)addr); } __EXTERN_INLINE unsigned long tsunami_readl(unsigned long addr) { - return *(vuip)(XADDR + TSUNAMI_MEM(XHOSE)); + return *(vuip)addr; } __EXTERN_INLINE unsigned long tsunami_readq(unsigned long addr) { - return *(vulp)(XADDR + TSUNAMI_MEM(XHOSE)); + return *(vulp)addr; } __EXTERN_INLINE void tsunami_writeb(unsigned char b, unsigned long addr) { - __kernel_stb(b, *(vucp)(XADDR + TSUNAMI_MEM(XHOSE))); - mb(); + __kernel_stb(b, *(vucp)addr); } __EXTERN_INLINE void tsunami_writew(unsigned short b, unsigned long addr) { - __kernel_stw(b, *(vusp)(XADDR + TSUNAMI_MEM(XHOSE))); - mb(); + __kernel_stw(b, *(vusp)addr); } __EXTERN_INLINE void tsunami_writel(unsigned int b, unsigned long addr) { - *(vuip)(XADDR + TSUNAMI_MEM(XHOSE)) = b; - mb(); + *(vuip)addr = b; } __EXTERN_INLINE void tsunami_writeq(unsigned long b, unsigned long addr) { - *(vulp)(XADDR + TSUNAMI_MEM(XHOSE)) = b; - mb(); -} - -/* Find the DENSE memory area for a given bus address. */ - -__EXTERN_INLINE unsigned long tsunami_dense_mem(unsigned long addr) -{ - return TSUNAMI_MEM(XHOSE); + *(vulp)addr = b; } #undef vucp @@ -409,9 +435,6 @@ __EXTERN_INLINE unsigned long tsunami_dense_mem(unsigned long addr) #undef vuip #undef vulp -#undef XADDR -#undef XHOSE - #ifdef __WANT_IO_DEF #define virt_to_bus tsunami_virt_to_bus @@ -431,25 +454,24 @@ __EXTERN_INLINE unsigned long tsunami_dense_mem(unsigned long addr) #define __readq tsunami_readq #define __writel tsunami_writel #define __writeq tsunami_writeq -#define dense_mem tsunami_dense_mem - -#define inb(port) __inb((port)) -#define inw(port) __inw((port)) -#define inl(port) __inl((port)) - -#define outb(v, port) __outb((v),(port)) -#define outw(v, port) __outw((v),(port)) -#define outl(v, port) __outl((v),(port)) - -#define readb(a) __readb((unsigned long)(a)) -#define readw(a) __readw((unsigned long)(a)) -#define readl(a) __readl((unsigned long)(a)) -#define readq(a) __readq((unsigned long)(a)) - -#define writeb(v,a) __writeb((v),(unsigned long)(a)) -#define writew(v,a) __writew((v),(unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) -#define writeq(v,a) __writeq((v),(unsigned long)(a)) +#define __ioremap tsunami_ioremap +#define __is_ioaddr tsunami_is_ioaddr + +#define inb(port) __inb((port)) +#define inw(port) __inw((port)) +#define inl(port) __inl((port)) +#define outb(v, port) __outb((v),(port)) +#define outw(v, port) __outw((v),(port)) +#define outl(v, port) __outl((v),(port)) + +#define __raw_readb(a) __readb((unsigned long)(a)) +#define __raw_readw(a) __readw((unsigned long)(a)) +#define __raw_readl(a) __readl((unsigned long)(a)) +#define __raw_readq(a) __readq((unsigned long)(a)) +#define __raw_writeb(v,a) __writeb((v),(unsigned long)(a)) +#define __raw_writew(v,a) __writew((v),(unsigned long)(a)) +#define __raw_writel(v,a) __writel((v),(unsigned long)(a)) +#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a)) #endif /* __WANT_IO_DEF */ diff --git a/include/asm-alpha/delay.h b/include/asm-alpha/delay.h index a55752abb..f60e9b5a7 100644 --- a/include/asm-alpha/delay.h +++ b/include/asm-alpha/delay.h @@ -12,9 +12,13 @@ extern __inline__ void __delay(unsigned long loops) { - __asm__ __volatile__(".align 3\n" - "1:\tsubq %0,1,%0\n\t" - "bge %0,1b": "=r" (loops) : "0" (loops)); + register unsigned long r0 __asm__("$0") = loops; +#ifdef MODULE + __asm__ __volatile__("lda $28,___delay; jsr $28,($28),0" + : "=r"(r0) : "r"(r0) : "$28"); +#else + __asm__ __volatile__("bsr $28,___delay" : "=r"(r0) : "r"(r0) : "$28"); +#endif } /* diff --git a/include/asm-alpha/dma.h b/include/asm-alpha/dma.h index d415b2a7e..28762e674 100644 --- a/include/asm-alpha/dma.h +++ b/include/asm-alpha/dma.h @@ -19,8 +19,8 @@ #define _ASM_DMA_H #include <linux/config.h> +#include <linux/spinlock.h> #include <asm/io.h> -#include <asm/spinlock.h> #define dma_outb outb #define dma_inb inb @@ -346,10 +346,11 @@ extern int check_dma(unsigned int dmanr); /* From PCI */ -#ifdef CONFIG_PCI_QUIRKS +#ifdef CONFIG_PCI extern int isa_dma_bridge_buggy; #else #define isa_dma_bridge_buggy (0) #endif + #endif /* _ASM_DMA_H */ diff --git a/include/asm-alpha/hardirq.h b/include/asm-alpha/hardirq.h index 1468b28e3..31cdbac06 100644 --- a/include/asm-alpha/hardirq.h +++ b/include/asm-alpha/hardirq.h @@ -3,10 +3,14 @@ /* Initially just a straight copy of the i386 code. */ -#include <linux/tasks.h> +#include <linux/threads.h> -extern unsigned int local_irq_count[NR_CPUS]; -extern unsigned long hardirq_no[NR_CPUS]; +#ifndef __SMP__ +extern int __local_irq_count; +#define local_irq_count(cpu) ((void)(cpu), __local_irq_count) +#else +#define local_irq_count(cpu) (cpu_data[cpu].irq_count) +#endif /* * Are we in an interrupt context? Either doing bottom half @@ -16,23 +20,23 @@ extern unsigned long hardirq_no[NR_CPUS]; #define in_interrupt() \ ({ \ int __cpu = smp_processor_id(); \ - (local_irq_count[__cpu] + local_bh_count[__cpu]) != 0; \ + (local_irq_count(__cpu) + local_bh_count(__cpu)) != 0; \ }) #ifndef __SMP__ -#define hardirq_trylock(cpu) (local_irq_count[cpu] == 0) +#define hardirq_trylock(cpu) (local_irq_count(cpu) == 0) #define hardirq_endlock(cpu) ((void) 0) -#define hardirq_enter(cpu, irq) (local_irq_count[cpu]++) -#define hardirq_exit(cpu, irq) (local_irq_count[cpu]--) +#define hardirq_enter(cpu, irq) (local_irq_count(cpu)++) +#define hardirq_exit(cpu, irq) (local_irq_count(cpu)--) #define synchronize_irq() barrier() #else #include <asm/atomic.h> -#include <asm/spinlock.h> +#include <linux/spinlock.h> #include <asm/smp.h> extern int global_irq_holder; @@ -50,21 +54,20 @@ static inline void release_irqlock(int cpu) static inline void hardirq_enter(int cpu, int irq) { - ++local_irq_count[cpu]; + ++local_irq_count(cpu); atomic_inc(&global_irq_count); - hardirq_no[cpu] |= 1L << irq; /* debugging only */ } static inline void hardirq_exit(int cpu, int irq) { - hardirq_no[cpu] &= ~(1L << irq); /* debugging only */ atomic_dec(&global_irq_count); - --local_irq_count[cpu]; + --local_irq_count(cpu); } static inline int hardirq_trylock(int cpu) { - return !atomic_read(&global_irq_count) && !global_irq_lock.lock; + return (!atomic_read(&global_irq_count) + && !spin_is_locked(&global_irq_lock)); } #define hardirq_endlock(cpu) ((void)0) diff --git a/include/asm-alpha/ide.h b/include/asm-alpha/ide.h index 2ef5de935..ecb696099 100644 --- a/include/asm-alpha/ide.h +++ b/include/asm-alpha/ide.h @@ -13,6 +13,8 @@ #ifdef __KERNEL__ +#include <linux/config.h> + #ifndef MAX_HWIFS #define MAX_HWIFS 4 #endif @@ -67,7 +69,7 @@ static __inline__ void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, */ static __inline__ void ide_init_default_hwifs(void) { -#ifdef __DO_I_NEED_THIS +#ifndef CONFIG_BLK_DEV_IDEPCI hw_regs_t hw; int index; @@ -76,7 +78,7 @@ static __inline__ void ide_init_default_hwifs(void) hw.irq = ide_default_irq(ide_default_io_base(index)); ide_register_hw(&hw, NULL); } -#endif /* __DO_I_NEED_THIS */ +#endif /* CONFIG_BLK_DEV_IDEPCI */ } typedef union { diff --git a/include/asm-alpha/init.h b/include/asm-alpha/init.h index f343aecd3..17d215574 100644 --- a/include/asm-alpha/init.h +++ b/include/asm-alpha/init.h @@ -1,19 +1 @@ -#ifndef _ALPHA_INIT_H -#define _ALPHA_INIT_H - -#ifndef MODULE -#define __init __attribute__ ((__section__ (".text.init"))) -#define __initdata __attribute__ ((__section__ (".data.init"))) -#define __initfunc(__arginit) \ - __arginit __init; \ - __arginit - -/* For assembly routines */ -#define __INIT .section .text.init,"ax" -#define __FINIT .previous -#define __INITDATA .section .data.init,"a" -#endif - -#define __cacheline_aligned __attribute__((__aligned__(32))) - -#endif +#error "<asm/init.h> should never be used - use <linux/init.h> instead" diff --git a/include/asm-alpha/io.h b/include/asm-alpha/io.h index 5ba356f61..8505e47c8 100644 --- a/include/asm-alpha/io.h +++ b/include/asm-alpha/io.h @@ -2,6 +2,7 @@ #define __ALPHA_IO_H #include <linux/config.h> +#include <linux/kernel.h> #include <asm/system.h> /* We don't use IO slowdowns on the Alpha, but.. */ @@ -103,6 +104,9 @@ extern void _sethae (unsigned long addr); /* cached version */ # define __writel(v,a) alpha_mv.mv_writel((v),(unsigned long)(a)) # define __writeq(v,a) alpha_mv.mv_writeq((v),(unsigned long)(a)) +# define __ioremap(a) alpha_mv.mv_ioremap(a) +# define __is_ioaddr(a) alpha_mv.mv_is_ioaddr(a) + # define inb __inb # define inw __inw # define inl __inl @@ -110,16 +114,14 @@ extern void _sethae (unsigned long addr); /* cached version */ # define outw __outw # define outl __outl -# define readb __readb -# define readw __readw -# define readl __readl -# define readq __readq -# define writeb __writeb -# define writew __writew -# define writel __writel -# define writeq __writeq - -# define dense_mem(a) alpha_mv.mv_dense_mem(a) +# define __raw_readb __readb +# define __raw_readw __readw +# define __raw_readl __readl +# define __raw_readq __readq +# define __raw_writeb __writeb +# define __raw_writew __writew +# define __raw_writel __writel +# define __raw_writeq __writeq #else @@ -142,7 +144,7 @@ extern void _sethae (unsigned long addr); /* cached version */ # include <asm/core_tsunami.h> #elif defined(CONFIG_ALPHA_JENSEN) # include <asm/jensen.h> -#elif defined(CONFIG_ALPHA_RX164) +#elif defined(CONFIG_ALPHA_POLARIS) # include <asm/core_polaris.h> #else #error "What system is this?" @@ -244,21 +246,85 @@ extern void writel(unsigned int b, unsigned long addr); #ifdef __KERNEL__ /* - * The "address" in IO memory space is not clearly either an integer or a - * pointer. We will accept both, thus the casts. + * On Alpha, we have the whole of I/O space mapped at all times, but + * at odd and sometimes discontinuous addresses. Note that the + * discontinuities are all across busses, so we need not care for that + * for any one device. * - * On the alpha, we have the whole physical address space mapped at all - * times, so "ioremap()" and "iounmap()" do not need to do anything. + * Map the I/O space address into the kernel's virtual address space. */ static inline void * ioremap(unsigned long offset, unsigned long size) { - return (void *) offset; + return (void *) __ioremap(offset); } static inline void iounmap(void *addr) { } +/* Indirect back to the macros provided. */ + +extern unsigned long ___raw_readb(unsigned long addr); +extern unsigned long ___raw_readw(unsigned long addr); +extern unsigned long ___raw_readl(unsigned long addr); +extern unsigned long ___raw_readq(unsigned long addr); +extern void ___raw_writeb(unsigned char b, unsigned long addr); +extern void ___raw_writew(unsigned short b, unsigned long addr); +extern void ___raw_writel(unsigned int b, unsigned long addr); +extern void ___raw_writeq(unsigned long b, unsigned long addr); + +#ifdef __raw_readb +# define readb(a) ({ unsigned long r_ = __raw_readb(a); mb(); r_; }) +#endif +#ifdef __raw_readw +# define readw(a) ({ unsigned long r_ = __raw_readw(a); mb(); r_; }) +#endif +#ifdef __raw_readl +# define readl(a) ({ unsigned long r_ = __raw_readl(a); mb(); r_; }) +#endif +#ifdef __raw_readq +# define readq(a) ({ unsigned long r_ = __raw_readq(a); mb(); r_; }) +#endif + +#ifdef __raw_writeb +# define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); }) +#endif +#ifdef __raw_writew +# define writew(v,a) ({ __raw_writew((v),(a)); mb(); }) +#endif +#ifdef __raw_writel +# define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) +#endif +#ifdef __raw_writeq +# define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); }) +#endif + +#ifndef __raw_readb +# define __raw_readb(a) ___raw_readb((unsigned long)(a)) +#endif +#ifndef __raw_readw +# define __raw_readw(a) ___raw_readw((unsigned long)(a)) +#endif +#ifndef __raw_readl +# define __raw_readl(a) ___raw_readl((unsigned long)(a)) +#endif +#ifndef __raw_readq +# define __raw_readq(a) ___raw_readq((unsigned long)(a)) +#endif + +#ifndef __raw_writeb +# define __raw_writeb(v,a) ___raw_writeb((v),(unsigned long)(a)) +#endif +#ifndef __raw_writew +# define __raw_writew(v,a) ___raw_writew((v),(unsigned long)(a)) +#endif +#ifndef __raw_writel +# define __raw_writel(v,a) ___raw_writel((v),(unsigned long)(a)) +#endif +#ifndef __raw_writeq +# define __raw_writeq(v,a) ___raw_writeq((v),(unsigned long)(a)) +#endif + #ifndef readb # define readb(a) _readb((unsigned long)(a)) #endif @@ -271,6 +337,7 @@ static inline void iounmap(void *addr) #ifndef readq # define readq(a) _readq((unsigned long)(a)) #endif + #ifndef writeb # define writeb(v,a) _writeb((v),(unsigned long)(a)) #endif diff --git a/include/asm-alpha/jensen.h b/include/asm-alpha/jensen.h index 874511e94..826dfc54d 100644 --- a/include/asm-alpha/jensen.h +++ b/include/asm-alpha/jensen.h @@ -292,12 +292,14 @@ __EXTERN_INLINE void jensen_writeq(unsigned long b, unsigned long addr) *(vuip) (addr + (4 << 7)) = b >> 32; } -/* Find the DENSE memory area for a given bus address. - Whee, there is none. */ +__EXTERN_INLINE unsigned long jensen_ioremap(unsigned long addr) +{ + return addr; +} -__EXTERN_INLINE unsigned long jensen_dense_mem(unsigned long addr) +__EXTERN_INLINE int jensen_is_ioaddr(unsigned long addr) { - return 0; + return (long)addr >= 0; } #undef vuip @@ -320,7 +322,8 @@ __EXTERN_INLINE unsigned long jensen_dense_mem(unsigned long addr) #define __readq jensen_readq #define __writel jensen_writel #define __writeq jensen_writeq -#define dense_mem jensen_dense_mem +#define __ioremap jensen_ioremap +#define __is_ioaddr jensen_is_ioaddr /* * The above have so much overhead that it probably doesn't make diff --git a/include/asm-alpha/machvec.h b/include/asm-alpha/machvec.h index 587fa8a3e..14be8d58b 100644 --- a/include/asm-alpha/machvec.h +++ b/include/asm-alpha/machvec.h @@ -19,6 +19,8 @@ struct mm_struct; struct pt_regs; struct vm_area_struct; struct linux_hose_info; +struct pci_dev; +struct pci_ops; struct alpha_machine_vector { @@ -34,6 +36,8 @@ struct alpha_machine_vector unsigned long max_dma_address; unsigned long irq_probe_mask; unsigned long iack_sc; + unsigned long min_io_address; + unsigned long min_mem_address; unsigned long (*mv_virt_to_bus)(void *); void * (*mv_bus_to_virt)(unsigned long); @@ -56,23 +60,13 @@ struct alpha_machine_vector void (*mv_writel)(unsigned int, unsigned long); void (*mv_writeq)(unsigned long, unsigned long); - unsigned long (*mv_dense_mem)(unsigned long); - - int (*hose_read_config_byte)(u8, u8, u8, u8 *value, - struct linux_hose_info *); - int (*hose_read_config_word)(u8, u8, u8, u16 *value, - struct linux_hose_info *); - int (*hose_read_config_dword)(u8, u8, u8, u32 *value, - struct linux_hose_info *); - - int (*hose_write_config_byte)(u8, u8, u8, u8 value, - struct linux_hose_info *); - int (*hose_write_config_word)(u8, u8, u8, u16 value, - struct linux_hose_info *); - int (*hose_write_config_dword)(u8, u8, u8, u32 value, - struct linux_hose_info *); - - void (*mv_get_mmu_context)(struct task_struct *); + unsigned long (*mv_ioremap)(unsigned long); + int (*mv_is_ioaddr)(unsigned long); + + void (*mv_switch_mm)(struct mm_struct *, struct mm_struct *, + struct task_struct *, long); + void (*mv_activate_mm)(struct mm_struct *, struct mm_struct *, long); + void (*mv_flush_tlb_current)(struct mm_struct *); void (*mv_flush_tlb_other)(struct mm_struct *); void (*mv_flush_tlb_current_page)(struct mm_struct * mm, @@ -87,9 +81,13 @@ struct alpha_machine_vector void (*init_arch)(unsigned long *, unsigned long *); void (*init_irq)(void); void (*init_pit)(void); - void (*pci_fixup)(void); + void (*init_pci)(void); void (*kill_arch)(int, char *); + u8 (*pci_swizzle)(struct pci_dev *, u8 *); + int (*pci_map_irq)(struct pci_dev *, u8, u8); + struct pci_ops *pci_ops; + const char *vector_name; /* System specific parameters. */ @@ -101,30 +99,23 @@ struct alpha_machine_vector struct { unsigned long gamma_bias; } t2; - } sys; - /* Runtime variables it is handy to keep close. */ - unsigned long dma_win_base; - unsigned long dma_win_size; - unsigned long sm_base_r1, sm_base_r2, sm_base_r3; + struct { + unsigned int route_tab; + } sio; + } sys; }; extern struct alpha_machine_vector alpha_mv; #ifdef CONFIG_ALPHA_GENERIC extern int alpha_using_srm; -extern int alpha_use_srm_setup; #else #ifdef CONFIG_ALPHA_SRM #define alpha_using_srm 1 #else #define alpha_using_srm 0 #endif -#if defined(CONFIG_ALPHA_SRM_SETUP) -#define alpha_use_srm_setup 1 -#else -#define alpha_use_srm_setup 0 -#endif #endif /* GENERIC */ #endif diff --git a/include/asm-alpha/mmu_context.h b/include/asm-alpha/mmu_context.h index 7b800d156..64d550938 100644 --- a/include/asm-alpha/mmu_context.h +++ b/include/asm-alpha/mmu_context.h @@ -11,6 +11,34 @@ #include <asm/system.h> #include <asm/machvec.h> + +/* + * Force a context reload. This is needed when we change the page + * table pointer or when we update the ASN of the current process. + */ + +/* Don't get into trouble with dueling __EXTERN_INLINEs. */ +#ifndef __EXTERN_INLINE +#include <asm/io.h> +#endif + +extern inline unsigned long +__reload_thread(struct thread_struct *pcb) +{ + register unsigned long a0 __asm__("$16"); + register unsigned long v0 __asm__("$0"); + + a0 = virt_to_phys(pcb); + __asm__ __volatile__( + "call_pal %2 #__reload_thread" + : "=r"(v0), "=r"(a0) + : "i"(PAL_swpctx), "r"(a0) + : "$1", "$16", "$22", "$23", "$24", "$25"); + + return v0; +} + + /* * The maximum ASN's the processor supports. On the EV4 this is 63 * but the PAL-code doesn't actually use this information. On the @@ -66,7 +94,11 @@ extern unsigned long last_asn; #endif /* __SMP__ */ #define WIDTH_HARDWARE_ASN 8 +#ifdef __SMP__ #define WIDTH_THIS_PROCESSOR 5 +#else +#define WIDTH_THIS_PROCESSOR 0 +#endif #define ASN_FIRST_VERSION (1UL << (WIDTH_THIS_PROCESSOR + WIDTH_HARDWARE_ASN)) #define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1) @@ -87,65 +119,104 @@ extern unsigned long last_asn; #define __MMU_EXTERN_INLINE #endif -extern void get_new_mmu_context(struct task_struct *p, struct mm_struct *mm); +extern void get_new_mm_context(struct task_struct *p, struct mm_struct *mm); static inline unsigned long -__get_new_mmu_context(struct task_struct *p, struct mm_struct *mm) +__get_new_mm_context(struct mm_struct *mm, long cpu) { - unsigned long asn = cpu_last_asn(smp_processor_id()); + unsigned long asn = cpu_last_asn(cpu); unsigned long next = asn + 1; - if ((next ^ asn) & ~MAX_ASN) { + if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) { tbiap(); next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION; } - cpu_last_asn(smp_processor_id()) = next; - mm->context = next; /* full version + asn */ + cpu_last_asn(cpu) = next; return next; } __EXTERN_INLINE void -ev4_get_mmu_context(struct task_struct *p) +ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *next, long cpu) { /* As described, ASN's are broken. But we can optimize for switching between threads -- if the mm is unchanged from current we needn't flush. */ - if (current->mm != p->mm) + /* ??? May not be needed because EV4 PALcode recognizes that + ASN's are broken and does a tbiap itself on swpctx, under + the "Must set ASN or flush" rule. At least this is true + for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com). + I'm going to leave this here anyway, just to Be Sure. -- r~ */ + + if (prev_mm != next_mm) tbiap(); } __EXTERN_INLINE void -ev5_get_mmu_context(struct task_struct *p) +ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, long cpu) +{ + /* This is only called after changing mm on current. */ + tbiap(); + + current->thread.ptbr + = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; +} + +__EXTERN_INLINE void +ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *next, long cpu) { /* Check if our ASN is of an older version, or on a different CPU, and thus invalid. */ + /* ??? If we have two threads on different cpus, we'll continually + fight over the context. Find a way to record a per-mm, per-cpu + value for the asn. */ - long asn = cpu_last_asn(smp_processor_id()); - struct mm_struct *mm = p->mm; - long mmc = mm->context; + unsigned long asn = cpu_last_asn(cpu); + unsigned long mmc = next_mm->context; - if ((p->tss.mm_context ^ asn) & ~HARDWARE_ASN_MASK) { - if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) - mmc = __get_new_mmu_context(p, mm); - p->tss.mm_context = mmc; - p->tss.asn = mmc & HARDWARE_ASN_MASK; + if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) { + mmc = __get_new_mm_context(next_mm, cpu); + next_mm->context = mmc; } + + /* Always update the PCB ASN. Another thread may have allocated + a new mm->context (via flush_tlb_mm) without the ASN serial + number wrapping. We have no way to detect when this is needed. */ + next->thread.asn = mmc & HARDWARE_ASN_MASK; } +__EXTERN_INLINE void +ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, long cpu) +{ + unsigned long mmc = __get_new_mm_context(next_mm, cpu); + next_mm->context = mmc; + current->thread.asn = mmc & HARDWARE_ASN_MASK; + current->thread.ptbr + = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; + + __reload_thread(¤t->thread); +} + + #ifdef CONFIG_ALPHA_GENERIC -# define get_mmu_context (alpha_mv.mv_get_mmu_context) +# define switch_mm alpha_mv.mv_switch_mm +# define activate_mm(x,y) alpha_mv.mv_activate_mm((x),(y),smp_processor_id()) #else # ifdef CONFIG_ALPHA_EV4 -# define get_mmu_context ev4_get_mmu_context +# define switch_mm ev4_switch_mm +# define activate_mm(x,y) ev4_activate_mm((x),(y),smp_processor_id()) # else -# define get_mmu_context ev5_get_mmu_context +# define switch_mm ev5_switch_mm +# define activate_mm(x,y) ev5_activate_mm((x),(y),smp_processor_id()) # endif #endif extern inline void -init_new_context(struct mm_struct *mm) +init_new_context(struct task_struct *tsk, struct mm_struct *mm) { mm->context = 0; + tsk->thread.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; } extern inline void @@ -159,48 +230,4 @@ destroy_context(struct mm_struct *mm) #undef __MMU_EXTERN_INLINE #endif -/* - * Force a context reload. This is needed when we change the page - * table pointer or when we update the ASN of the current process. - */ - -/* Don't get into trouble with dueling __EXTERN_INLINEs. */ -#ifndef __EXTERN_INLINE -#include <asm/io.h> -#endif - -extern inline unsigned long -__reload_tss(struct thread_struct *tss) -{ - register unsigned long a0 __asm__("$16"); - register unsigned long v0 __asm__("$0"); - - a0 = virt_to_phys(tss); - __asm__ __volatile__( - "call_pal %2 #__reload_tss" - : "=r"(v0), "=r"(a0) - : "i"(PAL_swpctx), "r"(a0) - : "$1", "$16", "$22", "$23", "$24", "$25"); - - return v0; -} - -extern inline void -reload_context(struct task_struct *task) -{ - __reload_tss(&task->tss); -} - -/* - * After setting current->mm to a new value, activate the context for the - * new mm so we see the new mappings. - */ - -extern inline void -activate_context(struct task_struct *task) -{ - get_new_mmu_context(task, task->mm); - reload_context(task); -} - #endif /* __ALPHA_MMU_CONTEXT_H */ diff --git a/include/asm-alpha/page.h b/include/asm-alpha/page.h index 816219ce9..8011c5859 100644 --- a/include/asm-alpha/page.h +++ b/include/asm-alpha/page.h @@ -106,13 +106,8 @@ typedef unsigned long pgprot_t; #endif /* STRICT_MM_TYPECHECKS */ -#define BUG() \ -do { \ - printk("Kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ - __asm__ __volatile__("call_pal 129 # bugchk"); \ -} while (1) - -#define PAGE_BUG(page) BUG() +#define BUG() __asm__ __volatile__("call_pal 129 # bugchk") +#define PAGE_BUG(page) BUG() #endif /* !ASSEMBLY */ diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h index 3b586974f..987879760 100644 --- a/include/asm-alpha/param.h +++ b/include/asm-alpha/param.h @@ -1,8 +1,18 @@ #ifndef _ASM_ALPHA_PARAM_H #define _ASM_ALPHA_PARAM_H +/* ??? Gross. I don't want to parameterize this, and supposedly the + hardware ignores reprogramming. We also need userland buy-in to the + change in HZ, since this is visible in the wait4 resources etc. */ + +#include <linux/config.h> + #ifndef HZ -# define HZ 1024 +# ifndef CONFIG_ALPHA_RAWHIDE +# define HZ 1024 +# else +# define HZ 1200 +# endif # define HZ_TO_STD(a) (a) #endif diff --git a/include/asm-alpha/parport.h b/include/asm-alpha/parport.h new file mode 100644 index 000000000..e9b590ee1 --- /dev/null +++ b/include/asm-alpha/parport.h @@ -0,0 +1,59 @@ +/* + * parport.h: platform-specific PC-style parport initialisation + * + * Copyright (C) 1999 Tim Waugh <tim@cyberelk.demon.co.uk> + * + * This file should only be included by drivers/parport/parport_pc.c. + */ + +#ifndef _ASM_AXP_PARPORT_H +#define _ASM_AXP_PARPORT_H 1 + +#include <linux/config.h> + +/* Maximum number of ports to support. It is useless to set this greater + than PARPORT_MAX (in <linux/parport.h>). */ +#define PARPORT_PC_MAX_PORTS 8 + +/* If parport_cs (PCMCIA) is managing ports for us, we'll need the + * probing routines forever; otherwise we can lose them at boot time. */ +#ifdef CONFIG_PARPORT_PC_PCMCIA +#define __maybe_initdata +#define __maybe_init +#else +#define __maybe_initdata __initdata +#define __maybe_init __init +#endif + +static int __maybe_init parport_pc_init_pci(int irq, int dma); + +static int user_specified __maybe_initdata = 0; +int __init +parport_pc_init(int *io, int *io_hi, int *irq, int *dma) +{ + int count = 0, i = 0; + + if (io && *io) { + /* Only probe the ports we were given. */ + user_specified = 1; + do { + if (!*io_hi) *io_hi = 0x400 + *io; + if (parport_pc_probe_port(*(io++), *(io_hi++), + *(irq++), *(dma++))) + count++; + } while (*io && (++i < PARPORT_PC_MAX_PORTS)); + } else { + /* Probe all the likely ports. */ + if (parport_pc_probe_port(0x3bc, 0x7bc, irq[0], dma[0])) + count++; + if (parport_pc_probe_port(0x378, 0x778, irq[0], dma[0])) + count++; + if (parport_pc_probe_port(0x278, 0x678, irq[0], dma[0])) + count++; + count += parport_pc_init_pci (irq[0], dma[0]); + } + + return count; +} + +#endif /* !(_ASM_AXP_PARPORT_H) */ diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h index fa6bd17e1..f78c9b975 100644 --- a/include/asm-alpha/pci.h +++ b/include/asm-alpha/pci.h @@ -1,48 +1,31 @@ #ifndef __ALPHA_PCI_H #define __ALPHA_PCI_H -#include <linux/config.h> -#include <linux/pci.h> - - /* * The following structure is used to manage multiple PCI busses. - * - * XXX: We should solve this problem in an architecture independent - * way, rather than hacking something up here. */ -struct linux_hose_info { - struct pci_bus pci_bus; - struct linux_hose_info *next; - unsigned long pci_io_space; - unsigned long pci_mem_space; - unsigned long pci_config_space; - unsigned long pci_sparse_space; - unsigned int pci_first_busno; - unsigned int pci_last_busno; - unsigned int pci_hose_index; +struct pci_bus; +struct resource; + +struct pci_controler { + /* Mandated. */ + struct pci_controler *next; + struct pci_bus *bus; + struct resource *io_space; + struct resource *mem_space; + + /* Alpha specific. */ + unsigned long config_space; + unsigned int index; + unsigned int first_busno; + unsigned int last_busno; }; -/* This is indexed by a pseudo- PCI bus number to obtain the real deal. */ -extern struct linux_hose_info *bus2hose[256]; - -/* Create a handle that is OR-ed into the reported I/O space address - for a device. We use this later to find the bus a device lives on. */ - -#if defined(CONFIG_ALPHA_GENERIC) \ - || defined(CONFIG_ALPHA_MCPCIA) \ - || defined(CONFIG_ALPHA_TSUNAMI) +/* Override the logic in pci_scan_bus for skipping already-configured + bus numbers. */ -#define PCI_HANDLE(bus) ((bus2hose[bus]->pci_hose_index & 3UL) << 32) -#define DEV_IS_ON_PRIMARY(dev) \ - (bus2hose[(dev)->bus->number]->pci_first_busno == (dev)->bus->number) - -#else - -#define PCI_HANDLE(bus) 0 -#define DEV_IS_ON_PRIMARY(dev) ((dev)->bus->number == 0) - -#endif /* Multiple busses */ +#define pcibios_assign_all_busses() 1 #endif /* __ALPHA_PCI_H */ + diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h index a11a02920..004924b93 100644 --- a/include/asm-alpha/pgtable.h +++ b/include/asm-alpha/pgtable.h @@ -9,12 +9,12 @@ * in <asm/page.h> (currently 8192). */ #include <linux/config.h> +#include <linux/spinlock.h> /* For the task lock */ #include <asm/system.h> #include <asm/processor.h> /* For TASK_SIZE */ #include <asm/mmu_context.h> #include <asm/machvec.h> -#include <asm/spinlock.h> /* For the task lock */ /* Caches aren't brain-dead on the Alpha. */ @@ -46,13 +46,7 @@ ev4_flush_tlb_other(struct mm_struct *mm) { } -__EXTERN_INLINE void -ev5_flush_tlb_current(struct mm_struct *mm) -{ - mm->context = 0; - get_new_mmu_context(current, mm); - reload_context(current); -} +extern void ev5_flush_tlb_current(struct mm_struct *mm); __EXTERN_INLINE void ev5_flush_tlb_other(struct mm_struct *mm) @@ -395,22 +389,6 @@ extern inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_FOE; return p extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; } extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; } -/* - * To set the page-dir. Note the self-mapping in the last entry - * - * Also note that if we update the current process ptbr, we need to - * update the PAL-cached ptbr value as well.. There doesn't seem to - * be any "wrptbr" PAL-insn, but we can do a dummy swpctx to ourself - * instead. - */ -extern inline void SET_PAGE_DIR(struct task_struct * tsk, pgd_t * pgdir) -{ - pgd_val(pgdir[PTRS_PER_PGD]) = pte_val(mk_pte((unsigned long) pgdir, PAGE_KERNEL)); - tsk->tss.ptbr = ((unsigned long) pgdir - PAGE_OFFSET) >> PAGE_SHIFT; - if (tsk == current) - reload_context(tsk); -} - #define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address)) /* to find an entry in a kernel page-table-directory */ @@ -463,6 +441,9 @@ extern __inline__ pgd_t *get_pgd_slow(void) memset (ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); + + pgd_val(ret[PTRS_PER_PGD]) + = pte_val(mk_pte((unsigned long)ret, PAGE_KERNEL)); } return ret; } @@ -640,4 +621,7 @@ extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #define PageSkip(page) (0) #define kern_addr_valid(addr) (1) +#define io_remap_page_range(start, busaddr, size, prot) \ + remap_page_range(start, virt_to_phys(ioremap(busaddr)), size, prot) + #endif /* _ALPHA_PGTABLE_H */ diff --git a/include/asm-alpha/processor.h b/include/asm-alpha/processor.h index fa6c47b63..0c5163433 100644 --- a/include/asm-alpha/processor.h +++ b/include/asm-alpha/processor.h @@ -61,15 +61,6 @@ struct thread_struct { */ unsigned long flags; - /* The full version of the ASN including serial number. - - Two threads running on two different processors must of necessity - have different serial numbers. Having this duplicated from - mm->context allows them to be slightly out of sync preventing - the asn from incrementing each and every time the two threads - are scheduled. */ - unsigned long mm_context; - /* Perform syscall argument validation (get/set_fs). */ mm_segment_t fs; @@ -82,14 +73,16 @@ struct thread_struct { #define INIT_MMAP { &init_mm, PAGE_OFFSET, PAGE_OFFSET+0x10000000, \ NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } -#define INIT_TSS { \ +#define INIT_THREAD { \ 0, 0, 0, \ 0, 0, 0, \ 0, 0, 0, \ - 0, 0, \ + 0, \ KERNEL_DS \ } +#define THREAD_SIZE (2*PAGE_SIZE) + #include <asm/ptrace.h> /* @@ -118,15 +111,16 @@ extern inline unsigned long thread_saved_pc(struct thread_struct *t) return 0; } -/* - * Do necessary setup to start up a newly executed thread. - */ +/* Do necessary setup to start up a newly executed thread. */ extern void start_thread(struct pt_regs *, unsigned long, unsigned long); /* Free all resources held by a thread. */ extern void release_thread(struct task_struct *); -#define copy_segments(nr, tsk, mm) do { } while (0) +/* Create a kernel thread without removing it from tasklists. */ +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +#define copy_segments(tsk, mm) do { } while (0) #define release_segments(mm) do { } while (0) #define forget_segments() do { } while (0) @@ -138,14 +132,4 @@ extern void release_thread(struct task_struct *); #define init_task (init_task_union.task) #define init_stack (init_task_union.stack) -/* - * Return_address is a replacement for __builtin_return_address(count) - * which on certain architectures cannot reasonably be implemented in GCC - * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). - * Note that __builtin_return_address(x>=1) is forbidden because the GCC - * aborts compilation on some CPUs. It's simply not possible to unwind - * some CPU's stackframes. - */ -#define return_address() __builtin_return_address(0) - #endif /* __ASM_ALPHA_PROCESSOR_H */ diff --git a/include/asm-alpha/ptrace.h b/include/asm-alpha/ptrace.h index 4079385ec..268ebfced 100644 --- a/include/asm-alpha/ptrace.h +++ b/include/asm-alpha/ptrace.h @@ -67,7 +67,7 @@ struct switch_stack { }; #ifdef __KERNEL__ -#define user_mode(regs) ((regs)->ps & 8) +#define user_mode(regs) (((regs)->ps & 8) != 0) #define instruction_pointer(regs) ((regs)->pc) extern void show_regs(struct pt_regs *); #endif diff --git a/include/asm-alpha/resource.h b/include/asm-alpha/resource.h index 96b338fc4..234cbfa2f 100644 --- a/include/asm-alpha/resource.h +++ b/include/asm-alpha/resource.h @@ -25,12 +25,12 @@ {LONG_MAX, LONG_MAX}, /* RLIMIT_CPU */ \ {LONG_MAX, LONG_MAX}, /* RLIMIT_FSIZE */ \ {LONG_MAX, LONG_MAX}, /* RLIMIT_DATA */ \ - {_STK_LIM, _STK_LIM}, /* RLIMIT_STACK */ \ + {_STK_LIM, LONG_MAX}, /* RLIMIT_STACK */ \ { 0, LONG_MAX}, /* RLIMIT_CORE */ \ {LONG_MAX, LONG_MAX}, /* RLIMIT_RSS */ \ - { NR_OPEN, NR_OPEN}, /* RLIMIT_NOFILE */ \ + {INR_OPEN, INR_OPEN}, /* RLIMIT_NOFILE */ \ {LONG_MAX, LONG_MAX}, /* RLIMIT_AS */ \ - {MAX_TASKS_PER_USER, MAX_TASKS_PER_USER}, /* RLIMIT_NPROC */ \ + {LONG_MAX, LONG_MAX}, /* RLIMIT_NPROC */ \ {LONG_MAX, LONG_MAX}, /* RLIMIT_MEMLOCK */ \ } diff --git a/include/asm-alpha/serial.h b/include/asm-alpha/serial.h index 7b2d9ee95..0b339a0c1 100644 --- a/include/asm-alpha/serial.h +++ b/include/asm-alpha/serial.h @@ -26,6 +26,9 @@ #define FOURPORT_FLAGS ASYNC_FOURPORT #define ACCENT_FLAGS 0 #define BOCA_FLAGS 0 +#define RS_TABLE_SIZE 64 +#else +#define RS_TABLE_SIZE 4 #endif #define STD_SERIAL_PORT_DEFNS \ diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h index 785194f81..e85061736 100644 --- a/include/asm-alpha/smp.h +++ b/include/asm-alpha/smp.h @@ -1,11 +1,25 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H +#include <asm/pal.h> + +/* HACK: Cabrio WHAMI return value is bogus if more than 8 bits used.. :-( */ + +static __inline__ unsigned char +__hard_smp_processor_id(void) +{ + register unsigned char __r0 __asm__("$0"); + __asm__ __volatile__( + "call_pal %1 #whami" + : "=r"(__r0) + :"i" (PAL_whami) + : "$1", "$22", "$23", "$24", "$25"); + return __r0; +} + #ifdef __SMP__ -#include <linux/tasks.h> -#include <asm/init.h> -#include <asm/pal.h> +#include <linux/threads.h> struct cpuinfo_alpha { unsigned long loops_per_sec; @@ -16,7 +30,11 @@ struct cpuinfo_alpha { unsigned long ipi_count; unsigned long prof_multiplier; unsigned long prof_counter; -} __cacheline_aligned; + int irq_count, bh_count; + unsigned char mcheck_expected; + unsigned char mcheck_taken; + unsigned char mcheck_extra; +} __attribute__((aligned(64))); extern struct cpuinfo_alpha cpu_data[NR_CPUS]; @@ -30,19 +48,7 @@ extern int cpu_number_map[NR_CPUS]; extern int __cpu_logical_map[NR_CPUS]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] -/* HACK: Cabrio WHAMI return value is bogus if more than 8 bits used.. :-( */ - -static __inline__ unsigned char hard_smp_processor_id(void) -{ - register unsigned char __r0 __asm__("$0"); - __asm__ __volatile__( - "call_pal %1 #whami" - : "=r"(__r0) - :"i" (PAL_whami) - : "$1", "$22", "$23", "$24", "$25"); - return __r0; -} - +#define hard_smp_processor_id() __hard_smp_processor_id() #define smp_processor_id() (current->processor) #endif /* __SMP__ */ diff --git a/include/asm-alpha/smplock.h b/include/asm-alpha/smplock.h index a33fd546a..2a5c62700 100644 --- a/include/asm-alpha/smplock.h +++ b/include/asm-alpha/smplock.h @@ -6,7 +6,7 @@ #include <linux/sched.h> #include <linux/interrupt.h> -#include <asm/spinlock.h> +#include <linux/spinlock.h> extern spinlock_t kernel_flag; diff --git a/include/asm-alpha/softirq.h b/include/asm-alpha/softirq.h index dad9c4905..d49064790 100644 --- a/include/asm-alpha/softirq.h +++ b/include/asm-alpha/softirq.h @@ -5,28 +5,33 @@ #include <asm/atomic.h> #include <asm/hardirq.h> -extern unsigned int local_bh_count[NR_CPUS]; +#ifndef __SMP__ +extern int __local_bh_count; +#define local_bh_count(cpu) ((void)(cpu), __local_bh_count) +#else +#define local_bh_count(cpu) (cpu_data[cpu].bh_count) +#endif extern inline void cpu_bh_disable(int cpu) { - local_bh_count[cpu]++; + local_bh_count(cpu)++; mb(); } extern inline void cpu_bh_enable(int cpu) { mb(); - local_bh_count[cpu]--; + local_bh_count(cpu)--; } extern inline int cpu_bh_trylock(int cpu) { - return local_bh_count[cpu] ? 0 : (local_bh_count[cpu] = 1); + return local_bh_count(cpu) ? 0 : (local_bh_count(cpu) = 1); } extern inline void cpu_bh_endlock(int cpu) { - local_bh_count[cpu] = 0; + local_bh_count(cpu) = 0; } #define local_bh_enable() cpu_bh_enable(smp_processor_id()) diff --git a/include/asm-alpha/spinlock.h b/include/asm-alpha/spinlock.h index 454a56582..6153b2a86 100644 --- a/include/asm-alpha/spinlock.h +++ b/include/asm-alpha/spinlock.h @@ -2,102 +2,6 @@ #define _ALPHA_SPINLOCK_H #include <asm/system.h> - -/* - * These are the generic versions of the spinlocks - * and read-write locks.. We should actually do a - * <linux/spinlock.h> with all of this. Oh, well. - */ -#define spin_lock_irqsave(lock, flags) \ - do { local_irq_save(flags); spin_lock(lock); } while (0) -#define spin_lock_irq(lock) \ - do { local_irq_disable(); spin_lock(lock); } while (0) -#define spin_lock_bh(lock) \ - do { local_bh_disable(); spin_lock(lock); } while (0) - -#define read_lock_irqsave(lock, flags) \ - do { local_irq_save(flags); read_lock(lock); } while (0) -#define read_lock_irq(lock) \ - do { local_irq_disable(); read_lock(lock); } while (0) -#define read_lock_bh(lock) \ - do { local_bh_disable(); read_lock(lock); } while (0) - -#define write_lock_irqsave(lock, flags) \ - do { local_irq_save(flags); write_lock(lock); } while (0) -#define write_lock_irq(lock) \ - do { local_irq_disable(); write_lock(lock); } while (0) -#define write_lock_bh(lock) \ - do { local_bh_disable(); write_lock(lock); } while (0) - -#define spin_unlock_irqrestore(lock, flags) \ - do { spin_unlock(lock); local_irq_restore(flags); } while (0) -#define spin_unlock_irq(lock) \ - do { spin_unlock(lock); local_irq_enable(); } while (0) -#define spin_unlock_bh(lock) \ - do { spin_unlock(lock); local_bh_enable(); } while (0) - -#define read_unlock_irqrestore(lock, flags) \ - do { read_unlock(lock); local_irq_restore(flags); } while (0) -#define read_unlock_irq(lock) \ - do { read_unlock(lock); local_irq_enable(); } while (0) -#define read_unlock_bh(lock) \ - do { read_unlock(lock); local_bh_enable(); } while (0) - -#define write_unlock_irqrestore(lock, flags) \ - do { write_unlock(lock); local_irq_restore(flags); } while (0) -#define write_unlock_irq(lock) \ - do { write_unlock(lock); local_irq_enable(); } while (0) -#define write_unlock_bh(lock) \ - do { write_unlock(lock); local_bh_enable(); } while (0) - -#ifndef __SMP__ - -/* - * Your basic spinlocks, allowing only a single CPU anywhere - * - * Gcc-2.7.x has a nasty bug with empty initializers. - */ -#if (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8) - typedef struct { } spinlock_t; - #define SPIN_LOCK_UNLOCKED (spinlock_t) { } -#else - typedef struct { int gcc_is_buggy; } spinlock_t; - #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#endif - -#define spin_lock_init(lock) ((void) 0) -#define spin_lock(lock) ((void) 0) -#define spin_trylock(lock) (1) -#define spin_unlock_wait(lock) ((void) 0) -#define spin_unlock(lock) ((void) 0) - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - * - * Gcc-2.7.x has a nasty bug with empty initializers. - */ -#if (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8) - typedef struct { } rwlock_t; - #define RW_LOCK_UNLOCKED (rwlock_t) { } -#else - typedef struct { int gcc_is_buggy; } rwlock_t; - #define RW_LOCK_UNLOCKED (rwlock_t) { 0 } -#endif - -#define read_lock(lock) ((void) 0) -#define read_unlock(lock) ((void) 0) -#define write_lock(lock) ((void) 0) -#define write_unlock(lock) ((void) 0) - -#else /* __SMP__ */ - #include <linux/kernel.h> #include <asm/current.h> @@ -131,8 +35,8 @@ typedef struct { #define spin_lock_init(x) ((x)->lock = 0) #endif -#define spin_unlock_wait(x) \ - ({ do { barrier(); } while(((volatile spinlock_t *)x)->lock); }) +#define spin_is_locked(x) ((x)->lock != 0) +#define spin_unlock_wait(x) ({ do { barrier(); } while ((x)->lock); }) typedef struct { unsigned long a[100]; } __dummy_lock_t; #define __dummy_lock(lock) (*(__dummy_lock_t *)(lock)) @@ -263,5 +167,4 @@ static inline void read_unlock(rwlock_t * lock) : "m" (__dummy_lock(lock))); } -#endif /* SMP */ #endif /* _ALPHA_SPINLOCK_H */ diff --git a/include/asm-alpha/string.h b/include/asm-alpha/string.h index f53d2ff74..8f87ba2cb 100644 --- a/include/asm-alpha/string.h +++ b/include/asm-alpha/string.h @@ -44,6 +44,7 @@ extern void * __memset(void *, int, size_t); #define __HAVE_ARCH_STRCHR #define __HAVE_ARCH_STRRCHR #define __HAVE_ARCH_STRLEN +#define __HAVE_ARCH_MEMCHR /* The following routine is like memset except that it writes 16-bit aligned values. The DEST and COUNT parameters must be even for diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h index 6939d37ab..880f0f4bb 100644 --- a/include/asm-alpha/system.h +++ b/include/asm-alpha/system.h @@ -88,11 +88,12 @@ struct el_common_EV5_uncorrectable_mcheck { extern void halt(void) __attribute__((noreturn)); +#define prepare_to_switch() do { } while(0) #define switch_to(prev,next,last) \ do { \ unsigned long pcbb; \ current = (next); \ - pcbb = virt_to_phys(¤t->tss); \ + pcbb = virt_to_phys(¤t->thread); \ (last) = alpha_switch_to(pcbb, (prev)); \ } while (0) @@ -107,6 +108,15 @@ __asm__ __volatile__("mb": : :"memory") #define wmb() \ __asm__ __volatile__("wmb": : :"memory") +#define set_mb(var, value) \ +do { var = value; mb(); } while (0) + +#define set_rmb(var, value) \ +do { var = value; rmb(); } while (0) + +#define set_wmb(var, value) \ +do { var = value; wmb(); } while (0) + #define imb() \ __asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory") diff --git a/include/asm-alpha/uaccess.h b/include/asm-alpha/uaccess.h index f615339f8..e08947135 100644 --- a/include/asm-alpha/uaccess.h +++ b/include/asm-alpha/uaccess.h @@ -23,9 +23,9 @@ #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define get_fs() (current->tss.fs) +#define get_fs() (current->thread.fs) #define get_ds() (KERNEL_DS) -#define set_fs(x) (current->tss.fs = (x)) +#define set_fs(x) (current->thread.fs = (x)) #define segment_eq(a,b) ((a).seg == (b).seg) diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h index df20edc7f..c2fe527c1 100644 --- a/include/asm-alpha/unistd.h +++ b/include/asm-alpha/unistd.h @@ -257,7 +257,7 @@ #define __NR_munlockall 317 #define __NR_sysinfo 318 #define __NR__sysctl 319 -#define __NR_idle 320 +/* 320 was sys_idle. */ #define __NR_oldumount 321 #define __NR_swapon 322 #define __NR_times 323 @@ -308,6 +308,8 @@ #define __NR_capget 368 #define __NR_capset 369 #define __NR_sendfile 370 +#define __NR_setresgid 371 +#define __NR_getresgid 372 #if defined(__LIBRARY__) && defined(__GNUC__) @@ -496,32 +498,25 @@ type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5, type6 arg6)\ #include <linux/string.h> #include <linux/signal.h> -extern long __kernel_thread(unsigned long, int (*)(void *), void *); - -static inline long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) -{ - return __kernel_thread(flags | CLONE_VM, fn, arg); -} - extern void sys_idle(void); static inline void idle(void) { sys_idle(); } -extern int sys_open(const char *, int, int); -static inline int open(const char * name, int mode, int flags) +extern long sys_open(const char *, int, int); +static inline long open(const char * name, int mode, int flags) { return sys_open(name, mode, flags); } -extern int sys_dup(int); -static inline int dup(int fd) +extern long sys_dup(int); +static inline long dup(int fd) { return sys_dup(fd); } -static inline int close(int fd) +static inline long close(int fd) { return sys_close(fd); } @@ -532,47 +527,47 @@ static inline off_t lseek(int fd, off_t off, int whense) return sys_lseek(fd, off, whense); } -extern int sys_exit(int); -static inline int _exit(int value) +extern long sys_exit(int); +static inline long _exit(int value) { return sys_exit(value); } #define exit(x) _exit(x) -extern int sys_write(int, const char *, int); -static inline int write(int fd, const char * buf, int nr) +extern long sys_write(int, const char *, int); +static inline long write(int fd, const char * buf, int nr) { return sys_write(fd, buf, nr); } -extern int sys_read(int, char *, int); -static inline int read(int fd, char * buf, int nr) +extern long sys_read(int, char *, int); +static inline long read(int fd, char * buf, int nr) { return sys_read(fd, buf, nr); } extern int __kernel_execve(char *, char **, char **, struct pt_regs *); -static inline int execve(char * file, char ** argvp, char ** envp) +static inline long execve(char * file, char ** argvp, char ** envp) { struct pt_regs regs; memset(®s, 0, sizeof(regs)); return __kernel_execve(file, argvp, envp, ®s); } -extern int sys_setsid(void); -static inline int setsid(void) +extern long sys_setsid(void); +static inline long setsid(void) { return sys_setsid(); } -extern int sys_sync(void); -static inline int sync(void) +extern long sys_sync(void); +static inline long sync(void) { return sys_sync(); } -extern int sys_wait4(int, int *, int, struct rusage *); +extern long sys_wait4(int, int *, int, struct rusage *); static inline pid_t waitpid(int pid, int * wait_stat, int flags) { return sys_wait4(pid, wait_stat, flags, NULL); @@ -583,8 +578,8 @@ static inline pid_t wait(int * wait_stat) return waitpid(-1,wait_stat,0); } -extern int sys_delete_module(const char *name); -static inline int delete_module(const char *name) +extern long sys_delete_module(const char *name); +static inline long delete_module(const char *name) { return sys_delete_module(name); } diff --git a/include/asm-alpha/vga.h b/include/asm-alpha/vga.h index 7e66f50d3..17e164742 100644 --- a/include/asm-alpha/vga.h +++ b/include/asm-alpha/vga.h @@ -15,26 +15,26 @@ extern inline void scr_writew(u16 val, u16 *addr) { - if ((long) addr < 0) - *addr = val; + if (__is_ioaddr((unsigned long) addr)) + __raw_writew(val, (unsigned long) addr); else - writew(val, (unsigned long) addr); + *addr = val; } extern inline u16 scr_readw(const u16 *addr) { - if ((long) addr < 0) - return *addr; + if (__is_ioaddr((unsigned long) addr)) + return __raw_readw((unsigned long) addr); else - return readw((unsigned long) addr); + return *addr; } extern inline void scr_memsetw(u16 *s, u16 c, unsigned int count) { - if ((long)s < 0) - memsetw(s, c, count); - else + if (__is_ioaddr((unsigned long) s)) memsetw_io(s, c, count); + else + memsetw(s, c, count); } extern inline void scr_memcpyw_from(u16 *d, const u16 *s, unsigned int count) @@ -47,10 +47,12 @@ extern inline void scr_memcpyw_to(u16 *d, const u16 *s, unsigned int count) memcpy_toio(d, s, count); } +/* ??? These are currently only used for downloading character sets. As + such, they don't need memory barriers. Is this all they are intended + to be used for? */ +#define vga_readb readb +#define vga_writeb writeb -#define vga_readb readb -#define vga_writeb writeb - -#define VGA_MAP_MEM(x) (x) +#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0)) #endif |