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-rw-r--r--include/asm-mips/galileo-boards/evb64120A/cntmr.h42
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/core.h209
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/dma.h80
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/eeprom_param.h53
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/flashdrv.h81
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/gt64120A.h347
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/i2o.h61
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/memory.h57
-rw-r--r--include/asm-mips/galileo-boards/evb64120A/pci.h165
9 files changed, 1095 insertions, 0 deletions
diff --git a/include/asm-mips/galileo-boards/evb64120A/cntmr.h b/include/asm-mips/galileo-boards/evb64120A/cntmr.h
new file mode 100644
index 000000000..31f11c0a0
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/cntmr.h
@@ -0,0 +1,42 @@
+/* cntmr.h - Timer/Counter interface header file */
+
+/* Copyright - Galileo technology */
+
+#ifndef __INCtimerCounterDrvh
+#define __INCtimerCounterDrvh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define FIRST_CNTMR 0
+#define LAST_CNTMR 3
+
+#define CNTMR0_READ(pData)\
+ GT_REG_READ(CNTMR0, pData)
+
+#define CNTMR1_READ(pData)\
+ GT_REG_READ(CNTMR1, pData)
+
+#define CNTMR2_READ(pData)\
+ GT_REG_READ(CNTMR2, pData)
+
+#define CNTMR3_READ(pData)\
+ GT_REG_READ(CNTMR3, pData)
+
+/* typedefs */
+
+typedef enum counterTimer{CNTMR_0,CNTMR_1,CNTMR_2,CNTMR_3} CNTMR_NUM;
+typedef enum cntTmrOpModes{COUNTER, TIMER} CNT_TMR_OP_MODES;
+
+bool cntTmrLoad(unsigned int countNum, unsigned int value);
+bool cntTmrSetMode(CNTMR_NUM countNum, CNT_TMR_OP_MODES opMode);
+bool cntTmrEnable(CNTMR_NUM countNum);
+bool cntTmrStart (CNTMR_NUM countNum,unsigned int countValue,
+ CNT_TMR_OP_MODES opMode);
+unsigned int cntTmrDisable(CNTMR_NUM countNum);
+unsigned int cntTmrRead(CNTMR_NUM countNum);
+
+#endif /* __INCtimerCounterDrvh */
diff --git a/include/asm-mips/galileo-boards/evb64120A/core.h b/include/asm-mips/galileo-boards/evb64120A/core.h
new file mode 100644
index 000000000..283d7a116
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/core.h
@@ -0,0 +1,209 @@
+/* Core.h - Basic core logic functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This header file contains simple Read/Write macros for addressing
+the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
+space). */
+
+#ifndef __INCcoreh
+#define __INCcoreh
+
+/* includes */
+#include "gt64120A.h"
+
+/* defines */
+
+#define INTERNAL_REG_BASE_ADDR 0x14000000
+
+#define NO_BIT 0x00000000
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+#define _1K 0x00000400
+#define _2K 0x00000800
+#define _4K 0x00001000
+#define _8K 0x00002000
+#define _16K 0x00004000
+#define _32K 0x00008000
+#define _64K 0x00010000
+#define _128K 0x00020000
+#define _256K 0x00040000
+#define _512K 0x00080000
+
+#define _1M 0x00100000
+#define _2M 0x00200000
+#define _3M 0x00300000
+#define _4M 0x00400000
+#define _5M 0x00500000
+#define _6M 0x00600000
+#define _7M 0x00700000
+#define _8M 0x00800000
+#define _9M 0x00900000
+#define _10M 0x00a00000
+#define _11M 0x00b00000
+#define _12M 0x00c00000
+#define _13M 0x00d00000
+#define _14M 0x00e00000
+#define _15M 0x00f00000
+#define _16M 0x01000000
+
+typedef enum _bool{false,true} bool;
+
+/* Little to Big endian conversion macros */
+
+#ifdef LE /* Little Endian */
+#define SHORTSWAP(X) (X)
+#define WORDSWAP(X) (X)
+#define LONGSWAP(X) ((l64)(X))
+#else /* Big Endian */
+#define SHORTSWAP(X) ((X <<8 ) | (X >> 8))
+
+#define WORDSWAP(X) (((X)&0xff)<<24)+ \
+ (((X)&0xff00)<<8)+ \
+ (((X)&0xff0000)>>8)+ \
+ (((X)&0xff000000)>>24)
+
+#define LONGSWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
+ (((X)&0xff00ULL)<<40)+ \
+ (((X)&0xff0000ULL)<<24)+ \
+ (((X)&0xff000000ULL)<<8)+ \
+ (((X)&0xff00000000ULL)>>8)+ \
+ (((X)&0xff0000000000ULL)>>24)+ \
+ (((X)&0xff000000000000ULL)>>40)+ \
+ (((X)&0xff00000000000000ULL)>>56))
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+/* The two following defines are according to MIPS architecture. */
+#define NONE_CACHEABLE 0xa0000000
+#define MIPS_CACHEABLE 0x80000000
+
+/* Read/Write to/from GT`s internal registers */
+#define GT_REG_READ(offset, pData) \
+*pData = (*((unsigned int *)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
+ offset))); \
+*pData = WORDSWAP(*pData)
+
+#define GT_REG_WRITE(offset, data) \
+*((unsigned int *)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | offset)) = \
+ WORDSWAP(data)
+
+#define VIRTUAL_TO_PHY(y) ((unsigned int)y & (unsigned int)0x5fffffff)
+#define PHY_TO_VIRTUAL(y) (((unsigned int)y) | NONE_CACHEABLE)
+
+/* Write 32/16/8 bit Non-Cache-able */
+#define WRITE_CHAR(address, data) \
+ *((unsigned char *)(address | NONE_CACHEABLE)) = data
+#define WRITE_SHORT(address, data) \
+ *((unsigned short *)(address | NONE_CACHEABLE)) = \
+ (unsigned short)data
+#define WRITE_WORD(address, data) \
+ *((unsigned int *)(address | NONE_CACHEABLE)) = \
+ (unsigned int)data
+
+/* Write 32/16/8 bits Cacheable */
+#define WRITE_CHAR_CACHEABLE(address, data) \
+ *((unsigned char *)(address | MIPS_CACHEABLE )) = data
+
+#define WRITE_SHORT_CACHEABLE(address, data) \
+ *((unsigned short *)(address | MIPS_CACHEABLE )) = \
+ (unsigned short)data
+
+#define WRITE_WORD_CACHEABLE(address, data) \
+ *((unsigned int *)(address | MIPS_CACHEABLE )) = \
+ (unsigned int)data
+
+/* Read 32/16/8 bits NonCacheable - returns data in variable. */
+#define READ_CHAR(address,pData) \
+ *pData = *((unsigned char *)(address | NONE_CACHEABLE))
+
+#define READ_SHORT(address,pData) \
+ *pData = *((unsigned short *)(address | NONE_CACHEABLE))
+
+#define READ_WORD(address,pData) \
+ *pData = *((unsigned int *)(address | NONE_CACHEABLE))
+
+/* Read 32/16/8 bit NonCacheable - returns data direct. */
+#define READCHAR(address) \
+ *((unsigned char *)(address | NONE_CACHEABLE))
+
+#define READSHORT(address) \
+ *((unsigned short *)(address | NONE_CACHEABLE))
+
+#define READWORD(address) \
+ *((unsigned int *)(address | NONE_CACHEABLE))
+
+/* Read 32/16/8 bit Cacheable - returns data in variable. */
+#define READ_CHAR_CACHEABLE(address,pData) \
+ *pData = *((unsigned char *)(address | MIPS_CACHEABLE ))
+
+#define READ_SHORT_CACHEABLE(address,pData) \
+ *pData = *((unsigned short *)(address | MIPS_CACHEABLE ))
+
+#define READ_WORD_CACHEABLE(address,pData) \
+ *pData = *((unsigned int *)(address | MIPS_CACHEABLE ))
+
+/* Read 32/16/8 bit Cacheable - returns data direct. */
+#define READCHAR_CACHEABLE(address) \
+ *((unsigned char *)(address | MIPS_CACHEABLE ))
+
+#define READSHORT_CACHEABLE(address) \
+ *((unsigned short *)(address | MIPS_CACHEABLE ))
+
+#define READWORD_CACHEABLE(address) \
+ *((unsigned int *)(address | MIPS_CACHEABLE ))
+
+/* SET_REG_BITS(regOffset,bits) -
+ gets register offset and bits: a 32bit value. It set to logic '1' in the
+ internal register the bits which given as an input example:
+ SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+ '1' in register 0x840 while the other bits stays as is. */
+#define SET_REG_BITS(regOffset,bits) \
+ *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
+ regOffset) |= (unsigned int)WORDSWAP(bits)
+
+/* RESET_REG_BITS(regOffset,bits) -
+ gets register offset and bits: a 32bit value. It set to logic '0' in the
+ internal register the bits which given as an input example:
+ RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+ '0' in register 0x840 while the other bits stays as is. */
+#define RESET_REG_BITS(regOffset,bits) \
+ *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
+ regOffset) &= ~( (unsigned int)WORDSWAP(bits) )
+
+#endif /* __INCcoreh */
diff --git a/include/asm-mips/galileo-boards/evb64120A/dma.h b/include/asm-mips/galileo-boards/evb64120A/dma.h
new file mode 100644
index 000000000..21767bc9f
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/dma.h
@@ -0,0 +1,80 @@
+/* DMA.h - DMA functions and definitions*/
+
+/* Copyright Galileo Technology. */
+
+#ifndef __INCdmah
+#define __INCdmah
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define FIRST_DMA_ENGINE 0
+#define LAST_DMA_ENGINE 3
+
+#define FLY_BY BIT0
+#define RD_WR_FLY BIT1
+#define DECREMENT_SOURCE_ADDRESS BIT2
+#define HOLD_SOURCE_ADDRESS BIT3
+#define DECREMENT_DEST_ADDRESS BIT4
+#define HOLD_DEST_ADDRESS BIT5
+#define DTL_1BYTE BIT6 | BIT8
+#define DTL_2BYTES BIT7 | BIT8
+#define DTL_4BYTES BIT7
+#define DTL_8BYTES NO_BIT
+#define DTL_16BYTES BIT6
+#define DTL_32BYTES BIT6 | BIT7
+#define DTL_64BYTES BIT6 | BIT7 | BIT8
+#define NON_CHAIN_MOD BIT9
+#define INT_EVERY_NULL_POINTER BIT10
+#define BLOCK_TRANSFER_MODE BIT11
+#define CHANNEL_ENABLE BIT12
+#define FETCH_NEXT_RECORED BIT13
+#define DMA_ACTIVITY_STATUS BIT14
+#define ALIGN_TOWARD_DEST BIT15
+#define MASK_DMA_REQ BIT16
+#define ENABLE_DESCRIPTOR BIT17
+#define ENABLE_EOT BIT18
+#define ENABLE_EOT_INTERRUPT BIT19
+#define ABORT_DMA BIT20
+#define SOURCE_ADDR_IN_PCI0 BIT21
+#define SOURCE_ADDR_IN_PCI1 BIT22
+#define DEST_ADDR_IN_PCI0 BIT23
+#define DEST_ADDR_IN_PCI1 BIT24
+#define REC_ADDR_IN_PCI0 BIT25
+#define REC_ADDR_IN_PCI1 BIT26
+#define REQ_FROM_TIMER_COUNTER BIT28
+
+/* typedefs */
+
+typedef enum dmaEngine{DMA_ENG_0,DMA_ENG_1,DMA_ENG_2,DMA_ENG_3} DMA_ENGINE;
+
+/* priority definitions */
+typedef enum prioChan01{ROUND_ROBIN01,CH_1,CH_0} PRIO_CHAN_0_1;
+typedef enum prioChan23{ROUND_ROBIN23,CH_3,CH_2} PRIO_CHAN_2_3;
+typedef enum prioGroup{ROUND_ROBIN,CH_2_3,CH_0_1} PRIO_GROUP;
+typedef enum prioOpt{RETURN_BUS,KEEP_BUS} PRIO_OPT;
+
+typedef struct dmaRecored
+{
+ unsigned int ByteCnt;
+ unsigned int SrcAdd;
+ unsigned int DestAdd;
+ unsigned int NextRecPtr;
+} DMA_RECORED;
+
+typedef enum __dma_status{CHANNEL_BUSY,NO_SUCH_CHANNEL,DMA_OK,
+ GENERAL_ERROR} DMA_STATUS;
+
+DMA_STATUS dmaTransfer (DMA_ENGINE engine,unsigned int sourceAddr,
+ unsigned int destAddr,unsigned int numOfBytes,
+ unsigned int command,DMA_RECORED * nextRecoredPointer);
+bool dmaCommand (DMA_ENGINE channel,unsigned int command);
+bool isDmaChannelActive (DMA_ENGINE channel);
+
+bool changeDmaPriority(PRIO_CHAN_0_1 prio_01, PRIO_CHAN_2_3 prio_23,
+ PRIO_GROUP prioGrp, PRIO_OPT prioOpt);
+
+#endif /* __INCdmah */
diff --git a/include/asm-mips/galileo-boards/evb64120A/eeprom_param.h b/include/asm-mips/galileo-boards/evb64120A/eeprom_param.h
new file mode 100644
index 000000000..271fd8493
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/eeprom_param.h
@@ -0,0 +1,53 @@
+#ifndef EEPROM_PARAM_
+#define EEPROM_PARAM_
+#define SDRAM_REGS 0xbf000000
+
+unsigned int galileo_dl(void);
+void (*boot_addr)(int argc, char **argv, char **envp);
+
+#define NETWORK_BT_BIN 0
+#define FLASH_BT 1
+#define SERIAL_BT 2
+#define NETWORK_BT_SREC 3
+
+#define LINUX_OS 0
+#define OTHER_OS 1
+
+/********************************************************************
+ *eeprom_parameters -
+ *
+ *This structure holds the eeprom parameters (usually stored on flash
+ *memory)
+ *The structure is all stored in flash memory except memory_size which
+ *is probed each boot time for the real size of memory on the
+ *evaluation board.
+ *
+ *The structure also holds information that is not used by all
+ *evaluation board, such as the eth?_mac, which holds the MAC addresses
+ *of the built in ethernet ports in the EVB96100 for example, but is
+ *never used by EVB64120A.
+ *
+ *********************************************************************/
+
+struct eeprom_parameters {
+ unsigned int boot_source;
+ unsigned int operating_system;
+
+ /* network loader parametrs */
+ unsigned int host_ip;
+ unsigned int server_ip;
+ char bootimage[64];
+
+ /* Board parameters */
+ char eth0_mac[6];
+ char eth1_mac[6];
+ char eth2_mac[6];
+ char eth3_mac[6];
+
+ /* Command Line (usually needed for Linux) */
+ char os_command_line[256];
+ unsigned int entry_point;
+ unsigned memory_size;
+};
+
+#endif /* EEPROM_PARAM_ */
diff --git a/include/asm-mips/galileo-boards/evb64120A/flashdrv.h b/include/asm-mips/galileo-boards/evb64120A/flashdrv.h
new file mode 100644
index 000000000..f69251ec0
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/flashdrv.h
@@ -0,0 +1,81 @@
+/* flashdrv.h - FLASH memory interface header file */
+
+/* Copyright Galileo Technology. */
+
+#ifndef __INCflashdrvh
+#define __INCflashdrvh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+/* Supported Flash Manufactures */
+
+#define AMD_FLASH 0x01
+#define ST_FLASH 0x20
+#define INTEL_FLASH 0x89
+#define MICRON_FLASH 0x89
+
+/* Supported Flash Devices */
+
+/* AMD Devices */
+#define AM29F400BT 0x2223
+#define AM29F400BB 0x22AB
+#define AM29LV800BT 0x22DA
+#define AM29LV400BT 0x22B9
+#define AM29LV400BB 0x22BA
+#define AM29LV040B 0x4f
+/* ST Devices */
+#define M29W040 0xE3
+/* INTEL Devices - We have added I before the name defintion.*/
+#define I28F320J3A 0x16
+#define I28F640J3A 0x17
+#define I28F128J3A 0x18
+#define I28F320B3_B 0x8897
+#define I28F320B3_T 0x8896
+#define I28F160B3_B 0x8891
+#define I28F160B3_T 0x8890
+
+#define POINTER_TO_FLASH flashParametrs[0]
+#define FLASH_BASE_ADDRESS flashParametrs[1]
+#define FLASH_WIDTH flashParametrs[2] /* In Bytes */
+#define FLASH_MODE flashParametrs[3] /* In bits */
+#define MANUFACTOR_ID POINTER_TO_FLASH + 0
+#define VENDOR_ID POINTER_TO_FLASH + 1
+#define NUMBER_OF_SECTORS POINTER_TO_FLASH + 2
+#define FIRST_SECTOR_SIZE POINTER_TO_FLASH + 3
+#define NUM_OF_DEVICES FLASH_WIDTH / (FLASH_MODE / 8)
+
+/* typedefs */
+
+typedef enum _FlashMode {PURE8,X8 = 8,X16 = 16} FLASHmode;
+/* PURE8 - when using a flash device whice can be configurated only as
+ 8 bit device. */
+/* X8 - when using a flash device which is 16 bit wide but configured to
+ operate in 8 bit mode.*/
+/* X16 - when using a flash device which is 16 bit wide */
+
+bool flashErase(void);
+bool flashEraseSector(unsigned int sectorNumber);
+bool flashWriteWord(unsigned int offset,unsigned int data);
+bool flashWriteShort(unsigned int offset,unsigned short sdata);
+bool flashWriteChar(unsigned int offset,unsigned char cdata);
+void flashReset(void);
+unsigned int flashInWhichSector(unsigned int offset);
+unsigned int flashGetSectorSize(unsigned int sectorNumber);
+unsigned int flashInit(unsigned int baseAddress,unsigned int flashWidth,
+ FLASHmode FlashMode);
+unsigned int flashGetNumOfSectors(void);
+unsigned int flashGetSize(void);
+unsigned int flashGetSectorOffset(unsigned int sectorNum);
+unsigned int flashWriteBlock(unsigned int offset,unsigned int numOfByte,
+ unsigned char * blockAddress);
+unsigned int flashReadWord(unsigned int offset);
+unsigned char flashReadChar(unsigned int offset);
+unsigned short flashReadShort(unsigned int offset);
+unsigned int flashReadBlock(unsigned int offset,unsigned int numOfByte,
+ unsigned char * blockAddress);
+#endif /* __INCflashdrvh */
+
diff --git a/include/asm-mips/galileo-boards/evb64120A/gt64120A.h b/include/asm-mips/galileo-boards/evb64120A/gt64120A.h
new file mode 100644
index 000000000..075857dc2
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/gt64120A.h
@@ -0,0 +1,347 @@
+/* GT64120A.h - GT64120A Internal registers definition file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef _INCgt64120ARh
+#define _INCgt64120ARh
+
+#ifndef GT64120A
+#define GT64120A
+#endif
+
+/****************************************/
+/* CPU Configuration */
+/****************************************/
+
+#define CPU_INTERFACE_CONFIGURATION 0x000
+#define MULTI_GT_REGISTER 0x120
+
+/****************************************/
+/* Processor Address Space */
+/****************************************/
+
+#define SCS_1_0_LOW_DECODE_ADDRESS 0x008
+#define SCS_1_0_HIGH_DECODE_ADDRESS 0x010
+#define SCS_3_2_LOW_DECODE_ADDRESS 0x018
+#define SCS_3_2_HIGH_DECODE_ADDRESS 0x020
+#define CS_2_0_LOW_DECODE_ADDRESS 0x028
+#define CS_2_0_HIGH_DECODE_ADDRESS 0x030
+#define CS_3_BOOTCS_LOW_DECODE_ADDRESS 0x038
+#define CS_3_BOOTCS_HIGH_DECODE_ADDRESS 0x040
+#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
+#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
+#define INTERNAL_SPACE_DECODE 0x068
+#define CPU_BUS_ERROR_LOW_ADDRESS 0x070
+#define CPU_BUS_ERROR_HIGH_ADDRESS 0x078
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
+#define SCS_1_0_ADDRESS_REMAP 0x0d0
+#define SCS_3_2_ADDRESS_REMAP 0x0d8
+#define CS_2_0_ADDRESS_REMAP 0x0e0
+#define CS_3_BOOTCS_ADDRESS_REMAP 0x0e8
+#define PCI_0I_O_ADDRESS_REMAP 0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
+#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
+#define PCI_1I_O_ADDRESS_REMAP 0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
+#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
+
+/****************************************/
+/* SDRAM and Device Address Space */
+/****************************************/
+
+#define SCS_0_LOW_DECODE_ADDRESS 0x400
+#define SCS_0_HIGH_DECODE_ADDRESS 0x404
+#define SCS_1_LOW_DECODE_ADDRESS 0x408
+#define SCS_1_HIGH_DECODE_ADDRESS 0x40C
+#define SCS_2_LOW_DECODE_ADDRESS 0x410
+#define SCS_2_HIGH_DECODE_ADDRESS 0x414
+#define SCS_3_LOW_DECODE_ADDRESS 0x418
+#define SCS_3_HIGH_DECODE_ADDRESS 0x41C
+#define CS_0_LOW_DECODE_ADDRESS 0x420
+#define CS_0_HIGH_DECODE_ADDRESS 0x424
+#define CS_1_LOW_DECODE_ADDRESS 0x428
+#define CS_1_HIGH_DECODE_ADDRESS 0x42C
+#define CS_2_LOW_DECODE_ADDRESS 0x430
+#define CS_2_HIGH_DECODE_ADDRESS 0x434
+#define CS_3_LOW_DECODE_ADDRESS 0x438
+#define CS_3_HIGH_DECODE_ADDRESS 0x43C
+#define BOOTCS_LOW_DECODE_ADDRESS 0x440
+#define BOOTCS_HIGH_DECODE_ADDRESS 0x444
+#define ADDRESS_DECODE_ERROR 0x470
+#define ADDRESS_DECODE 0x47C
+
+/****************************************/
+/* SDRAM Configuration */
+/****************************************/
+
+#define SDRAM_CONFIGURATION 0x448
+#define SDRAM_OPERATION_MODE 0x474
+#define SDRAM_ADDRESS_DECODE 0x47C
+
+/****************************************/
+/* SDRAM ECC */
+/****************************************/
+
+#define ECC_UPPER_DATA 0x480
+#define ECC_LOWER_DATA 0x484
+#define ECC_FROM_MEM 0x488
+#define ECC_CALCULATED 0x48c
+#define ECC_ERROR_REPORT 0x490
+
+/****************************************/
+/* SDRAM Parameters */
+/****************************************/
+
+#define SDRAM_BANK0PARAMETERS 0x44C
+#define SDRAM_BANK1PARAMETERS 0x450
+#define SDRAM_BANK2PARAMETERS 0x454
+#define SDRAM_BANK3PARAMETERS 0x458
+
+/****************************************/
+/* Device Parameters */
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS 0x45C
+#define DEVICE_BANK1PARAMETERS 0x460
+#define DEVICE_BANK2PARAMETERS 0x464
+#define DEVICE_BANK3PARAMETERS 0x468
+#define DEVICE_BOOT_BANK_PARAMETERS 0x46C
+
+/****************************************/
+/* DMA Record */
+/****************************************/
+
+#define CHANNEL0_DMA_BYTE_COUNT 0x800
+#define CHANNEL1_DMA_BYTE_COUNT 0x804
+#define CHANNEL2_DMA_BYTE_COUNT 0x808
+#define CHANNEL3_DMA_BYTE_COUNT 0x80C
+#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
+#define CHANNEL0NEXT_RECORD_POINTER 0x830
+#define CHANNEL1NEXT_RECORD_POINTER 0x834
+#define CHANNEL2NEXT_RECORD_POINTER 0x838
+#define CHANNEL3NEXT_RECORD_POINTER 0x83C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
+
+/****************************************/
+/* DMA Channel Control */
+/****************************************/
+
+#define CHANNEL0CONTROL 0x840
+#define CHANNEL1CONTROL 0x844
+#define CHANNEL2CONTROL 0x848
+#define CHANNEL3CONTROL 0x84C
+
+/****************************************/
+/* DMA Arbiter */
+/****************************************/
+
+#define ARBITER_CONTROL 0x860
+
+/****************************************/
+/* Timer_Counter */
+/****************************************/
+
+#define TIMER_COUNTER0 0x850
+#define TIMER_COUNTER1 0x854
+#define TIMER_COUNTER2 0x858
+#define TIMER_COUNTER3 0x85C
+#define TIMER_COUNTER_CONTROL 0x864
+
+/****************************************/
+/* PCI Internal */
+/****************************************/
+
+#define PCI_0COMMAND 0xC00
+#define PCI_0TIMEOUT_RETRY 0xC04
+#define PCI_0SCS_1_0_BANK_SIZE 0xC08
+#define PCI_0SCS_3_2_BANK_SIZE 0xC0C
+#define PCI_0CS_2_0_BANK_SIZE 0xC10
+#define PCI_0CS_3_BOOTCS_BANK_SIZE 0xC14
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xC3C
+#define PCI_0PREFETCH_MAX_BURST_SIZE 0xc40
+#define PCI_0SCS_1_0_BASE_ADDRESS_REMAP 0xC48
+#define PCI_0SCS_3_2_BASE_ADDRESS_REMAP 0xC4C
+#define PCI_0CS_2_0_BASE_ADDRESS_REMAP 0xC50
+#define PCI_0CS_3_BOOTCS_ADDRESS_REMAP 0xC54
+#define PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP 0xC58
+#define PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP 0xC5C
+#define PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP 0xC64
+#define PCI_0CONFIGURATION_ADDRESS 0xCF8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xCFC
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xC34
+#define PCI_1COMMAND 0xc80
+#define PCI_1TIMEOUT_RETRY 0xc84
+#define PCI_1SCS_1_0_BANK_SIZE 0xc88
+#define PCI_1SCS_3_2_BANK_SIZE 0xc8c
+#define PCI_1CS_2_0_BANK_SIZE 0xc90
+#define PCI_1CS_3_BOOTCS_BANK_SIZE 0xc94
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
+#define PCI_1PREFETCH_MAX_BURST_SIZE 0xcc0
+#define PCI_1SCS_1_0_BASE_ADDRESS_REMAP 0xcc8
+#define PCI_1SCS_3_2_BASE_ADDRESS_REMAP 0xccc
+#define PCI_1CS_2_0_BASE_ADDRESS_REMAP 0xcd0
+#define PCI_1CS_3_BOOTCS_ADDRESS_REMAP 0xcd4
+#define PCI_1SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP 0xcd8
+#define PCI_1SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP 0xcdc
+#define PCI_1SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP 0x0c4
+#define PCI_1CONFIGURATION_ADDRESS 0xcf0
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcf4
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc30
+
+/****************************************/
+/* Interrupts */
+/****************************************/
+
+#define INTERRUPT_CAUSE_REGISTER 0xC18
+#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc98
+#define CPU_INTERRUPT_MASK_REGISTER 0xC1C
+#define CPU_HIGH_INTERRUPT_MASK_REGISTER 0xc9c
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER 0xC24
+#define PCI_0HIGH_INTERRUPT_CAUSE_MASK_REGISTER 0xca4
+#define PCI_0SERR0_MASK 0xC28
+#define PCI_1SERR0_MASK 0xca8
+#define CPU_SELECT_CAUSE_REGISTER 0xc70
+#define PCI_0INTERRUPT_SELECT_REGISTER 0xc71
+
+/****************************************/
+/* PCI Configuration */
+/****************************************/
+
+#define PCI_0DEVICE_AND_VENDOR_ID 0x000
+#define PCI_0STATUS_AND_COMMAND 0x004
+#define PCI_0CLASS_CODE_AND_REVISION_ID 0x008
+#define PCI_0BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
+#define PCI_0SCS_1_0_BASE_ADDRESS 0x010
+#define PCI_0SCS_3_2_BASE_ADDRESS 0x014
+#define PCI_0CS_2_0_BASE_ADDRESS 0x018
+#define PCI_0CS_3_BOOTCS_BASE_ADDRESS 0x01C
+#define PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
+#define PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
+#define PCI_0SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
+#define EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
+#define PCI_0INTERRUPT_PIN_AND_LINE 0x03C
+#define PCI_1DEVICE_AND_VENDOR_ID 0x080
+#define PCI_1STATUS_AND_COMMAND 0x084
+#define PCI_1CLASS_CODE_AND_REVISION_ID 0x088
+#define PCI_1BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x08c
+#define PCI_1SCS_1_0_BASE_ADDRESS 0x090
+#define PCI_1SCS_3_2_BASE_ADDRESS 0x094
+#define PCI_1CS_2_0_BASE_ADDRESS 0x098
+#define PCI_1CS_3_BOOTCS_BASE_ADDRESS 0x09c
+#define PCI_1INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x0a0
+#define PCI_1INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x0a4
+#define PCI_1SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x0ac
+#define PCI_1INTERRUPT_PIN_AND_LINE 0x0bc
+
+/****************************************/
+/* PCI Configuration, Function 1 */
+/****************************************/
+
+#define PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS 0x110
+#define PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS 0x114
+#define PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS 0x11C
+#define PCI_1SWAPPED_SCS_1_0_BASE_ADDRESS 0x190
+#define PCI_1SWAPPED_SCS_3_2_BASE_ADDRESS 0x194
+#define PCI_1SWAPPED_CS_3_BOOTCS_BASE_ADDRESS 0x19c
+
+/****************************************/
+/* I20 Support registers */
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0 0x010
+#define INBOUND_MESSAGE_REGISTER1 0x014
+#define OUTBOUND_MESSAGE_REGISTER0 0x018
+#define OUTBOUND_MESSAGE_REGISTER1 0x01C
+#define INBOUND_DOORBELL_REGISTER 0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER 0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER 0x028
+#define OUTBOUND_DOORBELL_REGISTER 0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER 0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER 0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER 0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER 0x044
+#define QUEUE_CONTROL_REGISTER 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER 0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER 0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER 0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER 0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER 0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER 0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER 0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER 0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER 0x07C
+
+
+/****************************************/
+/* I20 Support registers */
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0X1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0X1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0X1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0X1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0X1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0X1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0X1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0X1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0X1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0X1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0X1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0X1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0X1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0X1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C7C
+
+
+#endif /* __INCgt64120ARh */
diff --git a/include/asm-mips/galileo-boards/evb64120A/i2o.h b/include/asm-mips/galileo-boards/evb64120A/i2o.h
new file mode 100644
index 000000000..a42ecabfe
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/i2o.h
@@ -0,0 +1,61 @@
+/* i2o.h - Header file for the I2O`s interface */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCi2oh
+#define __INCi2oh
+
+/* includes */
+
+#include "core.h"
+
+/* typedefs */
+
+typedef enum _i2oMessageReg{MESSAGE_REG_0,MESSAGE_REG_1} I2O_MESSAGE_REG;
+typedef enum _cirQueSize{I20_16K = 0x1,I20_32K = 0x2,I20_64K = 0x4,\
+ I20_128K = 0x8,I20_256K = 0xc} CIRCULAR_QUEUE_SIZE;
+
+/* Message handle Functions */
+unsigned int getInBoundMassege(I2O_MESSAGE_REG messageRegNum);
+bool sendOutBoundMassege(I2O_MESSAGE_REG messageRegNum,unsigned int message);
+bool checkInBoundIntAndClear(I2O_MESSAGE_REG messageRegNum);
+bool outBoundMessageAcknowledge(I2O_MESSAGE_REG messageRegNum);
+bool maskInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum);
+bool enableInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum);
+bool maskOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum);
+bool enableOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum);
+
+/* Doorbell handle Functions */
+unsigned int readInBoundDoorBellInt(void);
+bool initiateOutBoundDoorBellInt(unsigned int interruptBits);
+bool clearInBoundDoorBellInt(unsigned int interruptBits);
+bool isInBoundDoorBellInterruptSet(void);
+bool isOutBoundDoorBellInterruptSet(void); /* For acknowledge */
+bool maskInBoundDoorBellInterrupt(void);
+bool enableInBoundDoorBellInterrupt(void);
+bool maskOutBoundDoorBellInterrupt(void);
+bool enableOutBoundDoorBellInterrupt(void);
+
+/* I2O - Circular Queues handle Functions */
+
+/* initialization */
+bool circularQueueEnable(CIRCULAR_QUEUE_SIZE cirQueSize,
+ unsigned int queueBaseAddr);
+
+/* Inbound Post Queue */
+unsigned int inBoundPostQueuePop(void);
+bool isInBoundPostQueueInterruptSet(void);
+bool clearInBoundPostQueueInterrupt(void);
+void maskInBoundPostQueueInterrupt(void);
+void enableInBoundPostQueueInterrupt(void);
+/* Outbound Post Queue */
+bool outBoundPostQueuePush(unsigned int data);
+bool isOutBoundPostQueueEmpty(void);
+/* Inbound Free Queue */
+bool inBoundFreeQueuePush(unsigned int data);
+bool isInBoundFreeQueueEmpty(void);
+/* Outbound Free Queue */
+unsigned int outBoundFreeQueuePop(void);
+
+#endif /* __INCi2oh */
+
diff --git a/include/asm-mips/galileo-boards/evb64120A/memory.h b/include/asm-mips/galileo-boards/evb64120A/memory.h
new file mode 100644
index 000000000..d6427ec6b
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/memory.h
@@ -0,0 +1,57 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY 0xffffffff
+#define PARITY_SUPPORT 0x40000000
+
+#define _8BIT 0x00000000
+#define _16BIT 0x00010000
+#define _32BIT 0x00020000
+#define _64BIT 0x00030000
+
+/* typedefs */
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __device{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+
+unsigned int getMemoryBankBaseAddress(MEMORY_BANK bank);
+unsigned int getDeviceBaseAddress(DEVICE device);
+unsigned int getMemoryBankSize(MEMORY_BANK bank);
+unsigned int getDeviceSize(DEVICE device);
+unsigned int getDeviceWidth(DEVICE device);
+
+bool mapMemoryBanks0and1(unsigned int bank0Base,unsigned int bank0Length,
+ unsigned int bank1Base,unsigned int bank1Length);
+bool mapMemoryBanks2and3(unsigned int bank2Base,unsigned int bank2Length,
+ unsigned int bank3Base,unsigned int bank3Length);
+bool mapDevices0_1and2MemorySpace(unsigned int device0Base,
+ unsigned int device0Length,
+ unsigned int device1Base,
+ unsigned int device1Length,
+ unsigned int device2Base,
+ unsigned int device2Length);
+bool mapDevices3andBootMemorySpace(unsigned int device3Base,
+ unsigned int device3Length,
+ unsigned int bootDeviceBase,
+ unsigned int bootDeviceLength);
+bool mapInternalRegistersMemorySpace(unsigned int internalRegBase);
+bool modifyDeviceParameters(DEVICE device,unsigned int TurnOff,
+ unsigned int AccToFirst,unsigned int AccToNext,
+ unsigned int ALEtoWr, unsigned int WrActive,
+ unsigned int WrHigh,unsigned int Width,
+ bool ParitySupport);
+
+bool remapAddress(unsigned int remapReg, unsigned int remapValue);
+#endif /* __INCmemoryh */
+
diff --git a/include/asm-mips/galileo-boards/evb64120A/pci.h b/include/asm-mips/galileo-boards/evb64120A/pci.h
new file mode 100644
index 000000000..7a0a8aecc
--- /dev/null
+++ b/include/asm-mips/galileo-boards/evb64120A/pci.h
@@ -0,0 +1,165 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include"core.h"
+
+/* defines */
+
+#define PCI0_MASTER_ENABLE(deviceNumber) pci0WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
+ pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI0_MASTER_DISABLE(deviceNumber) pci0WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
+ pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI1_MASTER_ENABLE(deviceNumber) pci1WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
+ pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI1_MASTER_DISABLE(deviceNumber) pci1WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
+ pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI0_MEMORY_ENABLE(deviceNumber) pci0WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
+ pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI1_MEMORY_ENABLE(deviceNumber) pci1WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
+ pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI0_IO_ENABLE(deviceNumber) pci0WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
+ pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI1_IO_ENABLE(deviceNumber) pci1WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
+ pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI0_SLAVE_ENABLE(deviceNumber) pci0WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
+ pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI1_SLAVE_ENABLE(deviceNumber) pci1WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
+ pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI0_DISABLE(deviceNumber) pci0WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
+ pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber))
+
+#define PCI1_DISABLE(deviceNumber) pci1WriteConfigReg( \
+ PCI_0STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
+ pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber))
+
+#define MASTER_ENABLE BIT2
+#define MEMORY_ENABLE BIT1
+#define I_O_ENABLE BIT0
+#define SELF 0
+/* Agent on the PCI bus may have up to 6 BARS. */
+#define BAR0 0x10
+#define BAR1 0x14
+#define BAR2 0x18
+#define BAR3 0x1c
+#define BAR4 0x20
+#define BAR5 0x24
+
+
+/* typedefs */
+
+typedef struct pciDevice
+{
+ char type[20];
+ unsigned int deviceNum;
+ unsigned int venID;
+ unsigned int deviceID;
+ unsigned int bar0Base;
+ unsigned int bar0Size;
+ unsigned int bar0Type;
+ unsigned int bar1Base;
+ unsigned int bar1Size;
+ unsigned int bar1Type;
+ unsigned int bar2Base;
+ unsigned int bar2Size;
+ unsigned int bar2Type;
+ unsigned int bar3Base;
+ unsigned int bar3Size;
+ unsigned int bar3Type;
+ unsigned int bar4Base;
+ unsigned int bar4Size;
+ unsigned int bar4Type;
+ unsigned int bar5Base;
+ unsigned int bar5Size;
+ unsigned int bar5Type;
+} PCI_DEVICE;
+
+void pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
+ unsigned int data);
+void pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
+ unsigned int data);
+void pci0ScanDevices(PCI_DEVICE *pci0Detect,unsigned int numberOfElment);
+void pci1ScanDevices(PCI_DEVICE *pci1Detect,unsigned int numberOfElment);
+unsigned int pci0ReadConfigReg (unsigned int regOffset,
+ unsigned int pciDevNum);
+unsigned int pci1ReadConfigReg (unsigned int regOffset,
+ unsigned int pciDevNum);
+
+/* Master`s memory space */
+
+void pci0MapIOspace(unsigned int pci0IoBase,unsigned int pci0IoLength);
+void pci0MapMemory0space(unsigned int pci0Mem0Base,
+ unsigned int pci0Mem0Length);
+void pci0MapMemory1space(unsigned int pci0Mem1Base,
+ unsigned int pci0Mem1Length);
+
+void pci1MapIOspace(unsigned int pci1IoBase,unsigned int pci1IoLength);
+void pci1MapMemory0space(unsigned int pci1Mem0Base,
+ unsigned int pci1Mem0Length);
+void pci1MapMemory1space(unsigned int pci1Mem1Base,
+ unsigned int pci1Mem1Length);
+
+unsigned int pci0GetIOspaceBase(void);
+unsigned int pci0GetIOspaceSize(void);
+unsigned int pci0GetMemory0Base(void);
+unsigned int pci0GetMemory0Size(void);
+unsigned int pci0GetMemory1Base(void);
+unsigned int pci0GetMemory1Size(void);
+
+unsigned int pci1GetIOspaceBase(void);
+unsigned int pci1GetIOspaceSize(void);
+unsigned int pci1GetMemory0Base(void);
+unsigned int pci1GetMemory0Size(void);
+unsigned int pci1GetMemory1Base(void);
+unsigned int pci1GetMemory1Size(void);
+
+/* Slave`s memory space */
+void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
+void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
+void pci0MapMemoryBanks0_1(unsigned int pci0Dram0_1Base,
+ unsigned int pci0Dram0_1Size);
+void pci0MapMemoryBanks2_3(unsigned int pci0Dram2_3Base,
+ unsigned int pci0Dram2_3Size);
+void pci0MapDevices0_1and2MemorySpace(unsigned int pci0Dev012Base,
+ unsigned int pci0Dev012Length);
+void pci0MapDevices3andBootMemorySpace(unsigned int pci0Dev3andBootBase,
+ unsigned int pci0Dev3andBootLength);
+
+void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
+void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
+void pci1MapMemoryBanks0_1(unsigned int pci1Dram0_1Base,
+ unsigned int pci1Dram0_1Size);
+void pci1MapMemoryBanks2_3(unsigned int pci1Dram2_3Base,
+ unsigned int pci1Dram2_3Size);
+void pci1MapDevices0_1and2MemorySpace(unsigned int pci1Dev012Base,
+ unsigned int pci1Dev012Length);
+void pci1MapDevices3andBootMemorySpace(unsigned int pci1Dev3andBootBase,
+ unsigned int pci1Dev3andBootLength);
+
+#endif /* __INCpcih */
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-20 07:05:38 +0000