diff options
Diffstat (limited to 'include/asm-mips/sgi')
| -rw-r--r-- | include/asm-mips/sgi/sgi.h | 42 | ||||
| -rw-r--r-- | include/asm-mips/sgi/sgihpc.h | 372 | ||||
| -rw-r--r-- | include/asm-mips/sgi/sgimc.h | 223 | ||||
| -rw-r--r-- | include/asm-mips/sgi/sgint23.h | 214 |
4 files changed, 851 insertions, 0 deletions
diff --git a/include/asm-mips/sgi/sgi.h b/include/asm-mips/sgi/sgi.h new file mode 100644 index 000000000..bafe60b57 --- /dev/null +++ b/include/asm-mips/sgi/sgi.h @@ -0,0 +1,42 @@ +/* $Id: sgi.h,v 1.1.1.1 1997/06/01 03:17:12 ralf Exp $ + * sgi.h: Definitions specific to SGI machines. + * + * Copyright (C) 1996 David S. Miller (dm@sgi.com) + */ +#ifndef _MIPS_SGI_H +#define _MIPS_SGI_H + +/* UP=UniProcessor MP=MultiProcessor(capable) */ +enum sgi_mach { + ip4, /* R2k UP */ + ip5, /* R2k MP */ + ip6, /* R3k UP */ + ip7, /* R3k MP */ + ip9, /* R3k UP */ + ip12, /* R3kA UP, Indigo */ + ip15, /* R3kA MP */ + ip17, /* R4K UP */ + ip19, /* R4K MP */ + ip20, /* R4K UP, Indigo */ + ip21, /* TFP MP */ + ip22, /* R4x00 UP, Indigo2 */ + ip25, /* R10k MP */ + ip26, /* TFP UP, Indigo2 */ + ip28, /* R10k UP, Indigo2 */ + ip30, + ip32, +}; + +extern enum sgi_mach sgimach; +extern void sgi_sysinit(void); + +/* Many I/O space registers are byte sized and are contained within + * one byte per word, specifically the MSB, this macro helps out. + */ +#ifdef __MIPSEL__ +#define SGI_MSB(regaddr) (regaddr) +#else +#define SGI_MSB(regaddr) ((regaddr) | 0x3) +#endif + +#endif /* !(_MIPS_SGI_H) */ diff --git a/include/asm-mips/sgi/sgihpc.h b/include/asm-mips/sgi/sgihpc.h new file mode 100644 index 000000000..4bf59643e --- /dev/null +++ b/include/asm-mips/sgi/sgihpc.h @@ -0,0 +1,372 @@ +/* $Id: sgihpc.h,v 1.7 1999/08/11 20:26:49 andrewb Exp $ + * + * sgihpc.h: Various HPC I/O controller defines. The HPC is basically + * the approximate functional equivalent of the Sun SYSIO + * on SGI INDY machines. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1998 Ralf Baechle (ralf@gnu.org) + */ +#ifndef _MIPS_SGIHPC_H +#define _MIPS_SGIHPC_H + +#include <asm/page.h> + +extern int sgi_has_ioc2; /* to know if we have older ioc1 or ioc2. */ +extern int sgi_guiness; /* GUINESS or FULLHOUSE machine. */ +extern int sgi_boardid; /* Board revision. */ + +/* An HPC dma descriptor. */ +struct hpc_dma_desc { + unsigned long pbuf; /* physical address of data buffer */ + unsigned long cntinfo; /* counter and info bits */ +#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */ +#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */ +#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */ +#define HPCDMA_EORP 0x40000000 /* end of packet for rx */ +#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */ +#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */ +#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */ +#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */ +#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */ +#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */ + + unsigned long pnext; /* paddr of next hpc_dma_desc if any */ +}; + +typedef volatile unsigned long hpcreg; + +/* HPC1 stuff. */ + +/* HPC3 stuff. */ + +/* The set of regs for each HPC3 pbus dma channel. */ +struct hpc3_pbus_dmacregs { + hpcreg pbdma_bptr; /* pbus dma channel buffer ptr */ + hpcreg pbdma_dptr; /* pbus dma channel desc ptr */ + char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ + hpcreg pbdma_ctrl; /* pbus dma channel control reg */ +#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */ +#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */ +#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */ +#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */ +#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */ +#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */ +#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */ +#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */ +#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */ + + char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */ +}; + +/* The HPC3 scsi registers, this does not include external ones. */ +struct hpc3_scsiregs { + hpcreg cbptr; /* current dma buffer ptr, diagnostic use only */ + hpcreg ndptr; /* next dma descriptor ptr */ + char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ + hpcreg bcd; /* byte count info */ +#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */ +#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */ +#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */ + + hpcreg ctrl; /* control register */ +#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ +#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */ +#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */ +#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */ +#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */ +#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */ +#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */ +#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */ + + hpcreg gfptr; /* current GIO fifo ptr */ + hpcreg dfptr; /* current device fifo ptr */ + hpcreg dconfig; /* DMA configuration register */ +#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */ +#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */ +#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */ +#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */ +#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */ +#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */ +#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */ +#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */ +#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */ +#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */ + + hpcreg pconfig; /* PIO configuration register */ +#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */ +#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */ +#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */ +#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */ +#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */ +#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */ +#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */ +#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */ + + char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */ +}; + +/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */ +struct hpc3_ethregs { + /* Receiver registers. */ + hpcreg rx_cbptr; /* current dma buffer ptr, diagnostic use only */ + hpcreg rx_ndptr; /* next dma descriptor ptr */ + char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ + hpcreg rx_bcd; /* byte count info */ +#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */ +#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */ +#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */ + + hpcreg rx_ctrl; /* control register */ +#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */ +#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */ +#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */ +#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */ +#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */ +#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */ +#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */ + + hpcreg rx_gfptr; /* current GIO fifo ptr */ + hpcreg rx_dfptr; /* current device fifo ptr */ + hpcreg _unused2; /* padding */ + hpcreg rx_reset; /* reset register */ +#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ +#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ +#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ + + hpcreg rx_dconfig; /* DMA configuration register */ +#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ +#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ +#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ +#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ +#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ +#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ +#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ +#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ + + hpcreg rx_pconfig; /* PIO configuration register */ +#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ +#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ +#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ +#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ + + char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */ + + /* Transmitter registers. */ + hpcreg tx_cbptr; /* current dma buffer ptr, diagnostic use only */ + hpcreg tx_ndptr; /* next dma descriptor ptr */ + char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */ + hpcreg tx_bcd; /* byte count info */ +#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */ +#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */ +#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ +#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ +#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ + + hpcreg tx_ctrl; /* control register */ +#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */ +#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */ +#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */ +#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */ +#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */ +#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */ + + hpcreg tx_gfptr; /* current GIO fifo ptr */ + hpcreg tx_dfptr; /* current device fifo ptr */ + char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */ +}; + +struct hpc3_regs { + /* First regs for the PBUS 8 dma channels. */ + struct hpc3_pbus_dmacregs pbdma[8]; + + /* Now the HPC scsi registers, we get two scsi reg sets. */ + struct hpc3_scsiregs scsi_chan0, scsi_chan1; + + /* The SEEQ hpc3 ethernet dma/control registers. */ + struct hpc3_ethregs ethregs; + + /* Here are where the hpc3 fifo's can be directly accessed + * via PIO accesses. Under normal operation we never stick + * our grubby paws in here so it's just padding. + */ + char _unused1[PAGE_SIZE * 24]; + + /* HPC3 irq status regs. Due to a peculiar bug you need to + * look at two different register addresses to get at all of + * the status bits. The first reg can only reliably report + * bits 4:0 of the status, and the second reg can only + * reliably report bits 9:5 of the hpc3 irq status. I told + * you it was a peculiar bug. ;-) + */ + hpcreg istat0; /* Irq status, only bits <4:0> reliable. */ +#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */ +#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */ +#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */ + + hpcreg gio64_misc; /* GIO64 misc control bits. */ +#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ +#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ + + hpcreg eeprom_data; /* EEPROM data reg. */ +#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ +#define HPC3_EEPROM_CSEL 0x02 /* Chip select */ +#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ +#define HPC3_EEPROM_DATO 0x08 /* Data out */ +#define HPC3_EEPROM_DATI 0x10 /* Data in */ + + hpcreg istat1; /* Irq status, only bits <9:5> reliable. */ + hpcreg gio64_estat; /* GIO64 error interrupt status reg. */ +#define HPC3_GIOESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ +#define HPC3_GIOESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ +#define HPC3_GIOESTAT_PIDMSK 0x3f700 /* DMA channel parity identifier */ + + /* Now direct PIO per-HPC3 peripheral access to external regs. */ + char _unused2[0x13fec]; /* Trust me... */ + hpcreg scsi0_ext[256]; /* SCSI channel 0 external regs */ + char _unused3[0x07c00]; /* Trust me... */ + hpcreg scsi1_ext[256]; /* SCSI channel 1 external regs */ + char _unused4[0x07c00]; /* It'll only hurt a little... */ + + /* Did DaveM forget the ethernet external regs? + * Anyhow, they're not here and we need some padding instead. + */ + char _unused5[0x04000]; /* It'll hurt a lot if you leave this out */ + + /* Per-peripheral device external registers and dma/pio control. */ + hpcreg pbus_extregs[16][256]; /* 2nd indice indexes controller */ + hpcreg pbus_dmacfgs[8][128]; /* 2nd indice indexes controller */ +#define HPC3_PIODCFG_D3R 0x00000001 /* Cycles to spend in D3 for reads */ +#define HPC3_PIODCFG_D4R 0x0000001e /* Cycles to spend in D4 for reads */ +#define HPC3_PIODCFG_D5R 0x000001e0 /* Cycles to spend in D5 for reads */ +#define HPC3_PIODCFG_D3W 0x00000200 /* Cycles to spend in D3 for writes */ +#define HPC3_PIODCFG_D4W 0x00003c00 /* Cycles to spend in D4 for writes */ +#define HPC3_PIODCFG_D5W 0x0003c000 /* Cycles to spend in D5 for writes */ +#define HPC3_PIODCFG_HWORD 0x00040000 /* Enable 16-bit dma access mode */ +#define HPC3_PIODCFG_EHI 0x00080000 /* Places halfwords on high 16 bits of bus */ +#define HPC3_PIODCFG_RTIME 0x00200000 /* Make this device real time on GIO bus */ +#define HPC3_PIODCFG_BURST 0x07c00000 /* 5 bit burst count for DMA device */ +#define HPC3_PIODCFG_DRQLV 0x08000000 /* Use live pbus_dreq unsynchronized signal */ + + hpcreg pbus_piocfgs[64][10]; /* 2nd indice indexes controller */ +#define HPC3_PIOPCFG_RP2 0x00001 /* Cycles to spend in P2 state for reads */ +#define HPC3_PIOPCFG_RP3 0x0001e /* Cycles to spend in P3 state for reads */ +#define HPC3_PIOPCFG_RP4 0x001e0 /* Cycles to spend in P4 state for reads */ +#define HPC3_PIOPCFG_WP2 0x00200 /* Cycles to spend in P2 state for writes */ +#define HPC3_PIOPCFG_WP3 0x03c00 /* Cycles to spend in P3 state for writes */ +#define HPC3_PIOPCFG_WP4 0x3c000 /* Cycles to spend in P4 state for writes */ +#define HPC3_PIOPCFG_HW 0x40000 /* Enable 16-bit PIO accesses */ +#define HPC3_PIOPCFG_EHI 0x80000 /* Place even address bits in bits <15:8> */ + + /* PBUS PROM control regs. */ + hpcreg pbus_promwe; /* PROM write enable register */ +#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ + + char _unused6[0x800 - sizeof(hpcreg)]; + hpcreg pbus_promswap; /* Chip select swap reg */ +#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */ + + char _unused7[0x800 - sizeof(hpcreg)]; + hpcreg pbus_gout; /* PROM general purpose output reg */ +#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */ + + char _unused8[0x1000 - sizeof(hpcreg)]; + hpcreg pbus_promram[16384]; /* 64k of PROM battery backed ram */ +}; + +/* It is possible to have two HPC3's within the address space on + * one machine, though only having one is more likely on an INDY. + * Controller 0 lives at physical address 0x1fb80000 and the controller + * 1 if present lives at address 0x1fb00000. + */ +extern struct hpc3_regs *hpc3c0, *hpc3c1; +#define HPC3_CHIP0_PBASE 0x1fb80000 /* physical */ +#define HPC3_CHIP1_PBASE 0x1fb00000 /* physical */ + +/* Control and misc status information, these live in pbus channel 6. */ +struct hpc3_miscregs { + hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask; + hpcreg ptimer1, ptimer2, ptimer3, ptimer4; + hpcreg _unused1[2]; + hpcreg ser1cmd, ser1data; + hpcreg ser0cmd, ser0data; + hpcreg kbdmouse0, kbdmouse1; + hpcreg gcsel, genctrl, panel; + hpcreg _unused2; + hpcreg sysid; + hpcreg _unused3; + hpcreg read, _unused4; + hpcreg dselect; +#define HPC3_DSELECT_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ +#define HPC3_DSELECT_ISDNB 0x01 /* enable isdn B */ +#define HPC3_DSELECT_ISDNA 0x02 /* enable isdn A */ +#define HPC3_DSELECT_LPR 0x04 /* use parallel DMA */ +#define HPC3_DSELECT_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ +#define HPC3_DSELECT_SCLKEXT 0x20 /* use external serial clock */ + + hpcreg _unused5; + hpcreg write1; +#define HPC3_WRITE1_PRESET 0x01 /* 0=LPR_RESET, 1=NORMAL */ +#define HPC3_WRITE1_KMRESET 0x02 /* 0=KBDMOUSE_RESET, 1=NORMAL */ +#define HPC3_WRITE1_ERESET 0x04 /* 0=EISA_RESET, 1=NORMAL */ +#define HPC3_WRITE1_GRESET 0x08 /* 0=MAGIC_GIO_RESET, 1=NORMAL */ +#define HPC3_WRITE1_LC0OFF 0x10 /* turn led off (guiness=red, else green) */ +#define HPC3_WRITE1_LC1OFF 0x20 /* turn led off (guiness=green, else amber) */ + + hpcreg _unused6; + hpcreg write2; +#define HPC3_WRITE2_NTHRESH 0x01 /* use 4.5db threshhold */ +#define HPC3_WRITE2_TPSPEED 0x02 /* use 100ohm TP speed */ +#define HPC3_WRITE2_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ +#define HPC3_WRITE2_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ +#define HPC3_WRITE2_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ +#define HPC3_WRITE2_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ +#define HPC3_WRITE2_MLO 0x40 /* 1=4.75V 0=+5V */ +#define HPC3_WRITE2_MHI 0x80 /* 1=5.25V 0=+5V */ +}; +extern struct hpc3_miscregs *hpc3mregs; +#define HPC3_MREGS_PBASE 0x1fbd9800 /* physical */ + +/* We need software copies of these because they are write only. */ +extern unsigned long sgi_hpc_write1, sgi_hpc_write2; + +struct hpc_keyb { +#ifdef __MIPSEB__ + unsigned char _unused0[3]; + volatile unsigned char data; + unsigned char _unused1[3]; + volatile unsigned char command; +#else + volatile unsigned char data; + unsigned char _unused0[3]; + volatile unsigned char command; + unsigned char _unused1[3]; +#endif +}; + +/* Indy RTC */ + +/* The layout of registers for the INDY Dallas 1286 clock chipset. */ +struct indy_clock { + volatile unsigned int hsec; + volatile unsigned int sec; + volatile unsigned int min; + volatile unsigned int malarm; + volatile unsigned int hr; + volatile unsigned int halarm; + volatile unsigned int day; + volatile unsigned int dalarm; + volatile unsigned int date; + volatile unsigned int month; + volatile unsigned int year; + volatile unsigned int cmd; + volatile unsigned int whsec; + volatile unsigned int wsec; + volatile unsigned int _unused0[50]; +}; + +#define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000)) + +extern void sgihpc_init(void); + +#endif /* !(_MIPS_SGIHPC_H) */ diff --git a/include/asm-mips/sgi/sgimc.h b/include/asm-mips/sgi/sgimc.h new file mode 100644 index 000000000..808f562de --- /dev/null +++ b/include/asm-mips/sgi/sgimc.h @@ -0,0 +1,223 @@ +/* $Id: sgimc.h,v 1.1.1.1 1997/06/01 03:17:13 ralf Exp $ + * sgimc.h: Definitions for memory controller hardware found on + * SGI IP20, IP22, IP26, and IP28 machines. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ + +#ifndef _MIPS_SGIMC_H +#define _MIPS_SGIMC_H + +struct sgimc_misc_ctrl { + unsigned long _unused1; + volatile unsigned long cpuctrl0; /* CPU control register 0, readwrite */ +#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */ +#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ +#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ +#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */ +#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */ +#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */ +#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */ +#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */ +#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */ +#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */ +#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ +#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ +#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ +#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ +#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ +#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ +#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ +#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ +#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ + + unsigned long _unused2; + volatile unsigned long cpuctrl1; /* CPU control register 1, readwrite */ +#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ +#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ +#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ +#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ +#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ +#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ +#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ + + unsigned long _unused3; + volatile unsigned long watchdogt; /* Watchdog reg rdonly, write clears */ + + unsigned long _unused4; + volatile unsigned long systemid; /* MC system ID register, readonly */ +#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ +#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ + + unsigned long _unused5[3]; + volatile unsigned long divider; /* Divider reg for RPSS */ + + unsigned long _unused6; + volatile unsigned char eeprom; /* EEPROM byte reg for r4k */ +#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ +#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ +#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ +#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */ +#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ + + unsigned char _unused7[3]; + unsigned long _unused8[3]; + volatile unsigned short rcntpre; /* Preload refresh counter */ + + unsigned short _unused9; + unsigned long _unused9a; + volatile unsigned short rcounter; /* Readonly refresh counter */ + + unsigned short _unused10; + unsigned long _unused11[13]; + volatile unsigned long gioparm; /* Parameter word for GIO64 */ +#define SGIMC_GIOPARM_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ +#define SGIMC_GIOPARM_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ +#define SGIMC_GIOPARM_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ +#define SGIMC_GIOPARM_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */ +#define SGIMC_GIOPARM_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */ +#define SGIMC_GIOPARM_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */ +#define SGIMC_GIOPARM_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ +#define SGIMC_GIOPARM_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ +#define SGIMC_GIOPARM_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ +#define SGIMC_GIOPARM_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ +#define SGIMC_GIOPARM_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ +#define SGIMC_GIOPARM_MASTERGFX 0x00000800 /* GFX can act as a bus master */ +#define SGIMC_GIOPARM_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ +#define SGIMC_GIOPARM_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ +#define SGIMC_GIOPARM_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ +#define SGIMC_GIOPARM_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ + + unsigned long _unused13; + volatile unsigned short cputp; /* CPU bus arb time period */ + + unsigned short _unused14; + unsigned long _unused15[3]; + volatile unsigned short lbursttp; /* Time period for long bursts */ + + unsigned short _unused16; + unsigned long _unused17[9]; + volatile unsigned long mconfig0; /* Memory config register zero */ + unsigned long _unused18; + volatile unsigned long mconfig1; /* Memory config register one */ + + /* These defines apply to both mconfig registers above. */ +#define SGIMC_MCONFIG_FOURMB 0x00000000 /* Physical ram = 4megs */ +#define SGIMC_MCONFIG_EIGHTMB 0x00000100 /* Physical ram = 8megs */ +#define SGIMC_MCONFIG_SXTEENMB 0x00000300 /* Physical ram = 16megs */ +#define SGIMC_MCONFIG_TTWOMB 0x00000700 /* Physical ram = 32megs */ +#define SGIMC_MCONFIG_SFOURMB 0x00000f00 /* Physical ram = 64megs */ +#define SGIMC_MCONFIG_OTEIGHTMB 0x00001f00 /* Physical ram = 128megs */ +#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ + + unsigned long _unused19; + volatile unsigned long cmacc; /* Mem access config for CPU */ + unsigned long _unused20; + volatile unsigned long gmacc; /* Mem access config for GIO */ + + /* This define applies to both cmacc and gmacc registers above. */ +#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ + + /* Error address/status regs from GIO and CPU perspectives. */ + unsigned long _unused21; + volatile unsigned long cerr; /* Error address reg for CPU */ + unsigned long _unused22; + volatile unsigned long cstat; /* Status reg for CPU */ + unsigned long _unused23; + volatile unsigned long gerr; /* Error address reg for GIO */ + unsigned long _unused24; + volatile unsigned long gstat; /* Status reg for GIO */ + + /* Special hard bus locking registers. */ + unsigned long _unused25; + volatile unsigned char syssembit; /* Uni-bit system semaphore */ + unsigned char _unused26[3]; + unsigned long _unused27; + volatile unsigned char mlock; /* Global GIO memory access lock */ + unsigned char _unused28[3]; + unsigned long _unused29; + volatile unsigned char elock; /* Locks EISA from GIO accesses */ + + /* GIO dma control registers. */ + unsigned char _unused30[3]; + unsigned long _unused31[14]; + volatile unsigned long gio_dma_trans;/* DMA mask to translation GIO addrs */ + unsigned long _unused32; + volatile unsigned long gio_dma_sbits;/* DMA GIO addr substitution bits */ + unsigned long _unused33; + volatile unsigned long dma_intr_cause; /* DMA IRQ cause indicator bits */ + unsigned long _unused34; + volatile unsigned long dma_ctrl; /* Main DMA control reg */ + + /* DMA TLB entry 0 */ + unsigned long _unused35; + volatile unsigned long dtlb_hi0; + unsigned long _unused36; + volatile unsigned long dtlb_lo0; + + /* DMA TLB entry 1 */ + unsigned long _unused37; + volatile unsigned long dtlb_hi1; + unsigned long _unused38; + volatile unsigned long dtlb_lo1; + + /* DMA TLB entry 2 */ + unsigned long _unused39; + volatile unsigned long dtlb_hi2; + unsigned long _unused40; + volatile unsigned long dtlb_lo2; + + /* DMA TLB entry 3 */ + unsigned long _unused41; + volatile unsigned long dtlb_hi3; + unsigned long _unused42; + volatile unsigned long dtlb_lo3; +}; + +/* MC misc control registers live at physical 0x1fa00000. */ +extern struct sgimc_misc_ctrl *mcmisc_regs; +extern unsigned long *rpsscounter; /* Chirps at 100ns */ + +struct sgimc_dma_ctrl { + unsigned long _unused1; + volatile unsigned long maddronly; /* Address DMA goes at */ + unsigned long _unused2; + volatile unsigned long maddrpdeflts; /* Same as above, plus set defaults */ + unsigned long _unused3; + volatile unsigned long dmasz; /* DMA count */ + unsigned long _unused4; + volatile unsigned long ssize; /* DMA stride size */ + unsigned long _unused5; + volatile unsigned long gmaddronly; /* Set GIO DMA but do not start trans */ + unsigned long _unused6; + volatile unsigned long dmaddnpgo; /* Set GIO DMA addr + start transfer */ + unsigned long _unused7; + volatile unsigned long dmamode; /* DMA mode config bit settings */ + unsigned long _unused8; + volatile unsigned long dmacount; /* Zoom and byte count for DMA */ + unsigned long _unused9; + volatile unsigned long dmastart; /* Pedal to the metal. */ + unsigned long _unused10; + volatile unsigned long dmarunning; /* DMA op is in progress */ + unsigned long _unused11; + + /* Set dma addr, defaults, and kick it */ + volatile unsigned long maddr_defl_go; /* go go go! -lm */ +}; + +/* MC controller dma regs live at physical 0x1fa02000. */ +extern struct sgimc_dma_ctrl *dmactrlregs; + +/* Base location of the two ram banks found in IP2[0268] machines. */ +#define SGIMC_SEG0_BADDR 0x08000000 +#define SGIMC_SEG1_BADDR 0x20000000 + +/* Maximum size of the above banks are per machine. */ +extern unsigned long sgimc_seg0_size, sgimc_seg1_size; +#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */ +#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */ +#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */ + +extern void sgimc_init(void); + +#endif /* !(_MIPS_SGIMC_H) */ diff --git a/include/asm-mips/sgi/sgint23.h b/include/asm-mips/sgi/sgint23.h new file mode 100644 index 000000000..de98be6bc --- /dev/null +++ b/include/asm-mips/sgi/sgint23.h @@ -0,0 +1,214 @@ +/* $Id: sgint23.h,v 1.5 1999/10/09 00:01:43 ralf Exp $ + * + * sgint23.h: Defines for the SGI INT2 and INT3 chipsets. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - INT2 corrections + */ +#ifndef _ASM_SGINT23_H +#define _ASM_SGINT23_H + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an SGI machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define SGINT_LOCAL0 0 /* INDY has 8 local0 irq levels */ +#define SGINT_LOCAL1 8 /* INDY has 8 local1 irq levels */ +#define SGINT_LOCAL2 16 /* INDY has 8 local2 vectored irq levels */ +#define SGINT_LOCAL3 24 /* INDY has 8 local3 vectored irq levels */ +#define SGINT_GIO 32 /* INDY has 9 GIO irq levels */ +#define SGINT_HPCDMA 41 /* INDY has 11 HPCDMA irq _sources_ */ +#define SGINT_END 52 /* End of 'spaces' */ + +/* Individual interrupt definitions for the INDY and Indigo2 + */ + +#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ +#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ +#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ + +#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ + +#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ +#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ +#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ + +/* Individual interrupt definitions for the INDY and Indigo2 + */ + +#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ +#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ +#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ + +#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ + +#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ +#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ +#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ + +/* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */ +#define SGI_INT2_BASE 0x1fbd9000 /* physical */ +#define SGI_INT3_BASE 0x1fbd9880 /* physical */ + +struct sgi_ioc_ints { +#ifdef __MIPSEB__ + unsigned char _unused0[3]; + volatile unsigned char istat0; /* Interrupt status zero */ +#else + volatile unsigned char istat0; /* Interrupt status zero */ + unsigned char _unused0[3]; +#endif +#define ISTAT0_FFULL 0x01 +#define ISTAT0_SCSI0 0x02 +#define ISTAT0_SCSI1 0x04 +#define ISTAT0_ENET 0x08 +#define ISTAT0_GFXDMA 0x10 +#define ISTAT0_LPR 0x20 +#define ISTAT0_HPC2 0x40 +#define ISTAT0_LIO2 0x80 + +#ifdef __MIPSEB__ + unsigned char _unused1[3]; + volatile unsigned char imask0; /* Interrupt mask zero */ + unsigned char _unused2[3]; + volatile unsigned char istat1; /* Interrupt status one */ +#else + volatile unsigned char imask0; /* Interrupt mask zero */ + unsigned char _unused1[3]; + volatile unsigned char istat1; /* Interrupt status one */ + unsigned char _unused2[3]; +#endif +#define ISTAT1_ISDNI 0x01 +#define ISTAT1_PWR 0x02 +#define ISTAT1_ISDNH 0x04 +#define ISTAT1_LIO3 0x08 +#define ISTAT1_HPC3 0x10 +#define ISTAT1_AFAIL 0x20 +#define ISTAT1_VIDEO 0x40 +#define ISTAT1_GIO2 0x80 + +#ifdef __MIPSEB__ + unsigned char _unused3[3]; + volatile unsigned char imask1; /* Interrupt mask one */ + unsigned char _unused4[3]; + volatile unsigned char vmeistat; /* VME interrupt status */ + unsigned char _unused5[3]; + volatile unsigned char cmeimask0; /* VME interrupt mask zero */ + unsigned char _unused6[3]; + volatile unsigned char cmeimask1; /* VME interrupt mask one */ + unsigned char _unused7[3]; + volatile unsigned char cmepol; /* VME polarity */ +#else + volatile unsigned char imask1; /* Interrupt mask one */ + unsigned char _unused3[3]; + volatile unsigned char vmeistat; /* VME interrupt status */ + unsigned char _unused4[3]; + volatile unsigned char cmeimask0; /* VME interrupt mask zero */ + unsigned char _unused5[3]; + volatile unsigned char cmeimask1; /* VME interrupt mask one */ + unsigned char _unused6[3]; + volatile unsigned char cmepol; /* VME polarity */ + unsigned char _unused7[3]; +#endif +}; + +struct sgi_ioc_timers { +#ifdef __MIPSEB__ + unsigned char _unused0[3]; + volatile unsigned char tcnt0; /* counter 0 */ + unsigned char _unused1[3]; + volatile unsigned char tcnt1; /* counter 1 */ + unsigned char _unused2[3]; + volatile unsigned char tcnt2; /* counter 2 */ + unsigned char _unused3[3]; + volatile unsigned char tcword; /* control word */ +#else + volatile unsigned char tcnt0; /* counter 0 */ + unsigned char _unused0[3]; + volatile unsigned char tcnt1; /* counter 1 */ + unsigned char _unused1[3]; + volatile unsigned char tcnt2; /* counter 2 */ + unsigned char _unused2[3]; + volatile unsigned char tcword; /* control word */ + unsigned char _unused3[3]; +#endif +}; + +/* Timer control word bits. */ +#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ +#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ +#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ +#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ +#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ +#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ +#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ +#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ +#define SGINT_TCWORD_CMASK 0x30 /* Command mask */ +#define SGINT_TCWORD_CLAT 0x00 /* Latch command */ +#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ +#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ +#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ +#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ +#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ +#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ +#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ + +#define SGINT_TCSAMP_COUNTER 10255 + +/* FIXME: What does this really look like? It was written to have + * 17 registers, but there are only 16 in my Indigo2. + * I guessed at which one to remove... - andrewb + */ +struct sgi_int2_regs { + struct sgi_ioc_ints ints; + + volatile unsigned long ledbits; /* LED control bits */ +#define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */ +#define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */ +#define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */ +#define INT2_LED_CHEAPER 0x08 /* 0=cheapernet 1=ethernet */ +#define INT2_LED_POWEROFF 0x10 /* Power-off request, active high */ + +#ifdef __MIPSEB__ + unsigned char _unused0[3]; + volatile unsigned char tclear; /* Timer clear strobe address */ +#else + volatile unsigned char tclear; /* Timer clear strobe address */ + unsigned char _unused0[3]; +#endif +#define INT2_TCLEAR_T0CLR 0x1 /* Clear timer0 IRQ */ +#define INT2_TCLEAR_T1CLR 0x2 /* Clear timer1 IRQ */ +/* I am guesing there are only two unused registers here + * but I could be wrong... - andrewb + */ +/* unsigned long _unused[3]; */ + unsigned long _unused[2]; + struct sgi_ioc_timers timers; +}; + +struct sgi_int3_regs { + struct sgi_ioc_ints ints; + +#ifdef __MIPSEB__ + unsigned char _unused0[3]; + volatile unsigned char tclear; /* Timer clear strobe address */ +#else + volatile unsigned char tclear; /* Timer clear strobe address */ + unsigned char _unused0[3]; +#endif + volatile unsigned long estatus; /* Error status reg */ + unsigned long _unused1[2]; + struct sgi_ioc_timers timers; +}; + +extern struct sgi_int2_regs *sgi_i2regs; +extern struct sgi_int3_regs *sgi_i3regs; +extern struct sgi_ioc_ints *ioc_icontrol; +extern struct sgi_ioc_timers *ioc_timers; +extern volatile unsigned char *ioc_tclear; + +extern void sgint_init(void); +extern void indy_timer_init(void); + +#endif /* !(_ASM_SGINT23_H) */ |