diff options
Diffstat (limited to 'include/asm-mips64/bcache.h')
| -rw-r--r-- | include/asm-mips64/bcache.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/include/asm-mips64/bcache.h b/include/asm-mips64/bcache.h index e3507bb04..0df4edb7d 100644 --- a/include/asm-mips64/bcache.h +++ b/include/asm-mips64/bcache.h @@ -5,10 +5,17 @@ * for more details. * * Copyright (c) 1997, 1999 by Ralf Baechle + * Copyright (c) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_BCACHE_H #define _ASM_BCACHE_H +#include <linux/config.h> + +#ifdef CONFIG_BOARD_SCACHE + +/* Some R4000 / R4400 / R4600 / R5000 machines may have chipset implemented + caches. On machines with other CPUs the CPU does the cache thing itself. */ struct bcache_ops { void (*bc_enable)(void); void (*bc_disable)(void); @@ -21,4 +28,35 @@ extern void sni_pcimt_sc_init(void); extern struct bcache_ops *bcops; +void inline bc_enable(void) +{ + bcops->bc_enable(); +} + +void inline bc_disable(void) +{ + bcops->bc_disble(); +} + +void bc_wback_inv(unsigned long page, unsigned long size) +{ + bcops->bc_wback_inv(page, size); +} + +void bc_inv(unsigned long page, unsigned long size) +{ + bcops->bc_inv(page, size); +} + +#else /* !defined(CONFIG_BOARD_SCACHE) */ + +/* Not R4000 / R4400 / R4600 / R5000. */ + +#define bc_enable() do { } while (0) +#define bc_disable() do { } while (0) +#define bc_wback_inv(page, size) do { } while (0) +#define bc_inv(page, size) do { } while (0) + +#endif /* !defined(CONFIG_BOARD_SCACHE) */ + #endif /* _ASM_BCACHE_H */ |