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-rw-r--r--include/asm-mips64/mipsregs.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips64/mipsregs.h b/include/asm-mips64/mipsregs.h
index 7a9f12cc8..b0bfb829f 100644
--- a/include/asm-mips64/mipsregs.h
+++ b/include/asm-mips64/mipsregs.h
@@ -246,7 +246,7 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
#define CAUSEF_BD (1 << 31)
/*
- * Bits in the coprozessor 0 config register.
+ * Bits in the coprocessor 0 config register.
*/
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
@@ -265,7 +265,7 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
* R10000 performance counter definitions.
*
* FIXME: The R10000 performance counter opens a nice way to implement CPU
- * time accounting with a precission of one cycle. I don't have
+ * time accounting with a precision of one cycle. I don't have
* R10000 silicon but just a manual, so ...
*/